4 * \brief GMAC (Ethernet MAC) driver for SAM.
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6 * Copyright (c) 2013 Atmel Corporation. All rights reserved.
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12 * Redistribution and use in source and binary forms, with or without
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13 * modification, are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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18 * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 * this list of conditions and the following disclaimer in the documentation
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20 * and/or other materials provided with the distribution.
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22 * 3. The name of Atmel may not be used to endorse or promote products derived
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23 * from this software without specific prior written permission.
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25 * 4. This software may only be redistributed and used in connection with an
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26 * Atmel microcontroller product.
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28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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38 * POSSIBILITY OF SUCH DAMAGE.
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44 /* Standard includes. */
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50 /* FreeRTOS includes. */
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51 #include "FreeRTOS.h"
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54 #include "FreeRTOSIPConfig.h"
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56 #include "compiler.h"
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57 #include "instance/gmac.h"
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58 #include "ethernet_phy.h"
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69 #define ARRAY_SIZE(x) (int)( sizeof(x) / sizeof(x)[0] )
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72 * \defgroup gmac_group Ethernet Media Access Controller
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74 * See \ref gmac_quickstart.
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76 * Driver for the GMAC (Ethernet Media Access Controller).
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77 * This file contains basic functions for the GMAC, with support for all modes, settings
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80 * \section dependencies Dependencies
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81 * This driver does not depend on other modules.
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86 /** TX descriptor lists */
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88 static gmac_tx_descriptor_t gs_tx_desc[ GMAC_TX_BUFFERS ];
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89 #if( GMAC_USES_TX_CALLBACK != 0 )
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90 /** TX callback lists */
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91 static gmac_dev_tx_cb_t gs_tx_callback[ GMAC_TX_BUFFERS ];
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93 /** RX descriptors lists */
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95 static gmac_rx_descriptor_t gs_rx_desc[ GMAC_RX_BUFFERS ];
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97 #if( ipconfigZERO_COPY_TX_DRIVER == 0 )
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98 /** Send Buffer. Section 3.6 of AMBA 2.0 spec states that burst should not cross the
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99 * 1K Boundaries. Receive buffer manager write operations are burst of 2 words => 3 lsb bits
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100 * of the address shall be set to 0.
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102 COMPILER_ALIGNED(8)
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103 static uint8_t gs_uc_tx_buffer[ GMAC_TX_BUFFERS * GMAC_TX_UNITSIZE ];
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104 #endif /* ipconfigZERO_COPY_TX_DRIVER */
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106 /** Receive Buffer */
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107 COMPILER_ALIGNED(8)
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108 static uint8_t gs_uc_rx_buffer[ GMAC_RX_BUFFERS * GMAC_RX_UNITSIZE ];
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111 * GMAC device memory management struct.
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113 typedef struct gmac_dev_mem {
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114 /* Pointer to allocated buffer for RX. The address should be 8-byte aligned
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115 and the size should be GMAC_RX_UNITSIZE * wRxSize. */
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116 uint8_t *p_rx_buffer;
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117 /* Pointer to allocated RX descriptor list. */
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118 gmac_rx_descriptor_t *p_rx_dscr;
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119 /* RX size, in number of registered units (RX descriptors). */
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120 /* Increased size from 16- to 32-bits, because it's more efficient */
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121 uint32_t us_rx_size;
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122 /* Pointer to allocated buffer for TX. The address should be 8-byte aligned
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123 and the size should be GMAC_TX_UNITSIZE * wTxSize. */
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124 uint8_t *p_tx_buffer;
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125 /* Pointer to allocated TX descriptor list. */
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126 gmac_tx_descriptor_t *p_tx_dscr;
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127 /* TX size, in number of registered units (TX descriptors). */
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128 uint32_t us_tx_size;
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131 /** Return count in buffer */
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132 #define CIRC_CNT( head, tail, size ) ( ( ( head ) - ( tail ) ) % ( size ) )
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135 * Return space available, from 0 to size-1.
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136 * Always leave one free char as a completely full buffer that has (head == tail),
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137 * which is the same as empty.
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139 #define CIRC_SPACE( head, tail, size ) CIRC_CNT( ( tail ), ( ( head ) + 1 ), ( size ) )
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141 /** Circular buffer is empty ? */
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142 #define CIRC_EMPTY( head, tail ) ( head == tail )
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143 /** Clear circular buffer */
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144 #define CIRC_CLEAR( head, tail ) do { ( head ) = 0; ( tail ) = 0; } while( 0 )
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146 /** Increment head or tail */
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147 static __inline void circ_inc32( int32_t *lHeadOrTail, uint32_t ulSize )
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149 ( *lHeadOrTail ) ++;
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150 if( ( *lHeadOrTail ) >= ( int32_t )ulSize )
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152 ( *lHeadOrTail ) = 0;
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157 * \brief Wait PHY operation to be completed.
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159 * \param p_gmac HW controller address.
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160 * \param ul_retry The retry times, 0 to wait forever until completeness.
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162 * Return GMAC_OK if the operation is completed successfully.
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164 static uint8_t gmac_wait_phy(Gmac* p_gmac, const uint32_t ul_retry)
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166 volatile uint32_t ul_retry_count = 0;
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167 const uint32_t xPHYPollDelay = pdMS_TO_TICKS( 1ul );
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169 while (!gmac_is_phy_idle(p_gmac)) {
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170 if (ul_retry == 0) {
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176 if (ul_retry_count >= ul_retry) {
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177 return GMAC_TIMEOUT;
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180 /* Block the task to allow other tasks to execute while the PHY
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181 is not connected. */
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182 vTaskDelay( xPHYPollDelay );
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188 * \brief Disable transfer, reset registers and descriptor lists.
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190 * \param p_dev Pointer to GMAC driver instance.
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193 static void gmac_reset_tx_mem(gmac_device_t* p_dev)
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195 Gmac *p_hw = p_dev->p_hw;
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196 uint8_t *p_tx_buff = p_dev->p_tx_buffer;
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197 gmac_tx_descriptor_t *p_td = p_dev->p_tx_dscr;
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200 uint32_t ul_address;
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203 gmac_enable_transmit(p_hw, 0);
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205 /* Set up the TX descriptors */
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206 CIRC_CLEAR(p_dev->l_tx_head, p_dev->l_tx_tail);
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207 for( ul_index = 0; ul_index < p_dev->ul_tx_list_size; ul_index++ )
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209 #if( ipconfigZERO_COPY_TX_DRIVER != 0 )
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211 ul_address = (uint32_t) 0u;
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215 ul_address = (uint32_t) (&(p_tx_buff[ul_index * GMAC_TX_UNITSIZE]));
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217 #endif /* ipconfigZERO_COPY_TX_DRIVER */
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218 p_td[ul_index].addr = ul_address;
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219 p_td[ul_index].status.val = GMAC_TXD_USED;
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221 p_td[p_dev->ul_tx_list_size - 1].status.val =
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222 GMAC_TXD_USED | GMAC_TXD_WRAP;
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224 /* Set transmit buffer queue */
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225 gmac_set_tx_queue(p_hw, (uint32_t) p_td);
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229 * \brief Disable receiver, reset registers and descriptor list.
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231 * \param p_drv Pointer to GMAC Driver instance.
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233 static void gmac_reset_rx_mem(gmac_device_t* p_dev)
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235 Gmac *p_hw = p_dev->p_hw;
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236 uint8_t *p_rx_buff = p_dev->p_rx_buffer;
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237 gmac_rx_descriptor_t *pRd = p_dev->p_rx_dscr;
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240 uint32_t ul_address;
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243 gmac_enable_receive(p_hw, 0);
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245 /* Set up the RX descriptors */
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246 p_dev->ul_rx_idx = 0;
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247 for( ul_index = 0; ul_index < p_dev->ul_rx_list_size; ul_index++ )
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249 ul_address = (uint32_t) (&(p_rx_buff[ul_index * GMAC_RX_UNITSIZE]));
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250 pRd[ul_index].addr.val = ul_address & GMAC_RXD_ADDR_MASK;
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251 pRd[ul_index].status.val = 0;
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253 pRd[p_dev->ul_rx_list_size - 1].addr.val |= GMAC_RXD_WRAP;
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255 /* Set receive buffer queue */
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256 gmac_set_rx_queue(p_hw, (uint32_t) pRd);
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261 * \brief Initialize the allocated buffer lists for GMAC driver to transfer data.
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262 * Must be invoked after gmac_dev_init() but before RX/TX starts.
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264 * \note If input address is not 8-byte aligned, the address is automatically
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265 * adjusted and the list size is reduced by one.
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267 * \param p_gmac Pointer to GMAC instance.
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268 * \param p_gmac_dev Pointer to GMAC device instance.
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269 * \param p_dev_mm Pointer to the GMAC memory management control block.
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270 * \param p_tx_cb Pointer to allocated TX callback list.
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272 * \return GMAC_OK or GMAC_PARAM.
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274 static uint8_t gmac_init_mem(Gmac* p_gmac, gmac_device_t* p_gmac_dev,
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275 gmac_dev_mem_t* p_dev_mm
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276 #if( GMAC_USES_TX_CALLBACK != 0 )
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277 , gmac_dev_tx_cb_t* p_tx_cb
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281 if (p_dev_mm->us_rx_size <= 1 || p_dev_mm->us_tx_size <= 1
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282 #if( GMAC_USES_TX_CALLBACK != 0 )
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289 /* Assign RX buffers */
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290 if (((uint32_t) p_dev_mm->p_rx_buffer & 0x7)
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291 || ((uint32_t) p_dev_mm->p_rx_dscr & 0x7)) {
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292 p_dev_mm->us_rx_size--;
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294 p_gmac_dev->p_rx_buffer =
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295 (uint8_t *) ((uint32_t) p_dev_mm->p_rx_buffer & 0xFFFFFFF8);
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296 p_gmac_dev->p_rx_dscr =
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297 (gmac_rx_descriptor_t *) ((uint32_t) p_dev_mm->p_rx_dscr
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299 p_gmac_dev->ul_rx_list_size = p_dev_mm->us_rx_size;
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301 /* Assign TX buffers */
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302 if (((uint32_t) p_dev_mm->p_tx_buffer & 0x7)
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303 || ((uint32_t) p_dev_mm->p_tx_dscr & 0x7)) {
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304 p_dev_mm->us_tx_size--;
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306 p_gmac_dev->p_tx_buffer =
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307 (uint8_t *) ((uint32_t) p_dev_mm->p_tx_buffer & 0xFFFFFFF8);
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308 p_gmac_dev->p_tx_dscr =
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309 (gmac_tx_descriptor_t *) ((uint32_t) p_dev_mm->p_tx_dscr
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311 p_gmac_dev->ul_tx_list_size = p_dev_mm->us_tx_size;
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312 #if( GMAC_USES_TX_CALLBACK != 0 )
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313 p_gmac_dev->func_tx_cb_list = p_tx_cb;
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315 /* Reset TX & RX */
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316 gmac_reset_rx_mem(p_gmac_dev);
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317 gmac_reset_tx_mem(p_gmac_dev);
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319 /* Enable Rx and Tx, plus the statistics register */
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320 gmac_enable_transmit(p_gmac, true);
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321 gmac_enable_receive(p_gmac, true);
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322 gmac_enable_statistics_write(p_gmac, true);
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324 /* Set up the interrupts for transmission and errors */
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325 gmac_enable_interrupt(p_gmac,
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326 GMAC_IER_RXUBR | /* Enable receive used bit read interrupt. */
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327 GMAC_IER_TUR | /* Enable transmit underrun interrupt. */
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328 GMAC_IER_RLEX | /* Enable retry limit exceeded interrupt. */
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329 GMAC_IER_TFC | /* Enable transmit buffers exhausted in mid-frame interrupt. */
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330 GMAC_IER_TCOMP | /* Enable transmit complete interrupt. */
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331 GMAC_IER_ROVR | /* Enable receive overrun interrupt. */
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332 GMAC_IER_HRESP | /* Enable Hresp not OK interrupt. */
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333 GMAC_IER_PFNZ | /* Enable pause frame received interrupt. */
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334 GMAC_IER_PTZ); /* Enable pause time zero interrupt. */
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340 * \brief Read the PHY register.
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342 * \param p_gmac Pointer to the GMAC instance.
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343 * \param uc_phy_address PHY address.
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344 * \param uc_address Register address.
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345 * \param p_value Pointer to a 32-bit location to store read data.
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347 * \Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.
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349 uint8_t gmac_phy_read(Gmac* p_gmac, uint8_t uc_phy_address, uint8_t uc_address,
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352 gmac_maintain_phy(p_gmac, uc_phy_address, uc_address, 1, 0);
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354 if (gmac_wait_phy(p_gmac, MAC_PHY_RETRY_MAX) == GMAC_TIMEOUT) {
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355 return GMAC_TIMEOUT;
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357 *p_value = gmac_get_phy_data(p_gmac);
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362 * \brief Write the PHY register.
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364 * \param p_gmac Pointer to the GMAC instance.
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365 * \param uc_phy_address PHY Address.
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366 * \param uc_address Register Address.
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367 * \param ul_value Data to write, actually 16-bit data.
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369 * \Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.
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371 uint8_t gmac_phy_write(Gmac* p_gmac, uint8_t uc_phy_address,
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372 uint8_t uc_address, uint32_t ul_value)
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374 gmac_maintain_phy(p_gmac, uc_phy_address, uc_address, 0, ul_value);
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376 if (gmac_wait_phy(p_gmac, MAC_PHY_RETRY_MAX) == GMAC_TIMEOUT) {
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377 return GMAC_TIMEOUT;
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383 * \brief Initialize the GMAC driver.
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385 * \param p_gmac Pointer to the GMAC instance.
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386 * \param p_gmac_dev Pointer to the GMAC device instance.
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387 * \param p_opt GMAC configure options.
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389 void gmac_dev_init(Gmac* p_gmac, gmac_device_t* p_gmac_dev,
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390 gmac_options_t* p_opt)
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392 gmac_dev_mem_t gmac_dev_mm;
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394 /* Disable TX & RX and more */
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395 gmac_network_control(p_gmac, 0);
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396 gmac_disable_interrupt(p_gmac, ~0u);
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399 gmac_clear_statistics(p_gmac);
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401 /* Clear all status bits in the receive status register. */
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402 gmac_clear_rx_status(p_gmac, GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA);
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404 /* Clear all status bits in the transmit status register */
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405 gmac_clear_tx_status(p_gmac, GMAC_TSR_UBR | GMAC_TSR_COL | GMAC_TSR_RLE
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406 | GMAC_TSR_TFC | GMAC_TSR_TXCOMP | GMAC_TSR_UND);
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408 /* Clear interrupts */
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409 gmac_get_interrupt_status(p_gmac);
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410 #if !defined(ETHERNET_CONF_DATA_OFFSET)
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411 /* Receive Buffer Offset
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412 * Indicates the number of bytes by which the received data
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413 * is offset from the start of the receive buffer
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414 * which can be handy for alignment reasons */
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415 /* Note: FreeRTOS+TCP wants to have this offset set to 2 bytes */
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416 #error ETHERNET_CONF_DATA_OFFSET not defined, assuming 0
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418 /* Enable the copy of data into the buffers
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419 ignore broadcasts, and not copy FCS. */
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421 gmac_set_configure(p_gmac,
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422 ( gmac_get_configure(p_gmac) & ~GMAC_NCFGR_RXBUFO_Msk ) |
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423 GMAC_NCFGR_RFCS | /* Remove FCS, frame check sequence (last 4 bytes) */
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424 GMAC_NCFGR_PEN | /* Pause Enable */
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425 GMAC_NCFGR_RXBUFO( ETHERNET_CONF_DATA_OFFSET ) |
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429 * GMAC_DCFGR_TXCOEN: (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable.
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430 * Note: tha SAM4E does have RX checksum offloading
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431 * but TX checksum offloading has NOT been implemented.
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432 * http://community.atmel.com/forum/sam4e-gmac-transmit-checksum-offload-enablesolved
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435 gmac_set_dma(p_gmac,
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436 gmac_get_dma(p_gmac) | GMAC_DCFGR_TXCOEN );
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438 gmac_enable_copy_all(p_gmac, p_opt->uc_copy_all_frame);
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439 gmac_disable_broadcast(p_gmac, p_opt->uc_no_boardcast);
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441 /* Fill in GMAC device memory management */
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442 gmac_dev_mm.p_rx_buffer = gs_uc_rx_buffer;
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443 gmac_dev_mm.p_rx_dscr = gs_rx_desc;
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444 gmac_dev_mm.us_rx_size = GMAC_RX_BUFFERS;
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446 #if( ipconfigZERO_COPY_TX_DRIVER != 0 )
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448 gmac_dev_mm.p_tx_buffer = NULL;
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452 gmac_dev_mm.p_tx_buffer = gs_uc_tx_buffer;
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455 gmac_dev_mm.p_tx_dscr = gs_tx_desc;
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456 gmac_dev_mm.us_tx_size = GMAC_TX_BUFFERS;
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458 gmac_init_mem(p_gmac, p_gmac_dev, &gmac_dev_mm
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459 #if( GMAC_USES_TX_CALLBACK != 0 )
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464 gmac_set_address(p_gmac, 0, p_opt->uc_mac_addr);
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468 * \brief Frames can be read from the GMAC in multiple sections.
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470 * Returns > 0 if a complete frame is available
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471 * It also it cleans up incomplete older frames
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474 static uint32_t gmac_dev_poll(gmac_device_t* p_gmac_dev)
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476 uint32_t ulReturn = 0;
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477 int32_t ulIndex = p_gmac_dev->ul_rx_idx;
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478 gmac_rx_descriptor_t *pxHead = &p_gmac_dev->p_rx_dscr[ulIndex];
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480 /* Discard any incomplete frames */
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481 while ((pxHead->addr.val & GMAC_RXD_OWNERSHIP) &&
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482 (pxHead->status.val & GMAC_RXD_SOF) == 0) {
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483 pxHead->addr.val &= ~(GMAC_RXD_OWNERSHIP);
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484 circ_inc32 (&ulIndex, p_gmac_dev->ul_rx_list_size);
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485 pxHead = &p_gmac_dev->p_rx_dscr[ulIndex];
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486 p_gmac_dev->ul_rx_idx = ulIndex;
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487 #if( GMAC_STATS != 0 )
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489 gmacStats.incompCount++;
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494 while ((pxHead->addr.val & GMAC_RXD_OWNERSHIP) != 0) {
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495 if ((pxHead->status.val & GMAC_RXD_EOF) != 0) {
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496 /* Here a complete frame has been seen with SOF and EOF */
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497 ulReturn = pxHead->status.bm.len;
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500 circ_inc32 (&ulIndex, p_gmac_dev->ul_rx_list_size);
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501 pxHead = &p_gmac_dev->p_rx_dscr[ulIndex];
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502 if ((pxHead->addr.val & GMAC_RXD_OWNERSHIP) == 0) {
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503 /* CPU is not the owner (yet) */
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506 if ((pxHead->status.val & GMAC_RXD_SOF) != 0) {
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507 /* Strange, we found a new Start Of Frame
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508 * discard previous segments */
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509 int32_t ulPrev = p_gmac_dev->ul_rx_idx;
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510 pxHead = &p_gmac_dev->p_rx_dscr[ulPrev];
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512 pxHead->addr.val &= ~(GMAC_RXD_OWNERSHIP);
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513 circ_inc32 (&ulPrev, p_gmac_dev->ul_rx_list_size);
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514 pxHead = &p_gmac_dev->p_rx_dscr[ulPrev];
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515 #if( GMAC_STATS != 0 )
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517 gmacStats.truncCount++;
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520 } while (ulPrev != ulIndex);
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521 p_gmac_dev->ul_rx_idx = ulIndex;
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528 * \brief Frames can be read from the GMAC in multiple sections.
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529 * Read ul_frame_size bytes from the GMAC receive buffers to pcTo.
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530 * p_rcv_size is the size of the entire frame. Generally gmac_read
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531 * will be repeatedly called until the sum of all the ul_frame_size equals
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532 * the value of p_rcv_size.
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534 * \param p_gmac_dev Pointer to the GMAC device instance.
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535 * \param p_frame Address of the frame buffer.
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536 * \param ul_frame_size Length of the frame.
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537 * \param p_rcv_size Received frame size.
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539 * \return GMAC_OK if receiving frame successfully, otherwise failed.
\r
541 uint32_t gmac_dev_read(gmac_device_t* p_gmac_dev, uint8_t* p_frame,
\r
542 uint32_t ul_frame_size, uint32_t* p_rcv_size)
\r
544 int32_t nextIdx; /* A copy of the Rx-index 'ul_rx_idx' */
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545 int32_t bytesLeft = gmac_dev_poll (p_gmac_dev);
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546 gmac_rx_descriptor_t *pxHead;
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548 if (bytesLeft == 0 )
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550 return GMAC_RX_NULL;
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553 /* gmac_dev_poll has confirmed that there is a complete frame at
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554 * the current position 'ul_rx_idx'
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556 nextIdx = p_gmac_dev->ul_rx_idx;
\r
558 /* Read +2 bytes because buffers are aligned at -2 bytes */
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559 bytesLeft = min( bytesLeft + 2, ( int32_t )ul_frame_size );
\r
561 /* The frame will be copied in 1 or 2 memcpy's */
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562 if( ( p_frame != NULL ) && ( bytesLeft != 0 ) )
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564 const uint8_t *source;
\r
568 source = p_gmac_dev->p_rx_buffer + nextIdx * GMAC_RX_UNITSIZE;
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570 toCopy = ( p_gmac_dev->ul_rx_list_size - nextIdx ) * GMAC_RX_UNITSIZE;
\r
575 memcpy (p_frame, source, toCopy);
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580 memcpy (p_frame + toCopy, (void*)p_gmac_dev->p_rx_buffer, left);
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586 pxHead = &p_gmac_dev->p_rx_dscr[nextIdx];
\r
587 pxHead->addr.val &= ~(GMAC_RXD_OWNERSHIP);
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588 circ_inc32 (&nextIdx, p_gmac_dev->ul_rx_list_size);
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589 } while ((pxHead->status.val & GMAC_RXD_EOF) == 0);
\r
591 p_gmac_dev->ul_rx_idx = nextIdx;
\r
593 *p_rcv_size = bytesLeft;
\r
599 extern void vGMACGenerateChecksum( uint8_t *apBuffer );
\r
602 * \brief Send ulLength bytes from pcFrom. This copies the buffer to one of the
\r
603 * GMAC Tx buffers, and then indicates to the GMAC that the buffer is ready.
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604 * If lEndOfFrame is true then the data being copied is the end of the frame
\r
605 * and the frame can be transmitted.
\r
607 * \param p_gmac_dev Pointer to the GMAC device instance.
\r
608 * \param p_buffer Pointer to the data buffer.
\r
609 * \param ul_size Length of the frame.
\r
610 * \param func_tx_cb Transmit callback function.
\r
612 * \return Length sent.
\r
614 uint32_t gmac_dev_write(gmac_device_t* p_gmac_dev, void *p_buffer,
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615 uint32_t ul_size, gmac_dev_tx_cb_t func_tx_cb)
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618 volatile gmac_tx_descriptor_t *p_tx_td;
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619 #if( GMAC_USES_TX_CALLBACK != 0 )
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620 volatile gmac_dev_tx_cb_t *p_func_tx_cb;
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623 Gmac *p_hw = p_gmac_dev->p_hw;
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625 #if( GMAC_USES_TX_CALLBACK == 0 )
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626 ( void )func_tx_cb;
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629 /* Check parameter */
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630 if (ul_size > GMAC_TX_UNITSIZE) {
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634 /* Pointers to the current transmit descriptor */
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635 p_tx_td = &p_gmac_dev->p_tx_dscr[p_gmac_dev->l_tx_head];
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637 /* If no free TxTd, buffer can't be sent, schedule the wakeup callback */
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638 // if (CIRC_SPACE(p_gmac_dev->l_tx_head, p_gmac_dev->l_tx_tail,
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639 // p_gmac_dev->ul_tx_list_size) == 0)
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641 if ((p_tx_td->status.val & GMAC_TXD_USED) == 0)
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642 return GMAC_TX_BUSY;
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644 #if( GMAC_USES_TX_CALLBACK != 0 )
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645 /* Pointers to the current Tx callback */
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646 p_func_tx_cb = &p_gmac_dev->func_tx_cb_list[p_gmac_dev->l_tx_head];
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649 /* Set up/copy data to transmission buffer */
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650 if (p_buffer && ul_size) {
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651 /* Driver manages the ring buffer */
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652 /* Calculating the checksum here is faster than calculating it from the GMAC buffer
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653 * because withing p_buffer, it is well aligned */
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654 #if( ipconfigZERO_COPY_TX_DRIVER != 0 )
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657 p_tx_td->addr = ( uint32_t ) p_buffer;
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661 /* Or memcopy... */
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662 memcpy((void *)p_tx_td->addr, p_buffer, ul_size);
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664 #endif /* ipconfigZERO_COPY_TX_DRIVER */
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665 vGMACGenerateChecksum( ( uint8_t * ) p_tx_td->addr );
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668 #if( GMAC_USES_TX_CALLBACK != 0 )
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670 *p_func_tx_cb = func_tx_cb;
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673 /* Update transmit descriptor status */
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675 /* The buffer size defined is the length of ethernet frame,
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676 so it's always the last buffer of the frame. */
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677 if( p_gmac_dev->l_tx_head == ( int32_t )( p_gmac_dev->ul_tx_list_size - 1 ) )
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679 /* No need to 'and' with GMAC_TXD_LEN_MASK because ul_size has been checked */
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680 p_tx_td->status.val =
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681 ul_size | GMAC_TXD_LAST | GMAC_TXD_WRAP;
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683 p_tx_td->status.val =
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684 ul_size | GMAC_TXD_LAST;
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687 circ_inc32( &p_gmac_dev->l_tx_head, p_gmac_dev->ul_tx_list_size );
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689 /* Now start to transmit if it is still not done */
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690 gmac_start_transmission(p_hw);
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696 * \brief Get current load of transmit.
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698 * \param p_gmac_dev Pointer to the GMAC device instance.
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700 * \return Current load of transmit.
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702 #if( GMAC_USES_TX_CALLBACK != 0 )
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703 /* Without defining GMAC_USES_TX_CALLBACK, l_tx_tail won't be updated */
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704 uint32_t gmac_dev_get_tx_load(gmac_device_t* p_gmac_dev)
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706 uint16_t us_head = p_gmac_dev->l_tx_head;
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707 uint16_t us_tail = p_gmac_dev->l_tx_tail;
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708 return CIRC_CNT(us_head, us_tail, p_gmac_dev->ul_tx_list_size);
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713 * \brief Register/Clear RX callback. Callback will be invoked after the next received
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716 * When gmac_dev_read() returns GMAC_RX_NULL, the application task calls
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717 * gmac_dev_set_rx_callback() to register func_rx_cb() callback and enters suspend state.
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718 * The callback is in charge to resume the task once a new frame has been
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719 * received. The next time gmac_dev_read() is called, it will be successful.
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721 * This function is usually invoked from the RX callback itself with NULL
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722 * callback, to unregister. Once the callback has resumed the application task,
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723 * there is no need to invoke the callback again.
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725 * \param p_gmac_dev Pointer to the GMAC device instance.
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726 * \param func_tx_cb Receive callback function.
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728 void gmac_dev_set_rx_callback(gmac_device_t* p_gmac_dev,
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729 gmac_dev_rx_cb_t func_rx_cb)
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731 Gmac *p_hw = p_gmac_dev->p_hw;
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733 if (func_rx_cb == NULL) {
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734 gmac_disable_interrupt(p_hw, GMAC_IDR_RCOMP);
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735 p_gmac_dev->func_rx_cb = NULL;
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737 p_gmac_dev->func_rx_cb = func_rx_cb;
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738 gmac_enable_interrupt(p_hw, GMAC_IER_RCOMP);
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743 * \brief Register/Clear TX wakeup callback.
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745 * When gmac_dev_write() returns GMAC_TX_BUSY (all transmit descriptor busy), the application
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746 * task calls gmac_dev_set_tx_wakeup_callback() to register func_wakeup() callback and
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747 * enters suspend state. The callback is in charge to resume the task once
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748 * several transmit descriptors have been released. The next time gmac_dev_write() will be called,
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749 * it shall be successful.
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751 * This function is usually invoked with NULL callback from the TX wakeup
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752 * callback itself, to unregister. Once the callback has resumed the
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753 * application task, there is no need to invoke the callback again.
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755 * \param p_gmac_dev Pointer to GMAC device instance.
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756 * \param func_wakeup Pointer to wakeup callback function.
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757 * \param uc_threshold Number of free transmit descriptor before wakeup callback invoked.
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759 * \return GMAC_OK, GMAC_PARAM on parameter error.
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761 #if( GMAC_USES_WAKEUP_CALLBACK )
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762 uint8_t gmac_dev_set_tx_wakeup_callback(gmac_device_t* p_gmac_dev,
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763 gmac_dev_wakeup_cb_t func_wakeup_cb, uint8_t uc_threshold)
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765 if (func_wakeup_cb == NULL) {
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766 p_gmac_dev->func_wakeup_cb = NULL;
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768 if (uc_threshold <= p_gmac_dev->ul_tx_list_size) {
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769 p_gmac_dev->func_wakeup_cb = func_wakeup_cb;
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770 p_gmac_dev->uc_wakeup_threshold = uc_threshold;
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778 #endif /* GMAC_USES_WAKEUP_CALLBACK */
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781 * \brief Reset TX & RX queue & statistics.
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783 * \param p_gmac_dev Pointer to GMAC device instance.
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785 void gmac_dev_reset(gmac_device_t* p_gmac_dev)
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787 Gmac *p_hw = p_gmac_dev->p_hw;
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789 gmac_reset_rx_mem(p_gmac_dev);
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790 gmac_reset_tx_mem(p_gmac_dev);
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791 gmac_network_control(p_hw, GMAC_NCR_TXEN | GMAC_NCR_RXEN
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792 | GMAC_NCR_WESTAT | GMAC_NCR_CLRSTAT);
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795 void gmac_dev_halt(Gmac* p_gmac);
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797 void gmac_dev_halt(Gmac* p_gmac)
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799 gmac_network_control(p_gmac, GMAC_NCR_WESTAT | GMAC_NCR_CLRSTAT);
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800 gmac_disable_interrupt(p_gmac, ~0u);
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805 * \brief GMAC Interrupt handler.
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807 * \param p_gmac_dev Pointer to GMAC device instance.
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810 #if( GMAC_STATS != 0 )
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811 extern int logPrintf( const char *pcFormat, ... );
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813 void gmac_show_irq_counts ()
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816 for (index = 0; index < ARRAY_SIZE(intPairs); index++) {
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817 if (gmacStats.intStatus[intPairs[index].index]) {
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818 logPrintf("%s : %6u\n", intPairs[index].name, gmacStats.intStatus[intPairs[index].index]);
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824 void gmac_handler(gmac_device_t* p_gmac_dev)
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826 Gmac *p_hw = p_gmac_dev->p_hw;
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828 #if( GMAC_USES_TX_CALLBACK != 0 )
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829 gmac_tx_descriptor_t *p_tx_td;
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830 gmac_dev_tx_cb_t *p_tx_cb = NULL;
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831 uint32_t ul_tx_status_flag;
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833 #if( GMAC_STATS != 0 )
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837 /* volatile */ uint32_t ul_isr;
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838 /* volatile */ uint32_t ul_rsr;
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839 /* volatile */ uint32_t ul_tsr;
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841 ul_isr = gmac_get_interrupt_status(p_hw);
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842 ul_rsr = gmac_get_rx_status(p_hw);
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843 ul_tsr = gmac_get_tx_status(p_hw);
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845 /* Why clear bits that are ignored anyway ? */
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846 /* ul_isr &= ~(gmac_get_interrupt_mask(p_hw) | 0xF8030300); */
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847 #if( GMAC_STATS != 0 )
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849 for (index = 0; index < ARRAY_SIZE(intPairs); index++) {
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850 if (ul_isr & intPairs[index].mask)
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851 gmacStats.intStatus[intPairs[index].index]++;
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854 #endif /* GMAC_STATS != 0 */
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857 if ((ul_isr & GMAC_ISR_RCOMP) || (ul_rsr & (GMAC_RSR_REC|GMAC_RSR_RXOVR|GMAC_RSR_BNA))) {
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859 gmac_clear_rx_status(p_hw, ul_rsr);
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861 if (ul_isr & GMAC_ISR_RCOMP)
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862 ul_rsr |= GMAC_RSR_REC;
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863 /* Invoke callbacks which can be useful to wake op a task */
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864 if (p_gmac_dev->func_rx_cb) {
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865 p_gmac_dev->func_rx_cb(ul_rsr);
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870 if ((ul_isr & GMAC_ISR_TCOMP) || (ul_tsr & (GMAC_TSR_TXCOMP|GMAC_TSR_COL|GMAC_TSR_RLE|GMAC_TSR_UND))) {
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872 #if( GMAC_USES_TX_CALLBACK != 0 )
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873 ul_tx_status_flag = GMAC_TSR_TXCOMP;
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875 /* A frame transmitted */
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878 if (ul_tsr & GMAC_TSR_RLE) {
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879 /* Status RLE & Number of discarded buffers */
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880 #if( GMAC_USES_TX_CALLBACK != 0 )
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881 ul_tx_status_flag = GMAC_TSR_RLE | CIRC_CNT(p_gmac_dev->l_tx_head,
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882 p_gmac_dev->l_tx_tail, p_gmac_dev->ul_tx_list_size);
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883 p_tx_cb = &p_gmac_dev->func_tx_cb_list[p_gmac_dev->l_tx_tail];
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885 gmac_reset_tx_mem(p_gmac_dev);
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886 gmac_enable_transmit(p_hw, 1);
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889 gmac_clear_tx_status(p_hw, ul_tsr);
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891 #if( GMAC_USES_TX_CALLBACK != 0 )
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892 if (!CIRC_EMPTY(p_gmac_dev->l_tx_head, p_gmac_dev->l_tx_tail)) {
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893 /* Check the buffers */
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895 p_tx_td = &p_gmac_dev->p_tx_dscr[p_gmac_dev->l_tx_tail];
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896 p_tx_cb = &p_gmac_dev->func_tx_cb_list[p_gmac_dev->l_tx_tail];
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897 /* Any error? Exit if buffer has not been sent yet */
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898 if ((p_tx_td->status.val & GMAC_TXD_USED) == 0) {
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902 /* Notify upper layer that a packet has been sent */
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904 (*p_tx_cb) (ul_tx_status_flag, (void*)p_tx_td->addr);
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905 #if( ipconfigZERO_COPY_TX_DRIVER != 0 )
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907 p_tx_td->addr = 0ul;
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909 #endif /* ipconfigZERO_COPY_TX_DRIVER */
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912 circ_inc32(&p_gmac_dev->l_tx_tail, p_gmac_dev->ul_tx_list_size);
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913 } while (CIRC_CNT(p_gmac_dev->l_tx_head, p_gmac_dev->l_tx_tail,
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914 p_gmac_dev->ul_tx_list_size));
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917 if (ul_tsr & GMAC_TSR_RLE) {
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918 /* Notify upper layer RLE */
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920 (*p_tx_cb) (ul_tx_status_flag, NULL);
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923 #endif /* GMAC_USES_TX_CALLBACK */
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925 #if( GMAC_USES_WAKEUP_CALLBACK )
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926 /* If a wakeup has been scheduled, notify upper layer that it can
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927 send other packets, and the sending will be successful. */
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928 if ((CIRC_SPACE(p_gmac_dev->l_tx_head, p_gmac_dev->l_tx_tail,
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929 p_gmac_dev->ul_tx_list_size) >= p_gmac_dev->uc_wakeup_threshold)
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930 && p_gmac_dev->func_wakeup_cb) {
\r
931 p_gmac_dev->func_wakeup_cb();
\r
projects / freertos / blob