4 * \brief GMAC (Ethernet MAC) driver for SAM.
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6 * Copyright (c) 2013 Atmel Corporation. All rights reserved.
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12 * Redistribution and use in source and binary forms, with or without
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13 * modification, are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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18 * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 * this list of conditions and the following disclaimer in the documentation
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20 * and/or other materials provided with the distribution.
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22 * 3. The name of Atmel may not be used to endorse or promote products derived
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23 * from this software without specific prior written permission.
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25 * 4. This software may only be redistributed and used in connection with an
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26 * Atmel microcontroller product.
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28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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38 * POSSIBILITY OF SUCH DAMAGE.
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44 #ifndef GMAC_H_INCLUDED
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45 #define GMAC_H_INCLUDED
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47 #include "compiler.h"
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48 #include "component/gmac.h"
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58 /** The buffer addresses written into the descriptors must be aligned, so the
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59 last few bits are zero. These bits have special meaning for the GMAC
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60 peripheral and cannot be used as part of the address. */
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61 #define GMAC_RXD_ADDR_MASK 0xFFFFFFFC
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62 #define GMAC_RXD_WRAP (1ul << 1) /**< Wrap bit */
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63 #define GMAC_RXD_OWNERSHIP (1ul << 0) /**< Ownership bit */
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65 #define GMAC_RXD_BROADCAST (1ul << 31) /**< Broadcast detected */
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66 #define GMAC_RXD_MULTIHASH (1ul << 30) /**< Multicast hash match */
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67 #define GMAC_RXD_UNIHASH (1ul << 29) /**< Unicast hash match */
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68 #define GMAC_RXD_ADDR_FOUND (1ul << 27) /**< Specific address match found */
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69 #define GMAC_RXD_ADDR (3ul << 25) /**< Address match */
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70 #define GMAC_RXD_RXCOEN (1ul << 24) /**< RXCOEN related function */
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71 #define GMAC_RXD_TYPE (3ul << 22) /**< Type ID match */
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72 #define GMAC_RXD_VLAN (1ul << 21) /**< VLAN tag detected */
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73 #define GMAC_RXD_PRIORITY (1ul << 20) /**< Priority tag detected */
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74 #define GMAC_RXD_PRIORITY_MASK (3ul << 17) /**< VLAN priority */
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75 #define GMAC_RXD_CFI (1ul << 16) /**< Concatenation Format Indicator only if bit 21 is set */
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76 #define GMAC_RXD_EOF (1ul << 15) /**< End of frame */
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77 #define GMAC_RXD_SOF (1ul << 14) /**< Start of frame */
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78 #define GMAC_RXD_FCS (1ul << 13) /**< Frame check sequence */
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79 #define GMAC_RXD_OFFSET_MASK /**< Receive buffer offset */
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80 #define GMAC_RXD_LEN_MASK (0xFFF) /**< Length of frame including FCS (if selected) */
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81 #define GMAC_RXD_LENJUMBO_MASK (0x3FFF) /**< Jumbo frame length */
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83 #define GMAC_TXD_USED (1ul << 31) /**< Frame is transmitted */
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84 #define GMAC_TXD_WRAP (1ul << 30) /**< Last descriptor */
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85 #define GMAC_TXD_ERROR (1ul << 29) /**< Retry limit exceeded, error */
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86 #define GMAC_TXD_UNDERRUN (1ul << 28) /**< Transmit underrun */
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87 #define GMAC_TXD_EXHAUSTED (1ul << 27) /**< Buffer exhausted */
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88 #define GMAC_TXD_LATE (1ul << 26) /**< Late collision,transmit error */
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89 #define GMAC_TXD_CHECKSUM_ERROR (7ul << 20) /**< Checksum error */
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90 #define GMAC_TXD_NOCRC (1ul << 16) /**< No CRC */
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91 #define GMAC_TXD_LAST (1ul << 15) /**< Last buffer in frame */
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92 #define GMAC_TXD_LEN_MASK (0x1FFF) /**< Length of buffer */
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94 /** The MAC can support frame lengths up to 1536 bytes */
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95 #define GMAC_FRAME_LENTGH_MAX 1536
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97 #define GMAC_RX_UNITSIZE 128 /**< Fixed size for RX buffer */
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98 #define GMAC_TX_UNITSIZE 1518 /**< Size for ETH frame length */
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100 /** GMAC clock speed */
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101 #define GMAC_MCK_SPEED_240MHZ (240*1000*1000)
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102 #define GMAC_MCK_SPEED_160MHZ (160*1000*1000)
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103 #define GMAC_MCK_SPEED_120MHZ (120*1000*1000)
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104 #define GMAC_MCK_SPEED_80MHZ (80*1000*1000)
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105 #define GMAC_MCK_SPEED_40MHZ (40*1000*1000)
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106 #define GMAC_MCK_SPEED_20MHZ (20*1000*1000)
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108 /** GMAC maintain code default value*/
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109 #define GMAC_MAN_CODE_VALUE (10)
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111 /** GMAC maintain start of frame default value*/
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112 #define GMAC_MAN_SOF_VALUE (1)
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114 /** GMAC maintain read/write*/
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115 #define GMAC_MAN_RW_TYPE (2)
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117 /** GMAC maintain read only*/
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118 #define GMAC_MAN_READ_ONLY (1)
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120 /** GMAC address length */
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121 #define GMAC_ADDR_LENGTH (6)
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124 #define GMAC_DUPLEX_HALF 0
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125 #define GMAC_DUPLEX_FULL 1
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127 #define GMAC_SPEED_10M 0
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128 #define GMAC_SPEED_100M 1
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131 * \brief Return codes for GMAC APIs.
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134 GMAC_OK = 0, /** 0 Operation OK */
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135 GMAC_TIMEOUT = 1, /** 1 GMAC operation timeout */
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136 GMAC_TX_BUSY, /** 2 TX in progress */
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137 GMAC_RX_NULL, /** 3 No data received */
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138 GMAC_SIZE_TOO_SMALL, /** 4 Buffer size not enough */
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139 GMAC_PARAM, /** 5 Parameter error, TX packet invalid or RX size too small */
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140 GMAC_INVALID = 0xFF, /* Invalid */
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144 * \brief Media Independent Interface (MII) type.
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147 GMAC_PHY_MII = 0, /** MII mode */
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148 GMAC_PHY_RMII = 1, /** Reduced MII mode */
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149 GMAC_PHY_INVALID = 0xFF, /* Invalid mode*/
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152 /** Receive buffer descriptor struct */
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153 COMPILER_PACK_SET(8)
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154 typedef struct gmac_rx_descriptor {
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155 union gmac_rx_addr {
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157 struct gmac_rx_addr_bm {
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158 uint32_t b_ownership:1, /**< User clear, GMAC sets this to 1 once it has successfully written a frame to memory */
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159 b_wrap:1, /**< Marks last descriptor in receive buffer */
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160 addr_dw:30; /**< Address in number of DW */
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162 } addr; /**< Address, Wrap & Ownership */
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163 union gmac_rx_status {
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165 struct gmac_rx_status_bm {
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166 uint32_t len:13, /** 0..12 Length of frame including FCS */
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167 b_fcs:1, /** 13 Receive buffer offset, bits 13:12 of frame length for jumbo frame */
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168 b_sof:1, /** 14 Start of frame */
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169 b_eof:1, /** 15 End of frame */
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170 b_cfi:1, /** 16 Concatenation Format Indicator */
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171 vlan_priority:3, /** 17..19 VLAN priority (if VLAN detected) */
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172 b_priority_detected:1, /** 20 Priority tag detected */
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173 b_vlan_detected:1, /** 21 VLAN tag detected */
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174 b_type_id_match:2, /** 22..23 Type ID match */
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175 b_checksumoffload:1, /** 24 Checksum offload specific function */
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176 b_addrmatch:2, /** 25..26 Address register match */
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177 b_ext_addr_match:1, /** 27 External address match found */
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178 reserved:1, /** 28 */
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179 b_uni_hash_match:1, /** 29 Unicast hash match */
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180 b_multi_hash_match:1, /** 30 Multicast hash match */
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181 b_boardcast_detect:1; /** 31 Global broadcast address detected */
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184 } gmac_rx_descriptor_t;
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186 /** Transmit buffer descriptor struct */
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187 COMPILER_PACK_SET(8)
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188 typedef struct gmac_tx_descriptor {
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190 union gmac_tx_status {
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192 struct gmac_tx_status_bm {
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193 uint32_t len:14, /** 0..13 Length of buffer */
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194 reserved:1, /** 14 */
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195 b_last_buffer:1, /** 15 Last buffer (in the current frame) */
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196 b_no_crc:1, /** 16 No CRC */
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197 reserved1:3, /** 17..19 */
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198 b_checksumoffload:3, /** 20..22 Transmit checksum generation offload errors */
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199 reserved2:3, /** 23..25 */
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200 b_lco:1, /** 26 Late collision, transmit error detected */
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201 b_exhausted:1, /** 27 Buffer exhausted in mid frame */
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202 b_underrun:1, /** 28 Transmit underrun */
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203 b_error:1, /** 29 Retry limit exceeded, error detected */
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204 b_wrap:1, /** 30 Marks last descriptor in TD list */
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205 b_used:1; /** 31 User clear, GMAC sets this to 1 once a frame has been successfully transmitted */
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208 } gmac_tx_descriptor_t;
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210 COMPILER_PACK_RESET()
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213 * \brief Input parameters when initializing the gmac module mode.
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215 typedef struct gmac_options {
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216 /* Enable/Disable CopyAllFrame */
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217 uint8_t uc_copy_all_frame;
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218 /* Enable/Disable NoBroadCast */
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219 uint8_t uc_no_boardcast;
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221 uint8_t uc_mac_addr[GMAC_ADDR_LENGTH];
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225 typedef void (*gmac_dev_tx_cb_t) (uint32_t ul_status, uint8_t *puc_buffer);
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227 typedef void (*gmac_dev_rx_cb_t) (uint32_t ul_status);
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228 /** Wakeup callback */
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229 typedef void (*gmac_dev_wakeup_cb_t) (void);
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232 * GMAC driver structure.
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234 typedef struct gmac_device {
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236 /** Pointer to HW register base */
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239 * Pointer to allocated TX buffer.
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240 * Section 3.6 of AMBA 2.0 spec states that burst should not cross
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242 * Receive buffer manager writes are burst of 2 words => 3 lsb bits
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243 * of the address shall be set to 0.
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245 uint8_t *p_tx_buffer;
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246 /** Pointer to allocated RX buffer */
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247 uint8_t *p_rx_buffer;
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248 /** Pointer to Rx TDs (must be 8-byte aligned) */
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249 gmac_rx_descriptor_t *p_rx_dscr;
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250 /** Pointer to Tx TDs (must be 8-byte aligned) */
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251 gmac_tx_descriptor_t *p_tx_dscr;
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252 /** Optional callback to be invoked once a frame has been received */
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253 gmac_dev_rx_cb_t func_rx_cb;
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254 #if( GMAC_USES_WAKEUP_CALLBACK )
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255 /** Optional callback to be invoked once several TDs have been released */
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256 gmac_dev_wakeup_cb_t func_wakeup_cb;
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258 #if( GMAC_USES_TX_CALLBACK != 0 )
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259 /** Optional callback list to be invoked once TD has been processed */
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260 gmac_dev_tx_cb_t *func_tx_cb_list;
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262 /** RX TD list size */
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263 uint32_t ul_rx_list_size;
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264 /** RX index for current processing TD */
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265 uint32_t ul_rx_idx;
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266 /** TX TD list size */
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267 uint32_t ul_tx_list_size;
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268 /** Circular buffer head pointer by upper layer (buffer to be sent) */
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270 /** Circular buffer tail pointer incremented by handlers (buffer sent) */
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273 /** Number of free TD before wakeup callback is invoked */
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274 uint32_t uc_wakeup_threshold;
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278 * \brief Write network control value.
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280 * \param p_gmac Pointer to the GMAC instance.
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281 * \param ul_ncr Network control value.
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283 static inline void gmac_network_control(Gmac* p_gmac, uint32_t ul_ncr)
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285 p_gmac->GMAC_NCR = ul_ncr;
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289 * \brief Get network control value.
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291 * \param p_gmac Pointer to the GMAC instance.
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294 static inline uint32_t gmac_get_network_control(Gmac* p_gmac)
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296 return p_gmac->GMAC_NCR;
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300 * \brief Enable/Disable GMAC receive.
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302 * \param p_gmac Pointer to the GMAC instance.
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303 * \param uc_enable 0 to disable GMAC receiver, else to enable it.
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305 static inline void gmac_enable_receive(Gmac* p_gmac, uint8_t uc_enable)
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308 p_gmac->GMAC_NCR |= GMAC_NCR_RXEN;
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310 p_gmac->GMAC_NCR &= ~GMAC_NCR_RXEN;
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315 * \brief Enable/Disable GMAC transmit.
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317 * \param p_gmac Pointer to the GMAC instance.
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318 * \param uc_enable 0 to disable GMAC transmit, else to enable it.
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320 static inline void gmac_enable_transmit(Gmac* p_gmac, uint8_t uc_enable)
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323 p_gmac->GMAC_NCR |= GMAC_NCR_TXEN;
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325 p_gmac->GMAC_NCR &= ~GMAC_NCR_TXEN;
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330 * \brief Enable/Disable GMAC management.
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332 * \param p_gmac Pointer to the GMAC instance.
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333 * \param uc_enable 0 to disable GMAC management, else to enable it.
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335 static inline void gmac_enable_management(Gmac* p_gmac, uint8_t uc_enable)
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338 p_gmac->GMAC_NCR |= GMAC_NCR_MPE;
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340 p_gmac->GMAC_NCR &= ~GMAC_NCR_MPE;
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345 * \brief Clear all statistics registers.
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347 * \param p_gmac Pointer to the GMAC instance.
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349 static inline void gmac_clear_statistics(Gmac* p_gmac)
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351 p_gmac->GMAC_NCR |= GMAC_NCR_CLRSTAT;
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355 * \brief Increase all statistics registers.
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357 * \param p_gmac Pointer to the GMAC instance.
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359 static inline void gmac_increase_statistics(Gmac* p_gmac)
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361 p_gmac->GMAC_NCR |= GMAC_NCR_INCSTAT;
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365 * \brief Enable/Disable statistics registers writing.
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367 * \param p_gmac Pointer to the GMAC instance.
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368 * \param uc_enable 0 to disable the statistics registers writing, else to enable it.
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370 static inline void gmac_enable_statistics_write(Gmac* p_gmac,
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374 p_gmac->GMAC_NCR |= GMAC_NCR_WESTAT;
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376 p_gmac->GMAC_NCR &= ~GMAC_NCR_WESTAT;
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381 * \brief In half-duplex mode, forces collisions on all received frames.
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383 * \param p_gmac Pointer to the GMAC instance.
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384 * \param uc_enable 0 to disable the back pressure, else to enable it.
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386 static inline void gmac_enable_back_pressure(Gmac* p_gmac, uint8_t uc_enable)
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389 p_gmac->GMAC_NCR |= GMAC_NCR_BP;
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391 p_gmac->GMAC_NCR &= ~GMAC_NCR_BP;
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396 * \brief Start transmission.
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398 * \param p_gmac Pointer to the GMAC instance.
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400 static inline void gmac_start_transmission(Gmac* p_gmac)
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402 p_gmac->GMAC_NCR |= GMAC_NCR_TSTART;
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406 * \brief Halt transmission.
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408 * \param p_gmac Pointer to the GMAC instance.
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410 static inline void gmac_halt_transmission(Gmac* p_gmac)
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412 p_gmac->GMAC_NCR |= GMAC_NCR_THALT;
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416 * \brief Transmit pause frame.
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418 * \param p_gmac Pointer to the GMAC instance.
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420 static inline void gmac_tx_pause_frame(Gmac* p_gmac)
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422 p_gmac->GMAC_NCR |= GMAC_NCR_TXPF;
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426 * \brief Transmit zero quantum pause frame.
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428 * \param p_gmac Pointer to the GMAC instance.
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430 static inline void gmac_tx_pause_zero_quantum_frame(Gmac* p_gmac)
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432 p_gmac->GMAC_NCR |= GMAC_NCR_TXZQPF;
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436 * \brief Read snapshot.
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438 * \param p_gmac Pointer to the GMAC instance.
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440 static inline void gmac_read_snapshot(Gmac* p_gmac)
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442 p_gmac->GMAC_NCR |= GMAC_NCR_RDS;
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446 * \brief Store receivetime stamp to memory.
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448 * \param p_gmac Pointer to the GMAC instance.
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449 * \param uc_enable 0 to normal operation, else to enable the store.
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451 static inline void gmac_store_rx_time_stamp(Gmac* p_gmac, uint8_t uc_enable)
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454 p_gmac->GMAC_NCR |= GMAC_NCR_SRTSM;
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456 p_gmac->GMAC_NCR &= ~GMAC_NCR_SRTSM;
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461 * \brief Enable PFC priority-based pause reception.
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463 * \param p_gmac Pointer to the GMAC instance.
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464 * \param uc_enable 1 to set the reception, 0 to disable.
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466 static inline void gmac_enable_pfc_pause_frame(Gmac* p_gmac, uint8_t uc_enable)
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469 p_gmac->GMAC_NCR |= GMAC_NCR_ENPBPR;
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471 p_gmac->GMAC_NCR &= ~GMAC_NCR_ENPBPR;
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476 * \brief Transmit PFC priority-based pause reception.
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478 * \param p_gmac Pointer to the GMAC instance.
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480 static inline void gmac_transmit_pfc_pause_frame(Gmac* p_gmac)
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482 p_gmac->GMAC_NCR |= GMAC_NCR_TXPBPF;
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486 * \brief Flush next packet.
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488 * \param p_gmac Pointer to the GMAC instance.
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490 static inline void gmac_flush_next_packet(Gmac* p_gmac)
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492 p_gmac->GMAC_NCR |= GMAC_NCR_FNP;
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496 * \brief Set up network configuration register.
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498 * \param p_gmac Pointer to the GMAC instance.
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499 * \param ul_cfg Network configuration value.
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501 static inline void gmac_set_configure(Gmac* p_gmac, uint32_t ul_cfg)
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503 p_gmac->GMAC_NCFGR = ul_cfg;
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507 * \brief Get network configuration.
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509 * \param p_gmac Pointer to the GMAC instance.
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511 * \return Network configuration.
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513 static inline uint32_t gmac_get_configure(Gmac* p_gmac)
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515 return p_gmac->GMAC_NCFGR;
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519 /* Get and set DMA Configuration Register */
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520 static inline void gmac_set_dma(Gmac* p_gmac, uint32_t ul_cfg)
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522 p_gmac->GMAC_DCFGR = ul_cfg;
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525 static inline uint32_t gmac_get_dma(Gmac* p_gmac)
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527 return p_gmac->GMAC_DCFGR;
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531 * \brief Set speed.
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533 * \param p_gmac Pointer to the GMAC instance.
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534 * \param uc_speed 1 to indicate 100Mbps, 0 to 10Mbps.
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536 static inline void gmac_set_speed(Gmac* p_gmac, uint8_t uc_speed)
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539 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_SPD;
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541 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_SPD;
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546 * \brief Enable/Disable Full-Duplex mode.
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548 * \param p_gmac Pointer to the GMAC instance.
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549 * \param uc_enable 0 to disable the Full-Duplex mode, else to enable it.
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551 static inline void gmac_enable_full_duplex(Gmac* p_gmac, uint8_t uc_enable)
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554 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_FD;
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556 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_FD;
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561 * \brief Enable/Disable Copy(Receive) All Valid Frames.
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563 * \param p_gmac Pointer to the GMAC instance.
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564 * \param uc_enable 0 to disable copying all valid frames, else to enable it.
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566 static inline void gmac_enable_copy_all(Gmac* p_gmac, uint8_t uc_enable)
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569 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_CAF;
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571 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_CAF;
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576 * \brief Enable/Disable jumbo frames (up to 10240 bytes).
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578 * \param p_gmac Pointer to the GMAC instance.
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579 * \param uc_enable 0 to disable the jumbo frames, else to enable it.
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581 static inline void gmac_enable_jumbo_frames(Gmac* p_gmac, uint8_t uc_enable)
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584 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_JFRAME;
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586 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_JFRAME;
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591 * \brief Disable/Enable broadcast receiving.
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593 * \param p_gmac Pointer to the GMAC instance.
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594 * \param uc_enable 1 to disable the broadcast, else to enable it.
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596 static inline void gmac_disable_broadcast(Gmac* p_gmac, uint8_t uc_enable)
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599 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_NBC;
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601 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_NBC;
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606 * \brief Enable/Disable multicast hash.
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608 * \param p_gmac Pointer to the GMAC instance.
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609 * \param uc_enable 0 to disable the multicast hash, else to enable it.
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611 static inline void gmac_enable_multicast_hash(Gmac* p_gmac, uint8_t uc_enable)
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614 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_UNIHEN;
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616 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_UNIHEN;
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621 * \brief Enable/Disable big frames (over 1518, up to 1536).
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623 * \param p_gmac Pointer to the GMAC instance.
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624 * \param uc_enable 0 to disable big frames else to enable it.
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626 static inline void gmac_enable_big_frame(Gmac* p_gmac, uint8_t uc_enable)
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629 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_MAXFS;
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631 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_MAXFS;
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636 * \brief Set MDC clock divider.
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638 * \param p_gmac Pointer to the GMAC instance.
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639 * \param ul_mck GMAC MCK.
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641 * \return GMAC_OK if successfully.
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643 static inline uint8_t gmac_set_mdc_clock(Gmac* p_gmac, uint32_t ul_mck)
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647 if (ul_mck > GMAC_MCK_SPEED_240MHZ) {
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648 return GMAC_INVALID;
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649 } else if (ul_mck > GMAC_MCK_SPEED_160MHZ) {
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650 ul_clk = GMAC_NCFGR_CLK_MCK_96;
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651 } else if (ul_mck > GMAC_MCK_SPEED_120MHZ) {
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652 ul_clk = GMAC_NCFGR_CLK_MCK_64;
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653 } else if (ul_mck > GMAC_MCK_SPEED_80MHZ) {
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654 ul_clk = GMAC_NCFGR_CLK_MCK_48;
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655 } else if (ul_mck > GMAC_MCK_SPEED_40MHZ) {
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656 ul_clk = GMAC_NCFGR_CLK_MCK_32;
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657 } else if (ul_mck > GMAC_MCK_SPEED_20MHZ) {
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658 ul_clk = GMAC_NCFGR_CLK_MCK_16;
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660 ul_clk = GMAC_NCFGR_CLK_MCK_8;
\r
663 p_gmac->GMAC_NCFGR = (p_gmac->GMAC_NCFGR & ~GMAC_NCFGR_CLK_Msk) | ul_clk;
\r
668 * \brief Enable/Disable retry test.
\r
670 * \param p_gmac Pointer to the GMAC instance.
\r
671 * \param uc_enable 0 to disable the GMAC receiver, else to enable it.
\r
673 static inline void gmac_enable_retry_test(Gmac* p_gmac, uint8_t uc_enable)
\r
676 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_RTY;
\r
678 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_RTY;
\r
683 * \brief Enable/Disable pause (when a valid pause frame is received).
\r
685 * \param p_gmac Pointer to the GMAC instance.
\r
686 * \param uc_enable 0 to disable pause frame, else to enable it.
\r
688 static inline void gmac_enable_pause_frame(Gmac* p_gmac, uint8_t uc_enable)
\r
691 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_PEN;
\r
693 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_PEN;
\r
698 * \brief Set receive buffer offset to 0 ~ 3.
\r
700 * \param p_gmac Pointer to the GMAC instance.
\r
702 static inline void gmac_set_rx_buffer_offset(Gmac* p_gmac, uint8_t uc_offset)
\r
704 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_RXBUFO_Msk;
\r
705 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_RXBUFO(uc_offset);
\r
709 * \brief Enable/Disable receive length field checking.
\r
711 * \param p_gmac Pointer to the GMAC instance.
\r
712 * \param uc_enable 0 to disable receive length field checking, else to enable it.
\r
714 static inline void gmac_enable_rx_length_check(Gmac* p_gmac, uint8_t uc_enable)
\r
717 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_LFERD;
\r
719 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_LFERD;
\r
724 * \brief Enable/Disable discarding FCS field of received frames.
\r
726 * \param p_gmac Pointer to the GMAC instance.
\r
727 * \param uc_enable 0 to disable discarding FCS field of received frames, else to enable it.
\r
729 static inline void gmac_enable_discard_fcs(Gmac* p_gmac, uint8_t uc_enable)
\r
732 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_RFCS;
\r
734 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_RFCS;
\r
740 * \brief Enable/Disable frames to be received in half-duplex mode
\r
741 * while transmitting.
\r
743 * \param p_gmac Pointer to the GMAC instance.
\r
744 * \param uc_enable 0 to disable the received in half-duplex mode, else to enable it.
\r
746 static inline void gmac_enable_efrhd(Gmac* p_gmac, uint8_t uc_enable)
\r
749 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_EFRHD;
\r
751 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_EFRHD;
\r
756 * \brief Enable/Disable ignore RX FCS.
\r
758 * \param p_gmac Pointer to the GMAC instance.
\r
759 * \param uc_enable 0 to disable ignore RX FCS, else to enable it.
\r
761 static inline void gmac_enable_ignore_rx_fcs(Gmac* p_gmac, uint8_t uc_enable)
\r
764 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_IRXFCS;
\r
766 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_IRXFCS;
\r
771 * \brief Get Network Status.
\r
773 * \param p_gmac Pointer to the GMAC instance.
\r
775 * \return Network status.
\r
777 static inline uint32_t gmac_get_status(Gmac* p_gmac)
\r
779 return p_gmac->GMAC_NSR;
\r
783 * \brief Get MDIO IN pin status.
\r
785 * \param p_gmac Pointer to the GMAC instance.
\r
787 * \return MDIO IN pin status.
\r
789 static inline uint8_t gmac_get_MDIO(Gmac* p_gmac)
\r
791 return ((p_gmac->GMAC_NSR & GMAC_NSR_MDIO) > 0);
\r
795 * \brief Check if PHY is idle.
\r
797 * \param p_gmac Pointer to the GMAC instance.
\r
799 * \return 1 if PHY is idle.
\r
801 static inline uint8_t gmac_is_phy_idle(Gmac* p_gmac)
\r
803 return ((p_gmac->GMAC_NSR & GMAC_NSR_IDLE) > 0);
\r
807 * \brief Return transmit status.
\r
809 * \param p_gmac Pointer to the GMAC instance.
\r
811 * \return Transmit status.
\r
813 static inline uint32_t gmac_get_tx_status(Gmac* p_gmac)
\r
815 return p_gmac->GMAC_TSR;
\r
819 * \brief Clear transmit status.
\r
821 * \param p_gmac Pointer to the GMAC instance.
\r
822 * \param ul_status Transmit status.
\r
824 static inline void gmac_clear_tx_status(Gmac* p_gmac, uint32_t ul_status)
\r
826 p_gmac->GMAC_TSR = ul_status;
\r
830 * \brief Return receive status.
\r
832 * \param p_gmac Pointer to the GMAC instance.
\r
834 static inline uint32_t gmac_get_rx_status(Gmac* p_gmac)
\r
836 return p_gmac->GMAC_RSR;
\r
840 * \brief Clear receive status.
\r
842 * \param p_gmac Pointer to the GMAC instance.
\r
843 * \param ul_status Receive status.
\r
845 static inline void gmac_clear_rx_status(Gmac* p_gmac, uint32_t ul_status)
\r
847 p_gmac->GMAC_RSR = ul_status;
\r
851 * \brief Set Rx Queue.
\r
853 * \param p_gmac Pointer to the GMAC instance.
\r
854 * \param ul_addr Rx queue address.
\r
856 static inline void gmac_set_rx_queue(Gmac* p_gmac, uint32_t ul_addr)
\r
858 p_gmac->GMAC_RBQB = GMAC_RBQB_ADDR_Msk & ul_addr;
\r
862 * \brief Get Rx Queue Address.
\r
864 * \param p_gmac Pointer to the GMAC instance.
\r
866 * \return Rx queue address.
\r
868 static inline uint32_t gmac_get_rx_queue(Gmac* p_gmac)
\r
870 return p_gmac->GMAC_RBQB;
\r
874 * \brief Set Tx Queue.
\r
876 * \param p_gmac Pointer to the GMAC instance.
\r
877 * \param ul_addr Tx queue address.
\r
879 static inline void gmac_set_tx_queue(Gmac* p_gmac, uint32_t ul_addr)
\r
881 p_gmac->GMAC_TBQB = GMAC_TBQB_ADDR_Msk & ul_addr;
\r
885 * \brief Get Tx Queue.
\r
887 * \param p_gmac Pointer to the GMAC instance.
\r
889 * \return Rx queue address.
\r
891 static inline uint32_t gmac_get_tx_queue(Gmac* p_gmac)
\r
893 return p_gmac->GMAC_TBQB;
\r
897 * \brief Enable interrupt(s).
\r
899 * \param p_gmac Pointer to the GMAC instance.
\r
900 * \param ul_source Interrupt source(s) to be enabled.
\r
902 static inline void gmac_enable_interrupt(Gmac* p_gmac, uint32_t ul_source)
\r
904 p_gmac->GMAC_IER = ul_source;
\r
908 * \brief Disable interrupt(s).
\r
910 * \param p_gmac Pointer to the GMAC instance.
\r
911 * \param ul_source Interrupt source(s) to be disabled.
\r
913 static inline void gmac_disable_interrupt(Gmac* p_gmac, uint32_t ul_source)
\r
915 p_gmac->GMAC_IDR = ul_source;
\r
919 * \brief Return interrupt status.
\r
921 * \param p_gmac Pointer to the GMAC instance.
\r
923 * \return Interrupt status.
\r
925 static inline uint32_t gmac_get_interrupt_status(Gmac* p_gmac)
\r
927 return p_gmac->GMAC_ISR;
\r
931 * \brief Return interrupt mask.
\r
933 * \param p_gmac Pointer to the GMAC instance.
\r
935 * \return Interrupt mask.
\r
937 static inline uint32_t gmac_get_interrupt_mask(Gmac* p_gmac)
\r
939 return p_gmac->GMAC_IMR;
\r
943 * \brief Execute PHY maintenance command.
\r
945 * \param p_gmac Pointer to the GMAC instance.
\r
946 * \param uc_phy_addr PHY address.
\r
947 * \param uc_reg_addr Register address.
\r
948 * \param uc_rw 1 to Read, 0 to write.
\r
949 * \param us_data Data to be performed, write only.
\r
951 static inline void gmac_maintain_phy(Gmac* p_gmac,
\r
952 uint8_t uc_phy_addr, uint8_t uc_reg_addr, uint8_t uc_rw,
\r
955 /* Wait until bus idle */
\r
956 while ((p_gmac->GMAC_NSR & GMAC_NSR_IDLE) == 0);
\r
957 /* Write maintain register */
\r
958 p_gmac->GMAC_MAN = GMAC_MAN_WTN(GMAC_MAN_CODE_VALUE)
\r
960 | GMAC_MAN_PHYA(uc_phy_addr)
\r
961 | GMAC_MAN_REGA(uc_reg_addr)
\r
962 | GMAC_MAN_OP((uc_rw ? GMAC_MAN_RW_TYPE : GMAC_MAN_READ_ONLY))
\r
963 | GMAC_MAN_DATA(us_data);
\r
967 * \brief Get PHY maintenance data returned.
\r
969 * \param p_gmac Pointer to the GMAC instance.
\r
971 * \return Get PHY data.
\r
973 static inline uint16_t gmac_get_phy_data(Gmac* p_gmac)
\r
975 /* Wait until bus idle */
\r
976 while ((p_gmac->GMAC_NSR & GMAC_NSR_IDLE) == 0);
\r
978 return (uint16_t) (p_gmac->GMAC_MAN & GMAC_MAN_DATA_Msk);
\r
984 * \param p_gmac Pointer to the GMAC instance.
\r
985 * \param ul_hash_top Hash top.
\r
986 * \param ul_hash_bottom Hash bottom.
\r
988 static inline void gmac_set_hash(Gmac* p_gmac, uint32_t ul_hash_top,
\r
989 uint32_t ul_hash_bottom)
\r
991 p_gmac->GMAC_HRB = ul_hash_bottom;
\r
992 p_gmac->GMAC_HRT = ul_hash_top;
\r
996 * \brief Set 64 bits Hash.
\r
998 * \param p_gmac Pointer to the GMAC instance.
\r
999 * \param ull_hash 64 bits hash value.
\r
1001 static inline void gmac_set_hash64(Gmac* p_gmac, uint64_t ull_hash)
\r
1003 p_gmac->GMAC_HRB = (uint32_t) ull_hash;
\r
1004 p_gmac->GMAC_HRT = (uint32_t) (ull_hash >> 32);
\r
1008 * \brief Set MAC Address.
\r
1010 * \param p_gmac Pointer to the GMAC instance.
\r
1011 * \param uc_index GMAC specific address register index.
\r
1012 * \param p_mac_addr GMAC address.
\r
1014 static inline void gmac_set_address(Gmac* p_gmac, uint8_t uc_index,
\r
1015 uint8_t* p_mac_addr)
\r
1017 p_gmac->GMAC_SA[uc_index].GMAC_SAB = (p_mac_addr[3] << 24)
\r
1018 | (p_mac_addr[2] << 16)
\r
1019 | (p_mac_addr[1] << 8)
\r
1020 | (p_mac_addr[0]);
\r
1021 p_gmac->GMAC_SA[uc_index].GMAC_SAT = (p_mac_addr[5] << 8)
\r
1022 | (p_mac_addr[4]);
\r
1026 * \brief Set MAC Address via 2 dword.
\r
1028 * \param p_gmac Pointer to the GMAC instance.
\r
1029 * \param uc_index GMAC specific address register index.
\r
1030 * \param ul_mac_top GMAC top address.
\r
1031 * \param ul_mac_bottom GMAC bottom address.
\r
1033 static inline void gmac_set_address32(Gmac* p_gmac, uint8_t uc_index,
\r
1034 uint32_t ul_mac_top, uint32_t ul_mac_bottom)
\r
1036 p_gmac->GMAC_SA[uc_index].GMAC_SAB = ul_mac_bottom;
\r
1037 p_gmac->GMAC_SA[uc_index].GMAC_SAT = ul_mac_top;
\r
1041 * \brief Set MAC Address via int64.
\r
1043 * \param p_gmac Pointer to the GMAC instance.
\r
1044 * \param uc_index GMAC specific address register index.
\r
1045 * \param ull_mac 64-bit GMAC address.
\r
1047 static inline void gmac_set_address64(Gmac* p_gmac, uint8_t uc_index,
\r
1050 p_gmac->GMAC_SA[uc_index].GMAC_SAB = (uint32_t) ull_mac;
\r
1051 p_gmac->GMAC_SA[uc_index].GMAC_SAT = (uint32_t) (ull_mac >> 32);
\r
1055 * \brief Select media independent interface mode.
\r
1057 * \param p_gmac Pointer to the GMAC instance.
\r
1058 * \param mode Media independent interface mode.
\r
1060 static inline void gmac_select_mii_mode(Gmac* p_gmac, gmac_mii_mode_t mode)
\r
1063 case GMAC_PHY_MII:
\r
1064 case GMAC_PHY_RMII:
\r
1065 p_gmac->GMAC_UR |= GMAC_UR_RMIIMII;
\r
1069 p_gmac->GMAC_UR &= ~GMAC_UR_RMIIMII;
\r
1074 uint8_t gmac_phy_read(Gmac* p_gmac, uint8_t uc_phy_address, uint8_t uc_address,
\r
1075 uint32_t* p_value);
\r
1076 uint8_t gmac_phy_write(Gmac* p_gmac, uint8_t uc_phy_address,
\r
1077 uint8_t uc_address, uint32_t ul_value);
\r
1078 void gmac_dev_init(Gmac* p_gmac, gmac_device_t* p_gmac_dev,
\r
1079 gmac_options_t* p_opt);
\r
1080 uint32_t gmac_dev_read(gmac_device_t* p_gmac_dev, uint8_t* p_frame,
\r
1081 uint32_t ul_frame_size, uint32_t* p_rcv_size);
\r
1082 uint32_t gmac_dev_write(gmac_device_t* p_gmac_dev, void *p_buffer,
\r
1083 uint32_t ul_size, gmac_dev_tx_cb_t func_tx_cb);
\r
1084 uint32_t gmac_dev_get_tx_load(gmac_device_t* p_gmac_dev);
\r
1085 void gmac_dev_set_rx_callback(gmac_device_t* p_gmac_dev,
\r
1086 gmac_dev_rx_cb_t func_rx_cb);
\r
1087 uint8_t gmac_dev_set_tx_wakeup_callback(gmac_device_t* p_gmac_dev,
\r
1088 gmac_dev_wakeup_cb_t func_wakeup, uint8_t uc_threshold);
\r
1089 void gmac_dev_reset(gmac_device_t* p_gmac_dev);
\r
1090 void gmac_handler(gmac_device_t* p_gmac_dev);
\r
1094 #ifdef __cplusplus
\r
1101 * \page gmac_quickstart Quickstart guide for GMAC driver.
\r
1103 * This is the quickstart guide for the \ref gmac_group "Ethernet MAC",
\r
1104 * with step-by-step instructions on how to configure and use the driver in a
\r
1105 * selection of use cases.
\r
1107 * The use cases contain several code fragments. The code fragments in the
\r
1108 * steps for setup can be copied into a custom initialization function, while
\r
1109 * the steps for usage can be copied into, e.g., the main application function.
\r
1111 * \section gmac_basic_use_case Basic use case
\r
1112 * In the basic use case, the GMAC driver are configured for:
\r
1113 * - PHY component KSZ8051MNL is used
\r
1114 * - GMAC uses MII mode
\r
1115 * - The number of receive buffer is 16
\r
1116 * - The number of transfer buffer is 8
\r
1117 * - MAC address is set to 00-04-25-1c-a0-02
\r
1118 * - IP address is set to 192.168.0.2
\r
1119 * - IP address is set to 192.168.0.2
\r
1120 * - Gateway is set to 192.168.0.1
\r
1121 * - Network mask is 255.255.255.0
\r
1122 * - PHY operation max retry count is 1000000
\r
1123 * - GMAC is configured to not support copy all frame and support broadcast
\r
1124 * - The data will be read from the ethernet
\r
1126 * \section gmac_basic_use_case_setup Setup steps
\r
1128 * \subsection gmac_basic_use_case_setup_prereq Prerequisites
\r
1129 * -# \ref sysclk_group "System Clock Management (sysclock)"
\r
1130 * -# \ref pmc_group "Power Management Controller (pmc)"
\r
1131 * -# \ref ksz8051mnl_ethernet_phy_group "PHY component (KSZ8051MNL)"
\r
1133 * \subsection gmac_basic_use_case_setup_code Example code
\r
1134 * Content of conf_eth.h
\r
1136 * #define GMAC_RX_BUFFERS 16
\r
1137 * #define GMAC_TX_BUFFERS 8
\r
1138 * #define MAC_PHY_RETRY_MAX 1000000
\r
1139 * #define ETHERNET_CONF_ETHADDR0 0x00
\r
1140 * #define ETHERNET_CONF_ETHADDR0 0x00
\r
1141 * #define ETHERNET_CONF_ETHADDR1 0x04
\r
1142 * #define ETHERNET_CONF_ETHADDR2 0x25
\r
1143 * #define ETHERNET_CONF_ETHADDR3 0x1C
\r
1144 * #define ETHERNET_CONF_ETHADDR4 0xA0
\r
1145 * #define ETHERNET_CONF_ETHADDR5 0x02
\r
1146 * #define ETHERNET_CONF_IPADDR0 192
\r
1147 * #define ETHERNET_CONF_IPADDR1 168
\r
1148 * #define ETHERNET_CONF_IPADDR2 0
\r
1149 * #define ETHERNET_CONF_IPADDR3 2
\r
1150 * #define ETHERNET_CONF_GATEWAY_ADDR0 192
\r
1151 * #define ETHERNET_CONF_GATEWAY_ADDR1 168
\r
1152 * #define ETHERNET_CONF_GATEWAY_ADDR2 0
\r
1153 * #define ETHERNET_CONF_GATEWAY_ADDR3 1
\r
1154 * #define ETHERNET_CONF_NET_MASK0 255
\r
1155 * #define ETHERNET_CONF_NET_MASK1 255
\r
1156 * #define ETHERNET_CONF_NET_MASK2 255
\r
1157 * #define ETHERNET_CONF_NET_MASK3 0
\r
1158 * #define ETH_PHY_MODE ETH_PHY_MODE
\r
1161 * A specific gmac device and the receive data buffer must be defined; another ul_frm_size should be defined
\r
1162 * to trace the actual size of the data received.
\r
1164 * static gmac_device_t gs_gmac_dev;
\r
1165 * static volatile uint8_t gs_uc_eth_buffer[GMAC_FRAME_LENTGH_MAX];
\r
1167 * uint32_t ul_frm_size;
\r
1170 * Add to application C-file:
\r
1172 * void gmac_init(void)
\r
1178 * pmc_enable_periph_clk(ID_GMAC);
\r
1180 * gmac_option.uc_copy_all_frame = 0;
\r
1181 * gmac_option.uc_no_boardcast = 0;
\r
1182 * memcpy(gmac_option.uc_mac_addr, gs_uc_mac_address, sizeof(gs_uc_mac_address));
\r
1183 * gs_gmac_dev.p_hw = GMAC;
\r
1185 * gmac_dev_init(GMAC, &gs_gmac_dev, &gmac_option);
\r
1187 * NVIC_EnableIRQ(GMAC_IRQn);
\r
1189 * ethernet_phy_init(GMAC, BOARD_GMAC_PHY_ADDR, sysclk_get_cpu_hz());
\r
1191 * ethernet_phy_auto_negotiate(GMAC, BOARD_GMAC_PHY_ADDR);
\r
1193 * ethernet_phy_set_link(GMAC, BOARD_GMAC_PHY_ADDR, 1);
\r
1196 * \subsection gmac_basic_use_case_setup_flow Workflow
\r
1197 * - Ensure that conf_eth.h is present and contains the
\r
1198 * following configuration symbol. This configuration file is used
\r
1199 * by the driver and should not be included by the application.
\r
1200 * -# Define the receiving buffer size used in the internal GMAC driver.
\r
1201 * The buffer size used for RX is GMAC_RX_BUFFERS * 128.
\r
1202 * If it was supposed receiving a large number of frame, the
\r
1203 * GMAC_RX_BUFFERS should be set higher. E.g., the application wants to accept
\r
1204 * a ping echo test of 2048, the GMAC_RX_BUFFERS should be set at least
\r
1205 * (2048/128)=16, and as there are additional frames coming, a preferred
\r
1206 * number is 24 depending on a normal Ethernet throughput.
\r
1208 * #define GMAC_RX_BUFFERS 16
\r
1210 * -# Define the transmitting buffer size used in the internal GMAC driver.
\r
1211 * The buffer size used for TX is GMAC_TX_BUFFERS * 1518.
\r
1213 * #define GMAC_TX_BUFFERS 8
\r
1215 * -# Define maximum retry time for a PHY read/write operation.
\r
1217 * #define MAC_PHY_RETRY_MAX 1000000
\r
1219 * -# Define the MAC address. 00:04:25:1C:A0:02 is the address reserved
\r
1220 * for ATMEL, application should always change this address to its' own.
\r
1222 * #define ETHERNET_CONF_ETHADDR0 0x00
\r
1223 * #define ETHERNET_CONF_ETHADDR1 0x04
\r
1224 * #define ETHERNET_CONF_ETHADDR2 0x25
\r
1225 * #define ETHERNET_CONF_ETHADDR3 0x1C
\r
1226 * #define ETHERNET_CONF_ETHADDR4 0xA0
\r
1227 * #define ETHERNET_CONF_ETHADDR5 0x02
\r
1229 * -# Define the IP address configration used in the application. When DHCP
\r
1230 * is enabled, this configuration is not effected.
\r
1232 * #define ETHERNET_CONF_IPADDR0 192
\r
1233 * #define ETHERNET_CONF_IPADDR1 168
\r
1234 * #define ETHERNET_CONF_IPADDR2 0
\r
1235 * #define ETHERNET_CONF_IPADDR3 2
\r
1236 * #define ETHERNET_CONF_GATEWAY_ADDR0 192
\r
1237 * #define ETHERNET_CONF_GATEWAY_ADDR1 168
\r
1238 * #define ETHERNET_CONF_GATEWAY_ADDR2 0
\r
1239 * #define ETHERNET_CONF_GATEWAY_ADDR3 1
\r
1240 * #define ETHERNET_CONF_NET_MASK0 255
\r
1241 * #define ETHERNET_CONF_NET_MASK1 255
\r
1242 * #define ETHERNET_CONF_NET_MASK2 255
\r
1243 * #define ETHERNET_CONF_NET_MASK3 0
\r
1245 * -# Configure the PHY maintainance interface.
\r
1247 * #define ETH_PHY_MODE GMAC_PHY_MII
\r
1249 * -# Enable the system clock:
\r
1250 * - \code sysclk_init(); \endcode
\r
1251 * -# Enable PIO configurations for GMAC:
\r
1252 * - \code board_init(); \endcode
\r
1253 * -# Enable PMC clock for GMAC:
\r
1254 * - \code pmc_enable_periph_clk(ID_GMAC); \endcode
\r
1255 * -# Set the GMAC options; it's set to copy all frame and support broadcast:
\r
1257 * gmac_option.uc_copy_all_frame = 0;
\r
1258 * gmac_option.uc_no_boardcast = 0;
\r
1259 * memcpy(gmac_option.uc_mac_addr, gs_uc_mac_address, sizeof(gs_uc_mac_address));
\r
1260 * gs_gmac_dev.p_hw = GMAC;
\r
1262 * -# Initialize GMAC device with the filled option:
\r
1264 * gmac_dev_init(GMAC, &gs_gmac_dev, &gmac_option);
\r
1266 * -# Enable the interrupt service for GMAC:
\r
1268 * NVIC_EnableIRQ(GMAC_IRQn);
\r
1270 * -# Initialize the PHY component:
\r
1272 * ethernet_phy_init(GMAC, BOARD_GMAC_PHY_ADDR, sysclk_get_cpu_hz());
\r
1274 * -# The link will be established based on auto negotiation.
\r
1276 * ethernet_phy_auto_negotiate(GMAC, BOARD_GMAC_PHY_ADDR);
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1278 * -# Establish the ethernet link; the network can be worked from now on:
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1280 * ethernet_phy_set_link(GMAC, BOARD_GMAC_PHY_ADDR, 1);
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1283 * \section gmac_basic_use_case_usage Usage steps
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1284 * \subsection gmac_basic_use_case_usage_code Example code
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1285 * Add to, e.g., main loop in application C-file:
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1287 * gmac_dev_read(&gs_gmac_dev, (uint8_t *) gs_uc_eth_buffer, sizeof(gs_uc_eth_buffer), &ul_frm_size));
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1290 * \subsection gmac_basic_use_case_usage_flow Workflow
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1291 * -# Start reading the data from the ethernet:
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1292 * - \code gmac_dev_read(&gs_gmac_dev, (uint8_t *) gs_uc_eth_buffer, sizeof(gs_uc_eth_buffer), &ul_frm_size)); \endcode
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1295 # define GMAC_STATS 0
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1297 #if( GMAC_STATS != 0 )
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1299 /* Here below some code to study the types and
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1300 frequencies of GMAC interrupts. */
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1301 #define GMAC_IDX_RXUBR 0
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1302 #define GMAC_IDX_TUR 1
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1303 #define GMAC_IDX_RLEX 2
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1304 #define GMAC_IDX_TFC 3
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1305 #define GMAC_IDX_RCOMP 4
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1306 #define GMAC_IDX_TCOMP 5
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1307 #define GMAC_IDX_ROVR 6
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1308 #define GMAC_IDX_HRESP 7
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1309 #define GMAC_IDX_PFNZ 8
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1310 #define GMAC_IDX_PTZ 9
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1312 struct SGmacStats {
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1313 unsigned recvCount;
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1314 unsigned rovrCount;
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1315 unsigned bnaCount;
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1316 unsigned sendCount;
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1317 unsigned sovrCount;
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1318 unsigned incompCount;
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1319 unsigned truncCount;
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1321 unsigned intStatus[10];
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1323 extern struct SGmacStats gmacStats;
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1331 #define MK_PAIR( NAME ) #NAME, GMAC_IER_##NAME, GMAC_IDX_##NAME
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1332 static const struct SIntPair intPairs[] = {
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1333 { MK_PAIR( RXUBR ) }, /* Enable receive used bit read interrupt. */
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1334 { MK_PAIR( TUR ) }, /* Enable transmit underrun interrupt. */
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1335 { MK_PAIR( RLEX ) }, /* Enable retry limit exceeded interrupt. */
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1336 { MK_PAIR( TFC ) }, /* Enable transmit buffers exhausted in mid-frame interrupt. */
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1337 { MK_PAIR( RCOMP ) }, /* Receive complete */
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1338 { MK_PAIR( TCOMP ) }, /* Enable transmit complete interrupt. */
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1339 { MK_PAIR( ROVR ) }, /* Enable receive overrun interrupt. */
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1340 { MK_PAIR( HRESP ) }, /* Enable Hresp not OK interrupt. */
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1341 { MK_PAIR( PFNZ ) }, /* Enable pause frame received interrupt. */
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1342 { MK_PAIR( PTZ ) } /* Enable pause time zero interrupt. */
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1345 void gmac_show_irq_counts ();
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1349 #endif /* GMAC_H_INCLUDED */
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