2 * FreeRTOS+TCP V2.0.3
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://aws.amazon.com/freertos
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23 * http://www.FreeRTOS.org
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27 /* Standard includes. */
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32 /* FreeRTOS includes. */
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33 #include "FreeRTOS.h"
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38 /* FreeRTOS+TCP includes. */
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39 #include "FreeRTOS_IP.h"
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40 #include "FreeRTOS_Sockets.h"
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41 #include "FreeRTOS_IP_Private.h"
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42 #include "NetworkBufferManagement.h"
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43 #include "NetworkInterface.h"
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45 /* LPCOpen includes. */
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47 #include "lpc_phy.h"
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49 /* The size of the stack allocated to the task that handles Rx packets. */
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50 #define nwRX_TASK_STACK_SIZE 140
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52 #ifndef PHY_LS_HIGH_CHECK_TIME_MS
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53 /* Check if the LinkSStatus in the PHY is still high after 15 seconds of not
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54 receiving packets. */
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55 #define PHY_LS_HIGH_CHECK_TIME_MS 15000
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58 #ifndef PHY_LS_LOW_CHECK_TIME_MS
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59 /* Check if the LinkSStatus in the PHY is still low every second. */
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60 #define PHY_LS_LOW_CHECK_TIME_MS 1000
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63 #ifndef configUSE_RMII
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64 #define configUSE_RMII 1
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67 #ifndef configNUM_RX_DESCRIPTORS
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68 #error please define configNUM_RX_DESCRIPTORS in your FreeRTOSIPConfig.h
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71 #ifndef configNUM_TX_DESCRIPTORS
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72 #error please define configNUM_TX_DESCRIPTORS in your FreeRTOSIPConfig.h
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75 #ifndef NETWORK_IRQHandler
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76 #error NETWORK_IRQHandler must be defined to the name of the function that is installed in the interrupt vector table to handle Ethernet interrupts.
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79 #if !defined( MAC_FF_HMC )
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80 /* Hash for multicast. */
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81 #define MAC_FF_HMC ( 1UL << 2UL )
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84 #ifndef iptraceEMAC_TASK_STARTING
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85 #define iptraceEMAC_TASK_STARTING() do { } while( 0 )
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88 /* Define the bits of .STATUS that indicate a reception error. */
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89 #define nwRX_STATUS_ERROR_BITS \
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90 ( RDES_CE /* CRC Error */ | \
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91 RDES_RE /* Receive Error */ | \
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92 RDES_DE /* Descriptor Error */ | \
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93 RDES_RWT /* Receive Watchdog Timeout */ | \
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94 RDES_LC /* Late Collision */ | \
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95 RDES_OE /* Overflow Error */ | \
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96 RDES_SAF /* Source Address Filter Fail */ | \
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97 RDES_AFM /* Destination Address Filter Fail */ | \
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98 RDES_LE /* Length Error */ )
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100 /* Define the EMAC status bits that should trigger an interrupt. */
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101 #define nwDMA_INTERRUPT_MASK \
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102 ( DMA_IE_TIE /* Transmit interrupt enable */ | \
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103 DMA_IE_TSE /* Transmit stopped enable */ | \
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104 DMA_IE_OVE /* Overflow interrupt enable */ | \
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105 DMA_IE_RIE /* Receive interrupt enable */ | \
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106 DMA_IE_NIE /* Normal interrupt summary enable */ | \
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107 DMA_IE_AIE /* Abnormal interrupt summary enable */ | \
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108 DMA_IE_RUE /* Receive buffer unavailable enable */ | \
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109 DMA_IE_UNE /* Underflow interrupt enable. */ | \
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110 DMA_IE_TJE /* Transmit jabber timeout enable */ | \
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111 DMA_IE_RSE /* Received stopped enable */ | \
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112 DMA_IE_RWE /* Receive watchdog timeout enable */ | \
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113 DMA_IE_FBE )/* Fatal bus error enable */
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115 /* Interrupt events to process. Currently only the RX/TX events are processed
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116 although code for other events is included to allow for possible future
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118 #define EMAC_IF_RX_EVENT 1UL
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119 #define EMAC_IF_TX_EVENT 2UL
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120 #define EMAC_IF_ERR_EVENT 4UL
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121 #define EMAC_IF_ALL_EVENT ( EMAC_IF_RX_EVENT | EMAC_IF_TX_EVENT | EMAC_IF_ERR_EVENT )
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123 /* If ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES is set to 1, then the Ethernet
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124 driver will filter incoming packets and only pass the stack those packets it
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125 considers need processing. */
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126 #if( ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES == 0 )
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127 #define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eProcessBuffer
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129 #define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eConsiderFrameForProcessing( ( pucEthernetBuffer ) )
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132 #if( ipconfigZERO_COPY_RX_DRIVER == 0 ) || ( ipconfigZERO_COPY_TX_DRIVER == 0 )
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133 #warning It is adviced to enable both macros
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136 #ifndef configPLACE_IN_SECTION_RAM
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137 #define configPLACE_IN_SECTION_RAM
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139 #define configPLACE_IN_SECTION_RAM __attribute__ ((section(".ramfunc")))
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143 /*-----------------------------------------------------------*/
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146 * Delay function passed into the library. The implementation uses FreeRTOS
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147 * calls so the scheduler must be started before the driver can be used.
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149 static void prvDelay( uint32_t ulMilliSeconds );
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152 * Initialises the Tx and Rx descriptors respectively.
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154 static void prvSetupTxDescriptors( void );
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155 static void prvSetupRxDescriptors( void );
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158 * A task that processes received frames.
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160 static void prvEMACHandlerTask( void *pvParameters );
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163 * Sets up the MAC with the results of an auto-negotiation.
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165 static BaseType_t prvSetLinkSpeed( void );
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168 * Generates a CRC for a MAC address that is then used to generate a hash index.
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170 static uint32_t prvGenerateCRC32( const uint8_t *ucAddress );
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173 * Generates a hash index when setting a filter to permit a MAC address.
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175 static uint32_t prvGetHashIndex( const uint8_t *ucAddress );
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178 * Update the hash table to allow a MAC address.
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180 static void prvAddMACAddress( const uint8_t* ucMacAddress );
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183 * Sometimes the DMA will report received data as being longer than the actual
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184 * received from length. This function checks the reported length and corrects
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187 static void prvRemoveTrailingBytes( NetworkBufferDescriptor_t *pxDescriptor );
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189 /*-----------------------------------------------------------*/
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191 /* Bit map of outstanding ETH interrupt events for processing. Currently only
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192 the Rx and Tx interrupt is handled, although code is included for other events
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193 to enable future expansion. */
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194 static volatile uint32_t ulISREvents;
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196 /* A copy of PHY register 1: 'PHY_REG_01_BMSR' */
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197 static uint32_t ulPHYLinkStatus = 0;
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199 /* Tx descriptors and index. */
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200 static ENET_ENHTXDESC_T xDMATxDescriptors[ configNUM_TX_DESCRIPTORS ];
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202 /* ulNextFreeTxDescriptor is declared volatile, because it is accessed from
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203 to different tasks. */
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204 static volatile uint32_t ulNextFreeTxDescriptor;
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205 static uint32_t ulTxDescriptorToClear;
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207 /* Rx descriptors and index. */
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208 static ENET_ENHRXDESC_T xDMARxDescriptors[ configNUM_RX_DESCRIPTORS ];
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209 static uint32_t ulNextRxDescriptorToProcess;
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211 /* Must be defined externally - the demo applications define this in main.c. */
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212 extern uint8_t ucMACAddress[ 6 ];
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214 /* The handle of the task that processes Rx packets. The handle is required so
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215 the task can be notified when new packets arrive. */
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216 static TaskHandle_t xRxHanderTask = NULL;
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218 #if( ipconfigUSE_LLMNR == 1 )
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219 static const uint8_t xLLMNR_MACAddress[] = { '\x01', '\x00', '\x5E', '\x00', '\x00', '\xFC' };
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220 #endif /* ipconfigUSE_LLMNR == 1 */
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222 /* xTXDescriptorSemaphore is a counting semaphore with
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223 a maximum count of ETH_TXBUFNB, which is the number of
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224 DMA TX descriptors. */
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225 static SemaphoreHandle_t xTXDescriptorSemaphore = NULL;
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227 /*-----------------------------------------------------------*/
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230 BaseType_t xNetworkInterfaceInitialise( void )
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232 BaseType_t xReturn = pdPASS;
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233 static BaseType_t xHasInitialised = pdFALSE;
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235 if( xHasInitialised == pdFALSE )
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237 xHasInitialised = pdTRUE;
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239 /* The interrupt will be turned on when a link is established. */
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240 NVIC_DisableIRQ( ETHERNET_IRQn );
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242 /* Disable receive and transmit DMA processes. */
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243 LPC_ETHERNET->DMA_OP_MODE &= ~( DMA_OM_ST | DMA_OM_SR );
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245 /* Disable packet reception. */
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246 LPC_ETHERNET->MAC_CONFIG &= ~( MAC_CFG_RE | MAC_CFG_TE );
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248 /* Call the LPCOpen function to initialise the hardware. */
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249 Chip_ENET_Init( LPC_ETHERNET );
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251 /* Save MAC address. */
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252 Chip_ENET_SetADDR( LPC_ETHERNET, ucMACAddress );
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254 /* Clear all MAC address hash entries. */
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255 LPC_ETHERNET->MAC_HASHTABLE_HIGH = 0;
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256 LPC_ETHERNET->MAC_HASHTABLE_LOW = 0;
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258 #if( ipconfigUSE_LLMNR == 1 )
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260 prvAddMACAddress( xLLMNR_MACAddress );
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262 #endif /* ipconfigUSE_LLMNR == 1 */
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264 /* Promiscuous flag (PR) and Receive All flag (RA) set to zero. The
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265 registers MAC_HASHTABLE_[LOW|HIGH] will be loaded to allow certain
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266 multi-cast addresses. */
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267 LPC_ETHERNET->MAC_FRAME_FILTER = MAC_FF_HMC;
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269 #if( configUSE_RMII == 1 )
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271 if( lpc_phy_init( pdTRUE, prvDelay ) != SUCCESS )
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278 #warning This path has not been tested.
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279 if( lpc_phy_init( pdFALSE, prvDelay ) != SUCCESS )
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286 if( xReturn == pdPASS )
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288 if( xTXDescriptorSemaphore == NULL )
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290 /* Create a counting semaphore, with a value of 'configNUM_TX_DESCRIPTORS'
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291 and a maximum of 'configNUM_TX_DESCRIPTORS'. */
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292 xTXDescriptorSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) configNUM_TX_DESCRIPTORS, ( UBaseType_t ) configNUM_TX_DESCRIPTORS );
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293 configASSERT( xTXDescriptorSemaphore );
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296 /* Enable MAC interrupts. */
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297 LPC_ETHERNET->DMA_INT_EN = nwDMA_INTERRUPT_MASK;
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299 /* Auto-negotiate was already started. Wait for it to complete. */
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300 xReturn = prvSetLinkSpeed();
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302 if( xReturn == pdPASS )
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304 /* Initialise the descriptors. */
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305 prvSetupTxDescriptors();
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306 prvSetupRxDescriptors();
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308 /* Clear all interrupts. */
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309 LPC_ETHERNET->DMA_STAT = DMA_ST_ALL;
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311 /* Enable receive and transmit DMA processes. */
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312 LPC_ETHERNET->DMA_OP_MODE |= DMA_OM_ST | DMA_OM_SR;
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314 /* Set Receiver / Transmitter Enable. */
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315 LPC_ETHERNET->MAC_CONFIG |= MAC_CFG_RE | MAC_CFG_TE;
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317 /* Start receive polling. */
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318 LPC_ETHERNET->DMA_REC_POLL_DEMAND = 1;
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320 /* Enable interrupts in the NVIC. */
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321 NVIC_SetPriority( ETHERNET_IRQn, configMAC_INTERRUPT_PRIORITY );
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322 NVIC_EnableIRQ( ETHERNET_IRQn );
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324 /* Guard against the task being created more than once and the
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325 descriptors being initialised more than once. */
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326 if( xRxHanderTask == NULL )
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328 xReturn = xTaskCreate( prvEMACHandlerTask, "EMAC", nwRX_TASK_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, &xRxHanderTask );
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329 configASSERT( xReturn );
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334 /* Once prvEMACHandlerTask() has started, the variable
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335 'ulPHYLinkStatus' will be updated by that task.
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336 The IP-task will keep on calling this function untill
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337 it finally returns pdPASS.
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338 Only then can the DHCP-procedure start (if configured). */
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339 if( ( ulPHYLinkStatus & PHY_LINK_CONNECTED ) != 0 )
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350 /*-----------------------------------------------------------*/
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352 #define niBUFFER_1_PACKET_SIZE 1536
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354 static __attribute__ ((section("._ramAHB32"))) uint8_t ucNetworkPackets[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS * niBUFFER_1_PACKET_SIZE ] __attribute__ ( ( aligned( 32 ) ) );
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356 void vNetworkInterfaceAllocateRAMToBuffers( NetworkBufferDescriptor_t pxNetworkBuffers[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ] )
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359 uint8_t *ucRAMBuffer = ucNetworkPackets;
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362 for( ul = 0; ul < ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS; ul++ )
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364 pxNetworkBuffers[ ul ].pucEthernetBuffer = ucRAMBuffer + ipBUFFER_PADDING;
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365 *( ( unsigned * ) ucRAMBuffer ) = ( unsigned ) ( &( pxNetworkBuffers[ ul ] ) );
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366 ucRAMBuffer += niBUFFER_1_PACKET_SIZE;
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369 /*-----------------------------------------------------------*/
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371 configPLACE_IN_SECTION_RAM
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372 static void vClearTXBuffers()
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374 uint32_t ulLastDescriptor = ulNextFreeTxDescriptor;
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375 size_t uxCount = ( ( size_t ) configNUM_TX_DESCRIPTORS ) - uxSemaphoreGetCount( xTXDescriptorSemaphore );
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376 #if( ipconfigZERO_COPY_TX_DRIVER != 0 )
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377 NetworkBufferDescriptor_t *pxNetworkBuffer;
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378 uint8_t *ucPayLoad;
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381 /* This function is called after a TX-completion interrupt.
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382 It will release each Network Buffer used in xNetworkInterfaceOutput().
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383 'uxCount' represents the number of descriptors given to DMA for transmission.
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384 After sending a packet, the DMA will clear the 'TDES_OWN' bit. */
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385 while( ( uxCount > ( size_t ) 0u ) && ( ( xDMATxDescriptors[ ulTxDescriptorToClear ].CTRLSTAT & TDES_OWN ) == 0 ) )
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387 if( ( ulTxDescriptorToClear == ulLastDescriptor ) && ( uxCount != ( size_t ) configNUM_TX_DESCRIPTORS ) )
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393 #if( ipconfigZERO_COPY_TX_DRIVER != 0 )
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395 ucPayLoad = ( uint8_t * )xDMATxDescriptors[ ulTxDescriptorToClear ].B1ADD;
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396 if( ucPayLoad != NULL )
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398 /* B1ADD points to a pucEthernetBuffer of a Network Buffer descriptor. */
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399 pxNetworkBuffer = pxPacketBuffer_to_NetworkBuffer( ucPayLoad );
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401 configASSERT( pxNetworkBuffer != NULL );
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403 vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ) ;
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404 xDMATxDescriptors[ ulTxDescriptorToClear ].B1ADD = ( uint32_t )0u;
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407 #endif /* ipconfigZERO_COPY_TX_DRIVER */
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409 /* Move onto the next descriptor, wrapping if necessary. */
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410 ulTxDescriptorToClear++;
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411 if( ulTxDescriptorToClear >= configNUM_TX_DESCRIPTORS )
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413 ulTxDescriptorToClear = 0;
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417 /* Tell the counting semaphore that one more TX descriptor is available. */
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418 xSemaphoreGive( xTXDescriptorSemaphore );
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422 /*-----------------------------------------------------------*/
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424 configPLACE_IN_SECTION_RAM
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425 BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxDescriptor, BaseType_t bReleaseAfterSend )
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427 BaseType_t xReturn = pdFAIL;
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428 const TickType_t xBlockTimeTicks = pdMS_TO_TICKS( 50 );
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430 /* Attempt to obtain access to a Tx descriptor. */
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433 if( xTXDescriptorSemaphore == NULL )
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437 if( xSemaphoreTake( xTXDescriptorSemaphore, xBlockTimeTicks ) != pdPASS )
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439 /* Time-out waiting for a free TX descriptor. */
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443 /* If the descriptor is still owned by the DMA it can't be used. */
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444 if( ( xDMATxDescriptors[ ulNextFreeTxDescriptor ].CTRLSTAT & TDES_OWN ) != 0 )
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446 /* The semaphore was taken, the TX DMA-descriptor is still not available.
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447 Actually that should not occur, the 'TDES_OWN' was already confirmed low in vClearTXBuffers(). */
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448 xSemaphoreGive( xTXDescriptorSemaphore );
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452 #if( ipconfigZERO_COPY_TX_DRIVER != 0 )
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454 /* bReleaseAfterSend should always be set when using the zero
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456 configASSERT( bReleaseAfterSend != pdFALSE );
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458 /* The DMA's descriptor to point directly to the data in the
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459 network buffer descriptor. The data is not copied. */
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460 xDMATxDescriptors[ ulNextFreeTxDescriptor ].B1ADD = ( uint32_t ) pxDescriptor->pucEthernetBuffer;
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462 /* The DMA descriptor will 'own' this Network Buffer,
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463 until it has been sent. So don't release it now. */
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464 bReleaseAfterSend = pdFALSE;
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468 /* The data is copied from the network buffer descriptor into
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469 the DMA's descriptor. */
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470 memcpy( ( void * ) xDMATxDescriptors[ ulNextFreeTxDescriptor ].B1ADD, ( void * ) pxDescriptor->pucEthernetBuffer, pxDescriptor->xDataLength );
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474 xDMATxDescriptors[ ulNextFreeTxDescriptor ].BSIZE = ( uint32_t ) TDES_ENH_BS1( pxDescriptor->xDataLength );
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476 /* This descriptor is given back to the DMA. */
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477 xDMATxDescriptors[ ulNextFreeTxDescriptor ].CTRLSTAT |= TDES_OWN;
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479 /* Ensure the DMA is polling Tx descriptors. */
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480 LPC_ETHERNET->DMA_TRANS_POLL_DEMAND = 1;
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482 iptraceNETWORK_INTERFACE_TRANSMIT();
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484 /* Move onto the next descriptor, wrapping if necessary. */
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485 ulNextFreeTxDescriptor++;
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486 if( ulNextFreeTxDescriptor >= configNUM_TX_DESCRIPTORS )
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488 ulNextFreeTxDescriptor = 0;
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491 /* The Tx has been initiated. */
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496 /* The buffer has been sent so can be released. */
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497 if( bReleaseAfterSend != pdFALSE )
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499 vReleaseNetworkBufferAndDescriptor( pxDescriptor );
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504 /*-----------------------------------------------------------*/
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506 static void prvDelay( uint32_t ulMilliSeconds )
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508 /* Ensure the scheduler was started before attempting to use the scheduler to
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510 configASSERT( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING );
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512 vTaskDelay( pdMS_TO_TICKS( ulMilliSeconds ) );
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514 /*-----------------------------------------------------------*/
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516 static void prvSetupTxDescriptors( void )
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520 /* Start with Tx descriptors clear. */
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521 memset( ( void * ) xDMATxDescriptors, 0, sizeof( xDMATxDescriptors ) );
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523 /* Index to the next Tx descriptor to use. */
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524 ulNextFreeTxDescriptor = 0ul;
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526 /* Index to the next Tx descriptor to clear ( after transmission ). */
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527 ulTxDescriptorToClear = 0ul;
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529 for( x = 0; x < configNUM_TX_DESCRIPTORS; x++ )
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531 #if( ipconfigZERO_COPY_TX_DRIVER != 0 )
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533 /* Nothing to do, B1ADD will be set when data is ready to transmit.
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534 Currently the memset above will have set it to NULL. */
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538 /* Allocate a buffer to the Tx descriptor. This is the most basic
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539 way of creating a driver as the data is then copied into the
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541 xDMATxDescriptors[ x ].B1ADD = ( uint32_t ) pvPortMalloc( ipTOTAL_ETHERNET_FRAME_SIZE );
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543 /* Use an assert to check the allocation as +TCP applications will
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544 often not use a malloc() failed hook as the TCP stack will recover
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545 from allocation failures. */
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546 configASSERT( xDMATxDescriptors[ x ].B1ADD );
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550 /* Buffers hold an entire frame so all buffers are both the start and
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552 /* TDES_ENH_TCH Second Address Chained. */
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553 /* TDES_ENH_CIC(n) Checksum Insertion Control, tried but it does not work for the LPC18xx... */
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554 /* TDES_ENH_FS First Segment. */
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555 /* TDES_ENH_LS Last Segment. */
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556 /* TDES_ENH_IC Interrupt on Completion. */
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557 xDMATxDescriptors[ x ].CTRLSTAT = TDES_ENH_TCH | TDES_ENH_CIC( 3 ) | TDES_ENH_FS | TDES_ENH_LS | TDES_ENH_IC;
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558 xDMATxDescriptors[ x ].B2ADD = ( uint32_t ) &xDMATxDescriptors[ x + 1 ];
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561 xDMATxDescriptors[ configNUM_TX_DESCRIPTORS - 1 ].CTRLSTAT |= TDES_ENH_TER;
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562 xDMATxDescriptors[ configNUM_TX_DESCRIPTORS - 1 ].B2ADD = ( uint32_t ) &xDMATxDescriptors[ 0 ];
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564 /* Point the DMA to the base of the descriptor list. */
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565 LPC_ETHERNET->DMA_TRANS_DES_ADDR = ( uint32_t ) xDMATxDescriptors;
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567 /*-----------------------------------------------------------*/
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569 static void prvSetupRxDescriptors( void )
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572 #if( ipconfigZERO_COPY_RX_DRIVER != 0 )
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573 NetworkBufferDescriptor_t *pxNetworkBuffer;
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576 /* Index to the next Rx descriptor to use. */
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577 ulNextRxDescriptorToProcess = 0;
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579 /* Clear RX descriptor list. */
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580 memset( ( void * ) xDMARxDescriptors, 0, sizeof( xDMARxDescriptors ) );
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582 for( x = 0; x < configNUM_RX_DESCRIPTORS; x++ )
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584 /* Allocate a buffer of the largest possible frame size as it is not
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585 known what size received frames will be. */
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587 #if( ipconfigZERO_COPY_RX_DRIVER != 0 )
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589 pxNetworkBuffer = pxGetNetworkBufferWithDescriptor( ipTOTAL_ETHERNET_FRAME_SIZE, 0 );
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591 /* During start-up there should be enough Network Buffers available,
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592 so it is safe to use configASSERT().
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593 In case this assert fails, please check: configNUM_RX_DESCRIPTORS,
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594 ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS, and in case BufferAllocation_2.c
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595 is included, check the amount of available heap. */
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596 configASSERT( pxNetworkBuffer != NULL );
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598 /* Pass the actual buffer to DMA. */
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599 xDMARxDescriptors[ x ].B1ADD = ( uint32_t ) pxNetworkBuffer->pucEthernetBuffer;
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603 /* All DMA descriptors are populated with permanent memory blocks.
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604 Their contents will be copy to Network Buffers. */
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605 xDMARxDescriptors[ x ].B1ADD = ( uint32_t ) pvPortMalloc( ipTOTAL_ETHERNET_FRAME_SIZE );
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607 #endif /* ipconfigZERO_COPY_RX_DRIVER */
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609 /* Use an assert to check the allocation as +TCP applications will often
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610 not use a malloc failed hook as the TCP stack will recover from
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611 allocation failures. */
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612 configASSERT( xDMARxDescriptors[ x ].B1ADD );
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614 xDMARxDescriptors[ x ].B2ADD = ( uint32_t ) &( xDMARxDescriptors[ x + 1 ] );
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615 xDMARxDescriptors[ x ].CTRL = ( uint32_t ) RDES_ENH_BS1( ipTOTAL_ETHERNET_FRAME_SIZE ) | RDES_ENH_RCH;
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617 /* The descriptor is available for use by the DMA. */
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618 xDMARxDescriptors[ x ].STATUS = RDES_OWN;
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621 /* RDES_ENH_RER Receive End of Ring. */
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622 xDMARxDescriptors[ ( configNUM_RX_DESCRIPTORS - 1 ) ].CTRL |= RDES_ENH_RER;
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623 xDMARxDescriptors[ configNUM_RX_DESCRIPTORS - 1 ].B2ADD = ( uint32_t ) &( xDMARxDescriptors[ 0 ] );
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625 /* Point the DMA to the base of the descriptor list. */
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626 LPC_ETHERNET->DMA_REC_DES_ADDR = ( uint32_t ) xDMARxDescriptors;
\r
628 /*-----------------------------------------------------------*/
\r
629 configPLACE_IN_SECTION_RAM
\r
630 static void prvRemoveTrailingBytes( NetworkBufferDescriptor_t *pxDescriptor )
\r
632 size_t xExpectedLength;
\r
633 IPPacket_t *pxIPPacket;
\r
635 pxIPPacket = ( IPPacket_t * ) pxDescriptor->pucEthernetBuffer;
\r
636 /* Look at the actual length of the packet, translate it to a host-endial notation. */
\r
637 xExpectedLength = sizeof( EthernetHeader_t ) + ( size_t ) FreeRTOS_htons( pxIPPacket->xIPHeader.usLength );
\r
639 if( xExpectedLength == ( pxDescriptor->xDataLength + 4 ) )
\r
641 pxDescriptor->xDataLength -= 4;
\r
645 if( pxDescriptor->xDataLength > xExpectedLength )
\r
647 pxDescriptor->xDataLength = ( size_t ) xExpectedLength;
\r
651 /*-----------------------------------------------------------*/
\r
652 configPLACE_IN_SECTION_RAM
\r
653 BaseType_t xGetPhyLinkStatus( void )
\r
655 BaseType_t xReturn;
\r
657 if( ( ulPHYLinkStatus & PHY_LINK_CONNECTED ) == 0 )
\r
668 /*-----------------------------------------------------------*/
\r
670 configPLACE_IN_SECTION_RAM
\r
671 static BaseType_t prvNetworkInterfaceInput()
\r
673 BaseType_t xResult = pdFALSE;
\r
675 eFrameProcessingResult_t eResult;
\r
676 const TickType_t xDescriptorWaitTime = pdMS_TO_TICKS( 250 );
\r
677 const UBaseType_t uxMinimumBuffersRemaining = 3UL;
\r
679 NetworkBufferDescriptor_t *pxDescriptor;
\r
680 #if( ipconfigZERO_COPY_RX_DRIVER != 0 )
\r
681 NetworkBufferDescriptor_t *pxNewDescriptor;
\r
682 #endif /* ipconfigZERO_COPY_RX_DRIVER */
\r
683 IPStackEvent_t xRxEvent = { eNetworkRxEvent, NULL };
\r
685 /* Process each descriptor that is not still in use by the DMA. */
\r
686 ulStatus = xDMARxDescriptors[ ulNextRxDescriptorToProcess ].STATUS;
\r
687 if( ( ulStatus & RDES_OWN ) == 0 )
\r
689 /* Check packet for errors */
\r
690 if( ( ulStatus & nwRX_STATUS_ERROR_BITS ) != 0 )
\r
692 /* There is some reception error. */
\r
693 /* Clear error bits. */
\r
694 ulStatus &= ~( ( uint32_t )nwRX_STATUS_ERROR_BITS );
\r
700 eResult = ipCONSIDER_FRAME_FOR_PROCESSING( ( const uint8_t * const ) ( xDMARxDescriptors[ ulNextRxDescriptorToProcess ].B1ADD ) );
\r
701 if( eResult == eProcessBuffer )
\r
703 if( ( ulPHYLinkStatus & PHY_LINK_CONNECTED ) == 0 )
\r
705 ulPHYLinkStatus |= PHY_LINK_CONNECTED;
\r
706 FreeRTOS_printf( ( "prvEMACHandlerTask: PHY LS now %d (message received)\n", ( ulPHYLinkStatus & PHY_LINK_CONNECTED ) != 0 ) );
\r
709 #if( ipconfigZERO_COPY_RX_DRIVER != 0 )
\r
710 if( uxGetNumberOfFreeNetworkBuffers() > uxMinimumBuffersRemaining )
\r
712 pxNewDescriptor = pxGetNetworkBufferWithDescriptor( ipTOTAL_ETHERNET_FRAME_SIZE, xDescriptorWaitTime );
\r
716 /* Too risky to allocate a new Network Buffer. */
\r
717 pxNewDescriptor = NULL;
\r
719 if( pxNewDescriptor != NULL )
\r
721 if( uxGetNumberOfFreeNetworkBuffers() > uxMinimumBuffersRemaining )
\r
722 #endif /* ipconfigZERO_COPY_RX_DRIVER */
\r
724 #if( ipconfigZERO_COPY_RX_DRIVER != 0 )
\r
725 const uint8_t *pucBuffer;
\r
728 /* Get the actual length. */
\r
729 usLength = RDES_FLMSK( ulStatus );
\r
731 #if( ipconfigZERO_COPY_RX_DRIVER != 0 )
\r
733 /* Replace the character buffer 'B1ADD'. */
\r
734 pucBuffer = ( const uint8_t * const ) ( xDMARxDescriptors[ ulNextRxDescriptorToProcess ].B1ADD );
\r
735 xDMARxDescriptors[ ulNextRxDescriptorToProcess ].B1ADD = ( uint32_t ) pxNewDescriptor->pucEthernetBuffer;
\r
737 /* 'B1ADD' contained the address of a 'pucEthernetBuffer' that
\r
738 belongs to a Network Buffer. Find the original Network Buffer. */
\r
739 pxDescriptor = pxPacketBuffer_to_NetworkBuffer( pucBuffer );
\r
740 /* This zero-copy driver makes sure that every 'xDMARxDescriptors' contains
\r
741 a reference to a Network Buffer at any time.
\r
742 In case it runs out of Network Buffers, a DMA buffer won't be replaced,
\r
743 and the received messages is dropped. */
\r
744 configASSERT( pxDescriptor != NULL );
\r
748 /* Create a buffer of exactly the required length. */
\r
749 pxDescriptor = pxGetNetworkBufferWithDescriptor( usLength, xDescriptorWaitTime );
\r
751 #endif /* ipconfigZERO_COPY_RX_DRIVER */
\r
753 if( pxDescriptor != NULL )
\r
755 pxDescriptor->xDataLength = ( size_t ) usLength;
\r
756 #if( ipconfigZERO_COPY_RX_DRIVER == 0 )
\r
758 /* Copy the data into the allocated buffer. */
\r
759 memcpy( ( void * ) pxDescriptor->pucEthernetBuffer, ( void * ) xDMARxDescriptors[ ulNextRxDescriptorToProcess ].B1ADD, usLength );
\r
761 #endif /* ipconfigZERO_COPY_RX_DRIVER */
\r
762 /* It is possible that more data was copied than
\r
763 actually makes up the frame. If this is the case
\r
764 adjust the length to remove any trailing bytes. */
\r
765 prvRemoveTrailingBytes( pxDescriptor );
\r
767 /* Pass the data to the TCP/IP task for processing. */
\r
768 xRxEvent.pvData = ( void * ) pxDescriptor;
\r
769 if( xSendEventStructToIPTask( &xRxEvent, xDescriptorWaitTime ) == pdFALSE )
\r
771 /* Could not send the descriptor into the TCP/IP
\r
772 stack, it must be released. */
\r
773 vReleaseNetworkBufferAndDescriptor( pxDescriptor );
\r
777 iptraceNETWORK_INTERFACE_RECEIVE();
\r
782 /* Got here because received data was sent to the IP task or the
\r
783 data contained an error and was discarded. Give the descriptor
\r
784 back to the DMA. */
\r
785 xDMARxDescriptors[ ulNextRxDescriptorToProcess ].STATUS = ulStatus | RDES_OWN;
\r
787 /* Move onto the next descriptor. */
\r
788 ulNextRxDescriptorToProcess++;
\r
789 if( ulNextRxDescriptorToProcess >= configNUM_RX_DESCRIPTORS )
\r
791 ulNextRxDescriptorToProcess = 0;
\r
794 ulStatus = xDMARxDescriptors[ ulNextRxDescriptorToProcess ].STATUS;
\r
795 } /* if( ( ulStatus & nwRX_STATUS_ERROR_BITS ) != 0 ) */
\r
796 } /* if( ( ulStatus & RDES_OWN ) == 0 ) */
\r
798 /* Restart receive polling. */
\r
799 LPC_ETHERNET->DMA_REC_POLL_DEMAND = 1;
\r
803 /*-----------------------------------------------------------*/
\r
805 configPLACE_IN_SECTION_RAM
\r
806 void NETWORK_IRQHandler( void )
\r
808 BaseType_t xHigherPriorityTaskWoken = pdFALSE;
\r
809 uint32_t ulDMAStatus;
\r
810 const uint32_t ulRxInterruptMask =
\r
811 DMA_ST_RI | /* Receive interrupt */
\r
812 DMA_ST_RU; /* Receive buffer unavailable */
\r
813 const uint32_t ulTxInterruptMask =
\r
814 DMA_ST_TI | /* Transmit interrupt */
\r
815 DMA_ST_TPS; /* Transmit process stopped */
\r
817 configASSERT( xRxHanderTask );
\r
819 /* Get pending interrupts. */
\r
820 ulDMAStatus = LPC_ETHERNET->DMA_STAT;
\r
822 /* RX group interrupt(s). */
\r
823 if( ( ulDMAStatus & ulRxInterruptMask ) != 0x00 )
\r
825 /* Remember that an RX event has happened. */
\r
826 ulISREvents |= EMAC_IF_RX_EVENT;
\r
827 vTaskNotifyGiveFromISR( xRxHanderTask, &xHigherPriorityTaskWoken );
\r
830 /* TX group interrupt(s). */
\r
831 if( ( ulDMAStatus & ulTxInterruptMask ) != 0x00 )
\r
833 /* Remember that a TX event has happened. */
\r
834 ulISREvents |= EMAC_IF_TX_EVENT;
\r
835 vTaskNotifyGiveFromISR( xRxHanderTask, &xHigherPriorityTaskWoken );
\r
838 /* Test for 'Abnormal interrupt summary'. */
\r
839 if( ( ulDMAStatus & DMA_ST_AIE ) != 0x00 )
\r
841 /* The trace macro must be written such that it can be called from
\r
843 iptraceETHERNET_RX_EVENT_LOST();
\r
846 /* Clear pending interrupts */
\r
847 LPC_ETHERNET->DMA_STAT = ulDMAStatus;
\r
849 /* Context switch needed? */
\r
850 portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
\r
852 /*-----------------------------------------------------------*/
\r
854 static BaseType_t prvSetLinkSpeed( void )
\r
856 BaseType_t xReturn = pdFAIL;
\r
857 TickType_t xTimeOnEntering;
\r
858 uint32_t ulPhyStatus;
\r
859 const TickType_t xAutoNegotiateDelay = pdMS_TO_TICKS( 5000UL );
\r
861 /* Ensure polling does not starve lower priority tasks by temporarily
\r
862 setting the priority of this task to that of the idle task. */
\r
863 vTaskPrioritySet( NULL, tskIDLE_PRIORITY );
\r
865 xTimeOnEntering = xTaskGetTickCount();
\r
868 ulPhyStatus = lpcPHYStsPoll();
\r
869 if( ( ulPhyStatus & PHY_LINK_CONNECTED ) != 0x00 )
\r
871 /* Set interface speed and duplex. */
\r
872 if( ( ulPhyStatus & PHY_LINK_SPEED100 ) != 0x00 )
\r
874 Chip_ENET_SetSpeed( LPC_ETHERNET, 1 );
\r
878 Chip_ENET_SetSpeed( LPC_ETHERNET, 0 );
\r
881 if( ( ulPhyStatus & PHY_LINK_FULLDUPLX ) != 0x00 )
\r
883 Chip_ENET_SetDuplex( LPC_ETHERNET, pdTRUE );
\r
887 Chip_ENET_SetDuplex( LPC_ETHERNET, pdFALSE );
\r
893 } while( ( xTaskGetTickCount() - xTimeOnEntering ) < xAutoNegotiateDelay );
\r
895 /* Reset the priority of this task back to its original value. */
\r
896 vTaskPrioritySet( NULL, ipconfigIP_TASK_PRIORITY );
\r
900 /*-----------------------------------------------------------*/
\r
902 static uint32_t prvGenerateCRC32( const uint8_t *ucAddress )
\r
905 const uint32_t Polynomial = 0xEDB88320;
\r
906 uint32_t crc = ~0ul;
\r
907 const uint8_t *pucCurrent = ( const uint8_t * ) ucAddress;
\r
908 const uint8_t *pucLast = pucCurrent + 6;
\r
910 /* Calculate normal CRC32 */
\r
911 while( pucCurrent < pucLast )
\r
913 crc ^= *( pucCurrent++ );
\r
914 for( j = 0; j < 8; j++ )
\r
916 if( ( crc & 1 ) != 0 )
\r
918 crc = (crc >> 1) ^ Polynomial;
\r
928 /*-----------------------------------------------------------*/
\r
930 static uint32_t prvGetHashIndex( const uint8_t *ucAddress )
\r
932 uint32_t ulCrc = prvGenerateCRC32( ucAddress );
\r
933 uint32_t ulIndex = 0ul;
\r
934 BaseType_t xCount = 6;
\r
936 /* Take the lowest 6 bits of the CRC32 and reverse them */
\r
940 ulIndex |= ( ulCrc & 1 );
\r
944 /* This is the has value of 'ucAddress' */
\r
947 /*-----------------------------------------------------------*/
\r
949 static void prvAddMACAddress( const uint8_t* ucMacAddress )
\r
953 xIndex = prvGetHashIndex( ucMacAddress );
\r
956 LPC_ETHERNET->MAC_HASHTABLE_HIGH |= ( 1u << ( xIndex - 32 ) );
\r
960 LPC_ETHERNET->MAC_HASHTABLE_LOW |= ( 1u << xIndex );
\r
963 /*-----------------------------------------------------------*/
\r
965 configPLACE_IN_SECTION_RAM
\r
966 static void prvEMACHandlerTask( void *pvParameters )
\r
968 TimeOut_t xPhyTime;
\r
969 TickType_t xPhyRemTime;
\r
970 UBaseType_t uxLastMinBufferCount = 0;
\r
971 UBaseType_t uxCurrentCount;
\r
972 BaseType_t xResult = 0;
\r
974 const TickType_t xBlockTime = pdMS_TO_TICKS( 5000ul );
\r
976 /* Remove compiler warning about unused parameter. */
\r
977 ( void ) pvParameters;
\r
979 /* A possibility to set some additional task properties. */
\r
980 iptraceEMAC_TASK_STARTING();
\r
982 vTaskSetTimeOutState( &xPhyTime );
\r
983 xPhyRemTime = pdMS_TO_TICKS( PHY_LS_LOW_CHECK_TIME_MS );
\r
987 uxCurrentCount = uxGetMinimumFreeNetworkBuffers();
\r
988 if( uxLastMinBufferCount != uxCurrentCount )
\r
990 /* The logging produced below may be helpful
\r
991 while tuning +TCP: see how many buffers are in use. */
\r
992 uxLastMinBufferCount = uxCurrentCount;
\r
993 FreeRTOS_printf( ( "Network buffers: %lu lowest %lu\n",
\r
994 uxGetNumberOfFreeNetworkBuffers(), uxCurrentCount ) );
\r
997 #if( ipconfigCHECK_IP_QUEUE_SPACE != 0 )
\r
999 static UBaseType_t uxLastMinQueueSpace = 0;
\r
1001 uxCurrentCount = uxGetMinimumIPQueueSpace();
\r
1002 if( uxLastMinQueueSpace != uxCurrentCount )
\r
1004 /* The logging produced below may be helpful
\r
1005 while tuning +TCP: see how many buffers are in use. */
\r
1006 uxLastMinQueueSpace = uxCurrentCount;
\r
1007 FreeRTOS_printf( ( "Queue space: lowest %lu\n", uxCurrentCount ) );
\r
1010 #endif /* ipconfigCHECK_IP_QUEUE_SPACE */
\r
1012 ulTaskNotifyTake( pdTRUE, xBlockTime );
\r
1014 xResult = ( BaseType_t ) 0;
\r
1016 if( ( ulISREvents & EMAC_IF_TX_EVENT ) != 0 )
\r
1018 /* Code to release TX buffers if zero-copy is used. */
\r
1019 ulISREvents &= ~EMAC_IF_TX_EVENT;
\r
1021 /* Check if DMA packets have been delivered. */
\r
1022 vClearTXBuffers();
\r
1026 if( ( ulISREvents & EMAC_IF_RX_EVENT ) != 0 )
\r
1028 ulISREvents &= ~EMAC_IF_RX_EVENT;
\r
1030 xResult = prvNetworkInterfaceInput();
\r
1033 while( prvNetworkInterfaceInput() > 0 )
\r
1041 /* A packet was received. No need to check for the PHY status now,
\r
1042 but set a timer to check it later on. */
\r
1043 vTaskSetTimeOutState( &xPhyTime );
\r
1044 xPhyRemTime = pdMS_TO_TICKS( PHY_LS_HIGH_CHECK_TIME_MS );
\r
1047 else if( xTaskCheckForTimeOut( &xPhyTime, &xPhyRemTime ) != pdFALSE )
\r
1049 ulStatus = lpcPHYStsPoll();
\r
1051 if( ( ulPHYLinkStatus & PHY_LINK_CONNECTED ) != ( ulStatus & PHY_LINK_CONNECTED ) )
\r
1053 ulPHYLinkStatus = ulStatus;
\r
1054 FreeRTOS_printf( ( "prvEMACHandlerTask: PHY LS now %d (polled PHY)\n", ( ulPHYLinkStatus & PHY_LINK_CONNECTED ) != 0 ) );
\r
1057 vTaskSetTimeOutState( &xPhyTime );
\r
1058 if( ( ulPHYLinkStatus & PHY_LINK_CONNECTED ) != 0 )
\r
1060 xPhyRemTime = pdMS_TO_TICKS( PHY_LS_HIGH_CHECK_TIME_MS );
\r
1064 xPhyRemTime = pdMS_TO_TICKS( PHY_LS_LOW_CHECK_TIME_MS );
\r
1069 /*-----------------------------------------------------------*/
\r