1 /**************************************************************************//**
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2 * @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
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4 * Redistribution and use in source and binary forms, with or without modification,
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5 * are permitted provided that the following conditions are met:
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6 * 1. Redistributions of source code must retain the above copyright notice,
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7 * this list of conditions and the following disclaimer.
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8 * 2. Redistributions in binary form must reproduce the above copyright notice,
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9 * this list of conditions and the following disclaimer in the documentation
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10 * and/or other materials provided with the distribution.
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11 * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
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12 * may be used to endorse or promote products derived from this software
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13 * without specific prior written permission.
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15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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18 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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22 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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24 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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25 *****************************************************************************/
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30 /* Generic MII registers. */
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32 #define MII_BMCR 0x00 /* Basic mode control register */
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33 #define MII_BMSR 0x01 /* Basic mode status register */
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34 #define MII_PHYSID1 0x02 /* PHYS ID 1 */
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35 #define MII_PHYSID2 0x03 /* PHYS ID 2 */
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36 #define MII_ADVERTISE 0x04 /* Advertisement control reg */
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37 #define MII_LPA 0x05 /* Link partner ability reg */
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38 #define MII_EXPANSION 0x06 /* Expansion register */
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39 #define MII_DCOUNTER 0x12 /* Disconnect counter */
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40 #define MII_FCSCOUNTER 0x13 /* False carrier counter */
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41 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
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42 #define MII_RERRCOUNTER 0x15 /* Receive error counter */
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43 #define MII_SREVISION 0x16 /* Silicon revision */
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44 #define MII_RESV1 0x17 /* Reserved... */
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45 #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
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46 #define MII_PHYADDR 0x19 /* PHY address */
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47 #define MII_RESV2 0x1a /* Reserved... */
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48 #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
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49 #define MII_NCONFIG 0x1c /* Network interface config */
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51 /* Basic mode control register. */
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52 #define BMCR_RESV 0x007f /* Unused... */
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53 #define BMCR_CTST 0x0080 /* Collision test */
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54 #define BMCR_FULLDPLX 0x0100 /* Full duplex */
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55 #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
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56 #define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
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57 #define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
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58 #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
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59 #define BMCR_SPEED100 0x2000 /* Select 100Mbps */
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60 #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
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61 #define BMCR_RESET 0x8000 /* Reset the DP83840 */
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63 /* Basic mode status register. */
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64 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
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65 #define BMSR_JCD 0x0002 /* Jabber detected */
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66 #define BMSR_LSTATUS 0x0004 /* Link status */
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67 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
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68 #define BMSR_RFAULT 0x0010 /* Remote fault detected */
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69 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
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70 #define BMSR_RESV 0x07c0 /* Unused... */
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71 #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
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72 #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
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73 #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
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74 #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
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75 #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
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77 /* Advertisement control register. */
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78 #define ADVERTISE_SLCT 0x001f /* Selector bits */
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79 #define ADVERTISE_CSMA 0x0001 /* Only selector supported */
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80 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
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81 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
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82 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
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83 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
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84 #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
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85 #define ADVERTISE_RESV 0x1c00 /* Unused... */
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86 #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
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87 #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
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88 #define ADVERTISE_NPAGE 0x8000 /* Next page bit */
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90 #define RX_DESCRIPTOR_NUM 4 //8 // Max Number of Rx Frame Descriptors
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91 #define TX_DESCRIPTOR_NUM 2 //4 // Max number of Tx Frame Descriptors
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93 #define PACKET_BUFFER_SIZE 1520
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95 #define CONFIG_PHY_ADDR 1
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98 // Frame Descriptor's Owner bit
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99 #define OWNERSHIP_EMAC 0x80000000 // 1 = EMAC
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100 //#define OWNERSHIP_CPU 0x7fffffff // 0 = CPU
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104 // Rx Frame Descriptor Status
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105 #define RXFD_RXGD 0x00100000 // Receiving Good Packet Received
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106 #define RXFD_RTSAS 0x00800000 // RX Time Stamp Available
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109 // Tx Frame Descriptor's Control bits
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110 #define TXFD_TTSEN 0x08 // Tx Time Stamp Enable
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111 #define TXFD_INTEN 0x04 // Interrupt Enable
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112 #define TXFD_CRCAPP 0x02 // Append CRC
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113 #define TXFD_PADEN 0x01 // Padding Enable
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115 // Tx Frame Descriptor Status
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116 #define TXFD_TXCP 0x00080000 // Transmission Completion
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117 #define TXFD_TTSAS 0x08000000 // TX Time Stamp Available
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119 // Tx/Rx buffer descriptor structure
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120 struct eth_descriptor;
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121 struct eth_descriptor {
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125 struct eth_descriptor *next;
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126 #ifdef TIME_STAMPING
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129 uint32_t reserved1;
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130 uint32_t reserved2;
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134 #ifdef TIME_STAMPING
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136 #define ETH_TS_ENABLE() do{EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk;}while(0)
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137 #define ETH_TS_START() do{EMAC->TSCTL |= (EMAC_TSCTL_TSMODE_Msk | EMAC_TSCTL_TSIEN_Msk);}while(0)
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138 s32_t ETH_settime(u32_t sec, u32_t nsec);
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139 s32_t ETH_gettime(u32_t *sec, u32_t *nsec);
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140 s32_t ETH_updatetime(u32_t neg, u32_t sec, u32_t nsec);
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141 s32_t ETH_adjtimex(int ppm);
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142 void ETH_setinc(void);
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147 #define NU_DEBUGF(x) { printf x; }
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149 #define NU_DEBUGF(x)
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152 void numaker_set_mac_addr(uint8_t *addr);
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153 int numaker_eth_init(uint8_t *mac_addr);
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154 uint8_t *numaker_eth_get_tx_buf(void);
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155 void numaker_eth_trigger_tx(uint16_t length, void *p);
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156 int numaker_eth_get_rx_buf(uint16_t *len, uint8_t **buf);
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157 void numaker_eth_rx_next(void);
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158 void numaker_eth_trigger_rx(void);
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159 int numaker_eth_link_ok(void);
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160 void numaker_mac_address(uint8_t *mac);
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161 void numaker_eth_enable_interrupts(void);
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162 void numaker_eth_disable_interrupts(void);
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164 #endif /* _M480_ETH_ */
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