2 * Some constants, hardware definitions and comments taken from ST's HAL driver
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3 * library, COPYRIGHT(c) 2015 STMicroelectronics.
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7 * FreeRTOS+TCP V2.0.3
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8 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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10 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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11 * this software and associated documentation files (the "Software"), to deal in
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12 * the Software without restriction, including without limitation the rights to
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13 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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14 * the Software, and to permit persons to whom the Software is furnished to do so,
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15 * subject to the following conditions:
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17 * The above copyright notice and this permission notice shall be included in all
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18 * copies or substantial portions of the Software.
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20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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22 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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23 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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24 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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25 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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27 * http://aws.amazon.com/freertos
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28 * http://www.FreeRTOS.org
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32 /* Standard includes. */
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37 /* FreeRTOS includes. */
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38 #include "FreeRTOS.h"
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43 /* FreeRTOS+TCP includes. */
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44 #include "FreeRTOS_IP.h"
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45 #include "FreeRTOS_Sockets.h"
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46 #include "FreeRTOS_IP_Private.h"
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47 #include "FreeRTOS_DNS.h"
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48 #include "NetworkBufferManagement.h"
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49 #include "NetworkInterface.h"
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50 #include "phyHandling.h"
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54 #include "stm32f7xx_hal.h"
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56 #include "stm32f4xx_hal.h"
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59 /* Interrupt events to process. Currently only the Rx event is processed
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60 although code for other events is included to allow for possible future
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62 #define EMAC_IF_RX_EVENT 1UL
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63 #define EMAC_IF_TX_EVENT 2UL
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64 #define EMAC_IF_ERR_EVENT 4UL
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65 #define EMAC_IF_ALL_EVENT ( EMAC_IF_RX_EVENT | EMAC_IF_TX_EVENT | EMAC_IF_ERR_EVENT )
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67 #define ETH_DMA_ALL_INTS \
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68 ( ETH_DMA_IT_TST | ETH_DMA_IT_PMT | ETH_DMA_IT_MMC | ETH_DMA_IT_NIS | ETH_DMA_IT_ER | \
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69 ETH_DMA_IT_FBE | ETH_DMA_IT_RWT | ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | \
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70 ETH_DMA_IT_TU | ETH_DMA_IT_RO | ETH_DMA_IT_TJT | ETH_DMA_IT_TPS | ETH_DMA_IT_T )
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74 #define ipFRAGMENT_OFFSET_BIT_MASK ( ( uint16_t ) 0x0fff ) /* The bits in the two byte IP header field that make up the fragment offset value. */
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77 * Most users will want a PHY that negotiates about
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78 * the connection properties: speed, dmix and duplex.
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79 * On some rare cases, you want to select what is being
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80 * advertised, properties like MDIX and duplex.
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83 #if !defined( ipconfigETHERNET_AN_ENABLE )
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84 /* Enable auto-negotiation */
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85 #define ipconfigETHERNET_AN_ENABLE 1
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88 #if !defined( ipconfigETHERNET_AUTO_CROSS_ENABLE )
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89 #define ipconfigETHERNET_AUTO_CROSS_ENABLE 1
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92 #if( ipconfigETHERNET_AN_ENABLE == 0 )
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94 * The following three defines are only used in case there
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95 * is no auto-negotiation.
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97 #if !defined( ipconfigETHERNET_CROSSED_LINK )
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98 #define ipconfigETHERNET_CROSSED_LINK 1
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101 #if !defined( ipconfigETHERNET_USE_100MB )
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102 #define ipconfigETHERNET_USE_100MB 1
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105 #if !defined( ipconfigETHERNET_USE_FULL_DUPLEX )
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106 #define ipconfigETHERNET_USE_FULL_DUPLEX 1
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108 #endif /* ipconfigETHERNET_AN_ENABLE == 0 */
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110 /* Default the size of the stack used by the EMAC deferred handler task to twice
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111 the size of the stack used by the idle task - but allow this to be overridden in
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112 FreeRTOSConfig.h as configMINIMAL_STACK_SIZE is a user definable constant. */
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113 #ifndef configEMAC_TASK_STACK_SIZE
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114 #define configEMAC_TASK_STACK_SIZE ( 2 * configMINIMAL_STACK_SIZE )
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117 /* Two choices must be made: RMII versus MII,
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118 and the index of the PHY in use ( between 0 and 31 ). */
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119 #ifndef ipconfigUSE_RMII
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121 #define ipconfigUSE_RMII 1
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123 #define ipconfigUSE_RMII 0
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124 #endif /* STM32F7xx */
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125 #endif /* ipconfigUSE_RMII */
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129 /*-----------------------------------------------------------*/
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132 * A deferred interrupt handler task that processes
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134 static void prvEMACHandlerTask( void *pvParameters );
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137 * Force a negotiation with the Switch or Router and wait for LS.
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139 static void prvEthernetUpdateConfig( BaseType_t xForce );
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142 * See if there is a new packet and forward it to the IP-task.
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144 static BaseType_t prvNetworkInterfaceInput( void );
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146 #if( ipconfigUSE_LLMNR != 0 )
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148 * For LLMNR, an extra MAC-address must be configured to
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149 * be able to receive the multicast messages.
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151 static void prvMACAddressConfig(ETH_HandleTypeDef *heth, uint32_t ulIndex, uint8_t *Addr);
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155 * Check if a given packet should be accepted.
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157 static BaseType_t xMayAcceptPacket( uint8_t *pcBuffer );
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160 * Initialise the TX descriptors.
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162 static void prvDMATxDescListInit( void );
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165 * Initialise the RX descriptors.
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167 static void prvDMARxDescListInit( void );
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169 /* After packets have been sent, the network
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170 buffers will be released. */
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171 static void vClearTXBuffers( void );
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173 /*-----------------------------------------------------------*/
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175 /* Bit map of outstanding ETH interrupt events for processing. Currently only
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176 the Rx interrupt is handled, although code is included for other events to
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177 enable future expansion. */
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178 static volatile uint32_t ulISREvents;
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180 #if( ipconfigUSE_LLMNR == 1 )
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181 static const uint8_t xLLMNR_MACAddress[] = { 0x01, 0x00, 0x5E, 0x00, 0x00, 0xFC };
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184 static EthernetPhy_t xPhyObject;
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186 /* Ethernet handle. */
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187 static ETH_HandleTypeDef xETH;
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189 /* xTXDescriptorSemaphore is a counting semaphore with
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190 a maximum count of ETH_TXBUFNB, which is the number of
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191 DMA TX descriptors. */
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192 static SemaphoreHandle_t xTXDescriptorSemaphore = NULL;
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195 * Note: it is adviced to define both
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197 * #define ipconfigZERO_COPY_RX_DRIVER 1
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198 * #define ipconfigZERO_COPY_TX_DRIVER 1
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200 * The method using memcpy is slower and probaly uses more RAM memory.
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201 * The possibility is left in the code just for comparison.
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203 * It is adviced to define ETH_TXBUFNB at least 4. Note that no
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204 * TX buffers are allocated in a zero-copy driver.
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206 /* MAC buffers: ---------------------------------------------------------*/
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208 /* Put the DMA descriptors in '.first_data'.
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209 This is important for STM32F7, which has an L1 data cache.
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210 The first 64KB of the SRAM is not cached. */
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212 /* Ethernet Rx MA Descriptor */
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213 __attribute__ ((aligned (32)))
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214 __attribute__ ((section(".first_data")))
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215 ETH_DMADescTypeDef DMARxDscrTab[ ETH_RXBUFNB ];
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217 #if( ipconfigZERO_COPY_RX_DRIVER == 0 )
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218 /* Ethernet Receive Buffer */
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219 __ALIGN_BEGIN uint8_t Rx_Buff[ ETH_RXBUFNB ][ ETH_RX_BUF_SIZE ] __ALIGN_END;
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222 /* Ethernet Tx DMA Descriptor */
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223 __attribute__ ((aligned (32)))
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224 __attribute__ ((section(".first_data")))
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225 ETH_DMADescTypeDef DMATxDscrTab[ ETH_TXBUFNB ];
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227 #if( ipconfigZERO_COPY_TX_DRIVER == 0 )
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228 /* Ethernet Transmit Buffer */
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229 __ALIGN_BEGIN uint8_t Tx_Buff[ ETH_TXBUFNB ][ ETH_TX_BUF_SIZE ] __ALIGN_END;
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232 #if( ipconfigZERO_COPY_TX_DRIVER != 0 )
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233 /* DMATxDescToClear points to the next TX DMA descriptor
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234 that must be cleared by vClearTXBuffers(). */
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235 static __IO ETH_DMADescTypeDef *DMATxDescToClear;
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238 /* ucMACAddress as it appears in main.c */
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239 extern const uint8_t ucMACAddress[ 6 ];
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241 /* Holds the handle of the task used as a deferred interrupt processor. The
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242 handle is used so direct notifications can be sent to the task for all EMAC/DMA
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243 related interrupts. */
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244 static TaskHandle_t xEMACTaskHandle = NULL;
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246 /* For local use only: describe the PHY's properties: */
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247 const PhyProperties_t xPHYProperties =
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249 #if( ipconfigETHERNET_AN_ENABLE != 0 )
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250 .ucSpeed = PHY_SPEED_AUTO,
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251 .ucDuplex = PHY_DUPLEX_AUTO,
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253 #if( ipconfigETHERNET_USE_100MB != 0 )
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254 .ucSpeed = PHY_SPEED_100,
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256 .ucSpeed = PHY_SPEED_10,
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259 #if( ipconfigETHERNET_USE_FULL_DUPLEX != 0 )
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260 .duplex = PHY_DUPLEX_FULL,
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262 .duplex = PHY_DUPLEX_HALF,
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266 #if( ipconfigETHERNET_AN_ENABLE != 0 ) && ( ipconfigETHERNET_AUTO_CROSS_ENABLE != 0 )
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267 .ucMDI_X = PHY_MDIX_AUTO,
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268 #elif( ipconfigETHERNET_CROSSED_LINK != 0 )
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269 .ucMDI_X = PHY_MDIX_CROSSED,
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271 .ucMDI_X = PHY_MDIX_DIRECT,
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275 /*-----------------------------------------------------------*/
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277 void HAL_ETH_RxCpltCallback( ETH_HandleTypeDef *heth )
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279 BaseType_t xHigherPriorityTaskWoken = pdFALSE;
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281 /* Ethernet RX-Complete callback function, elsewhere declared as weak. */
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282 ulISREvents |= EMAC_IF_RX_EVENT;
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283 /* Wakeup the prvEMACHandlerTask. */
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284 if( xEMACTaskHandle != NULL )
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286 vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken );
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287 portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
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290 /*-----------------------------------------------------------*/
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292 void HAL_ETH_TxCpltCallback( ETH_HandleTypeDef *heth )
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294 BaseType_t xHigherPriorityTaskWoken = pdFALSE;
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296 /* This call-back is only useful in case packets are being sent
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297 zero-copy. Once they're sent, the buffers will be released
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298 by the function vClearTXBuffers(). */
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299 ulISREvents |= EMAC_IF_TX_EVENT;
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300 /* Wakeup the prvEMACHandlerTask. */
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301 if( xEMACTaskHandle != NULL )
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303 vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken );
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304 portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
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308 /*-----------------------------------------------------------*/
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310 static void vClearTXBuffers()
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312 __IO ETH_DMADescTypeDef *txLastDescriptor = xETH.TxDesc;
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313 size_t uxCount = ( ( UBaseType_t ) ETH_TXBUFNB ) - uxSemaphoreGetCount( xTXDescriptorSemaphore );
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314 #if( ipconfigZERO_COPY_TX_DRIVER != 0 )
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315 NetworkBufferDescriptor_t *pxNetworkBuffer;
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316 uint8_t *ucPayLoad;
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319 /* This function is called after a TX-completion interrupt.
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320 It will release each Network Buffer used in xNetworkInterfaceOutput().
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321 'uxCount' represents the number of descriptors given to DMA for transmission.
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322 After sending a packet, the DMA will clear the 'ETH_DMATXDESC_OWN' bit. */
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323 while( ( uxCount > 0 ) && ( ( DMATxDescToClear->Status & ETH_DMATXDESC_OWN ) == 0 ) )
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325 if( ( DMATxDescToClear == txLastDescriptor ) && ( uxCount != ETH_TXBUFNB ) )
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329 #if( ipconfigZERO_COPY_TX_DRIVER != 0 )
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331 ucPayLoad = ( uint8_t * )DMATxDescToClear->Buffer1Addr;
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333 if( ucPayLoad != NULL )
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335 pxNetworkBuffer = pxPacketBuffer_to_NetworkBuffer( ucPayLoad );
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336 if( pxNetworkBuffer != NULL )
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338 vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ) ;
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340 DMATxDescToClear->Buffer1Addr = ( uint32_t )0u;
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343 #endif /* ipconfigZERO_COPY_TX_DRIVER */
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345 DMATxDescToClear = ( ETH_DMADescTypeDef * )( DMATxDescToClear->Buffer2NextDescAddr );
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348 /* Tell the counting semaphore that one more TX descriptor is available. */
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349 xSemaphoreGive( xTXDescriptorSemaphore );
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352 /*-----------------------------------------------------------*/
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354 BaseType_t xNetworkInterfaceInitialise( void )
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356 HAL_StatusTypeDef hal_eth_init_status;
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357 BaseType_t xResult;
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359 if( xEMACTaskHandle == NULL )
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361 if( xTXDescriptorSemaphore == NULL )
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363 xTXDescriptorSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) ETH_TXBUFNB, ( UBaseType_t ) ETH_TXBUFNB );
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364 configASSERT( xTXDescriptorSemaphore );
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367 /* Initialise ETH */
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369 xETH.Instance = ETH;
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370 xETH.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
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371 xETH.Init.Speed = ETH_SPEED_100M;
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372 xETH.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
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373 /* Value of PhyAddress doesn't matter, will be probed for. */
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374 xETH.Init.PhyAddress = 0;
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376 xETH.Init.MACAddr = ( uint8_t *) ucMACAddress;
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377 xETH.Init.RxMode = ETH_RXINTERRUPT_MODE;
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379 /* using the ETH_CHECKSUM_BY_HARDWARE option:
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380 both the IP and the protocol checksums will be calculated
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381 by the peripheral. */
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382 xETH.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
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384 #if( ipconfigUSE_RMII != 0 )
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386 xETH.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
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390 xETH.Init.MediaInterface = ETH_MEDIA_INTERFACE_MII;
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392 #endif /* ipconfigUSE_RMII */
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394 hal_eth_init_status = HAL_ETH_Init( &xETH );
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396 /* Only for inspection by debugger. */
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397 ( void ) hal_eth_init_status;
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399 /* Set the TxDesc and RxDesc pointers. */
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400 xETH.TxDesc = DMATxDscrTab;
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401 xETH.RxDesc = DMARxDscrTab;
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403 /* Make sure that all unused fields are cleared. */
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404 memset( &DMATxDscrTab, '\0', sizeof( DMATxDscrTab ) );
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405 memset( &DMARxDscrTab, '\0', sizeof( DMARxDscrTab ) );
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407 /* Initialize Tx Descriptors list: Chain Mode */
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408 DMATxDescToClear = DMATxDscrTab;
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410 /* Initialise TX-descriptors. */
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411 prvDMATxDescListInit();
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413 /* Initialise RX-descriptors. */
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414 prvDMARxDescListInit();
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416 #if( ipconfigUSE_LLMNR != 0 )
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418 /* Program the LLMNR address at index 1. */
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419 prvMACAddressConfig( &xETH, ETH_MAC_ADDRESS1, ( uint8_t *) xLLMNR_MACAddress );
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423 /* Force a negotiation with the Switch or Router and wait for LS. */
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424 prvEthernetUpdateConfig( pdTRUE );
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426 /* The deferred interrupt handler task is created at the highest
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427 possible priority to ensure the interrupt handler can return directly
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428 to it. The task's handle is stored in xEMACTaskHandle so interrupts can
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429 notify the task when there is something to process. */
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430 xTaskCreate( prvEMACHandlerTask, "EMAC", configEMAC_TASK_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, &xEMACTaskHandle );
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431 } /* if( xEMACTaskHandle == NULL ) */
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433 if( xPhyObject.ulLinkStatusMask != 0 )
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435 xETH.Instance->DMAIER |= ETH_DMA_ALL_INTS;
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437 FreeRTOS_printf( ( "Link Status is high\n" ) ) ;
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441 /* For now pdFAIL will be returned. But prvEMACHandlerTask() is running
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442 and it will keep on checking the PHY and set 'ulLinkStatusMask' when necessary. */
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444 FreeRTOS_printf( ( "Link Status still low\n" ) ) ;
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446 /* When returning non-zero, the stack will become active and
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447 start DHCP (in configured) */
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450 /*-----------------------------------------------------------*/
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452 static void prvDMATxDescListInit()
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454 ETH_DMADescTypeDef *pxDMADescriptor;
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457 /* Get the pointer on the first member of the descriptor list */
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458 pxDMADescriptor = DMATxDscrTab;
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460 /* Fill each DMA descriptor with the right values */
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461 for( xIndex = 0; xIndex < ETH_TXBUFNB; xIndex++, pxDMADescriptor++ )
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463 /* Set Second Address Chained bit */
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464 pxDMADescriptor->Status = ETH_DMATXDESC_TCH;
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466 #if( ipconfigZERO_COPY_TX_DRIVER == 0 )
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468 /* Set Buffer1 address pointer */
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469 pxDMADescriptor->Buffer1Addr = ( uint32_t )( Tx_Buff[ xIndex ] );
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473 if( xETH.Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE )
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475 /* Set the DMA Tx descriptors checksum insertion for TCP, UDP, and ICMP */
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476 pxDMADescriptor->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
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479 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
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480 if( xIndex < ETH_TXBUFNB - 1 )
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482 /* Set next descriptor address register with next descriptor base address */
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483 pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) ( pxDMADescriptor + 1 );
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487 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
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488 pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) DMATxDscrTab;
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492 /* Set Transmit Descriptor List Address Register */
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493 xETH.Instance->DMATDLAR = ( uint32_t ) DMATxDscrTab;
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495 /*-----------------------------------------------------------*/
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497 static void prvDMARxDescListInit()
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499 ETH_DMADescTypeDef *pxDMADescriptor;
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505 /* Get the pointer on the first member of the descriptor list */
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506 pxDMADescriptor = DMARxDscrTab;
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508 /* Fill each DMA descriptor with the right values */
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509 for( xIndex = 0; xIndex < ETH_RXBUFNB; xIndex++, pxDMADescriptor++ )
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512 /* Set Buffer1 size and Second Address Chained bit */
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513 pxDMADescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | (uint32_t)ETH_RX_BUF_SIZE;
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515 #if( ipconfigZERO_COPY_RX_DRIVER != 0 )
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517 /* Set Buffer1 address pointer */
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518 NetworkBufferDescriptor_t *pxBuffer;
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520 pxBuffer = pxGetNetworkBufferWithDescriptor( ETH_RX_BUF_SIZE, 100ul );
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521 /* If the assert below fails, make sure that there are at least 'ETH_RXBUFNB'
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522 Network Buffers available during start-up ( ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ) */
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523 configASSERT( pxBuffer != NULL );
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524 if( pxBuffer != NULL )
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526 pxDMADescriptor->Buffer1Addr = (uint32_t)pxBuffer->pucEthernetBuffer;
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527 pxDMADescriptor->Status = ETH_DMARXDESC_OWN;
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532 /* Set Buffer1 address pointer */
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533 pxDMADescriptor->Buffer1Addr = ( uint32_t )( Rx_Buff[ xIndex ] );
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534 /* Set Own bit of the Rx descriptor Status */
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535 pxDMADescriptor->Status = ETH_DMARXDESC_OWN;
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539 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
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540 if( xIndex < ETH_RXBUFNB - 1 )
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542 /* Set next descriptor address register with next descriptor base address */
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543 pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t )( pxDMADescriptor + 1 );
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547 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
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548 pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) DMARxDscrTab;
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552 /* Set Receive Descriptor List Address Register */
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553 xETH.Instance->DMARDLAR = ( uint32_t ) DMARxDscrTab;
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555 /*-----------------------------------------------------------*/
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557 static void prvMACAddressConfig(ETH_HandleTypeDef *heth, uint32_t ulIndex, uint8_t *Addr)
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559 uint32_t ulTempReg;
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561 /* Calculate the selected MAC address high register. */
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562 ulTempReg = 0x80000000ul | ( ( uint32_t ) Addr[ 5 ] << 8 ) | ( uint32_t ) Addr[ 4 ];
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564 /* Load the selected MAC address high register. */
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565 ( *(__IO uint32_t *)( ( uint32_t ) ( ETH_MAC_ADDR_HBASE + ulIndex ) ) ) = ulTempReg;
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567 /* Calculate the selected MAC address low register. */
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568 ulTempReg = ( ( uint32_t ) Addr[ 3 ] << 24 ) | ( ( uint32_t ) Addr[ 2 ] << 16 ) | ( ( uint32_t ) Addr[ 1 ] << 8 ) | Addr[ 0 ];
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570 /* Load the selected MAC address low register */
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571 ( *(__IO uint32_t *) ( ( uint32_t ) ( ETH_MAC_ADDR_LBASE + ulIndex ) ) ) = ulTempReg;
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573 /*-----------------------------------------------------------*/
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575 BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxDescriptor, BaseType_t bReleaseAfterSend )
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577 BaseType_t xReturn = pdFAIL;
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578 uint32_t ulTransmitSize = 0;
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579 __IO ETH_DMADescTypeDef *pxDmaTxDesc;
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580 /* Do not wait too long for a free TX DMA buffer. */
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581 const TickType_t xBlockTimeTicks = pdMS_TO_TICKS( 50u );
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583 #if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 )
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585 ProtocolPacket_t *pxPacket;
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587 #if( ipconfigZERO_COPY_RX_DRIVER != 0 )
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589 configASSERT( bReleaseAfterSend != 0 );
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591 #endif /* ipconfigZERO_COPY_RX_DRIVER */
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593 /* If the peripheral must calculate the checksum, it wants
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594 the protocol checksum to have a value of zero. */
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595 pxPacket = ( ProtocolPacket_t * ) ( pxDescriptor->pucEthernetBuffer );
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597 if( pxPacket->xICMPPacket.xIPHeader.ucProtocol == ipPROTOCOL_ICMP )
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599 pxPacket->xICMPPacket.xICMPHeader.usChecksum = ( uint16_t )0u;
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604 /* Open a do {} while ( 0 ) loop to be able to call break. */
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607 if( xPhyObject.ulLinkStatusMask != 0 )
\r
609 if( xSemaphoreTake( xTXDescriptorSemaphore, xBlockTimeTicks ) != pdPASS )
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611 /* Time-out waiting for a free TX descriptor. */
\r
615 /* This function does the actual transmission of the packet. The packet is
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616 contained in 'pxDescriptor' that is passed to the function. */
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617 pxDmaTxDesc = xETH.TxDesc;
\r
619 /* Is this buffer available? */
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620 configASSERT ( ( pxDmaTxDesc->Status & ETH_DMATXDESC_OWN ) == 0 );
\r
623 /* Is this buffer available? */
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624 /* Get bytes in current buffer. */
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625 ulTransmitSize = pxDescriptor->xDataLength;
\r
627 if( ulTransmitSize > ETH_TX_BUF_SIZE )
\r
629 ulTransmitSize = ETH_TX_BUF_SIZE;
\r
632 #if( ipconfigZERO_COPY_TX_DRIVER == 0 )
\r
634 /* Copy the bytes. */
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635 memcpy( ( void * ) pxDmaTxDesc->Buffer1Addr, pxDescriptor->pucEthernetBuffer, ulTransmitSize );
\r
639 /* Move the buffer. */
\r
640 pxDmaTxDesc->Buffer1Addr = ( uint32_t )pxDescriptor->pucEthernetBuffer;
\r
641 /* The Network Buffer has been passed to DMA, no need to release it. */
\r
642 bReleaseAfterSend = pdFALSE_UNSIGNED;
\r
644 #endif /* ipconfigZERO_COPY_TX_DRIVER */
\r
646 /* Ask to set the IPv4 checksum.
\r
647 Also need an Interrupt on Completion so that 'vClearTXBuffers()' will be called.. */
\r
648 pxDmaTxDesc->Status |= ETH_DMATXDESC_CIC_TCPUDPICMP_FULL | ETH_DMATXDESC_IC;
\r
650 /* Prepare transmit descriptors to give to DMA. */
\r
652 /* Set LAST and FIRST segment */
\r
653 pxDmaTxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS;
\r
654 /* Set frame size */
\r
655 pxDmaTxDesc->ControlBufferSize = ( ulTransmitSize & ETH_DMATXDESC_TBS1 );
\r
656 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
\r
657 pxDmaTxDesc->Status |= ETH_DMATXDESC_OWN;
\r
659 /* Point to next descriptor */
\r
660 xETH.TxDesc = ( ETH_DMADescTypeDef * ) ( xETH.TxDesc->Buffer2NextDescAddr );
\r
661 /* Ensure completion of memory access */
\r
663 /* Resume DMA transmission*/
\r
664 xETH.Instance->DMATPDR = 0;
\r
665 iptraceNETWORK_INTERFACE_TRANSMIT();
\r
671 /* The PHY has no Link Status, packet shall be dropped. */
\r
674 /* The buffer has been sent so can be released. */
\r
675 if( bReleaseAfterSend != pdFALSE )
\r
677 vReleaseNetworkBufferAndDescriptor( pxDescriptor );
\r
682 /*-----------------------------------------------------------*/
\r
684 static BaseType_t xMayAcceptPacket( uint8_t *pcBuffer )
\r
686 const ProtocolPacket_t *pxProtPacket = ( const ProtocolPacket_t * )pcBuffer;
\r
688 switch( pxProtPacket->xTCPPacket.xEthernetHeader.usFrameType )
\r
690 case ipARP_FRAME_TYPE:
\r
691 /* Check it later. */
\r
693 case ipIPv4_FRAME_TYPE:
\r
694 /* Check it here. */
\r
697 /* Refuse the packet. */
\r
701 #if( ipconfigETHERNET_DRIVER_FILTERS_PACKETS == 1 )
\r
703 const IPHeader_t *pxIPHeader = &(pxProtPacket->xTCPPacket.xIPHeader);
\r
704 uint32_t ulDestinationIPAddress;
\r
706 /* Ensure that the incoming packet is not fragmented (only outgoing packets
\r
707 * can be fragmented) as these are the only handled IP frames currently. */
\r
708 if( ( pxIPHeader->usFragmentOffset & FreeRTOS_ntohs( ipFRAGMENT_OFFSET_BIT_MASK ) ) != 0U )
\r
712 /* HT: Might want to make the following configurable because
\r
713 * most IP messages have a standard length of 20 bytes */
\r
715 /* 0x45 means: IPv4 with an IP header of 5 x 4 = 20 bytes
\r
716 * 0x47 means: IPv4 with an IP header of 7 x 4 = 28 bytes */
\r
717 if( pxIPHeader->ucVersionHeaderLength < 0x45 || pxIPHeader->ucVersionHeaderLength > 0x4F )
\r
722 ulDestinationIPAddress = pxIPHeader->ulDestinationIPAddress;
\r
723 /* Is the packet for this node? */
\r
724 if( ( ulDestinationIPAddress != *ipLOCAL_IP_ADDRESS_POINTER ) &&
\r
725 /* Is it a broadcast address x.x.x.255 ? */
\r
726 ( ( FreeRTOS_ntohl( ulDestinationIPAddress ) & 0xff ) != 0xff ) &&
\r
727 #if( ipconfigUSE_LLMNR == 1 )
\r
728 ( ulDestinationIPAddress != ipLLMNR_IP_ADDR ) &&
\r
730 ( *ipLOCAL_IP_ADDRESS_POINTER != 0 ) ) {
\r
731 FreeRTOS_printf( ( "Drop IP %lxip\n", FreeRTOS_ntohl( ulDestinationIPAddress ) ) );
\r
735 if( pxIPHeader->ucProtocol == ipPROTOCOL_UDP )
\r
737 uint16_t port = pxProtPacket->xUDPPacket.xUDPHeader.usDestinationPort;
\r
739 if( ( xPortHasUDPSocket( port ) == pdFALSE )
\r
740 #if ipconfigUSE_LLMNR == 1
\r
741 && ( port != FreeRTOS_ntohs( ipLLMNR_PORT ) )
\r
743 #if ipconfigUSE_NBNS == 1
\r
744 && ( port != FreeRTOS_ntohs( ipNBNS_PORT ) )
\r
746 #if ipconfigUSE_DNS == 1
\r
747 && ( pxProtPacket->xUDPPacket.xUDPHeader.usSourcePort != FreeRTOS_ntohs( ipDNS_PORT ) )
\r
750 /* Drop this packet, not for this device. */
\r
755 #endif /* ipconfigETHERNET_DRIVER_FILTERS_PACKETS */
\r
758 /*-----------------------------------------------------------*/
\r
760 static BaseType_t prvNetworkInterfaceInput( void )
\r
762 NetworkBufferDescriptor_t *pxCurDescriptor;
\r
763 NetworkBufferDescriptor_t *pxNewDescriptor = NULL;
\r
764 BaseType_t xReceivedLength, xAccepted;
\r
765 __IO ETH_DMADescTypeDef *pxDMARxDescriptor;
\r
766 xIPStackEvent_t xRxEvent = { eNetworkRxEvent, NULL };
\r
767 const TickType_t xDescriptorWaitTime = pdMS_TO_TICKS( 250 );
\r
768 uint8_t *pucBuffer;
\r
770 pxDMARxDescriptor = xETH.RxDesc;
\r
772 if( ( pxDMARxDescriptor->Status & ETH_DMARXDESC_OWN) == 0 )
\r
774 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
\r
775 xReceivedLength = ( ( pxDMARxDescriptor->Status & ETH_DMARXDESC_FL ) >> ETH_DMARXDESC_FRAMELENGTHSHIFT ) - 4;
\r
777 pucBuffer = (uint8_t *) pxDMARxDescriptor->Buffer1Addr;
\r
779 /* Update the ETHERNET DMA global Rx descriptor with next Rx descriptor */
\r
780 /* Chained Mode */
\r
781 /* Selects the next DMA Rx descriptor list for next buffer to read */
\r
782 xETH.RxDesc = ( ETH_DMADescTypeDef* )pxDMARxDescriptor->Buffer2NextDescAddr;
\r
786 xReceivedLength = 0;
\r
789 /* Obtain the size of the packet and put it into the "usReceivedLength" variable. */
\r
791 /* get received frame */
\r
792 if( xReceivedLength > 0ul )
\r
794 /* In order to make the code easier and faster, only packets in a single buffer
\r
795 will be accepted. This can be done by making the buffers large enough to
\r
796 hold a complete Ethernet packet (1536 bytes).
\r
797 Therefore, two sanity checks: */
\r
798 configASSERT( xReceivedLength <= ETH_RX_BUF_SIZE );
\r
800 if( ( pxDMARxDescriptor->Status & ( ETH_DMARXDESC_CE | ETH_DMARXDESC_IPV4HCE | ETH_DMARXDESC_FT ) ) != ETH_DMARXDESC_FT )
\r
802 /* Not an Ethernet frame-type or a checmsum error. */
\r
803 xAccepted = pdFALSE;
\r
807 /* See if this packet must be handled. */
\r
808 xAccepted = xMayAcceptPacket( pucBuffer );
\r
811 if( xAccepted != pdFALSE )
\r
813 /* The packet wil be accepted, but check first if a new Network Buffer can
\r
814 be obtained. If not, the packet will still be dropped. */
\r
815 pxNewDescriptor = pxGetNetworkBufferWithDescriptor( ETH_RX_BUF_SIZE, xDescriptorWaitTime );
\r
817 if( pxNewDescriptor == NULL )
\r
819 /* A new descriptor can not be allocated now. This packet will be dropped. */
\r
820 xAccepted = pdFALSE;
\r
823 #if( ipconfigZERO_COPY_RX_DRIVER != 0 )
\r
825 /* Find out which Network Buffer was originally passed to the descriptor. */
\r
826 pxCurDescriptor = pxPacketBuffer_to_NetworkBuffer( pucBuffer );
\r
827 configASSERT( pxCurDescriptor != NULL );
\r
831 /* In this mode, the two descriptors are the same. */
\r
832 pxCurDescriptor = pxNewDescriptor;
\r
833 if( pxNewDescriptor != NULL )
\r
835 /* The packet is acepted and a new Network Buffer was created,
\r
836 copy data to the Network Bufffer. */
\r
837 memcpy( pxNewDescriptor->pucEthernetBuffer, pucBuffer, xReceivedLength );
\r
842 if( xAccepted != pdFALSE )
\r
844 pxCurDescriptor->xDataLength = xReceivedLength;
\r
845 xRxEvent.pvData = ( void * ) pxCurDescriptor;
\r
847 /* Pass the data to the TCP/IP task for processing. */
\r
848 if( xSendEventStructToIPTask( &xRxEvent, xDescriptorWaitTime ) == pdFALSE )
\r
850 /* Could not send the descriptor into the TCP/IP stack, it
\r
851 must be released. */
\r
852 vReleaseNetworkBufferAndDescriptor( pxCurDescriptor );
\r
853 iptraceETHERNET_RX_EVENT_LOST();
\r
857 iptraceNETWORK_INTERFACE_RECEIVE();
\r
861 /* Release descriptors to DMA */
\r
862 #if( ipconfigZERO_COPY_RX_DRIVER != 0 )
\r
864 /* Set Buffer1 address pointer */
\r
865 if( pxNewDescriptor != NULL )
\r
867 pxDMARxDescriptor->Buffer1Addr = (uint32_t)pxNewDescriptor->pucEthernetBuffer;
\r
871 /* The packet was dropped and the same Network
\r
872 Buffer will be used to receive a new packet. */
\r
875 #endif /* ipconfigZERO_COPY_RX_DRIVER */
\r
877 /* Set Buffer1 size and Second Address Chained bit */
\r
878 pxDMARxDescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | (uint32_t)ETH_RX_BUF_SIZE;
\r
879 pxDMARxDescriptor->Status = ETH_DMARXDESC_OWN;
\r
881 /* Ensure completion of memory access */
\r
883 /* When Rx Buffer unavailable flag is set clear it and resume
\r
885 if( ( xETH.Instance->DMASR & ETH_DMASR_RBUS ) != 0 )
\r
887 /* Clear RBUS ETHERNET DMA flag. */
\r
888 xETH.Instance->DMASR = ETH_DMASR_RBUS;
\r
890 /* Resume DMA reception. */
\r
891 xETH.Instance->DMARPDR = 0;
\r
895 return ( xReceivedLength > 0 );
\r
897 /*-----------------------------------------------------------*/
\r
900 BaseType_t xSTM32_PhyRead( BaseType_t xAddress, BaseType_t xRegister, uint32_t *pulValue )
\r
902 uint16_t usPrevAddress = xETH.Init.PhyAddress;
\r
903 BaseType_t xResult;
\r
904 HAL_StatusTypeDef xHALResult;
\r
906 xETH.Init.PhyAddress = xAddress;
\r
907 xHALResult = HAL_ETH_ReadPHYRegister( &xETH, ( uint16_t )xRegister, pulValue );
\r
908 xETH.Init.PhyAddress = usPrevAddress;
\r
910 if( xHALResult == HAL_OK )
\r
920 /*-----------------------------------------------------------*/
\r
922 BaseType_t xSTM32_PhyWrite( BaseType_t xAddress, BaseType_t xRegister, uint32_t ulValue )
\r
924 uint16_t usPrevAddress = xETH.Init.PhyAddress;
\r
925 BaseType_t xResult;
\r
926 HAL_StatusTypeDef xHALResult;
\r
928 xETH.Init.PhyAddress = xAddress;
\r
929 xHALResult = HAL_ETH_WritePHYRegister( &xETH, ( uint16_t )xRegister, ulValue );
\r
930 xETH.Init.PhyAddress = usPrevAddress;
\r
932 if( xHALResult == HAL_OK )
\r
942 /*-----------------------------------------------------------*/
\r
946 BaseType_t xPhyCount;
\r
947 BaseType_t xPhyIndex;
\r
949 vPhyInitialise( &xPhyObject, xSTM32_PhyRead, xSTM32_PhyWrite );
\r
950 xPhyCount = xPhyDiscover( &xPhyObject );
\r
951 FreeRTOS_printf( ( "PHY count %ld\n", xPhyCount ) );
\r
952 for( xPhyIndex = 0; xPhyIndex < xPhyCount; xPhyIndex++ )
\r
954 FreeRTOS_printf( ( "PHY[%d] at address %d ( 0x%08X )\n",
\r
956 xPhyObject.ucPhyIndexes[ xPhyIndex ],
\r
957 xPhyObject.ulPhyIDs[ xPhyIndex ] ) );
\r
963 void vMACBProbePhy( void )
\r
965 vPhyInitialise( &xPhyObject, xSTM32_PhyRead, xSTM32_PhyWrite );
\r
966 xPhyDiscover( &xPhyObject );
\r
967 xPhyConfigure( &xPhyObject, &xPHYProperties );
\r
969 /*-----------------------------------------------------------*/
\r
971 static void prvEthernetUpdateConfig( BaseType_t xForce )
\r
973 FreeRTOS_printf( ( "prvEthernetUpdateConfig: LS mask %02lX Force %d\n",
\r
974 xPhyObject.ulLinkStatusMask,
\r
977 if( ( xForce != pdFALSE ) || ( xPhyObject.ulLinkStatusMask != 0 ) )
\r
979 /* Restart the auto-negotiation. */
\r
980 if( xETH.Init.AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE )
\r
982 xPhyStartAutoNegotiation( &xPhyObject, xPhyGetMask( &xPhyObject ) );
\r
984 /* Configure the MAC with the Duplex Mode fixed by the
\r
985 auto-negotiation process. */
\r
986 if( xPhyObject.xPhyProperties.ucDuplex == PHY_DUPLEX_FULL )
\r
988 xETH.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
\r
992 xETH.Init.DuplexMode = ETH_MODE_HALFDUPLEX;
\r
995 /* Configure the MAC with the speed fixed by the
\r
996 auto-negotiation process. */
\r
997 if( xPhyObject.xPhyProperties.ucSpeed == PHY_SPEED_10 )
\r
999 xETH.Init.Speed = ETH_SPEED_10M;
\r
1003 xETH.Init.Speed = ETH_SPEED_100M;
\r
1006 else /* AutoNegotiation Disable */
\r
1008 /* Check parameters */
\r
1009 assert_param( IS_ETH_SPEED( xETH.Init.Speed ) );
\r
1010 assert_param( IS_ETH_DUPLEX_MODE( xETH.Init.DuplexMode ) );
\r
1012 if( xETH.Init.DuplexMode == ETH_MODE_FULLDUPLEX )
\r
1014 xPhyObject.xPhyPreferences.ucDuplex = PHY_DUPLEX_HALF;
\r
1018 xPhyObject.xPhyPreferences.ucDuplex = PHY_DUPLEX_FULL;
\r
1021 if( xETH.Init.Speed == ETH_SPEED_10M )
\r
1023 xPhyObject.xPhyPreferences.ucSpeed = PHY_SPEED_10;
\r
1027 xPhyObject.xPhyPreferences.ucSpeed = PHY_SPEED_100;
\r
1030 xPhyObject.xPhyPreferences.ucMDI_X = PHY_MDIX_AUTO;
\r
1032 /* Use predefined (fixed) configuration. */
\r
1033 xPhyFixedValue( &xPhyObject, xPhyGetMask( &xPhyObject ) );
\r
1036 /* ETHERNET MAC Re-Configuration */
\r
1037 HAL_ETH_ConfigMAC( &xETH, (ETH_MACInitTypeDef *) NULL);
\r
1039 /* Restart MAC interface */
\r
1040 HAL_ETH_Start( &xETH);
\r
1044 /* Stop MAC interface */
\r
1045 HAL_ETH_Stop( &xETH );
\r
1048 /*-----------------------------------------------------------*/
\r
1050 BaseType_t xGetPhyLinkStatus( void )
\r
1052 BaseType_t xReturn;
\r
1054 if( xPhyObject.ulLinkStatusMask != 0 )
\r
1065 /*-----------------------------------------------------------*/
\r
1067 /* Uncomment this in case BufferAllocation_1.c is used. */
\r
1070 #define niBUFFER_1_PACKET_SIZE 1536
\r
1072 static __attribute__ ((section(".first_data"))) uint8_t ucNetworkPackets[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS * niBUFFER_1_PACKET_SIZE ] __attribute__ ( ( aligned( 32 ) ) );
\r
1074 void vNetworkInterfaceAllocateRAMToBuffers( NetworkBufferDescriptor_t pxNetworkBuffers[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ] )
\r
1077 uint8_t *ucRAMBuffer = ucNetworkPackets;
\r
1080 for( ul = 0; ul < ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS; ul++ )
\r
1082 pxNetworkBuffers[ ul ].pucEthernetBuffer = ucRAMBuffer + ipBUFFER_PADDING;
\r
1083 *( ( unsigned * ) ucRAMBuffer ) = ( unsigned ) ( &( pxNetworkBuffers[ ul ] ) );
\r
1084 ucRAMBuffer += niBUFFER_1_PACKET_SIZE;
\r
1088 /*-----------------------------------------------------------*/
\r
1090 static void prvEMACHandlerTask( void *pvParameters )
\r
1092 UBaseType_t uxLastMinBufferCount = 0;
\r
1093 #if( ipconfigCHECK_IP_QUEUE_SPACE != 0 )
\r
1094 UBaseType_t uxLastMinQueueSpace = 0;
\r
1096 UBaseType_t uxCurrentCount;
\r
1097 BaseType_t xResult;
\r
1098 const TickType_t ulMaxBlockTime = pdMS_TO_TICKS( 100UL );
\r
1100 /* Remove compiler warnings about unused parameters. */
\r
1101 ( void ) pvParameters;
\r
1106 uxCurrentCount = uxGetMinimumFreeNetworkBuffers();
\r
1107 if( uxLastMinBufferCount != uxCurrentCount )
\r
1109 /* The logging produced below may be helpful
\r
1110 while tuning +TCP: see how many buffers are in use. */
\r
1111 uxLastMinBufferCount = uxCurrentCount;
\r
1112 FreeRTOS_printf( ( "Network buffers: %lu lowest %lu\n",
\r
1113 uxGetNumberOfFreeNetworkBuffers(), uxCurrentCount ) );
\r
1116 if( xTXDescriptorSemaphore != NULL )
\r
1118 static UBaseType_t uxLowestSemCount = ( UBaseType_t ) ETH_TXBUFNB - 1;
\r
1120 uxCurrentCount = uxSemaphoreGetCount( xTXDescriptorSemaphore );
\r
1121 if( uxLowestSemCount > uxCurrentCount )
\r
1123 uxLowestSemCount = uxCurrentCount;
\r
1124 FreeRTOS_printf( ( "TX DMA buffers: lowest %lu\n", uxLowestSemCount ) );
\r
1129 #if( ipconfigCHECK_IP_QUEUE_SPACE != 0 )
\r
1131 uxCurrentCount = uxGetMinimumIPQueueSpace();
\r
1132 if( uxLastMinQueueSpace != uxCurrentCount )
\r
1134 /* The logging produced below may be helpful
\r
1135 while tuning +TCP: see how many buffers are in use. */
\r
1136 uxLastMinQueueSpace = uxCurrentCount;
\r
1137 FreeRTOS_printf( ( "Queue space: lowest %lu\n", uxCurrentCount ) );
\r
1140 #endif /* ipconfigCHECK_IP_QUEUE_SPACE */
\r
1142 if( ( ulISREvents & EMAC_IF_ALL_EVENT ) == 0 )
\r
1144 /* No events to process now, wait for the next. */
\r
1145 ulTaskNotifyTake( pdFALSE, ulMaxBlockTime );
\r
1148 if( ( ulISREvents & EMAC_IF_RX_EVENT ) != 0 )
\r
1150 ulISREvents &= ~EMAC_IF_RX_EVENT;
\r
1152 xResult = prvNetworkInterfaceInput();
\r
1155 while( prvNetworkInterfaceInput() > 0 )
\r
1161 if( ( ulISREvents & EMAC_IF_TX_EVENT ) != 0 )
\r
1163 /* Code to release TX buffers if zero-copy is used. */
\r
1164 ulISREvents &= ~EMAC_IF_TX_EVENT;
\r
1165 /* Check if DMA packets have been delivered. */
\r
1166 vClearTXBuffers();
\r
1169 if( ( ulISREvents & EMAC_IF_ERR_EVENT ) != 0 )
\r
1171 /* Future extension: logging about errors that occurred. */
\r
1172 ulISREvents &= ~EMAC_IF_ERR_EVENT;
\r
1174 if( xPhyCheckLinkStatus( &xPhyObject, xResult ) != 0 )
\r
1176 /* Something has changed to a Link Status, need re-check. */
\r
1177 prvEthernetUpdateConfig( pdFALSE );
\r
1181 /*-----------------------------------------------------------*/
\r
1183 void ETH_IRQHandler( void )
\r
1185 HAL_ETH_IRQHandler( &xETH );
\r