2 * Some constants, hardware definitions and comments taken from ST's HAL driver
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3 * library, COPYRIGHT(c) 2015 STMicroelectronics.
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8 Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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10 Permission is hereby granted, free of charge, to any person obtaining a copy of
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11 this software and associated documentation files (the "Software"), to deal in
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12 the Software without restriction, including without limitation the rights to
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13 use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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14 the Software, and to permit persons to whom the Software is furnished to do so,
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15 subject to the following conditions:
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17 The above copyright notice and this permission notice shall be included in all
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18 copies or substantial portions of the Software.
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20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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21 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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22 FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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23 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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24 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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25 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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27 http://aws.amazon.com/freertos
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28 http://www.FreeRTOS.org
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31 /* Standard includes. */
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36 /* FreeRTOS includes. */
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37 #include "FreeRTOS.h"
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42 /* FreeRTOS+TCP includes. */
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43 #include "FreeRTOS_IP.h"
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44 #include "FreeRTOS_Sockets.h"
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45 #include "FreeRTOS_IP_Private.h"
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46 #include "FreeRTOS_DNS.h"
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47 #include "FreeRTOS_ARP.h"
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48 #include "NetworkBufferManagement.h"
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49 #include "NetworkInterface.h"
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50 #include "phyHandling.h"
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53 #if defined( STM32F7xx )
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54 #include "stm32f7xx_hal.h"
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55 #elif defined( STM32F4xx )
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56 #include "stm32f4xx_hal.h"
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57 #elif defined( STM32F2xx )
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58 #include "stm32f2xx_hal.h"
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59 #elif !defined( _lint ) /* Lint does not like an #error */
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63 #include "stm32fxx_hal_eth.h"
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65 /* Interrupt events to process. Currently only the Rx event is processed
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66 although code for other events is included to allow for possible future
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68 #define EMAC_IF_RX_EVENT 1UL
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69 #define EMAC_IF_TX_EVENT 2UL
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70 #define EMAC_IF_ERR_EVENT 4UL
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71 #define EMAC_IF_ALL_EVENT ( EMAC_IF_RX_EVENT | EMAC_IF_TX_EVENT | EMAC_IF_ERR_EVENT )
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73 #define ETH_DMA_ALL_INTS \
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74 ( ETH_DMA_IT_TST | ETH_DMA_IT_PMT | ETH_DMA_IT_MMC | ETH_DMA_IT_NIS | ETH_DMA_IT_ER | \
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75 ETH_DMA_IT_FBE | ETH_DMA_IT_RWT | ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | \
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76 ETH_DMA_IT_TU | ETH_DMA_IT_RO | ETH_DMA_IT_TJT | ETH_DMA_IT_TPS | ETH_DMA_IT_T )
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78 #ifndef niEMAC_HANDLER_TASK_PRIORITY
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79 #define niEMAC_HANDLER_TASK_PRIORITY configMAX_PRIORITIES - 1
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82 #define ipFRAGMENT_OFFSET_BIT_MASK ( ( uint16_t ) 0x0fff ) /* The bits in the two byte IP header field that make up the fragment offset value. */
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84 #if( ( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM == 0 ) || ( ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM == 0 ) )
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85 #warning Consider enabling checksum offloading
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88 #ifndef niDESCRIPTOR_WAIT_TIME_MS
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89 #define niDESCRIPTOR_WAIT_TIME_MS 250uL
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93 * Most users will want a PHY that negotiates about
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94 * the connection properties: speed, dmix and duplex.
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95 * On some rare cases, you want to select what is being
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96 * advertised, properties like MDIX and duplex.
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99 #if !defined( ipconfigETHERNET_AN_ENABLE )
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100 /* Enable auto-negotiation */
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101 #define ipconfigETHERNET_AN_ENABLE 1
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104 #if !defined( ipconfigETHERNET_AUTO_CROSS_ENABLE )
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105 #define ipconfigETHERNET_AUTO_CROSS_ENABLE 1
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108 #if( ipconfigETHERNET_AN_ENABLE == 0 )
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110 * The following three defines are only used in case there
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111 * is no auto-negotiation.
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113 #if !defined( ipconfigETHERNET_CROSSED_LINK )
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114 #define ipconfigETHERNET_CROSSED_LINK 1
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117 #if !defined( ipconfigETHERNET_USE_100MB )
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118 #define ipconfigETHERNET_USE_100MB 1
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121 #if !defined( ipconfigETHERNET_USE_FULL_DUPLEX )
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122 #define ipconfigETHERNET_USE_FULL_DUPLEX 1
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124 #endif /* ipconfigETHERNET_AN_ENABLE == 0 */
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126 /* Default the size of the stack used by the EMAC deferred handler task to twice
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127 the size of the stack used by the idle task - but allow this to be overridden in
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128 FreeRTOSConfig.h as configMINIMAL_STACK_SIZE is a user definable constant. */
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129 #ifndef configEMAC_TASK_STACK_SIZE
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130 #define configEMAC_TASK_STACK_SIZE ( 2 * configMINIMAL_STACK_SIZE )
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133 /* Two choices must be made: RMII versus MII,
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134 and the index of the PHY in use ( between 0 and 31 ). */
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135 #ifndef ipconfigUSE_RMII
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137 #define ipconfigUSE_RMII 1
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139 #define ipconfigUSE_RMII 0
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140 #endif /* STM32F7xx */
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141 #endif /* ipconfigUSE_RMII */
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143 #if( ipconfigUSE_RMII != 0 )
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144 #warning Using RMII, make sure if this is correct
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146 #warning Using MII, make sure if this is correct
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151 eMACInit, /* Must initialise MAC. */
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152 eMACPass, /* Initialisation was successful. */
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153 eMACFailed, /* Initialisation failed. */
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154 } eMAC_INIT_STATUS_TYPE;
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156 static eMAC_INIT_STATUS_TYPE xMacInitStatus = eMACInit;
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158 /*-----------------------------------------------------------*/
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161 * A deferred interrupt handler task that processes
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163 static void prvEMACHandlerTask( void *pvParameters );
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166 * Force a negotiation with the Switch or Router and wait for LS.
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168 static void prvEthernetUpdateConfig( BaseType_t xForce );
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171 * See if there is a new packet and forward it to the IP-task.
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173 static BaseType_t prvNetworkInterfaceInput( void );
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175 #if( ipconfigUSE_LLMNR != 0 )
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177 * For LLMNR, an extra MAC-address must be configured to
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178 * be able to receive the multicast messages.
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180 static void prvMACAddressConfig(ETH_HandleTypeDef *heth, uint32_t ulIndex, uint8_t *Addr);
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184 * Check if a given packet should be accepted.
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186 static BaseType_t xMayAcceptPacket( uint8_t *pcBuffer );
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189 * Initialise the TX descriptors.
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191 static void prvDMATxDescListInit( void );
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194 * Initialise the RX descriptors.
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196 static void prvDMARxDescListInit( void );
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198 /* After packets have been sent, the network
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199 buffers will be released. */
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200 static void vClearTXBuffers( void );
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202 /*-----------------------------------------------------------*/
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204 /* Bit map of outstanding ETH interrupt events for processing. Currently only
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205 the Rx interrupt is handled, although code is included for other events to
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206 enable future expansion. */
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207 static volatile uint32_t ulISREvents;
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209 #if( ipconfigUSE_LLMNR == 1 )
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210 static const uint8_t xLLMNR_MACAddress[] = { 0x01, 0x00, 0x5E, 0x00, 0x00, 0xFC };
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213 static EthernetPhy_t xPhyObject;
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215 /* Ethernet handle. */
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216 static ETH_HandleTypeDef xETH;
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218 /* xTXDescriptorSemaphore is a counting semaphore with
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219 a maximum count of ETH_TXBUFNB, which is the number of
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220 DMA TX descriptors. */
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221 static SemaphoreHandle_t xTXDescriptorSemaphore = NULL;
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224 * Note: it is adviced to define both
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226 * #define ipconfigZERO_COPY_RX_DRIVER 1
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227 * #define ipconfigZERO_COPY_TX_DRIVER 1
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229 * The method using memcpy is slower and probaly uses more RAM memory.
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230 * The possibility is left in the code just for comparison.
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232 * It is adviced to define ETH_TXBUFNB at least 4. Note that no
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233 * TX buffers are allocated in a zero-copy driver.
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235 /* MAC buffers: ---------------------------------------------------------*/
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237 /* Put the DMA descriptors in '.first_data'.
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238 This is important for STM32F7, which has an L1 data cache.
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239 The first 64KB of the SRAM is not cached. */
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241 /* Ethernet Rx MA Descriptor */
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242 __attribute__ ((aligned (32)))
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243 __attribute__ ((section(".first_data")))
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244 ETH_DMADescTypeDef DMARxDscrTab[ ETH_RXBUFNB ];
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246 #if( ipconfigZERO_COPY_RX_DRIVER == 0 )
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247 /* Ethernet Receive Buffer */
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248 __ALIGN_BEGIN uint8_t Rx_Buff[ ETH_RXBUFNB ][ ETH_RX_BUF_SIZE ] __ALIGN_END;
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251 /* Ethernet Tx DMA Descriptor */
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252 __attribute__ ((aligned (32)))
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253 __attribute__ ((section(".first_data")))
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254 ETH_DMADescTypeDef DMATxDscrTab[ ETH_TXBUFNB ];
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256 #if( ipconfigZERO_COPY_TX_DRIVER == 0 )
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257 /* Ethernet Transmit Buffer */
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258 __ALIGN_BEGIN uint8_t Tx_Buff[ ETH_TXBUFNB ][ ETH_TX_BUF_SIZE ] __ALIGN_END;
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261 /* DMATxDescToClear points to the next TX DMA descriptor
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262 that must be cleared by vClearTXBuffers(). */
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263 static __IO ETH_DMADescTypeDef *DMATxDescToClear;
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265 /* Holds the handle of the task used as a deferred interrupt processor. The
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266 handle is used so direct notifications can be sent to the task for all EMAC/DMA
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267 related interrupts. */
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268 static TaskHandle_t xEMACTaskHandle = NULL;
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270 /* For local use only: describe the PHY's properties: */
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271 const PhyProperties_t xPHYProperties =
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273 #if( ipconfigETHERNET_AN_ENABLE != 0 )
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274 .ucSpeed = PHY_SPEED_AUTO,
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275 .ucDuplex = PHY_DUPLEX_AUTO,
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277 #if( ipconfigETHERNET_USE_100MB != 0 )
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278 .ucSpeed = PHY_SPEED_100,
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280 .ucSpeed = PHY_SPEED_10,
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283 #if( ipconfigETHERNET_USE_FULL_DUPLEX != 0 )
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284 .ucDuplex = PHY_DUPLEX_FULL,
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286 .ucDuplex = PHY_DUPLEX_HALF,
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290 #if( ipconfigETHERNET_AN_ENABLE != 0 ) && ( ipconfigETHERNET_AUTO_CROSS_ENABLE != 0 )
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291 .ucMDI_X = PHY_MDIX_AUTO,
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292 #elif( ipconfigETHERNET_CROSSED_LINK != 0 )
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293 .ucMDI_X = PHY_MDIX_CROSSED,
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295 .ucMDI_X = PHY_MDIX_DIRECT,
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299 /*-----------------------------------------------------------*/
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301 void HAL_ETH_RxCpltCallback( ETH_HandleTypeDef *heth )
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303 BaseType_t xHigherPriorityTaskWoken = pdFALSE;
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307 /* Ethernet RX-Complete callback function, elsewhere declared as weak. */
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308 ulISREvents |= EMAC_IF_RX_EVENT;
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309 /* Wakeup the prvEMACHandlerTask. */
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310 if( xEMACTaskHandle != NULL )
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312 vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken );
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313 portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
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316 /*-----------------------------------------------------------*/
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318 void HAL_ETH_TxCpltCallback( ETH_HandleTypeDef *heth )
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320 BaseType_t xHigherPriorityTaskWoken = pdFALSE;
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324 /* This call-back is only useful in case packets are being sent
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325 zero-copy. Once they're sent, the buffers will be released
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326 by the function vClearTXBuffers(). */
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327 ulISREvents |= EMAC_IF_TX_EVENT;
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328 /* Wakeup the prvEMACHandlerTask. */
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329 if( xEMACTaskHandle != NULL )
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331 vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken );
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332 portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
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335 /*-----------------------------------------------------------*/
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337 static void vClearTXBuffers()
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339 __IO ETH_DMADescTypeDef *txLastDescriptor = xETH.TxDesc;
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340 size_t uxCount = ( ( UBaseType_t ) ETH_TXBUFNB ) - uxSemaphoreGetCount( xTXDescriptorSemaphore );
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341 #if( ipconfigZERO_COPY_TX_DRIVER != 0 )
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342 NetworkBufferDescriptor_t *pxNetworkBuffer;
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343 uint8_t *ucPayLoad;
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346 /* This function is called after a TX-completion interrupt.
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347 It will release each Network Buffer used in xNetworkInterfaceOutput().
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348 'uxCount' represents the number of descriptors given to DMA for transmission.
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349 After sending a packet, the DMA will clear the 'ETH_DMATXDESC_OWN' bit. */
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350 while( ( uxCount > 0 ) && ( ( DMATxDescToClear->Status & ETH_DMATXDESC_OWN ) == 0 ) )
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352 if( ( DMATxDescToClear == txLastDescriptor ) && ( uxCount != ETH_TXBUFNB ) )
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356 #if( ipconfigZERO_COPY_TX_DRIVER != 0 )
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358 ucPayLoad = ( uint8_t * )DMATxDescToClear->Buffer1Addr;
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360 if( ucPayLoad != NULL )
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362 pxNetworkBuffer = pxPacketBuffer_to_NetworkBuffer( ucPayLoad );
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363 if( pxNetworkBuffer != NULL )
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365 vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ) ;
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367 DMATxDescToClear->Buffer1Addr = ( uint32_t )0u;
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370 #endif /* ipconfigZERO_COPY_TX_DRIVER */
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372 DMATxDescToClear = ( ETH_DMADescTypeDef * )( DMATxDescToClear->Buffer2NextDescAddr );
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375 /* Tell the counting semaphore that one more TX descriptor is available. */
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376 xSemaphoreGive( xTXDescriptorSemaphore );
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379 /*-----------------------------------------------------------*/
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381 BaseType_t xNetworkInterfaceInitialise( void )
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383 HAL_StatusTypeDef hal_eth_init_status;
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384 BaseType_t xResult;
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386 if( xMacInitStatus == eMACInit )
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388 xTXDescriptorSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) ETH_TXBUFNB, ( UBaseType_t ) ETH_TXBUFNB );
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389 if( xTXDescriptorSemaphore == NULL )
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391 xMacInitStatus = eMACFailed;
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395 /* Initialise ETH */
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397 xETH.Instance = ETH;
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398 xETH.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
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399 xETH.Init.Speed = ETH_SPEED_100M;
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400 xETH.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
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401 /* Value of PhyAddress doesn't matter, will be probed for. */
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402 xETH.Init.PhyAddress = 0;
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404 xETH.Init.MACAddr = ( uint8_t * ) FreeRTOS_GetMACAddress();
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405 xETH.Init.RxMode = ETH_RXINTERRUPT_MODE;
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407 #if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 )
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409 /* using the ETH_CHECKSUM_BY_HARDWARE option:
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410 both the IP and the protocol checksums will be calculated
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411 by the peripheral. */
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412 xETH.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
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416 xETH.Init.ChecksumMode = ETH_CHECKSUM_BY_SOFTWARE;
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420 #if( ipconfigUSE_RMII != 0 )
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422 xETH.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
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426 xETH.Init.MediaInterface = ETH_MEDIA_INTERFACE_MII;
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428 #endif /* ipconfigUSE_RMII */
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430 hal_eth_init_status = HAL_ETH_Init( &xETH );
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432 /* Only for inspection by debugger. */
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433 ( void ) hal_eth_init_status;
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435 /* Set the TxDesc and RxDesc pointers. */
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436 xETH.TxDesc = DMATxDscrTab;
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437 xETH.RxDesc = DMARxDscrTab;
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439 /* Make sure that all unused fields are cleared. */
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440 memset( &DMATxDscrTab, '\0', sizeof( DMATxDscrTab ) );
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441 memset( &DMARxDscrTab, '\0', sizeof( DMARxDscrTab ) );
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443 /* Initialize Tx Descriptors list: Chain Mode */
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444 DMATxDescToClear = DMATxDscrTab;
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446 /* Initialise TX-descriptors. */
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447 prvDMATxDescListInit();
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449 /* Initialise RX-descriptors. */
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450 prvDMARxDescListInit();
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452 #if( ipconfigUSE_LLMNR != 0 )
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454 /* Program the LLMNR address at index 1. */
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455 prvMACAddressConfig( &xETH, ETH_MAC_ADDRESS1, ( uint8_t *) xLLMNR_MACAddress );
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459 /* Force a negotiation with the Switch or Router and wait for LS. */
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460 prvEthernetUpdateConfig( pdTRUE );
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462 /* The deferred interrupt handler task is created at the highest
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463 possible priority to ensure the interrupt handler can return directly
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464 to it. The task's handle is stored in xEMACTaskHandle so interrupts can
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465 notify the task when there is something to process. */
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466 if( xTaskCreate( prvEMACHandlerTask, "EMAC", configEMAC_TASK_STACK_SIZE, NULL, niEMAC_HANDLER_TASK_PRIORITY, &xEMACTaskHandle ) == pdPASS )
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468 /* The xTXDescriptorSemaphore and the task are created successfully. */
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469 xMacInitStatus = eMACPass;
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473 xMacInitStatus = eMACFailed;
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476 } /* if( xEMACTaskHandle == NULL ) */
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478 if( xMacInitStatus != eMACPass )
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480 /* EMAC initialisation failed, return pdFAIL. */
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485 if( xPhyObject.ulLinkStatusMask != 0uL )
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487 xETH.Instance->DMAIER |= ETH_DMA_ALL_INTS;
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489 FreeRTOS_printf( ( "Link Status is high\n" ) ) ;
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493 /* For now pdFAIL will be returned. But prvEMACHandlerTask() is running
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494 and it will keep on checking the PHY and set 'ulLinkStatusMask' when necessary. */
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498 /* When returning non-zero, the stack will become active and
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499 start DHCP (in configured) */
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502 /*-----------------------------------------------------------*/
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504 static void prvDMATxDescListInit()
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506 ETH_DMADescTypeDef *pxDMADescriptor;
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509 /* Get the pointer on the first member of the descriptor list */
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510 pxDMADescriptor = DMATxDscrTab;
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512 /* Fill each DMA descriptor with the right values */
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513 for( xIndex = 0; xIndex < ETH_TXBUFNB; xIndex++, pxDMADescriptor++ )
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515 /* Set Second Address Chained bit */
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516 pxDMADescriptor->Status = ETH_DMATXDESC_TCH;
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518 #if( ipconfigZERO_COPY_TX_DRIVER == 0 )
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520 /* Set Buffer1 address pointer */
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521 pxDMADescriptor->Buffer1Addr = ( uint32_t )( Tx_Buff[ xIndex ] );
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525 if( xETH.Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE )
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527 /* Set the DMA Tx descriptors checksum insertion for TCP, UDP, and ICMP */
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528 pxDMADescriptor->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
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532 pxDMADescriptor->Status &= ~( ( uint32_t ) ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL );
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535 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
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536 if( xIndex < ETH_TXBUFNB - 1 )
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538 /* Set next descriptor address register with next descriptor base address */
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539 pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) ( pxDMADescriptor + 1 );
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543 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
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544 pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) DMATxDscrTab;
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548 /* Set Transmit Descriptor List Address Register */
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549 xETH.Instance->DMATDLAR = ( uint32_t ) DMATxDscrTab;
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551 /*-----------------------------------------------------------*/
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553 static void prvDMARxDescListInit()
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555 ETH_DMADescTypeDef *pxDMADescriptor;
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561 /* Get the pointer on the first member of the descriptor list */
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562 pxDMADescriptor = DMARxDscrTab;
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564 /* Fill each DMA descriptor with the right values */
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565 for( xIndex = 0; xIndex < ETH_RXBUFNB; xIndex++, pxDMADescriptor++ )
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568 /* Set Buffer1 size and Second Address Chained bit */
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569 pxDMADescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | (uint32_t)ETH_RX_BUF_SIZE;
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571 #if( ipconfigZERO_COPY_RX_DRIVER != 0 )
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573 /* Set Buffer1 address pointer */
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574 NetworkBufferDescriptor_t *pxBuffer;
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576 pxBuffer = pxGetNetworkBufferWithDescriptor( ETH_RX_BUF_SIZE, 100ul );
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577 /* If the assert below fails, make sure that there are at least 'ETH_RXBUFNB'
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578 Network Buffers available during start-up ( ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ) */
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579 configASSERT( pxBuffer != NULL );
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580 if( pxBuffer != NULL )
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582 pxDMADescriptor->Buffer1Addr = (uint32_t)pxBuffer->pucEthernetBuffer;
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583 pxDMADescriptor->Status = ETH_DMARXDESC_OWN;
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588 /* Set Buffer1 address pointer */
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589 pxDMADescriptor->Buffer1Addr = ( uint32_t )( Rx_Buff[ xIndex ] );
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590 /* Set Own bit of the Rx descriptor Status */
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591 pxDMADescriptor->Status = ETH_DMARXDESC_OWN;
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595 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
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596 if( xIndex < ETH_RXBUFNB - 1 )
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598 /* Set next descriptor address register with next descriptor base address */
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599 pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t )( pxDMADescriptor + 1 );
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603 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
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604 pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) DMARxDscrTab;
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608 /* Set Receive Descriptor List Address Register */
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609 xETH.Instance->DMARDLAR = ( uint32_t ) DMARxDscrTab;
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611 /*-----------------------------------------------------------*/
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613 static void prvMACAddressConfig(ETH_HandleTypeDef *heth, uint32_t ulIndex, uint8_t *Addr)
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615 uint32_t ulTempReg;
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619 /* Calculate the selected MAC address high register. */
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620 ulTempReg = 0x80000000ul | ( ( uint32_t ) Addr[ 5 ] << 8 ) | ( uint32_t ) Addr[ 4 ];
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622 /* Load the selected MAC address high register. */
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623 ( *(__IO uint32_t *)( ( uint32_t ) ( ETH_MAC_ADDR_HBASE + ulIndex ) ) ) = ulTempReg;
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625 /* Calculate the selected MAC address low register. */
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626 ulTempReg = ( ( uint32_t ) Addr[ 3 ] << 24 ) | ( ( uint32_t ) Addr[ 2 ] << 16 ) | ( ( uint32_t ) Addr[ 1 ] << 8 ) | Addr[ 0 ];
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628 /* Load the selected MAC address low register */
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629 ( *(__IO uint32_t *) ( ( uint32_t ) ( ETH_MAC_ADDR_LBASE + ulIndex ) ) ) = ulTempReg;
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631 /*-----------------------------------------------------------*/
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633 BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxDescriptor, BaseType_t bReleaseAfterSend )
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635 BaseType_t xReturn = pdFAIL;
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636 uint32_t ulTransmitSize = 0;
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637 __IO ETH_DMADescTypeDef *pxDmaTxDesc;
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638 /* Do not wait too long for a free TX DMA buffer. */
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639 const TickType_t xBlockTimeTicks = pdMS_TO_TICKS( 50u );
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641 /* Open a do {} while ( 0 ) loop to be able to call break. */
\r
644 if( xCheckLoopback( pxDescriptor, bReleaseAfterSend ) != 0 )
\r
646 /* The packet has been sent back to the IP-task.
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647 The IP-task will further handle it.
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648 Do not release the descriptor. */
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649 bReleaseAfterSend = pdFALSE;
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652 #if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 )
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654 ProtocolPacket_t *pxPacket;
\r
656 /* If the peripheral must calculate the checksum, it wants
\r
657 the protocol checksum to have a value of zero. */
\r
658 pxPacket = ( ProtocolPacket_t * ) ( pxDescriptor->pucEthernetBuffer );
\r
660 if( pxPacket->xICMPPacket.xIPHeader.ucProtocol == ( uint8_t ) ipPROTOCOL_ICMP )
\r
662 pxPacket->xICMPPacket.xICMPHeader.usChecksum = ( uint16_t )0u;
\r
665 #endif /* ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM */
\r
666 if( xPhyObject.ulLinkStatusMask != 0 )
\r
668 if( xSemaphoreTake( xTXDescriptorSemaphore, xBlockTimeTicks ) != pdPASS )
\r
670 /* Time-out waiting for a free TX descriptor. */
\r
674 /* This function does the actual transmission of the packet. The packet is
\r
675 contained in 'pxDescriptor' that is passed to the function. */
\r
676 pxDmaTxDesc = xETH.TxDesc;
\r
678 /* Is this buffer available? */
\r
679 configASSERT ( ( pxDmaTxDesc->Status & ETH_DMATXDESC_OWN ) == 0 );
\r
682 /* Is this buffer available? */
\r
683 /* Get bytes in current buffer. */
\r
684 ulTransmitSize = pxDescriptor->xDataLength;
\r
686 if( ulTransmitSize > ETH_TX_BUF_SIZE )
\r
688 ulTransmitSize = ETH_TX_BUF_SIZE;
\r
691 #if( ipconfigZERO_COPY_TX_DRIVER == 0 )
\r
693 /* Copy the bytes. */
\r
694 memcpy( ( void * ) pxDmaTxDesc->Buffer1Addr, pxDescriptor->pucEthernetBuffer, ulTransmitSize );
\r
698 configASSERT( bReleaseAfterSend != 0 );
\r
700 /* Move the buffer. */
\r
701 pxDmaTxDesc->Buffer1Addr = ( uint32_t )pxDescriptor->pucEthernetBuffer;
\r
702 /* The Network Buffer has been passed to DMA, no need to release it. */
\r
703 bReleaseAfterSend = pdFALSE_UNSIGNED;
\r
705 #endif /* ipconfigZERO_COPY_TX_DRIVER */
\r
707 /* Ask to set the IPv4 checksum.
\r
708 Also need an Interrupt on Completion so that 'vClearTXBuffers()' will be called.. */
\r
709 #if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 )
\r
711 pxDmaTxDesc->Status |= ETH_DMATXDESC_CIC_TCPUDPICMP_FULL | ETH_DMATXDESC_IC;
\r
715 pxDmaTxDesc->Status &= ~( ( uint32_t ) ETH_DMATXDESC_CIC );
\r
716 pxDmaTxDesc->Status |= ETH_DMATXDESC_IC;
\r
721 /* Prepare transmit descriptors to give to DMA. */
\r
723 /* Set LAST and FIRST segment */
\r
724 pxDmaTxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS;
\r
725 /* Set frame size */
\r
726 pxDmaTxDesc->ControlBufferSize = ( ulTransmitSize & ETH_DMATXDESC_TBS1 );
\r
728 #if( NETWORK_BUFFERS_CACHED != 0 )
\r
730 BaseType_t xlength = CACHE_LINE_SIZE * ( ( ulTransmitSize + NETWORK_BUFFER_HEADER_SIZE + CACHE_LINE_SIZE - 1 ) / CACHE_LINE_SIZE );
\r
731 uint32_t *pulBuffer = ( uint32_t )( pxDescriptor->pucEthernetBuffer - NETWORK_BUFFER_HEADER_SIZE );
\r
732 cache_clean_invalidate_by_addr( pulBuffer, xlength );
\r
736 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
\r
737 pxDmaTxDesc->Status |= ETH_DMATXDESC_OWN;
\r
739 /* Point to next descriptor */
\r
740 xETH.TxDesc = ( ETH_DMADescTypeDef * ) ( xETH.TxDesc->Buffer2NextDescAddr );
\r
741 /* Ensure completion of memory access */
\r
743 /* Resume DMA transmission*/
\r
744 xETH.Instance->DMATPDR = 0;
\r
745 iptraceNETWORK_INTERFACE_TRANSMIT();
\r
751 /* The PHY has no Link Status, packet shall be dropped. */
\r
754 /* The buffer has been sent so can be released. */
\r
755 if( bReleaseAfterSend != pdFALSE )
\r
757 vReleaseNetworkBufferAndDescriptor( pxDescriptor );
\r
762 /*-----------------------------------------------------------*/
\r
764 static BaseType_t xMayAcceptPacket( uint8_t *pcBuffer )
\r
766 const ProtocolPacket_t *pxProtPacket = ( const ProtocolPacket_t * )pcBuffer;
\r
768 switch( pxProtPacket->xTCPPacket.xEthernetHeader.usFrameType )
\r
770 case ipARP_FRAME_TYPE:
\r
771 /* Check it later. */
\r
773 case ipIPv4_FRAME_TYPE:
\r
774 /* Check it here. */
\r
777 /* Refuse the packet. */
\r
781 #if( ipconfigETHERNET_DRIVER_FILTERS_PACKETS == 1 )
\r
783 const IPHeader_t *pxIPHeader = &(pxProtPacket->xTCPPacket.xIPHeader);
\r
784 uint32_t ulDestinationIPAddress;
\r
786 /* Ensure that the incoming packet is not fragmented (only outgoing packets
\r
787 * can be fragmented) as these are the only handled IP frames currently. */
\r
788 if( ( pxIPHeader->usFragmentOffset & FreeRTOS_ntohs( ipFRAGMENT_OFFSET_BIT_MASK ) ) != 0U )
\r
792 /* HT: Might want to make the following configurable because
\r
793 * most IP messages have a standard length of 20 bytes */
\r
795 /* 0x45 means: IPv4 with an IP header of 5 x 4 = 20 bytes
\r
796 * 0x47 means: IPv4 with an IP header of 7 x 4 = 28 bytes */
\r
797 if( pxIPHeader->ucVersionHeaderLength < 0x45 || pxIPHeader->ucVersionHeaderLength > 0x4F )
\r
802 ulDestinationIPAddress = pxIPHeader->ulDestinationIPAddress;
\r
803 /* Is the packet for this node? */
\r
804 if( ( ulDestinationIPAddress != *ipLOCAL_IP_ADDRESS_POINTER ) &&
\r
805 /* Is it a broadcast address x.x.x.255 ? */
\r
806 ( ( FreeRTOS_ntohl( ulDestinationIPAddress ) & 0xff ) != 0xff ) &&
\r
807 #if( ipconfigUSE_LLMNR == 1 )
\r
808 ( ulDestinationIPAddress != ipLLMNR_IP_ADDR ) &&
\r
810 ( *ipLOCAL_IP_ADDRESS_POINTER != 0 ) ) {
\r
811 FreeRTOS_printf( ( "Drop IP %lxip\n", FreeRTOS_ntohl( ulDestinationIPAddress ) ) );
\r
815 if( pxIPHeader->ucProtocol == ipPROTOCOL_UDP )
\r
817 uint16_t usSourcePort = FreeRTOS_ntohs( pxProtPacket->xUDPPacket.xUDPHeader.usSourcePort );
\r
818 uint16_t usDestinationPort = FreeRTOS_ntohs( pxProtPacket->xUDPPacket.xUDPHeader.usDestinationPort );
\r
820 if( ( xPortHasUDPSocket( pxProtPacket->xUDPPacket.xUDPHeader.usDestinationPort ) == pdFALSE )
\r
821 #if ipconfigUSE_LLMNR == 1
\r
822 && ( usDestinationPort != ipLLMNR_PORT )
\r
823 && ( usSourcePort != ipLLMNR_PORT )
\r
825 #if ipconfigUSE_NBNS == 1
\r
826 && ( usDestinationPort != ipNBNS_PORT )
\r
827 && ( usSourcePort != ipNBNS_PORT )
\r
829 #if ipconfigUSE_DNS == 1
\r
830 && ( usSourcePort != ipDNS_PORT )
\r
833 /* Drop this packet, not for this device. */
\r
834 /* FreeRTOS_printf( ( "Drop: UDP port %d -> %d\n", usSourcePort, usDestinationPort ) ); */
\r
839 #endif /* ipconfigETHERNET_DRIVER_FILTERS_PACKETS */
\r
842 /*-----------------------------------------------------------*/
\r
844 static void prvPassEthMessages( NetworkBufferDescriptor_t *pxDescriptor )
\r
846 IPStackEvent_t xRxEvent;
\r
848 xRxEvent.eEventType = eNetworkRxEvent;
\r
849 xRxEvent.pvData = ( void * ) pxDescriptor;
\r
851 if( xSendEventStructToIPTask( &xRxEvent, ( TickType_t ) 1000 ) != pdPASS )
\r
853 /* The buffer could not be sent to the stack so must be released again.
\r
854 This is a deferred handler taskr, not a real interrupt, so it is ok to
\r
855 use the task level function here. */
\r
856 #if( ipconfigUSE_LINKED_RX_MESSAGES != 0 )
\r
860 NetworkBufferDescriptor_t *pxNext = pxDescriptor->pxNextBuffer;
\r
861 vReleaseNetworkBufferAndDescriptor( pxDescriptor );
\r
862 pxDescriptor = pxNext;
\r
863 } while( pxDescriptor != NULL );
\r
867 vReleaseNetworkBufferAndDescriptor( pxDescriptor );
\r
869 #endif /* ipconfigUSE_LINKED_RX_MESSAGES */
\r
870 iptraceETHERNET_RX_EVENT_LOST();
\r
871 FreeRTOS_printf( ( "prvPassEthMessages: Can not queue return packet!\n" ) );
\r
875 iptraceNETWORK_INTERFACE_RECEIVE();
\r
879 static BaseType_t prvNetworkInterfaceInput( void )
\r
881 NetworkBufferDescriptor_t *pxCurDescriptor;
\r
882 NetworkBufferDescriptor_t *pxNewDescriptor = NULL;
\r
883 #if( ipconfigUSE_LINKED_RX_MESSAGES != 0 )
\r
884 NetworkBufferDescriptor_t *pxFirstDescriptor = NULL;
\r
885 NetworkBufferDescriptor_t *pxLastDescriptor = NULL;
\r
887 BaseType_t xReceivedLength = 0;
\r
888 __IO ETH_DMADescTypeDef *pxDMARxDescriptor;
\r
889 const TickType_t xDescriptorWaitTime = pdMS_TO_TICKS( niDESCRIPTOR_WAIT_TIME_MS );
\r
890 uint8_t *pucBuffer;
\r
892 pxDMARxDescriptor = xETH.RxDesc;
\r
894 while( ( pxDMARxDescriptor->Status & ETH_DMARXDESC_OWN ) == 0u )
\r
896 BaseType_t xAccepted = pdTRUE;
\r
897 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
\r
898 xReceivedLength = ( ( pxDMARxDescriptor->Status & ETH_DMARXDESC_FL ) >> ETH_DMARXDESC_FRAMELENGTHSHIFT ) - 4;
\r
900 pucBuffer = (uint8_t *) pxDMARxDescriptor->Buffer1Addr;
\r
902 /* Update the ETHERNET DMA global Rx descriptor with next Rx descriptor */
\r
903 /* Chained Mode */
\r
904 /* Selects the next DMA Rx descriptor list for next buffer to read */
\r
905 xETH.RxDesc = ( ETH_DMADescTypeDef* )pxDMARxDescriptor->Buffer2NextDescAddr;
\r
907 /* In order to make the code easier and faster, only packets in a single buffer
\r
908 will be accepted. This can be done by making the buffers large enough to
\r
909 hold a complete Ethernet packet (1536 bytes).
\r
910 Therefore, two sanity checks: */
\r
911 configASSERT( xReceivedLength <= ETH_RX_BUF_SIZE );
\r
913 if( ( pxDMARxDescriptor->Status & ( ETH_DMARXDESC_CE | ETH_DMARXDESC_IPV4HCE | ETH_DMARXDESC_FT ) ) != ETH_DMARXDESC_FT )
\r
915 /* Not an Ethernet frame-type or a checmsum error. */
\r
916 xAccepted = pdFALSE;
\r
920 /* See if this packet must be handled. */
\r
921 xAccepted = xMayAcceptPacket( pucBuffer );
\r
924 if( xAccepted != pdFALSE )
\r
926 /* The packet wil be accepted, but check first if a new Network Buffer can
\r
927 be obtained. If not, the packet will still be dropped. */
\r
928 pxNewDescriptor = pxGetNetworkBufferWithDescriptor( ETH_RX_BUF_SIZE, xDescriptorWaitTime );
\r
930 if( pxNewDescriptor == NULL )
\r
932 /* A new descriptor can not be allocated now. This packet will be dropped. */
\r
933 xAccepted = pdFALSE;
\r
936 #if( ipconfigZERO_COPY_RX_DRIVER != 0 )
\r
938 /* Find out which Network Buffer was originally passed to the descriptor. */
\r
939 pxCurDescriptor = pxPacketBuffer_to_NetworkBuffer( pucBuffer );
\r
940 configASSERT( pxCurDescriptor != NULL );
\r
944 /* In this mode, the two descriptors are the same. */
\r
945 pxCurDescriptor = pxNewDescriptor;
\r
946 if( pxNewDescriptor != NULL )
\r
948 /* The packet is acepted and a new Network Buffer was created,
\r
949 copy data to the Network Bufffer. */
\r
950 memcpy( pxNewDescriptor->pucEthernetBuffer, pucBuffer, xReceivedLength );
\r
955 if( xAccepted != pdFALSE )
\r
957 pxCurDescriptor->xDataLength = xReceivedLength;
\r
958 #if( ipconfigUSE_LINKED_RX_MESSAGES != 0 )
\r
960 pxCurDescriptor->pxNextBuffer = NULL;
\r
962 if( pxFirstDescriptor == NULL )
\r
964 // Becomes the first message
\r
965 pxFirstDescriptor = pxCurDescriptor;
\r
967 else if( pxLastDescriptor != NULL )
\r
970 pxLastDescriptor->pxNextBuffer = pxCurDescriptor;
\r
973 pxLastDescriptor = pxCurDescriptor;
\r
977 prvPassEthMessages( pxCurDescriptor );
\r
982 /* Release descriptors to DMA */
\r
983 #if( ipconfigZERO_COPY_RX_DRIVER != 0 )
\r
985 /* Set Buffer1 address pointer */
\r
986 if( pxNewDescriptor != NULL )
\r
988 pxDMARxDescriptor->Buffer1Addr = (uint32_t)pxNewDescriptor->pucEthernetBuffer;
\r
992 /* The packet was dropped and the same Network
\r
993 Buffer will be used to receive a new packet. */
\r
996 #endif /* ipconfigZERO_COPY_RX_DRIVER */
\r
998 /* Set Buffer1 size and Second Address Chained bit */
\r
999 pxDMARxDescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | (uint32_t)ETH_RX_BUF_SIZE;
\r
1000 pxDMARxDescriptor->Status = ETH_DMARXDESC_OWN;
\r
1002 /* Ensure completion of memory access */
\r
1004 /* When Rx Buffer unavailable flag is set clear it and resume
\r
1006 if( ( xETH.Instance->DMASR & ETH_DMASR_RBUS ) != 0 )
\r
1008 /* Clear RBUS ETHERNET DMA flag. */
\r
1009 xETH.Instance->DMASR = ETH_DMASR_RBUS;
\r
1011 /* Resume DMA reception. */
\r
1012 xETH.Instance->DMARPDR = 0;
\r
1014 pxDMARxDescriptor = xETH.RxDesc;
\r
1017 #if( ipconfigUSE_LINKED_RX_MESSAGES != 0 )
\r
1019 if( pxFirstDescriptor != NULL )
\r
1021 prvPassEthMessages( pxFirstDescriptor );
\r
1024 #endif /* ipconfigUSE_LINKED_RX_MESSAGES */
\r
1026 return ( xReceivedLength > 0 );
\r
1028 /*-----------------------------------------------------------*/
\r
1031 BaseType_t xSTM32_PhyRead( BaseType_t xAddress, BaseType_t xRegister, uint32_t *pulValue )
\r
1033 uint16_t usPrevAddress = xETH.Init.PhyAddress;
\r
1034 BaseType_t xResult;
\r
1035 HAL_StatusTypeDef xHALResult;
\r
1037 xETH.Init.PhyAddress = xAddress;
\r
1038 xHALResult = HAL_ETH_ReadPHYRegister( &xETH, ( uint16_t )xRegister, pulValue );
\r
1039 xETH.Init.PhyAddress = usPrevAddress;
\r
1041 if( xHALResult == HAL_OK )
\r
1051 /*-----------------------------------------------------------*/
\r
1053 BaseType_t xSTM32_PhyWrite( BaseType_t xAddress, BaseType_t xRegister, uint32_t ulValue )
\r
1055 uint16_t usPrevAddress = xETH.Init.PhyAddress;
\r
1056 BaseType_t xResult;
\r
1057 HAL_StatusTypeDef xHALResult;
\r
1059 xETH.Init.PhyAddress = xAddress;
\r
1060 xHALResult = HAL_ETH_WritePHYRegister( &xETH, ( uint16_t )xRegister, ulValue );
\r
1061 xETH.Init.PhyAddress = usPrevAddress;
\r
1063 if( xHALResult == HAL_OK )
\r
1073 /*-----------------------------------------------------------*/
\r
1075 void vMACBProbePhy( void )
\r
1077 vPhyInitialise( &xPhyObject, xSTM32_PhyRead, xSTM32_PhyWrite );
\r
1078 xPhyDiscover( &xPhyObject );
\r
1079 xPhyConfigure( &xPhyObject, &xPHYProperties );
\r
1081 /*-----------------------------------------------------------*/
\r
1083 static void prvEthernetUpdateConfig( BaseType_t xForce )
\r
1085 FreeRTOS_printf( ( "prvEthernetUpdateConfig: LS mask %02lX Force %d\n",
\r
1086 xPhyObject.ulLinkStatusMask,
\r
1087 ( int )xForce ) );
\r
1089 if( ( xForce != pdFALSE ) || ( xPhyObject.ulLinkStatusMask != 0 ) )
\r
1091 /* Restart the auto-negotiation. */
\r
1092 if( xETH.Init.AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE )
\r
1094 xPhyStartAutoNegotiation( &xPhyObject, xPhyGetMask( &xPhyObject ) );
\r
1096 /* Configure the MAC with the Duplex Mode fixed by the
\r
1097 auto-negotiation process. */
\r
1098 if( xPhyObject.xPhyProperties.ucDuplex == PHY_DUPLEX_FULL )
\r
1100 xETH.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
\r
1104 xETH.Init.DuplexMode = ETH_MODE_HALFDUPLEX;
\r
1107 /* Configure the MAC with the speed fixed by the
\r
1108 auto-negotiation process. */
\r
1109 if( xPhyObject.xPhyProperties.ucSpeed == PHY_SPEED_10 )
\r
1111 xETH.Init.Speed = ETH_SPEED_10M;
\r
1115 xETH.Init.Speed = ETH_SPEED_100M;
\r
1118 else /* AutoNegotiation Disable */
\r
1120 /* Check parameters */
\r
1121 assert_param( IS_ETH_SPEED( xETH.Init.Speed ) );
\r
1122 assert_param( IS_ETH_DUPLEX_MODE( xETH.Init.DuplexMode ) );
\r
1124 if( xETH.Init.DuplexMode == ETH_MODE_FULLDUPLEX )
\r
1126 xPhyObject.xPhyPreferences.ucDuplex = PHY_DUPLEX_HALF;
\r
1130 xPhyObject.xPhyPreferences.ucDuplex = PHY_DUPLEX_FULL;
\r
1133 if( xETH.Init.Speed == ETH_SPEED_10M )
\r
1135 xPhyObject.xPhyPreferences.ucSpeed = PHY_SPEED_10;
\r
1139 xPhyObject.xPhyPreferences.ucSpeed = PHY_SPEED_100;
\r
1142 xPhyObject.xPhyPreferences.ucMDI_X = PHY_MDIX_AUTO;
\r
1144 /* Use predefined (fixed) configuration. */
\r
1145 xPhyFixedValue( &xPhyObject, xPhyGetMask( &xPhyObject ) );
\r
1148 /* ETHERNET MAC Re-Configuration */
\r
1149 HAL_ETH_ConfigMAC( &xETH, (ETH_MACInitTypeDef *) NULL);
\r
1151 /* Restart MAC interface */
\r
1152 HAL_ETH_Start( &xETH);
\r
1156 /* Stop MAC interface */
\r
1157 HAL_ETH_Stop( &xETH );
\r
1160 /*-----------------------------------------------------------*/
\r
1162 BaseType_t xGetPhyLinkStatus( void )
\r
1164 BaseType_t xReturn;
\r
1166 if( xPhyObject.ulLinkStatusMask != 0 )
\r
1177 /*-----------------------------------------------------------*/
\r
1179 /* Uncomment this in case BufferAllocation_1.c is used. */
\r
1181 void vNetworkInterfaceAllocateRAMToBuffers( NetworkBufferDescriptor_t pxNetworkBuffers[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ] )
\r
1183 static __attribute__ ((section(".first_data"))) uint8_t ucNetworkPackets[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS * ETH_MAX_PACKET_SIZE ] __attribute__ ( ( aligned( 32 ) ) );
\r
1184 uint8_t *ucRAMBuffer = ucNetworkPackets;
\r
1187 for( ul = 0; ul < ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS; ul++ )
\r
1189 pxNetworkBuffers[ ul ].pucEthernetBuffer = ucRAMBuffer + ipBUFFER_PADDING;
\r
1190 *( ( unsigned * ) ucRAMBuffer ) = ( unsigned ) ( &( pxNetworkBuffers[ ul ] ) );
\r
1191 ucRAMBuffer += ETH_MAX_PACKET_SIZE;
\r
1194 /*-----------------------------------------------------------*/
\r
1196 static void prvEMACHandlerTask( void *pvParameters )
\r
1198 UBaseType_t uxLastMinBufferCount = 0;
\r
1199 #if( ipconfigCHECK_IP_QUEUE_SPACE != 0 )
\r
1200 UBaseType_t uxLastMinQueueSpace = 0;
\r
1202 UBaseType_t uxCurrentCount;
\r
1203 BaseType_t xResult;
\r
1204 const TickType_t ulMaxBlockTime = pdMS_TO_TICKS( 100UL );
\r
1206 /* Remove compiler warnings about unused parameters. */
\r
1207 ( void ) pvParameters;
\r
1212 uxCurrentCount = uxGetMinimumFreeNetworkBuffers();
\r
1213 if( uxLastMinBufferCount != uxCurrentCount )
\r
1215 /* The logging produced below may be helpful
\r
1216 while tuning +TCP: see how many buffers are in use. */
\r
1217 uxLastMinBufferCount = uxCurrentCount;
\r
1218 FreeRTOS_printf( ( "Network buffers: %lu lowest %lu\n",
\r
1219 uxGetNumberOfFreeNetworkBuffers(), uxCurrentCount ) );
\r
1222 if( xTXDescriptorSemaphore != NULL )
\r
1224 static UBaseType_t uxLowestSemCount = ( UBaseType_t ) ETH_TXBUFNB - 1;
\r
1226 uxCurrentCount = uxSemaphoreGetCount( xTXDescriptorSemaphore );
\r
1227 if( uxLowestSemCount > uxCurrentCount )
\r
1229 uxLowestSemCount = uxCurrentCount;
\r
1230 FreeRTOS_printf( ( "TX DMA buffers: lowest %lu\n", uxLowestSemCount ) );
\r
1235 #if( ipconfigCHECK_IP_QUEUE_SPACE != 0 )
\r
1237 uxCurrentCount = uxGetMinimumIPQueueSpace();
\r
1238 if( uxLastMinQueueSpace != uxCurrentCount )
\r
1240 /* The logging produced below may be helpful
\r
1241 while tuning +TCP: see how many buffers are in use. */
\r
1242 uxLastMinQueueSpace = uxCurrentCount;
\r
1243 FreeRTOS_printf( ( "Queue space: lowest %lu\n", uxCurrentCount ) );
\r
1246 #endif /* ipconfigCHECK_IP_QUEUE_SPACE */
\r
1248 if( ( ulISREvents & EMAC_IF_ALL_EVENT ) == 0 )
\r
1250 /* No events to process now, wait for the next. */
\r
1251 ulTaskNotifyTake( pdFALSE, ulMaxBlockTime );
\r
1254 if( ( ulISREvents & EMAC_IF_RX_EVENT ) != 0 )
\r
1256 ulISREvents &= ~EMAC_IF_RX_EVENT;
\r
1258 xResult = prvNetworkInterfaceInput();
\r
1261 if( ( ulISREvents & EMAC_IF_TX_EVENT ) != 0 )
\r
1263 /* Code to release TX buffers if zero-copy is used. */
\r
1264 ulISREvents &= ~EMAC_IF_TX_EVENT;
\r
1265 /* Check if DMA packets have been delivered. */
\r
1266 vClearTXBuffers();
\r
1269 if( ( ulISREvents & EMAC_IF_ERR_EVENT ) != 0 )
\r
1271 /* Future extension: logging about errors that occurred. */
\r
1272 ulISREvents &= ~EMAC_IF_ERR_EVENT;
\r
1274 if( xPhyCheckLinkStatus( &xPhyObject, xResult ) != 0 )
\r
1276 /* Something has changed to a Link Status, need re-check. */
\r
1277 prvEthernetUpdateConfig( pdFALSE );
\r
1281 /*-----------------------------------------------------------*/
\r
1283 void ETH_IRQHandler( void )
\r
1285 HAL_ETH_IRQHandler( &xETH );
\r