2 ******************************************************************************
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3 * @file stm32fxx_hal_eth.c
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4 * @author MCD Application Team
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7 * @brief ETH HAL module driver.
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8 * This file provides firmware functions to manage the following
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9 * functionalities of the Ethernet (ETH) peripheral:
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10 * + Initialization and de-initialization functions
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11 * + IO operation functions
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12 * + Peripheral Control functions
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13 * + Peripheral State and Errors functions
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16 ==============================================================================
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17 ##### How to use this driver #####
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18 ==============================================================================
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20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
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21 ETH_HandleTypeDef heth;
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23 (#)Fill parameters of Init structure in heth handle
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25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
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27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
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28 (##) Enable the Ethernet interface clock using
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29 (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
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30 (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
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31 (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
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33 (##) Initialize the related GPIO clocks
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34 (##) Configure Ethernet pin-out
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35 (##) Configure Ethernet NVIC interrupt (IT mode)
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37 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
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38 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
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39 (##) HAL_ETH_DMARxDescListInit(); for Reception process
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41 (#)Enable MAC and DMA transmission and reception:
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42 (##) HAL_ETH_Start();
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44 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
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45 the frame to MAC TX FIFO:
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46 (##) HAL_ETH_TransmitFrame();
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48 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
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50 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
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52 (#) Get a received frame when an ETH RX interrupt occurs:
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53 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
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55 (#) Communicate with external PHY device:
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56 (##) Read a specific register from the PHY
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57 HAL_ETH_ReadPHYRegister();
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58 (##) Write data to a specific RHY register:
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59 HAL_ETH_WritePHYRegister();
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61 (#) Configure the Ethernet MAC after ETH peripheral initialization
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62 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
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64 (#) Configure the Ethernet DMA after ETH peripheral initialization
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65 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
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67 -@- The PTP protocol and the DMA descriptors ring mode are not supported
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71 ******************************************************************************
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74 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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76 * Redistribution and use in source and binary forms, with or without modification,
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77 * are permitted provided that the following conditions are met:
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78 * 1. Redistributions of source code must retain the above copyright notice,
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79 * this list of conditions and the following disclaimer.
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80 * 2. Redistributions in binary form must reproduce the above copyright notice,
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81 * this list of conditions and the following disclaimer in the documentation
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82 * and/or other materials provided with the distribution.
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83 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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84 * may be used to endorse or promote products derived from this software
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85 * without specific prior written permission.
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87 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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88 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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89 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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90 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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91 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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92 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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93 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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94 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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95 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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96 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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98 ******************************************************************************
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101 /* Includes ------------------------------------------------------------------*/
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103 #if defined(STM32F7xx)
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104 #include "stm32f7xx_hal.h"
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105 #define stm_is_F7 1
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106 #elif defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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107 #include "stm32f4xx_hal.h"
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108 #define stm_is_F4 1
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109 #elif defined(STM32F2xx)
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110 #include "stm32f2xx_hal.h"
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111 #define stm_is_F2 1
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113 #error For what part should this be compiled?
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116 #include "stm32fxx_hal_eth.h"
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118 /** @addtogroup STM32F4xx_HAL_Driver
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122 /** @defgroup ETH ETH
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123 * @brief ETH HAL module driver
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127 #if !defined( ARRAY_SIZE )
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128 #define ARRAY_SIZE( x ) ( sizeof ( x ) / sizeof ( x )[ 0 ] )
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131 #ifdef HAL_ETH_MODULE_ENABLED
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133 #if( stm_is_F2 != 0 || stm_is_F4 != 0 || stm_is_F7 )
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135 /* Private typedef -----------------------------------------------------------*/
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136 /* Private define ------------------------------------------------------------*/
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137 /** @defgroup ETH_Private_Constants ETH Private Constants
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144 /* Private macro -------------------------------------------------------------*/
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145 /* Private variables ---------------------------------------------------------*/
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146 /* Private function prototypes -----------------------------------------------*/
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147 /** @defgroup ETH_Private_Functions ETH Private Functions
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150 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
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151 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
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152 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
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153 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
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154 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
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155 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
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156 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
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157 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
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158 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
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159 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
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160 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
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165 /* Private functions ---------------------------------------------------------*/
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167 /** @defgroup ETH_Exported_Functions ETH Exported Functions
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171 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
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172 * @brief Initialization and Configuration functions
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175 ===============================================================================
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176 ##### Initialization and de-initialization functions #####
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177 ===============================================================================
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178 [..] This section provides functions allowing to:
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179 (+) Initialize and configure the Ethernet peripheral
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180 (+) De-initialize the Ethernet peripheral
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185 extern void vMACBProbePhy ( void );
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188 * @brief Initializes the Ethernet MAC and DMA according to default
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190 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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191 * the configuration information for ETHERNET module
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192 * @retval HAL status
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194 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
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196 uint32_t tmpreg = 0uL;
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197 uint32_t hclk = 60000000uL;
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198 uint32_t err = ETH_SUCCESS;
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200 /* Check the ETH peripheral state */
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206 /* Check parameters */
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207 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
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208 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
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209 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
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210 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
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212 if( heth->State == HAL_ETH_STATE_RESET )
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214 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
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215 HAL_ETH_MspInit( heth );
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218 /* Enable SYSCFG Clock */
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219 __HAL_RCC_SYSCFG_CLK_ENABLE();
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221 /* Select MII or RMII Mode*/
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222 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
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223 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
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225 /* Ethernet Software reset */
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226 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
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227 /* After reset all the registers holds their respective reset values */
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228 /* Also enable EDFE: Enhanced descriptor format enable. */
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229 heth->Instance->DMABMR |= ETH_DMABMR_SR | ETH_DMABMR_EDE;
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231 /* Wait for software reset */
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232 while ((heth->Instance->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
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234 /* If your program hangs here, please check the value of 'ipconfigUSE_RMII'. */
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237 /*-------------------------------- MAC Initialization ----------------------*/
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238 /* Get the ETHERNET MACMIIAR value */
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239 tmpreg = heth->Instance->MACMIIAR;
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240 /* Clear CSR Clock Range CR[2:0] bits */
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241 tmpreg &= ETH_MACMIIAR_CR_MASK;
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243 /* Get hclk frequency value (e.g. 168,000,000) */
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244 hclk = HAL_RCC_GetHCLKFreq();
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246 /* Set CR bits depending on hclk value */
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247 if(( hclk >= 20000000uL ) && ( hclk < 35000000uL ) )
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249 /* CSR Clock Range between 20-35 MHz */
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250 tmpreg |= ( uint32_t) ETH_MACMIIAR_CR_Div16;
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252 else if( ( hclk >= 35000000uL ) && ( hclk < 60000000uL ) )
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254 /* CSR Clock Range between 35-60 MHz */
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255 tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div26;
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257 else if( ( hclk >= 60000000uL ) && ( hclk < 100000000uL ) )
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259 /* CSR Clock Range between 60-100 MHz */
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260 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
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262 else if( ( hclk >= 100000000uL ) && ( hclk < 150000000uL ) )
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264 /* CSR Clock Range between 100-150 MHz */
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265 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
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267 else /* ( ( hclk >= 150000000uL ) && ( hclk <= 183000000uL ) ) */
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269 /* CSR Clock Range between 150-183 MHz */
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270 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
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273 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
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274 heth->Instance->MACMIIAR = (uint32_t)tmpreg;
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276 /* Initialise the MACB and set all PHY properties */
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279 /* Config MAC and DMA */
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280 ETH_MACDMAConfig(heth, err);
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282 /* Set ETH HAL State to Ready */
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283 heth->State= HAL_ETH_STATE_READY;
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285 /* Return function status */
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290 * @brief De-Initializes the ETH peripheral.
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291 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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292 * the configuration information for ETHERNET module
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293 * @retval HAL status
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295 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
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297 /* Set the ETH peripheral state to BUSY */
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298 heth->State = HAL_ETH_STATE_BUSY;
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300 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
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301 HAL_ETH_MspDeInit( heth );
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303 /* Set ETH HAL state to Disabled */
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304 heth->State= HAL_ETH_STATE_RESET;
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307 __HAL_UNLOCK( heth );
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309 /* Return function status */
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314 * @brief Initializes the ETH MSP.
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315 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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316 * the configuration information for ETHERNET module
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319 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
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321 /* NOTE : This function Should not be modified, when the callback is needed,
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322 the HAL_ETH_MspInit could be implemented in the user file
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328 * @brief DeInitializes ETH MSP.
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329 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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330 * the configuration information for ETHERNET module
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333 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
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335 /* NOTE : This function Should not be modified, when the callback is needed,
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336 the HAL_ETH_MspDeInit could be implemented in the user file
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345 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
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346 * @brief Data transfers functions
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349 ==============================================================================
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350 ##### IO operation functions #####
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351 ==============================================================================
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352 [..] This section provides functions allowing to:
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353 (+) Transmit a frame
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354 HAL_ETH_TransmitFrame();
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355 (+) Receive a frame
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356 HAL_ETH_GetReceivedFrame();
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357 HAL_ETH_GetReceivedFrame_IT();
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358 (+) Read from an External PHY register
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359 HAL_ETH_ReadPHYRegister();
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360 (+) Write to an External PHY register
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361 HAL_ETH_WritePHYRegister();
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368 #define ETH_DMA_ALL_INTS \
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369 ( ETH_DMA_IT_TST | ETH_DMA_IT_PMT | ETH_DMA_IT_MMC | ETH_DMA_IT_NIS | ETH_DMA_IT_AIS | ETH_DMA_IT_ER | \
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370 ETH_DMA_IT_FBE | ETH_DMA_IT_ET | ETH_DMA_IT_RWT | ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | \
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371 ETH_DMA_IT_TU | ETH_DMA_IT_RO | ETH_DMA_IT_TJT | ETH_DMA_IT_TPS | ETH_DMA_IT_T )
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373 //#define ETH_DMA_ALL_INTS ETH_DMA_IT_RBU | ETH_DMA_FLAG_T | ETH_DMA_FLAG_AIS
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375 #define INT_MASK ( ( uint32_t ) ~ ( ETH_DMA_IT_TBU ) )
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376 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
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380 dmasr = heth->Instance->DMASR & ETH_DMA_ALL_INTS;
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381 heth->Instance->DMASR = dmasr;
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383 /* Frame received */
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384 if( ( dmasr & ( ETH_DMA_FLAG_R | ETH_DMA_IT_RBU ) ) != 0 )
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386 /* Receive complete callback */
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387 HAL_ETH_RxCpltCallback( heth );
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389 /* Frame transmitted */
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390 if( ( dmasr & ( ETH_DMA_FLAG_T ) ) != 0 )
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392 /* Transfer complete callback */
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393 HAL_ETH_TxCpltCallback( heth );
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396 /* ETH DMA Error */
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397 if( ( dmasr & ( ETH_DMA_FLAG_AIS ) ) != 0 )
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399 /* Ethernet Error callback */
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400 HAL_ETH_ErrorCallback( heth );
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405 * @brief Tx Transfer completed callbacks.
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406 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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407 * the configuration information for ETHERNET module
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410 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
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412 /* NOTE : This function Should not be modified, when the callback is needed,
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413 the HAL_ETH_TxCpltCallback could be implemented in the user file
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419 * @brief Rx Transfer completed callbacks.
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420 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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421 * the configuration information for ETHERNET module
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424 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
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426 /* NOTE : This function Should not be modified, when the callback is needed,
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427 the HAL_ETH_TxCpltCallback could be implemented in the user file
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433 * @brief Ethernet transfer error callbacks
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434 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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435 * the configuration information for ETHERNET module
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438 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
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440 /* NOTE : This function Should not be modified, when the callback is needed,
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441 the HAL_ETH_TxCpltCallback could be implemented in the user file
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447 * @brief Reads a PHY register
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448 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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449 * the configuration information for ETHERNET module
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450 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
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451 * This parameter can be one of the following values:
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452 * PHY_BCR: Transceiver Basic Control Register,
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453 * PHY_BSR: Transceiver Basic Status Register.
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454 * More PHY register could be read depending on the used PHY
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455 * @param RegValue: PHY register value
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456 * @retval HAL status
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458 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
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460 uint32_t tmpreg = 0uL;
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461 uint32_t tickstart = 0uL;
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462 HAL_StatusTypeDef xResult;
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464 /* Check parameters */
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465 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
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467 /* Check the ETH peripheral state */
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468 if( heth->State == HAL_ETH_STATE_BUSY_RD )
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470 xResult = HAL_BUSY;
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474 __HAL_LOCK( heth );
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476 /* Set ETH HAL State to BUSY_RD */
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477 heth->State = HAL_ETH_STATE_BUSY_RD;
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479 /* Get the ETHERNET MACMIIAR value */
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480 tmpreg = heth->Instance->MACMIIAR;
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482 /* Keep only the CSR Clock Range CR[2:0] bits value */
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483 tmpreg &= ~ETH_MACMIIAR_CR_MASK;
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485 /* Prepare the MII address register value */
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486 tmpreg |= ( ( ( uint32_t )heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA ); /* Set the PHY device address */
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487 tmpreg |= ( ( ( uint32_t )PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */
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488 tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
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489 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
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491 /* Write the result value into the MII Address register */
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492 heth->Instance->MACMIIAR = tmpreg;
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495 tickstart = HAL_GetTick();
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497 /* Check for the Busy flag */
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500 tmpreg = heth->Instance->MACMIIAR;
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502 if( ( tmpreg & ETH_MACMIIAR_MB ) == 0uL )
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504 /* Get MACMIIDR value */
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505 *RegValue = ( uint32_t ) heth->Instance->MACMIIDR;
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509 /* Check for the Timeout */
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510 if( ( HAL_GetTick( ) - tickstart ) > PHY_READ_TO )
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512 xResult = HAL_TIMEOUT;
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518 /* Set ETH HAL State to READY */
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519 heth->State = HAL_ETH_STATE_READY;
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521 /* Process Unlocked */
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522 __HAL_UNLOCK( heth );
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525 /* Return function status */
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530 * @brief Writes to a PHY register.
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531 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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532 * the configuration information for ETHERNET module
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533 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
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534 * This parameter can be one of the following values:
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535 * PHY_BCR: Transceiver Control Register.
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536 * More PHY register could be written depending on the used PHY
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537 * @param RegValue: the value to write
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538 * @retval HAL status
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540 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
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542 uint32_t tmpreg = 0;
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543 uint32_t tickstart = 0;
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544 HAL_StatusTypeDef xResult;
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546 /* Check parameters */
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547 assert_param( IS_ETH_PHY_ADDRESS( heth->Init.PhyAddress ) );
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549 /* Check the ETH peripheral state */
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550 if( heth->State == HAL_ETH_STATE_BUSY_WR )
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552 xResult = HAL_BUSY;
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556 __HAL_LOCK( heth );
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558 /* Set ETH HAL State to BUSY_WR */
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559 heth->State = HAL_ETH_STATE_BUSY_WR;
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561 /* Get the ETHERNET MACMIIAR value */
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562 tmpreg = heth->Instance->MACMIIAR;
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564 /* Keep only the CSR Clock Range CR[2:0] bits value */
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565 tmpreg &= ~ETH_MACMIIAR_CR_MASK;
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567 /* Prepare the MII register address value */
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568 tmpreg |= ( ( ( uint32_t ) heth->Init.PhyAddress << 11 ) & ETH_MACMIIAR_PA ); /* Set the PHY device address */
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569 tmpreg |= ( ( ( uint32_t ) PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */
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570 tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
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571 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
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573 /* Give the value to the MII data register */
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574 heth->Instance->MACMIIDR = ( uint16_t ) RegValue;
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576 /* Write the result value into the MII Address register */
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577 heth->Instance->MACMIIAR = tmpreg;
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580 tickstart = HAL_GetTick();
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582 /* Check for the Busy flag */
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585 tmpreg = heth->Instance->MACMIIAR;
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587 if( ( tmpreg & ETH_MACMIIAR_MB ) == 0ul )
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592 /* Check for the Timeout */
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593 if( ( HAL_GetTick( ) - tickstart ) > PHY_WRITE_TO )
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595 xResult = HAL_TIMEOUT;
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600 /* Set ETH HAL State to READY */
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601 heth->State = HAL_ETH_STATE_READY;
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602 /* Process Unlocked */
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603 __HAL_UNLOCK( heth );
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606 /* Return function status */
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614 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
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615 * @brief Peripheral Control functions
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618 ===============================================================================
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619 ##### Peripheral Control functions #####
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620 ===============================================================================
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621 [..] This section provides functions allowing to:
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622 (+) Enable MAC and DMA transmission and reception.
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624 (+) Disable MAC and DMA transmission and reception.
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626 (+) Set the MAC configuration in runtime mode
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627 HAL_ETH_ConfigMAC();
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628 (+) Set the DMA configuration in runtime mode
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629 HAL_ETH_ConfigDMA();
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636 * @brief Enables Ethernet MAC and DMA reception/transmission
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637 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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638 * the configuration information for ETHERNET module
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639 * @retval HAL status
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641 HAL_StatusTypeDef HAL_ETH_Start( ETH_HandleTypeDef *heth )
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643 /* Process Locked */
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644 __HAL_LOCK( heth );
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646 /* Set the ETH peripheral state to BUSY */
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647 heth->State = HAL_ETH_STATE_BUSY;
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649 /* Enable transmit state machine of the MAC for transmission on the MII */
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650 ETH_MACTransmissionEnable( heth );
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652 /* Enable receive state machine of the MAC for reception from the MII */
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653 ETH_MACReceptionEnable( heth );
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655 /* Flush Transmit FIFO */
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656 ETH_FlushTransmitFIFO( heth );
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658 /* Start DMA transmission */
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659 ETH_DMATransmissionEnable( heth );
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661 /* Start DMA reception */
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662 ETH_DMAReceptionEnable( heth );
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664 /* Set the ETH state to READY*/
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665 heth->State= HAL_ETH_STATE_READY;
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667 /* Process Unlocked */
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668 __HAL_UNLOCK( heth );
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670 /* Return function status */
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675 * @brief Stop Ethernet MAC and DMA reception/transmission
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676 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
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677 * the configuration information for ETHERNET module
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678 * @retval HAL status
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680 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
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682 /* Process Locked */
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683 __HAL_LOCK( heth );
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685 /* Set the ETH peripheral state to BUSY */
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686 heth->State = HAL_ETH_STATE_BUSY;
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688 /* Stop DMA transmission */
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689 ETH_DMATransmissionDisable( heth );
\r
691 /* Stop DMA reception */
\r
692 ETH_DMAReceptionDisable( heth );
\r
694 /* Disable receive state machine of the MAC for reception from the MII */
\r
695 ETH_MACReceptionDisable( heth );
\r
697 /* Flush Transmit FIFO */
\r
698 ETH_FlushTransmitFIFO( heth );
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700 /* Disable transmit state machine of the MAC for transmission on the MII */
\r
701 ETH_MACTransmissionDisable( heth );
\r
703 /* Set the ETH state*/
\r
704 heth->State = HAL_ETH_STATE_READY;
\r
706 /* Process Unlocked */
\r
707 __HAL_UNLOCK( heth );
\r
709 /* Return function status */
\r
713 static void vRegisterDelay()
\r
717 * Regarding the HAL delay functions, I noticed that HAL delay is being used to workaround the
\r
718 * "Successive write operations to the same register might not be fully taken into account" errata.
\r
719 * The workaround requires a delay of four TX_CLK/RX_CLK clock cycles. For a 10 Mbit connection,
\r
720 * these clocks are running at 2.5 MHz, so this delay would be at most 1.6 microseconds.
\r
721 * 180 Mhz = 288 loops
\r
722 * 168 Mhz = 269 loops
\r
723 * 100 Mhz = 160 loops
\r
724 * 84 Mhz = 134 loops
\r
726 #define WAIT_TIME_NS 1600uL /* 1.6 microseconds */
\r
727 #define CPU_MAX_FREQ SystemCoreClock /* 84, 100, 168 or 180 MHz */
\r
728 uint32_t NOP_COUNT = ( WAIT_TIME_NS * ( CPU_MAX_FREQ / 1000uL ) ) / 1000000uL;
\r
729 for( uxCount = NOP_COUNT; uxCount > 0uL; uxCount-- )
\r
735 static void prvWriteMACFCR( ETH_HandleTypeDef *heth, uint32_t ulValue)
\r
737 /* Enable the MAC transmission */
\r
738 heth->Instance->MACFCR = ulValue;
\r
740 /* Wait until the write operation will be taken into account:
\r
741 at least four TX_CLK/RX_CLK clock cycles.
\r
742 Read it back, wait a ms and */
\r
743 ( void ) heth->Instance->MACFCR;
\r
747 heth->Instance->MACFCR = ulValue;
\r
750 static void prvWriteDMAOMR( ETH_HandleTypeDef *heth, uint32_t ulValue)
\r
752 /* Enable the MAC transmission */
\r
753 heth->Instance->DMAOMR = ulValue;
\r
755 /* Wait until the write operation will be taken into account:
\r
756 at least four TX_CLK/RX_CLK clock cycles.
\r
757 Read it back, wait a ms and */
\r
758 ( void ) heth->Instance->DMAOMR;
\r
762 heth->Instance->DMAOMR = ulValue;
\r
765 static void prvWriteMACCR( ETH_HandleTypeDef *heth, uint32_t ulValue)
\r
767 /* Enable the MAC transmission */
\r
768 heth->Instance->MACCR = ulValue;
\r
770 /* Wait until the write operation will be taken into account:
\r
771 at least four TX_CLK/RX_CLK clock cycles.
\r
772 Read it back, wait a ms and */
\r
773 ( void ) heth->Instance->MACCR;
\r
777 heth->Instance->MACCR = ulValue;
\r
781 * @brief Set ETH MAC Configuration.
\r
782 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
783 * the configuration information for ETHERNET module
\r
784 * @param macconf: MAC Configuration structure
\r
785 * @retval HAL status
\r
787 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
\r
789 uint32_t tmpreg = 0uL;
\r
791 /* Process Locked */
\r
792 __HAL_LOCK( heth );
\r
794 /* Set the ETH peripheral state to BUSY */
\r
795 heth->State= HAL_ETH_STATE_BUSY;
\r
797 assert_param(IS_ETH_SPEED(heth->Init.Speed));
\r
798 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
\r
800 if (macconf != NULL)
\r
802 /* Check the parameters */
\r
803 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
\r
804 assert_param(IS_ETH_JABBER(macconf->Jabber));
\r
805 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
\r
806 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
\r
807 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
\r
808 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
\r
809 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
\r
810 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
\r
811 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
\r
812 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
\r
813 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
\r
814 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
\r
815 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
\r
816 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
\r
817 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
\r
818 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
\r
819 assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
\r
820 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
\r
821 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
\r
822 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
\r
823 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
\r
824 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
\r
825 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
\r
826 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
\r
827 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
\r
828 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
\r
829 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
\r
831 /*------------------------ ETHERNET MACCR Configuration --------------------*/
\r
832 /* Get the ETHERNET MACCR value */
\r
833 tmpreg = heth->Instance->MACCR;
\r
834 /* Clear WD, PCE, PS, TE and RE bits */
\r
835 tmpreg &= ETH_MACCR_CLEAR_MASK;
\r
837 tmpreg |= (uint32_t)(
\r
838 macconf->Watchdog |
\r
840 macconf->InterFrameGap |
\r
841 macconf->CarrierSense |
\r
843 macconf->ReceiveOwn |
\r
844 macconf->LoopbackMode |
\r
845 heth->Init.DuplexMode |
\r
846 macconf->ChecksumOffload |
\r
847 macconf->RetryTransmission |
\r
848 macconf->AutomaticPadCRCStrip |
\r
849 macconf->BackOffLimit |
\r
850 macconf->DeferralCheck);
\r
852 /* Write to ETHERNET MACCR */
\r
853 prvWriteMACCR( heth, tmpreg );
\r
855 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
\r
856 /* Write to ETHERNET MACFFR */
\r
857 heth->Instance->MACFFR = (uint32_t)(
\r
858 macconf->ReceiveAll |
\r
859 macconf->SourceAddrFilter |
\r
860 macconf->PassControlFrames |
\r
861 macconf->BroadcastFramesReception |
\r
862 macconf->DestinationAddrFilter |
\r
863 macconf->PromiscuousMode |
\r
864 macconf->MulticastFramesFilter |
\r
865 macconf->UnicastFramesFilter);
\r
867 /* Wait until the write operation will be taken into account :
\r
868 at least four TX_CLK/RX_CLK clock cycles */
\r
869 tmpreg = heth->Instance->MACFFR;
\r
871 heth->Instance->MACFFR = tmpreg;
\r
873 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
\r
874 /* Write to ETHERNET MACHTHR */
\r
875 heth->Instance->MACHTHR = (uint32_t)macconf->HashTableHigh;
\r
877 /* Write to ETHERNET MACHTLR */
\r
878 heth->Instance->MACHTLR = (uint32_t)macconf->HashTableLow;
\r
879 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
\r
881 /* Get the ETHERNET MACFCR value */
\r
882 tmpreg = heth->Instance->MACFCR;
\r
883 /* Clear xx bits */
\r
884 tmpreg &= ETH_MACFCR_CLEAR_MASK;
\r
886 tmpreg |= (uint32_t)((
\r
887 macconf->PauseTime << 16) |
\r
888 macconf->ZeroQuantaPause |
\r
889 macconf->PauseLowThreshold |
\r
890 macconf->UnicastPauseFrameDetect |
\r
891 macconf->ReceiveFlowControl |
\r
892 macconf->TransmitFlowControl);
\r
894 /* Write to ETHERNET MACFCR */
\r
895 prvWriteMACFCR( heth, tmpreg );
\r
897 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
\r
898 heth->Instance->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
\r
899 macconf->VLANTagIdentifier);
\r
901 /* Wait until the write operation will be taken into account :
\r
902 at least four TX_CLK/RX_CLK clock cycles */
\r
903 tmpreg = heth->Instance->MACVLANTR;
\r
905 heth->Instance->MACVLANTR = tmpreg;
\r
907 else /* macconf == NULL : here we just configure Speed and Duplex mode */
\r
909 /*------------------------ ETHERNET MACCR Configuration --------------------*/
\r
910 /* Get the ETHERNET MACCR value */
\r
911 tmpreg = heth->Instance->MACCR;
\r
913 /* Clear FES and DM bits */
\r
914 tmpreg &= ~( ( uint32_t ) 0x00004800uL );
\r
916 tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
\r
918 /* Write to ETHERNET MACCR */
\r
919 prvWriteMACCR( heth, tmpreg );
\r
922 /* Set the ETH state to Ready */
\r
923 heth->State= HAL_ETH_STATE_READY;
\r
925 /* Process Unlocked */
\r
926 __HAL_UNLOCK( heth );
\r
928 /* Return function status */
\r
933 * @brief Sets ETH DMA Configuration.
\r
934 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
935 * the configuration information for ETHERNET module
\r
936 * @param dmaconf: DMA Configuration structure
\r
937 * @retval HAL status
\r
939 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
\r
941 uint32_t tmpreg = 0uL;
\r
943 /* Process Locked */
\r
944 __HAL_LOCK( heth );
\r
946 /* Set the ETH peripheral state to BUSY */
\r
947 heth->State= HAL_ETH_STATE_BUSY;
\r
949 /* Check parameters */
\r
950 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
\r
951 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
\r
952 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
\r
953 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
\r
954 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
\r
955 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
\r
956 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
\r
957 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
\r
958 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
\r
959 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
\r
960 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
\r
961 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
\r
962 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
\r
963 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
\r
964 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
\r
965 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
\r
967 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
\r
968 /* Get the ETHERNET DMAOMR value */
\r
969 tmpreg = heth->Instance->DMAOMR;
\r
970 /* Clear xx bits */
\r
971 tmpreg &= ETH_DMAOMR_CLEAR_MASK;
\r
973 tmpreg |= (uint32_t)(
\r
974 dmaconf->DropTCPIPChecksumErrorFrame |
\r
975 dmaconf->ReceiveStoreForward |
\r
976 dmaconf->FlushReceivedFrame |
\r
977 dmaconf->TransmitStoreForward |
\r
978 dmaconf->TransmitThresholdControl |
\r
979 dmaconf->ForwardErrorFrames |
\r
980 dmaconf->ForwardUndersizedGoodFrames |
\r
981 dmaconf->ReceiveThresholdControl |
\r
982 dmaconf->SecondFrameOperate);
\r
984 /* Write to ETHERNET DMAOMR */
\r
985 prvWriteDMAOMR( heth, tmpreg );
\r
987 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
\r
988 heth->Instance->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
\r
989 dmaconf->FixedBurst |
\r
990 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
\r
991 dmaconf->TxDMABurstLength |
\r
992 dmaconf->EnhancedDescriptorFormat |
\r
993 (dmaconf->DescriptorSkipLength << 2) |
\r
994 dmaconf->DMAArbitration |
\r
995 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
\r
997 /* Wait until the write operation will be taken into account:
\r
998 at least four TX_CLK/RX_CLK clock cycles */
\r
999 tmpreg = heth->Instance->DMABMR;
\r
1001 heth->Instance->DMABMR = tmpreg;
\r
1003 /* Set the ETH state to Ready */
\r
1004 heth->State= HAL_ETH_STATE_READY;
\r
1006 /* Process Unlocked */
\r
1007 __HAL_UNLOCK( heth );
\r
1009 /* Return function status */
\r
1017 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
\r
1018 * @brief Peripheral State functions
\r
1021 ===============================================================================
\r
1022 ##### Peripheral State functions #####
\r
1023 ===============================================================================
\r
1025 This subsection permits to get in run-time the status of the peripheral
\r
1026 and the data flow.
\r
1027 (+) Get the ETH handle state:
\r
1028 HAL_ETH_GetState();
\r
1036 * @brief Return the ETH HAL state
\r
1037 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1038 * the configuration information for ETHERNET module
\r
1039 * @retval HAL state
\r
1041 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
\r
1043 /* Return ETH state */
\r
1044 return heth->State;
\r
1055 /** @addtogroup ETH_Private_Functions
\r
1060 * @brief Configures Ethernet MAC and DMA with default parameters.
\r
1061 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1062 * the configuration information for ETHERNET module
\r
1063 * @param err: Ethernet Init error
\r
1064 * @retval HAL status
\r
1066 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
\r
1068 ETH_MACInitTypeDef macinit;
\r
1069 ETH_DMAInitTypeDef dmainit;
\r
1070 uint32_t tmpreg = 0uL;
\r
1072 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
\r
1074 /* Set Ethernet duplex mode to Full-duplex */
\r
1075 heth->Init.DuplexMode = ETH_MODE_FULLDUPLEX;
\r
1077 /* Set Ethernet speed to 100M */
\r
1078 heth->Init.Speed = ETH_SPEED_100M;
\r
1081 /* Ethernet MAC default initialization **************************************/
\r
1082 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
\r
1083 macinit.Jabber = ETH_JABBER_ENABLE;
\r
1084 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
\r
1085 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
\r
1086 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
\r
1087 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
\r
1088 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
\r
1090 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
\r
1094 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
\r
1096 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
\r
1097 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
\r
1098 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
\r
1099 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
\r
1100 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
\r
1101 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
\r
1102 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
\r
1103 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
\r
1104 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
\r
1105 macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
\r
1106 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
\r
1107 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
\r
1108 macinit.HashTableHigh = 0x0uL;
\r
1109 macinit.HashTableLow = 0x0uL;
\r
1110 macinit.PauseTime = 0x0uL;
\r
1111 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
\r
1112 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
\r
1113 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
\r
1114 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
\r
1115 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
\r
1116 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
\r
1117 macinit.VLANTagIdentifier = 0x0uL;
\r
1119 /*------------------------ ETHERNET MACCR Configuration --------------------*/
\r
1120 /* Get the ETHERNET MACCR value */
\r
1121 tmpreg = heth->Instance->MACCR;
\r
1122 /* Clear WD, PCE, PS, TE and RE bits */
\r
1123 tmpreg &= ETH_MACCR_CLEAR_MASK;
\r
1124 /* Set the WD bit according to ETH Watchdog value */
\r
1125 /* Set the JD: bit according to ETH Jabber value */
\r
1126 /* Set the IFG bit according to ETH InterFrameGap value */
\r
1127 /* Set the DCRS bit according to ETH CarrierSense value */
\r
1128 /* Set the FES bit according to ETH Speed value */
\r
1129 /* Set the DO bit according to ETH ReceiveOwn value */
\r
1130 /* Set the LM bit according to ETH LoopbackMode value */
\r
1131 /* Set the DM bit according to ETH Mode value */
\r
1132 /* Set the IPCO bit according to ETH ChecksumOffload value */
\r
1133 /* Set the DR bit according to ETH RetryTransmission value */
\r
1134 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
\r
1135 /* Set the BL bit according to ETH BackOffLimit value */
\r
1136 /* Set the DC bit according to ETH DeferralCheck value */
\r
1137 tmpreg |= (uint32_t)(macinit.Watchdog |
\r
1139 macinit.InterFrameGap |
\r
1140 macinit.CarrierSense |
\r
1141 heth->Init.Speed |
\r
1142 macinit.ReceiveOwn |
\r
1143 macinit.LoopbackMode |
\r
1144 heth->Init.DuplexMode |
\r
1145 macinit.ChecksumOffload |
\r
1146 macinit.RetryTransmission |
\r
1147 macinit.AutomaticPadCRCStrip |
\r
1148 macinit.BackOffLimit |
\r
1149 macinit.DeferralCheck);
\r
1151 /* Write to ETHERNET MACCR */
\r
1152 prvWriteMACCR( heth, tmpreg );
\r
1154 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
\r
1155 /* Set the RA bit according to ETH ReceiveAll value */
\r
1156 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
\r
1157 /* Set the PCF bit according to ETH PassControlFrames value */
\r
1158 /* Set the DBF bit according to ETH BroadcastFramesReception value */
\r
1159 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
\r
1160 /* Set the PR bit according to ETH PromiscuousMode value */
\r
1161 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
\r
1162 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
\r
1163 /* Write to ETHERNET MACFFR */
\r
1164 heth->Instance->MACFFR = (uint32_t)(macinit.ReceiveAll |
\r
1165 macinit.SourceAddrFilter |
\r
1166 macinit.PassControlFrames |
\r
1167 macinit.BroadcastFramesReception |
\r
1168 macinit.DestinationAddrFilter |
\r
1169 macinit.PromiscuousMode |
\r
1170 macinit.MulticastFramesFilter |
\r
1171 macinit.UnicastFramesFilter);
\r
1173 /* Wait until the write operation will be taken into account:
\r
1174 at least four TX_CLK/RX_CLK clock cycles */
\r
1175 tmpreg = heth->Instance->MACFFR;
\r
1177 heth->Instance->MACFFR = tmpreg;
\r
1179 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
\r
1180 /* Write to ETHERNET MACHTHR */
\r
1181 heth->Instance->MACHTHR = (uint32_t)macinit.HashTableHigh;
\r
1183 /* Write to ETHERNET MACHTLR */
\r
1184 heth->Instance->MACHTLR = (uint32_t)macinit.HashTableLow;
\r
1185 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
\r
1187 /* Get the ETHERNET MACFCR value */
\r
1188 tmpreg = heth->Instance->MACFCR;
\r
1189 /* Clear xx bits */
\r
1190 tmpreg &= ETH_MACFCR_CLEAR_MASK;
\r
1192 /* Set the PT bit according to ETH PauseTime value */
\r
1193 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
\r
1194 /* Set the PLT bit according to ETH PauseLowThreshold value */
\r
1195 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
\r
1196 /* Set the RFE bit according to ETH ReceiveFlowControl value */
\r
1197 /* Set the TFE bit according to ETH TransmitFlowControl value */
\r
1198 tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
\r
1199 macinit.ZeroQuantaPause |
\r
1200 macinit.PauseLowThreshold |
\r
1201 macinit.UnicastPauseFrameDetect |
\r
1202 macinit.ReceiveFlowControl |
\r
1203 macinit.TransmitFlowControl);
\r
1205 /* Write to ETHERNET MACFCR */
\r
1206 prvWriteMACFCR( heth, tmpreg );
\r
1208 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
\r
1209 /* Set the ETV bit according to ETH VLANTagComparison value */
\r
1210 /* Set the VL bit according to ETH VLANTagIdentifier value */
\r
1211 heth->Instance->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
\r
1212 macinit.VLANTagIdentifier);
\r
1214 /* Wait until the write operation will be taken into account:
\r
1215 at least four TX_CLK/RX_CLK clock cycles */
\r
1216 tmpreg = heth->Instance->MACVLANTR;
\r
1218 heth->Instance->MACVLANTR = tmpreg;
\r
1220 /* Ethernet DMA default initialization ************************************/
\r
1221 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
\r
1222 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
\r
1223 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
\r
1224 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
\r
1225 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
\r
1226 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
\r
1227 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
\r
1228 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
\r
1229 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
\r
1230 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
\r
1231 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
\r
1232 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
\r
1233 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
\r
1234 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
\r
1235 dmainit.DescriptorSkipLength = 0x0uL;
\r
1236 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
\r
1238 /* Get the ETHERNET DMAOMR value */
\r
1239 tmpreg = heth->Instance->DMAOMR;
\r
1240 /* Clear xx bits */
\r
1241 tmpreg &= ETH_DMAOMR_CLEAR_MASK;
\r
1243 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
\r
1244 /* Set the RSF bit according to ETH ReceiveStoreForward value */
\r
1245 /* Set the DFF bit according to ETH FlushReceivedFrame value */
\r
1246 /* Set the TSF bit according to ETH TransmitStoreForward value */
\r
1247 /* Set the TTC bit according to ETH TransmitThresholdControl value */
\r
1248 /* Set the FEF bit according to ETH ForwardErrorFrames value */
\r
1249 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
\r
1250 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
\r
1251 /* Set the OSF bit according to ETH SecondFrameOperate value */
\r
1252 tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
\r
1253 dmainit.ReceiveStoreForward |
\r
1254 dmainit.FlushReceivedFrame |
\r
1255 dmainit.TransmitStoreForward |
\r
1256 dmainit.TransmitThresholdControl |
\r
1257 dmainit.ForwardErrorFrames |
\r
1258 dmainit.ForwardUndersizedGoodFrames |
\r
1259 dmainit.ReceiveThresholdControl |
\r
1260 dmainit.SecondFrameOperate);
\r
1262 /* Write to ETHERNET DMAOMR */
\r
1263 prvWriteDMAOMR( heth, tmpreg );
\r
1265 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
\r
1266 /* Set the AAL bit according to ETH AddressAlignedBeats value */
\r
1267 /* Set the FB bit according to ETH FixedBurst value */
\r
1268 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
\r
1269 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
\r
1270 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
\r
1271 /* Set the DSL bit according to ETH DesciptorSkipLength value */
\r
1272 /* Set the PR and DA bits according to ETH DMAArbitration value */
\r
1273 heth->Instance->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
\r
1274 dmainit.FixedBurst |
\r
1275 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
\r
1276 dmainit.TxDMABurstLength |
\r
1277 dmainit.EnhancedDescriptorFormat |
\r
1278 (dmainit.DescriptorSkipLength << 2) |
\r
1279 dmainit.DMAArbitration |
\r
1280 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
\r
1282 /* Wait until the write operation will be taken into account:
\r
1283 at least four TX_CLK/RX_CLK clock cycles */
\r
1284 tmpreg = heth->Instance->DMABMR;
\r
1286 heth->Instance->DMABMR = tmpreg;
\r
1288 if(heth->Init.RxMode == ETH_RXINTERRUPT_MODE)
\r
1290 /* Enable the Ethernet Rx Interrupt */
\r
1291 __HAL_ETH_DMA_ENABLE_IT(( heth ), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
\r
1294 /* Initialize MAC address in ethernet MAC */
\r
1295 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
\r
1299 * @brief Configures the selected MAC address.
\r
1300 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1301 * the configuration information for ETHERNET module
\r
1302 * @param MacAddr: The MAC address to configure
\r
1303 * This parameter can be one of the following values:
\r
1304 * @arg ETH_MAC_Address0: MAC Address0
\r
1305 * @arg ETH_MAC_Address1: MAC Address1
\r
1306 * @arg ETH_MAC_Address2: MAC Address2
\r
1307 * @arg ETH_MAC_Address3: MAC Address3
\r
1308 * @param Addr: Pointer to MAC address buffer data (6 bytes)
\r
1309 * @retval HAL status
\r
1311 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
\r
1317 /* Check the parameters */
\r
1318 assert_param( IS_ETH_MAC_ADDRESS0123( MacAddr ) );
\r
1320 /* Calculate the selected MAC address high register */
\r
1321 /* Register ETH_MACA0HR: Bit 31 MO: Always 1. */
\r
1322 tmpreg = 0x80000000uL | ( ( uint32_t )Addr[ 5 ] << 8) | (uint32_t)Addr[ 4 ];
\r
1323 /* Load the selected MAC address high register */
\r
1324 ( * ( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_HBASE + MacAddr ) ) ) = tmpreg;
\r
1325 /* Calculate the selected MAC address low register */
\r
1326 tmpreg = ( ( uint32_t )Addr[ 3 ] << 24 ) | ( ( uint32_t )Addr[ 2 ] << 16 ) | ( ( uint32_t )Addr[ 1 ] << 8 ) | Addr[ 0 ];
\r
1328 /* Load the selected MAC address low register */
\r
1329 ( * ( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_LBASE + MacAddr ) ) ) = tmpreg;
\r
1333 * @brief Enables the MAC transmission.
\r
1334 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1335 * the configuration information for ETHERNET module
\r
1338 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
\r
1340 uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_TE;
\r
1342 prvWriteMACCR( heth, tmpreg );
\r
1346 * @brief Disables the MAC transmission.
\r
1347 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1348 * the configuration information for ETHERNET module
\r
1351 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
\r
1353 uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_TE );
\r
1355 prvWriteMACCR( heth, tmpreg );
\r
1359 * @brief Enables the MAC reception.
\r
1360 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1361 * the configuration information for ETHERNET module
\r
1364 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
\r
1366 __IO uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_RE;
\r
1368 prvWriteMACCR( heth, tmpreg );
\r
1372 * @brief Disables the MAC reception.
\r
1373 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1374 * the configuration information for ETHERNET module
\r
1377 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
\r
1379 __IO uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_RE );
\r
1381 prvWriteMACCR( heth, tmpreg );
\r
1385 * @brief Enables the DMA transmission.
\r
1386 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1387 * the configuration information for ETHERNET module
\r
1390 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
\r
1392 /* Enable the DMA transmission */
\r
1393 __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_ST;
\r
1395 prvWriteDMAOMR( heth, tmpreg );
\r
1399 * @brief Disables the DMA transmission.
\r
1400 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1401 * the configuration information for ETHERNET module
\r
1404 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
\r
1406 /* Disable the DMA transmission */
\r
1407 __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_ST );
\r
1409 prvWriteDMAOMR( heth, tmpreg );
\r
1413 * @brief Enables the DMA reception.
\r
1414 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1415 * the configuration information for ETHERNET module
\r
1418 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
\r
1420 /* Enable the DMA reception */
\r
1421 __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_SR;
\r
1423 prvWriteDMAOMR( heth, tmpreg );
\r
1427 * @brief Disables the DMA reception.
\r
1428 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1429 * the configuration information for ETHERNET module
\r
1432 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
\r
1434 /* Disable the DMA reception */
\r
1435 __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_SR );
\r
1437 prvWriteDMAOMR( heth, tmpreg );
\r
1441 * @brief Clears the ETHERNET transmit FIFO.
\r
1442 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1443 * the configuration information for ETHERNET module
\r
1446 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
\r
1448 /* Set the Flush Transmit FIFO bit */
\r
1449 __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_FTF;
\r
1451 prvWriteDMAOMR( heth, tmpreg );
\r
1457 #endif /* stm_is_F2 != 0 || stm_is_F4 != 0 || stm_is_F7 */
\r
1459 #endif /* HAL_ETH_MODULE_ENABLED */
\r
1468 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r