5 * \brief KS8851SNL registers definitions.
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7 * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
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13 * Redistribution and use in source and binary forms, with or without
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14 * modification, are permitted provided that the following conditions are met:
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16 * 1. Redistributions of source code must retain the above copyright notice,
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17 * this list of conditions and the following disclaimer.
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19 * 2. Redistributions in binary form must reproduce the above copyright notice,
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20 * this list of conditions and the following disclaimer in the documentation
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21 * and/or other materials provided with the distribution.
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23 * 3. The name of Atmel may not be used to endorse or promote products derived
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24 * from this software without specific prior written permission.
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26 * 4. This software may only be redistributed and used in connection with an
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27 * Atmel microcontroller product.
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29 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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30 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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31 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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32 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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33 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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38 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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39 * POSSIBILITY OF SUCH DAMAGE.
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45 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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48 #ifndef KSZ8851SNL_REG_H_INCLUDED
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49 #define KSZ8851SNL_REG_H_INCLUDED
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51 #define REG_ADDR_MASK (0x3F0) /* Register address mask */
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52 #define OPCODE_MASK (3 << 14)
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53 #define CMD_READ (0 << 14)
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54 #define CMD_WRITE (1 << 14)
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55 #define FIFO_READ (0x80)
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56 #define FIFO_WRITE (0xC0)
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60 * (Offset 0x00 - 0x25)
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62 #define REG_BUS_ERROR_STATUS (0x06) /* BESR */
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63 #define BUS_ERROR_IBEC (0x8000)
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64 #define BUS_ERROR_IBECV_MASK (0x7800) /* Default IPSec clock at 166Mhz */
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66 #define REG_CHIP_CFG_STATUS (0x08) /* CCFG */
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67 #define LITTLE_ENDIAN_BUS_MODE (0x0400) /* Bus in little endian mode */
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68 #define EEPROM_PRESENCE (0x0200) /* External EEPROM is used */
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69 #define SPI_BUS_MODE (0x0100) /* In SPI bus mode */
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70 #define DATA_BUS_8BIT (0x0080) /* In 8-bit bus mode operation */
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71 #define DATA_BUS_16BIT (0x0040) /* In 16-bit bus mode operation */
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72 #define DATA_BUS_32BIT (0x0020) /* In 32-bit bus mode operation */
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73 #define MULTIPLEX_MODE (0x0010) /* Data and address bus are shared */
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74 #define CHIP_PACKAGE_128PIN (0x0008) /* 128-pin package */
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75 #define CHIP_PACKAGE_80PIN (0x0004) /* 80-pin package */
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76 #define CHIP_PACKAGE_48PIN (0x0002) /* 48-pin package */
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77 #define CHIP_PACKAGE_32PIN (0x0001) /* 32-pin package for SPI host interface only */
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79 #define REG_MAC_ADDR_0 (0x10) /* MARL */
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80 #define REG_MAC_ADDR_1 (0x11) /* MARL */
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81 #define REG_MAC_ADDR_2 (0x12) /* MARM */
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82 #define REG_MAC_ADDR_3 (0x13) /* MARM */
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83 #define REG_MAC_ADDR_4 (0x14) /* MARH */
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84 #define REG_MAC_ADDR_5 (0x15) /* MARH */
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86 #define REG_BUS_CLOCK_CTRL (0x20) /* OBCR */
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87 #define BUS_CLOCK_166 (0x0004) /* 166 MHz on-chip bus clock (defaul is 125MHz) */
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88 #define BUS_CLOCK_DIVIDEDBY_5 (0x0003) /* Bus clock devided by 5 */
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89 #define BUS_CLOCK_DIVIDEDBY_3 (0x0002) /* Bus clock devided by 3 */
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90 #define BUS_CLOCK_DIVIDEDBY_2 (0x0001) /* Bus clock devided by 2 */
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91 #define BUS_CLOCK_DIVIDEDBY_1 (0x0000) /* Bus clock devided by 1 */
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92 #define BUS_CLOCK_DIVIDED_MASK (0x0003) /* Bus clock devider mask */
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94 #define BUS_SPEED_166_MHZ (0x0004) /* Set bus speed to 166 MHz */
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95 #define BUS_SPEED_125_MHZ (0x0000) /* Set bus speed to 125 MHz */
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96 #define BUS_SPEED_83_MHZ (0x0005) /* Set bus speed to 83 MHz (166/2)*/
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97 #define BUS_SPEED_62_5_MHZ (0x0001) /* Set bus speed to 62.5 MHz (125/2) */
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98 #define BUS_SPEED_53_3_MHZ (0x0006) /* Set bus speed to 53.3 MHz (166/3) */
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99 #define BUS_SPEED_41_7_MHZ (0x0002) /* Set bus speed to 41.67 MHz (125/3) */
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100 #define BUS_SPEED_33_2_MHZ (0x0007) /* Set bus speed to 33.2 MHz (166/5) */
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101 #define BUS_SPEED_25_MHZ (0x0003) /* Set bus speed to 25 MHz (125/5) */
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103 #define REG_EEPROM_CTRL (0x22) /* EEPCR */
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104 #define EEPROM_ACCESS_ENABLE (0x0010) /* Enable software to access EEPROM through bit 3 to bit 0 */
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105 #define EEPROM_DATA_IN (0x0008) /* Data receive from EEPROM (EEDI pin) */
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106 #define EEPROM_DATA_OUT (0x0004) /* Data transmit to EEPROM (EEDO pin) */
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107 #define EEPROM_SERIAL_CLOCK (0x0002) /* Serial clock (EESK pin) */
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108 #define EEPROM_CHIP_SELECT (0x0001) /* EEPROM chip select (EECS pin) */
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110 #define REG_MEM_BIST_INFO (0x24) /* MBIR */
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111 #define TX_MEM_TEST_FINISHED (0x1000) /* TX memeory BIST test finish */
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112 #define TX_MEM_TEST_FAILED (0x0800) /* TX memory BIST test fail */
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113 #define TX_MEM_TEST_FAILED_COUNT (0x0700) /* TX memory BIST test fail count */
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114 #define RX_MEM_TEST_FINISHED (0x0010) /* RX memory BIST test finish */
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115 #define RX_MEM_TEST_FAILED (0x0008) /* RX memory BIST test fail */
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116 #define RX_MEM_TEST_FAILED_COUNT (0x0003) /* RX memory BIST test fail count */
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118 #define REG_RESET_CTRL (0x26) /* GRR */
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119 #define QMU_SOFTWARE_RESET (0x0002) /* QMU soft reset (clear TxQ, RxQ) */
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120 #define GLOBAL_SOFTWARE_RESET (0x0001) /* Global soft reset (PHY, MAC, QMU) */
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123 * Wake On Lan Control Registers
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124 * (Offset 0x2A - 0x6B)
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126 #define REG_WOL_CTRL (0x2A) /* WFCR */
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127 #define WOL_MAGIC_ENABLE (0x0080) /* Enable the magic packet pattern detection */
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128 #define WOL_FRAME3_ENABLE (0x0008) /* Enable the wake up frame 3 pattern detection */
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129 #define WOL_FRAME2_ENABLE (0x0004) /* Enable the wake up frame 2 pattern detection */
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130 #define WOL_FRAME1_ENABLE (0x0002) /* Enable the wake up frame 1 pattern detection */
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131 #define WOL_FRAME0_ENABLE (0x0001) /* Enable the wake up frame 0 pattern detection */
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133 #define REG_WOL_FRAME0_CRC0 (0x30) /* WF0CRC0 */
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134 #define REG_WOL_FRAME0_CRC1 (0x32) /* WF0CRC1 */
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135 #define REG_WOL_FRAME0_BYTE_MASK0 (0x34) /* WF0BM0 */
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136 #define REG_WOL_FRAME0_BYTE_MASK1 (0x36) /* WF0BM1 */
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137 #define REG_WOL_FRAME0_BYTE_MASK2 (0x38) /* WF0BM2 */
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138 #define REG_WOL_FRAME0_BYTE_MASK3 (0x3A) /* WF0BM3 */
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140 #define REG_WOL_FRAME1_CRC0 (0x40) /* WF1CRC0 */
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141 #define REG_WOL_FRAME1_CRC1 (0x42) /* WF1CRC1 */
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142 #define REG_WOL_FRAME1_BYTE_MASK0 (0x44) /* WF1BM0 */
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143 #define REG_WOL_FRAME1_BYTE_MASK1 (0x46) /* WF1BM1 */
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144 #define REG_WOL_FRAME1_BYTE_MASK2 (0x48) /* WF1BM2 */
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145 #define REG_WOL_FRAME1_BYTE_MASK3 (0x4A) /* WF1BM3 */
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147 #define REG_WOL_FRAME2_CRC0 (0x50) /* WF2CRC0 */
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148 #define REG_WOL_FRAME2_CRC1 (0x52) /* WF2CRC1 */
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149 #define REG_WOL_FRAME2_BYTE_MASK0 (0x54) /* WF2BM0 */
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150 #define REG_WOL_FRAME2_BYTE_MASK1 (0x56) /* WF2BM1 */
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151 #define REG_WOL_FRAME2_BYTE_MASK2 (0x58) /* WF2BM2 */
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152 #define REG_WOL_FRAME2_BYTE_MASK3 (0x5A) /* WF2BM3 */
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154 #define REG_WOL_FRAME3_CRC0 (0x60) /* WF3CRC0 */
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155 #define REG_WOL_FRAME3_CRC1 (0x62) /* WF3CRC1 */
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156 #define REG_WOL_FRAME3_BYTE_MASK0 (0x64) /* WF3BM0 */
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157 #define REG_WOL_FRAME3_BYTE_MASK1 (0x66) /* WF3BM1 */
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158 #define REG_WOL_FRAME3_BYTE_MASK2 (0x68) /* WF3BM2 */
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159 #define REG_WOL_FRAME3_BYTE_MASK3 (0x6A) /* WF3BM3 */
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162 * Transmit/Receive Control Registers
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163 * (Offset 0x70 - 0x9F)
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166 /* Transmit Frame Header */
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167 #define REG_QDR_DUMMY (0x00) /* Dummy address to access QMU RxQ, TxQ */
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168 #define TX_CTRL_INTERRUPT_ON (0x8000) /* Transmit Interrupt on Completion */
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170 #define REG_TX_CTRL (0x70) /* TXCR */
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171 #define TX_CTRL_ICMP_CHECKSUM (0x0100) /* Enable ICMP frame checksum generation */
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172 #define TX_CTRL_UDP_CHECKSUM (0x0080) /* Enable UDP frame checksum generation */
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173 #define TX_CTRL_TCP_CHECKSUM (0x0040) /* Enable TCP frame checksum generation */
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174 #define TX_CTRL_IP_CHECKSUM (0x0020) /* Enable IP frame checksum generation */
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175 #define TX_CTRL_FLUSH_QUEUE (0x0010) /* Clear transmit queue, reset tx frame pointer */
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176 #define TX_CTRL_FLOW_ENABLE (0x0008) /* Enable transmit flow control */
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177 #define TX_CTRL_PAD_ENABLE (0x0004) /* Eanble adding a padding to a packet shorter than 64 bytes */
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178 #define TX_CTRL_CRC_ENABLE (0x0002) /* Enable adding a CRC to the end of transmit frame */
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179 #define TX_CTRL_ENABLE (0x0001) /* Enable tranmsit */
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181 #define REG_TX_STATUS (0x72) /* TXSR */
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182 #define TX_STAT_LATE_COL (0x2000) /* Tranmsit late collision occurs */
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183 #define TX_STAT_MAX_COL (0x1000) /* Tranmsit maximum collision is reached */
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184 #define TX_FRAME_ID_MASK (0x003F) /* Transmit frame ID mask */
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185 #define TX_STAT_ERRORS ( TX_STAT_MAX_COL | TX_STAT_LATE_COL )
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187 #define REG_RX_CTRL1 (0x74) /* RXCR1 */
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188 #define RX_CTRL_FLUSH_QUEUE (0x8000) /* Clear receive queue, reset rx frame pointer */
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189 #define RX_CTRL_UDP_CHECKSUM (0x4000) /* Enable UDP frame checksum verification */
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190 #define RX_CTRL_TCP_CHECKSUM (0x2000) /* Enable TCP frame checksum verification */
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191 #define RX_CTRL_IP_CHECKSUM (0x1000) /* Enable IP frame checksum verification */
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192 #define RX_CTRL_MAC_FILTER (0x0800) /* Receive with address that pass MAC address filtering */
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193 #define RX_CTRL_FLOW_ENABLE (0x0400) /* Enable receive flow control */
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194 #define RX_CTRL_BAD_PACKET (0x0200) /* Eanble receive CRC error frames */
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195 #define RX_CTRL_MULTICAST (0x0100) /* Receive multicast frames that pass the CRC hash filtering */
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196 #define RX_CTRL_BROADCAST (0x0080) /* Receive all the broadcast frames */
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197 #define RX_CTRL_ALL_MULTICAST (0x0040) /* Receive all the multicast frames (including broadcast frames) */
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198 #define RX_CTRL_UNICAST (0x0020) /* Receive unicast frames that match the device MAC address */
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199 #define RX_CTRL_PROMISCUOUS (0x0010) /* Receive all incoming frames, regardless of frame's DA */
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200 #define RX_CTRL_STRIP_CRC (0x0008) /* Enable strip CRC on the received frames */
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201 #define RX_CTRL_INVERSE_FILTER (0x0002) /* Receive with address check in inverse filtering mode */
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202 #define RX_CTRL_ENABLE (0x0001) /* Enable receive */
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204 /* Address filtering scheme mask */
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205 #define RX_CTRL_FILTER_MASK ( RX_CTRL_INVERSE_FILTER | RX_CTRL_PROMISCUOUS | RX_CTRL_MULTICAST | RX_CTRL_MAC_FILTER )
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207 #define REG_RX_CTRL2 (0x76) /* RXCR2 */
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208 #define RX_CTRL_IPV6_UDP_NOCHECKSUM (0x0010) /* No checksum generation and verification if IPv6 UDP is fragment */
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209 #define RX_CTRL_IPV6_UDP_CHECKSUM (0x0008) /* Receive pass IPv6 UDP frame with UDP checksum is zero */
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210 #define RX_CTRL_UDP_LITE_CHECKSUM (0x0004) /* Enable UDP Lite frame checksum generation and verification */
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211 #define RX_CTRL_ICMP_CHECKSUM (0x0002) /* Enable ICMP frame checksum verification */
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212 #define RX_CTRL_BLOCK_MAC (0x0001) /* Receive drop frame if the SA is same as device MAC address */
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213 #define RX_CTRL_BURST_LEN_MASK (0x00e0) /* SRDBL SPI Receive Data Burst Length */
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214 #define RX_CTRL_BURST_LEN_4 (0x0000)
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215 #define RX_CTRL_BURST_LEN_8 (0x0020)
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216 #define RX_CTRL_BURST_LEN_16 (0x0040)
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217 #define RX_CTRL_BURST_LEN_32 (0x0060)
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218 #define RX_CTRL_BURST_LEN_FRAME (0x0080)
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220 #define REG_TX_MEM_INFO (0x78) /* TXMIR */
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221 #define TX_MEM_AVAILABLE_MASK (0x1FFF) /* The amount of memory available in TXQ */
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223 #define REG_RX_FHR_STATUS (0x7C) /* RXFHSR */
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224 #define RX_VALID (0x8000) /* Frame in the receive packet memory is valid */
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225 #define RX_ICMP_ERROR (0x2000) /* ICMP checksum field doesn't match */
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226 #define RX_IP_ERROR (0x1000) /* IP checksum field doesn't match */
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227 #define RX_TCP_ERROR (0x0800) /* TCP checksum field doesn't match */
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228 #define RX_UDP_ERROR (0x0400) /* UDP checksum field doesn't match */
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229 #define RX_BROADCAST (0x0080) /* Received frame is a broadcast frame */
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230 #define RX_MULTICAST (0x0040) /* Received frame is a multicast frame */
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231 #define RX_UNICAST (0x0020) /* Received frame is a unicast frame */
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232 #define RX_PHY_ERROR (0x0010) /* Received frame has runt error */
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233 #define RX_FRAME_ETHER (0x0008) /* Received frame is an Ethernet-type frame */
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234 #define RX_TOO_LONG (0x0004) /* Received frame length exceeds max size 0f 2048 bytes */
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235 #define RX_RUNT_ERROR (0x0002) /* Received frame was demaged by a collision */
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236 #define RX_BAD_CRC (0x0001) /* Received frame has a CRC error */
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237 #define RX_ERRORS ( RX_BAD_CRC | RX_TOO_LONG | RX_RUNT_ERROR | RX_PHY_ERROR | \
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238 RX_ICMP_ERROR | RX_IP_ERROR | RX_TCP_ERROR | RX_UDP_ERROR )
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240 #define REG_RX_FHR_BYTE_CNT (0x7E) /* RXFHBCR */
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241 #define RX_BYTE_CNT_MASK (0x0FFF) /* Received frame byte size mask */
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243 #define REG_TXQ_CMD (0x80) /* TXQCR */
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244 #define TXQ_AUTO_ENQUEUE (0x0004) /* Enable enqueue tx frames from tx buffer automatically */
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245 #define TXQ_MEM_AVAILABLE_INT (0x0002) /* Enable generate interrupt when tx memory is available */
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246 #define TXQ_ENQUEUE (0x0001) /* Enable enqueue tx frames one frame at a time */
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248 #define REG_RXQ_CMD (0x82) /* RXQCR */
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249 #define RXQ_STAT_TIME_INT (0x1000) /* RX interrupt is occured by timer duration */
\r
250 #define RXQ_STAT_BYTE_CNT_INT (0x0800) /* RX interrupt is occured by byte count threshold */
\r
251 #define RXQ_STAT_FRAME_CNT_INT (0x0400) /* RX interrupt is occured by frame count threshold */
\r
252 #define RXQ_TWOBYTE_OFFSET (0x0200) /* Enable adding 2-byte before frame header for IP aligned with DWORD */
\r
253 #define RXQ_TIME_INT (0x0080) /* Enable RX interrupt by timer duration */
\r
254 #define RXQ_BYTE_CNT_INT (0x0040) /* Enable RX interrupt by byte count threshold */
\r
255 #define RXQ_FRAME_CNT_INT (0x0020) /* Enable RX interrupt by frame count threshold */
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256 #define RXQ_AUTO_DEQUEUE (0x0010) /* Enable release rx frames from rx buffer automatically */
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257 #define RXQ_START (0x0008) /* Start QMU transfer operation */
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258 #define RXQ_CMD_FREE_PACKET (0x0001) /* Manual dequeue (release the current frame from RxQ) */
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260 #define RXQ_CMD_CNTL (RXQ_FRAME_CNT_INT|RXQ_AUTO_DEQUEUE)
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262 #define REG_TX_ADDR_PTR (0x84) /* TXFDPR */
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263 #define REG_RX_ADDR_PTR (0x86) /* RXFDPR */
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264 #define ADDR_PTR_AUTO_INC (0x4000) /* Enable Frame data pointer increments automatically */
\r
265 #define ADDR_PTR_MASK (0x03ff) /* Address pointer mask */
\r
267 #define REG_RX_TIME_THRES (0x8C) /* RXDTTR */
\r
268 #define RX_TIME_THRESHOLD_MASK (0xFFFF) /* Set receive timer duration threshold */
\r
270 #define REG_RX_BYTE_CNT_THRES (0x8E) /* RXDBCTR */
\r
271 #define RX_BYTE_THRESHOLD_MASK (0xFFFF) /* Set receive byte count threshold */
\r
273 #define REG_INT_MASK (0x90) /* IER */
\r
274 #define INT_PHY (0x8000) /* Enable link change interrupt */
\r
275 #define INT_TX (0x4000) /* Enable transmit done interrupt */
\r
276 #define INT_RX (0x2000) /* Enable receive interrupt */
\r
277 #define INT_RX_OVERRUN (0x0800) /* Enable receive overrun interrupt */
\r
278 #define INT_TX_STOPPED (0x0200) /* Enable transmit process stopped interrupt */
\r
279 #define INT_RX_STOPPED (0x0100) /* Enable receive process stopped interrupt */
\r
280 #define INT_TX_SPACE (0x0040) /* Enable transmit space available interrupt */
\r
281 #define INT_RX_WOL_FRAME (0x0020) /* Enable WOL on receive wake-up frame detect interrupt */
\r
282 #define INT_RX_WOL_MAGIC (0x0010) /* Enable WOL on receive magic packet detect interrupt */
\r
283 #define INT_RX_WOL_LINKUP (0x0008) /* Enable WOL on link up detect interrupt */
\r
284 #define INT_RX_WOL_ENERGY (0x0004) /* Enable WOL on energy detect interrupt */
\r
285 #define INT_RX_SPI_ERROR (0x0002) /* Enable receive SPI bus error interrupt */
\r
286 #define INT_RX_WOL_DELAY_ENERGY (0x0001) /* Enable WOL on delay energy detect interrupt */
\r
287 #define INT_MASK ( INT_RX | INT_TX | INT_PHY )
\r
289 #define REG_INT_STATUS (0x92) /* ISR */
\r
291 #define REG_RX_FRAME_CNT_THRES (0x9C) /* RXFCTFC */
\r
292 #define RX_FRAME_CNT_MASK (0xFF00) /* Received frame count mask */
\r
293 #define RX_FRAME_THRESHOLD_MASK (0x00FF) /* Set receive frame count threshold mask */
\r
295 #define REG_TX_TOTAL_FRAME_SIZE (0x9E) /* TXNTFSR */
\r
296 #define TX_TOTAL_FRAME_SIZE_MASK (0xFFFF) /* Set next total tx frame size mask */
\r
299 * MAC Address Hash Table Control Registers
\r
300 * (Offset 0xA0 - 0xA7)
\r
302 #define REG_MAC_HASH_0 (0xA0) /* MAHTR0 */
\r
303 #define REG_MAC_HASH_1 (0xA1)
\r
305 #define REG_MAC_HASH_2 (0xA2) /* MAHTR1 */
\r
306 #define REG_MAC_HASH_3 (0xA3)
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308 #define REG_MAC_HASH_4 (0xA4) /* MAHTR2 */
\r
309 #define REG_MAC_HASH_5 (0xA5)
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311 #define REG_MAC_HASH_6 (0xA6) /* MAHTR3 */
\r
312 #define REG_MAC_HASH_7 (0xA7)
\r
315 * QMU Receive Queue Watermark Control Registers
\r
316 * (Offset 0xB0 - 0xB5)
\r
318 #define REG_RX_LOW_WATERMARK (0xB0) /* FCLWR */
\r
319 #define RX_LOW_WATERMARK_MASK (0x0FFF) /* Set QMU RxQ low watermark mask */
\r
321 #define REG_RX_HIGH_WATERMARK (0xB2) /* FCHWR */
\r
322 #define RX_HIGH_WATERMARK_MASK (0x0FFF) /* Set QMU RxQ high watermark mask */
\r
324 #define REG_RX_OVERRUN_WATERMARK (0xB4) /* FCOWR */
\r
325 #define RX_OVERRUN_WATERMARK_MASK (0x0FFF) /* Set QMU RxQ overrun watermark mask */
\r
328 * Global Control Registers
\r
329 * (Offset 0xC0 - 0xD3)
\r
331 #define REG_CHIP_ID (0xC0) /* CIDER */
\r
332 #define CHIP_ID_MASK (0xFFF0) /* Family ID and chip ID mask */
\r
333 #define REVISION_MASK (0x000E) /* Chip revision mask */
\r
334 #define CHIP_ID_SHIFT (4)
\r
335 #define REVISION_SHIFT (1)
\r
336 #define CHIP_ID_8851_16 (0x8870) /* KS8851-16/32MQL chip ID */
\r
338 #define REG_LED_CTRL (0xC6) /* CGCR */
\r
339 #define LED_CTRL_SEL1 (0x8000) /* Select LED3/LED2/LED1/LED0 indication */
\r
340 #define LED_CTRL_SEL0 (0x0200) /* Select LED3/LED2/LED1/LED0 indication */
\r
342 #define REG_IND_IACR (0xC8) /* IACR */
\r
343 #define TABLE_READ (0x1000) /* Indirect read */
\r
344 #define TABLE_MIB (0x0C00) /* Select MIB counter table */
\r
345 #define TABLE_ENTRY_MASK (0x001F) /* Set table entry to access */
\r
347 #define REG_IND_DATA_LOW (0xD0) /* IADLR */
\r
348 #define REG_IND_DATA_HIGH (0xD2) /* IADHR */
\r
351 * Power Management Control Registers
\r
352 * (Offset 0xD4 - 0xD7)
\r
354 #define REG_POWER_CNTL (0xD4) /* PMECR */
\r
355 #define PME_DELAY_ENABLE (0x4000) /* Enable the PME output pin assertion delay */
\r
356 #define PME_ACTIVE_HIGHT (0x1000) /* PME output pin is active high */
\r
357 #define PME_FROM_WKFRAME (0x0800) /* PME asserted when wake-up frame is detected */
\r
358 #define PME_FROM_MAGIC (0x0400) /* PME asserted when magic packet is detected */
\r
359 #define PME_FROM_LINKUP (0x0200) /* PME asserted when link up is detected */
\r
360 #define PME_FROM_ENERGY (0x0100) /* PME asserted when energy is detected */
\r
361 #define PME_EVENT_MASK (0x0F00) /* PME asserted event mask */
\r
362 #define WAKEUP_AUTO_ENABLE (0x0080) /* Enable auto wake-up in energy mode */
\r
363 #define WAKEUP_NORMAL_AUTO_ENABLE (0x0040) /* Enable auto goto normal mode from energy detecion mode */
\r
364 #define WAKEUP_FROM_WKFRAME (0x0020) /* Wake-up from wake-up frame event detected */
\r
365 #define WAKEUP_FROM_MAGIC (0x0010) /* Wake-up from magic packet event detected */
\r
366 #define WAKEUP_FROM_LINKUP (0x0008) /* Wake-up from link up event detected */
\r
367 #define WAKEUP_FROM_ENERGY (0x0004) /* Wake-up from energy event detected */
\r
368 #define WAKEUP_EVENT_MASK (0x003C) /* Wake-up event mask */
\r
369 #define POWER_STATE_D1 (0x0003) /* Power saving mode */
\r
370 #define POWER_STATE_D3 (0x0002) /* Power down mode */
\r
371 #define POWER_STATE_D2 (0x0001) /* Power detection mode */
\r
372 #define POWER_STATE_D0 (0x0000) /* Normal operation mode (default) */
\r
373 #define POWER_STATE_MASK (0x0003) /* Power management mode mask */
\r
375 #define REG_WAKEUP_TIME (0xD6) /* GSWUTR */
\r
376 #define WAKEUP_TIME (0xFF00) /* Min time (sec) wake-uo after detected energy */
\r
377 #define GOSLEEP_TIME (0x00FF) /* Min time (sec) before goto sleep when in energy mode */
\r
380 * PHY Control Registers
\r
381 * (Offset 0xD8 - 0xF9)
\r
383 #define REG_PHY_RESET (0xD8) /* PHYRR */
\r
384 #define PHY_RESET (0x0001) /* Reset PHY */
\r
386 #define REG_PHY_CNTL (0xE4) /* P1MBCR */
\r
387 #define PHY_SPEED_100MBIT (0x2000) /* Force PHY 100Mbps */
\r
388 #define PHY_AUTO_NEG_ENABLE (0x1000) /* Enable PHY auto-negotiation */
\r
389 #define PHY_POWER_DOWN (0x0800) /* Set PHY power-down */
\r
390 #define PHY_AUTO_NEG_RESTART (0x0200) /* Restart PHY auto-negotiation */
\r
391 #define PHY_FULL_DUPLEX (0x0100) /* Force PHY in full duplex mode */
\r
392 #define PHY_HP_MDIX (0x0020) /* Set PHY in HP auto MDI-X mode */
\r
393 #define PHY_FORCE_MDIX (0x0010) /* Force MDI-X */
\r
394 #define PHY_AUTO_MDIX_DISABLE (0x0008) /* Disable auto MDI-X */
\r
395 #define PHY_TRANSMIT_DISABLE (0x0002) /* Disable PHY transmit */
\r
396 #define PHY_LED_DISABLE (0x0001) /* Disable PHY LED */
\r
398 #define REG_PHY_STATUS (0xE6) /* P1MBSR */
\r
399 #define PHY_100BT4_CAPABLE (0x8000) /* 100 BASE-T4 capable */
\r
400 #define PHY_100BTX_FD_CAPABLE (0x4000) /* 100BASE-TX full duplex capable */
\r
401 #define PHY_100BTX_CAPABLE (0x2000) /* 100BASE-TX half duplex capable */
\r
402 #define PHY_10BT_FD_CAPABLE (0x1000) /* 10BASE-TX full duplex capable */
\r
403 #define PHY_10BT_CAPABLE (0x0800) /* 10BASE-TX half duplex capable */
\r
404 #define PHY_AUTO_NEG_ACKNOWLEDGE (0x0020) /* Auto-negotiation complete */
\r
405 #define PHY_AUTO_NEG_CAPABLE (0x0008) /* Auto-negotiation capable */
\r
406 #define PHY_LINK_UP (0x0004) /* PHY link is up */
\r
407 #define PHY_EXTENDED_CAPABILITY (0x0001) /* PHY extended register capable */
\r
409 #define REG_PHY_ID_LOW (0xE8) /* PHY1ILR */
\r
410 #define REG_PHY_ID_HIGH (0xEA) /* PHY1IHR */
\r
412 #define REG_PHY_AUTO_NEGOTIATION (0xEC) /* P1ANAR */
\r
413 #define PHY_AUTO_NEG_SYM_PAUSE (0x0400) /* Advertise pause capability */
\r
414 #define PHY_AUTO_NEG_100BTX_FD (0x0100) /* Advertise 100 full-duplex capability */
\r
415 #define PHY_AUTO_NEG_100BTX (0x0080) /* Advertise 100 half-duplex capability */
\r
416 #define PHY_AUTO_NEG_10BT_FD (0x0040) /* Advertise 10 full-duplex capability */
\r
417 #define PHY_AUTO_NEG_10BT (0x0020) /* Advertise 10 half-duplex capability */
\r
418 #define PHY_AUTO_NEG_SELECTOR (0x001F) /* Selector field mask */
\r
419 #define PHY_AUTO_NEG_802_3 (0x0001) /* 802.3 */
\r
421 #define REG_PHY_REMOTE_CAPABILITY (0xEE) /* P1ANLPR */
\r
422 #define PHY_REMOTE_SYM_PAUSE (0x0400) /* Link partner pause capability */
\r
423 #define PHY_REMOTE_100BTX_FD (0x0100) /* Link partner 100 full-duplex capability */
\r
424 #define PHY_REMOTE_100BTX (0x0080) /* Link partner 100 half-duplex capability */
\r
425 #define PHY_REMOTE_10BT_FD (0x0040) /* Link partner 10 full-duplex capability */
\r
426 #define PHY_REMOTE_10BT (0x0020) /* Link partner 10 half-duplex capability */
\r
428 #define REG_PORT_LINK_MD (0xF4) /* P1SCLMD */
\r
429 #define PORT_CABLE_10M_SHORT (0x8000) /* Cable length is less than 10m short */
\r
430 #define PORT_CABLE_STAT_FAILED (0x6000) /* Cable diagnostic test fail */
\r
431 #define PORT_CABLE_STAT_SHORT (0x4000) /* Short condition detected in the cable */
\r
432 #define PORT_CABLE_STAT_OPEN (0x2000) /* Open condition detected in the cable */
\r
433 #define PORT_CABLE_STAT_NORMAL (0x0000) /* Normal condition */
\r
434 #define PORT_CABLE_DIAG_RESULT (0x6000) /* Cable diagnostic test result mask */
\r
435 #define PORT_START_CABLE_DIAG (0x1000) /* Enable cable diagnostic test */
\r
436 #define PORT_FORCE_LINK (0x0800) /* Enable force link pass */
\r
437 #define PORT_POWER_SAVING (0x0400) /* Disable power saving */
\r
438 #define PORT_REMOTE_LOOPBACK (0x0200) /* Enable remote loopback at PHY */
\r
439 #define PORT_CABLE_FAULT_COUNTER (0x01FF) /* Cable length distance to the fault */
\r
441 #define REG_PORT_CTRL (0xF6) /* P1CR */
\r
442 #define PORT_LED_OFF (0x8000) /* Turn off all the port LEDs (LED3/LED2/LED1/LED0) */
\r
443 #define PORT_TX_DISABLE (0x4000) /* Disable port transmit */
\r
444 #define PORT_AUTO_NEG_RESTART (0x2000) /* Restart auto-negotiation */
\r
445 #define PORT_POWER_DOWN (0x0800) /* Set port power-down */
\r
446 #define PORT_AUTO_MDIX_DISABLE (0x0400) /* Disable auto MDI-X */
\r
447 #define PORT_FORCE_MDIX (0x0200) /* Force MDI-X */
\r
448 #define PORT_AUTO_NEG_ENABLE (0x0080) /* Enable auto-negotiation */
\r
449 #define PORT_FORCE_100_MBIT (0x0040) /* Force PHY 100Mbps */
\r
450 #define PORT_FORCE_FULL_DUPLEX (0x0020) /* Force PHY in full duplex mode */
\r
451 #define PORT_AUTO_NEG_SYM_PAUSE (0x0010) /* Advertise pause capability */
\r
452 #define PORT_AUTO_NEG_100BTX_FD (0x0008) /* Advertise 100 full-duplex capability */
\r
453 #define PORT_AUTO_NEG_100BTX (0x0004) /* Advertise 100 half-duplex capability */
\r
454 #define PORT_AUTO_NEG_10BT_FD (0x0002) /* Advertise 10 full-duplex capability */
\r
455 #define PORT_AUTO_NEG_10BT (0x0001) /* Advertise 10 half-duplex capability */
\r
457 #define REG_PORT_STATUS (0xF8) /* P1SR */
\r
458 #define PORT_HP_MDIX (0x8000) /* Set PHY in HP auto MDI-X mode */
\r
459 #define PORT_REVERSED_POLARITY (0x2000) /* Polarity is reversed */
\r
460 #define PORT_RX_FLOW_CTRL (0x1000) /* Reeive flow control feature is active */
\r
461 #define PORT_TX_FLOW_CTRL (0x0800) /* Transmit flow control feature is active */
\r
462 #define PORT_STAT_SPEED_100MBIT (0x0400) /* Link is 100Mbps */
\r
463 #define PORT_STAT_FULL_DUPLEX (0x0200) /* Link is full duplex mode */
\r
464 #define PORT_MDIX_STATUS (0x0080) /* Is MDI */
\r
465 #define PORT_AUTO_NEG_COMPLETE (0x0040) /* Auto-negotiation complete */
\r
466 #define PORT_STATUS_LINK_GOOD (0x0020) /* PHY link is up */
\r
467 #define PORT_REMOTE_SYM_PAUSE (0x0010) /* Link partner pause capability */
\r
468 #define PORT_REMOTE_100BTX_FD (0x0008) /* Link partner 100 full-duplex capability */
\r
469 #define PORT_REMOTE_100BTX (0x0004) /* Link partner 100 half-duplex capability */
\r
470 #define PORT_REMOTE_10BT_FD (0x0002) /* Link partner 10 full-duplex capability */
\r
471 #define PORT_REMOTE_10BT (0x0001) /* Link partner 10 half-duplex capability */
\r
473 #endif /* KSZ8851SNL_REG_H_INCLUDED */
\r
projects / freertos / blob