2 FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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32 >>>NOTE<<< The modification to the GPL is included to allow you to
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33 distribute a combined work that includes FreeRTOS without being obliged to
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34 provide the source code for proprietary components outside of the FreeRTOS
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35 kernel. FreeRTOS is distributed in the hope that it will be useful, but
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36 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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37 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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38 more details. You should have received a copy of the GNU General Public
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39 License and the FreeRTOS license exception along with FreeRTOS; if not it
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40 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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41 by writing to Richard Barry, contact details for whom are available on the
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46 ***************************************************************************
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48 * Having a problem? Start by reading the FAQ "My application does *
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49 * not run, what could be wrong?" *
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51 * http://www.FreeRTOS.org/FAQHelp.html *
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53 ***************************************************************************
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56 http://www.FreeRTOS.org - Documentation, training, latest versions, license
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57 and contact details.
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59 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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60 including FreeRTOS+Trace - an indispensable productivity tool.
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62 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
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63 the code with commercial support, indemnification, and middleware, under
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64 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
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65 provide a safety engineered and independently SIL3 certified version under
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66 the SafeRTOS brand: http://www.SafeRTOS.com.
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69 /* Standard includes. */
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72 /* Scheduler includes. */
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73 #include "FreeRTOS.h"
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77 /* Demo application includes. */
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78 #include "SAM7_EMAC.h"
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83 /* Hardware specific includes. */
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86 #include "AT91SAM7X256.h"
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89 /* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
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90 to use an MII interface. */
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91 #define USE_RMII_INTERFACE 0
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93 /* The buffer addresses written into the descriptors must be aligned so the
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94 last few bits are zero. These bits have special meaning for the EMAC
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95 peripheral and cannot be used as part of the address. */
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96 #define emacADDRESS_MASK ( ( unsigned long ) 0xFFFFFFFC )
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98 /* Bit used within the address stored in the descriptor to mark the last
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99 descriptor in the array. */
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100 #define emacRX_WRAP_BIT ( ( unsigned long ) 0x02 )
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102 /* Bit used within the Tx descriptor status to indicate whether the
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103 descriptor is under the control of the EMAC or the software. */
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104 #define emacTX_BUF_USED ( ( unsigned long ) 0x80000000 )
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106 /* A short delay is used to wait for a buffer to become available, should
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107 one not be immediately available when trying to transmit a frame. */
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108 #define emacBUFFER_WAIT_DELAY ( 2 )
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109 #define emacMAX_WAIT_CYCLES ( configTICK_RATE_HZ / 40 )
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111 /* Misc defines. */
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112 #define emacINTERRUPT_LEVEL ( 5 )
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113 #define emacNO_DELAY ( 0 )
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114 #define emacTOTAL_FRAME_HEADER_SIZE ( 54 )
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115 #define emacPHY_INIT_DELAY ( 5000 / portTICK_RATE_MS )
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116 #define emacRESET_KEY ( ( unsigned long ) 0xA5000000 )
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117 #define emacRESET_LENGTH ( ( unsigned long ) ( 0x01 << 8 ) )
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119 /* The Atmel header file only defines the TX frame length mask. */
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120 #define emacRX_LENGTH_FRAME ( 0xfff )
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122 /* Peripheral setup for the EMAC. */
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123 #define emacPERIPHERAL_A_SETUP ( ( unsigned long ) AT91C_PB2_ETX0 ) | \
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124 ( ( unsigned long ) AT91C_PB12_ETXER ) | \
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125 ( ( unsigned long ) AT91C_PB16_ECOL ) | \
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126 ( ( unsigned long ) AT91C_PB11_ETX3 ) | \
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127 ( ( unsigned long ) AT91C_PB6_ERX1 ) | \
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128 ( ( unsigned long ) AT91C_PB15_ERXDV ) | \
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129 ( ( unsigned long ) AT91C_PB13_ERX2 ) | \
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130 ( ( unsigned long ) AT91C_PB3_ETX1 ) | \
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131 ( ( unsigned long ) AT91C_PB8_EMDC ) | \
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132 ( ( unsigned long ) AT91C_PB5_ERX0 ) | \
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133 ( ( unsigned long ) AT91C_PB14_ERX3 ) | \
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134 ( ( unsigned long ) AT91C_PB4_ECRS_ECRSDV ) | \
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135 ( ( unsigned long ) AT91C_PB1_ETXEN ) | \
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136 ( ( unsigned long ) AT91C_PB10_ETX2 ) | \
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137 ( ( unsigned long ) AT91C_PB0_ETXCK_EREFCK ) | \
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138 ( ( unsigned long ) AT91C_PB9_EMDIO ) | \
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139 ( ( unsigned long ) AT91C_PB7_ERXER ) | \
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140 ( ( unsigned long ) AT91C_PB17_ERXCK );
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142 /*-----------------------------------------------------------*/
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145 * Prototype for the EMAC interrupt function - called by the asm wrapper.
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147 extern void vEMACISR_Wrapper( void ) __attribute__((naked));
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150 * Initialise both the Tx and Rx descriptors used by the EMAC.
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152 static void prvSetupDescriptors(void);
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155 * Write our MAC address into the EMAC. The MAC address is set as one of the
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158 static void prvSetupMACAddress( void );
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161 * Configure the EMAC and AIC for EMAC interrupts.
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163 static void prvSetupEMACInterrupt( void );
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166 * Some initialisation functions taken from the Atmel EMAC sample code.
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168 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue );
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169 #if USE_RMII_INTERFACE != 1
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170 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue);
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172 static portBASE_TYPE xGetLinkSpeed( void );
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173 static portBASE_TYPE prvProbePHY( void );
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175 /*-----------------------------------------------------------*/
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177 /* Buffer written to by the EMAC DMA. Must be aligned as described by the
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178 comment above the emacADDRESS_MASK definition. */
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179 #pragma data_alignment=8
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180 static volatile char pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ];
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182 /* Buffer read by the EMAC DMA. Must be aligned as described by he comment
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183 above the emacADDRESS_MASK definition. */
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184 #pragma data_alignment=8
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185 static char pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ];
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187 /* Descriptors used to communicate between the program and the EMAC peripheral.
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188 These descriptors hold the locations and state of the Rx and Tx buffers. */
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189 static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
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190 static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
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192 /* The IP and Ethernet addresses are read from the uIP setup. */
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193 const char cMACAddress[ 6 ] = { uipMAC_ADDR0, uipMAC_ADDR1, uipMAC_ADDR2, uipMAC_ADDR3, uipMAC_ADDR4, uipMAC_ADDR5 };
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194 const unsigned char ucIPAddress[ 4 ] = { uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 };
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196 /* The semaphore used by the EMAC ISR to wake the EMAC task. */
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197 static xSemaphoreHandle xSemaphore = NULL;
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199 /*-----------------------------------------------------------*/
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201 xSemaphoreHandle xEMACInit( void )
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203 /* Code supplied by Atmel -------------------------------*/
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205 /* Disable pull up on RXDV => PHY normal mode (not in test mode),
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206 PHY has internal pull down. */
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207 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
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209 #if USE_RMII_INTERFACE != 1
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210 /* PHY has internal pull down : set MII mode. */
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211 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 16;
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214 /* Clear PB18 <=> PHY powerdown. */
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215 AT91C_BASE_PIOB->PIO_PER = 1 << 18;
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216 AT91C_BASE_PIOB->PIO_OER = 1 << 18;
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217 AT91C_BASE_PIOB->PIO_CODR = 1 << 18;
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219 /* After PHY power up, hardware reset. */
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220 AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
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221 AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
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223 /* Wait for hardware reset end. */
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224 while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
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226 __asm volatile ( "NOP" );
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228 __asm volatile ( "NOP" );
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230 /* Setup the pins. */
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231 AT91C_BASE_PIOB->PIO_ASR = emacPERIPHERAL_A_SETUP;
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232 AT91C_BASE_PIOB->PIO_PDR = emacPERIPHERAL_A_SETUP;
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234 /* Enable com between EMAC PHY.
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236 Enable management port. */
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237 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
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239 /* MDC = MCK/32. */
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240 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
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242 /* Wait for PHY auto init end (rather crude delay!). */
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243 vTaskDelay( emacPHY_INIT_DELAY );
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245 /* PHY configuration. */
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246 #if USE_RMII_INTERFACE != 1
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248 unsigned long ulControl;
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250 /* PHY has internal pull down : disable MII isolate. */
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251 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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252 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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253 ulControl &= ~BMCR_ISOLATE;
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254 vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
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258 /* Disable management port again. */
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259 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
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261 #if USE_RMII_INTERFACE != 1
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262 /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
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263 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
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265 /* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
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267 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
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270 /* End of code supplied by Atmel ------------------------*/
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272 /* Setup the buffers and descriptors. */
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273 prvSetupDescriptors();
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275 /* Load our MAC address into the EMAC. */
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276 prvSetupMACAddress();
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278 /* Are we connected? */
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279 if( prvProbePHY() )
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281 /* Enable the interrupt! */
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282 portENTER_CRITICAL();
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284 prvSetupEMACInterrupt();
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285 vPassEMACSemaphore( xSemaphore );
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287 portEXIT_CRITICAL();
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292 /*-----------------------------------------------------------*/
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294 long lEMACSend( void )
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296 static unsigned portBASE_TYPE uxTxBufferIndex = 0;
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297 portBASE_TYPE xWaitCycles = 0;
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298 long lReturn = pdPASS;
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301 /* Is a buffer available? */
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302 while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
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304 /* There is no room to write the Tx data to the Tx buffer. Wait a
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305 short while, then try again. */
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307 if( xWaitCycles > emacMAX_WAIT_CYCLES )
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315 vTaskDelay( emacBUFFER_WAIT_DELAY );
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319 /* lReturn will only be pdPASS if a buffer is available. */
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320 if( lReturn == pdPASS )
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322 /* Copy the headers into the Tx buffer. These will be in the uIP buffer. */
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323 pcBuffer = ( char * ) xTxDescriptors[ uxTxBufferIndex ].addr;
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324 memcpy( ( void * ) pcBuffer, ( void * ) uip_buf, emacTOTAL_FRAME_HEADER_SIZE );
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326 /* If there is room, also copy in the application data if any. */
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327 if( ( uip_len > emacTOTAL_FRAME_HEADER_SIZE ) && ( uip_len <= ( ETH_TX_BUFFER_SIZE - emacTOTAL_FRAME_HEADER_SIZE ) ) )
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329 memcpy( ( void * ) &( pcBuffer[ emacTOTAL_FRAME_HEADER_SIZE ] ), ( void * ) uip_appdata, ( uip_len - emacTOTAL_FRAME_HEADER_SIZE ) );
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333 portENTER_CRITICAL();
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335 if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
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337 /* Fill out the necessary in the descriptor to get the data sent. */
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338 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned long ) AT91C_LENGTH_FRAME )
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339 | AT91C_LAST_BUFFER
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340 | AT91C_TRANSMIT_WRAP;
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341 uxTxBufferIndex = 0;
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345 /* Fill out the necessary in the descriptor to get the data sent. */
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346 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned long ) AT91C_LENGTH_FRAME )
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347 | AT91C_LAST_BUFFER;
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351 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
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353 portEXIT_CRITICAL();
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358 /*-----------------------------------------------------------*/
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360 unsigned long ulEMACPoll( void )
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362 static unsigned portBASE_TYPE ulNextRxBuffer = 0;
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363 unsigned long ulSectionLength = 0, ulLengthSoFar = 0, ulEOF = pdFALSE;
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366 /* Skip any fragments. */
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367 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
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369 /* Mark the buffer as free again. */
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370 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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372 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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374 ulNextRxBuffer = 0;
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378 /* Is there a packet ready? */
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380 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !ulSectionLength )
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382 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
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383 ulSectionLength = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & emacRX_LENGTH_FRAME;
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385 if( ulSectionLength == 0 )
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387 /* The frame is longer than the buffer pointed to by this
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388 descriptor so copy the entire buffer to uIP - then move onto
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389 the next descriptor to get the rest of the frame. */
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390 if( ( ulLengthSoFar + ETH_RX_BUFFER_SIZE ) <= UIP_BUFSIZE )
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392 memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ETH_RX_BUFFER_SIZE );
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393 ulLengthSoFar += ETH_RX_BUFFER_SIZE;
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398 /* This is the last section of the frame. Copy the section to
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400 if( ulSectionLength < UIP_BUFSIZE )
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402 /* The section length holds the length of the entire frame.
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403 ulLengthSoFar holds the length of the frame sections already
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404 copied to uIP, so the length of the final section is
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405 ulSectionLength - ulLengthSoFar; */
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406 if( ulSectionLength > ulLengthSoFar )
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408 memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ( ulSectionLength - ulLengthSoFar ) );
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412 /* Is this the last buffer for the frame? If not why? */
\r
413 ulEOF = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_EOF;
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416 /* Mark the buffer as free again. */
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417 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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419 /* Increment to the next buffer, wrapping if necessary. */
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421 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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423 ulNextRxBuffer = 0;
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427 /* If we obtained data but for some reason did not find the end of the
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428 frame then discard the data as it must contain an error. */
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431 ulSectionLength = 0;
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434 return ulSectionLength;
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436 /*-----------------------------------------------------------*/
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438 static void prvSetupDescriptors(void)
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440 unsigned portBASE_TYPE xIndex;
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441 unsigned long ulAddress;
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443 /* Initialise xRxDescriptors descriptor. */
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444 for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
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446 /* Calculate the address of the nth buffer within the array. */
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447 ulAddress = ( unsigned long )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
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449 /* Write the buffer address into the descriptor. The DMA will place
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450 the data at this address when this descriptor is being used. Mask off
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451 the bottom bits of the address as these have special meaning. */
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452 xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
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455 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
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456 to the first buffer. */
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457 xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
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459 /* Initialise xTxDescriptors. */
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460 for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
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462 /* Calculate the address of the nth buffer within the array. */
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463 ulAddress = ( unsigned long )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
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465 /* Write the buffer address into the descriptor. The DMA will read
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466 data from here when the descriptor is being used. */
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467 xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
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468 xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
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471 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
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472 to the first buffer. */
\r
473 xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
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475 /* Tell the EMAC where to find the descriptors. */
\r
476 AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned long ) xRxDescriptors;
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477 AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned long ) xTxDescriptors;
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479 /* Clear all the bits in the receive status register. */
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480 AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
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482 /* Enable the copy of data into the buffers, ignore broadcasts,
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483 and don't copy FCS. */
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484 AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
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486 /* Enable Rx and Tx, plus the stats register. */
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487 AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
\r
489 /*-----------------------------------------------------------*/
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491 static void prvSetupMACAddress( void )
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493 /* Must be written SA1L then SA1H. */
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494 AT91C_BASE_EMAC->EMAC_SA1L = ( ( unsigned long ) cMACAddress[ 3 ] << 24 ) |
\r
495 ( ( unsigned long ) cMACAddress[ 2 ] << 16 ) |
\r
496 ( ( unsigned long ) cMACAddress[ 1 ] << 8 ) |
\r
499 AT91C_BASE_EMAC->EMAC_SA1H = ( ( unsigned long ) cMACAddress[ 5 ] << 8 ) |
\r
502 /*-----------------------------------------------------------*/
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504 static void prvSetupEMACInterrupt( void )
\r
506 /* Create the semaphore used to trigger the EMAC task. */
\r
507 vSemaphoreCreateBinary( xSemaphore );
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510 /* We start by 'taking' the semaphore so the ISR can 'give' it when the
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511 first interrupt occurs. */
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512 xSemaphoreTake( xSemaphore, emacNO_DELAY );
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513 portENTER_CRITICAL();
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515 /* We want to interrupt on Rx events. */
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516 AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP;
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518 /* Enable the interrupts in the AIC. */
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519 AT91F_AIC_ConfigureIt( AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISR_Wrapper );
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520 AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_EMAC;
\r
522 portEXIT_CRITICAL();
\r
525 /*-----------------------------------------------------------*/
\r
531 * The following functions are initialisation functions taken from the Atmel
\r
532 * EMAC sample code.
\r
535 static portBASE_TYPE prvProbePHY( void )
\r
537 unsigned long ulPHYId1, ulPHYId2, ulStatus;
\r
538 portBASE_TYPE xReturn = pdPASS;
\r
540 /* Code supplied by Atmel (reformatted) -----------------*/
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542 /* Enable management port */
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543 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
\r
544 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
\r
546 /* Read the PHY ID. */
\r
547 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
\r
548 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
\r
553 Bits 3:0 Revision Number Four bit manufacturer
\92s revision number.
\r
554 0001 stands for Rev. A, etc.
\r
556 if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
\r
558 /* Did not expect this ID. */
\r
563 ulStatus = xGetLinkSpeed();
\r
565 if( ulStatus != pdPASS )
\r
571 /* Disable management port */
\r
572 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
\r
574 /* End of code supplied by Atmel ------------------------*/
\r
578 /*-----------------------------------------------------------*/
\r
580 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue )
\r
582 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
584 AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30))
\r
585 | (2 << 16) | (2 << 28)
\r
586 | ((ucPHYAddress & 0x1f) << 23)
\r
587 | (ucAddress << 18);
\r
589 /* Wait until IDLE bit in Network Status register is cleared. */
\r
590 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
595 *pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );
\r
597 /* End of code supplied by Atmel ------------------------*/
\r
599 /*-----------------------------------------------------------*/
\r
601 #if USE_RMII_INTERFACE != 1
\r
602 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue )
\r
604 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
606 AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
\r
607 | (2 << 16) | (1 << 28)
\r
608 | ((ucPHYAddress & 0x1f) << 23)
\r
609 | (ucAddress << 18))
\r
610 | (ulValue & 0xffff);
\r
612 /* Wait until IDLE bit in Network Status register is cleared */
\r
613 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
618 /* End of code supplied by Atmel ------------------------*/
\r
621 /*-----------------------------------------------------------*/
\r
623 static portBASE_TYPE xGetLinkSpeed( void )
\r
625 unsigned long ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
\r
627 /* Code supplied by Atmel (reformatted) -----------------*/
\r
629 /* Link status is latched, so read twice to get current value */
\r
630 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
631 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
633 if( !( ulBMSR & BMSR_LSTATUS ) )
\r
639 vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
\r
640 if (ulBMCR & BMCR_ANENABLE)
\r
642 /* AutoNegotiation is enabled. */
\r
643 if (!(ulBMSR & BMSR_ANEGCOMPLETE))
\r
645 /* Auto-negotiation in progress. */
\r
649 vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
\r
650 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
\r
652 ulSpeed = SPEED_100;
\r
656 ulSpeed = SPEED_10;
\r
659 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
\r
661 ulDuplex = DUPLEX_FULL;
\r
665 ulDuplex = DUPLEX_HALF;
\r
670 ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
\r
671 ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
\r
674 /* Update the MAC */
\r
675 ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
\r
676 if( ulSpeed == SPEED_100 )
\r
678 if( ulDuplex == DUPLEX_FULL )
\r
680 /* 100 Full Duplex */
\r
681 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
\r
685 /* 100 Half Duplex */
\r
686 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
\r
691 if (ulDuplex == DUPLEX_FULL)
\r
693 /* 10 Full Duplex */
\r
694 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
\r
698 /* 10 Half Duplex */
\r
699 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
\r
703 /* End of code supplied by Atmel ------------------------*/
\r