git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/serial/serial.c

   1 /*\r
   2     FreeRTOS V8.2.0rc1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     This file is part of the FreeRTOS distribution.\r
   8 \r
   9     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  10     the terms of the GNU General Public License (version 2) as published by the\r
  11     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  12 \r
  13     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
  14     >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
  15     >>!   obliged to provide the source code for proprietary components     !<<\r
  16     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  17 \r
  18     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  19     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  20     FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r
  21     link: http://www.freertos.org/a00114.html\r
  22 \r
  23     1 tab == 4 spaces!\r
  24 \r
  25     ***************************************************************************\r
  26      *                                                                       *\r
  27      *    Having a problem?  Start by reading the FAQ "My application does   *\r
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  32     ***************************************************************************\r
  33 \r
  34     ***************************************************************************\r
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  45      *                                                                       *\r
  46     ***************************************************************************\r
  47 \r
  48     ***************************************************************************\r
  49      *                                                                       *\r
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  53      *   earlier than would otherwise be possible.  Richard Barry is both    *\r
  54      *   the architect and key author of FreeRTOS, and so also the world's   *\r
  55      *   leading authority on what is the world's most popular real time     *\r
  56      *   kernel for deeply embedded MCU designs.  Obtaining your training    *\r
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  60      *   by Richard Barry:  http://www.FreeRTOS.org/contact\r
  61      *                                                                       *\r
  62     ***************************************************************************\r
  63 \r
  64     ***************************************************************************\r
  65      *                                                                       *\r
  66      *    You are receiving this top quality software for free.  Please play *\r
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  69      *    http://www.FreeRTOS.org/support                                    *\r
  70      *                                                                       *\r
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  72      *                                                                       *\r
  73     ***************************************************************************\r
  74 \r
  75     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  76     license and Real Time Engineers Ltd. contact details.\r
  77 \r
  78     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  79     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  80     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  81 \r
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  84 \r
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  86     Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  87     licenses offer ticketed support, indemnification and commercial middleware.\r
  88 \r
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  90     engineered and independently SIL3 certified version for use in safety and\r
  91     mission critical applications that require provable dependability.\r
  92 \r
  93     1 tab == 4 spaces!\r
  94 */\r
  95 \r
  96 \r
  97 /* \r
  98         BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. \r
  99 \r
 100         Note this driver is used to test the FreeRTOS port.  It is NOT intended to\r
 101         be an example of an efficient implementation!\r
 102 */\r
 103 \r
 104 /* Standard includes. */\r
 105 #include <stdlib.h>\r
 106 \r
 107 /* Scheduler includes. */\r
 108 #include "FreeRTOS.h"\r
 109 #include "queue.h"\r
 110 #include "task.h"\r
 111 \r
 112 /* Demo application includes. */\r
 113 #include "serial.h"\r
 114 \r
 115 /*-----------------------------------------------------------*/\r
 116 \r
 117 /* Constants to setup and access the UART. */\r
 118 #define serDLAB                                                 ( ( unsigned char ) 0x80 )\r
 119 #define serENABLE_INTERRUPTS                    ( ( unsigned char ) 0x03 )\r
 120 #define serNO_PARITY                                    ( ( unsigned char ) 0x00 )\r
 121 #define ser1_STOP_BIT                                   ( ( unsigned char ) 0x00 )\r
 122 #define ser8_BIT_CHARS                                  ( ( unsigned char ) 0x03 )\r
 123 #define serFIFO_ON                                              ( ( unsigned char ) 0x01 )\r
 124 #define serCLEAR_FIFO                                   ( ( unsigned char ) 0x06 )\r
 125 #define serWANTED_CLOCK_SCALING                 ( ( unsigned long ) 16 )\r
 126 \r
 127 /* Constants to setup and access the VIC. */\r
 128 #define serU1VIC_CHANNEL                                ( ( unsigned long ) 0x0007 )\r
 129 #define serU1VIC_CHANNEL_BIT                    ( ( unsigned long ) 0x0080 )\r
 130 #define serU1VIC_ENABLE                                 ( ( unsigned long ) 0x0020 )\r
 131 \r
 132 /* Misc. */\r
 133 #define serINVALID_QUEUE                                ( ( QueueHandle_t ) 0 )\r
 134 #define serHANDLE                                               ( ( xComPortHandle ) 1 )\r
 135 #define serNO_BLOCK                                             ( ( TickType_t ) 0 )\r
 136 \r
 137 /* Constant to access the VIC. */\r
 138 #define serCLEAR_VIC_INTERRUPT                  ( ( unsigned long ) 0 )\r
 139 \r
 140 /* Constants to determine the ISR source. */\r
 141 #define serSOURCE_THRE                                  ( ( unsigned char ) 0x02 )\r
 142 #define serSOURCE_RX_TIMEOUT                    ( ( unsigned char ) 0x0c )\r
 143 #define serSOURCE_ERROR                                 ( ( unsigned char ) 0x06 )\r
 144 #define serSOURCE_RX                                    ( ( unsigned char ) 0x04 )\r
 145 #define serINTERRUPT_SOURCE_MASK                ( ( unsigned char ) 0x0f )\r
 146 #define serINTERRUPT_IS_PENDING                 ( ( unsigned char ) 0x01 )\r
 147 \r
 148 /*-----------------------------------------------------------*/\r
 149 \r
 150 /*\r
 151  * The asm wrapper for the interrupt service routine.\r
 152  */\r
 153 extern void vUART_ISREntry( void );\r
 154 \r
 155 /* \r
 156  * The C function called from the asm wrapper. \r
 157  */\r
 158 void vUART_ISRHandler( void );\r
 159 \r
 160 /*-----------------------------------------------------------*/\r
 161 \r
 162 /* Queues used to hold received characters, and characters waiting to be\r
 163 transmitted. */\r
 164 static QueueHandle_t xRxedChars; \r
 165 static QueueHandle_t xCharsForTx; \r
 166 \r
 167 /* Communication flag between the interrupt service routine and serial API. */\r
 168 static volatile long lTHREEmpty;\r
 169 \r
 170 /*-----------------------------------------------------------*/\r
 171 \r
 172 xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
 173 {\r
 174 unsigned long ulDivisor, ulWantedClock;\r
 175 xComPortHandle xReturn = serHANDLE;\r
 176 \r
 177         /* Create the queues used to hold Rx and Tx characters. */\r
 178         xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );\r
 179         xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );\r
 180 \r
 181         /* Initialise the THRE empty flag. */\r
 182         lTHREEmpty = pdTRUE;\r
 183 \r
 184         if( \r
 185                 ( xRxedChars != serINVALID_QUEUE ) && \r
 186                 ( xCharsForTx != serINVALID_QUEUE ) && \r
 187                 ( ulWantedBaud != ( unsigned long ) 0 ) \r
 188           )\r
 189         {\r
 190                 portENTER_CRITICAL()\r
 191                 {\r
 192                         /* Setup the baud rate:  Calculate the divisor value. */\r
 193                         ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING;\r
 194                         ulDivisor = configCPU_CLOCK_HZ / ulWantedClock;\r
 195 \r
 196                         /* Set the DLAB bit so we can access the divisor. */\r
 197                         U1LCR |= serDLAB;\r
 198 \r
 199                         /* Setup the divisor. */\r
 200                         U1DLL = ( unsigned char ) ( ulDivisor & ( unsigned long ) 0xff );\r
 201                         ulDivisor >>= 8;\r
 202                         U1DLM = ( unsigned char ) ( ulDivisor & ( unsigned long ) 0xff );\r
 203 \r
 204                         /* Turn on the FIFO's and clear the buffers. */\r
 205                         U1FCR = ( serFIFO_ON | serCLEAR_FIFO );\r
 206 \r
 207                         /* Setup transmission format. */\r
 208                         U1LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS;\r
 209 \r
 210                         /* Setup the VIC for the UART. */\r
 211                         VICIntSelect &= ~( serU1VIC_CHANNEL_BIT );\r
 212                         VICIntEnable |= serU1VIC_CHANNEL_BIT;\r
 213                         VICVectAddr1 = ( unsigned long ) vUART_ISREntry;\r
 214                         VICVectCntl1 = serU1VIC_CHANNEL | serU1VIC_ENABLE;\r
 215 \r
 216                         /* Enable UART0 interrupts. */\r
 217                         U1IER |= serENABLE_INTERRUPTS;\r
 218                 }\r
 219                 portEXIT_CRITICAL();\r
 220         }\r
 221         else\r
 222         {\r
 223                 xReturn = ( xComPortHandle ) 0;\r
 224         }\r
 225 \r
 226         return xReturn;\r
 227 }\r
 228 /*-----------------------------------------------------------*/\r
 229 \r
 230 signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime )\r
 231 {\r
 232         /* The port handle is not required as this driver only supports UART0. */\r
 233         ( void ) pxPort;\r
 234 \r
 235         /* Get the next character from the buffer.  Return false if no characters\r
 236         are available, or arrive before xBlockTime expires. */\r
 237         if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
 238         {\r
 239                 return pdTRUE;\r
 240         }\r
 241         else\r
 242         {\r
 243                 return pdFALSE;\r
 244         }\r
 245 }\r
 246 /*-----------------------------------------------------------*/\r
 247 \r
 248 void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )\r
 249 {\r
 250 signed char *pxNext;\r
 251 \r
 252         /* NOTE: This implementation does not handle the queue being full as no\r
 253         block time is used! */\r
 254 \r
 255         /* The port handle is not required as this driver only supports UART0. */\r
 256         ( void ) pxPort;\r
 257         ( void ) usStringLength;\r
 258 \r
 259         /* Send each character in the string, one at a time. */\r
 260         pxNext = ( signed char * ) pcString;\r
 261         while( *pxNext )\r
 262         {\r
 263                 xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );\r
 264                 pxNext++;\r
 265         }\r
 266 }\r
 267 /*-----------------------------------------------------------*/\r
 268 \r
 269 signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime )\r
 270 {\r
 271 signed portBASE_TYPE xReturn;\r
 272 \r
 273         /* The port handle is not required as this driver only supports UART0. */\r
 274         ( void ) pxPort;\r
 275 \r
 276         portENTER_CRITICAL();\r
 277         {\r
 278                 /* Is there space to write directly to the UART? */\r
 279                 if( lTHREEmpty == ( long ) pdTRUE )\r
 280                 {\r
 281                         /* We wrote the character directly to the UART, so was \r
 282                         successful. */\r
 283                         lTHREEmpty = pdFALSE;\r
 284                         U1THR = cOutChar;\r
 285                         xReturn = pdPASS;\r
 286                 }\r
 287                 else \r
 288                 {\r
 289                         /* We cannot write directly to the UART, so queue the character.\r
 290                         Block for a maximum of xBlockTime if there is no space in the\r
 291                         queue.  It is ok to block within a critical section as each\r
 292                         task has it's own critical section management. */\r
 293                         xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );\r
 294 \r
 295                         /* Depending on queue sizing and task prioritisation:  While we \r
 296                         were blocked waiting to post interrupts were not disabled.  It is \r
 297                         possible that the serial ISR has emptied the Tx queue, in which\r
 298                         case we need to start the Tx off again. */\r
 299                         if( lTHREEmpty == ( long ) pdTRUE )\r
 300                         {\r
 301                                 xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );\r
 302                                 lTHREEmpty = pdFALSE;\r
 303                                 U1THR = cOutChar;\r
 304                         }\r
 305                 }\r
 306         }\r
 307         portEXIT_CRITICAL();\r
 308 \r
 309         return xReturn;\r
 310 }\r
 311 /*-----------------------------------------------------------*/\r
 312 \r
 313 void vUART_ISRHandler( void )\r
 314 {\r
 315 signed char cChar;\r
 316 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
 317 unsigned char ucInterrupt;\r
 318 \r
 319         ucInterrupt = U1IIR;\r
 320 \r
 321         /* The interrupt pending bit is active low. */\r
 322         while( ( ucInterrupt & serINTERRUPT_IS_PENDING ) == 0 )\r
 323         {\r
 324                 /* What caused the interrupt? */\r
 325                 switch( ucInterrupt & serINTERRUPT_SOURCE_MASK )\r
 326                 {\r
 327                         case serSOURCE_ERROR :  /* Not handling this, but clear the interrupt. */\r
 328                                                                         cChar = U1LSR;\r
 329                                                                         break;\r
 330         \r
 331                         case serSOURCE_THRE     :       /* The THRE is empty.  If there is another\r
 332                                                                         character in the Tx queue, send it now. */\r
 333                                                                         if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )\r
 334                                                                         {\r
 335                                                                                 U1THR = cChar;\r
 336                                                                         }\r
 337                                                                         else\r
 338                                                                         {\r
 339                                                                                 /* There are no further characters \r
 340                                                                                 queued to send so we can indicate \r
 341                                                                                 that the THRE is available. */\r
 342                                                                                 lTHREEmpty = pdTRUE;\r
 343                                                                         }\r
 344                                                                         break;\r
 345         \r
 346                         case serSOURCE_RX_TIMEOUT :\r
 347                         case serSOURCE_RX       :       /* A character was received.  Place it in \r
 348                                                                         the queue of received characters. */\r
 349                                                                         cChar = U1RBR;\r
 350                                                                         xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );\r
 351                                                                         break;\r
 352         \r
 353                         default                         :       /* There is nothing to do, leave the ISR. */\r
 354                                                                         break;\r
 355                 }\r
 356 \r
 357                 ucInterrupt = U1IIR;\r
 358         }\r
 359 \r
 360         /* Clear the ISR in the VIC. */\r
 361         VICVectAddr = serCLEAR_VIC_INTERRUPT;\r
 362 \r
 363         /* Exit the ISR.  If a task was woken by either a character being received\r
 364         or transmitted then a context switch will occur. */\r
 365         portEXIT_SWITCHING_ISR( xHigherPriorityTaskWoken );\r
 366 }\r
 367 /*-----------------------------------------------------------*/\r
 368 \r
 369 \r
 370 \r
 371 \r
 372 \r
 373 \r
 374         \r