git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/serial/serial.c

   1 /*\r
   2     FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd. \r
   3     All rights reserved\r
   4 \r
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  19     ***************************************************************************\r
  20 \r
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  38 \r
  39     ***************************************************************************\r
  40      *                                                                       *\r
  41      *    Having a problem?  Start by reading the FAQ "My application does   *\r
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  63     1 tab == 4 spaces!\r
  64 */\r
  65 \r
  66 \r
  67 /* \r
  68         BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. \r
  69 \r
  70         Note this driver is used to test the FreeRTOS port.  It is NOT intended to\r
  71         be an example of an efficient implementation!\r
  72 */\r
  73 \r
  74 /* Standard includes. */\r
  75 #include <stdlib.h>\r
  76 \r
  77 /* Scheduler includes. */\r
  78 #include "FreeRTOS.h"\r
  79 #include "queue.h"\r
  80 #include "task.h"\r
  81 \r
  82 /* Demo application includes. */\r
  83 #include "serial.h"\r
  84 \r
  85 /*-----------------------------------------------------------*/\r
  86 \r
  87 /* Constants to setup and access the UART. */\r
  88 #define serDLAB                                                 ( ( unsigned char ) 0x80 )\r
  89 #define serENABLE_INTERRUPTS                    ( ( unsigned char ) 0x03 )\r
  90 #define serNO_PARITY                                    ( ( unsigned char ) 0x00 )\r
  91 #define ser1_STOP_BIT                                   ( ( unsigned char ) 0x00 )\r
  92 #define ser8_BIT_CHARS                                  ( ( unsigned char ) 0x03 )\r
  93 #define serFIFO_ON                                              ( ( unsigned char ) 0x01 )\r
  94 #define serCLEAR_FIFO                                   ( ( unsigned char ) 0x06 )\r
  95 #define serWANTED_CLOCK_SCALING                 ( ( unsigned long ) 16 )\r
  96 \r
  97 /* Constants to setup and access the VIC. */\r
  98 #define serU1VIC_CHANNEL                                ( ( unsigned long ) 0x0007 )\r
  99 #define serU1VIC_CHANNEL_BIT                    ( ( unsigned long ) 0x0080 )\r
 100 #define serU1VIC_ENABLE                                 ( ( unsigned long ) 0x0020 )\r
 101 \r
 102 /* Misc. */\r
 103 #define serINVALID_QUEUE                                ( ( QueueHandle_t ) 0 )\r
 104 #define serHANDLE                                               ( ( xComPortHandle ) 1 )\r
 105 #define serNO_BLOCK                                             ( ( TickType_t ) 0 )\r
 106 \r
 107 /* Constant to access the VIC. */\r
 108 #define serCLEAR_VIC_INTERRUPT                  ( ( unsigned long ) 0 )\r
 109 \r
 110 /* Constants to determine the ISR source. */\r
 111 #define serSOURCE_THRE                                  ( ( unsigned char ) 0x02 )\r
 112 #define serSOURCE_RX_TIMEOUT                    ( ( unsigned char ) 0x0c )\r
 113 #define serSOURCE_ERROR                                 ( ( unsigned char ) 0x06 )\r
 114 #define serSOURCE_RX                                    ( ( unsigned char ) 0x04 )\r
 115 #define serINTERRUPT_SOURCE_MASK                ( ( unsigned char ) 0x0f )\r
 116 #define serINTERRUPT_IS_PENDING                 ( ( unsigned char ) 0x01 )\r
 117 \r
 118 /*-----------------------------------------------------------*/\r
 119 \r
 120 /*\r
 121  * The asm wrapper for the interrupt service routine.\r
 122  */\r
 123 extern void vUART_ISREntry( void );\r
 124 \r
 125 /* \r
 126  * The C function called from the asm wrapper. \r
 127  */\r
 128 void vUART_ISRHandler( void );\r
 129 \r
 130 /*-----------------------------------------------------------*/\r
 131 \r
 132 /* Queues used to hold received characters, and characters waiting to be\r
 133 transmitted. */\r
 134 static QueueHandle_t xRxedChars; \r
 135 static QueueHandle_t xCharsForTx; \r
 136 \r
 137 /* Communication flag between the interrupt service routine and serial API. */\r
 138 static volatile long lTHREEmpty;\r
 139 \r
 140 /*-----------------------------------------------------------*/\r
 141 \r
 142 xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
 143 {\r
 144 unsigned long ulDivisor, ulWantedClock;\r
 145 xComPortHandle xReturn = serHANDLE;\r
 146 \r
 147         /* Create the queues used to hold Rx and Tx characters. */\r
 148         xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );\r
 149         xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );\r
 150 \r
 151         /* Initialise the THRE empty flag. */\r
 152         lTHREEmpty = pdTRUE;\r
 153 \r
 154         if( \r
 155                 ( xRxedChars != serINVALID_QUEUE ) && \r
 156                 ( xCharsForTx != serINVALID_QUEUE ) && \r
 157                 ( ulWantedBaud != ( unsigned long ) 0 ) \r
 158           )\r
 159         {\r
 160                 portENTER_CRITICAL()\r
 161                 {\r
 162                         /* Setup the baud rate:  Calculate the divisor value. */\r
 163                         ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING;\r
 164                         ulDivisor = configCPU_CLOCK_HZ / ulWantedClock;\r
 165 \r
 166                         /* Set the DLAB bit so we can access the divisor. */\r
 167                         U1LCR |= serDLAB;\r
 168 \r
 169                         /* Setup the divisor. */\r
 170                         U1DLL = ( unsigned char ) ( ulDivisor & ( unsigned long ) 0xff );\r
 171                         ulDivisor >>= 8;\r
 172                         U1DLM = ( unsigned char ) ( ulDivisor & ( unsigned long ) 0xff );\r
 173 \r
 174                         /* Turn on the FIFO's and clear the buffers. */\r
 175                         U1FCR = ( serFIFO_ON | serCLEAR_FIFO );\r
 176 \r
 177                         /* Setup transmission format. */\r
 178                         U1LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS;\r
 179 \r
 180                         /* Setup the VIC for the UART. */\r
 181                         VICIntSelect &= ~( serU1VIC_CHANNEL_BIT );\r
 182                         VICIntEnable |= serU1VIC_CHANNEL_BIT;\r
 183                         VICVectAddr1 = ( unsigned long ) vUART_ISREntry;\r
 184                         VICVectCntl1 = serU1VIC_CHANNEL | serU1VIC_ENABLE;\r
 185 \r
 186                         /* Enable UART0 interrupts. */\r
 187                         U1IER |= serENABLE_INTERRUPTS;\r
 188                 }\r
 189                 portEXIT_CRITICAL();\r
 190         }\r
 191         else\r
 192         {\r
 193                 xReturn = ( xComPortHandle ) 0;\r
 194         }\r
 195 \r
 196         return xReturn;\r
 197 }\r
 198 /*-----------------------------------------------------------*/\r
 199 \r
 200 signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime )\r
 201 {\r
 202         /* The port handle is not required as this driver only supports UART0. */\r
 203         ( void ) pxPort;\r
 204 \r
 205         /* Get the next character from the buffer.  Return false if no characters\r
 206         are available, or arrive before xBlockTime expires. */\r
 207         if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
 208         {\r
 209                 return pdTRUE;\r
 210         }\r
 211         else\r
 212         {\r
 213                 return pdFALSE;\r
 214         }\r
 215 }\r
 216 /*-----------------------------------------------------------*/\r
 217 \r
 218 void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )\r
 219 {\r
 220 signed char *pxNext;\r
 221 \r
 222         /* NOTE: This implementation does not handle the queue being full as no\r
 223         block time is used! */\r
 224 \r
 225         /* The port handle is not required as this driver only supports UART0. */\r
 226         ( void ) pxPort;\r
 227         ( void ) usStringLength;\r
 228 \r
 229         /* Send each character in the string, one at a time. */\r
 230         pxNext = ( signed char * ) pcString;\r
 231         while( *pxNext )\r
 232         {\r
 233                 xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );\r
 234                 pxNext++;\r
 235         }\r
 236 }\r
 237 /*-----------------------------------------------------------*/\r
 238 \r
 239 signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime )\r
 240 {\r
 241 signed portBASE_TYPE xReturn;\r
 242 \r
 243         /* The port handle is not required as this driver only supports UART0. */\r
 244         ( void ) pxPort;\r
 245 \r
 246         portENTER_CRITICAL();\r
 247         {\r
 248                 /* Is there space to write directly to the UART? */\r
 249                 if( lTHREEmpty == ( long ) pdTRUE )\r
 250                 {\r
 251                         /* We wrote the character directly to the UART, so was \r
 252                         successful. */\r
 253                         lTHREEmpty = pdFALSE;\r
 254                         U1THR = cOutChar;\r
 255                         xReturn = pdPASS;\r
 256                 }\r
 257                 else \r
 258                 {\r
 259                         /* We cannot write directly to the UART, so queue the character.\r
 260                         Block for a maximum of xBlockTime if there is no space in the\r
 261                         queue.  It is ok to block within a critical section as each\r
 262                         task has it's own critical section management. */\r
 263                         xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );\r
 264 \r
 265                         /* Depending on queue sizing and task prioritisation:  While we \r
 266                         were blocked waiting to post interrupts were not disabled.  It is \r
 267                         possible that the serial ISR has emptied the Tx queue, in which\r
 268                         case we need to start the Tx off again. */\r
 269                         if( lTHREEmpty == ( long ) pdTRUE )\r
 270                         {\r
 271                                 xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );\r
 272                                 lTHREEmpty = pdFALSE;\r
 273                                 U1THR = cOutChar;\r
 274                         }\r
 275                 }\r
 276         }\r
 277         portEXIT_CRITICAL();\r
 278 \r
 279         return xReturn;\r
 280 }\r
 281 /*-----------------------------------------------------------*/\r
 282 \r
 283 void vUART_ISRHandler( void )\r
 284 {\r
 285 signed char cChar;\r
 286 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
 287 unsigned char ucInterrupt;\r
 288 \r
 289         ucInterrupt = U1IIR;\r
 290 \r
 291         /* The interrupt pending bit is active low. */\r
 292         while( ( ucInterrupt & serINTERRUPT_IS_PENDING ) == 0 )\r
 293         {\r
 294                 /* What caused the interrupt? */\r
 295                 switch( ucInterrupt & serINTERRUPT_SOURCE_MASK )\r
 296                 {\r
 297                         case serSOURCE_ERROR :  /* Not handling this, but clear the interrupt. */\r
 298                                                                         cChar = U1LSR;\r
 299                                                                         break;\r
 300         \r
 301                         case serSOURCE_THRE     :       /* The THRE is empty.  If there is another\r
 302                                                                         character in the Tx queue, send it now. */\r
 303                                                                         if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )\r
 304                                                                         {\r
 305                                                                                 U1THR = cChar;\r
 306                                                                         }\r
 307                                                                         else\r
 308                                                                         {\r
 309                                                                                 /* There are no further characters \r
 310                                                                                 queued to send so we can indicate \r
 311                                                                                 that the THRE is available. */\r
 312                                                                                 lTHREEmpty = pdTRUE;\r
 313                                                                         }\r
 314                                                                         break;\r
 315         \r
 316                         case serSOURCE_RX_TIMEOUT :\r
 317                         case serSOURCE_RX       :       /* A character was received.  Place it in \r
 318                                                                         the queue of received characters. */\r
 319                                                                         cChar = U1RBR;\r
 320                                                                         xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );\r
 321                                                                         break;\r
 322         \r
 323                         default                         :       /* There is nothing to do, leave the ISR. */\r
 324                                                                         break;\r
 325                 }\r
 326 \r
 327                 ucInterrupt = U1IIR;\r
 328         }\r
 329 \r
 330         /* Clear the ISR in the VIC. */\r
 331         VICVectAddr = serCLEAR_VIC_INTERRUPT;\r
 332 \r
 333         /* Exit the ISR.  If a task was woken by either a character being received\r
 334         or transmitted then a context switch will occur. */\r
 335         portEXIT_SWITCHING_ISR( xHigherPriorityTaskWoken );\r
 336 }\r
 337 /*-----------------------------------------------------------*/\r
 338 \r
 339 \r
 340 \r
 341 \r
 342 \r
 343 \r
 344         \r