2 * FreeRTOS Kernel V10.0.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software. If you wish to use our Amazon
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14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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23 * http://www.FreeRTOS.org
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24 * http://aws.amazon.com/freertos
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26 * 1 tab == 4 spaces!
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30 BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART1.
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33 /* Library includes. */
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34 #include "91x_lib.h"
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36 /* Scheduler includes. */
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37 #include "FreeRTOS.h"
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41 /* Demo application includes. */
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43 /*-----------------------------------------------------------*/
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46 #define serINVALID_QUEUE ( ( QueueHandle_t ) 0 )
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47 #define serNO_BLOCK ( ( TickType_t ) 0 )
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48 #define serTX_BLOCK_TIME ( 40 / portTICK_PERIOD_MS )
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50 /* Interrupt and status bit definitions. */
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51 #define mainTXRIS 0x20
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52 #define mainRXRIS 0x50
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53 #define serTX_FIFO_FULL 0x20
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54 #define serCLEAR_ALL_INTERRUPTS 0x3ff
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55 /*-----------------------------------------------------------*/
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57 /* The queue used to hold received characters. */
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58 static QueueHandle_t xRxedChars;
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60 /* The semaphore used to wake a task waiting for space to become available
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62 static SemaphoreHandle_t xTxFIFOSemaphore;
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64 /*-----------------------------------------------------------*/
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66 /* UART interrupt handler. */
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67 void UART1_IRQHandler( void );
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69 /* The interrupt service routine - called from the assembly entry point. */
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70 __arm void UART1_IRQHandler( void );
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72 /*-----------------------------------------------------------*/
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74 /* Flag to indicate whether or not a task is blocked waiting for space on
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76 static long lTaskWaiting = pdFALSE;
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79 * See the serial2.h header file.
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81 xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
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83 xComPortHandle xReturn;
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84 UART_InitTypeDef xUART1_Init;
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85 GPIO_InitTypeDef GPIO_InitStructure;
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87 /* Create the queues used to hold Rx characters. */
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88 xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
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90 /* Create the semaphore used to wake a task waiting for space to become
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91 available in the FIFO. */
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92 vSemaphoreCreateBinary( xTxFIFOSemaphore );
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94 /* If the queue/semaphore was created correctly then setup the serial port
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96 if( ( xRxedChars != serINVALID_QUEUE ) && ( xTxFIFOSemaphore != serINVALID_QUEUE ) )
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98 /* Pre take the semaphore so a task will block if it tries to access
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100 xSemaphoreTake( xTxFIFOSemaphore, 0 );
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102 /* Configure the UART. */
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103 xUART1_Init.UART_WordLength = UART_WordLength_8D;
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104 xUART1_Init.UART_StopBits = UART_StopBits_1;
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105 xUART1_Init.UART_Parity = UART_Parity_No;
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106 xUART1_Init.UART_BaudRate = ulWantedBaud;
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107 xUART1_Init.UART_HardwareFlowControl = UART_HardwareFlowControl_None;
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108 xUART1_Init.UART_Mode = UART_Mode_Tx_Rx;
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109 xUART1_Init.UART_FIFO = UART_FIFO_Enable;
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111 /* Enable the UART1 Clock */
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112 SCU_APBPeriphClockConfig( __UART1, ENABLE );
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114 /* Enable the GPIO3 Clock */
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115 SCU_APBPeriphClockConfig( __GPIO3, ENABLE );
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117 /* Configure UART1_Rx pin GPIO3.2 */
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118 GPIO_InitStructure.GPIO_Direction = GPIO_PinInput;
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119 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
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120 GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ;
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121 GPIO_InitStructure.GPIO_IPConnected = GPIO_IPConnected_Enable;
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122 GPIO_InitStructure.GPIO_Alternate = GPIO_InputAlt1 ;
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123 GPIO_Init( GPIO3, &GPIO_InitStructure );
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125 /* Configure UART1_Tx pin GPIO3.3 */
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126 GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput;
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127 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
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128 GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ;
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129 GPIO_InitStructure.GPIO_IPConnected = GPIO_IPConnected_Enable;
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130 GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt2 ;
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131 GPIO_Init( GPIO3, &GPIO_InitStructure );
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134 portENTER_CRITICAL();
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136 /* Configure the UART itself. */
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137 UART_DeInit( UART1 );
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138 UART_Init( UART1, &xUART1_Init );
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139 UART_ITConfig( UART1, UART_IT_Receive | UART_IT_Transmit, ENABLE );
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140 UART1->ICR = serCLEAR_ALL_INTERRUPTS;
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141 UART_LoopBackConfig( UART1, DISABLE );
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142 UART_IrDACmd( IrDA1, DISABLE );
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144 /* Configure the VIC for the UART interrupts. */
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145 VIC_Config( UART1_ITLine, VIC_IRQ, 9 );
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146 VIC_ITCmd( UART1_ITLine, ENABLE );
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148 UART_Cmd( UART1, ENABLE );
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149 lTaskWaiting = pdFALSE;
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151 portEXIT_CRITICAL();
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155 xReturn = ( xComPortHandle ) 0;
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158 /* This demo file only supports a single port but we have to return
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159 something to comply with the standard demo header file. */
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162 /*-----------------------------------------------------------*/
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164 signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime )
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166 /* The port handle is not required as this driver only supports one port. */
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169 /* Get the next character from the buffer. Return false if no characters
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170 are available, or arrive before xBlockTime expires. */
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171 if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
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180 /*-----------------------------------------------------------*/
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182 void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )
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184 signed char *pxNext;
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186 /* A couple of parameters that this port does not use. */
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187 ( void ) usStringLength;
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190 /* NOTE: This implementation does not handle the queue being full as no
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191 block time is used! */
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193 /* The port handle is not required as this driver only supports UART1. */
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196 /* Send each character in the string, one at a time. */
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197 pxNext = ( signed char * ) pcString;
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200 xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
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204 /*-----------------------------------------------------------*/
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206 signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime )
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208 portBASE_TYPE xReturn;
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210 portENTER_CRITICAL();
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212 /* Can we write to the FIFO? */
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213 if( UART1->FR & serTX_FIFO_FULL )
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215 /* Wait for the interrupt letting us know there is space on the
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216 FIFO. It is ok to block in a critical section, interrupts will be
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217 enabled for other tasks once we force a switch. */
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218 lTaskWaiting = pdTRUE;
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220 /* Just to be a bit different this driver uses a semaphore to
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221 block the sending task when the FIFO is full. The standard COMTest
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222 task assumes a queue of adequate length exists so does not use
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223 a block time. For this demo the block time is therefore hard
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225 xReturn = xSemaphoreTake( xTxFIFOSemaphore, serTX_BLOCK_TIME );
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228 UART1->DR = cOutChar;
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233 UART1->DR = cOutChar;
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237 portEXIT_CRITICAL();
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241 /*-----------------------------------------------------------*/
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243 void vSerialClose( xComPortHandle xPort )
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245 /* Not supported as not required by the demo application. */
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247 /*-----------------------------------------------------------*/
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249 void UART1_IRQHandler( void )
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252 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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254 while( UART1->RIS & mainRXRIS )
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256 /* The interrupt was caused by a character being received. Grab the
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257 character from the DR and place it in the queue of received
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260 xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
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263 if( UART1->RIS & mainTXRIS )
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265 if( lTaskWaiting == pdTRUE )
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267 /* This interrupt was caused by space becoming available on the Tx
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268 FIFO, wake any task that is waiting to post (if any). */
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269 xSemaphoreGiveFromISR( xTxFIFOSemaphore, &xHigherPriorityTaskWoken );
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270 lTaskWaiting = pdFALSE;
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273 UART1->ICR = mainTXRIS;
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276 /* If a task was woken by either a character being received or a character
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277 being transmitted then we may need to switch to another task. */
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278 portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
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