2 FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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71 * NOTE: Currently only timer 1 and timer 2 are used -
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73 * This file initialises two timers as follows:
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75 * Timer 0 and Timer 1 provide the interrupts that are used with the IntQ
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76 * standard demo tasks, which test interrupt nesting and using queues from
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77 * interrupts. Both these interrupts operate below the maximum syscall
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78 * interrupt priority.
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80 * Timer 2 is a much higher frequency timer that tests the nesting of interrupts
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81 * that execute above the maximum syscall interrupt priority.
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83 * All the timers can nest with the tick interrupt - creating a maximum
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84 * interrupt nesting depth of 4.
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86 * For convenience, the high frequency timer is also used to provide the time
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87 * base for the run time stats.
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90 /* Scheduler includes. */
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91 #include "FreeRTOS.h"
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93 /* Demo includes. */
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94 #include "IntQueueTimer.h"
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95 #include "IntQueue.h"
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97 /* Xilinx includes. */
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99 #include "xscugic.h"
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101 /* The frequencies at which the first two timers expire are slightly offset to
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102 ensure they don't remain synchronised. The frequency of the interrupt that
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103 operates above the max syscall interrupt priority is 10 times faster so really
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104 hammers the interrupt entry and exit code. */
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105 #define tmrTIMERS_USED 3
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106 #define tmrTIMER_0_FREQUENCY ( 100UL )
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107 #define tmrTIMER_1_FREQUENCY ( 111UL )
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108 #define tmrTIMER_2_FREQUENCY ( 20000UL )
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110 /*-----------------------------------------------------------*/
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113 * The single interrupt service routines that is used to service all three
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116 static void prvTimerHandler( void *CallBackRef );
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118 /*-----------------------------------------------------------*/
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120 /* Hardware constants. */
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121 static const BaseType_t xDeviceIDs[ tmrTIMERS_USED ] = { XPAR_XTTCPS_0_DEVICE_ID, XPAR_XTTCPS_1_DEVICE_ID, XPAR_XTTCPS_2_DEVICE_ID };
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122 static const BaseType_t xInterruptIDs[ tmrTIMERS_USED ] = { XPAR_XTTCPS_0_INTR, XPAR_XTTCPS_1_INTR, XPAR_XTTCPS_2_INTR };
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124 /* Timer configuration settings. */
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127 uint32_t OutputHz; /* Output frequency. */
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128 uint16_t Interval; /* Interval value. */
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129 uint8_t Prescaler; /* Prescaler value. */
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130 uint16_t Options; /* Option settings. */
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133 static TmrCntrSetup xTimerSettings[ tmrTIMERS_USED ] =
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135 { tmrTIMER_0_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE },
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136 { tmrTIMER_1_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE },
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137 { tmrTIMER_2_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE }
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140 /* Lower priority number means higher logical priority, so
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141 configMAX_API_CALL_INTERRUPT_PRIORITY - 1 is above the maximum system call
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142 interrupt priority. */
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143 static const UBaseType_t uxInterruptPriorities[ tmrTIMERS_USED ] =
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145 configMAX_API_CALL_INTERRUPT_PRIORITY + 1,
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146 configMAX_API_CALL_INTERRUPT_PRIORITY,
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147 configMAX_API_CALL_INTERRUPT_PRIORITY - 1
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150 static XTtcPs xTimerInstances[ tmrTIMERS_USED ];
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152 /* Used to provide a means of ensuring the intended interrupt nesting depth is
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153 actually being reached. */
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154 extern uint64_t ullPortInterruptNesting;
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155 static volatile uint32_t ulMaxRecordedNesting = 1;
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157 /* Used to ensure the high frequency timer is running at the expected
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159 static volatile uint32_t ulHighFrequencyTimerCounts = 0;
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161 /*-----------------------------------------------------------*/
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163 void vInitialiseTimerForIntQueueTest( void )
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165 BaseType_t xStatus;
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166 TmrCntrSetup *pxTimerSettings;
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167 extern XScuGic xInterruptController;
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169 XTtcPs *pxTimerInstance;
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170 XTtcPs_Config *pxTimerConfiguration;
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171 const uint8_t ucRisingEdge = 3;
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173 /*_RB_ Currently only timer 1 and timer 2 are used. */
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174 for( xTimer = 0; xTimer < ( tmrTIMERS_USED - 1 ); xTimer++ )
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176 /* Look up the timer's configuration. */
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177 pxTimerInstance = &( xTimerInstances[ xTimer ] );
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178 pxTimerConfiguration = XTtcPs_LookupConfig( xDeviceIDs[ xTimer ] );
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179 configASSERT( pxTimerConfiguration );
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181 pxTimerSettings = &( xTimerSettings[ xTimer ] );
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183 /* Initialise the device. */
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184 xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
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185 if( xStatus != XST_SUCCESS )
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187 /* Not sure how to do this before XTtcPs_CfgInitialize is called
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188 as pxTimerInstance is set within XTtcPs_CfgInitialize(). */
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189 XTtcPs_Stop( pxTimerInstance );
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190 xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
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191 configASSERT( xStatus == XST_SUCCESS );
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194 /* Set the options. */
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195 XTtcPs_SetOptions( pxTimerInstance, pxTimerSettings->Options );
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197 /* The timer frequency is preset in the pxTimerSettings structure.
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198 Derive the values for the other structure members. */
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199 XTtcPs_CalcIntervalFromFreq( pxTimerInstance, pxTimerSettings->OutputHz, &( pxTimerSettings->Interval ), &( pxTimerSettings->Prescaler ) );
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201 /* Set the interval and prescale. */
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202 XTtcPs_SetInterval( pxTimerInstance, pxTimerSettings->Interval );
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203 XTtcPs_SetPrescaler( pxTimerInstance, pxTimerSettings->Prescaler );
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205 /* The priority must be the lowest possible. */
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206 XScuGic_SetPriorityTriggerType( &xInterruptController, xInterruptIDs[ xTimer ], uxInterruptPriorities[ xTimer ] << portPRIORITY_SHIFT, ucRisingEdge );
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208 /* Connect to the interrupt controller. */
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209 xStatus = XScuGic_Connect( &xInterruptController, xInterruptIDs[ xTimer ], ( Xil_InterruptHandler ) prvTimerHandler, ( void * ) pxTimerInstance );
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210 configASSERT( xStatus == XST_SUCCESS);
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212 /* Enable the interrupt in the GIC. */
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213 XScuGic_Enable( &xInterruptController, xInterruptIDs[ xTimer ] );
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215 /* Enable the interrupts in the timer. */
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216 XTtcPs_EnableInterrupts( pxTimerInstance, XTTCPS_IXR_INTERVAL_MASK );
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218 /* Start the timer. */
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219 XTtcPs_Start( pxTimerInstance );
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222 /*-----------------------------------------------------------*/
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224 static void prvTimerHandler( void *pvCallBackRef )
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226 uint32_t ulInterruptStatus;
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227 XTtcPs *pxTimer = ( XTtcPs * ) pvCallBackRef;
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228 BaseType_t xYieldRequired;
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230 /* Read the interrupt status, then write it back to clear the interrupt. */
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231 ulInterruptStatus = XTtcPs_GetInterruptStatus( pxTimer );
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232 XTtcPs_ClearInterruptStatus( pxTimer, ulInterruptStatus );
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233 __asm volatile( "DSB SY" );
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234 __asm volatile( "ISB SY" );
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237 /* Now the interrupt has been cleared, interrupts can be re-enabled. */
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238 portENABLE_INTERRUPTS();
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240 /* Only one interrupt event type is expected. */
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241 configASSERT( ( XTTCPS_IXR_INTERVAL_MASK & ulInterruptStatus ) != 0 );
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243 /* Check the device ID to know which IntQueue demo to call. */
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244 if( pxTimer->Config.DeviceId == xDeviceIDs[ 0 ] )
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246 xYieldRequired = xFirstTimerHandler();
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248 else if( pxTimer->Config.DeviceId == xDeviceIDs[ 1 ] )
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250 xYieldRequired = xSecondTimerHandler();
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254 /* Used to check the timer is running at the expected frequency. */
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255 ulHighFrequencyTimerCounts++;
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256 xYieldRequired = pdFALSE;
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259 /* Latch the highest interrupt nesting count detected. */
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260 if( ullPortInterruptNesting > ulMaxRecordedNesting )
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262 ulMaxRecordedNesting = ullPortInterruptNesting;
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265 /* If xYieldRequired is not pdFALSE then calling either xFirstTimerHandler()
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266 or xSecondTimerHandler() resulted in a task leaving the blocked state and
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267 the task that left the blocked state had a priority higher than the currently
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268 running task (the task this interrupt interrupted) - so a context switch
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269 should be performed so the interrupt returns directly to the higher priority
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270 task. xYieldRequired is tested inside the following macro. */
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271 portYIELD_FROM_ISR( xYieldRequired );
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