1 /******************************************************************************
3 * Copyright (C) 2015 Xilinx, Inc. All rights reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
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9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * Use of the Software is limited solely to applications:
16 * (a) running on a Xilinx device, or
17 * (b) that interact with a Xilinx device through a bus or interconnect.
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31 ******************************************************************************/
32 /****************************************************************************/
39 * MODIFICATION HISTORY:
41 * Ver Who Date Changes
42 * ----- ----- -------- -----------------------------------------------------
43 * 1.00a bss 01/22/15 First release
47 *****************************************************************************/
49 #ifndef XUSBPSU_HW_H /* Prevent circular inclusions */
50 #define XUSBPSU_HW_H /* by using protection macros */
56 /***************************** Include Files ********************************/
58 /************************** Constant Definitions ****************************/
60 /**@name Register offsets
62 * The following constants provide access to each of the registers of the
67 /* XUSBPSU registers memory space boundries */
68 #define XUSBPSU_GLOBALS_REGS_START 0xc100
69 #define XUSBPSU_GLOBALS_REGS_END 0xc6ff
70 #define XUSBPSU_DEVICE_REGS_START 0xc700
71 #define XUSBPSU_DEVICE_REGS_END 0xcbff
72 #define XUSBPSU_OTG_REGS_START 0xcc00
73 #define XUSBPSU_OTG_REGS_END 0xccff
75 /* Global Registers */
76 #define XUSBPSU_GSBUSCFG0 0xc100
77 #define XUSBPSU_GSBUSCFG1 0xc104
78 #define XUSBPSU_GTXTHRCFG 0xc108
79 #define XUSBPSU_GRXTHRCFG 0xc10c
80 #define XUSBPSU_GCTL 0xc110
81 #define XUSBPSU_GEVTEN 0xc114
82 #define XUSBPSU_GSTS 0xc118
83 #define XUSBPSU_GSNPSID 0xc120
84 #define XUSBPSU_GGPIO 0xc124
85 #define XUSBPSU_GUID 0xc128
86 #define XUSBPSU_GUCTL 0xc12c
87 #define XUSBPSU_GBUSERRADDR0 0xc130
88 #define XUSBPSU_GBUSERRADDR1 0xc134
89 #define XUSBPSU_GPRTBIMAP0 0xc138
90 #define XUSBPSU_GPRTBIMAP1 0xc13c
91 #define XUSBPSU_GHWPARAMS0_OFFSET 0xc140
92 #define XUSBPSU_GHWPARAMS1_OFFSET 0xc144
93 #define XUSBPSU_GHWPARAMS2_OFFSET 0xc148
94 #define XUSBPSU_GHWPARAMS3_OFFSET 0xc14c
95 #define XUSBPSU_GHWPARAMS4_OFFSET 0xc150
96 #define XUSBPSU_GHWPARAMS5_OFFSET 0xc154
97 #define XUSBPSU_GHWPARAMS6_OFFSET 0xc158
98 #define XUSBPSU_GHWPARAMS7_OFFSET 0xc15c
99 #define XUSBPSU_GDBGFIFOSPACE 0xc160
100 #define XUSBPSU_GDBGLTSSM 0xc164
101 #define XUSBPSU_GPRTBIMAP_HS0 0xc180
102 #define XUSBPSU_GPRTBIMAP_HS1 0xc184
103 #define XUSBPSU_GPRTBIMAP_FS0 0xc188
104 #define XUSBPSU_GPRTBIMAP_FS1 0xc18c
106 #define XUSBPSU_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
107 #define XUSBPSU_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
109 #define XUSBPSU_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
111 #define XUSBPSU_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
113 #define XUSBPSU_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
114 #define XUSBPSU_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
116 #define XUSBPSU_GEVNTADRLO(n) (0xc400 + (n * 0x10))
117 #define XUSBPSU_GEVNTADRHI(n) (0xc404 + (n * 0x10))
118 #define XUSBPSU_GEVNTSIZ(n) (0xc408 + (n * 0x10))
119 #define XUSBPSU_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
121 #define XUSBPSU_GHWPARAMS8 0xc600
123 /* Device Registers */
124 #define XUSBPSU_DCFG 0xc700
125 #define XUSBPSU_DCTL 0xc704
126 #define XUSBPSU_DEVTEN 0xc708
127 #define XUSBPSU_DSTS 0xc70c
128 #define XUSBPSU_DGCMDPAR 0xc710
129 #define XUSBPSU_DGCMD 0xc714
130 #define XUSBPSU_DALEPENA 0xc720
131 #define XUSBPSU_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
132 #define XUSBPSU_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
133 #define XUSBPSU_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
134 #define XUSBPSU_DEPCMD(n) (0xc80c + (n * 0x10))
137 #define XUSBPSU_OCFG 0xcc00
138 #define XUSBPSU_OCTL 0xcc04
139 #define XUSBPSU_OEVT 0xcc08
140 #define XUSBPSU_OEVTEN 0xcc0C
141 #define XUSBPSU_OSTS 0xcc10
145 /* Global Configuration Register */
146 #define XUSBPSU_GCTL_PWRDNSCALE(n) ((n) << 19)
147 #define XUSBPSU_GCTL_U2RSTECN (1 << 16)
148 #define XUSBPSU_GCTL_RAMCLKSEL(x) (((x) & XUSBPSU_GCTL_CLK_MASK) << 6)
149 #define XUSBPSU_GCTL_CLK_BUS (0)
150 #define XUSBPSU_GCTL_CLK_PIPE (1)
151 #define XUSBPSU_GCTL_CLK_PIPEHALF (2)
152 #define XUSBPSU_GCTL_CLK_MASK (3)
154 #define XUSBPSU_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
155 #define XUSBPSU_GCTL_PRTCAPDIR(n) ((n) << 12)
156 #define XUSBPSU_GCTL_PRTCAP_HOST 1
157 #define XUSBPSU_GCTL_PRTCAP_DEVICE 2
158 #define XUSBPSU_GCTL_PRTCAP_OTG 3
160 #define XUSBPSU_GCTL_CORESOFTRESET (1 << 11)
161 #define XUSBPSU_GCTL_SOFITPSYNC (1 << 10)
162 #define XUSBPSU_GCTL_SCALEDOWN(n) ((n) << 4)
163 #define XUSBPSU_GCTL_SCALEDOWN_MASK XUSBPSU_GCTL_SCALEDOWN(3)
164 #define XUSBPSU_GCTL_DISSCRAMBLE (1 << 3)
165 #define XUSBPSU_GCTL_GBLHIBERNATIONEN (1 << 1)
166 #define XUSBPSU_GCTL_DSBLCLKGTNG (1 << 0)
168 /* Global Status Register Device Interrupt Mask */
169 #define XUSBPSU_GSTS_DEVICE_IP_MASK 0x00000040
171 /* Global USB2 PHY Configuration Register */
172 #define XUSBPSU_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
173 #define XUSBPSU_GUSB2PHYCFG_SUSPHY (1 << 6)
175 /* Global USB3 PIPE Control Register */
176 #define XUSBPSU_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
177 #define XUSBPSU_GUSB3PIPECTL_SUSPHY (1 << 17)
179 /* Global TX Fifo Size Register */
180 #define XUSBPSU_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
181 #define XUSBPSU_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
183 /* Global Event Size Registers */
184 #define XUSBPSU_GEVNTSIZ_INTMASK (1 << 31)
185 #define XUSBPSU_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
187 /* Global HWPARAMS1 Register */
188 #define XUSBPSU_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
189 #define XUSBPSU_GHWPARAMS1_EN_PWROPT_NO 0
190 #define XUSBPSU_GHWPARAMS1_EN_PWROPT_CLK 1
191 #define XUSBPSU_GHWPARAMS1_EN_PWROPT_HIB 2
192 #define XUSBPSU_GHWPARAMS1_PWROPT(n) ((n) << 24)
193 #define XUSBPSU_GHWPARAMS1_PWROPT_MASK XUSBPSU_GHWPARAMS1_PWROPT(3)
195 /* Global HWPARAMS4 Register */
196 #define XUSBPSU_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
197 #define XUSBPSU_MAX_HIBER_SCRATCHBUFS 15
199 /* Device Configuration Register */
200 #define XUSBPSU_DCFG_DEVADDR(addr) ((addr) << 3)
201 #define XUSBPSU_DCFG_DEVADDR_MASK XUSBPSU_DCFG_DEVADDR(0x7f)
203 #define XUSBPSU_DCFG_SPEED_MASK 7
204 #define XUSBPSU_DCFG_SUPERSPEED 4
205 #define XUSBPSU_DCFG_HIGHSPEED 0
206 #define XUSBPSU_DCFG_FULLSPEED2 1
207 #define XUSBPSU_DCFG_LOWSPEED 2
208 #define XUSBPSU_DCFG_FULLSPEED1 3
210 #define XUSBPSU_DCFG_LPM_CAP (1 << 22)
212 /* Device Control Register */
213 #define XUSBPSU_DCTL_RUN_STOP (1 << 31)
214 #define XUSBPSU_DCTL_CSFTRST (1 << 30)
215 #define XUSBPSU_DCTL_LSFTRST (1 << 29)
217 #define XUSBPSU_DCTL_HIRD_THRES_MASK (0x1f << 24)
218 #define XUSBPSU_DCTL_HIRD_THRES(n) ((n) << 24)
220 #define XUSBPSU_DCTL_APPL1RES (1 << 23)
222 /* These apply for core versions 1.87a and earlier */
223 #define XUSBPSU_DCTL_TRGTULST_MASK (0x0f << 17)
224 #define XUSBPSU_DCTL_TRGTULST(n) ((n) << 17)
225 #define XUSBPSU_DCTL_TRGTULST_U2 (XUSBPSU_DCTL_TRGTULST(2))
226 #define XUSBPSU_DCTL_TRGTULST_U3 (XUSBPSU_DCTL_TRGTULST(3))
227 #define XUSBPSU_DCTL_TRGTULST_SS_DIS (XUSBPSU_DCTL_TRGTULST(4))
228 #define XUSBPSU_DCTL_TRGTULST_RX_DET (XUSBPSU_DCTL_TRGTULST(5))
229 #define XUSBPSU_DCTL_TRGTULST_SS_INACT (XUSBPSU_DCTL_TRGTULST(6))
231 /* These apply for core versions 1.94a and later */
232 #define XUSBPSU_DCTL_KEEP_CONNECT (1 << 19)
233 #define XUSBPSU_DCTL_L1_HIBER_EN (1 << 18)
234 #define XUSBPSU_DCTL_CRS (1 << 17)
235 #define XUSBPSU_DCTL_CSS (1 << 16)
237 #define XUSBPSU_DCTL_INITU2ENA (1 << 12)
238 #define XUSBPSU_DCTL_ACCEPTU2ENA (1 << 11)
239 #define XUSBPSU_DCTL_INITU1ENA (1 << 10)
240 #define XUSBPSU_DCTL_ACCEPTU1ENA (1 << 9)
241 #define XUSBPSU_DCTL_TSTCTRL_MASK (0xf << 1)
243 #define XUSBPSU_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
244 #define XUSBPSU_DCTL_ULSTCHNGREQ(n) (((n) << 5) & XUSBPSU_DCTL_ULSTCHNGREQ_MASK)
246 #define XUSBPSU_DCTL_ULSTCHNG_NO_ACTION (XUSBPSU_DCTL_ULSTCHNGREQ(0))
247 #define XUSBPSU_DCTL_ULSTCHNG_SS_DISABLED (XUSBPSU_DCTL_ULSTCHNGREQ(4))
248 #define XUSBPSU_DCTL_ULSTCHNG_RX_DETECT (XUSBPSU_DCTL_ULSTCHNGREQ(5))
249 #define XUSBPSU_DCTL_ULSTCHNG_SS_INACTIVE (XUSBPSU_DCTL_ULSTCHNGREQ(6))
250 #define XUSBPSU_DCTL_ULSTCHNG_RECOVERY (XUSBPSU_DCTL_ULSTCHNGREQ(8))
251 #define XUSBPSU_DCTL_ULSTCHNG_COMPLIANCE (XUSBPSU_DCTL_ULSTCHNGREQ(10))
252 #define XUSBPSU_DCTL_ULSTCHNG_LOOPBACK (XUSBPSU_DCTL_ULSTCHNGREQ(11))
254 /* Device Event Enable Register */
255 #define XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
256 #define XUSBPSU_DEVTEN_EVNTOVERFLOWEN (1 << 11)
257 #define XUSBPSU_DEVTEN_CMDCMPLTEN (1 << 10)
258 #define XUSBPSU_DEVTEN_ERRTICERREN (1 << 9)
259 #define XUSBPSU_DEVTEN_SOFEN (1 << 7)
260 #define XUSBPSU_DEVTEN_EOPFEN (1 << 6)
261 #define XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
262 #define XUSBPSU_DEVTEN_WKUPEVTEN (1 << 4)
263 #define XUSBPSU_DEVTEN_ULSTCNGEN (1 << 3)
264 #define XUSBPSU_DEVTEN_CONNECTDONEEN (1 << 2)
265 #define XUSBPSU_DEVTEN_USBRSTEN (1 << 1)
266 #define XUSBPSU_DEVTEN_DISCONNEVTEN (1 << 0)
268 /* Device Status Register */
269 #define XUSBPSU_DSTS_DCNRD (1 << 29)
271 /* This applies for core versions 1.87a and earlier */
272 #define XUSBPSU_DSTS_PWRUPREQ (1 << 24)
274 /* These apply for core versions 1.94a and later */
275 #define XUSBPSU_DSTS_RSS (1 << 25)
276 #define XUSBPSU_DSTS_SSS (1 << 24)
278 #define XUSBPSU_DSTS_COREIDLE (1 << 23)
279 #define XUSBPSU_DSTS_DEVCTRLHLT (1 << 22)
281 #define XUSBPSU_DSTS_USBLNKST_MASK (0x0f << 18)
282 #define XUSBPSU_DSTS_USBLNKST(n) (((n) & XUSBPSU_DSTS_USBLNKST_MASK) >> 18)
284 #define XUSBPSU_DSTS_RXFIFOEMPTY (1 << 17)
286 #define XUSBPSU_DSTS_SOFFN_MASK (0x3fff << 3)
287 #define XUSBPSU_DSTS_SOFFN(n) (((n) & XUSBPSU_DSTS_SOFFN_MASK) >> 3)
289 #define XUSBPSU_DSTS_CONNECTSPD (7 << 0)
291 #define XUSBPSU_DSTS_SUPERSPEED (4 << 0)
292 #define XUSBPSU_DSTS_HIGHSPEED (0 << 0)
293 #define XUSBPSU_DSTS_FULLSPEED2 (1 << 0)
294 #define XUSBPSU_DSTS_LOWSPEED (2 << 0)
295 #define XUSBPSU_DSTS_FULLSPEED1 (3 << 0)
297 /* Device Generic Command Register */
298 #define XUSBPSU_DGCMD_SET_LMP 0x01
299 #define XUSBPSU_DGCMD_SET_PERIODIC_PAR 0x02
300 #define XUSBPSU_DGCMD_XMIT_FUNCTION 0x03
302 /* These apply for core versions 1.94a and later */
303 #define XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
304 #define XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
306 #define XUSBPSU_DGCMD_SELECTED_FIFO_FLUSH 0x09
307 #define XUSBPSU_DGCMD_ALL_FIFO_FLUSH 0x0a
308 #define XUSBPSU_DGCMD_SET_ENDPOINT_NRDY 0x0c
309 #define XUSBPSU_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
311 #define XUSBPSU_DGCMD_STATUS(n) (((n) >> 15) & 1)
312 #define XUSBPSU_DGCMD_CMDACT (1 << 10)
313 #define XUSBPSU_DGCMD_CMDIOC (1 << 8)
315 /* Device Generic Command Parameter Register */
316 #define XUSBPSU_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
317 #define XUSBPSU_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
318 #define XUSBPSU_DGCMDPAR_RX_FIFO (0 << 5)
319 #define XUSBPSU_DGCMDPAR_TX_FIFO (1 << 5)
320 #define XUSBPSU_DGCMDPAR_LOOPBACK_DIS (0 << 0)
321 #define XUSBPSU_DGCMDPAR_LOOPBACK_ENA (1 << 0)
323 /* Device Endpoint Command Register */
324 #define XUSBPSU_DEPCMD_PARAM_SHIFT 16
325 #define XUSBPSU_DEPCMD_PARAM(x) ((x) << XUSBPSU_DEPCMD_PARAM_SHIFT)
326 #define XUSBPSU_DEPCMD_GET_RSC_IDX(x) (((x) >> XUSBPSU_DEPCMD_PARAM_SHIFT) & \
328 #define XUSBPSU_DEPCMD_STATUS(x) (((x) >> 12) & 0xF)
329 #define XUSBPSU_DEPCMD_HIPRI_FORCERM (1 << 11)
330 #define XUSBPSU_DEPCMD_CMDACT (1 << 10)
331 #define XUSBPSU_DEPCMD_CMDIOC (1 << 8)
333 #define XUSBPSU_DEPCMD_DEPSTARTCFG 0x09
334 #define XUSBPSU_DEPCMD_ENDTRANSFER 0x08
335 #define XUSBPSU_DEPCMD_UPDATETRANSFER 0x07
336 #define XUSBPSU_DEPCMD_STARTTRANSFER 0x06
337 #define XUSBPSU_DEPCMD_CLEARSTALL 0x05
338 #define XUSBPSU_DEPCMD_SETSTALL 0x04
339 #define XUSBPSU_DEPCMD_GETEPSTATE 0x03
340 #define XUSBPSU_DEPCMD_SETTRANSFRESOURCE 0x02
341 #define XUSBPSU_DEPCMD_SETEPCONFIG 0x01
343 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
344 #define XUSBPSU_DALEPENA_EP(n) (1 << n)
346 #define XUSBPSU_DEPCFG_INT_NUM(n) ((n) << 0)
347 #define XUSBPSU_DEPCFG_XFER_COMPLETE_EN (1 << 8)
348 #define XUSBPSU_DEPCFG_XFER_IN_PROGRESS_EN (1 << 9)
349 #define XUSBPSU_DEPCFG_XFER_NOT_READY_EN (1 << 10)
350 #define XUSBPSU_DEPCFG_FIFO_ERROR_EN (1 << 11)
351 #define XUSBPSU_DEPCFG_STREAM_EVENT_EN (1 << 13)
352 #define XUSBPSU_DEPCFG_BINTERVAL_M1(n) ((n) << 16)
353 #define XUSBPSU_DEPCFG_STREAM_CAPABLE (1 << 24)
354 #define XUSBPSU_DEPCFG_EP_NUMBER(n) ((n) << 25)
355 #define XUSBPSU_DEPCFG_BULK_BASED (1 << 30)
356 #define XUSBPSU_DEPCFG_FIFO_BASED (1 << 31)
358 /* DEPCFG parameter 0 */
359 #define XUSBPSU_DEPCFG_EP_TYPE(n) ((n) << 1)
360 #define XUSBPSU_DEPCFG_MAX_PACKET_SIZE(n) ((n) << 3)
361 #define XUSBPSU_DEPCFG_FIFO_NUMBER(n) ((n) << 17)
362 #define XUSBPSU_DEPCFG_BURST_SIZE(n) ((n) << 22)
363 #define XUSBPSU_DEPCFG_DATA_SEQ_NUM(n) ((n) << 26)
364 /* This applies for core versions earlier than 1.94a */
365 #define XUSBPSU_DEPCFG_IGN_SEQ_NUM (1 << 31)
366 /* These apply for core versions 1.94a and later */
367 #define XUSBPSU_DEPCFG_ACTION_INIT (0 << 30)
368 #define XUSBPSU_DEPCFG_ACTION_RESTORE (1 << 30)
369 #define XUSBPSU_DEPCFG_ACTION_MODIFY (2 << 30)
371 /* DEPXFERCFG parameter 0 */
372 #define XUSBPSU_DEPXFERCFG_NUM_XFER_RES(n) ((n) & 0xffff)
374 #define XUSBPSU_DEPCMD_TYPE_BULK 2
375 #define XUSBPSU_DEPCMD_TYPE_INTR 3
377 /* TRB Length, PCM and Status */
378 #define XUSBPSU_TRB_SIZE_MASK (0x00ffffff)
379 #define XUSBPSU_TRB_SIZE_LENGTH(n) ((n) & XUSBPSU_TRB_SIZE_MASK)
380 #define XUSBPSU_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
381 #define XUSBPSU_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
383 #define XUSBPSU_TRBSTS_OK 0
384 #define XUSBPSU_TRBSTS_MISSED_ISOC 1
385 #define XUSBPSU_TRBSTS_SETUP_PENDING 2
386 #define XUSBPSU_TRB_STS_XFER_IN_PROG 4
389 #define XUSBPSU_TRB_CTRL_HWO (1 << 0)
390 #define XUSBPSU_TRB_CTRL_LST (1 << 1)
391 #define XUSBPSU_TRB_CTRL_CHN (1 << 2)
392 #define XUSBPSU_TRB_CTRL_CSP (1 << 3)
393 #define XUSBPSU_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
394 #define XUSBPSU_TRB_CTRL_ISP_IMI (1 << 10)
395 #define XUSBPSU_TRB_CTRL_IOC (1 << 11)
396 #define XUSBPSU_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
398 #define XUSBPSU_TRBCTL_NORMAL XUSBPSU_TRB_CTRL_TRBCTL(1)
399 #define XUSBPSU_TRBCTL_CONTROL_SETUP XUSBPSU_TRB_CTRL_TRBCTL(2)
400 #define XUSBPSU_TRBCTL_CONTROL_STATUS2 XUSBPSU_TRB_CTRL_TRBCTL(3)
401 #define XUSBPSU_TRBCTL_CONTROL_STATUS3 XUSBPSU_TRB_CTRL_TRBCTL(4)
402 #define XUSBPSU_TRBCTL_CONTROL_DATA XUSBPSU_TRB_CTRL_TRBCTL(5)
403 #define XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST XUSBPSU_TRB_CTRL_TRBCTL(6)
404 #define XUSBPSU_TRBCTL_ISOCHRONOUS XUSBPSU_TRB_CTRL_TRBCTL(7)
405 #define XUSBPSU_TRBCTL_LINK_TRB XUSBPSU_TRB_CTRL_TRBCTL(8)
409 /**************************** Type Definitions *******************************/
411 /***************** Macros (Inline Functions) Definitions *********************/
413 /*****************************************************************************/
416 * Read a register of the USBPS8 device. This macro provides register
417 * access to all registers using the register offsets defined above.
419 * @param InstancePtr is a pointer to the XUsbPsu instance.
420 * @param Offset is the offset of the register to read.
422 * @return The contents of the register.
424 * @note C-style Signature:
425 * u32 XUsbPsu_ReadReg(struct XUsbPsu *InstancePtr, u32 Offset);
427 ******************************************************************************/
428 #define XUsbPsu_ReadReg(InstancePtr, Offset) \
429 Xil_In32((InstancePtr)->ConfigPtr->BaseAddress + (Offset))
431 /*****************************************************************************/
434 * Write a register of the USBPS8 device. This macro provides
435 * register access to all registers using the register offsets defined above.
437 * @param InstancePtr is a pointer to the XUsbPsu instance.
438 * @param RegOffset is the offset of the register to write.
439 * @param Data is the value to write to the register.
443 * @note C-style Signature:
444 * void XUsbPsu_WriteReg(struct XUsbPsu *InstancePtr,
445 * u32 Offset,u32 Data)
447 ******************************************************************************/
448 #define XUsbPsu_WriteReg(InstancePtr, Offset, Data) \
449 Xil_Out32((InstancePtr)->ConfigPtr->BaseAddress + (Offset), (Data))
451 /************************** Function Prototypes ******************************/
457 #endif /* End of protection macro. */
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