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[freertos] / FreeRTOS / Demo / CORTEX_A53_64-bit_UltraScale_MPSoC / RTOSDemo_A53_bsp / psu_cortexa53_0 / libsrc / axipmon_v6_6 / src / xaxipmon_g.c
1 \r
2 /*******************************************************************\r
3 *\r
4 * CAUTION: This file is automatically generated by HSI.\r
5 * Version: \r
6 * DO NOT EDIT.\r
7 *\r
8 * Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*\r
9 *Permission is hereby granted, free of charge, to any person obtaining a copy\r
10 *of this software and associated documentation files (the Software), to deal\r
11 *in the Software without restriction, including without limitation the rights\r
12 *to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
13 *copies of the Software, and to permit persons to whom the Software is\r
14 *furnished to do so, subject to the following conditions:\r
15 *\r
16 *The above copyright notice and this permission notice shall be included in\r
17 *all copies or substantial portions of the Software.\r
18\r
19 * Use of the Software is limited solely to applications:\r
20 *(a) running on a Xilinx device, or\r
21 *(b) that interact with a Xilinx device through a bus or interconnect.\r
22 *\r
23 *THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
24 *IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
25 *FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
26 *XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
27 *WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
28 *OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
29 *\r
30 *Except as contained in this notice, the name of the Xilinx shall not be used\r
31 *in advertising or otherwise to promote the sale, use or other dealings in\r
32 *this Software without prior written authorization from Xilinx.\r
33 *\r
34 \r
35\r
36 * Description: Driver configuration\r
37 *\r
38 *******************************************************************/\r
39 \r
40 #include "xparameters.h"\r
41 #include "xaxipmon.h"\r
42 \r
43 /*\r
44 * The configuration table for devices\r
45 */\r
46 \r
47 XAxiPmon_Config XAxiPmon_ConfigTable[XPAR_XAXIPMON_NUM_INSTANCES] =\r
48 {\r
49         {\r
50                 XPAR_PSU_APM_0_DEVICE_ID,\r
51                 XPAR_PSU_APM_0_BASEADDR,\r
52                 XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH,\r
53                 XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH,\r
54                 XPAR_PSU_APM_0_ENABLE_EVENT_COUNT,\r
55                 XPAR_PSU_APM_0_NUM_MONITOR_SLOTS,\r
56                 XPAR_PSU_APM_0_NUM_OF_COUNTERS,\r
57                 XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT,\r
58                 XPAR_PSU_APM_0_ENABLE_EVENT_LOG,\r
59                 XPAR_PSU_APM_0_FIFO_AXIS_DEPTH,\r
60                 XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH,\r
61                 XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH,\r
62                 XPAR_PSU_APM_0_METRIC_COUNT_SCALE,\r
63                 XPAR_PSU_APM_0_ENABLE_ADVANCED,\r
64                 XPAR_PSU_APM_0_ENABLE_PROFILE,\r
65                 XPAR_PSU_APM_0_ENABLE_TRACE,\r
66                 XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID\r
67         },\r
68         {\r
69                 XPAR_PSU_APM_1_DEVICE_ID,\r
70                 XPAR_PSU_APM_1_BASEADDR,\r
71                 XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH,\r
72                 XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH,\r
73                 XPAR_PSU_APM_1_ENABLE_EVENT_COUNT,\r
74                 XPAR_PSU_APM_1_NUM_MONITOR_SLOTS,\r
75                 XPAR_PSU_APM_1_NUM_OF_COUNTERS,\r
76                 XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT,\r
77                 XPAR_PSU_APM_1_ENABLE_EVENT_LOG,\r
78                 XPAR_PSU_APM_1_FIFO_AXIS_DEPTH,\r
79                 XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH,\r
80                 XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH,\r
81                 XPAR_PSU_APM_1_METRIC_COUNT_SCALE,\r
82                 XPAR_PSU_APM_1_ENABLE_ADVANCED,\r
83                 XPAR_PSU_APM_1_ENABLE_PROFILE,\r
84                 XPAR_PSU_APM_1_ENABLE_TRACE,\r
85                 XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID\r
86         },\r
87         {\r
88                 XPAR_PSU_APM_2_DEVICE_ID,\r
89                 XPAR_PSU_APM_2_BASEADDR,\r
90                 XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH,\r
91                 XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH,\r
92                 XPAR_PSU_APM_2_ENABLE_EVENT_COUNT,\r
93                 XPAR_PSU_APM_2_NUM_MONITOR_SLOTS,\r
94                 XPAR_PSU_APM_2_NUM_OF_COUNTERS,\r
95                 XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT,\r
96                 XPAR_PSU_APM_2_ENABLE_EVENT_LOG,\r
97                 XPAR_PSU_APM_2_FIFO_AXIS_DEPTH,\r
98                 XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH,\r
99                 XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH,\r
100                 XPAR_PSU_APM_2_METRIC_COUNT_SCALE,\r
101                 XPAR_PSU_APM_2_ENABLE_ADVANCED,\r
102                 XPAR_PSU_APM_2_ENABLE_PROFILE,\r
103                 XPAR_PSU_APM_2_ENABLE_TRACE,\r
104                 XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID\r
105         },\r
106         {\r
107                 XPAR_PSU_APM_5_DEVICE_ID,\r
108                 XPAR_PSU_APM_5_BASEADDR,\r
109                 XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH,\r
110                 XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH,\r
111                 XPAR_PSU_APM_5_ENABLE_EVENT_COUNT,\r
112                 XPAR_PSU_APM_5_NUM_MONITOR_SLOTS,\r
113                 XPAR_PSU_APM_5_NUM_OF_COUNTERS,\r
114                 XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT,\r
115                 XPAR_PSU_APM_5_ENABLE_EVENT_LOG,\r
116                 XPAR_PSU_APM_5_FIFO_AXIS_DEPTH,\r
117                 XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH,\r
118                 XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH,\r
119                 XPAR_PSU_APM_5_METRIC_COUNT_SCALE,\r
120                 XPAR_PSU_APM_5_ENABLE_ADVANCED,\r
121                 XPAR_PSU_APM_5_ENABLE_PROFILE,\r
122                 XPAR_PSU_APM_5_ENABLE_TRACE,\r
123                 XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID\r
124         }\r
125 };\r
126 \r
127 \r