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Update Zynq MPSoC hardware definition and BSP files to be those shipped with the...
[freertos] / FreeRTOS / Demo / CORTEX_A53_64-bit_UltraScale_MPSoC / RTOSDemo_A53_bsp / psu_cortexa53_0 / libsrc / ipipsu_v2_1 / src / xipipsu_g.c
1 \r
2 /*******************************************************************\r
3 *\r
4 * CAUTION: This file is automatically generated by HSI.\r
5 * Version: \r
6 * DO NOT EDIT.\r
7 *\r
8 * Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*\r
9 *Permission is hereby granted, free of charge, to any person obtaining a copy\r
10 *of this software and associated documentation files (the Software), to deal\r
11 *in the Software without restriction, including without limitation the rights\r
12 *to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
13 *copies of the Software, and to permit persons to whom the Software is\r
14 *furnished to do so, subject to the following conditions:\r
15 *\r
16 *The above copyright notice and this permission notice shall be included in\r
17 *all copies or substantial portions of the Software.\r
18\r
19 * Use of the Software is limited solely to applications:\r
20 *(a) running on a Xilinx device, or\r
21 *(b) that interact with a Xilinx device through a bus or interconnect.\r
22 *\r
23 *THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
24 *IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
25 *FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
26 *XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
27 *WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
28 *OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
29 *\r
30 *Except as contained in this notice, the name of the Xilinx shall not be used\r
31 *in advertising or otherwise to promote the sale, use or other dealings in\r
32 *this Software without prior written authorization from Xilinx.\r
33 *\r
34 \r
35\r
36 * Description: Driver configuration\r
37 *\r
38 *******************************************************************/\r
39 \r
40 #include "xparameters.h"\r
41 #include "xipipsu.h"\r
42 \r
43 /*\r
44 * The configuration table for devices\r
45 */\r
46 \r
47 XIpiPsu_Config XIpiPsu_ConfigTable[] =\r
48 {\r
49 \r
50         {\r
51                 XPAR_PSU_IPI_0_DEVICE_ID,\r
52                 XPAR_PSU_IPI_0_BASE_ADDRESS,\r
53                 XPAR_PSU_IPI_0_BIT_MASK,\r
54                 XPAR_PSU_IPI_0_BUFFER_INDEX,\r
55                 XPAR_PSU_IPI_0_INT_ID,\r
56                 XPAR_XIPIPSU_NUM_TARGETS,\r
57                 {\r
58 \r
59                         {\r
60                                 XPAR_PSU_IPI_0_BIT_MASK,\r
61                                 XPAR_PSU_IPI_0_BUFFER_INDEX\r
62                         },\r
63                         {\r
64                                 XPAR_PSU_IPI_1_BIT_MASK,\r
65                                 XPAR_PSU_IPI_1_BUFFER_INDEX\r
66                         },\r
67                         {\r
68                                 XPAR_PSU_IPI_2_BIT_MASK,\r
69                                 XPAR_PSU_IPI_2_BUFFER_INDEX\r
70                         },\r
71                         {\r
72                                 XPAR_PSU_IPI_3_BIT_MASK,\r
73                                 XPAR_PSU_IPI_3_BUFFER_INDEX\r
74                         },\r
75                         {\r
76                                 XPAR_PSU_IPI_4_BIT_MASK,\r
77                                 XPAR_PSU_IPI_4_BUFFER_INDEX\r
78                         },\r
79                         {\r
80                                 XPAR_PSU_IPI_5_BIT_MASK,\r
81                                 XPAR_PSU_IPI_5_BUFFER_INDEX\r
82                         },\r
83                         {\r
84                                 XPAR_PSU_IPI_6_BIT_MASK,\r
85                                 XPAR_PSU_IPI_6_BUFFER_INDEX\r
86                         },\r
87                         {\r
88                                 XPAR_PSU_IPI_7_BIT_MASK,\r
89                                 XPAR_PSU_IPI_7_BUFFER_INDEX\r
90                         },\r
91                         {\r
92                                 XPAR_PSU_IPI_8_BIT_MASK,\r
93                                 XPAR_PSU_IPI_8_BUFFER_INDEX\r
94                         },\r
95                         {\r
96                                 XPAR_PSU_IPI_9_BIT_MASK,\r
97                                 XPAR_PSU_IPI_9_BUFFER_INDEX\r
98                         },\r
99                         {\r
100                                 XPAR_PSU_IPI_10_BIT_MASK,\r
101                                 XPAR_PSU_IPI_10_BUFFER_INDEX\r
102                         }\r
103                 }\r
104         }\r
105 };\r