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[freertos] / FreeRTOS / Demo / CORTEX_A53_64-bit_UltraScale_MPSoC / RTOSDemo_A53_bsp / psu_cortexa53_0 / libsrc / standalone_v5_0 / src / xlpd_xppu_sink.h
1 /* ### HEADER ### */
2
3 #ifndef __XLPD_XPPU_SINK_H__
4 #define __XLPD_XPPU_SINK_H__
5
6
7 #ifdef __cplusplus
8 extern "C" {
9 #endif
10
11 /**
12  * XlpdXppuSink Base Address
13  */
14 #define XLPD_XPPU_SINK_BASEADDR      0xFF9C0000UL
15
16 /**
17  * Register: XlpdXppuSinkErrSts
18  */
19 #define XLPD_XPPU_SINK_ERR_STS    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF00UL )
20 #define XLPD_XPPU_SINK_ERR_STS_RSTVAL   0x00000000UL
21
22 #define XLPD_XPPU_SINK_ERR_STS_RDWR_SHIFT   31UL
23 #define XLPD_XPPU_SINK_ERR_STS_RDWR_WIDTH   1UL
24 #define XLPD_XPPU_SINK_ERR_STS_RDWR_MASK    0x80000000UL
25 #define XLPD_XPPU_SINK_ERR_STS_RDWR_DEFVAL  0x0UL
26
27 #define XLPD_XPPU_SINK_ERR_STS_ADDR_SHIFT   0UL
28 #define XLPD_XPPU_SINK_ERR_STS_ADDR_WIDTH   12UL
29 #define XLPD_XPPU_SINK_ERR_STS_ADDR_MASK    0x00000fffUL
30 #define XLPD_XPPU_SINK_ERR_STS_ADDR_DEFVAL  0x0UL
31
32 /**
33  * Register: XlpdXppuSinkIsr
34  */
35 #define XLPD_XPPU_SINK_ISR    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF10UL )
36 #define XLPD_XPPU_SINK_ISR_RSTVAL   0x00000000UL
37
38 #define XLPD_XPPU_SINK_ISRADDRDECDERR_SHIFT   0UL
39 #define XLPD_XPPU_SINK_ISRADDRDECDERR_WIDTH   1UL
40 #define XLPD_XPPU_SINK_ISRADDRDECDERR_MASK    0x00000001UL
41 #define XLPD_XPPU_SINK_ISRADDRDECDERR_DEFVAL  0x0UL
42
43 /**
44  * Register: XlpdXppuSinkImr
45  */
46 #define XLPD_XPPU_SINK_IMR    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF14UL )
47 #define XLPD_XPPU_SINK_IMR_RSTVAL   0x00000001UL
48
49 #define XLPD_XPPU_SINK_IMRADDRDECDERR_SHIFT   0UL
50 #define XLPD_XPPU_SINK_IMRADDRDECDERR_WIDTH   1UL
51 #define XLPD_XPPU_SINK_IMRADDRDECDERR_MASK    0x00000001UL
52 #define XLPD_XPPU_SINK_IMRADDRDECDERR_DEFVAL  0x1UL
53
54 /**
55  * Register: XlpdXppuSinkIer
56  */
57 #define XLPD_XPPU_SINK_IER    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF18UL )
58 #define XLPD_XPPU_SINK_IER_RSTVAL   0x00000000UL
59
60 #define XLPD_XPPU_SINK_IERADDRDECDERR_SHIFT   0UL
61 #define XLPD_XPPU_SINK_IERADDRDECDERR_WIDTH   1UL
62 #define XLPD_XPPU_SINK_IERADDRDECDERR_MASK    0x00000001UL
63 #define XLPD_XPPU_SINK_IERADDRDECDERR_DEFVAL  0x0UL
64
65 /**
66  * Register: XlpdXppuSinkIdr
67  */
68 #define XLPD_XPPU_SINK_IDR    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF1CUL )
69 #define XLPD_XPPU_SINK_IDR_RSTVAL   0x00000000UL
70
71 #define XLPD_XPPU_SINK_IDRADDRDECDERR_SHIFT   0UL
72 #define XLPD_XPPU_SINK_IDRADDRDECDERR_WIDTH   1UL
73 #define XLPD_XPPU_SINK_IDRADDRDECDERR_MASK    0x00000001UL
74 #define XLPD_XPPU_SINK_IDRADDRDECDERR_DEFVAL  0x0UL
75
76
77 #ifdef __cplusplus
78 }
79 #endif
80
81 #endif /* __XLPD_XPPU_SINK_H__ */