1 /******************************************************************************
3 * Copyright (C) 2016 Xilinx, Inc. All rights reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * Use of the Software is limited solely to applications:
16 * (a) running on a Xilinx device, or
17 * (b) that interact with a Xilinx device through a bus or interconnect.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27 * Except as contained in this notice, the name of the Xilinx shall not be used
28 * in advertising or otherwise to promote the sale, use or other dealings in
29 * this Software without prior written authorization from Xilinx.
31 ******************************************************************************/
32 /****************************************************************************/
36 * @addtogroup usbpsu_v1_0
41 * MODIFICATION HISTORY:
43 * Ver Who Date Changes
44 * ----- ----- -------- -----------------------------------------------------
45 * 1.0 sg 06/16/16 First release
46 * 1.1 sg 10/24/16 Added new function XUsbPsu_IsSuperSpeed
50 *****************************************************************************/
52 /***************************** Include Files ********************************/
56 /************************** Constant Definitions *****************************/
59 /**************************** Type Definitions *******************************/
62 /***************** Macros (Inline Functions) Definitions *********************/
65 /************************** Function Prototypes ******************************/
68 /************************** Variable Definitions *****************************/
70 /*****************************************************************************/
72 * Waits until a bit in a register is cleared or timeout occurs
74 * @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
75 * @param Offset is register offset.
76 * @param BitMask is bit mask of required bit to be checked.
77 * @param Timeout is the time to wait specified in micro seconds.
80 * - XST_SUCCESS when bit is cleared.
81 * - XST_FAILURE when timed out.
83 ******************************************************************************/
84 s32 XUsbPsu_Wait_Clear_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
85 u32 BitMask, u32 Timeout)
88 u32 LocalTimeout = Timeout;
91 RegVal = XUsbPsu_ReadReg(InstancePtr, Offset);
92 if ((RegVal & BitMask) == 0U) {
96 if (LocalTimeout == 0U) {
105 /*****************************************************************************/
107 * Waits until a bit in a register is set or timeout occurs
109 * @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
110 * @param Offset is register offset.
111 * @param BitMask is bit mask of required bit to be checked.
112 * @param Timeout is the time to wait specified in micro seconds.
115 * - XST_SUCCESS when bit is set.
116 * - XST_FAILURE when timed out.
118 ******************************************************************************/
119 s32 XUsbPsu_Wait_Set_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
120 u32 BitMask, u32 Timeout)
123 u32 LocalTimeout = Timeout;
126 RegVal = XUsbPsu_ReadReg(InstancePtr, Offset);
127 if ((RegVal & BitMask) != 0U) {
131 if (LocalTimeout == 0U) {
140 /*****************************************************************************/
142 * Sets mode of Core to USB Device/Host/OTG.
145 * @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
146 * @param Mode is mode to set
147 * - XUSBPSU_GCTL_PRTCAP_OTG
148 * - XUSBPSU_GCTL_PRTCAP_HOST
149 * - XUSBPSU_GCTL_PRTCAP_DEVICE
153 ******************************************************************************/
154 void XUsbPsu_SetMode(struct XUsbPsu *InstancePtr, u32 Mode)
158 Xil_AssertVoid(InstancePtr != NULL);
159 Xil_AssertVoid((Mode <= XUSBPSU_GCTL_PRTCAP_OTG) &&
160 (Mode >= XUSBPSU_GCTL_PRTCAP_HOST));
162 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
163 RegVal &= ~(XUSBPSU_GCTL_PRTCAPDIR(XUSBPSU_GCTL_PRTCAP_OTG));
164 RegVal |= XUSBPSU_GCTL_PRTCAPDIR(Mode);
165 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
168 /*****************************************************************************/
170 * Issues core PHY reset.
172 * @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
176 ******************************************************************************/
177 void XUsbPsu_PhyReset(struct XUsbPsu *InstancePtr)
181 Xil_AssertVoid(InstancePtr != NULL);
183 /* Before Resetting PHY, put Core in Reset */
184 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
185 RegVal |= XUSBPSU_GCTL_CORESOFTRESET;
186 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
188 /* Assert USB3 PHY reset */
189 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0));
190 RegVal |= XUSBPSU_GUSB3PIPECTL_PHYSOFTRST;
191 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0), RegVal);
193 /* Assert USB2 PHY reset */
194 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0));
195 RegVal |= XUSBPSU_GUSB2PHYCFG_PHYSOFTRST;
196 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0), RegVal);
198 XUsbSleep(XUSBPSU_PHY_TIMEOUT);
200 /* Clear USB3 PHY reset */
201 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0));
202 RegVal &= ~XUSBPSU_GUSB3PIPECTL_PHYSOFTRST;
203 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0), RegVal);
205 /* Clear USB2 PHY reset */
206 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0));
207 RegVal &= ~XUSBPSU_GUSB2PHYCFG_PHYSOFTRST;
208 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0), RegVal);
210 XUsbSleep(XUSBPSU_PHY_TIMEOUT);
212 /* Take Core out of reset state after PHYS are stable*/
213 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
214 RegVal &= ~XUSBPSU_GCTL_CORESOFTRESET;
215 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
218 /*****************************************************************************/
220 * Sets up Event buffers so that events are written by Core.
222 * @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
226 ******************************************************************************/
227 void XUsbPsu_EventBuffersSetup(struct XUsbPsu *InstancePtr)
229 struct XUsbPsu_EvtBuffer *Evt;
231 Xil_AssertVoid(InstancePtr != NULL);
233 Evt = &InstancePtr->Evt;
234 Evt->BuffAddr = (void *)InstancePtr->EventBuffer;
236 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRLO(0),
237 (UINTPTR)InstancePtr->EventBuffer);
238 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRHI(0),
239 ((UINTPTR)(InstancePtr->EventBuffer) >> 16U) >> 16U);
240 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0),
241 XUSBPSU_GEVNTSIZ_SIZE(sizeof(InstancePtr->EventBuffer)));
242 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), 0);
245 /*****************************************************************************/
247 * Resets Event buffer Registers to zero so that events are not written by Core.
249 * @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
253 ******************************************************************************/
254 void XUsbPsu_EventBuffersReset(struct XUsbPsu *InstancePtr)
257 Xil_AssertVoid(InstancePtr != NULL);
259 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRLO(0U), 0U);
260 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRHI(0U), 0U);
261 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0U),
262 (u32)XUSBPSU_GEVNTSIZ_INTMASK | XUSBPSU_GEVNTSIZ_SIZE(0U));
263 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0U), 0U);
266 /*****************************************************************************/
268 * Reads data from Hardware Params Registers of Core.
270 * @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
271 * @param RegIndex is Register number to read
272 * - XUSBPSU_GHWPARAMS0
273 * - XUSBPSU_GHWPARAMS1
274 * - XUSBPSU_GHWPARAMS2
275 * - XUSBPSU_GHWPARAMS3
276 * - XUSBPSU_GHWPARAMS4
277 * - XUSBPSU_GHWPARAMS5
278 * - XUSBPSU_GHWPARAMS6
279 * - XUSBPSU_GHWPARAMS7
281 * @return One of the GHWPARAMS RegValister contents.
283 ******************************************************************************/
284 u32 XUsbPsu_ReadHwParams(struct XUsbPsu *InstancePtr, u8 RegIndex)
288 Xil_AssertNonvoid(InstancePtr != NULL);
289 Xil_AssertNonvoid(RegIndex <= (u8)XUSBPSU_GHWPARAMS7);
291 RegVal = XUsbPsu_ReadReg(InstancePtr, ((u32)XUSBPSU_GHWPARAMS0_OFFSET +
292 ((u32)RegIndex * (u32)4)));
296 /*****************************************************************************/
300 * @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
303 * - XST_SUCCESS if initialization was successful
304 * - XST_FAILURE if initialization was not successful
306 ******************************************************************************/
307 s32 XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr)
312 /* issue device SoftReset too */
313 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, XUSBPSU_DCTL_CSFTRST);
315 if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DCTL,
316 XUSBPSU_DCTL_CSFTRST, 500U) == XST_FAILURE) {
317 /* timed out return failure */
321 XUsbPsu_PhyReset(InstancePtr);
323 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
324 RegVal &= ~XUSBPSU_GCTL_SCALEDOWN_MASK;
325 RegVal &= ~XUSBPSU_GCTL_DISSCRAMBLE;
326 RegVal |= XUSBPSU_GCTL_U2EXIT_LFPS;
328 Hwparams1 = XUsbPsu_ReadHwParams(InstancePtr, 1U);
330 switch (XUSBPSU_GHWPARAMS1_EN_PWROPT(Hwparams1)) {
331 case XUSBPSU_GHWPARAMS1_EN_PWROPT_CLK:
332 RegVal &= ~XUSBPSU_GCTL_DSBLCLKGTNG;
335 case XUSBPSU_GHWPARAMS1_EN_PWROPT_HIB:
336 /* enable hibernation here */
340 /* Made for Misra-C Compliance. */
344 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
349 /*****************************************************************************/
351 * Enables an interrupt in Event Enable RegValister.
353 * @param InstancePtr is a pointer to the XUsbPsu instance to be worked on
354 * @param Mask is the OR of any Interrupt Enable Masks:
355 * - XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN
356 * - XUSBPSU_DEVTEN_EVNTOVERFLOWEN
357 * - XUSBPSU_DEVTEN_CMDCMPLTEN
358 * - XUSBPSU_DEVTEN_ERRTICERREN
359 * - XUSBPSU_DEVTEN_SOFEN
360 * - XUSBPSU_DEVTEN_EOPFEN
361 * - XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN
362 * - XUSBPSU_DEVTEN_WKUPEVTEN
363 * - XUSBPSU_DEVTEN_ULSTCNGEN
364 * - XUSBPSU_DEVTEN_CONNECTDONEEN
365 * - XUSBPSU_DEVTEN_USBRSTEN
366 * - XUSBPSU_DEVTEN_DISCONNEVTEN
370 ******************************************************************************/
371 void XUsbPsu_EnableIntr(struct XUsbPsu *InstancePtr, u32 Mask)
375 Xil_AssertVoid(InstancePtr != NULL);
377 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEVTEN);
380 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEVTEN, RegVal);
383 /*****************************************************************************/
385 * Disables an interrupt in Event Enable RegValister.
387 * @param InstancePtr is a pointer to the XUsbPsu instance to be worked on.
388 * @param Mask is the OR of Interrupt Enable Masks
389 * - XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN
390 * - XUSBPSU_DEVTEN_EVNTOVERFLOWEN
391 * - XUSBPSU_DEVTEN_CMDCMPLTEN
392 * - XUSBPSU_DEVTEN_ERRTICERREN
393 * - XUSBPSU_DEVTEN_SOFEN
394 * - XUSBPSU_DEVTEN_EOPFEN
395 * - XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN
396 * - XUSBPSU_DEVTEN_WKUPEVTEN
397 * - XUSBPSU_DEVTEN_ULSTCNGEN
398 * - XUSBPSU_DEVTEN_CONNECTDONEEN
399 * - XUSBPSU_DEVTEN_USBRSTEN
400 * - XUSBPSU_DEVTEN_DISCONNEVTEN
404 ******************************************************************************/
405 void XUsbPsu_DisableIntr(struct XUsbPsu *InstancePtr, u32 Mask)
409 Xil_AssertVoid(InstancePtr != NULL);
411 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEVTEN);
413 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEVTEN, RegVal);
416 /****************************************************************************/
419 * This function does the following:
420 * - initializes a specific XUsbPsu instance.
421 * - sets up Event Buffer for Core to write events.
422 * - Core Reset and PHY Reset.
423 * - Sets core in Device Mode.
424 * - Sets default speed as HIGH_SPEED.
425 * - Sets Device Address to 0.
426 * - Enables interrupts.
428 * @param InstancePtr is a pointer to the XUsbPsu instance.
429 * @param ConfigPtr points to the XUsbPsu device configuration structure.
430 * @param BaseAddress is the device base address in the virtual memory
431 * address space. If the address translation is not used then the
432 * physical address is passed.
433 * Unexpected errors may occur if the address mapping is changed
434 * after this function is invoked.
436 * @return XST_SUCCESS else XST_FAILURE
440 *****************************************************************************/
441 s32 XUsbPsu_CfgInitialize(struct XUsbPsu *InstancePtr,
442 XUsbPsu_Config *ConfigPtr, u32 BaseAddress)
448 Xil_AssertNonvoid(InstancePtr != NULL);
449 Xil_AssertNonvoid(ConfigPtr != NULL);
450 Xil_AssertNonvoid(BaseAddress != 0U)
452 InstancePtr->ConfigPtr = ConfigPtr;
454 Status = XUsbPsu_CoreInit(InstancePtr);
455 if (Status != XST_SUCCESS) {
457 xil_printf("Core initialization failed\r\n");
462 RegVal = XUsbPsu_ReadHwParams(InstancePtr, 3U);
463 InstancePtr->NumInEps = (u8)XUSBPSU_NUM_IN_EPS(RegVal);
464 InstancePtr->NumOutEps = (u8)(XUSBPSU_NUM_EPS(RegVal) -
465 InstancePtr->NumInEps);
467 /* Map USB and Physical Endpoints */
468 XUsbPsu_InitializeEps(InstancePtr);
470 XUsbPsu_EventBuffersSetup(InstancePtr);
472 XUsbPsu_SetMode(InstancePtr, XUSBPSU_GCTL_PRTCAP_DEVICE);
475 * Setting to max speed to support SS and HS
477 XUsbPsu_SetSpeed(InstancePtr, XUSBPSU_DCFG_SUPERSPEED);
479 (void)XUsbPsu_SetDeviceAddress(InstancePtr, 0U);
484 /****************************************************************************/
487 * Starts the controller so that Host can detect this device.
489 * @param InstancePtr is a pointer to the XUsbPsu instance.
491 * @return XST_SUCCESS else XST_FAILURE
495 *****************************************************************************/
496 s32 XUsbPsu_Start(struct XUsbPsu *InstancePtr)
500 Xil_AssertNonvoid(InstancePtr != NULL);
502 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
504 RegVal |= XUSBPSU_DCTL_RUN_STOP;
506 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
508 if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS,
509 XUSBPSU_DSTS_DEVCTRLHLT, 500U) == XST_FAILURE) {
516 /****************************************************************************/
519 * Stops the controller so that Device disconnects from Host.
521 * @param InstancePtr is a pointer to the XUsbPsu instance.
523 * @return XST_SUCCESS else XST_FAILURE
527 *****************************************************************************/
528 s32 XUsbPsu_Stop(struct XUsbPsu *InstancePtr)
532 Xil_AssertNonvoid(InstancePtr != NULL);
534 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
535 RegVal &= ~XUSBPSU_DCTL_RUN_STOP;
537 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
539 if (XUsbPsu_Wait_Set_Timeout(InstancePtr, XUSBPSU_DSTS,
540 XUSBPSU_DSTS_DEVCTRLHLT, 500U) == XST_FAILURE) {
547 /****************************************************************************/
549 * Enables USB2 Test Modes
551 * @param InstancePtr is a pointer to the XUsbPsu instance.
552 * @param Mode is Test mode to set.
554 * @return XST_SUCCESS else XST_FAILURE
558 ****************************************************************************/
559 s32 XUsbPsu_SetTestMode(struct XUsbPsu *InstancePtr, u32 Mode)
562 s32 Status = XST_SUCCESS;
564 Xil_AssertNonvoid(InstancePtr != NULL);
565 Xil_AssertNonvoid((Mode >= XUSBPSU_TEST_J)
566 && (Mode <= XUSBPSU_TEST_FORCE_ENABLE));
568 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
569 RegVal &= ~XUSBPSU_DCTL_TSTCTRL_MASK;
574 case XUSBPSU_TEST_SE0_NAK:
575 case XUSBPSU_TEST_PACKET:
576 case XUSBPSU_TEST_FORCE_ENABLE:
577 RegVal |= (u32)Mode << 1;
581 Status = (s32)XST_FAILURE;
585 if (Status != (s32)XST_FAILURE) {
586 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
587 Status = XST_SUCCESS;
593 /****************************************************************************/
595 * Gets current State of USB Link
597 * @param InstancePtr is a pointer to the XUsbPsu instance.
603 ****************************************************************************/
604 XusbPsuLinkState XUsbPsu_GetLinkState(struct XUsbPsu *InstancePtr)
608 Xil_AssertNonvoid(InstancePtr != NULL);
610 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DSTS);
612 return XUSBPSU_DSTS_USBLNKST(RegVal);
615 /****************************************************************************/
617 * Sets USB Link to a particular State
619 * @param InstancePtr is a pointer to the XUsbPsu instance.
620 * @param State is State of Link to set.
622 * @return XST_SUCCESS else XST_FAILURE
626 ****************************************************************************/
627 s32 XUsbPsu_SetLinkState(struct XUsbPsu *InstancePtr,
628 XusbPsuLinkStateChange State)
632 Xil_AssertNonvoid(InstancePtr != NULL);
634 /* Wait until device controller is ready. */
635 if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS,
636 XUSBPSU_DSTS_DCNRD, 500U) == XST_FAILURE) {
640 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
641 RegVal &= ~XUSBPSU_DCTL_ULSTCHNGREQ_MASK;
643 RegVal |= XUSBPSU_DCTL_ULSTCHNGREQ(State);
644 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
649 /****************************************************************************/
651 * Sets speed of the Core for connecting to Host
653 * @param InstancePtr is a pointer to the XUsbPsu instance.
654 * @param Speed is required speed
655 * - XUSBPSU_DCFG_HIGHSPEED
656 * - XUSBPSU_DCFG_FULLSPEED2
657 * - XUSBPSU_DCFG_LOWSPEED
658 * - XUSBPSU_DCFG_FULLSPEED1
664 *****************************************************************************/
665 void XUsbPsu_SetSpeed(struct XUsbPsu *InstancePtr, u32 Speed)
669 Xil_AssertVoid(InstancePtr != NULL);
670 Xil_AssertVoid(Speed <= (u32)XUSBPSU_DCFG_SUPERSPEED);
672 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
673 RegVal &= ~(XUSBPSU_DCFG_SPEED_MASK);
675 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
678 /****************************************************************************/
680 * Sets Device Address of the Core
682 * @param InstancePtr is a pointer to the XUsbPsu instance.
683 * @param Addr is address to set.
685 * @return XST_SUCCESS else XST_FAILURE
689 *****************************************************************************/
690 s32 XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr)
694 Xil_AssertNonvoid(InstancePtr != NULL);
695 Xil_AssertNonvoid(Addr <= 127U);
697 if (InstancePtr->State == XUSBPSU_STATE_CONFIGURED) {
701 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
702 RegVal &= ~(XUSBPSU_DCFG_DEVADDR_MASK);
703 RegVal |= XUSBPSU_DCFG_DEVADDR(Addr);
704 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
707 InstancePtr->State = XUSBPSU_STATE_ADDRESS;
710 InstancePtr->State = XUSBPSU_STATE_DEFAULT;
716 /****************************************************************************/
718 * Sets speed of the Core for connecting to Host
720 * @param InstancePtr is a pointer to the XUsbPsu instance.
722 * @return XST_SUCCESS else XST_FAILURE
726 *****************************************************************************/
727 s32 XUsbPsu_IsSuperSpeed(struct XUsbPsu *InstancePtr)
729 if (InstancePtr->Speed != XUSBPSU_SPEED_SUPER) {
736 /****************************************************************************/
738 * Set U1 sleep timeout
740 * @param InstancePtr is a pointer to the XUsbPsu instance.
741 * @param Sleep is time in microseconds
743 * @return XST_SUCCESS else XST_FAILURE
747 *****************************************************************************/
748 s32 XUsbPsu_SetU1SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep)
752 Xil_AssertNonvoid(InstancePtr != NULL);
754 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_PORTMSC_30);
755 RegVal &= ~XUSBPSU_PORTMSC_30_U1_TIMEOUT_MASK;
756 RegVal |= (Sleep << XUSBPSU_PORTMSC_30_U1_TIMEOUT_SHIFT);
757 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_PORTMSC_30, RegVal);
762 /****************************************************************************/
764 * Set U2 sleep timeout
766 * @param InstancePtr is a pointer to the XUsbPsu instance.
767 * @param Sleep is time in microseconds
769 * @return XST_SUCCESS else XST_FAILURE
773 *****************************************************************************/
774 s32 XUsbPsu_SetU2SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep)
778 Xil_AssertNonvoid(InstancePtr != NULL);
780 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_PORTMSC_30);
781 RegVal &= ~XUSBPSU_PORTMSC_30_U2_TIMEOUT_MASK;
782 RegVal |= (Sleep << XUSBPSU_PORTMSC_30_U2_TIMEOUT_SHIFT);
783 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_PORTMSC_30, RegVal);
787 /****************************************************************************/
789 * Enable Accept U1 and U2 sleep enable
791 * @param InstancePtr is a pointer to the XUsbPsu instance.
793 * @return XST_SUCCESS else XST_FAILURE
797 *****************************************************************************/
798 s32 XUsbPsu_AcceptU1U2Sleep(struct XUsbPsu *InstancePtr)
802 Xil_AssertNonvoid(InstancePtr != NULL);
804 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
805 RegVal |= XUSBPSU_DCTL_ACCEPTU2ENA | XUSBPSU_DCTL_ACCEPTU1ENA;
806 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
811 /****************************************************************************/
813 * Enable U1 enable sleep
815 * @param InstancePtr is a pointer to the XUsbPsu instance.
817 * @return XST_SUCCESS else XST_FAILURE
821 *****************************************************************************/
822 s32 XUsbPsu_U1SleepEnable(struct XUsbPsu *InstancePtr)
826 Xil_AssertNonvoid(InstancePtr != NULL);
828 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
829 RegVal |= XUSBPSU_DCTL_INITU1ENA;
830 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
835 /****************************************************************************/
837 * Enable U2 enable sleep
839 * @param InstancePtr is a pointer to the XUsbPsu instance.
841 * @return XST_SUCCESS else XST_FAILURE
845 *****************************************************************************/
846 s32 XUsbPsu_U2SleepEnable(struct XUsbPsu *InstancePtr)
850 Xil_AssertNonvoid(InstancePtr != NULL);
852 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
853 RegVal |= XUSBPSU_DCTL_INITU2ENA;
854 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
859 /****************************************************************************/
861 * Enable U1 disable sleep
863 * @param InstancePtr is a pointer to the XUsbPsu instance.
865 * @return XST_SUCCESS else XST_FAILURE
869 *****************************************************************************/
870 s32 XUsbPsu_U1SleepDisable(struct XUsbPsu *InstancePtr)
874 Xil_AssertNonvoid(InstancePtr != NULL);
876 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
877 RegVal &= ~XUSBPSU_DCTL_INITU1ENA;
878 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
883 /****************************************************************************/
885 * Enable U2 disable sleep
887 * @param InstancePtr is a pointer to the XUsbPsu instance.
889 * @return XST_SUCCESS else XST_FAILURE
893 *****************************************************************************/
894 s32 XUsbPsu_U2SleepDisable(struct XUsbPsu *InstancePtr)
898 Xil_AssertNonvoid(InstancePtr != NULL);
900 RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
901 RegVal &= ~XUSBPSU_DCTL_INITU2ENA;
902 XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);