1 /******************************************************************************
3 * Copyright (C) 2015 Xilinx, Inc. All rights reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * Use of the Software is limited solely to applications:
16 * (a) running on a Xilinx device, or
17 * (b) that interact with a Xilinx device through a bus or interconnect.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
22 * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27 * Except as contained in this notice, the name of the Xilinx shall not be used
28 * in advertising or otherwise to promote the sale, use or other dealings in
29 * this Software without prior written authorization from Xilinx.
31 ******************************************************************************/
32 /****************************************************************************/
37 * This file is automatically generated
39 *****************************************************************************/
42 #undef CRL_APB_RPLL_CFG_OFFSET
43 #define CRL_APB_RPLL_CFG_OFFSET 0XFF5E0034
44 #undef CRL_APB_RPLL_CTRL_OFFSET
45 #define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030
46 #undef CRL_APB_RPLL_CTRL_OFFSET
47 #define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030
48 #undef CRL_APB_RPLL_CTRL_OFFSET
49 #define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030
50 #undef CRL_APB_RPLL_CTRL_OFFSET
51 #define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030
52 #undef CRL_APB_RPLL_CTRL_OFFSET
53 #define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030
54 #undef CRL_APB_RPLL_TO_FPD_CTRL_OFFSET
55 #define CRL_APB_RPLL_TO_FPD_CTRL_OFFSET 0XFF5E0048
56 #undef CRL_APB_IOPLL_CFG_OFFSET
57 #define CRL_APB_IOPLL_CFG_OFFSET 0XFF5E0024
58 #undef CRL_APB_IOPLL_CTRL_OFFSET
59 #define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020
60 #undef CRL_APB_IOPLL_CTRL_OFFSET
61 #define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020
62 #undef CRL_APB_IOPLL_CTRL_OFFSET
63 #define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020
64 #undef CRL_APB_IOPLL_CTRL_OFFSET
65 #define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020
66 #undef CRL_APB_IOPLL_CTRL_OFFSET
67 #define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020
68 #undef CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET
69 #define CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET 0XFF5E0044
70 #undef CRF_APB_APLL_CFG_OFFSET
71 #define CRF_APB_APLL_CFG_OFFSET 0XFD1A0024
72 #undef CRF_APB_APLL_CTRL_OFFSET
73 #define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020
74 #undef CRF_APB_APLL_CTRL_OFFSET
75 #define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020
76 #undef CRF_APB_APLL_CTRL_OFFSET
77 #define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020
78 #undef CRF_APB_APLL_CTRL_OFFSET
79 #define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020
80 #undef CRF_APB_APLL_CTRL_OFFSET
81 #define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020
82 #undef CRF_APB_APLL_TO_LPD_CTRL_OFFSET
83 #define CRF_APB_APLL_TO_LPD_CTRL_OFFSET 0XFD1A0048
84 #undef CRF_APB_DPLL_CFG_OFFSET
85 #define CRF_APB_DPLL_CFG_OFFSET 0XFD1A0030
86 #undef CRF_APB_DPLL_CTRL_OFFSET
87 #define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C
88 #undef CRF_APB_DPLL_CTRL_OFFSET
89 #define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C
90 #undef CRF_APB_DPLL_CTRL_OFFSET
91 #define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C
92 #undef CRF_APB_DPLL_CTRL_OFFSET
93 #define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C
94 #undef CRF_APB_DPLL_CTRL_OFFSET
95 #define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C
96 #undef CRF_APB_DPLL_TO_LPD_CTRL_OFFSET
97 #define CRF_APB_DPLL_TO_LPD_CTRL_OFFSET 0XFD1A004C
98 #undef CRF_APB_VPLL_CFG_OFFSET
99 #define CRF_APB_VPLL_CFG_OFFSET 0XFD1A003C
100 #undef CRF_APB_VPLL_CTRL_OFFSET
101 #define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038
102 #undef CRF_APB_VPLL_CTRL_OFFSET
103 #define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038
104 #undef CRF_APB_VPLL_CTRL_OFFSET
105 #define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038
106 #undef CRF_APB_VPLL_CTRL_OFFSET
107 #define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038
108 #undef CRF_APB_VPLL_CTRL_OFFSET
109 #define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038
110 #undef CRF_APB_VPLL_TO_LPD_CTRL_OFFSET
111 #define CRF_APB_VPLL_TO_LPD_CTRL_OFFSET 0XFD1A0050
114 * PLL loop filter resistor control
116 #undef CRL_APB_RPLL_CFG_RES_DEFVAL
117 #undef CRL_APB_RPLL_CFG_RES_SHIFT
118 #undef CRL_APB_RPLL_CFG_RES_MASK
119 #define CRL_APB_RPLL_CFG_RES_DEFVAL 0x00000000
120 #define CRL_APB_RPLL_CFG_RES_SHIFT 0
121 #define CRL_APB_RPLL_CFG_RES_MASK 0x0000000FU
124 * PLL charge pump control
126 #undef CRL_APB_RPLL_CFG_CP_DEFVAL
127 #undef CRL_APB_RPLL_CFG_CP_SHIFT
128 #undef CRL_APB_RPLL_CFG_CP_MASK
129 #define CRL_APB_RPLL_CFG_CP_DEFVAL 0x00000000
130 #define CRL_APB_RPLL_CFG_CP_SHIFT 5
131 #define CRL_APB_RPLL_CFG_CP_MASK 0x000001E0U
134 * PLL loop filter high frequency capacitor control
136 #undef CRL_APB_RPLL_CFG_LFHF_DEFVAL
137 #undef CRL_APB_RPLL_CFG_LFHF_SHIFT
138 #undef CRL_APB_RPLL_CFG_LFHF_MASK
139 #define CRL_APB_RPLL_CFG_LFHF_DEFVAL 0x00000000
140 #define CRL_APB_RPLL_CFG_LFHF_SHIFT 10
141 #define CRL_APB_RPLL_CFG_LFHF_MASK 0x00000C00U
144 * Lock circuit counter setting
146 #undef CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL
147 #undef CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT
148 #undef CRL_APB_RPLL_CFG_LOCK_CNT_MASK
149 #define CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL 0x00000000
150 #define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 13
151 #define CRL_APB_RPLL_CFG_LOCK_CNT_MASK 0x007FE000U
154 * Lock circuit configuration settings for lock windowsize
156 #undef CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL
157 #undef CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT
158 #undef CRL_APB_RPLL_CFG_LOCK_DLY_MASK
159 #define CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL 0x00000000
160 #define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 25
161 #define CRL_APB_RPLL_CFG_LOCK_DLY_MASK 0xFE000000U
164 * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
165 * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
166 * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
168 #undef CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL
169 #undef CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT
170 #undef CRL_APB_RPLL_CTRL_PRE_SRC_MASK
171 #define CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09
172 #define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 20
173 #define CRL_APB_RPLL_CTRL_PRE_SRC_MASK 0x00700000U
176 * The integer portion of the feedback divider to the PLL
178 #undef CRL_APB_RPLL_CTRL_FBDIV_DEFVAL
179 #undef CRL_APB_RPLL_CTRL_FBDIV_SHIFT
180 #undef CRL_APB_RPLL_CTRL_FBDIV_MASK
181 #define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 0x00012C09
182 #define CRL_APB_RPLL_CTRL_FBDIV_SHIFT 8
183 #define CRL_APB_RPLL_CTRL_FBDIV_MASK 0x00007F00U
186 * This turns on the divide by 2 that is inside of the PLL. This does not c
187 * hange the VCO frequency, just the output frequency
189 #undef CRL_APB_RPLL_CTRL_DIV2_DEFVAL
190 #undef CRL_APB_RPLL_CTRL_DIV2_SHIFT
191 #undef CRL_APB_RPLL_CTRL_DIV2_MASK
192 #define CRL_APB_RPLL_CTRL_DIV2_DEFVAL 0x00012C09
193 #define CRL_APB_RPLL_CTRL_DIV2_SHIFT 16
194 #define CRL_APB_RPLL_CTRL_DIV2_MASK 0x00010000U
197 * Bypasses the PLL clock. The usable clock will be determined from the POS
198 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
199 * clock and 4 cycles of the new clock. This is not usually an issue, but d
200 * esigners must be aware.)
202 #undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL
203 #undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT
204 #undef CRL_APB_RPLL_CTRL_BYPASS_MASK
205 #define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09
206 #define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3
207 #define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U
210 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
213 #undef CRL_APB_RPLL_CTRL_RESET_DEFVAL
214 #undef CRL_APB_RPLL_CTRL_RESET_SHIFT
215 #undef CRL_APB_RPLL_CTRL_RESET_MASK
216 #define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09
217 #define CRL_APB_RPLL_CTRL_RESET_SHIFT 0
218 #define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U
221 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
224 #undef CRL_APB_RPLL_CTRL_RESET_DEFVAL
225 #undef CRL_APB_RPLL_CTRL_RESET_SHIFT
226 #undef CRL_APB_RPLL_CTRL_RESET_MASK
227 #define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09
228 #define CRL_APB_RPLL_CTRL_RESET_SHIFT 0
229 #define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U
234 #undef CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL
235 #undef CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT
236 #undef CRL_APB_PLL_STATUS_RPLL_LOCK_MASK
237 #define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 0x00000018
238 #define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 1
239 #define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 0x00000002U
240 #define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040
243 * Bypasses the PLL clock. The usable clock will be determined from the POS
244 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
245 * clock and 4 cycles of the new clock. This is not usually an issue, but d
246 * esigners must be aware.)
248 #undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL
249 #undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT
250 #undef CRL_APB_RPLL_CTRL_BYPASS_MASK
251 #define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09
252 #define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3
253 #define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U
256 * Divisor value for this clock.
258 #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL
259 #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
260 #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK
261 #define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400
262 #define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8
263 #define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U
266 * PLL loop filter resistor control
268 #undef CRL_APB_IOPLL_CFG_RES_DEFVAL
269 #undef CRL_APB_IOPLL_CFG_RES_SHIFT
270 #undef CRL_APB_IOPLL_CFG_RES_MASK
271 #define CRL_APB_IOPLL_CFG_RES_DEFVAL 0x00000000
272 #define CRL_APB_IOPLL_CFG_RES_SHIFT 0
273 #define CRL_APB_IOPLL_CFG_RES_MASK 0x0000000FU
276 * PLL charge pump control
278 #undef CRL_APB_IOPLL_CFG_CP_DEFVAL
279 #undef CRL_APB_IOPLL_CFG_CP_SHIFT
280 #undef CRL_APB_IOPLL_CFG_CP_MASK
281 #define CRL_APB_IOPLL_CFG_CP_DEFVAL 0x00000000
282 #define CRL_APB_IOPLL_CFG_CP_SHIFT 5
283 #define CRL_APB_IOPLL_CFG_CP_MASK 0x000001E0U
286 * PLL loop filter high frequency capacitor control
288 #undef CRL_APB_IOPLL_CFG_LFHF_DEFVAL
289 #undef CRL_APB_IOPLL_CFG_LFHF_SHIFT
290 #undef CRL_APB_IOPLL_CFG_LFHF_MASK
291 #define CRL_APB_IOPLL_CFG_LFHF_DEFVAL 0x00000000
292 #define CRL_APB_IOPLL_CFG_LFHF_SHIFT 10
293 #define CRL_APB_IOPLL_CFG_LFHF_MASK 0x00000C00U
296 * Lock circuit counter setting
298 #undef CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL
299 #undef CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT
300 #undef CRL_APB_IOPLL_CFG_LOCK_CNT_MASK
301 #define CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL 0x00000000
302 #define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 13
303 #define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK 0x007FE000U
306 * Lock circuit configuration settings for lock windowsize
308 #undef CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL
309 #undef CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT
310 #undef CRL_APB_IOPLL_CFG_LOCK_DLY_MASK
311 #define CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL 0x00000000
312 #define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 25
313 #define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK 0xFE000000U
316 * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
317 * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
318 * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
320 #undef CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL
321 #undef CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT
322 #undef CRL_APB_IOPLL_CTRL_PRE_SRC_MASK
323 #define CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09
324 #define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 20
325 #define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK 0x00700000U
328 * The integer portion of the feedback divider to the PLL
330 #undef CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL
331 #undef CRL_APB_IOPLL_CTRL_FBDIV_SHIFT
332 #undef CRL_APB_IOPLL_CTRL_FBDIV_MASK
333 #define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 0x00012C09
334 #define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 8
335 #define CRL_APB_IOPLL_CTRL_FBDIV_MASK 0x00007F00U
338 * This turns on the divide by 2 that is inside of the PLL. This does not c
339 * hange the VCO frequency, just the output frequency
341 #undef CRL_APB_IOPLL_CTRL_DIV2_DEFVAL
342 #undef CRL_APB_IOPLL_CTRL_DIV2_SHIFT
343 #undef CRL_APB_IOPLL_CTRL_DIV2_MASK
344 #define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 0x00012C09
345 #define CRL_APB_IOPLL_CTRL_DIV2_SHIFT 16
346 #define CRL_APB_IOPLL_CTRL_DIV2_MASK 0x00010000U
349 * Bypasses the PLL clock. The usable clock will be determined from the POS
350 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
351 * clock and 4 cycles of the new clock. This is not usually an issue, but d
352 * esigners must be aware.)
354 #undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL
355 #undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
356 #undef CRL_APB_IOPLL_CTRL_BYPASS_MASK
357 #define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09
358 #define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3
359 #define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U
362 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
365 #undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL
366 #undef CRL_APB_IOPLL_CTRL_RESET_SHIFT
367 #undef CRL_APB_IOPLL_CTRL_RESET_MASK
368 #define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09
369 #define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0
370 #define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U
373 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
376 #undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL
377 #undef CRL_APB_IOPLL_CTRL_RESET_SHIFT
378 #undef CRL_APB_IOPLL_CTRL_RESET_MASK
379 #define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09
380 #define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0
381 #define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U
386 #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL
387 #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT
388 #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK
389 #define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 0x00000018
390 #define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 0
391 #define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 0x00000001U
392 #define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040
395 * Bypasses the PLL clock. The usable clock will be determined from the POS
396 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
397 * clock and 4 cycles of the new clock. This is not usually an issue, but d
398 * esigners must be aware.)
400 #undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL
401 #undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
402 #undef CRL_APB_IOPLL_CTRL_BYPASS_MASK
403 #define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09
404 #define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3
405 #define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U
408 * Divisor value for this clock.
410 #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL
411 #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
412 #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK
413 #define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400
414 #define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8
415 #define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U
418 * PLL loop filter resistor control
420 #undef CRF_APB_APLL_CFG_RES_DEFVAL
421 #undef CRF_APB_APLL_CFG_RES_SHIFT
422 #undef CRF_APB_APLL_CFG_RES_MASK
423 #define CRF_APB_APLL_CFG_RES_DEFVAL 0x00000000
424 #define CRF_APB_APLL_CFG_RES_SHIFT 0
425 #define CRF_APB_APLL_CFG_RES_MASK 0x0000000FU
428 * PLL charge pump control
430 #undef CRF_APB_APLL_CFG_CP_DEFVAL
431 #undef CRF_APB_APLL_CFG_CP_SHIFT
432 #undef CRF_APB_APLL_CFG_CP_MASK
433 #define CRF_APB_APLL_CFG_CP_DEFVAL 0x00000000
434 #define CRF_APB_APLL_CFG_CP_SHIFT 5
435 #define CRF_APB_APLL_CFG_CP_MASK 0x000001E0U
438 * PLL loop filter high frequency capacitor control
440 #undef CRF_APB_APLL_CFG_LFHF_DEFVAL
441 #undef CRF_APB_APLL_CFG_LFHF_SHIFT
442 #undef CRF_APB_APLL_CFG_LFHF_MASK
443 #define CRF_APB_APLL_CFG_LFHF_DEFVAL 0x00000000
444 #define CRF_APB_APLL_CFG_LFHF_SHIFT 10
445 #define CRF_APB_APLL_CFG_LFHF_MASK 0x00000C00U
448 * Lock circuit counter setting
450 #undef CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL
451 #undef CRF_APB_APLL_CFG_LOCK_CNT_SHIFT
452 #undef CRF_APB_APLL_CFG_LOCK_CNT_MASK
453 #define CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL 0x00000000
454 #define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 13
455 #define CRF_APB_APLL_CFG_LOCK_CNT_MASK 0x007FE000U
458 * Lock circuit configuration settings for lock windowsize
460 #undef CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL
461 #undef CRF_APB_APLL_CFG_LOCK_DLY_SHIFT
462 #undef CRF_APB_APLL_CFG_LOCK_DLY_MASK
463 #define CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL 0x00000000
464 #define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 25
465 #define CRF_APB_APLL_CFG_LOCK_DLY_MASK 0xFE000000U
468 * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
469 * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
470 * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
472 #undef CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL
473 #undef CRF_APB_APLL_CTRL_PRE_SRC_SHIFT
474 #undef CRF_APB_APLL_CTRL_PRE_SRC_MASK
475 #define CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL 0x00012C09
476 #define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 20
477 #define CRF_APB_APLL_CTRL_PRE_SRC_MASK 0x00700000U
480 * The integer portion of the feedback divider to the PLL
482 #undef CRF_APB_APLL_CTRL_FBDIV_DEFVAL
483 #undef CRF_APB_APLL_CTRL_FBDIV_SHIFT
484 #undef CRF_APB_APLL_CTRL_FBDIV_MASK
485 #define CRF_APB_APLL_CTRL_FBDIV_DEFVAL 0x00012C09
486 #define CRF_APB_APLL_CTRL_FBDIV_SHIFT 8
487 #define CRF_APB_APLL_CTRL_FBDIV_MASK 0x00007F00U
490 * This turns on the divide by 2 that is inside of the PLL. This does not c
491 * hange the VCO frequency, just the output frequency
493 #undef CRF_APB_APLL_CTRL_DIV2_DEFVAL
494 #undef CRF_APB_APLL_CTRL_DIV2_SHIFT
495 #undef CRF_APB_APLL_CTRL_DIV2_MASK
496 #define CRF_APB_APLL_CTRL_DIV2_DEFVAL 0x00012C09
497 #define CRF_APB_APLL_CTRL_DIV2_SHIFT 16
498 #define CRF_APB_APLL_CTRL_DIV2_MASK 0x00010000U
501 * Bypasses the PLL clock. The usable clock will be determined from the POS
502 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
503 * clock and 4 cycles of the new clock. This is not usually an issue, but d
504 * esigners must be aware.)
506 #undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL
507 #undef CRF_APB_APLL_CTRL_BYPASS_SHIFT
508 #undef CRF_APB_APLL_CTRL_BYPASS_MASK
509 #define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09
510 #define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3
511 #define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U
514 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
517 #undef CRF_APB_APLL_CTRL_RESET_DEFVAL
518 #undef CRF_APB_APLL_CTRL_RESET_SHIFT
519 #undef CRF_APB_APLL_CTRL_RESET_MASK
520 #define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09
521 #define CRF_APB_APLL_CTRL_RESET_SHIFT 0
522 #define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U
525 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
528 #undef CRF_APB_APLL_CTRL_RESET_DEFVAL
529 #undef CRF_APB_APLL_CTRL_RESET_SHIFT
530 #undef CRF_APB_APLL_CTRL_RESET_MASK
531 #define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09
532 #define CRF_APB_APLL_CTRL_RESET_SHIFT 0
533 #define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U
538 #undef CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL
539 #undef CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT
540 #undef CRF_APB_PLL_STATUS_APLL_LOCK_MASK
541 #define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 0x00000038
542 #define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 0
543 #define CRF_APB_PLL_STATUS_APLL_LOCK_MASK 0x00000001U
544 #define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044
547 * Bypasses the PLL clock. The usable clock will be determined from the POS
548 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
549 * clock and 4 cycles of the new clock. This is not usually an issue, but d
550 * esigners must be aware.)
552 #undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL
553 #undef CRF_APB_APLL_CTRL_BYPASS_SHIFT
554 #undef CRF_APB_APLL_CTRL_BYPASS_MASK
555 #define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09
556 #define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3
557 #define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U
560 * Divisor value for this clock.
562 #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL
563 #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT
564 #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK
565 #define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400
566 #define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8
567 #define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U
570 * PLL loop filter resistor control
572 #undef CRF_APB_DPLL_CFG_RES_DEFVAL
573 #undef CRF_APB_DPLL_CFG_RES_SHIFT
574 #undef CRF_APB_DPLL_CFG_RES_MASK
575 #define CRF_APB_DPLL_CFG_RES_DEFVAL 0x00000000
576 #define CRF_APB_DPLL_CFG_RES_SHIFT 0
577 #define CRF_APB_DPLL_CFG_RES_MASK 0x0000000FU
580 * PLL charge pump control
582 #undef CRF_APB_DPLL_CFG_CP_DEFVAL
583 #undef CRF_APB_DPLL_CFG_CP_SHIFT
584 #undef CRF_APB_DPLL_CFG_CP_MASK
585 #define CRF_APB_DPLL_CFG_CP_DEFVAL 0x00000000
586 #define CRF_APB_DPLL_CFG_CP_SHIFT 5
587 #define CRF_APB_DPLL_CFG_CP_MASK 0x000001E0U
590 * PLL loop filter high frequency capacitor control
592 #undef CRF_APB_DPLL_CFG_LFHF_DEFVAL
593 #undef CRF_APB_DPLL_CFG_LFHF_SHIFT
594 #undef CRF_APB_DPLL_CFG_LFHF_MASK
595 #define CRF_APB_DPLL_CFG_LFHF_DEFVAL 0x00000000
596 #define CRF_APB_DPLL_CFG_LFHF_SHIFT 10
597 #define CRF_APB_DPLL_CFG_LFHF_MASK 0x00000C00U
600 * Lock circuit counter setting
602 #undef CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL
603 #undef CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT
604 #undef CRF_APB_DPLL_CFG_LOCK_CNT_MASK
605 #define CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL 0x00000000
606 #define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13
607 #define CRF_APB_DPLL_CFG_LOCK_CNT_MASK 0x007FE000U
610 * Lock circuit configuration settings for lock windowsize
612 #undef CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL
613 #undef CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT
614 #undef CRF_APB_DPLL_CFG_LOCK_DLY_MASK
615 #define CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL 0x00000000
616 #define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25
617 #define CRF_APB_DPLL_CFG_LOCK_DLY_MASK 0xFE000000U
620 * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
621 * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
622 * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
624 #undef CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL
625 #undef CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT
626 #undef CRF_APB_DPLL_CTRL_PRE_SRC_MASK
627 #define CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL 0x00002C09
628 #define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 20
629 #define CRF_APB_DPLL_CTRL_PRE_SRC_MASK 0x00700000U
632 * The integer portion of the feedback divider to the PLL
634 #undef CRF_APB_DPLL_CTRL_FBDIV_DEFVAL
635 #undef CRF_APB_DPLL_CTRL_FBDIV_SHIFT
636 #undef CRF_APB_DPLL_CTRL_FBDIV_MASK
637 #define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 0x00002C09
638 #define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8
639 #define CRF_APB_DPLL_CTRL_FBDIV_MASK 0x00007F00U
642 * This turns on the divide by 2 that is inside of the PLL. This does not c
643 * hange the VCO frequency, just the output frequency
645 #undef CRF_APB_DPLL_CTRL_DIV2_DEFVAL
646 #undef CRF_APB_DPLL_CTRL_DIV2_SHIFT
647 #undef CRF_APB_DPLL_CTRL_DIV2_MASK
648 #define CRF_APB_DPLL_CTRL_DIV2_DEFVAL 0x00002C09
649 #define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16
650 #define CRF_APB_DPLL_CTRL_DIV2_MASK 0x00010000U
653 * Bypasses the PLL clock. The usable clock will be determined from the POS
654 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
655 * clock and 4 cycles of the new clock. This is not usually an issue, but d
656 * esigners must be aware.)
658 #undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL
659 #undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT
660 #undef CRF_APB_DPLL_CTRL_BYPASS_MASK
661 #define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09
662 #define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3
663 #define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U
666 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
669 #undef CRF_APB_DPLL_CTRL_RESET_DEFVAL
670 #undef CRF_APB_DPLL_CTRL_RESET_SHIFT
671 #undef CRF_APB_DPLL_CTRL_RESET_MASK
672 #define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09
673 #define CRF_APB_DPLL_CTRL_RESET_SHIFT 0
674 #define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U
677 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
680 #undef CRF_APB_DPLL_CTRL_RESET_DEFVAL
681 #undef CRF_APB_DPLL_CTRL_RESET_SHIFT
682 #undef CRF_APB_DPLL_CTRL_RESET_MASK
683 #define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09
684 #define CRF_APB_DPLL_CTRL_RESET_SHIFT 0
685 #define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U
690 #undef CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL
691 #undef CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT
692 #undef CRF_APB_PLL_STATUS_DPLL_LOCK_MASK
693 #define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 0x00000038
694 #define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 1
695 #define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 0x00000002U
696 #define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044
699 * Bypasses the PLL clock. The usable clock will be determined from the POS
700 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
701 * clock and 4 cycles of the new clock. This is not usually an issue, but d
702 * esigners must be aware.)
704 #undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL
705 #undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT
706 #undef CRF_APB_DPLL_CTRL_BYPASS_MASK
707 #define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09
708 #define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3
709 #define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U
712 * Divisor value for this clock.
714 #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL
715 #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
716 #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK
717 #define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400
718 #define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8
719 #define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U
722 * PLL loop filter resistor control
724 #undef CRF_APB_VPLL_CFG_RES_DEFVAL
725 #undef CRF_APB_VPLL_CFG_RES_SHIFT
726 #undef CRF_APB_VPLL_CFG_RES_MASK
727 #define CRF_APB_VPLL_CFG_RES_DEFVAL 0x00000000
728 #define CRF_APB_VPLL_CFG_RES_SHIFT 0
729 #define CRF_APB_VPLL_CFG_RES_MASK 0x0000000FU
732 * PLL charge pump control
734 #undef CRF_APB_VPLL_CFG_CP_DEFVAL
735 #undef CRF_APB_VPLL_CFG_CP_SHIFT
736 #undef CRF_APB_VPLL_CFG_CP_MASK
737 #define CRF_APB_VPLL_CFG_CP_DEFVAL 0x00000000
738 #define CRF_APB_VPLL_CFG_CP_SHIFT 5
739 #define CRF_APB_VPLL_CFG_CP_MASK 0x000001E0U
742 * PLL loop filter high frequency capacitor control
744 #undef CRF_APB_VPLL_CFG_LFHF_DEFVAL
745 #undef CRF_APB_VPLL_CFG_LFHF_SHIFT
746 #undef CRF_APB_VPLL_CFG_LFHF_MASK
747 #define CRF_APB_VPLL_CFG_LFHF_DEFVAL 0x00000000
748 #define CRF_APB_VPLL_CFG_LFHF_SHIFT 10
749 #define CRF_APB_VPLL_CFG_LFHF_MASK 0x00000C00U
752 * Lock circuit counter setting
754 #undef CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL
755 #undef CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT
756 #undef CRF_APB_VPLL_CFG_LOCK_CNT_MASK
757 #define CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL 0x00000000
758 #define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 13
759 #define CRF_APB_VPLL_CFG_LOCK_CNT_MASK 0x007FE000U
762 * Lock circuit configuration settings for lock windowsize
764 #undef CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL
765 #undef CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT
766 #undef CRF_APB_VPLL_CFG_LOCK_DLY_MASK
767 #define CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL 0x00000000
768 #define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 25
769 #define CRF_APB_VPLL_CFG_LOCK_DLY_MASK 0xFE000000U
772 * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
773 * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
774 * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
776 #undef CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL
777 #undef CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT
778 #undef CRF_APB_VPLL_CTRL_PRE_SRC_MASK
779 #define CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL 0x00012809
780 #define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 20
781 #define CRF_APB_VPLL_CTRL_PRE_SRC_MASK 0x00700000U
784 * The integer portion of the feedback divider to the PLL
786 #undef CRF_APB_VPLL_CTRL_FBDIV_DEFVAL
787 #undef CRF_APB_VPLL_CTRL_FBDIV_SHIFT
788 #undef CRF_APB_VPLL_CTRL_FBDIV_MASK
789 #define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 0x00012809
790 #define CRF_APB_VPLL_CTRL_FBDIV_SHIFT 8
791 #define CRF_APB_VPLL_CTRL_FBDIV_MASK 0x00007F00U
794 * This turns on the divide by 2 that is inside of the PLL. This does not c
795 * hange the VCO frequency, just the output frequency
797 #undef CRF_APB_VPLL_CTRL_DIV2_DEFVAL
798 #undef CRF_APB_VPLL_CTRL_DIV2_SHIFT
799 #undef CRF_APB_VPLL_CTRL_DIV2_MASK
800 #define CRF_APB_VPLL_CTRL_DIV2_DEFVAL 0x00012809
801 #define CRF_APB_VPLL_CTRL_DIV2_SHIFT 16
802 #define CRF_APB_VPLL_CTRL_DIV2_MASK 0x00010000U
805 * Bypasses the PLL clock. The usable clock will be determined from the POS
806 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
807 * clock and 4 cycles of the new clock. This is not usually an issue, but d
808 * esigners must be aware.)
810 #undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL
811 #undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT
812 #undef CRF_APB_VPLL_CTRL_BYPASS_MASK
813 #define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809
814 #define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3
815 #define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U
818 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
821 #undef CRF_APB_VPLL_CTRL_RESET_DEFVAL
822 #undef CRF_APB_VPLL_CTRL_RESET_SHIFT
823 #undef CRF_APB_VPLL_CTRL_RESET_MASK
824 #define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809
825 #define CRF_APB_VPLL_CTRL_RESET_SHIFT 0
826 #define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U
829 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
832 #undef CRF_APB_VPLL_CTRL_RESET_DEFVAL
833 #undef CRF_APB_VPLL_CTRL_RESET_SHIFT
834 #undef CRF_APB_VPLL_CTRL_RESET_MASK
835 #define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809
836 #define CRF_APB_VPLL_CTRL_RESET_SHIFT 0
837 #define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U
842 #undef CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL
843 #undef CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT
844 #undef CRF_APB_PLL_STATUS_VPLL_LOCK_MASK
845 #define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 0x00000038
846 #define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 2
847 #define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 0x00000004U
848 #define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044
851 * Bypasses the PLL clock. The usable clock will be determined from the POS
852 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
853 * clock and 4 cycles of the new clock. This is not usually an issue, but d
854 * esigners must be aware.)
856 #undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL
857 #undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT
858 #undef CRF_APB_VPLL_CTRL_BYPASS_MASK
859 #define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809
860 #define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3
861 #define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U
864 * Divisor value for this clock.
866 #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL
867 #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
868 #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK
869 #define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400
870 #define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8
871 #define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U
872 #undef CRL_APB_GEM3_REF_CTRL_OFFSET
873 #define CRL_APB_GEM3_REF_CTRL_OFFSET 0XFF5E005C
874 #undef CRL_APB_GEM_TSU_REF_CTRL_OFFSET
875 #define CRL_APB_GEM_TSU_REF_CTRL_OFFSET 0XFF5E0100
876 #undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET
877 #define CRL_APB_USB0_BUS_REF_CTRL_OFFSET 0XFF5E0060
878 #undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET
879 #define CRL_APB_USB3_DUAL_REF_CTRL_OFFSET 0XFF5E004C
880 #undef CRL_APB_QSPI_REF_CTRL_OFFSET
881 #define CRL_APB_QSPI_REF_CTRL_OFFSET 0XFF5E0068
882 #undef CRL_APB_SDIO1_REF_CTRL_OFFSET
883 #define CRL_APB_SDIO1_REF_CTRL_OFFSET 0XFF5E0070
884 #undef IOU_SLCR_SDIO_CLK_CTRL_OFFSET
885 #define IOU_SLCR_SDIO_CLK_CTRL_OFFSET 0XFF18030C
886 #undef CRL_APB_UART0_REF_CTRL_OFFSET
887 #define CRL_APB_UART0_REF_CTRL_OFFSET 0XFF5E0074
888 #undef CRL_APB_UART1_REF_CTRL_OFFSET
889 #define CRL_APB_UART1_REF_CTRL_OFFSET 0XFF5E0078
890 #undef CRL_APB_I2C0_REF_CTRL_OFFSET
891 #define CRL_APB_I2C0_REF_CTRL_OFFSET 0XFF5E0120
892 #undef CRL_APB_I2C1_REF_CTRL_OFFSET
893 #define CRL_APB_I2C1_REF_CTRL_OFFSET 0XFF5E0124
894 #undef CRL_APB_CAN1_REF_CTRL_OFFSET
895 #define CRL_APB_CAN1_REF_CTRL_OFFSET 0XFF5E0088
896 #undef CRL_APB_CPU_R5_CTRL_OFFSET
897 #define CRL_APB_CPU_R5_CTRL_OFFSET 0XFF5E0090
898 #undef CRL_APB_IOU_SWITCH_CTRL_OFFSET
899 #define CRL_APB_IOU_SWITCH_CTRL_OFFSET 0XFF5E009C
900 #undef CRL_APB_PCAP_CTRL_OFFSET
901 #define CRL_APB_PCAP_CTRL_OFFSET 0XFF5E00A4
902 #undef CRL_APB_LPD_SWITCH_CTRL_OFFSET
903 #define CRL_APB_LPD_SWITCH_CTRL_OFFSET 0XFF5E00A8
904 #undef CRL_APB_LPD_LSBUS_CTRL_OFFSET
905 #define CRL_APB_LPD_LSBUS_CTRL_OFFSET 0XFF5E00AC
906 #undef CRL_APB_DBG_LPD_CTRL_OFFSET
907 #define CRL_APB_DBG_LPD_CTRL_OFFSET 0XFF5E00B0
908 #undef CRL_APB_ADMA_REF_CTRL_OFFSET
909 #define CRL_APB_ADMA_REF_CTRL_OFFSET 0XFF5E00B8
910 #undef CRL_APB_PL0_REF_CTRL_OFFSET
911 #define CRL_APB_PL0_REF_CTRL_OFFSET 0XFF5E00C0
912 #undef CRL_APB_AMS_REF_CTRL_OFFSET
913 #define CRL_APB_AMS_REF_CTRL_OFFSET 0XFF5E0108
914 #undef CRL_APB_DLL_REF_CTRL_OFFSET
915 #define CRL_APB_DLL_REF_CTRL_OFFSET 0XFF5E0104
916 #undef CRL_APB_TIMESTAMP_REF_CTRL_OFFSET
917 #define CRL_APB_TIMESTAMP_REF_CTRL_OFFSET 0XFF5E0128
918 #undef CRF_APB_SATA_REF_CTRL_OFFSET
919 #define CRF_APB_SATA_REF_CTRL_OFFSET 0XFD1A00A0
920 #undef CRF_APB_PCIE_REF_CTRL_OFFSET
921 #define CRF_APB_PCIE_REF_CTRL_OFFSET 0XFD1A00B4
922 #undef CRF_APB_DP_VIDEO_REF_CTRL_OFFSET
923 #define CRF_APB_DP_VIDEO_REF_CTRL_OFFSET 0XFD1A0070
924 #undef CRF_APB_DP_AUDIO_REF_CTRL_OFFSET
925 #define CRF_APB_DP_AUDIO_REF_CTRL_OFFSET 0XFD1A0074
926 #undef CRF_APB_DP_STC_REF_CTRL_OFFSET
927 #define CRF_APB_DP_STC_REF_CTRL_OFFSET 0XFD1A007C
928 #undef CRF_APB_ACPU_CTRL_OFFSET
929 #define CRF_APB_ACPU_CTRL_OFFSET 0XFD1A0060
930 #undef CRF_APB_DBG_FPD_CTRL_OFFSET
931 #define CRF_APB_DBG_FPD_CTRL_OFFSET 0XFD1A0068
932 #undef CRF_APB_DDR_CTRL_OFFSET
933 #define CRF_APB_DDR_CTRL_OFFSET 0XFD1A0080
934 #undef CRF_APB_GPU_REF_CTRL_OFFSET
935 #define CRF_APB_GPU_REF_CTRL_OFFSET 0XFD1A0084
936 #undef CRF_APB_GDMA_REF_CTRL_OFFSET
937 #define CRF_APB_GDMA_REF_CTRL_OFFSET 0XFD1A00B8
938 #undef CRF_APB_DPDMA_REF_CTRL_OFFSET
939 #define CRF_APB_DPDMA_REF_CTRL_OFFSET 0XFD1A00BC
940 #undef CRF_APB_TOPSW_MAIN_CTRL_OFFSET
941 #define CRF_APB_TOPSW_MAIN_CTRL_OFFSET 0XFD1A00C0
942 #undef CRF_APB_TOPSW_LSBUS_CTRL_OFFSET
943 #define CRF_APB_TOPSW_LSBUS_CTRL_OFFSET 0XFD1A00C4
944 #undef CRF_APB_DBG_TSTMP_CTRL_OFFSET
945 #define CRF_APB_DBG_TSTMP_CTRL_OFFSET 0XFD1A00F8
946 #undef IOU_SLCR_IOU_TTC_APB_CLK_OFFSET
947 #define IOU_SLCR_IOU_TTC_APB_CLK_OFFSET 0XFF180380
948 #undef FPD_SLCR_WDT_CLK_SEL_OFFSET
949 #define FPD_SLCR_WDT_CLK_SEL_OFFSET 0XFD610100
950 #undef IOU_SLCR_WDT_CLK_SEL_OFFSET
951 #define IOU_SLCR_WDT_CLK_SEL_OFFSET 0XFF180300
952 #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET
953 #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET 0XFF410050
956 * Clock active for the RX channel
958 #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL
959 #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT
960 #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK
961 #define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500
962 #define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 26
963 #define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 0x04000000U
966 * Clock active signal. Switch to 0 to disable the clock
968 #undef CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL
969 #undef CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT
970 #undef CRL_APB_GEM3_REF_CTRL_CLKACT_MASK
971 #define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 0x00002500
972 #define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 25
973 #define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 0x02000000U
978 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL
979 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT
980 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK
981 #define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 0x00002500
982 #define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 16
983 #define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 0x003F0000U
988 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL
989 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT
990 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK
991 #define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 0x00002500
992 #define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 8
993 #define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 0x00003F00U
996 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
997 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
998 * usually an issue, but designers must be aware.)
1000 #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL
1001 #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT
1002 #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK
1003 #define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 0x00002500
1004 #define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 0
1005 #define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 0x00000007U
1010 #undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL
1011 #undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT
1012 #undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK
1013 #define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL 0x00051000
1014 #define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT 8
1015 #define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1018 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1019 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1020 * usually an issue, but designers must be aware.)
1022 #undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL
1023 #undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT
1024 #undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK
1025 #define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL 0x00051000
1026 #define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT 0
1027 #define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK 0x00000007U
1032 #undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL
1033 #undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT
1034 #undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK
1035 #define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL 0x00051000
1036 #define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT 16
1037 #define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1040 * Clock active signal. Switch to 0 to disable the clock
1042 #undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL
1043 #undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT
1044 #undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK
1045 #define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL 0x00051000
1046 #define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT 24
1047 #define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK 0x01000000U
1050 * Clock active signal. Switch to 0 to disable the clock
1052 #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL
1053 #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT
1054 #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK
1055 #define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 0x00052000
1056 #define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 25
1057 #define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 0x02000000U
1062 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL
1063 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT
1064 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK
1065 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 0x00052000
1066 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 16
1067 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1072 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL
1073 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT
1074 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK
1075 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 0x00052000
1076 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 8
1077 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1080 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1081 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1082 * usually an issue, but designers must be aware.)
1084 #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL
1085 #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT
1086 #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK
1087 #define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 0x00052000
1088 #define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 0
1089 #define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 0x00000007U
1092 * Clock active signal. Switch to 0 to disable the clock
1094 #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL
1095 #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT
1096 #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK
1097 #define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 0x00052000
1098 #define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 25
1099 #define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 0x02000000U
1104 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL
1105 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT
1106 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK
1107 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 0x00052000
1108 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 16
1109 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1114 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL
1115 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT
1116 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK
1117 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 0x00052000
1118 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 8
1119 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1122 * 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af
1123 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1124 * usually an issue, but designers must be aware.)
1126 #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL
1127 #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT
1128 #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK
1129 #define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 0x00052000
1130 #define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 0
1131 #define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 0x00000007U
1134 * Clock active signal. Switch to 0 to disable the clock
1136 #undef CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL
1137 #undef CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT
1138 #undef CRL_APB_QSPI_REF_CTRL_CLKACT_MASK
1139 #define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 0x01000800
1140 #define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 24
1141 #define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 0x01000000U
1146 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL
1147 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT
1148 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK
1149 #define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 0x01000800
1150 #define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 16
1151 #define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1156 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL
1157 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT
1158 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK
1159 #define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 0x01000800
1160 #define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 8
1161 #define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1164 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1165 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1166 * usually an issue, but designers must be aware.)
1168 #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL
1169 #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT
1170 #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK
1171 #define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 0x01000800
1172 #define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 0
1173 #define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 0x00000007U
1176 * Clock active signal. Switch to 0 to disable the clock
1178 #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL
1179 #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT
1180 #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK
1181 #define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 0x01000F00
1182 #define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 24
1183 #define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 0x01000000U
1188 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL
1189 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT
1190 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK
1191 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 0x01000F00
1192 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 16
1193 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1198 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL
1199 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT
1200 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK
1201 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 0x01000F00
1202 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 8
1203 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1206 * 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af
1207 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1208 * usually an issue, but designers must be aware.)
1210 #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL
1211 #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT
1212 #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK
1213 #define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 0x01000F00
1214 #define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 0
1215 #define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 0x00000007U
1218 * MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO
1221 #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL
1222 #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT
1223 #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK
1224 #define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 0x00000000
1225 #define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 17
1226 #define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 0x00020000U
1229 * Clock active signal. Switch to 0 to disable the clock
1231 #undef CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL
1232 #undef CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT
1233 #undef CRL_APB_UART0_REF_CTRL_CLKACT_MASK
1234 #define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 0x01001800
1235 #define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 24
1236 #define CRL_APB_UART0_REF_CTRL_CLKACT_MASK 0x01000000U
1241 #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL
1242 #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT
1243 #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK
1244 #define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
1245 #define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 16
1246 #define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1251 #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL
1252 #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT
1253 #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK
1254 #define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
1255 #define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 8
1256 #define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1259 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1260 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1261 * usually an issue, but designers must be aware.)
1263 #undef CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL
1264 #undef CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT
1265 #undef CRL_APB_UART0_REF_CTRL_SRCSEL_MASK
1266 #define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 0x01001800
1267 #define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 0
1268 #define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 0x00000007U
1271 * Clock active signal. Switch to 0 to disable the clock
1273 #undef CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL
1274 #undef CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT
1275 #undef CRL_APB_UART1_REF_CTRL_CLKACT_MASK
1276 #define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 0x01001800
1277 #define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 24
1278 #define CRL_APB_UART1_REF_CTRL_CLKACT_MASK 0x01000000U
1283 #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL
1284 #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT
1285 #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK
1286 #define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
1287 #define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 16
1288 #define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1293 #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL
1294 #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT
1295 #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK
1296 #define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
1297 #define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 8
1298 #define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1301 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1302 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1303 * usually an issue, but designers must be aware.)
1305 #undef CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL
1306 #undef CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT
1307 #undef CRL_APB_UART1_REF_CTRL_SRCSEL_MASK
1308 #define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 0x01001800
1309 #define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 0
1310 #define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 0x00000007U
1313 * Clock active signal. Switch to 0 to disable the clock
1315 #undef CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL
1316 #undef CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT
1317 #undef CRL_APB_I2C0_REF_CTRL_CLKACT_MASK
1318 #define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 0x01000500
1319 #define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 24
1320 #define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 0x01000000U
1325 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL
1326 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT
1327 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK
1328 #define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 0x01000500
1329 #define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 16
1330 #define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1335 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL
1336 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT
1337 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK
1338 #define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 0x01000500
1339 #define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 8
1340 #define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1343 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1344 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1345 * usually an issue, but designers must be aware.)
1347 #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL
1348 #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT
1349 #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK
1350 #define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 0x01000500
1351 #define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 0
1352 #define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 0x00000007U
1355 * Clock active signal. Switch to 0 to disable the clock
1357 #undef CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL
1358 #undef CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT
1359 #undef CRL_APB_I2C1_REF_CTRL_CLKACT_MASK
1360 #define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 0x01000500
1361 #define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 24
1362 #define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 0x01000000U
1367 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL
1368 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT
1369 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK
1370 #define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 0x01000500
1371 #define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 16
1372 #define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1377 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL
1378 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT
1379 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK
1380 #define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 0x01000500
1381 #define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 8
1382 #define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1385 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1386 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1387 * usually an issue, but designers must be aware.)
1389 #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL
1390 #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT
1391 #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK
1392 #define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 0x01000500
1393 #define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 0
1394 #define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 0x00000007U
1397 * Clock active signal. Switch to 0 to disable the clock
1399 #undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL
1400 #undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT
1401 #undef CRL_APB_CAN1_REF_CTRL_CLKACT_MASK
1402 #define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 0x01001800
1403 #define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 24
1404 #define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 0x01000000U
1409 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL
1410 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT
1411 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK
1412 #define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
1413 #define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 16
1414 #define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1419 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL
1420 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT
1421 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK
1422 #define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
1423 #define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 8
1424 #define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1427 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1428 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1429 * usually an issue, but designers must be aware.)
1431 #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL
1432 #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT
1433 #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK
1434 #define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 0x01001800
1435 #define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 0
1436 #define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 0x00000007U
1439 * Turing this off will shut down the OCM, some parts of the APM, and preve
1440 * nt transactions going from the FPD to the LPD and could lead to system h
1443 #undef CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL
1444 #undef CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT
1445 #undef CRL_APB_CPU_R5_CTRL_CLKACT_MASK
1446 #define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 0x03000600
1447 #define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 24
1448 #define CRL_APB_CPU_R5_CTRL_CLKACT_MASK 0x01000000U
1453 #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL
1454 #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT
1455 #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK
1456 #define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 0x03000600
1457 #define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 8
1458 #define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 0x00003F00U
1461 * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
1462 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1463 * usually an issue, but designers must be aware.)
1465 #undef CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL
1466 #undef CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT
1467 #undef CRL_APB_CPU_R5_CTRL_SRCSEL_MASK
1468 #define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 0x03000600
1469 #define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 0
1470 #define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 0x00000007U
1473 * Clock active signal. Switch to 0 to disable the clock
1475 #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL
1476 #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT
1477 #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK
1478 #define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 0x00001500
1479 #define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 24
1480 #define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 0x01000000U
1485 #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL
1486 #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT
1487 #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK
1488 #define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 0x00001500
1489 #define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8
1490 #define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U
1493 * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
1494 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1495 * usually an issue, but designers must be aware.)
1497 #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL
1498 #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT
1499 #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK
1500 #define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 0x00001500
1501 #define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 0
1502 #define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 0x00000007U
1505 * Clock active signal. Switch to 0 to disable the clock
1507 #undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL
1508 #undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT
1509 #undef CRL_APB_PCAP_CTRL_CLKACT_MASK
1510 #define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 0x00001500
1511 #define CRL_APB_PCAP_CTRL_CLKACT_SHIFT 24
1512 #define CRL_APB_PCAP_CTRL_CLKACT_MASK 0x01000000U
1517 #undef CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL
1518 #undef CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT
1519 #undef CRL_APB_PCAP_CTRL_DIVISOR0_MASK
1520 #define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 0x00001500
1521 #define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 8
1522 #define CRL_APB_PCAP_CTRL_DIVISOR0_MASK 0x00003F00U
1525 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1526 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1527 * usually an issue, but designers must be aware.)
1529 #undef CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL
1530 #undef CRL_APB_PCAP_CTRL_SRCSEL_SHIFT
1531 #undef CRL_APB_PCAP_CTRL_SRCSEL_MASK
1532 #define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 0x00001500
1533 #define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 0
1534 #define CRL_APB_PCAP_CTRL_SRCSEL_MASK 0x00000007U
1537 * Clock active signal. Switch to 0 to disable the clock
1539 #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL
1540 #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT
1541 #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK
1542 #define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 0x01000500
1543 #define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 24
1544 #define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 0x01000000U
1549 #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL
1550 #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT
1551 #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK
1552 #define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 0x01000500
1553 #define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 8
1554 #define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U
1557 * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
1558 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1559 * usually an issue, but designers must be aware.)
1561 #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL
1562 #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT
1563 #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK
1564 #define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 0x01000500
1565 #define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 0
1566 #define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 0x00000007U
1569 * Clock active signal. Switch to 0 to disable the clock
1571 #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL
1572 #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT
1573 #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK
1574 #define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 0x01001800
1575 #define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 24
1576 #define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 0x01000000U
1581 #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL
1582 #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT
1583 #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK
1584 #define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01001800
1585 #define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 8
1586 #define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U
1589 * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
1590 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1591 * usually an issue, but designers must be aware.)
1593 #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL
1594 #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT
1595 #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK
1596 #define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 0x01001800
1597 #define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 0
1598 #define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 0x00000007U
1601 * Clock active signal. Switch to 0 to disable the clock
1603 #undef CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL
1604 #undef CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT
1605 #undef CRL_APB_DBG_LPD_CTRL_CLKACT_MASK
1606 #define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 0x01002000
1607 #define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 24
1608 #define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 0x01000000U
1613 #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL
1614 #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT
1615 #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK
1616 #define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 0x01002000
1617 #define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 8
1618 #define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 0x00003F00U
1621 * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
1622 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1623 * usually an issue, but designers must be aware.)
1625 #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL
1626 #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT
1627 #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK
1628 #define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 0x01002000
1629 #define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 0
1630 #define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 0x00000007U
1633 * Clock active signal. Switch to 0 to disable the clock
1635 #undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL
1636 #undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT
1637 #undef CRL_APB_ADMA_REF_CTRL_CLKACT_MASK
1638 #define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 0x00002000
1639 #define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 24
1640 #define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 0x01000000U
1645 #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL
1646 #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT
1647 #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK
1648 #define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 0x00002000
1649 #define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 8
1650 #define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1653 * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
1654 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1655 * usually an issue, but designers must be aware.)
1657 #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL
1658 #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT
1659 #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK
1660 #define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 0x00002000
1661 #define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 0
1662 #define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 0x00000007U
1665 * Clock active signal. Switch to 0 to disable the clock
1667 #undef CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL
1668 #undef CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT
1669 #undef CRL_APB_PL0_REF_CTRL_CLKACT_MASK
1670 #define CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL 0x00052000
1671 #define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 24
1672 #define CRL_APB_PL0_REF_CTRL_CLKACT_MASK 0x01000000U
1677 #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL
1678 #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT
1679 #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK
1680 #define CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL 0x00052000
1681 #define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 16
1682 #define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1687 #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL
1688 #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT
1689 #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK
1690 #define CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL 0x00052000
1691 #define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 8
1692 #define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1695 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1696 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1697 * usually an issue, but designers must be aware.)
1699 #undef CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL
1700 #undef CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT
1701 #undef CRL_APB_PL0_REF_CTRL_SRCSEL_MASK
1702 #define CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL 0x00052000
1703 #define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 0
1704 #define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK 0x00000007U
1709 #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL
1710 #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT
1711 #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK
1712 #define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
1713 #define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16
1714 #define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1719 #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL
1720 #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT
1721 #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK
1722 #define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
1723 #define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8
1724 #define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1727 * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
1728 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1729 * usually an issue, but designers must be aware.)
1731 #undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL
1732 #undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT
1733 #undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK
1734 #define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 0x01001800
1735 #define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0
1736 #define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 0x00000007U
1739 * Clock active signal. Switch to 0 to disable the clock
1741 #undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL
1742 #undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT
1743 #undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK
1744 #define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 0x01001800
1745 #define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24
1746 #define CRL_APB_AMS_REF_CTRL_CLKACT_MASK 0x01000000U
1749 * 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles
1750 * of the old clock and 4 cycles of the new clock. This is not usually an
1751 * issue, but designers must be aware.)
1753 #undef CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL
1754 #undef CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT
1755 #undef CRL_APB_DLL_REF_CTRL_SRCSEL_MASK
1756 #define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 0x00000000
1757 #define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 0
1758 #define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 0x00000007U
1763 #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL
1764 #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT
1765 #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK
1766 #define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 0x00001800
1767 #define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 8
1768 #define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1771 * 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may
1772 * only be toggled after 4 cycles of the old clock and 4 cycles of the new
1773 * clock. This is not usually an issue, but designers must be aware.)
1775 #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL
1776 #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT
1777 #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK
1778 #define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 0x00001800
1779 #define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 0
1780 #define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 0x00000007U
1783 * Clock active signal. Switch to 0 to disable the clock
1785 #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL
1786 #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT
1787 #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK
1788 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 0x00001800
1789 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 24
1790 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 0x01000000U
1793 * 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog
1794 * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
1795 * is not usually an issue, but designers must be aware.)
1797 #undef CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL
1798 #undef CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT
1799 #undef CRF_APB_SATA_REF_CTRL_SRCSEL_MASK
1800 #define CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL 0x01001600
1801 #define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 0
1802 #define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK 0x00000007U
1805 * Clock active signal. Switch to 0 to disable the clock
1807 #undef CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL
1808 #undef CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT
1809 #undef CRF_APB_SATA_REF_CTRL_CLKACT_MASK
1810 #define CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL 0x01001600
1811 #define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 24
1812 #define CRF_APB_SATA_REF_CTRL_CLKACT_MASK 0x01000000U
1817 #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL
1818 #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT
1819 #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK
1820 #define CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL 0x01001600
1821 #define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 8
1822 #define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1825 * 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only
1826 * be toggled after 4 cycles of the old clock and 4 cycles of the new cloc
1827 * k. This is not usually an issue, but designers must be aware.)
1829 #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL
1830 #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT
1831 #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK
1832 #define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 0x00001500
1833 #define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 0
1834 #define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 0x00000007U
1837 * Clock active signal. Switch to 0 to disable the clock
1839 #undef CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL
1840 #undef CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT
1841 #undef CRF_APB_PCIE_REF_CTRL_CLKACT_MASK
1842 #define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 0x00001500
1843 #define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 24
1844 #define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 0x01000000U
1849 #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL
1850 #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT
1851 #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK
1852 #define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 0x00001500
1853 #define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 8
1854 #define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1859 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL
1860 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT
1861 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK
1862 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 0x01002300
1863 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16
1864 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1869 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL
1870 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT
1871 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK
1872 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 0x01002300
1873 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8
1874 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1877 * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T
1878 * his signal may only be toggled after 4 cycles of the old clock and 4 cyc
1879 * les of the new clock. This is not usually an issue, but designers must b
1882 #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL
1883 #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT
1884 #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK
1885 #define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 0x01002300
1886 #define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 0
1887 #define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007U
1890 * Clock active signal. Switch to 0 to disable the clock
1892 #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL
1893 #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT
1894 #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK
1895 #define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 0x01002300
1896 #define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 24
1897 #define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000U
1902 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL
1903 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT
1904 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK
1905 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 0x01032300
1906 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 16
1907 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1912 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL
1913 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT
1914 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK
1915 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 0x01032300
1916 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 8
1917 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1920 * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T
1921 * his signal may only be toggled after 4 cycles of the old clock and 4 cyc
1922 * les of the new clock. This is not usually an issue, but designers must b
1925 #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL
1926 #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT
1927 #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK
1928 #define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 0x01032300
1929 #define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 0
1930 #define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 0x00000007U
1933 * Clock active signal. Switch to 0 to disable the clock
1935 #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL
1936 #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT
1937 #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK
1938 #define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 0x01032300
1939 #define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 24
1940 #define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 0x01000000U
1945 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL
1946 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT
1947 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK
1948 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 0x01203200
1949 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 16
1950 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1955 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL
1956 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT
1957 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK
1958 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 0x01203200
1959 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 8
1960 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1963 * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg
1964 * led after 4 cycles of the old clock and 4 cycles of the new clock. This
1965 * is not usually an issue, but designers must be aware.)
1967 #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL
1968 #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT
1969 #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK
1970 #define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 0x01203200
1971 #define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 0
1972 #define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 0x00000007U
1975 * Clock active signal. Switch to 0 to disable the clock
1977 #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL
1978 #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT
1979 #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK
1980 #define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 0x01203200
1981 #define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 24
1982 #define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 0x01000000U
1987 #undef CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL
1988 #undef CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT
1989 #undef CRF_APB_ACPU_CTRL_DIVISOR0_MASK
1990 #define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 0x03000400
1991 #define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 8
1992 #define CRF_APB_ACPU_CTRL_DIVISOR0_MASK 0x00003F00U
1995 * 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft
1996 * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
1997 * usually an issue, but designers must be aware.)
1999 #undef CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL
2000 #undef CRF_APB_ACPU_CTRL_SRCSEL_SHIFT
2001 #undef CRF_APB_ACPU_CTRL_SRCSEL_MASK
2002 #define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 0x03000400
2003 #define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 0
2004 #define CRF_APB_ACPU_CTRL_SRCSEL_MASK 0x00000007U
2007 * Clock active signal. Switch to 0 to disable the clock. For the half spee
2010 #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL
2011 #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT
2012 #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK
2013 #define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 0x03000400
2014 #define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 25
2015 #define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 0x02000000U
2018 * Clock active signal. Switch to 0 to disable the clock. For the full spee
2019 * d ACPUX Clock. This will shut off the high speed clock to the entire APU
2021 #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL
2022 #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT
2023 #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK
2024 #define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 0x03000400
2025 #define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 24
2026 #define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 0x01000000U
2031 #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL
2032 #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT
2033 #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK
2034 #define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 0x01002500
2035 #define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 8
2036 #define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 0x00003F00U
2039 * 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog
2040 * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
2041 * is not usually an issue, but designers must be aware.)
2043 #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL
2044 #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT
2045 #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK
2046 #define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 0x01002500
2047 #define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 0
2048 #define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 0x00000007U
2051 * Clock active signal. Switch to 0 to disable the clock
2053 #undef CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL
2054 #undef CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT
2055 #undef CRF_APB_DBG_FPD_CTRL_CLKACT_MASK
2056 #define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 0x01002500
2057 #define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 24
2058 #define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 0x01000000U
2063 #undef CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL
2064 #undef CRF_APB_DDR_CTRL_DIVISOR0_SHIFT
2065 #undef CRF_APB_DDR_CTRL_DIVISOR0_MASK
2066 #define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 0x01000500
2067 #define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 8
2068 #define CRF_APB_DDR_CTRL_DIVISOR0_MASK 0x00003F00U
2071 * 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles
2072 * of the old clock and 4 cycles of the new clock. This is not usually an i
2073 * ssue, but designers must be aware.)
2075 #undef CRF_APB_DDR_CTRL_SRCSEL_DEFVAL
2076 #undef CRF_APB_DDR_CTRL_SRCSEL_SHIFT
2077 #undef CRF_APB_DDR_CTRL_SRCSEL_MASK
2078 #define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 0x01000500
2079 #define CRF_APB_DDR_CTRL_SRCSEL_SHIFT 0
2080 #define CRF_APB_DDR_CTRL_SRCSEL_MASK 0x00000007U
2085 #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL
2086 #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT
2087 #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK
2088 #define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 0x00001500
2089 #define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 8
2090 #define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 0x00003F00U
2093 * 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog
2094 * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
2095 * is not usually an issue, but designers must be aware.)
2097 #undef CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL
2098 #undef CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT
2099 #undef CRF_APB_GPU_REF_CTRL_SRCSEL_MASK
2100 #define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 0x00001500
2101 #define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 0
2102 #define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 0x00000007U
2105 * Clock active signal. Switch to 0 to disable the clock, which will stop c
2106 * lock for GPU (and both Pixel Processors).
2108 #undef CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL
2109 #undef CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT
2110 #undef CRF_APB_GPU_REF_CTRL_CLKACT_MASK
2111 #define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 0x00001500
2112 #define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 24
2113 #define CRF_APB_GPU_REF_CTRL_CLKACT_MASK 0x01000000U
2116 * Clock active signal for Pixel Processor. Switch to 0 to disable the cloc
2117 * k only to this Pixel Processor
2119 #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL
2120 #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT
2121 #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK
2122 #define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 0x00001500
2123 #define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 25
2124 #define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 0x02000000U
2127 * Clock active signal for Pixel Processor. Switch to 0 to disable the cloc
2128 * k only to this Pixel Processor
2130 #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL
2131 #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT
2132 #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK
2133 #define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 0x00001500
2134 #define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 26
2135 #define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 0x04000000U
2140 #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL
2141 #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT
2142 #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK
2143 #define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500
2144 #define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 8
2145 #define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U
2148 * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
2149 * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
2150 * usually an issue, but designers must be aware.)
2152 #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL
2153 #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT
2154 #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK
2155 #define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500
2156 #define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 0
2157 #define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 0x00000007U
2160 * Clock active signal. Switch to 0 to disable the clock
2162 #undef CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL
2163 #undef CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT
2164 #undef CRF_APB_GDMA_REF_CTRL_CLKACT_MASK
2165 #define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500
2166 #define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 24
2167 #define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 0x01000000U
2172 #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL
2173 #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT
2174 #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK
2175 #define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500
2176 #define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 8
2177 #define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U
2180 * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
2181 * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
2182 * usually an issue, but designers must be aware.)
2184 #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL
2185 #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT
2186 #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK
2187 #define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500
2188 #define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 0
2189 #define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 0x00000007U
2192 * Clock active signal. Switch to 0 to disable the clock
2194 #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL
2195 #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT
2196 #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK
2197 #define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500
2198 #define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 24
2199 #define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 0x01000000U
2204 #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL
2205 #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT
2206 #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK
2207 #define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 0x01000400
2208 #define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 8
2209 #define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 0x00003F00U
2212 * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
2213 * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
2214 * usually an issue, but designers must be aware.)
2216 #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL
2217 #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT
2218 #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK
2219 #define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 0x01000400
2220 #define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 0
2221 #define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 0x00000007U
2224 * Clock active signal. Switch to 0 to disable the clock
2226 #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL
2227 #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT
2228 #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK
2229 #define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 0x01000400
2230 #define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 24
2231 #define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 0x01000000U
2236 #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL
2237 #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT
2238 #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK
2239 #define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01000800
2240 #define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 8
2241 #define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U
2244 * 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog
2245 * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
2246 * is not usually an issue, but designers must be aware.)
2248 #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL
2249 #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT
2250 #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK
2251 #define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 0x01000800
2252 #define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 0
2253 #define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 0x00000007U
2256 * Clock active signal. Switch to 0 to disable the clock
2258 #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL
2259 #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT
2260 #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK
2261 #define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 0x01000800
2262 #define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 24
2263 #define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 0x01000000U
2268 #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL
2269 #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT
2270 #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK
2271 #define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 0x00000A00
2272 #define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 8
2273 #define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 0x00003F00U
2276 * 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog
2277 * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
2278 * is not usually an issue, but designers must be aware.)
2280 #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL
2281 #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT
2282 #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK
2283 #define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 0x00000A00
2284 #define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 0
2285 #define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 0x00000007U
2288 * 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se
2289 * lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5
2290 * clock for the APB interface of TTC0
2292 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL
2293 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT
2294 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK
2295 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL 0x00000000
2296 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT 0
2297 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK 0x00000003U
2300 * 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se
2301 * lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5
2302 * clock for the APB interface of TTC1
2304 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL
2305 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT
2306 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK
2307 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL 0x00000000
2308 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT 2
2309 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK 0x0000000CU
2312 * 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se
2313 * lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5
2314 * clock for the APB interface of TTC2
2316 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL
2317 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT
2318 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK
2319 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL 0x00000000
2320 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT 4
2321 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK 0x00000030U
2324 * 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se
2325 * lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5
2326 * clock for the APB interface of TTC3
2328 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL
2329 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT
2330 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK
2331 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL 0x00000000
2332 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT 6
2333 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK 0x000000C0U
2336 * System watchdog timer clock source selection: 0: Internal APB clock 1: E
2337 * xternal (PL clock via EMIO or Pinout clock via MIO)
2339 #undef FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL
2340 #undef FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT
2341 #undef FPD_SLCR_WDT_CLK_SEL_SELECT_MASK
2342 #define FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000
2343 #define FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0
2344 #define FPD_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U
2347 * System watchdog timer clock source selection: 0: internal clock APB cloc
2348 * k 1: external clock from PL via EMIO, or from pinout via MIO
2350 #undef IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL
2351 #undef IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT
2352 #undef IOU_SLCR_WDT_CLK_SEL_SELECT_MASK
2353 #define IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000
2354 #define IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0
2355 #define IOU_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U
2358 * System watchdog timer clock source selection: 0: internal clock APB cloc
2359 * k 1: external clock pss_ref_clk
2361 #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL
2362 #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT
2363 #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK
2364 #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000
2365 #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 0
2366 #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK 0x00000001U
2367 #undef CRF_APB_RST_DDR_SS_OFFSET
2368 #define CRF_APB_RST_DDR_SS_OFFSET 0XFD1A0108
2369 #undef DDRC_MSTR_OFFSET
2370 #define DDRC_MSTR_OFFSET 0XFD070000
2371 #undef DDRC_MRCTRL0_OFFSET
2372 #define DDRC_MRCTRL0_OFFSET 0XFD070010
2373 #undef DDRC_DERATEEN_OFFSET
2374 #define DDRC_DERATEEN_OFFSET 0XFD070020
2375 #undef DDRC_DERATEINT_OFFSET
2376 #define DDRC_DERATEINT_OFFSET 0XFD070024
2377 #undef DDRC_PWRCTL_OFFSET
2378 #define DDRC_PWRCTL_OFFSET 0XFD070030
2379 #undef DDRC_PWRTMG_OFFSET
2380 #define DDRC_PWRTMG_OFFSET 0XFD070034
2381 #undef DDRC_RFSHCTL0_OFFSET
2382 #define DDRC_RFSHCTL0_OFFSET 0XFD070050
2383 #undef DDRC_RFSHCTL1_OFFSET
2384 #define DDRC_RFSHCTL1_OFFSET 0XFD070054
2385 #undef DDRC_RFSHCTL3_OFFSET
2386 #define DDRC_RFSHCTL3_OFFSET 0XFD070060
2387 #undef DDRC_RFSHTMG_OFFSET
2388 #define DDRC_RFSHTMG_OFFSET 0XFD070064
2389 #undef DDRC_ECCCFG0_OFFSET
2390 #define DDRC_ECCCFG0_OFFSET 0XFD070070
2391 #undef DDRC_ECCCFG1_OFFSET
2392 #define DDRC_ECCCFG1_OFFSET 0XFD070074
2393 #undef DDRC_CRCPARCTL1_OFFSET
2394 #define DDRC_CRCPARCTL1_OFFSET 0XFD0700C4
2395 #undef DDRC_CRCPARCTL2_OFFSET
2396 #define DDRC_CRCPARCTL2_OFFSET 0XFD0700C8
2397 #undef DDRC_INIT0_OFFSET
2398 #define DDRC_INIT0_OFFSET 0XFD0700D0
2399 #undef DDRC_INIT1_OFFSET
2400 #define DDRC_INIT1_OFFSET 0XFD0700D4
2401 #undef DDRC_INIT2_OFFSET
2402 #define DDRC_INIT2_OFFSET 0XFD0700D8
2403 #undef DDRC_INIT3_OFFSET
2404 #define DDRC_INIT3_OFFSET 0XFD0700DC
2405 #undef DDRC_INIT4_OFFSET
2406 #define DDRC_INIT4_OFFSET 0XFD0700E0
2407 #undef DDRC_INIT5_OFFSET
2408 #define DDRC_INIT5_OFFSET 0XFD0700E4
2409 #undef DDRC_INIT6_OFFSET
2410 #define DDRC_INIT6_OFFSET 0XFD0700E8
2411 #undef DDRC_INIT7_OFFSET
2412 #define DDRC_INIT7_OFFSET 0XFD0700EC
2413 #undef DDRC_DIMMCTL_OFFSET
2414 #define DDRC_DIMMCTL_OFFSET 0XFD0700F0
2415 #undef DDRC_RANKCTL_OFFSET
2416 #define DDRC_RANKCTL_OFFSET 0XFD0700F4
2417 #undef DDRC_DRAMTMG0_OFFSET
2418 #define DDRC_DRAMTMG0_OFFSET 0XFD070100
2419 #undef DDRC_DRAMTMG1_OFFSET
2420 #define DDRC_DRAMTMG1_OFFSET 0XFD070104
2421 #undef DDRC_DRAMTMG2_OFFSET
2422 #define DDRC_DRAMTMG2_OFFSET 0XFD070108
2423 #undef DDRC_DRAMTMG3_OFFSET
2424 #define DDRC_DRAMTMG3_OFFSET 0XFD07010C
2425 #undef DDRC_DRAMTMG4_OFFSET
2426 #define DDRC_DRAMTMG4_OFFSET 0XFD070110
2427 #undef DDRC_DRAMTMG5_OFFSET
2428 #define DDRC_DRAMTMG5_OFFSET 0XFD070114
2429 #undef DDRC_DRAMTMG6_OFFSET
2430 #define DDRC_DRAMTMG6_OFFSET 0XFD070118
2431 #undef DDRC_DRAMTMG7_OFFSET
2432 #define DDRC_DRAMTMG7_OFFSET 0XFD07011C
2433 #undef DDRC_DRAMTMG8_OFFSET
2434 #define DDRC_DRAMTMG8_OFFSET 0XFD070120
2435 #undef DDRC_DRAMTMG9_OFFSET
2436 #define DDRC_DRAMTMG9_OFFSET 0XFD070124
2437 #undef DDRC_DRAMTMG11_OFFSET
2438 #define DDRC_DRAMTMG11_OFFSET 0XFD07012C
2439 #undef DDRC_DRAMTMG12_OFFSET
2440 #define DDRC_DRAMTMG12_OFFSET 0XFD070130
2441 #undef DDRC_ZQCTL0_OFFSET
2442 #define DDRC_ZQCTL0_OFFSET 0XFD070180
2443 #undef DDRC_ZQCTL1_OFFSET
2444 #define DDRC_ZQCTL1_OFFSET 0XFD070184
2445 #undef DDRC_DFITMG0_OFFSET
2446 #define DDRC_DFITMG0_OFFSET 0XFD070190
2447 #undef DDRC_DFITMG1_OFFSET
2448 #define DDRC_DFITMG1_OFFSET 0XFD070194
2449 #undef DDRC_DFILPCFG0_OFFSET
2450 #define DDRC_DFILPCFG0_OFFSET 0XFD070198
2451 #undef DDRC_DFILPCFG1_OFFSET
2452 #define DDRC_DFILPCFG1_OFFSET 0XFD07019C
2453 #undef DDRC_DFIUPD0_OFFSET
2454 #define DDRC_DFIUPD0_OFFSET 0XFD0701A0
2455 #undef DDRC_DFIUPD1_OFFSET
2456 #define DDRC_DFIUPD1_OFFSET 0XFD0701A4
2457 #undef DDRC_DFIMISC_OFFSET
2458 #define DDRC_DFIMISC_OFFSET 0XFD0701B0
2459 #undef DDRC_DFITMG2_OFFSET
2460 #define DDRC_DFITMG2_OFFSET 0XFD0701B4
2461 #undef DDRC_DBICTL_OFFSET
2462 #define DDRC_DBICTL_OFFSET 0XFD0701C0
2463 #undef DDRC_ADDRMAP0_OFFSET
2464 #define DDRC_ADDRMAP0_OFFSET 0XFD070200
2465 #undef DDRC_ADDRMAP1_OFFSET
2466 #define DDRC_ADDRMAP1_OFFSET 0XFD070204
2467 #undef DDRC_ADDRMAP2_OFFSET
2468 #define DDRC_ADDRMAP2_OFFSET 0XFD070208
2469 #undef DDRC_ADDRMAP3_OFFSET
2470 #define DDRC_ADDRMAP3_OFFSET 0XFD07020C
2471 #undef DDRC_ADDRMAP4_OFFSET
2472 #define DDRC_ADDRMAP4_OFFSET 0XFD070210
2473 #undef DDRC_ADDRMAP5_OFFSET
2474 #define DDRC_ADDRMAP5_OFFSET 0XFD070214
2475 #undef DDRC_ADDRMAP6_OFFSET
2476 #define DDRC_ADDRMAP6_OFFSET 0XFD070218
2477 #undef DDRC_ADDRMAP7_OFFSET
2478 #define DDRC_ADDRMAP7_OFFSET 0XFD07021C
2479 #undef DDRC_ADDRMAP8_OFFSET
2480 #define DDRC_ADDRMAP8_OFFSET 0XFD070220
2481 #undef DDRC_ADDRMAP9_OFFSET
2482 #define DDRC_ADDRMAP9_OFFSET 0XFD070224
2483 #undef DDRC_ADDRMAP10_OFFSET
2484 #define DDRC_ADDRMAP10_OFFSET 0XFD070228
2485 #undef DDRC_ADDRMAP11_OFFSET
2486 #define DDRC_ADDRMAP11_OFFSET 0XFD07022C
2487 #undef DDRC_ODTCFG_OFFSET
2488 #define DDRC_ODTCFG_OFFSET 0XFD070240
2489 #undef DDRC_ODTMAP_OFFSET
2490 #define DDRC_ODTMAP_OFFSET 0XFD070244
2491 #undef DDRC_SCHED_OFFSET
2492 #define DDRC_SCHED_OFFSET 0XFD070250
2493 #undef DDRC_PERFLPR1_OFFSET
2494 #define DDRC_PERFLPR1_OFFSET 0XFD070264
2495 #undef DDRC_PERFWR1_OFFSET
2496 #define DDRC_PERFWR1_OFFSET 0XFD07026C
2497 #undef DDRC_DQMAP0_OFFSET
2498 #define DDRC_DQMAP0_OFFSET 0XFD070280
2499 #undef DDRC_DQMAP1_OFFSET
2500 #define DDRC_DQMAP1_OFFSET 0XFD070284
2501 #undef DDRC_DQMAP2_OFFSET
2502 #define DDRC_DQMAP2_OFFSET 0XFD070288
2503 #undef DDRC_DQMAP3_OFFSET
2504 #define DDRC_DQMAP3_OFFSET 0XFD07028C
2505 #undef DDRC_DQMAP4_OFFSET
2506 #define DDRC_DQMAP4_OFFSET 0XFD070290
2507 #undef DDRC_DQMAP5_OFFSET
2508 #define DDRC_DQMAP5_OFFSET 0XFD070294
2509 #undef DDRC_DBG0_OFFSET
2510 #define DDRC_DBG0_OFFSET 0XFD070300
2511 #undef DDRC_DBGCMD_OFFSET
2512 #define DDRC_DBGCMD_OFFSET 0XFD07030C
2513 #undef DDRC_SWCTL_OFFSET
2514 #define DDRC_SWCTL_OFFSET 0XFD070320
2515 #undef DDRC_PCCFG_OFFSET
2516 #define DDRC_PCCFG_OFFSET 0XFD070400
2517 #undef DDRC_PCFGR_0_OFFSET
2518 #define DDRC_PCFGR_0_OFFSET 0XFD070404
2519 #undef DDRC_PCFGW_0_OFFSET
2520 #define DDRC_PCFGW_0_OFFSET 0XFD070408
2521 #undef DDRC_PCTRL_0_OFFSET
2522 #define DDRC_PCTRL_0_OFFSET 0XFD070490
2523 #undef DDRC_PCFGQOS0_0_OFFSET
2524 #define DDRC_PCFGQOS0_0_OFFSET 0XFD070494
2525 #undef DDRC_PCFGQOS1_0_OFFSET
2526 #define DDRC_PCFGQOS1_0_OFFSET 0XFD070498
2527 #undef DDRC_PCFGR_1_OFFSET
2528 #define DDRC_PCFGR_1_OFFSET 0XFD0704B4
2529 #undef DDRC_PCFGW_1_OFFSET
2530 #define DDRC_PCFGW_1_OFFSET 0XFD0704B8
2531 #undef DDRC_PCTRL_1_OFFSET
2532 #define DDRC_PCTRL_1_OFFSET 0XFD070540
2533 #undef DDRC_PCFGQOS0_1_OFFSET
2534 #define DDRC_PCFGQOS0_1_OFFSET 0XFD070544
2535 #undef DDRC_PCFGQOS1_1_OFFSET
2536 #define DDRC_PCFGQOS1_1_OFFSET 0XFD070548
2537 #undef DDRC_PCFGR_2_OFFSET
2538 #define DDRC_PCFGR_2_OFFSET 0XFD070564
2539 #undef DDRC_PCFGW_2_OFFSET
2540 #define DDRC_PCFGW_2_OFFSET 0XFD070568
2541 #undef DDRC_PCTRL_2_OFFSET
2542 #define DDRC_PCTRL_2_OFFSET 0XFD0705F0
2543 #undef DDRC_PCFGQOS0_2_OFFSET
2544 #define DDRC_PCFGQOS0_2_OFFSET 0XFD0705F4
2545 #undef DDRC_PCFGQOS1_2_OFFSET
2546 #define DDRC_PCFGQOS1_2_OFFSET 0XFD0705F8
2547 #undef DDRC_PCFGR_3_OFFSET
2548 #define DDRC_PCFGR_3_OFFSET 0XFD070614
2549 #undef DDRC_PCFGW_3_OFFSET
2550 #define DDRC_PCFGW_3_OFFSET 0XFD070618
2551 #undef DDRC_PCTRL_3_OFFSET
2552 #define DDRC_PCTRL_3_OFFSET 0XFD0706A0
2553 #undef DDRC_PCFGQOS0_3_OFFSET
2554 #define DDRC_PCFGQOS0_3_OFFSET 0XFD0706A4
2555 #undef DDRC_PCFGQOS1_3_OFFSET
2556 #define DDRC_PCFGQOS1_3_OFFSET 0XFD0706A8
2557 #undef DDRC_PCFGWQOS0_3_OFFSET
2558 #define DDRC_PCFGWQOS0_3_OFFSET 0XFD0706AC
2559 #undef DDRC_PCFGWQOS1_3_OFFSET
2560 #define DDRC_PCFGWQOS1_3_OFFSET 0XFD0706B0
2561 #undef DDRC_PCFGR_4_OFFSET
2562 #define DDRC_PCFGR_4_OFFSET 0XFD0706C4
2563 #undef DDRC_PCFGW_4_OFFSET
2564 #define DDRC_PCFGW_4_OFFSET 0XFD0706C8
2565 #undef DDRC_PCTRL_4_OFFSET
2566 #define DDRC_PCTRL_4_OFFSET 0XFD070750
2567 #undef DDRC_PCFGQOS0_4_OFFSET
2568 #define DDRC_PCFGQOS0_4_OFFSET 0XFD070754
2569 #undef DDRC_PCFGQOS1_4_OFFSET
2570 #define DDRC_PCFGQOS1_4_OFFSET 0XFD070758
2571 #undef DDRC_PCFGWQOS0_4_OFFSET
2572 #define DDRC_PCFGWQOS0_4_OFFSET 0XFD07075C
2573 #undef DDRC_PCFGWQOS1_4_OFFSET
2574 #define DDRC_PCFGWQOS1_4_OFFSET 0XFD070760
2575 #undef DDRC_PCFGR_5_OFFSET
2576 #define DDRC_PCFGR_5_OFFSET 0XFD070774
2577 #undef DDRC_PCFGW_5_OFFSET
2578 #define DDRC_PCFGW_5_OFFSET 0XFD070778
2579 #undef DDRC_PCTRL_5_OFFSET
2580 #define DDRC_PCTRL_5_OFFSET 0XFD070800
2581 #undef DDRC_PCFGQOS0_5_OFFSET
2582 #define DDRC_PCFGQOS0_5_OFFSET 0XFD070804
2583 #undef DDRC_PCFGQOS1_5_OFFSET
2584 #define DDRC_PCFGQOS1_5_OFFSET 0XFD070808
2585 #undef DDRC_PCFGWQOS0_5_OFFSET
2586 #define DDRC_PCFGWQOS0_5_OFFSET 0XFD07080C
2587 #undef DDRC_PCFGWQOS1_5_OFFSET
2588 #define DDRC_PCFGWQOS1_5_OFFSET 0XFD070810
2589 #undef DDRC_SARBASE0_OFFSET
2590 #define DDRC_SARBASE0_OFFSET 0XFD070F04
2591 #undef DDRC_SARSIZE0_OFFSET
2592 #define DDRC_SARSIZE0_OFFSET 0XFD070F08
2593 #undef DDRC_SARBASE1_OFFSET
2594 #define DDRC_SARBASE1_OFFSET 0XFD070F0C
2595 #undef DDRC_SARSIZE1_OFFSET
2596 #define DDRC_SARSIZE1_OFFSET 0XFD070F10
2597 #undef DDRC_DFITMG0_SHADOW_OFFSET
2598 #define DDRC_DFITMG0_SHADOW_OFFSET 0XFD072190
2599 #undef CRF_APB_RST_DDR_SS_OFFSET
2600 #define CRF_APB_RST_DDR_SS_OFFSET 0XFD1A0108
2601 #undef DDR_PHY_PGCR0_OFFSET
2602 #define DDR_PHY_PGCR0_OFFSET 0XFD080010
2603 #undef DDR_PHY_PGCR2_OFFSET
2604 #define DDR_PHY_PGCR2_OFFSET 0XFD080018
2605 #undef DDR_PHY_PGCR3_OFFSET
2606 #define DDR_PHY_PGCR3_OFFSET 0XFD08001C
2607 #undef DDR_PHY_PGCR5_OFFSET
2608 #define DDR_PHY_PGCR5_OFFSET 0XFD080024
2609 #undef DDR_PHY_PTR0_OFFSET
2610 #define DDR_PHY_PTR0_OFFSET 0XFD080040
2611 #undef DDR_PHY_PTR1_OFFSET
2612 #define DDR_PHY_PTR1_OFFSET 0XFD080044
2613 #undef DDR_PHY_PLLCR0_OFFSET
2614 #define DDR_PHY_PLLCR0_OFFSET 0XFD080068
2615 #undef DDR_PHY_DSGCR_OFFSET
2616 #define DDR_PHY_DSGCR_OFFSET 0XFD080090
2617 #undef DDR_PHY_GPR0_OFFSET
2618 #define DDR_PHY_GPR0_OFFSET 0XFD0800C0
2619 #undef DDR_PHY_DCR_OFFSET
2620 #define DDR_PHY_DCR_OFFSET 0XFD080100
2621 #undef DDR_PHY_DTPR0_OFFSET
2622 #define DDR_PHY_DTPR0_OFFSET 0XFD080110
2623 #undef DDR_PHY_DTPR1_OFFSET
2624 #define DDR_PHY_DTPR1_OFFSET 0XFD080114
2625 #undef DDR_PHY_DTPR2_OFFSET
2626 #define DDR_PHY_DTPR2_OFFSET 0XFD080118
2627 #undef DDR_PHY_DTPR3_OFFSET
2628 #define DDR_PHY_DTPR3_OFFSET 0XFD08011C
2629 #undef DDR_PHY_DTPR4_OFFSET
2630 #define DDR_PHY_DTPR4_OFFSET 0XFD080120
2631 #undef DDR_PHY_DTPR5_OFFSET
2632 #define DDR_PHY_DTPR5_OFFSET 0XFD080124
2633 #undef DDR_PHY_DTPR6_OFFSET
2634 #define DDR_PHY_DTPR6_OFFSET 0XFD080128
2635 #undef DDR_PHY_RDIMMGCR0_OFFSET
2636 #define DDR_PHY_RDIMMGCR0_OFFSET 0XFD080140
2637 #undef DDR_PHY_RDIMMGCR1_OFFSET
2638 #define DDR_PHY_RDIMMGCR1_OFFSET 0XFD080144
2639 #undef DDR_PHY_RDIMMCR0_OFFSET
2640 #define DDR_PHY_RDIMMCR0_OFFSET 0XFD080150
2641 #undef DDR_PHY_RDIMMCR1_OFFSET
2642 #define DDR_PHY_RDIMMCR1_OFFSET 0XFD080154
2643 #undef DDR_PHY_MR0_OFFSET
2644 #define DDR_PHY_MR0_OFFSET 0XFD080180
2645 #undef DDR_PHY_MR1_OFFSET
2646 #define DDR_PHY_MR1_OFFSET 0XFD080184
2647 #undef DDR_PHY_MR2_OFFSET
2648 #define DDR_PHY_MR2_OFFSET 0XFD080188
2649 #undef DDR_PHY_MR3_OFFSET
2650 #define DDR_PHY_MR3_OFFSET 0XFD08018C
2651 #undef DDR_PHY_MR4_OFFSET
2652 #define DDR_PHY_MR4_OFFSET 0XFD080190
2653 #undef DDR_PHY_MR5_OFFSET
2654 #define DDR_PHY_MR5_OFFSET 0XFD080194
2655 #undef DDR_PHY_MR6_OFFSET
2656 #define DDR_PHY_MR6_OFFSET 0XFD080198
2657 #undef DDR_PHY_MR11_OFFSET
2658 #define DDR_PHY_MR11_OFFSET 0XFD0801AC
2659 #undef DDR_PHY_MR12_OFFSET
2660 #define DDR_PHY_MR12_OFFSET 0XFD0801B0
2661 #undef DDR_PHY_MR13_OFFSET
2662 #define DDR_PHY_MR13_OFFSET 0XFD0801B4
2663 #undef DDR_PHY_MR14_OFFSET
2664 #define DDR_PHY_MR14_OFFSET 0XFD0801B8
2665 #undef DDR_PHY_MR22_OFFSET
2666 #define DDR_PHY_MR22_OFFSET 0XFD0801D8
2667 #undef DDR_PHY_DTCR0_OFFSET
2668 #define DDR_PHY_DTCR0_OFFSET 0XFD080200
2669 #undef DDR_PHY_DTCR1_OFFSET
2670 #define DDR_PHY_DTCR1_OFFSET 0XFD080204
2671 #undef DDR_PHY_CATR0_OFFSET
2672 #define DDR_PHY_CATR0_OFFSET 0XFD080240
2673 #undef DDR_PHY_DQSDR0_OFFSET
2674 #define DDR_PHY_DQSDR0_OFFSET 0XFD080250
2675 #undef DDR_PHY_BISTLSR_OFFSET
2676 #define DDR_PHY_BISTLSR_OFFSET 0XFD080414
2677 #undef DDR_PHY_RIOCR5_OFFSET
2678 #define DDR_PHY_RIOCR5_OFFSET 0XFD0804F4
2679 #undef DDR_PHY_ACIOCR0_OFFSET
2680 #define DDR_PHY_ACIOCR0_OFFSET 0XFD080500
2681 #undef DDR_PHY_ACIOCR2_OFFSET
2682 #define DDR_PHY_ACIOCR2_OFFSET 0XFD080508
2683 #undef DDR_PHY_ACIOCR3_OFFSET
2684 #define DDR_PHY_ACIOCR3_OFFSET 0XFD08050C
2685 #undef DDR_PHY_ACIOCR4_OFFSET
2686 #define DDR_PHY_ACIOCR4_OFFSET 0XFD080510
2687 #undef DDR_PHY_IOVCR0_OFFSET
2688 #define DDR_PHY_IOVCR0_OFFSET 0XFD080520
2689 #undef DDR_PHY_VTCR0_OFFSET
2690 #define DDR_PHY_VTCR0_OFFSET 0XFD080528
2691 #undef DDR_PHY_VTCR1_OFFSET
2692 #define DDR_PHY_VTCR1_OFFSET 0XFD08052C
2693 #undef DDR_PHY_ACBDLR1_OFFSET
2694 #define DDR_PHY_ACBDLR1_OFFSET 0XFD080544
2695 #undef DDR_PHY_ACBDLR2_OFFSET
2696 #define DDR_PHY_ACBDLR2_OFFSET 0XFD080548
2697 #undef DDR_PHY_ACBDLR6_OFFSET
2698 #define DDR_PHY_ACBDLR6_OFFSET 0XFD080558
2699 #undef DDR_PHY_ACBDLR7_OFFSET
2700 #define DDR_PHY_ACBDLR7_OFFSET 0XFD08055C
2701 #undef DDR_PHY_ACBDLR8_OFFSET
2702 #define DDR_PHY_ACBDLR8_OFFSET 0XFD080560
2703 #undef DDR_PHY_ACBDLR9_OFFSET
2704 #define DDR_PHY_ACBDLR9_OFFSET 0XFD080564
2705 #undef DDR_PHY_ZQCR_OFFSET
2706 #define DDR_PHY_ZQCR_OFFSET 0XFD080680
2707 #undef DDR_PHY_ZQ0PR0_OFFSET
2708 #define DDR_PHY_ZQ0PR0_OFFSET 0XFD080684
2709 #undef DDR_PHY_ZQ0OR0_OFFSET
2710 #define DDR_PHY_ZQ0OR0_OFFSET 0XFD080694
2711 #undef DDR_PHY_ZQ0OR1_OFFSET
2712 #define DDR_PHY_ZQ0OR1_OFFSET 0XFD080698
2713 #undef DDR_PHY_ZQ1PR0_OFFSET
2714 #define DDR_PHY_ZQ1PR0_OFFSET 0XFD0806A4
2715 #undef DDR_PHY_DX0GCR0_OFFSET
2716 #define DDR_PHY_DX0GCR0_OFFSET 0XFD080700
2717 #undef DDR_PHY_DX0GCR4_OFFSET
2718 #define DDR_PHY_DX0GCR4_OFFSET 0XFD080710
2719 #undef DDR_PHY_DX0GCR5_OFFSET
2720 #define DDR_PHY_DX0GCR5_OFFSET 0XFD080714
2721 #undef DDR_PHY_DX0GCR6_OFFSET
2722 #define DDR_PHY_DX0GCR6_OFFSET 0XFD080718
2723 #undef DDR_PHY_DX1GCR0_OFFSET
2724 #define DDR_PHY_DX1GCR0_OFFSET 0XFD080800
2725 #undef DDR_PHY_DX1GCR4_OFFSET
2726 #define DDR_PHY_DX1GCR4_OFFSET 0XFD080810
2727 #undef DDR_PHY_DX1GCR5_OFFSET
2728 #define DDR_PHY_DX1GCR5_OFFSET 0XFD080814
2729 #undef DDR_PHY_DX1GCR6_OFFSET
2730 #define DDR_PHY_DX1GCR6_OFFSET 0XFD080818
2731 #undef DDR_PHY_DX2GCR0_OFFSET
2732 #define DDR_PHY_DX2GCR0_OFFSET 0XFD080900
2733 #undef DDR_PHY_DX2GCR1_OFFSET
2734 #define DDR_PHY_DX2GCR1_OFFSET 0XFD080904
2735 #undef DDR_PHY_DX2GCR4_OFFSET
2736 #define DDR_PHY_DX2GCR4_OFFSET 0XFD080910
2737 #undef DDR_PHY_DX2GCR5_OFFSET
2738 #define DDR_PHY_DX2GCR5_OFFSET 0XFD080914
2739 #undef DDR_PHY_DX2GCR6_OFFSET
2740 #define DDR_PHY_DX2GCR6_OFFSET 0XFD080918
2741 #undef DDR_PHY_DX3GCR0_OFFSET
2742 #define DDR_PHY_DX3GCR0_OFFSET 0XFD080A00
2743 #undef DDR_PHY_DX3GCR1_OFFSET
2744 #define DDR_PHY_DX3GCR1_OFFSET 0XFD080A04
2745 #undef DDR_PHY_DX3GCR4_OFFSET
2746 #define DDR_PHY_DX3GCR4_OFFSET 0XFD080A10
2747 #undef DDR_PHY_DX3GCR5_OFFSET
2748 #define DDR_PHY_DX3GCR5_OFFSET 0XFD080A14
2749 #undef DDR_PHY_DX3GCR6_OFFSET
2750 #define DDR_PHY_DX3GCR6_OFFSET 0XFD080A18
2751 #undef DDR_PHY_DX4GCR0_OFFSET
2752 #define DDR_PHY_DX4GCR0_OFFSET 0XFD080B00
2753 #undef DDR_PHY_DX4GCR1_OFFSET
2754 #define DDR_PHY_DX4GCR1_OFFSET 0XFD080B04
2755 #undef DDR_PHY_DX4GCR4_OFFSET
2756 #define DDR_PHY_DX4GCR4_OFFSET 0XFD080B10
2757 #undef DDR_PHY_DX4GCR5_OFFSET
2758 #define DDR_PHY_DX4GCR5_OFFSET 0XFD080B14
2759 #undef DDR_PHY_DX4GCR6_OFFSET
2760 #define DDR_PHY_DX4GCR6_OFFSET 0XFD080B18
2761 #undef DDR_PHY_DX5GCR0_OFFSET
2762 #define DDR_PHY_DX5GCR0_OFFSET 0XFD080C00
2763 #undef DDR_PHY_DX5GCR1_OFFSET
2764 #define DDR_PHY_DX5GCR1_OFFSET 0XFD080C04
2765 #undef DDR_PHY_DX5GCR4_OFFSET
2766 #define DDR_PHY_DX5GCR4_OFFSET 0XFD080C10
2767 #undef DDR_PHY_DX5GCR5_OFFSET
2768 #define DDR_PHY_DX5GCR5_OFFSET 0XFD080C14
2769 #undef DDR_PHY_DX5GCR6_OFFSET
2770 #define DDR_PHY_DX5GCR6_OFFSET 0XFD080C18
2771 #undef DDR_PHY_DX6GCR0_OFFSET
2772 #define DDR_PHY_DX6GCR0_OFFSET 0XFD080D00
2773 #undef DDR_PHY_DX6GCR1_OFFSET
2774 #define DDR_PHY_DX6GCR1_OFFSET 0XFD080D04
2775 #undef DDR_PHY_DX6GCR4_OFFSET
2776 #define DDR_PHY_DX6GCR4_OFFSET 0XFD080D10
2777 #undef DDR_PHY_DX6GCR5_OFFSET
2778 #define DDR_PHY_DX6GCR5_OFFSET 0XFD080D14
2779 #undef DDR_PHY_DX6GCR6_OFFSET
2780 #define DDR_PHY_DX6GCR6_OFFSET 0XFD080D18
2781 #undef DDR_PHY_DX7GCR0_OFFSET
2782 #define DDR_PHY_DX7GCR0_OFFSET 0XFD080E00
2783 #undef DDR_PHY_DX7GCR1_OFFSET
2784 #define DDR_PHY_DX7GCR1_OFFSET 0XFD080E04
2785 #undef DDR_PHY_DX7GCR4_OFFSET
2786 #define DDR_PHY_DX7GCR4_OFFSET 0XFD080E10
2787 #undef DDR_PHY_DX7GCR5_OFFSET
2788 #define DDR_PHY_DX7GCR5_OFFSET 0XFD080E14
2789 #undef DDR_PHY_DX7GCR6_OFFSET
2790 #define DDR_PHY_DX7GCR6_OFFSET 0XFD080E18
2791 #undef DDR_PHY_DX8GCR0_OFFSET
2792 #define DDR_PHY_DX8GCR0_OFFSET 0XFD080F00
2793 #undef DDR_PHY_DX8GCR1_OFFSET
2794 #define DDR_PHY_DX8GCR1_OFFSET 0XFD080F04
2795 #undef DDR_PHY_DX8GCR4_OFFSET
2796 #define DDR_PHY_DX8GCR4_OFFSET 0XFD080F10
2797 #undef DDR_PHY_DX8GCR5_OFFSET
2798 #define DDR_PHY_DX8GCR5_OFFSET 0XFD080F14
2799 #undef DDR_PHY_DX8GCR6_OFFSET
2800 #define DDR_PHY_DX8GCR6_OFFSET 0XFD080F18
2801 #undef DDR_PHY_DX8SL0OSC_OFFSET
2802 #define DDR_PHY_DX8SL0OSC_OFFSET 0XFD081400
2803 #undef DDR_PHY_DX8SL0PLLCR0_OFFSET
2804 #define DDR_PHY_DX8SL0PLLCR0_OFFSET 0XFD081404
2805 #undef DDR_PHY_DX8SL0DQSCTL_OFFSET
2806 #define DDR_PHY_DX8SL0DQSCTL_OFFSET 0XFD08141C
2807 #undef DDR_PHY_DX8SL0DXCTL2_OFFSET
2808 #define DDR_PHY_DX8SL0DXCTL2_OFFSET 0XFD08142C
2809 #undef DDR_PHY_DX8SL0IOCR_OFFSET
2810 #define DDR_PHY_DX8SL0IOCR_OFFSET 0XFD081430
2811 #undef DDR_PHY_DX8SL1OSC_OFFSET
2812 #define DDR_PHY_DX8SL1OSC_OFFSET 0XFD081440
2813 #undef DDR_PHY_DX8SL1PLLCR0_OFFSET
2814 #define DDR_PHY_DX8SL1PLLCR0_OFFSET 0XFD081444
2815 #undef DDR_PHY_DX8SL1DQSCTL_OFFSET
2816 #define DDR_PHY_DX8SL1DQSCTL_OFFSET 0XFD08145C
2817 #undef DDR_PHY_DX8SL1DXCTL2_OFFSET
2818 #define DDR_PHY_DX8SL1DXCTL2_OFFSET 0XFD08146C
2819 #undef DDR_PHY_DX8SL1IOCR_OFFSET
2820 #define DDR_PHY_DX8SL1IOCR_OFFSET 0XFD081470
2821 #undef DDR_PHY_DX8SL2OSC_OFFSET
2822 #define DDR_PHY_DX8SL2OSC_OFFSET 0XFD081480
2823 #undef DDR_PHY_DX8SL2PLLCR0_OFFSET
2824 #define DDR_PHY_DX8SL2PLLCR0_OFFSET 0XFD081484
2825 #undef DDR_PHY_DX8SL2DQSCTL_OFFSET
2826 #define DDR_PHY_DX8SL2DQSCTL_OFFSET 0XFD08149C
2827 #undef DDR_PHY_DX8SL2DXCTL2_OFFSET
2828 #define DDR_PHY_DX8SL2DXCTL2_OFFSET 0XFD0814AC
2829 #undef DDR_PHY_DX8SL2IOCR_OFFSET
2830 #define DDR_PHY_DX8SL2IOCR_OFFSET 0XFD0814B0
2831 #undef DDR_PHY_DX8SL3OSC_OFFSET
2832 #define DDR_PHY_DX8SL3OSC_OFFSET 0XFD0814C0
2833 #undef DDR_PHY_DX8SL3PLLCR0_OFFSET
2834 #define DDR_PHY_DX8SL3PLLCR0_OFFSET 0XFD0814C4
2835 #undef DDR_PHY_DX8SL3DQSCTL_OFFSET
2836 #define DDR_PHY_DX8SL3DQSCTL_OFFSET 0XFD0814DC
2837 #undef DDR_PHY_DX8SL3DXCTL2_OFFSET
2838 #define DDR_PHY_DX8SL3DXCTL2_OFFSET 0XFD0814EC
2839 #undef DDR_PHY_DX8SL3IOCR_OFFSET
2840 #define DDR_PHY_DX8SL3IOCR_OFFSET 0XFD0814F0
2841 #undef DDR_PHY_DX8SL4OSC_OFFSET
2842 #define DDR_PHY_DX8SL4OSC_OFFSET 0XFD081500
2843 #undef DDR_PHY_DX8SL4PLLCR0_OFFSET
2844 #define DDR_PHY_DX8SL4PLLCR0_OFFSET 0XFD081504
2845 #undef DDR_PHY_DX8SL4DQSCTL_OFFSET
2846 #define DDR_PHY_DX8SL4DQSCTL_OFFSET 0XFD08151C
2847 #undef DDR_PHY_DX8SL4DXCTL2_OFFSET
2848 #define DDR_PHY_DX8SL4DXCTL2_OFFSET 0XFD08152C
2849 #undef DDR_PHY_DX8SL4IOCR_OFFSET
2850 #define DDR_PHY_DX8SL4IOCR_OFFSET 0XFD081530
2851 #undef DDR_PHY_DX8SLBPLLCR0_OFFSET
2852 #define DDR_PHY_DX8SLBPLLCR0_OFFSET 0XFD0817C4
2853 #undef DDR_PHY_DX8SLBDQSCTL_OFFSET
2854 #define DDR_PHY_DX8SLBDQSCTL_OFFSET 0XFD0817DC
2857 * DDR block level reset inside of the DDR Sub System
2859 #undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL
2860 #undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT
2861 #undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK
2862 #define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F
2863 #define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3
2864 #define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U
2867 * Indicates the configuration of the device used in the system. - 00 - x4
2868 * device - 01 - x8 device - 10 - x16 device - 11 - x32 device
2870 #undef DDRC_MSTR_DEVICE_CONFIG_DEFVAL
2871 #undef DDRC_MSTR_DEVICE_CONFIG_SHIFT
2872 #undef DDRC_MSTR_DEVICE_CONFIG_MASK
2873 #define DDRC_MSTR_DEVICE_CONFIG_DEFVAL 0x03040001
2874 #define DDRC_MSTR_DEVICE_CONFIG_SHIFT 30
2875 #define DDRC_MSTR_DEVICE_CONFIG_MASK 0xC0000000U
2878 * Choose which registers are used. - 0 - Original registers - 1 - Shadow r
2881 #undef DDRC_MSTR_FREQUENCY_MODE_DEFVAL
2882 #undef DDRC_MSTR_FREQUENCY_MODE_SHIFT
2883 #undef DDRC_MSTR_FREQUENCY_MODE_MASK
2884 #define DDRC_MSTR_FREQUENCY_MODE_DEFVAL 0x03040001
2885 #define DDRC_MSTR_FREQUENCY_MODE_SHIFT 29
2886 #define DDRC_MSTR_FREQUENCY_MODE_MASK 0x20000000U
2889 * Only present for multi-rank configurations. Each bit represents one rank
2890 * . For two-rank configurations, only bits[25:24] are present. - 1 - popul
2891 * ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow
2892 * ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others -
2893 * Reserved. For 4 ranks following combinations are legal: - 0001 - One ran
2894 * k - 0011 - Two ranks - 1111 - Four ranks
2896 #undef DDRC_MSTR_ACTIVE_RANKS_DEFVAL
2897 #undef DDRC_MSTR_ACTIVE_RANKS_SHIFT
2898 #undef DDRC_MSTR_ACTIVE_RANKS_MASK
2899 #define DDRC_MSTR_ACTIVE_RANKS_DEFVAL 0x03040001
2900 #define DDRC_MSTR_ACTIVE_RANKS_SHIFT 24
2901 #define DDRC_MSTR_ACTIVE_RANKS_MASK 0x03000000U
2904 * SDRAM burst length used: - 0001 - Burst length of 2 (only supported for
2905 * mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur
2906 * st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other
2907 * values are reserved. This controls the burst size used to access the SDR
2908 * AM. This must match the burst length mode register setting in the SDRAM.
2909 * (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100)
2910 * Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH
2911 * is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1
2913 #undef DDRC_MSTR_BURST_RDWR_DEFVAL
2914 #undef DDRC_MSTR_BURST_RDWR_SHIFT
2915 #undef DDRC_MSTR_BURST_RDWR_MASK
2916 #define DDRC_MSTR_BURST_RDWR_DEFVAL 0x03040001
2917 #define DDRC_MSTR_BURST_RDWR_SHIFT 16
2918 #define DDRC_MSTR_BURST_RDWR_MASK 0x000F0000U
2921 * Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low
2922 * frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for
2923 * normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC
2924 * TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi
2925 * s bit must be set to '0'.
2927 #undef DDRC_MSTR_DLL_OFF_MODE_DEFVAL
2928 #undef DDRC_MSTR_DLL_OFF_MODE_SHIFT
2929 #undef DDRC_MSTR_DLL_OFF_MODE_MASK
2930 #define DDRC_MSTR_DLL_OFF_MODE_DEFVAL 0x03040001
2931 #define DDRC_MSTR_DLL_OFF_MODE_SHIFT 15
2932 #define DDRC_MSTR_DLL_OFF_MODE_MASK 0x00008000U
2935 * Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full
2936 * DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter
2937 * DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is
2938 * only supported when the SDRAM bus width is a multiple of 16, and quarter
2939 * bus width mode is only supported when the SDRAM bus width is a multiple
2940 * of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid
2941 * th refers to DQ bus width (excluding any ECC width).
2943 #undef DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL
2944 #undef DDRC_MSTR_DATA_BUS_WIDTH_SHIFT
2945 #undef DDRC_MSTR_DATA_BUS_WIDTH_MASK
2946 #define DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL 0x03040001
2947 #define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 12
2948 #define DDRC_MSTR_DATA_BUS_WIDTH_MASK 0x00003000U
2951 * 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D
2952 * RAM in normal mode (1N). This register can be changed, only when the Con
2953 * troller is in self-refresh mode. This signal must be set the same value
2954 * as MR3 bit A3. Note: Geardown mode is not supported if the configuration
2955 * parameter MEMC_CMD_RTN2IDLE is set
2957 #undef DDRC_MSTR_GEARDOWN_MODE_DEFVAL
2958 #undef DDRC_MSTR_GEARDOWN_MODE_SHIFT
2959 #undef DDRC_MSTR_GEARDOWN_MODE_MASK
2960 #define DDRC_MSTR_GEARDOWN_MODE_DEFVAL 0x03040001
2961 #define DDRC_MSTR_GEARDOWN_MODE_SHIFT 11
2962 #define DDRC_MSTR_GEARDOWN_MODE_MASK 0x00000800U
2965 * If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin
2966 * g, all command signals (except chip select) are held for 2 clocks on the
2967 * SDRAM bus. Chip select is asserted on the second cycle of the command N
2968 * ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti
2969 * ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i
2970 * s set Note: 2T timing is not supported in DDR4 geardown mode.
2972 #undef DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL
2973 #undef DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT
2974 #undef DDRC_MSTR_EN_2T_TIMING_MODE_MASK
2975 #define DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL 0x03040001
2976 #define DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT 10
2977 #define DDRC_MSTR_EN_2T_TIMING_MODE_MASK 0x00000400U
2980 * When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci
2981 * sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full
2982 * bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer
2983 * cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is
2984 * disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl
2985 * ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported
2986 * , and this bit must be set to '0'
2988 #undef DDRC_MSTR_BURSTCHOP_DEFVAL
2989 #undef DDRC_MSTR_BURSTCHOP_SHIFT
2990 #undef DDRC_MSTR_BURSTCHOP_MASK
2991 #define DDRC_MSTR_BURSTCHOP_DEFVAL 0x03040001
2992 #define DDRC_MSTR_BURSTCHOP_SHIFT 9
2993 #define DDRC_MSTR_BURSTCHOP_MASK 0x00000200U
2996 * Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d
2997 * evice in use Present only in designs configured to support LPDDR4.
2999 #undef DDRC_MSTR_LPDDR4_DEFVAL
3000 #undef DDRC_MSTR_LPDDR4_SHIFT
3001 #undef DDRC_MSTR_LPDDR4_MASK
3002 #define DDRC_MSTR_LPDDR4_DEFVAL 0x03040001
3003 #define DDRC_MSTR_LPDDR4_SHIFT 5
3004 #define DDRC_MSTR_LPDDR4_MASK 0x00000020U
3007 * Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device
3008 * in use Present only in designs configured to support DDR4.
3010 #undef DDRC_MSTR_DDR4_DEFVAL
3011 #undef DDRC_MSTR_DDR4_SHIFT
3012 #undef DDRC_MSTR_DDR4_MASK
3013 #define DDRC_MSTR_DDR4_DEFVAL 0x03040001
3014 #define DDRC_MSTR_DDR4_SHIFT 4
3015 #define DDRC_MSTR_DDR4_MASK 0x00000010U
3018 * Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d
3019 * evice in use Present only in designs configured to support LPDDR3.
3021 #undef DDRC_MSTR_LPDDR3_DEFVAL
3022 #undef DDRC_MSTR_LPDDR3_SHIFT
3023 #undef DDRC_MSTR_LPDDR3_MASK
3024 #define DDRC_MSTR_LPDDR3_DEFVAL 0x03040001
3025 #define DDRC_MSTR_LPDDR3_SHIFT 3
3026 #define DDRC_MSTR_LPDDR3_MASK 0x00000008U
3029 * Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d
3030 * evice in use Present only in designs configured to support LPDDR2.
3032 #undef DDRC_MSTR_LPDDR2_DEFVAL
3033 #undef DDRC_MSTR_LPDDR2_SHIFT
3034 #undef DDRC_MSTR_LPDDR2_MASK
3035 #define DDRC_MSTR_LPDDR2_DEFVAL 0x03040001
3036 #define DDRC_MSTR_LPDDR2_SHIFT 2
3037 #define DDRC_MSTR_LPDDR2_MASK 0x00000004U
3040 * Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de
3041 * vice in use Only present in designs that support DDR3.
3043 #undef DDRC_MSTR_DDR3_DEFVAL
3044 #undef DDRC_MSTR_DDR3_SHIFT
3045 #undef DDRC_MSTR_DDR3_MASK
3046 #define DDRC_MSTR_DDR3_DEFVAL 0x03040001
3047 #define DDRC_MSTR_DDR3_SHIFT 0
3048 #define DDRC_MSTR_DDR3_MASK 0x00000001U
3051 * Setting this register bit to 1 triggers a mode register read or write op
3052 * eration. When the MR operation is complete, the uMCTL2 automatically cle
3053 * ars this bit. The other register fields of this register must be written
3054 * in a separate APB transaction, before setting this mr_wr bit. It is rec
3055 * ommended NOT to set this signal if in Init, Deep power-down or MPSM oper
3058 #undef DDRC_MRCTRL0_MR_WR_DEFVAL
3059 #undef DDRC_MRCTRL0_MR_WR_SHIFT
3060 #undef DDRC_MRCTRL0_MR_WR_MASK
3061 #define DDRC_MRCTRL0_MR_WR_DEFVAL 0x00000030
3062 #define DDRC_MRCTRL0_MR_WR_SHIFT 31
3063 #define DDRC_MRCTRL0_MR_WR_MASK 0x80000000U
3066 * Address of the mode register that is to be written to. - 0000 - MR0 - 00
3067 * 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR
3068 * 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data
3069 * for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als
3070 * o used for writing to control words of RDIMMs. In that case, it correspo
3071 * nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[
3072 * 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a
3073 * s the bit[2:0] must be set to an appropriate value which is considered b
3074 * oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R
3077 #undef DDRC_MRCTRL0_MR_ADDR_DEFVAL
3078 #undef DDRC_MRCTRL0_MR_ADDR_SHIFT
3079 #undef DDRC_MRCTRL0_MR_ADDR_MASK
3080 #define DDRC_MRCTRL0_MR_ADDR_DEFVAL 0x00000030
3081 #define DDRC_MRCTRL0_MR_ADDR_SHIFT 12
3082 #define DDRC_MRCTRL0_MR_ADDR_MASK 0x0000F000U
3085 * Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire
3086 * d to access all ranks, so all bits should be set to 1. However, for mult
3087 * i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess
3088 * ary to access ranks individually. Examples (assume uMCTL2 is configured
3089 * for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x
3090 * 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran
3093 #undef DDRC_MRCTRL0_MR_RANK_DEFVAL
3094 #undef DDRC_MRCTRL0_MR_RANK_SHIFT
3095 #undef DDRC_MRCTRL0_MR_RANK_MASK
3096 #define DDRC_MRCTRL0_MR_RANK_DEFVAL 0x00000030
3097 #define DDRC_MRCTRL0_MR_RANK_SHIFT 4
3098 #define DDRC_MRCTRL0_MR_RANK_MASK 0x00000030U
3101 * Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b
3102 * efore automatic SDRAM initialization routine or not. For DDR4, this bit
3103 * can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init
3104 * ialization. For LPDDR4, this bit can be used to program additional mode
3105 * registers before automatic SDRAM initialization if necessary. Note: This
3106 * must be cleared to 0 after completing Software operation. Otherwise, SD
3107 * RAM initialization routine will not re-start. - 0 - Software interventio
3108 * n is not allowed - 1 - Software intervention is allowed
3110 #undef DDRC_MRCTRL0_SW_INIT_INT_DEFVAL
3111 #undef DDRC_MRCTRL0_SW_INIT_INT_SHIFT
3112 #undef DDRC_MRCTRL0_SW_INIT_INT_MASK
3113 #define DDRC_MRCTRL0_SW_INIT_INT_DEFVAL 0x00000030
3114 #define DDRC_MRCTRL0_SW_INIT_INT_SHIFT 3
3115 #define DDRC_MRCTRL0_SW_INIT_INT_MASK 0x00000008U
3118 * Indicates whether the mode register operation is MRS in PDA mode or not
3119 * - 0 - MRS - 1 - MRS in Per DRAM Addressability mode
3121 #undef DDRC_MRCTRL0_PDA_EN_DEFVAL
3122 #undef DDRC_MRCTRL0_PDA_EN_SHIFT
3123 #undef DDRC_MRCTRL0_PDA_EN_MASK
3124 #define DDRC_MRCTRL0_PDA_EN_DEFVAL 0x00000030
3125 #define DDRC_MRCTRL0_PDA_EN_SHIFT 2
3126 #define DDRC_MRCTRL0_PDA_EN_MASK 0x00000004U
3129 * Indicates whether the mode register operation is MRS or WR/RD for MPR (o
3130 * nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR
3132 #undef DDRC_MRCTRL0_MPR_EN_DEFVAL
3133 #undef DDRC_MRCTRL0_MPR_EN_SHIFT
3134 #undef DDRC_MRCTRL0_MPR_EN_MASK
3135 #define DDRC_MRCTRL0_MPR_EN_DEFVAL 0x00000030
3136 #define DDRC_MRCTRL0_MPR_EN_SHIFT 1
3137 #define DDRC_MRCTRL0_MPR_EN_MASK 0x00000002U
3140 * Indicates whether the mode register operation is read or write. Only use
3141 * d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read
3143 #undef DDRC_MRCTRL0_MR_TYPE_DEFVAL
3144 #undef DDRC_MRCTRL0_MR_TYPE_SHIFT
3145 #undef DDRC_MRCTRL0_MR_TYPE_MASK
3146 #define DDRC_MRCTRL0_MR_TYPE_DEFVAL 0x00000030
3147 #define DDRC_MRCTRL0_MR_TYPE_SHIFT 0
3148 #define DDRC_MRCTRL0_MR_TYPE_MASK 0x00000001U
3151 * Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us
3152 * es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d
3153 * esigns configured to support LPDDR4. The required number of cycles for d
3154 * erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p
3155 * eriod, and rounding up the next integer.
3157 #undef DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL
3158 #undef DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT
3159 #undef DDRC_DERATEEN_RC_DERATE_VALUE_MASK
3160 #define DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL 0x00000000
3161 #define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT 8
3162 #define DDRC_DERATEEN_RC_DERATE_VALUE_MASK 0x00000300U
3165 * Derate byte Present only in designs configured to support LPDDR2/LPDDR3/
3166 * LPDDR4 Indicates which byte of the MRR data is used for derating. The ma
3167 * ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.
3169 #undef DDRC_DERATEEN_DERATE_BYTE_DEFVAL
3170 #undef DDRC_DERATEEN_DERATE_BYTE_SHIFT
3171 #undef DDRC_DERATEEN_DERATE_BYTE_MASK
3172 #define DDRC_DERATEEN_DERATE_BYTE_DEFVAL 0x00000000
3173 #define DDRC_DERATEEN_DERATE_BYTE_SHIFT 4
3174 #define DDRC_DERATEEN_DERATE_BYTE_MASK 0x000000F0U
3177 * Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl
3178 * y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all
3179 * LPDDR2 speed grades as derating value of +1.875 ns is less than a core_
3180 * ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8
3181 * 75 ns is less than a core_ddrc_core_clk period or not.
3183 #undef DDRC_DERATEEN_DERATE_VALUE_DEFVAL
3184 #undef DDRC_DERATEEN_DERATE_VALUE_SHIFT
3185 #undef DDRC_DERATEEN_DERATE_VALUE_MASK
3186 #define DDRC_DERATEEN_DERATE_VALUE_DEFVAL 0x00000000
3187 #define DDRC_DERATEEN_DERATE_VALUE_SHIFT 1
3188 #define DDRC_DERATEEN_DERATE_VALUE_MASK 0x00000002U
3191 * Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin
3192 * g parameter derating is enabled using MR4 read value. Present only in de
3193 * signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set
3194 * to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
3196 #undef DDRC_DERATEEN_DERATE_ENABLE_DEFVAL
3197 #undef DDRC_DERATEEN_DERATE_ENABLE_SHIFT
3198 #undef DDRC_DERATEEN_DERATE_ENABLE_MASK
3199 #define DDRC_DERATEEN_DERATE_ENABLE_DEFVAL 0x00000000
3200 #define DDRC_DERATEEN_DERATE_ENABLE_SHIFT 0
3201 #define DDRC_DERATEEN_DERATE_ENABLE_MASK 0x00000001U
3204 * Interval between two MR4 reads, used to derate the timing parameters. Pr
3205 * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r
3206 * egister must not be set to zero
3208 #undef DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL
3209 #undef DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT
3210 #undef DDRC_DERATEINT_MR4_READ_INTERVAL_MASK
3211 #define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL
3212 #define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 0
3213 #define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 0xFFFFFFFFU
3216 * Self refresh state is an intermediate state to enter to Self refresh pow
3217 * er down state or exit Self refresh power down state for LPDDR4. This reg
3218 * ister controls transition from the Self refresh state. - 1 - Prohibit tr
3219 * ansition from Self refresh state - 0 - Allow transition from Self refres
3222 #undef DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL
3223 #undef DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT
3224 #undef DDRC_PWRCTL_STAY_IN_SELFREF_MASK
3225 #define DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL 0x00000000
3226 #define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT 6
3227 #define DDRC_PWRCTL_STAY_IN_SELFREF_MASK 0x00000040U
3230 * A value of 1 to this register causes system to move to Self Refresh stat
3231 * e immediately, as long as it is not in INIT or DPD/MPSM operating_mode.
3232 * This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa
3233 * re Entry to Self Refresh - 0 - Software Exit from Self Refresh
3235 #undef DDRC_PWRCTL_SELFREF_SW_DEFVAL
3236 #undef DDRC_PWRCTL_SELFREF_SW_SHIFT
3237 #undef DDRC_PWRCTL_SELFREF_SW_MASK
3238 #define DDRC_PWRCTL_SELFREF_SW_DEFVAL 0x00000000
3239 #define DDRC_PWRCTL_SELFREF_SW_SHIFT 5
3240 #define DDRC_PWRCTL_SELFREF_SW_MASK 0x00000020U
3243 * When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode
3244 * when the transaction store is empty. This register must be reset to '0'
3245 * to bring uMCTL2 out of maximum power saving mode. Present only in desig
3246 * ns configured to support DDR4. For non-DDR4, this register should not be
3247 * set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if
3248 * the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r
3249 * equires the chip-select signal to toggle. FOR PERFORMANCE ONLY.
3251 #undef DDRC_PWRCTL_MPSM_EN_DEFVAL
3252 #undef DDRC_PWRCTL_MPSM_EN_SHIFT
3253 #undef DDRC_PWRCTL_MPSM_EN_MASK
3254 #define DDRC_PWRCTL_MPSM_EN_DEFVAL 0x00000000
3255 #define DDRC_PWRCTL_MPSM_EN_SHIFT 4
3256 #define DDRC_PWRCTL_MPSM_EN_MASK 0x00000010U
3259 * Enable the assertion of dfi_dram_clk_disable whenever a clock is not req
3260 * uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted.
3261 * Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only
3262 * be asserted in Self Refresh. In DDR4, can be asserted in following: - i
3263 * n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca
3264 * n be asserted in following: - in Self Refresh - in Power Down - in Deep
3265 * Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse
3266 * rted in following: - in Self Refresh Power Down - in Power Down - during
3267 * Normal operation (Clock Stop)
3269 #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL
3270 #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT
3271 #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK
3272 #define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL 0x00000000
3273 #define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 3
3274 #define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 0x00000008U
3277 * When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the
3278 * transaction store is empty. This register must be reset to '0' to bring
3279 * uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM
3280 * initialization on deep power-down exit. Present only in designs configu
3281 * red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD
3282 * DR3, this register should not be set to 1. FOR PERFORMANCE ONLY.
3284 #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL
3285 #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT
3286 #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK
3287 #define DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL 0x00000000
3288 #define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT 2
3289 #define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK 0x00000004U
3292 * If true then the uMCTL2 goes into power-down after a programmable number
3293 * of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_
3294 * x32). This register bit may be re-programmed during the course of normal
3297 #undef DDRC_PWRCTL_POWERDOWN_EN_DEFVAL
3298 #undef DDRC_PWRCTL_POWERDOWN_EN_SHIFT
3299 #undef DDRC_PWRCTL_POWERDOWN_EN_MASK
3300 #define DDRC_PWRCTL_POWERDOWN_EN_DEFVAL 0x00000000
3301 #define DDRC_PWRCTL_POWERDOWN_EN_SHIFT 1
3302 #define DDRC_PWRCTL_POWERDOWN_EN_MASK 0x00000002U
3305 * If true then the uMCTL2 puts the SDRAM into Self Refresh after a program
3306 * mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG.
3307 * selfref_to_x32)'. This register bit may be re-programmed during the cour
3308 * se of normal operation.
3310 #undef DDRC_PWRCTL_SELFREF_EN_DEFVAL
3311 #undef DDRC_PWRCTL_SELFREF_EN_SHIFT
3312 #undef DDRC_PWRCTL_SELFREF_EN_MASK
3313 #define DDRC_PWRCTL_SELFREF_EN_DEFVAL 0x00000000
3314 #define DDRC_PWRCTL_SELFREF_EN_SHIFT 0
3315 #define DDRC_PWRCTL_SELFREF_EN_MASK 0x00000001U
3318 * After this many clocks of NOP or deselect the uMCTL2 automatically puts
3319 * the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_
3320 * en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
3322 #undef DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL
3323 #undef DDRC_PWRTMG_SELFREF_TO_X32_SHIFT
3324 #undef DDRC_PWRTMG_SELFREF_TO_X32_MASK
3325 #define DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL 0x00402010
3326 #define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT 16
3327 #define DDRC_PWRTMG_SELFREF_TO_X32_MASK 0x00FF0000U
3330 * Minimum deep power-down time. For mDDR, value from the JEDEC specificati
3331 * on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL
3332 * .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE
3333 * C specification is 500us. Unit: Multiples of 4096 clocks. Present only i
3334 * n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE
3337 #undef DDRC_PWRTMG_T_DPD_X4096_DEFVAL
3338 #undef DDRC_PWRTMG_T_DPD_X4096_SHIFT
3339 #undef DDRC_PWRTMG_T_DPD_X4096_MASK
3340 #define DDRC_PWRTMG_T_DPD_X4096_DEFVAL 0x00402010
3341 #define DDRC_PWRTMG_T_DPD_X4096_SHIFT 8
3342 #define DDRC_PWRTMG_T_DPD_X4096_MASK 0x0000FF00U
3345 * After this many clocks of NOP or deselect the uMCTL2 automatically puts
3346 * the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_
3347 * en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.
3349 #undef DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL
3350 #undef DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT
3351 #undef DDRC_PWRTMG_POWERDOWN_TO_X32_MASK
3352 #define DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL 0x00402010
3353 #define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT 0
3354 #define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK 0x0000001FU
3357 * Threshold value in number of clock cycles before the critical refresh or
3358 * page timer expires. A critical refresh is to be issued before this thre
3359 * shold is reached. It is recommended that this not be changed from the de
3360 * fault value, currently shown as 0x2. It must always be less than interna
3361 * lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u
3362 * sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i
3363 * s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n
3364 * om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo
3367 #undef DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL
3368 #undef DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT
3369 #undef DDRC_RFSHCTL0_REFRESH_MARGIN_MASK
3370 #define DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL 0x00210000
3371 #define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT 20
3372 #define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK 0x00F00000U
3375 * If the refresh timer (tRFCnom, also known as tREFI) has expired at least
3376 * once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then
3377 * a speculative refresh may be performed. A speculative refresh is a refr
3378 * esh performed at a time when refresh would be useful, but before it is a
3379 * bsolutely required. When the SDRAM bus is idle for a period of time dete
3380 * rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired
3381 * at least once since the last refresh, then a speculative refresh is per
3382 * formed. Speculative refreshes continues successively until there are no
3383 * refreshes pending or until new reads or writes are issued to the uMCTL2.
3384 * FOR PERFORMANCE ONLY.
3386 #undef DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL
3387 #undef DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT
3388 #undef DDRC_RFSHCTL0_REFRESH_TO_X32_MASK
3389 #define DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL 0x00210000
3390 #define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT 12
3391 #define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK 0x0001F000U
3394 * The programmed value + 1 is the number of refresh timeouts that is allow
3395 * ed to accumulate before traffic is blocked and the refreshes are forced
3396 * to execute. Closing pages to perform a refresh is a one-time penalty tha
3397 * t must be paid for each group of refreshes. Therefore, performing refres
3398 * hes in a burst reduces the per-refresh penalty of these page closings. H
3399 * igher numbers for RFSHCTL.refresh_burst slightly increases utilization;
3400 * lower numbers decreases the worst-case latency associated with refreshes
3401 * . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh
3402 * For information on burst refresh feature refer to section 3.9 of DDR2 J
3403 * EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe
3404 * r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF
3405 * I cycles using the burst refresh feature. In DDR4 mode, according to Fin
3406 * e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre
3407 * shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda
3408 * tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens
3409 * ure that tRFCmax is not violated due to a PHY-initiated update occurring
3410 * shortly before a refresh burst was due. In this situation, the refresh
3411 * burst will be delayed until the PHY-initiated update is complete.
3413 #undef DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL
3414 #undef DDRC_RFSHCTL0_REFRESH_BURST_SHIFT
3415 #undef DDRC_RFSHCTL0_REFRESH_BURST_MASK
3416 #define DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL 0x00210000
3417 #define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT 4
3418 #define DDRC_RFSHCTL0_REFRESH_BURST_MASK 0x000001F0U
3421 * - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows
3422 * traffic to flow to other banks. Per bank refresh is not supported by all
3423 * LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr
3424 * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4
3426 #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL
3427 #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT
3428 #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK
3429 #define DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL 0x00210000
3430 #define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT 2
3431 #define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK 0x00000004U
3434 * Refresh timer start for rank 1 (only present in multi-rank configuration
3435 * s). This is useful in staggering the refreshes to multiple ranks to help
3436 * traffic to proceed. This is explained in Refresh Controls section of ar
3437 * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
3439 #undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL
3440 #undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT
3441 #undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK
3442 #define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL 0x00000000
3443 #define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT 16
3444 #define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK 0x0FFF0000U
3447 * Refresh timer start for rank 0 (only present in multi-rank configuration
3448 * s). This is useful in staggering the refreshes to multiple ranks to help
3449 * traffic to proceed. This is explained in Refresh Controls section of ar
3450 * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
3452 #undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL
3453 #undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT
3454 #undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK
3455 #define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL 0x00000000
3456 #define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT 0
3457 #define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK 0x00000FFFU
3460 * Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix
3461 * ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11
3462 * 0 - Enable on the fly 4x (not supported) - Everything else - reserved No
3463 * te: The on-the-fly modes is not supported in this version of the uMCTL2.
3464 * Note: This must be set up while the Controller is in reset or while the
3465 * Controller is in self-refresh mode. Changing this during normal operati
3466 * on is not allowed. Making this a dynamic register will be supported in f
3467 * uture version of the uMCTL2.
3469 #undef DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL
3470 #undef DDRC_RFSHCTL3_REFRESH_MODE_SHIFT
3471 #undef DDRC_RFSHCTL3_REFRESH_MODE_MASK
3472 #define DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL 0x00000000
3473 #define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT 4
3474 #define DDRC_RFSHCTL3_REFRESH_MODE_MASK 0x00000070U
3477 * Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that
3478 * the refresh register(s) have been updated. The value is automatically up
3479 * dated when exiting reset, so it does not need to be toggled initially.
3481 #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL
3482 #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT
3483 #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK
3484 #define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL 0x00000000
3485 #define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 1
3486 #define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK 0x00000002U
3489 * When '1', disable auto-refresh generated by the uMCTL2. When auto-refres
3490 * h is disabled, the SoC core must generate refreshes using the registers
3491 * reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a
3492 * nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1
3493 * , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4
3494 * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d
3495 * isable auto-refresh is not supported, and this bit must be set to '0'. T
3496 * his register field is changeable on the fly.
3498 #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL
3499 #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT
3500 #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK
3501 #define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL 0x00000000
3502 #define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT 0
3503 #define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK 0x00000001U
3506 * tREFI: Average time interval between refreshes per rank (Specification:
3507 * 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2,
3508 * LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre
3509 * shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE
3510 * FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this
3511 * register should be set to tREFIpb For configurations with MEMC_FREQ_RAT
3512 * IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val
3513 * ue is different depending on the refresh mode. The user should program t
3514 * he appropriate value from the spec based on the value programmed in the
3515 * refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea
3516 * ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th
3517 * an 0x1. Unit: Multiples of 32 clocks.
3519 #undef DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL
3520 #undef DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT
3521 #undef DDRC_RFSHTMG_T_RFC_NOM_X32_MASK
3522 #define DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL 0x0062008C
3523 #define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 16
3524 #define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK 0x0FFF0000U
3527 * Used only when LPDDR3 memory type is connected. Should only be changed w
3528 * hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r
3529 * equired by some LPDDR3 devices which comply with earlier versions of the
3530 * LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1
3531 * - tREFBW parameter used
3533 #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL
3534 #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT
3535 #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK
3536 #define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL 0x0062008C
3537 #define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT 15
3538 #define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK 0x00008000U
3541 * tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F
3542 * REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t
3543 * CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro
3544 * undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using
3545 * all-bank refreshes, the tRFCmin value in the above equations is equal to
3546 * tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq
3547 * uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above
3548 * equations is different depending on the refresh mode (fixed 1X,2X,4X) an
3549 * d the device density. The user should program the appropriate value from
3550 * the spec based on the 'refresh_mode' and the device density that is use
3553 #undef DDRC_RFSHTMG_T_RFC_MIN_DEFVAL
3554 #undef DDRC_RFSHTMG_T_RFC_MIN_SHIFT
3555 #undef DDRC_RFSHTMG_T_RFC_MIN_MASK
3556 #define DDRC_RFSHTMG_T_RFC_MIN_DEFVAL 0x0062008C
3557 #define DDRC_RFSHTMG_T_RFC_MIN_SHIFT 0
3558 #define DDRC_RFSHTMG_T_RFC_MIN_MASK 0x000003FFU
3561 * Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U
3564 #undef DDRC_ECCCFG0_DIS_SCRUB_DEFVAL
3565 #undef DDRC_ECCCFG0_DIS_SCRUB_SHIFT
3566 #undef DDRC_ECCCFG0_DIS_SCRUB_MASK
3567 #define DDRC_ECCCFG0_DIS_SCRUB_DEFVAL 0x00000000
3568 #define DDRC_ECCCFG0_DIS_SCRUB_SHIFT 4
3569 #define DDRC_ECCCFG0_DIS_SCRUB_MASK 0x00000010U
3572 * ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov
3573 * er 1 beat - all other settings are reserved for future use
3575 #undef DDRC_ECCCFG0_ECC_MODE_DEFVAL
3576 #undef DDRC_ECCCFG0_ECC_MODE_SHIFT
3577 #undef DDRC_ECCCFG0_ECC_MODE_MASK
3578 #define DDRC_ECCCFG0_ECC_MODE_DEFVAL 0x00000000
3579 #define DDRC_ECCCFG0_ECC_MODE_SHIFT 0
3580 #define DDRC_ECCCFG0_ECC_MODE_MASK 0x00000007U
3583 * Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da
3584 * ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat
3587 #undef DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL
3588 #undef DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT
3589 #undef DDRC_ECCCFG1_DATA_POISON_BIT_MASK
3590 #define DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL 0x00000000
3591 #define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT 1
3592 #define DDRC_ECCCFG1_DATA_POISON_BIT_MASK 0x00000002U
3595 * Enable ECC data poisoning - introduces ECC errors on writes to address s
3596 * pecified by the ECCPOISONADDR0/1 registers
3598 #undef DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL
3599 #undef DDRC_ECCCFG1_DATA_POISON_EN_SHIFT
3600 #undef DDRC_ECCCFG1_DATA_POISON_EN_MASK
3601 #define DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL 0x00000000
3602 #define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT 0
3603 #define DDRC_ECCCFG1_DATA_POISON_EN_MASK 0x00000001U
3606 * The maximum number of DFI PHY clock cycles allowed from the assertion of
3607 * the dfi_rddata_en signal to the assertion of each of the corresponding
3608 * bits of the dfi_rddata_valid signal. This corresponds to the DFI timing
3609 * parameter tphy_rdlat. Refer to PHY specification for correct value. This
3610 * value it only used for detecting read data timeout when DDR4 retry is e
3611 * nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value:
3612 * - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r
3613 * dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1
3614 * : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d
3615 * fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_
3616 * rdlat < 'd114 Unit: DFI Clocks
3618 #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL
3619 #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT
3620 #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK
3621 #define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL 0x10000200
3622 #define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT 24
3623 #define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK 0x3F000000U
3626 * After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa
3627 * re has an option to read the mode registers in the DRAM before the hardw
3628 * are begins the retry process - 1: Wait for software to read/write the mo
3629 * de registers before hardware begins the retry. After software is done wi
3630 * th its operations, it will clear the alert interrupt register bit - 0: H
3631 * ardware can begin the retry right away after the dfi_alert_n pulse goes
3632 * away. The value on this register is valid only when retry is enabled (PA
3633 * RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t
3634 * he software doesn't clear the interrupt register after handling the pari
3635 * ty/CRC error, then the hardware will not begin the retry process and the
3636 * system will hang. In the case of Parity/CRC error, there are two possib
3637 * ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten
3638 * t parity' mode register bit is NOT set: the commands sent during retry a
3639 * nd normal operation are executed without parity checking. The value in t
3640 * he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent
3641 * parity' mode register bit is SET: Parity checking is done for commands s
3642 * ent during retry and normal operation. If multiple errors occur before M
3643 * R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don'
3646 #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL
3647 #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT
3648 #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK
3649 #define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL 0x10000200
3650 #define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT 9
3651 #define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK 0x00000200U
3654 * - 1: Enable command retry mechanism in case of C/A Parity or CRC error -
3655 * 0: Disable command retry mechanism when C/A Parity or CRC features are
3656 * enabled. Note that retry functionality is not supported if burst chop is
3657 * enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF
3658 * SHCTL3.dis_auto_refresh = 1)
3660 #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL
3661 #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT
3662 #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK
3663 #define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL 0x10000200
3664 #define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT 8
3665 #define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK 0x00000100U
3668 * CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no
3669 * t includes DM signal Present only in designs configured to support DDR4.
3671 #undef DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL
3672 #undef DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT
3673 #undef DDRC_CRCPARCTL1_CRC_INC_DM_MASK
3674 #define DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL 0x10000200
3675 #define DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT 7
3676 #define DDRC_CRCPARCTL1_CRC_INC_DM_MASK 0x00000080U
3679 * CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio
3680 * n of CRC The setting of this register should match the CRC mode register
3681 * setting in the DRAM.
3683 #undef DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL
3684 #undef DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT
3685 #undef DDRC_CRCPARCTL1_CRC_ENABLE_MASK
3686 #define DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL 0x10000200
3687 #define DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT 4
3688 #define DDRC_CRCPARCTL1_CRC_ENABLE_MASK 0x00000010U
3691 * C/A Parity enable register - 1: Enable generation of C/A parity and dete
3692 * ction of C/A parity error - 0: Disable generation of C/A parity and disa
3693 * ble detection of C/A parity error If RCD's parity error detection or SDR
3694 * AM's parity detection is enabled, this register should be 1.
3696 #undef DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL
3697 #undef DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT
3698 #undef DDRC_CRCPARCTL1_PARITY_ENABLE_MASK
3699 #define DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL 0x10000200
3700 #define DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT 0
3701 #define DDRC_CRCPARCTL1_PARITY_ENABLE_MASK 0x00000001U
3704 * Value from the DRAM spec indicating the maximum width of the dfi_alert_n
3705 * pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M
3706 * AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT
3707 * _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i
3708 * llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.
3710 #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL
3711 #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT
3712 #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK
3713 #define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL 0x0030050C
3714 #define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT 16
3715 #define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK 0x01FF0000U
3718 * Value from the DRAM spec indicating the maximum width of the dfi_alert_n
3719 * pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX
3720 * For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW
3721 * .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille
3722 * gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.
3724 #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL
3725 #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT
3726 #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK
3727 #define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL 0x0030050C
3728 #define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT 8
3729 #define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK 0x00001F00U
3732 * Indicates the maximum duration in number of DRAM clock cycles for which
3733 * a command should be held in the Command Retry FIFO before it is popped o
3734 * ut. Every location in the Command Retry FIFO has an associated down coun
3735 * ting timer that will use this register as the start value. The down coun
3736 * ting starts when a command is loaded into the FIFO. The timer counts dow
3737 * n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe
3738 * d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err
3739 * or occurs before the counter reaches zero. The counter is reset to 0, af
3740 * ter all the commands in the FIFO are retried. Recommended(minimum) value
3741 * s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK)
3742 * + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten
3743 * cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable
3744 * d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R
3745 * DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK)
3746 * + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be
3747 * in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n
3748 * ) should be considered. Note 3: Use the worst case(longer) value for PHY
3749 * Latencies/Board delay Note 4: The Recommended values are minimum value
3750 * to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max
3751 * value can be set to this register is defined below: - MEMC_BURST_LENGTH
3752 * == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2
3753 * Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b
3754 * us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod
3755 * e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C
3756 * RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC=
3757 * ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16
3758 * Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full
3759 * bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod
3760 * e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC
3761 * =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF
3762 * ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma
3763 * x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal
3766 #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL
3767 #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT
3768 #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK
3769 #define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL 0x0030050C
3770 #define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT 0
3771 #define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK 0x0000003FU
3774 * If lower bit is enabled the SDRAM initialization routine is skipped. The
3775 * upper bit decides what state the controller starts up in when reset is
3776 * removed - 00 - SDRAM Intialization routine is run after power-up - 01 -
3777 * SDRAM Intialization routine is skipped after power-up. Controller starts
3778 * up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p
3779 * ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ
3780 * ation routine is run after power-up. Note: The only 2'b00 is supported f
3781 * or LPDDR4 in this version of the uMCTL2.
3783 #undef DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL
3784 #undef DDRC_INIT0_SKIP_DRAM_INIT_SHIFT
3785 #undef DDRC_INIT0_SKIP_DRAM_INIT_MASK
3786 #define DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL 0x0002004E
3787 #define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT 30
3788 #define DDRC_INIT0_SKIP_DRAM_INIT_MASK 0xC0000000U
3791 * Cycles to wait after driving CKE high to start the SDRAM initialization
3792 * sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req
3793 * uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD
3794 * R3 typically requires this to be programmed for a delay of 200 us. LPDDR
3795 * 4 typically requires this to be programmed for a delay of 2 us. For conf
3796 * igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi
3797 * ded by 2, and round it up to next integer value.
3799 #undef DDRC_INIT0_POST_CKE_X1024_DEFVAL
3800 #undef DDRC_INIT0_POST_CKE_X1024_SHIFT
3801 #undef DDRC_INIT0_POST_CKE_X1024_MASK
3802 #define DDRC_INIT0_POST_CKE_X1024_DEFVAL 0x0002004E
3803 #define DDRC_INIT0_POST_CKE_X1024_SHIFT 16
3804 #define DDRC_INIT0_POST_CKE_X1024_MASK 0x03FF0000U
3807 * Cycles to wait after reset before driving CKE high to start the SDRAM in
3808 * itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi
3809 * cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD
3810 * DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati
3811 * ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by
3812 * 2, and round it up to next integer value.
3814 #undef DDRC_INIT0_PRE_CKE_X1024_DEFVAL
3815 #undef DDRC_INIT0_PRE_CKE_X1024_SHIFT
3816 #undef DDRC_INIT0_PRE_CKE_X1024_MASK
3817 #define DDRC_INIT0_PRE_CKE_X1024_DEFVAL 0x0002004E
3818 #define DDRC_INIT0_PRE_CKE_X1024_SHIFT 0
3819 #define DDRC_INIT0_PRE_CKE_X1024_MASK 0x00000FFFU
3822 * Number of cycles to assert SDRAM reset signal during init sequence. This
3823 * is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo
3824 * r use with a DDR PHY, this should be set to a minimum of 1
3826 #undef DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL
3827 #undef DDRC_INIT1_DRAM_RSTN_X1024_SHIFT
3828 #undef DDRC_INIT1_DRAM_RSTN_X1024_MASK
3829 #define DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL 0x00000000
3830 #define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT 16
3831 #define DDRC_INIT1_DRAM_RSTN_X1024_MASK 0x01FF0000U
3834 * Cycles to wait after completing the SDRAM initialization sequence before
3835 * starting the dynamic scheduler. Unit: Counts of a global timer that pul
3836 * ses every 32 clock cycles. There is no known specific requirement for th
3837 * is; it may be set to zero.
3839 #undef DDRC_INIT1_FINAL_WAIT_X32_DEFVAL
3840 #undef DDRC_INIT1_FINAL_WAIT_X32_SHIFT
3841 #undef DDRC_INIT1_FINAL_WAIT_X32_MASK
3842 #define DDRC_INIT1_FINAL_WAIT_X32_DEFVAL 0x00000000
3843 #define DDRC_INIT1_FINAL_WAIT_X32_SHIFT 8
3844 #define DDRC_INIT1_FINAL_WAIT_X32_MASK 0x00007F00U
3847 * Wait period before driving the OCD complete command to SDRAM. Unit: Coun
3848 * ts of a global timer that pulses every 32 clock cycles. There is no know
3849 * n specific requirement for this; it may be set to zero.
3851 #undef DDRC_INIT1_PRE_OCD_X32_DEFVAL
3852 #undef DDRC_INIT1_PRE_OCD_X32_SHIFT
3853 #undef DDRC_INIT1_PRE_OCD_X32_MASK
3854 #define DDRC_INIT1_PRE_OCD_X32_DEFVAL 0x00000000
3855 #define DDRC_INIT1_PRE_OCD_X32_SHIFT 0
3856 #define DDRC_INIT1_PRE_OCD_X32_MASK 0x0000000FU
3859 * Idle time after the reset command, tINIT4. Present only in designs confi
3860 * gured to support LPDDR2. Unit: 32 clock cycles.
3862 #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL
3863 #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT
3864 #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK
3865 #define DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL 0x00000D05
3866 #define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT 8
3867 #define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK 0x0000FF00U
3870 * Time to wait after the first CKE high, tINIT2. Present only in designs c
3871 * onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t
3872 * ypically requires 5 x tCK delay.
3874 #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL
3875 #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT
3876 #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK
3877 #define DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL 0x00000D05
3878 #define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT 0
3879 #define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK 0x0000000FU
3882 * DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he
3883 * re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value
3884 * loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP
3885 * DDR3/LPDDR4 - Value to write to MR1 register
3887 #undef DDRC_INIT3_MR_DEFVAL
3888 #undef DDRC_INIT3_MR_SHIFT
3889 #undef DDRC_INIT3_MR_MASK
3890 #define DDRC_INIT3_MR_DEFVAL 0x00000510
3891 #define DDRC_INIT3_MR_SHIFT 16
3892 #define DDRC_INIT3_MR_MASK 0xFFFF0000U
3895 * DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti
3896 * ng in this register is ignored. The uMCTL2 sets those bits appropriately
3897 * . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu
3898 * ation mode training is enabled, this bit is set appropriately by the uMC
3899 * TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/
3900 * LPDDR3/LPDDR4 - Value to write to MR2 register
3902 #undef DDRC_INIT3_EMR_DEFVAL
3903 #undef DDRC_INIT3_EMR_SHIFT
3904 #undef DDRC_INIT3_EMR_MASK
3905 #define DDRC_INIT3_EMR_DEFVAL 0x00000510
3906 #define DDRC_INIT3_EMR_SHIFT 0
3907 #define DDRC_INIT3_EMR_MASK 0x0000FFFFU
3910 * DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2
3911 * register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus
3914 #undef DDRC_INIT4_EMR2_DEFVAL
3915 #undef DDRC_INIT4_EMR2_SHIFT
3916 #undef DDRC_INIT4_EMR2_MASK
3917 #define DDRC_INIT4_EMR2_DEFVAL 0x00000000
3918 #define DDRC_INIT4_EMR2_SHIFT 16
3919 #define DDRC_INIT4_EMR2_MASK 0xFFFF0000U
3922 * DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3
3923 * register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis
3926 #undef DDRC_INIT4_EMR3_DEFVAL
3927 #undef DDRC_INIT4_EMR3_SHIFT
3928 #undef DDRC_INIT4_EMR3_MASK
3929 #define DDRC_INIT4_EMR3_DEFVAL 0x00000000
3930 #define DDRC_INIT4_EMR3_SHIFT 0
3931 #define DDRC_INIT4_EMR3_MASK 0x0000FFFFU
3934 * ZQ initial calibration, tZQINIT. Present only in designs configured to s
3935 * upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica
3936 * lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir
3939 #undef DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL
3940 #undef DDRC_INIT5_DEV_ZQINIT_X32_SHIFT
3941 #undef DDRC_INIT5_DEV_ZQINIT_X32_MASK
3942 #define DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL 0x00100004
3943 #define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT 16
3944 #define DDRC_INIT5_DEV_ZQINIT_X32_MASK 0x00FF0000U
3947 * Maximum duration of the auto initialization, tINIT5. Present only in des
3948 * igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir
3951 #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL
3952 #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT
3953 #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK
3954 #define DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL 0x00100004
3955 #define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT 0
3956 #define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK 0x000003FFU
3959 * DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs
3962 #undef DDRC_INIT6_MR4_DEFVAL
3963 #undef DDRC_INIT6_MR4_SHIFT
3964 #undef DDRC_INIT6_MR4_MASK
3965 #define DDRC_INIT6_MR4_DEFVAL 0x00000000
3966 #define DDRC_INIT6_MR4_SHIFT 16
3967 #define DDRC_INIT6_MR4_MASK 0xFFFF0000U
3970 * DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs
3973 #undef DDRC_INIT6_MR5_DEFVAL
3974 #undef DDRC_INIT6_MR5_SHIFT
3975 #undef DDRC_INIT6_MR5_MASK
3976 #define DDRC_INIT6_MR5_DEFVAL 0x00000000
3977 #define DDRC_INIT6_MR5_SHIFT 0
3978 #define DDRC_INIT6_MR5_MASK 0x0000FFFFU
3981 * DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs
3984 #undef DDRC_INIT7_MR6_DEFVAL
3985 #undef DDRC_INIT7_MR6_SHIFT
3986 #undef DDRC_INIT7_MR6_MASK
3987 #define DDRC_INIT7_MR6_DEFVAL
3988 #define DDRC_INIT7_MR6_SHIFT 16
3989 #define DDRC_INIT7_MR6_MASK 0xFFFF0000U
3992 * Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and
3993 * BG1 are NOT swapped even if Address Mirroring is enabled. This will be r
3994 * equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp
3995 * ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled.
3997 #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL
3998 #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT
3999 #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK
4000 #define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL 0x00000000
4001 #define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT 5
4002 #define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK 0x00000020U
4005 * Enable for BG1 bit of MRS command. BG1 bit of the mode register address
4006 * is specified as RFU (Reserved for Future Use) and must be programmed to
4007 * 0 during MRS. In case where DRAMs which do not have BG1 are attached and
4008 * both the CA parity and the Output Inversion are enabled, this must be s
4009 * et to 0, so that the calculation of CA parity will not include BG1 bit.
4010 * Note: This has no effect on the address of any other memory accesses, or
4011 * of software-driven mode register accesses. If address mirroring is enab
4012 * led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En
4013 * abled - 0 - Disabled
4015 #undef DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL
4016 #undef DDRC_DIMMCTL_MRS_BG1_EN_SHIFT
4017 #undef DDRC_DIMMCTL_MRS_BG1_EN_MASK
4018 #define DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL 0x00000000
4019 #define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT 4
4020 #define DDRC_DIMMCTL_MRS_BG1_EN_MASK 0x00000010U
4023 * Enable for A17 bit of MRS command. A17 bit of the mode register address
4024 * is specified as RFU (Reserved for Future Use) and must be programmed to
4025 * 0 during MRS. In case where DRAMs which do not have A17 are attached and
4026 * the Output Inversion are enabled, this must be set to 0, so that the ca
4027 * lculation of CA parity will not include A17 bit. Note: This has no effec
4028 * t on the address of any other memory accesses, or of software-driven mod
4029 * e register accesses. - 1 - Enabled - 0 - Disabled
4031 #undef DDRC_DIMMCTL_MRS_A17_EN_DEFVAL
4032 #undef DDRC_DIMMCTL_MRS_A17_EN_SHIFT
4033 #undef DDRC_DIMMCTL_MRS_A17_EN_MASK
4034 #define DDRC_DIMMCTL_MRS_A17_EN_DEFVAL 0x00000000
4035 #define DDRC_DIMMCTL_MRS_A17_EN_SHIFT 3
4036 #define DDRC_DIMMCTL_MRS_A17_EN_MASK 0x00000008U
4039 * Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM
4040 * M implements the Output Inversion feature by default, which means that t
4041 * he following address, bank address and bank group bits of B-side DRAMs a
4042 * re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en
4043 * sures that, for mode register accesses generated by the uMCTL2 during th
4044 * e automatic initialization routine and enabling of a particular DDR4 fea
4045 * ture, separate A-side and B-side mode register accesses are generated. F
4046 * or B-side mode register accesses, these bits are inverted within the uMC
4047 * TL2 to compensate for this RDIMM inversion. Note: This has no effect on
4048 * the address of any other memory accesses, or of software-driven mode reg
4049 * ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 -
4050 * Do not implement output inversion for B-side DRAMs.
4052 #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL
4053 #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT
4054 #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK
4055 #define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL 0x00000000
4056 #define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT 2
4057 #define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK 0x00000004U
4060 * Address Mirroring Enable (for multi-rank UDIMM implementations and multi
4061 * -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement
4062 * address mirroring for odd ranks, which means that the following address
4063 * , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7,
4064 * A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t
4065 * his bit ensures that, for mode register accesses during the automatic in
4066 * itialization routine, these bits are swapped within the uMCTL2 to compen
4067 * sate for this UDIMM/RDIMM swapping. In addition to the automatic initial
4068 * ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th
4069 * e automatic MRS access to enable/disable of a particular DDR4 feature. N
4070 * ote: This has no effect on the address of any other memory accesses, or
4071 * of software-driven mode register accesses. This is not supported for mDD
4072 * R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1
4073 * output of MRS for the odd ranks is same as BG0 because BG1 is invalid,
4074 * hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran
4075 * ks, implement address mirroring for MRS commands to during initializatio
4076 * n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp
4077 * lements address mirroring) - 0 - Do not implement address mirroring
4079 #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL
4080 #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT
4081 #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK
4082 #define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL 0x00000000
4083 #define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT 1
4084 #define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK 0x00000002U
4087 * Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM
4088 * M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3
4089 * or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of
4090 * software driven MR commands (via MRCTRL0/MRCTRL1), where software is re
4091 * sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se
4092 * nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma
4093 * nds to even and odd ranks seperately - 0 - Do not stagger accesses
4095 #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL
4096 #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT
4097 #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK
4098 #define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL 0x00000000
4099 #define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT 0
4100 #define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK 0x00000001U
4103 * Only present for multi-rank configurations. Indicates the number of cloc
4104 * ks of gap in data responses when performing consecutive writes to differ
4105 * ent ranks. This is used to switch the delays in the PHY to match the ran
4106 * k requirements. This value should consider both PHY requirement and ODT
4107 * requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v
4108 * alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by
4109 * 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas
4110 * ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc
4111 * reased by 1. - ODT requirement: The value programmed in this register ta
4112 * kes care of the ODT switch off timing requirement when switching ranks d
4113 * uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1
4114 * For configurations with MEMC_FREQ_RATIO=1, program this to the larger o
4115 * f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_
4116 * RATIO=2, program this to the larger value divided by two and round it up
4117 * to the next integer.
4119 #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL
4120 #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT
4121 #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK
4122 #define DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL 0x0000066F
4123 #define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT 8
4124 #define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK 0x00000F00U
4127 * Only present for multi-rank configurations. Indicates the number of cloc
4128 * ks of gap in data responses when performing consecutive reads to differe
4129 * nt ranks. This is used to switch the delays in the PHY to match the rank
4130 * requirements. This value should consider both PHY requirement and ODT r
4131 * equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va
4132 * lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only),
4133 * should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only
4134 * ), should be increased by 1. - ODT requirement: The value programmed in
4135 * this register takes care of the ODT switch off timing requirement when s
4136 * witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1,
4137 * program this to the larger of PHY requirement or ODT requirement. For co
4138 * nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di
4139 * vided by two and round it up to the next integer.
4141 #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL
4142 #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT
4143 #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK
4144 #define DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL 0x0000066F
4145 #define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT 4
4146 #define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK 0x000000F0U
4149 * Only present for multi-rank configurations. Background: Reads to the sam
4150 * e rank can be performed back-to-back. Reads to different ranks require a
4151 * dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is
4152 * to avoid possible data bus contention as well as to give PHY enough tim
4153 * e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus
4154 * access on a cycle-by-cycle basis; therefore after a read is scheduled,
4155 * there are few clock cycles (determined by the value on RANKCTL.diff_rank
4156 * _rd_gap register) in which only reads from the same rank are eligible to
4157 * be scheduled. This prevents reads from other ranks from having fair acc
4158 * ess to the data bus. This parameter represents the maximum number of rea
4159 * ds that can be scheduled consecutively to the same rank. After this numb
4160 * er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by
4161 * the scheduler to allow all ranks a fair opportunity to be scheduled. Hig
4162 * her numbers increase bandwidth utilization, lower numbers increase fairn
4163 * ess. This feature can be DISABLED by setting this register to 0. When se
4164 * t to 0, the Controller will stay on the same rank as long as commands ar
4165 * e available for it. Minimum programmable value is 0 (feature disabled) a
4166 * nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY.
4168 #undef DDRC_RANKCTL_MAX_RANK_RD_DEFVAL
4169 #undef DDRC_RANKCTL_MAX_RANK_RD_SHIFT
4170 #undef DDRC_RANKCTL_MAX_RANK_RD_MASK
4171 #define DDRC_RANKCTL_MAX_RANK_RD_DEFVAL 0x0000066F
4172 #define DDRC_RANKCTL_MAX_RANK_RD_SHIFT 0
4173 #define DDRC_RANKCTL_MAX_RANK_RD_MASK 0x0000000FU
4176 * Minimum time between write and precharge to same bank. Unit: Clocks Spec
4177 * ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks
4178 * @400MHz and less for lower frequencies where: - WL = write latency - BL
4179 * = burst length. This must match the value programmed in the BL bit of t
4180 * he mode register to the SDRAM. BST (burst terminate) is not supported at
4181 * present. - tWR = Write recovery time. This comes directly from the SDRA
4182 * M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p
4183 * arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the
4184 * above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT
4185 * IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u
4186 * p to the next integer value.
4188 #undef DDRC_DRAMTMG0_WR2PRE_DEFVAL
4189 #undef DDRC_DRAMTMG0_WR2PRE_SHIFT
4190 #undef DDRC_DRAMTMG0_WR2PRE_MASK
4191 #define DDRC_DRAMTMG0_WR2PRE_DEFVAL 0x0F101B0F
4192 #define DDRC_DRAMTMG0_WR2PRE_SHIFT 24
4193 #define DDRC_DRAMTMG0_WR2PRE_MASK 0x7F000000U
4196 * tFAW Valid only when 8 or more banks(or banks x bank groups) are present
4197 * . In 8-bank design, at most 4 banks must be activated in a rolling windo
4198 * w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi
4199 * s to (tFAW/2) and round up to next integer value. In a 4-bank design, se
4200 * t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration.
4203 #undef DDRC_DRAMTMG0_T_FAW_DEFVAL
4204 #undef DDRC_DRAMTMG0_T_FAW_SHIFT
4205 #undef DDRC_DRAMTMG0_T_FAW_MASK
4206 #define DDRC_DRAMTMG0_T_FAW_DEFVAL 0x0F101B0F
4207 #define DDRC_DRAMTMG0_T_FAW_SHIFT 16
4208 #define DDRC_DRAMTMG0_T_FAW_MASK 0x003F0000U
4211 * tRAS(max): Maximum time between activate and precharge to same bank. Thi
4212 * s is the maximum time that a page can be kept open Minimum value of this
4213 * register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO
4214 * =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of
4217 #undef DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL
4218 #undef DDRC_DRAMTMG0_T_RAS_MAX_SHIFT
4219 #undef DDRC_DRAMTMG0_T_RAS_MAX_MASK
4220 #define DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL 0x0F101B0F
4221 #define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT 8
4222 #define DDRC_DRAMTMG0_T_RAS_MAX_MASK 0x00007F00U
4225 * tRAS(min): Minimum time between activate and precharge to the same bank.
4226 * For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA
4227 * S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T
4228 * mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th
4229 * e next integer value. Unit: Clocks
4231 #undef DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL
4232 #undef DDRC_DRAMTMG0_T_RAS_MIN_SHIFT
4233 #undef DDRC_DRAMTMG0_T_RAS_MIN_MASK
4234 #define DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL 0x0F101B0F
4235 #define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT 0
4236 #define DDRC_DRAMTMG0_T_RAS_MIN_MASK 0x0000003FU
4239 * tXP: Minimum time after power-down exit to any operation. For DDR3, this
4240 * should be programmed to tXPDLL if slow powerdown exit is selected in MR
4241 * 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf
4242 * igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it
4243 * up to the next integer value. Units: Clocks
4245 #undef DDRC_DRAMTMG1_T_XP_DEFVAL
4246 #undef DDRC_DRAMTMG1_T_XP_SHIFT
4247 #undef DDRC_DRAMTMG1_T_XP_MASK
4248 #define DDRC_DRAMTMG1_T_XP_DEFVAL 0x00080414
4249 #define DDRC_DRAMTMG1_T_XP_SHIFT 16
4250 #define DDRC_DRAMTMG1_T_XP_MASK 0x001F0000U
4253 * tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL
4254 * /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi
4255 * ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2
4256 * - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t
4257 * RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4)
4258 * - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_
4259 * RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi
4260 * gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo
4261 * ve value by 2 and round it up to the next integer value. Unit: Clocks.
4263 #undef DDRC_DRAMTMG1_RD2PRE_DEFVAL
4264 #undef DDRC_DRAMTMG1_RD2PRE_SHIFT
4265 #undef DDRC_DRAMTMG1_RD2PRE_MASK
4266 #define DDRC_DRAMTMG1_RD2PRE_DEFVAL 0x00080414
4267 #define DDRC_DRAMTMG1_RD2PRE_SHIFT 8
4268 #define DDRC_DRAMTMG1_RD2PRE_MASK 0x00001F00U
4271 * tRC: Minimum time between activates to same bank. For configurations wit
4272 * h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege
4273 * r value. Unit: Clocks.
4275 #undef DDRC_DRAMTMG1_T_RC_DEFVAL
4276 #undef DDRC_DRAMTMG1_T_RC_SHIFT
4277 #undef DDRC_DRAMTMG1_T_RC_MASK
4278 #define DDRC_DRAMTMG1_T_RC_DEFVAL 0x00080414
4279 #define DDRC_DRAMTMG1_T_RC_SHIFT 0
4280 #define DDRC_DRAMTMG1_T_RC_MASK 0x0000007FU
4283 * Set to WL Time from write command to write data on SDRAM interface. This
4284 * must be set to WL. For mDDR, it should normally be set to 1. Note that,
4285 * depending on the PHY, if using RDIMM, it may be necessary to use a valu
4286 * e of WL + 1 to compensate for the extra cycle of latency through the RDI
4287 * MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate
4288 * d using the above equation by 2, and round it up to next integer. This r
4289 * egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING
4290 * is set), as the DFI read and write latencies defined in DFITMG0 and DFI
4291 * TMG1 are sufficient for those protocols Unit: clocks
4293 #undef DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL
4294 #undef DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT
4295 #undef DDRC_DRAMTMG2_WRITE_LATENCY_MASK
4296 #define DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL 0x0305060D
4297 #define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT 24
4298 #define DDRC_DRAMTMG2_WRITE_LATENCY_MASK 0x3F000000U
4301 * Set to RL Time from read command to read data on SDRAM interface. This m
4302 * ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma
4303 * t be necessary to use a value of RL + 1 to compensate for the extra cycl
4304 * e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2
4305 * , divide the value calculated using the above equation by 2, and round i
4306 * t up to next integer. This register field is not required for DDR2 and D
4307 * DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie
4308 * s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit
4311 #undef DDRC_DRAMTMG2_READ_LATENCY_DEFVAL
4312 #undef DDRC_DRAMTMG2_READ_LATENCY_SHIFT
4313 #undef DDRC_DRAMTMG2_READ_LATENCY_MASK
4314 #define DDRC_DRAMTMG2_READ_LATENCY_DEFVAL 0x0305060D
4315 #define DDRC_DRAMTMG2_READ_LATENCY_SHIFT 16
4316 #define DDRC_DRAMTMG2_READ_LATENCY_MASK 0x003F0000U
4319 * DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L
4320 * PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di
4321 * sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL
4322 * LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL
4323 * E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write
4324 * command. Include time for bus turnaround and all per-bank, per-rank, an
4325 * d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b
4326 * urst length. This must match the value programmed in the BL bit of the m
4327 * ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL
4328 * E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE =
4329 * read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d
4330 * erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should
4331 * be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal
4332 * culated using the above equation by 2, and round it up to next integer.
4334 #undef DDRC_DRAMTMG2_RD2WR_DEFVAL
4335 #undef DDRC_DRAMTMG2_RD2WR_SHIFT
4336 #undef DDRC_DRAMTMG2_RD2WR_MASK
4337 #define DDRC_DRAMTMG2_RD2WR_DEFVAL 0x0305060D
4338 #define DDRC_DRAMTMG2_RD2WR_SHIFT 8
4339 #define DDRC_DRAMTMG2_RD2WR_MASK 0x00003F00U
4342 * DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu
4343 * m time from write command to read command for same bank group. In others
4344 * , minimum time from write command to read command. Includes time for bus
4345 * turnaround, recovery times, and all per-bank, per-rank, and global cons
4346 * traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la
4347 * tency - BL = burst length. This must match the value programmed in the B
4348 * L bit of the mode register to the SDRAM - tWTR_L = internal write to rea
4349 * d command delay for same bank group. This comes directly from the SDRAM
4350 * specification. - tWTR = internal write to read command delay. This comes
4351 * directly from the SDRAM specification. Add one extra cycle for LPDDR2/L
4352 * PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid
4353 * e the value calculated using the above equation by 2, and round it up to
4356 #undef DDRC_DRAMTMG2_WR2RD_DEFVAL
4357 #undef DDRC_DRAMTMG2_WR2RD_SHIFT
4358 #undef DDRC_DRAMTMG2_WR2RD_MASK
4359 #define DDRC_DRAMTMG2_WR2RD_DEFVAL 0x0305060D
4360 #define DDRC_DRAMTMG2_WR2RD_SHIFT 0
4361 #define DDRC_DRAMTMG2_WR2RD_MASK 0x0000003FU
4364 * Time to wait after a mode register write or read (MRW or MRR). Present o
4365 * nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty
4366 * pically requires value of 5. LPDDR3 typically requires value of 10. LPDD
4367 * R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist
4368 * er is used for the time from a MRW/MRR to all other commands. For LDPDR3
4369 * , this register is used for the time from a MRW/MRR to a MRW/MRR.
4371 #undef DDRC_DRAMTMG3_T_MRW_DEFVAL
4372 #undef DDRC_DRAMTMG3_T_MRW_SHIFT
4373 #undef DDRC_DRAMTMG3_T_MRW_MASK
4374 #define DDRC_DRAMTMG3_T_MRW_DEFVAL 0x0050400C
4375 #define DDRC_DRAMTMG3_T_MRW_SHIFT 20
4376 #define DDRC_DRAMTMG3_T_MRW_MASK 0x3FF00000U
4379 * tMRD: Cycles to wait after a mode register write or read. Depending on t
4380 * he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com
4381 * mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim
4382 * e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2,
4383 * program this to (tMRD/2) and round it up to the next integer value. If
4384 * C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead.
4386 #undef DDRC_DRAMTMG3_T_MRD_DEFVAL
4387 #undef DDRC_DRAMTMG3_T_MRD_SHIFT
4388 #undef DDRC_DRAMTMG3_T_MRD_MASK
4389 #define DDRC_DRAMTMG3_T_MRD_DEFVAL 0x0050400C
4390 #define DDRC_DRAMTMG3_T_MRD_SHIFT 12
4391 #define DDRC_DRAMTMG3_T_MRD_MASK 0x0003F000U
4394 * tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com
4395 * mand and following non-load mode command. If C/A parity for DDR4 is used
4396 * , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or
4397 * tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if
4398 * using RDIMM, depending on the PHY, it may be necessary to use a value of
4399 * tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a
4400 * pplied to mode register writes by the RDIMM chip.
4402 #undef DDRC_DRAMTMG3_T_MOD_DEFVAL
4403 #undef DDRC_DRAMTMG3_T_MOD_SHIFT
4404 #undef DDRC_DRAMTMG3_T_MOD_MASK
4405 #define DDRC_DRAMTMG3_T_MOD_DEFVAL 0x0050400C
4406 #define DDRC_DRAMTMG3_T_MOD_SHIFT 0
4407 #define DDRC_DRAMTMG3_T_MOD_MASK 0x000003FFU
4410 * tRCD - tAL: Minimum time from activate to read or write command to same
4411 * bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD
4412 * - tAL)/2) and round it up to the next integer value. Minimum value allow
4413 * ed for this register is 1, which implies minimum (tRCD - tAL) value to b
4414 * e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.
4416 #undef DDRC_DRAMTMG4_T_RCD_DEFVAL
4417 #undef DDRC_DRAMTMG4_T_RCD_SHIFT
4418 #undef DDRC_DRAMTMG4_T_RCD_MASK
4419 #define DDRC_DRAMTMG4_T_RCD_DEFVAL 0x05040405
4420 #define DDRC_DRAMTMG4_T_RCD_SHIFT 24
4421 #define DDRC_DRAMTMG4_T_RCD_MASK 0x1F000000U
4424 * DDR4: tCCD_L: This is the minimum time between two reads or two writes f
4425 * or same bank group. Others: tCCD: This is the minimum time between two r
4426 * eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t
4427 * his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U
4430 #undef DDRC_DRAMTMG4_T_CCD_DEFVAL
4431 #undef DDRC_DRAMTMG4_T_CCD_SHIFT
4432 #undef DDRC_DRAMTMG4_T_CCD_MASK
4433 #define DDRC_DRAMTMG4_T_CCD_DEFVAL 0x05040405
4434 #define DDRC_DRAMTMG4_T_CCD_SHIFT 16
4435 #define DDRC_DRAMTMG4_T_CCD_MASK 0x000F0000U
4438 * DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f
4439 * or same bank group. Others: tRRD: Minimum time between activates from ba
4440 * nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi
4441 * s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni
4444 #undef DDRC_DRAMTMG4_T_RRD_DEFVAL
4445 #undef DDRC_DRAMTMG4_T_RRD_SHIFT
4446 #undef DDRC_DRAMTMG4_T_RRD_MASK
4447 #define DDRC_DRAMTMG4_T_RRD_DEFVAL 0x05040405
4448 #define DDRC_DRAMTMG4_T_RRD_SHIFT 8
4449 #define DDRC_DRAMTMG4_T_RRD_MASK 0x00000F00U
4452 * tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ
4453 * _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM
4454 * C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t
4455 * RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho
4456 * uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
4458 #undef DDRC_DRAMTMG4_T_RP_DEFVAL
4459 #undef DDRC_DRAMTMG4_T_RP_SHIFT
4460 #undef DDRC_DRAMTMG4_T_RP_MASK
4461 #define DDRC_DRAMTMG4_T_RP_DEFVAL 0x05040405
4462 #define DDRC_DRAMTMG4_T_RP_SHIFT 0
4463 #define DDRC_DRAMTMG4_T_RP_MASK 0x0000001FU
4466 * This is the time before Self Refresh Exit that CK is maintained as a val
4467 * id clock before issuing SRX. Specifies the clock stable time before SRX.
4468 * Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK
4469 * EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_
4470 * FREQ_RATIO=2, program this to recommended value divided by two and round
4471 * it up to next integer.
4473 #undef DDRC_DRAMTMG5_T_CKSRX_DEFVAL
4474 #undef DDRC_DRAMTMG5_T_CKSRX_SHIFT
4475 #undef DDRC_DRAMTMG5_T_CKSRX_MASK
4476 #define DDRC_DRAMTMG5_T_CKSRX_DEFVAL 0x05050403
4477 #define DDRC_DRAMTMG5_T_CKSRX_SHIFT 24
4478 #define DDRC_DRAMTMG5_T_CKSRX_MASK 0x0F000000U
4481 * This is the time after Self Refresh Down Entry that CK is maintained as
4482 * a valid clock. Specifies the clock disable delay after SRE. Recommended
4483 * settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1
4484 * - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations
4485 * with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw
4486 * o and round it up to next integer.
4488 #undef DDRC_DRAMTMG5_T_CKSRE_DEFVAL
4489 #undef DDRC_DRAMTMG5_T_CKSRE_SHIFT
4490 #undef DDRC_DRAMTMG5_T_CKSRE_MASK
4491 #define DDRC_DRAMTMG5_T_CKSRE_DEFVAL 0x05050403
4492 #define DDRC_DRAMTMG5_T_CKSRE_SHIFT 16
4493 #define DDRC_DRAMTMG5_T_CKSRE_MASK 0x000F0000U
4496 * Minimum CKE low width for Self refresh or Self refresh power down entry
4497 * to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF
4498 * C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2:
4499 * tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ
4500 * _RATIO=2, program this to recommended value divided by two and round it
4501 * up to next integer.
4503 #undef DDRC_DRAMTMG5_T_CKESR_DEFVAL
4504 #undef DDRC_DRAMTMG5_T_CKESR_SHIFT
4505 #undef DDRC_DRAMTMG5_T_CKESR_MASK
4506 #define DDRC_DRAMTMG5_T_CKESR_DEFVAL 0x05050403
4507 #define DDRC_DRAMTMG5_T_CKESR_SHIFT 8
4508 #define DDRC_DRAMTMG5_T_CKESR_MASK 0x00003F00U
4511 * Minimum number of cycles of CKE HIGH/LOW during power-down and self refr
4512 * esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP
4513 * DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/
4514 * non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration
4515 * s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and
4516 * round it up to the next integer value. Unit: Clocks.
4518 #undef DDRC_DRAMTMG5_T_CKE_DEFVAL
4519 #undef DDRC_DRAMTMG5_T_CKE_SHIFT
4520 #undef DDRC_DRAMTMG5_T_CKE_MASK
4521 #define DDRC_DRAMTMG5_T_CKE_DEFVAL 0x05050403
4522 #define DDRC_DRAMTMG5_T_CKE_SHIFT 0
4523 #define DDRC_DRAMTMG5_T_CKE_MASK 0x0000001FU
4526 * This is the time after Deep Power Down Entry that CK is maintained as a
4527 * valid clock. Specifies the clock disable delay after DPDE. Recommended s
4528 * ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_
4529 * FREQ_RATIO=2, program this to recommended value divided by two and round
4530 * it up to next integer. This is only present for designs supporting mDDR
4531 * or LPDDR2/LPDDR3 devices.
4533 #undef DDRC_DRAMTMG6_T_CKDPDE_DEFVAL
4534 #undef DDRC_DRAMTMG6_T_CKDPDE_SHIFT
4535 #undef DDRC_DRAMTMG6_T_CKDPDE_MASK
4536 #define DDRC_DRAMTMG6_T_CKDPDE_DEFVAL 0x02020005
4537 #define DDRC_DRAMTMG6_T_CKDPDE_SHIFT 24
4538 #define DDRC_DRAMTMG6_T_CKDPDE_MASK 0x0F000000U
4541 * This is the time before Deep Power Down Exit that CK is maintained as a
4542 * valid clock before issuing DPDX. Specifies the clock stable time before
4543 * DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config
4544 * urations with MEMC_FREQ_RATIO=2, program this to recommended value divid
4545 * ed by two and round it up to next integer. This is only present for desi
4546 * gns supporting mDDR or LPDDR2 devices.
4548 #undef DDRC_DRAMTMG6_T_CKDPDX_DEFVAL
4549 #undef DDRC_DRAMTMG6_T_CKDPDX_SHIFT
4550 #undef DDRC_DRAMTMG6_T_CKDPDX_MASK
4551 #define DDRC_DRAMTMG6_T_CKDPDX_DEFVAL 0x02020005
4552 #define DDRC_DRAMTMG6_T_CKDPDX_SHIFT 16
4553 #define DDRC_DRAMTMG6_T_CKDPDX_MASK 0x000F0000U
4556 * This is the time before Clock Stop Exit that CK is maintained as a valid
4557 * clock before issuing Clock Stop Exit. Specifies the clock stable time b
4558 * efore next command after Clock Stop Exit. Recommended settings: - mDDR:
4559 * 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio
4560 * ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by
4561 * two and round it up to next integer. This is only present for designs su
4562 * pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
4564 #undef DDRC_DRAMTMG6_T_CKCSX_DEFVAL
4565 #undef DDRC_DRAMTMG6_T_CKCSX_SHIFT
4566 #undef DDRC_DRAMTMG6_T_CKCSX_MASK
4567 #define DDRC_DRAMTMG6_T_CKCSX_DEFVAL 0x02020005
4568 #define DDRC_DRAMTMG6_T_CKCSX_SHIFT 0
4569 #define DDRC_DRAMTMG6_T_CKCSX_MASK 0x0000000FU
4572 * This is the time after Power Down Entry that CK is maintained as a valid
4573 * clock. Specifies the clock disable delay after PDE. Recommended setting
4574 * s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration
4575 * s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t
4576 * wo and round it up to next integer. This is only present for designs sup
4577 * porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
4579 #undef DDRC_DRAMTMG7_T_CKPDE_DEFVAL
4580 #undef DDRC_DRAMTMG7_T_CKPDE_SHIFT
4581 #undef DDRC_DRAMTMG7_T_CKPDE_MASK
4582 #define DDRC_DRAMTMG7_T_CKPDE_DEFVAL 0x00000202
4583 #define DDRC_DRAMTMG7_T_CKPDE_SHIFT 8
4584 #define DDRC_DRAMTMG7_T_CKPDE_MASK 0x00000F00U
4587 * This is the time before Power Down Exit that CK is maintained as a valid
4588 * clock before issuing PDX. Specifies the clock stable time before PDX. R
4589 * ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c
4590 * onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value
4591 * divided by two and round it up to next integer. This is only present for
4592 * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
4594 #undef DDRC_DRAMTMG7_T_CKPDX_DEFVAL
4595 #undef DDRC_DRAMTMG7_T_CKPDX_SHIFT
4596 #undef DDRC_DRAMTMG7_T_CKPDX_MASK
4597 #define DDRC_DRAMTMG7_T_CKPDX_DEFVAL 0x00000202
4598 #define DDRC_DRAMTMG7_T_CKPDX_SHIFT 0
4599 #define DDRC_DRAMTMG7_T_CKPDX_MASK 0x0000000FU
4602 * tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and
4603 * Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this
4604 * to the above value divided by 2 and round up to next integer value. Unit
4605 * : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com
4606 * mands. Note: Ensure this is less than or equal to t_xs_x32.
4608 #undef DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL
4609 #undef DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT
4610 #undef DDRC_DRAMTMG8_T_XS_FAST_X32_MASK
4611 #define DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL 0x03034405
4612 #define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT 24
4613 #define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK 0x7F000000U
4616 * tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S
4617 * elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th
4618 * is to the above value divided by 2 and round up to next integer value. U
4619 * nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to
4622 #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL
4623 #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT
4624 #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK
4625 #define DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL 0x03034405
4626 #define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT 16
4627 #define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK 0x007F0000U
4630 * tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config
4631 * urations with MEMC_FREQ_RATIO=2, program this to the above value divided
4632 * by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
4633 * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs.
4635 #undef DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL
4636 #undef DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT
4637 #undef DDRC_DRAMTMG8_T_XS_DLL_X32_MASK
4638 #define DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL 0x03034405
4639 #define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT 8
4640 #define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK 0x00007F00U
4643 * tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi
4644 * gurations with MEMC_FREQ_RATIO=2, program this to the above value divide
4645 * d by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
4646 * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs.
4648 #undef DDRC_DRAMTMG8_T_XS_X32_DEFVAL
4649 #undef DDRC_DRAMTMG8_T_XS_X32_SHIFT
4650 #undef DDRC_DRAMTMG8_T_XS_X32_MASK
4651 #define DDRC_DRAMTMG8_T_XS_X32_DEFVAL 0x03034405
4652 #define DDRC_DRAMTMG8_T_XS_X32_SHIFT 0
4653 #define DDRC_DRAMTMG8_T_XS_X32_MASK 0x0000007FU
4656 * DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o
4657 * nly with MEMC_FREQ_RATIO=2
4659 #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL
4660 #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT
4661 #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK
4662 #define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL 0x0004040D
4663 #define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT 30
4664 #define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK 0x40000000U
4667 * tCCD_S: This is the minimum time between two reads or two writes for dif
4668 * ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m
4669 * inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2
4670 * , program this to (tCCD_S/2) and round it up to the next integer value.
4671 * Present only in designs configured to support DDR4. Unit: clocks.
4673 #undef DDRC_DRAMTMG9_T_CCD_S_DEFVAL
4674 #undef DDRC_DRAMTMG9_T_CCD_S_SHIFT
4675 #undef DDRC_DRAMTMG9_T_CCD_S_MASK
4676 #define DDRC_DRAMTMG9_T_CCD_S_DEFVAL 0x0004040D
4677 #define DDRC_DRAMTMG9_T_CCD_S_SHIFT 16
4678 #define DDRC_DRAMTMG9_T_CCD_S_MASK 0x00070000U
4681 * tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif
4682 * ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th
4683 * is to (tRRD_S/2) and round it up to the next integer value. Present only
4684 * in designs configured to support DDR4. Unit: Clocks.
4686 #undef DDRC_DRAMTMG9_T_RRD_S_DEFVAL
4687 #undef DDRC_DRAMTMG9_T_RRD_S_SHIFT
4688 #undef DDRC_DRAMTMG9_T_RRD_S_MASK
4689 #define DDRC_DRAMTMG9_T_RRD_S_DEFVAL 0x0004040D
4690 #define DDRC_DRAMTMG9_T_RRD_S_SHIFT 8
4691 #define DDRC_DRAMTMG9_T_RRD_S_MASK 0x00000F00U
4694 * CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command
4695 * for different bank group. Includes time for bus turnaround, recovery ti
4696 * mes, and all per-bank, per-rank, and global constraints. Present only in
4697 * designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr
4698 * ite latency - PL = Parity latency - BL = burst length. This must match t
4699 * he value programmed in the BL bit of the mode register to the SDRAM - tW
4700 * TR_S = internal write to read command delay for different bank group. Th
4701 * is comes directly from the SDRAM specification. For configurations with
4702 * MEMC_FREQ_RATIO=2, divide the value calculated using the above equation
4703 * by 2, and round it up to next integer.
4705 #undef DDRC_DRAMTMG9_WR2RD_S_DEFVAL
4706 #undef DDRC_DRAMTMG9_WR2RD_S_SHIFT
4707 #undef DDRC_DRAMTMG9_WR2RD_S_MASK
4708 #define DDRC_DRAMTMG9_WR2RD_S_DEFVAL 0x0004040D
4709 #define DDRC_DRAMTMG9_WR2RD_S_SHIFT 0
4710 #define DDRC_DRAMTMG9_WR2RD_S_MASK 0x0000003FU
4713 * tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL
4714 * L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2
4715 * ) and round it up to the next integer value. Present only in designs con
4716 * figured to support DDR4. Unit: Multiples of 32 clocks.
4718 #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL
4719 #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT
4720 #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK
4721 #define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL 0x440C021C
4722 #define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT 24
4723 #define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK 0x7F000000U
4726 * tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For
4727 * configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2
4728 * )+1. Present only in designs configured to support DDR4. Unit: clocks.
4730 #undef DDRC_DRAMTMG11_T_MPX_LH_DEFVAL
4731 #undef DDRC_DRAMTMG11_T_MPX_LH_SHIFT
4732 #undef DDRC_DRAMTMG11_T_MPX_LH_MASK
4733 #define DDRC_DRAMTMG11_T_MPX_LH_DEFVAL 0x440C021C
4734 #define DDRC_DRAMTMG11_T_MPX_LH_SHIFT 16
4735 #define DDRC_DRAMTMG11_T_MPX_LH_MASK 0x001F0000U
4738 * tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_
4739 * FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int
4740 * eger value. Present only in designs configured to support DDR4. Unit: Cl
4743 #undef DDRC_DRAMTMG11_T_MPX_S_DEFVAL
4744 #undef DDRC_DRAMTMG11_T_MPX_S_SHIFT
4745 #undef DDRC_DRAMTMG11_T_MPX_S_MASK
4746 #define DDRC_DRAMTMG11_T_MPX_S_DEFVAL 0x440C021C
4747 #define DDRC_DRAMTMG11_T_MPX_S_SHIFT 8
4748 #define DDRC_DRAMTMG11_T_MPX_S_MASK 0x00000300U
4751 * tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i
4752 * n designs configured to support DDR4. Unit: Clocks. For configurations w
4753 * ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat
4754 * ion by 2, and round it up to next integer.
4756 #undef DDRC_DRAMTMG11_T_CKMPE_DEFVAL
4757 #undef DDRC_DRAMTMG11_T_CKMPE_SHIFT
4758 #undef DDRC_DRAMTMG11_T_CKMPE_MASK
4759 #define DDRC_DRAMTMG11_T_CKMPE_DEFVAL 0x440C021C
4760 #define DDRC_DRAMTMG11_T_CKMPE_SHIFT 0
4761 #define DDRC_DRAMTMG11_T_CKMPE_MASK 0x0000001FU
4764 * tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg
4765 * er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr
4766 * am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu
4769 #undef DDRC_DRAMTMG12_T_CMDCKE_DEFVAL
4770 #undef DDRC_DRAMTMG12_T_CMDCKE_SHIFT
4771 #undef DDRC_DRAMTMG12_T_CMDCKE_MASK
4772 #define DDRC_DRAMTMG12_T_CMDCKE_DEFVAL 0x00020610
4773 #define DDRC_DRAMTMG12_T_CMDCKE_SHIFT 16
4774 #define DDRC_DRAMTMG12_T_CMDCKE_MASK 0x00030000U
4777 * tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat
4778 * ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u
4779 * p to next integer value.
4781 #undef DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL
4782 #undef DDRC_DRAMTMG12_T_CKEHCMD_SHIFT
4783 #undef DDRC_DRAMTMG12_T_CKEHCMD_MASK
4784 #define DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL 0x00020610
4785 #define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT 8
4786 #define DDRC_DRAMTMG12_T_CKEHCMD_MASK 0x00000F00U
4789 * tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode.
4790 * For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2)
4791 * and round it up to next integer value.
4793 #undef DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL
4794 #undef DDRC_DRAMTMG12_T_MRD_PDA_SHIFT
4795 #undef DDRC_DRAMTMG12_T_MRD_PDA_MASK
4796 #define DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL 0x00020610
4797 #define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT 0
4798 #define DDRC_DRAMTMG12_T_MRD_PDA_MASK 0x0000001FU
4801 * - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg
4802 * ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration
4803 * request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati
4804 * on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre
4805 * sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
4807 #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL
4808 #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT
4809 #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK
4810 #define DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL 0x02000040
4811 #define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT 31
4812 #define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK 0x80000000U
4815 * - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres
4816 * h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2
4817 * or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio
4818 * n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i
4819 * n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present
4820 * for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
4822 #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL
4823 #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT
4824 #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK
4825 #define DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL 0x02000040
4826 #define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT 30
4827 #define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK 0x40000000U
4830 * - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC
4831 * L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with
4832 * tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co
4833 * mmands to different ranks do not overlap. - 0 - ZQ resistor is not share
4834 * d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR
4837 #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL
4838 #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT
4839 #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK
4840 #define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL 0x02000040
4841 #define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT 29
4842 #define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK 0x20000000U
4845 * - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit.
4846 * Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com
4847 * mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4
4848 * mode. This is only present for designs supporting DDR4 devices.
4850 #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL
4851 #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT
4852 #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK
4853 #define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL 0x02000040
4854 #define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT 28
4855 #define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK 0x10000000U
4858 * tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe
4859 * r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St
4860 * art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO
4861 * =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int
4862 * eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th
4863 * e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t
4864 * o the next integer value. Unit: Clock cycles. This is only present for d
4865 * esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
4867 #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL
4868 #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT
4869 #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK
4870 #define DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL 0x02000040
4871 #define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT 16
4872 #define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK 0x07FF0000U
4875 * tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of
4876 * NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command
4877 * is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t
4878 * his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy
4879 * cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP
4880 * DDR3/LPDDR4 devices.
4882 #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL
4883 #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT
4884 #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK
4885 #define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL 0x02000040
4886 #define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT 0
4887 #define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK 0x000003FFU
4890 * tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati
4891 * on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_
4892 * RATIO=2, program this to tZQReset/2 and round it up to the next integer
4893 * value. Unit: Clock cycles. This is only present for designs supporting L
4894 * PDDR2/LPDDR3/LPDDR4 devices.
4896 #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL
4897 #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT
4898 #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK
4899 #define DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL 0x02000100
4900 #define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT 20
4901 #define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK 0x3FF00000U
4904 * Average interval to wait between automatically issuing ZQCS (ZQ calibrat
4905 * ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR
4906 * 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles
4907 * . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3
4910 #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL
4911 #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT
4912 #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK
4913 #define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL 0x02000100
4914 #define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT 0
4915 #define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK 0x000FFFFFU
4918 * Specifies the number of DFI clock cycles after an assertion or de-assert
4919 * ion of the DFI control signals that the control signals at the PHY-DRAM
4920 * interface reflect the assertion or de-assertion. If the DFI clock and th
4921 * e memory clock are not phase-aligned, this timing parameter should be ro
4922 * unded up to the next integer value. Note that if using RDIMM, it is nece
4923 * ssary to increment this parameter by RDIMM's extra cycle of latency in t
4924 * erms of DFI clock.
4926 #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL
4927 #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT
4928 #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK
4929 #define DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL 0x07020002
4930 #define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT 24
4931 #define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK 0x1F000000U
4934 * Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u
4935 * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en
4936 * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles
4937 * - 1 in terms of SDR clock cycles Refer to PHY specification for correct
4940 #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL
4941 #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT
4942 #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK
4943 #define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002
4944 #define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT 23
4945 #define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK 0x00800000U
4948 * Time from the assertion of a read command on the DFI interface to the as
4949 * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr
4950 * ect value. This corresponds to the DFI parameter trddata_en. Note that,
4951 * depending on the PHY, if using RDIMM, it may be necessary to use the val
4952 * ue (CL + 1) in the calculation of trddata_en. This is to compensate for
4953 * the extra cycle of latency through the RDIMM. Unit: Clocks
4955 #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL
4956 #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT
4957 #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK
4958 #define DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL 0x07020002
4959 #define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT 16
4960 #define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK 0x003F0000U
4963 * Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us
4964 * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is
4965 * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df
4966 * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR
4967 * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio
4968 * n for correct value.
4970 #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL
4971 #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT
4972 #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK
4973 #define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002
4974 #define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT 15
4975 #define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK 0x00008000U
4978 * Specifies the number of clock cycles between when dfi_wrdata_en is asser
4979 * ted to when the associated write data is driven on the dfi_wrdata signal
4980 * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY
4981 * specification for correct value. Note, max supported value is 8. Unit:
4984 #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL
4985 #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT
4986 #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK
4987 #define DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL 0x07020002
4988 #define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT 8
4989 #define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK 0x00003F00U
4992 * Write latency Number of clocks from the write command to write data enab
4993 * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr
4994 * lat. Refer to PHY specification for correct value.Note that, depending o
4995 * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1)
4996 * in the calculation of tphy_wrlat. This is to compensate for the extra c
4997 * ycle of latency through the RDIMM.
4999 #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL
5000 #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT
5001 #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK
5002 #define DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL 0x07020002
5003 #define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT 0
5004 #define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK 0x0000003FU
5007 * Specifies the number of DFI PHY clocks between when the dfi_cs signal is
5008 * asserted and when the associated command is driven. This field is used
5009 * for CAL mode, should be set to '0' or the value which matches the CAL mo
5010 * de register setting in the DRAM. If the PHY can add the latency for CAL
5011 * mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
5013 #undef DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL
5014 #undef DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT
5015 #undef DDRC_DFITMG1_DFI_T_CMD_LAT_MASK
5016 #define DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL 0x00000404
5017 #define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT 28
5018 #define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK 0xF0000000U
5021 * Specifies the number of DFI PHY clocks between when the dfi_cs signal is
5022 * asserted and when the associated dfi_parity_in signal is driven.
5024 #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL
5025 #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT
5026 #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK
5027 #define DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL 0x00000404
5028 #define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT 24
5029 #define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK 0x03000000U
5032 * Specifies the number of DFI clocks between when the dfi_wrdata_en signal
5033 * is asserted and when the corresponding write data transfer is completed
5034 * on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d
5035 * elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set
5036 * to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI
5037 * 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va
5038 * lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_
5039 * RATIO=2, divide PHY's value by 2 and round up to next integer. If using
5040 * DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks
5042 #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL
5043 #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT
5044 #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK
5045 #define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL 0x00000404
5046 #define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT 16
5047 #define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK 0x001F0000U
5050 * Specifies the number of DFI clock cycles from the assertion of the dfi_d
5051 * ram_clk_disable signal on the DFI until the clock to the DRAM memory dev
5052 * ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock
5053 * and the memory clock are not phase aligned, this timing parameter should
5054 * be rounded up to the next integer value.
5056 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL
5057 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT
5058 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK
5059 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL 0x00000404
5060 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT 8
5061 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK 0x00000F00U
5064 * Specifies the number of DFI clock cycles from the de-assertion of the df
5065 * i_dram_clk_disable signal on the DFI until the first valid rising edge o
5066 * f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the
5067 * DFI clock and the memory clock are not phase aligned, this timing param
5068 * eter should be rounded up to the next integer value.
5070 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL
5071 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT
5072 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK
5073 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL 0x00000404
5074 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT 0
5075 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK 0x0000000FU
5078 * Setting for DFI's tlp_resp time. Same value is used for both Power Down,
5079 * Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s
5080 * pecification onwards, recommends using a fixed value of 7 always.
5082 #undef DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL
5083 #undef DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT
5084 #undef DDRC_DFILPCFG0_DFI_TLP_RESP_MASK
5085 #define DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL 0x07000000
5086 #define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT 24
5087 #define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK 0x0F000000U
5090 * Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente
5091 * red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32
5092 * cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5
5093 * 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles -
5094 * 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553
5095 * 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T
5096 * his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices
5099 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL
5100 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT
5101 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK
5102 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL 0x07000000
5103 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT 20
5104 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK 0x00F00000U
5107 * Enables DFI Low Power interface handshaking during Deep Power Down Entry
5108 * /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup
5109 * porting mDDR or LPDDR2/LPDDR3 devices.
5111 #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL
5112 #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT
5113 #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK
5114 #define DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL 0x07000000
5115 #define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT 16
5116 #define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK 0x00010000U
5119 * Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered
5120 * . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc
5121 * les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512
5122 * cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9
5123 * - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c
5124 * ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited
5126 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL
5127 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT
5128 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK
5129 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL 0x07000000
5130 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT 12
5131 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK 0x0000F000U
5134 * Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex
5135 * it. - 0 - Disabled - 1 - Enabled
5137 #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL
5138 #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT
5139 #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK
5140 #define DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL 0x07000000
5141 #define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT 8
5142 #define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK 0x00000100U
5145 * Value to drive on dfi_lp_wakeup signal when Power Down mode is entered.
5146 * Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle
5147 * s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy
5148 * cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 -
5149 * 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc
5150 * les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited
5152 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL
5153 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT
5154 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK
5155 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL 0x07000000
5156 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT 4
5157 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK 0x000000F0U
5160 * Enables DFI Low Power interface handshaking during Power Down Entry/Exit
5161 * . - 0 - Disabled - 1 - Enabled
5163 #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL
5164 #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT
5165 #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK
5166 #define DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL 0x07000000
5167 #define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT 0
5168 #define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK 0x00000001U
5171 * Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is
5172 * entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1
5173 * - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x
5174 * 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl
5175 * es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC -
5176 * 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi
5177 * ted This is only present for designs supporting DDR4 devices.
5179 #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL
5180 #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT
5181 #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK
5182 #define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL 0x00000000
5183 #define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT 4
5184 #define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK 0x000000F0U
5187 * Enables DFI Low Power interface handshaking during Maximum Power Saving
5188 * Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d
5189 * esigns supporting DDR4 devices.
5191 #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL
5192 #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT
5193 #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK
5194 #define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL 0x00000000
5195 #define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT 0
5196 #define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK 0x00000001U
5199 * When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2
5200 * . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc
5201 * _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically.
5203 #undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_DEFVAL
5204 #undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT
5205 #undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK
5206 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_DEFVAL 0x00400003
5207 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT 31
5208 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK 0x80000000U
5211 * When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2
5212 * following a self-refresh exit. The core must issue the dfi_ctrlupd_req
5213 * signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct
5214 * rlupd_req after exiting self-refresh.
5216 #undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_DEFVAL
5217 #undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT
5218 #undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK
5219 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_DEFVAL 0x00400003
5220 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT 30
5221 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK 0x40000000U
5224 * Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si
5225 * gnal can assert. Lowest value to assign to this variable is 0x40. Unit:
5228 #undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_DEFVAL
5229 #undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT
5230 #undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK
5231 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_DEFVAL 0x00400003
5232 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT 16
5233 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK 0x03FF0000U
5236 * Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si
5237 * gnal must be asserted. The uMCTL2 expects the PHY to respond within this
5238 * time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup
5239 * d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this
5240 * variable is 0x3. Unit: Clocks
5242 #undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_DEFVAL
5243 #undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT
5244 #undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK
5245 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_DEFVAL 0x00400003
5246 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT 0
5247 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK 0x000003FFU
5250 * This is the minimum amount of time between uMCTL2 initiated DFI update r
5251 * equests (which is executed whenever the uMCTL2 is idle). Set this number
5252 * higher to reduce the frequency of update requests, which can have a sma
5253 * ll impact on the latency of the first read request when the uMCTL2 is id
5254 * le. Unit: 1024 clocks
5256 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL
5257 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT
5258 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK
5259 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL 0x00000000
5260 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT 16
5261 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK 0x00FF0000U
5264 * This is the maximum amount of time between uMCTL2 initiated DFI update r
5265 * equests. This timer resets with each update request; when the timer expi
5266 * res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd
5267 * _ackx is received. PHY can use this idle time to recalibrate the delay l
5268 * ines to the DLLs. The DFI controller update is also used to reset PHY FI
5269 * FO pointers in case of data capture errors. Updates are required to main
5270 * tain calibration over PVT, but frequent updates may impact performance.
5271 * Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must
5272 * be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl
5275 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL
5276 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT
5277 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK
5278 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL 0x00000000
5279 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT 0
5280 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK 0x000000FFU
5283 * Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal
5284 * s are active low - 1: Signals are active high
5286 #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL
5287 #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT
5288 #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK
5289 #define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL 0x00000001
5290 #define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT 2
5291 #define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK 0x00000004U
5294 * DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality.
5295 * - 1 - PHY implements DBI functionality. Present only in designs configu
5296 * red to support DDR4 and LPDDR4.
5298 #undef DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL
5299 #undef DDRC_DFIMISC_PHY_DBI_MODE_SHIFT
5300 #undef DDRC_DFIMISC_PHY_DBI_MODE_MASK
5301 #define DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL 0x00000001
5302 #define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT 1
5303 #define DDRC_DFIMISC_PHY_DBI_MODE_MASK 0x00000002U
5306 * PHY initialization complete enable signal. When asserted the dfi_init_co
5307 * mplete signal can be used to trigger SDRAM initialisation
5309 #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL
5310 #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT
5311 #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK
5312 #define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL 0x00000001
5313 #define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT 0
5314 #define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK 0x00000001U
5317 * >Number of clocks between when a read command is sent on the DFI control
5318 * interface and when the associated dfi_rddata_cs signal is asserted. Thi
5319 * s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe
5320 * cification for correct value.
5322 #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL
5323 #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT
5324 #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK
5325 #define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL 0x00000202
5326 #define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT 8
5327 #define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK 0x00003F00U
5330 * Number of clocks between when a write command is sent on the DFI control
5331 * interface and when the associated dfi_wrdata_cs signal is asserted. Thi
5332 * s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe
5333 * cification for correct value.
5335 #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL
5336 #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT
5337 #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK
5338 #define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL 0x00000202
5339 #define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT 0
5340 #define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK 0x0000003FU
5343 * Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D
5344 * BI is enabled. This signal must be set the same value as DRAM's mode reg
5345 * ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b
5346 * e set to 0. - LPDDR4: MR3[6]
5348 #undef DDRC_DBICTL_RD_DBI_EN_DEFVAL
5349 #undef DDRC_DBICTL_RD_DBI_EN_SHIFT
5350 #undef DDRC_DBICTL_RD_DBI_EN_MASK
5351 #define DDRC_DBICTL_RD_DBI_EN_DEFVAL 0x00000001
5352 #define DDRC_DBICTL_RD_DBI_EN_SHIFT 2
5353 #define DDRC_DBICTL_RD_DBI_EN_MASK 0x00000004U
5356 * Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ
5357 * e DBI is enabled. This signal must be set the same value as DRAM's mode
5358 * register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus
5359 * t be set to 0. - LPDDR4: MR3[7]
5361 #undef DDRC_DBICTL_WR_DBI_EN_DEFVAL
5362 #undef DDRC_DBICTL_WR_DBI_EN_SHIFT
5363 #undef DDRC_DBICTL_WR_DBI_EN_MASK
5364 #define DDRC_DBICTL_WR_DBI_EN_DEFVAL 0x00000001
5365 #define DDRC_DBICTL_WR_DBI_EN_SHIFT 1
5366 #define DDRC_DBICTL_WR_DBI_EN_MASK 0x00000002U
5369 * DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi
5370 * s signal must be set the same logical value as DRAM's mode register. - D
5371 * DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th
5372 * is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13
5373 * [5] which is opposite polarity from this signal
5375 #undef DDRC_DBICTL_DM_EN_DEFVAL
5376 #undef DDRC_DBICTL_DM_EN_SHIFT
5377 #undef DDRC_DBICTL_DM_EN_MASK
5378 #define DDRC_DBICTL_DM_EN_DEFVAL 0x00000001
5379 #define DDRC_DBICTL_DM_EN_SHIFT 0
5380 #define DDRC_DBICTL_DM_EN_MASK 0x00000001U
5383 * Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t
5384 * o 27, and 31 Internal Base: 6 The selected HIF address bit is determined
5385 * by adding the internal base to the value of this field. If set to 31, r
5386 * ank address bit 0 is set to 0.
5388 #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL
5389 #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT
5390 #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK
5391 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL
5392 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT 0
5393 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK 0x0000001FU
5396 * Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t
5397 * o 29 and 31 Internal Base: 4 The selected HIF address bit is determined
5398 * by adding the internal base to the value of this field. If set to 31, ba
5399 * nk address bit 2 is set to 0.
5401 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL
5402 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT
5403 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK
5404 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL 0x00000000
5405 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT 16
5406 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK 0x001F0000U
5409 * Selects the HIF address bits used as bank address bit 1. Valid Range: 0
5410 * to 30 Internal Base: 3 The selected HIF address bit for each of the bank
5411 * address bits is determined by adding the internal base to the value of
5414 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL
5415 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT
5416 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK
5417 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL 0x00000000
5418 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT 8
5419 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK 0x00001F00U
5422 * Selects the HIF address bits used as bank address bit 0. Valid Range: 0
5423 * to 30 Internal Base: 2 The selected HIF address bit for each of the bank
5424 * address bits is determined by adding the internal base to the value of
5427 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL
5428 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT
5429 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK
5430 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL 0x00000000
5431 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT 0
5432 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK 0x0000001FU
5435 * - Full bus width mode: Selects the HIF address bit used as column addres
5436 * s bit 5. - Half bus width mode: Selects the HIF address bit used as colu
5437 * mn address bit 6. - Quarter bus width mode: Selects the HIF address bit
5438 * used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base
5439 * : 5 The selected HIF address bit is determined by adding the internal ba
5440 * se to the value of this field. If set to 15, this column address bit is
5443 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL
5444 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT
5445 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK
5446 #define DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL 0x00000000
5447 #define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT 24
5448 #define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK 0x0F000000U
5451 * - Full bus width mode: Selects the HIF address bit used as column addres
5452 * s bit 4. - Half bus width mode: Selects the HIF address bit used as colu
5453 * mn address bit 5. - Quarter bus width mode: Selects the HIF address bit
5454 * used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base:
5455 * 4 The selected HIF address bit is determined by adding the internal bas
5456 * e to the value of this field. If set to 15, this column address bit is s
5459 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL
5460 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT
5461 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK
5462 #define DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL 0x00000000
5463 #define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT 16
5464 #define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK 0x000F0000U
5467 * - Full bus width mode: Selects the HIF address bit used as column addres
5468 * s bit 3. - Half bus width mode: Selects the HIF address bit used as colu
5469 * mn address bit 4. - Quarter bus width mode: Selects the HIF address bit
5470 * used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s
5471 * elected HIF address bit is determined by adding the internal base to the
5472 * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1
5473 * 6, it is required to program this to 0, hence register does not exist in
5476 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL
5477 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT
5478 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK
5479 #define DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL 0x00000000
5480 #define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT 8
5481 #define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK 0x00000F00U
5484 * - Full bus width mode: Selects the HIF address bit used as column addres
5485 * s bit 2. - Half bus width mode: Selects the HIF address bit used as colu
5486 * mn address bit 3. - Quarter bus width mode: Selects the HIF address bit
5487 * used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s
5488 * elected HIF address bit is determined by adding the internal base to the
5489 * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8
5490 * or 16, it is required to program this to 0.
5492 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL
5493 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT
5494 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK
5495 #define DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL 0x00000000
5496 #define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT 0
5497 #define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK 0x0000000FU
5500 * - Full bus width mode: Selects the HIF address bit used as column addres
5501 * s bit 9. - Half bus width mode: Selects the HIF address bit used as colu
5502 * mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode:
5503 * Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/
5504 * LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected
5505 * HIF address bit is determined by adding the internal base to the value o
5506 * f this field. If set to 15, this column address bit is set to 0. Note: P
5507 * er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo
5508 * r indicating auto-precharge, and hence no source address bit can be mapp
5509 * ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit
5510 * for auto-precharge in the CA bus and hence column bit 10 is used.
5512 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL
5513 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT
5514 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK
5515 #define DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL 0x00000000
5516 #define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT 24
5517 #define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK 0x0F000000U
5520 * - Full bus width mode: Selects the HIF address bit used as column addres
5521 * s bit 8. - Half bus width mode: Selects the HIF address bit used as colu
5522 * mn address bit 9. - Quarter bus width mode: Selects the HIF address bit
5523 * used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0
5524 * to 7, and 15 Internal Base: 8 The selected HIF address bit is determine
5525 * d by adding the internal base to the value of this field. If set to 15,
5526 * this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi
5527 * cation, column address bit 10 is reserved for indicating auto-precharge,
5528 * and hence no source address bit can be mapped to column address bit 10.
5529 * In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA
5530 * bus and hence column bit 10 is used.
5532 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL
5533 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT
5534 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK
5535 #define DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL 0x00000000
5536 #define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT 16
5537 #define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK 0x000F0000U
5540 * - Full bus width mode: Selects the HIF address bit used as column addres
5541 * s bit 7. - Half bus width mode: Selects the HIF address bit used as colu
5542 * mn address bit 8. - Quarter bus width mode: Selects the HIF address bit
5543 * used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base:
5544 * 7 The selected HIF address bit is determined by adding the internal bas
5545 * e to the value of this field. If set to 15, this column address bit is s
5548 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL
5549 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT
5550 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK
5551 #define DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL 0x00000000
5552 #define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT 8
5553 #define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK 0x00000F00U
5556 * - Full bus width mode: Selects the HIF address bit used as column addres
5557 * s bit 6. - Half bus width mode: Selects the HIF address bit used as colu
5558 * mn address bit 7. - Quarter bus width mode: Selects the HIF address bit
5559 * used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base:
5560 * 6 The selected HIF address bit is determined by adding the internal bas
5561 * e to the value of this field. If set to 15, this column address bit is s
5564 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL
5565 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT
5566 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK
5567 #define DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL 0x00000000
5568 #define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT 0
5569 #define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK 0x0000000FU
5572 * - Full bus width mode: Selects the HIF address bit used as column addres
5573 * s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m
5574 * ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un
5575 * used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7,
5576 * and 15 Internal Base: 11 The selected HIF address bit is determined by
5577 * adding the internal base to the value of this field. If set to 15, this
5578 * column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio
5579 * n, column address bit 10 is reserved for indicating auto-precharge, and
5580 * hence no source address bit can be mapped to column address bit 10. In L
5581 * PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus
5582 * and hence column bit 10 is used.
5584 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL
5585 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT
5586 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK
5587 #define DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL 0x00000000
5588 #define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT 8
5589 #define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK 0x00000F00U
5592 * - Full bus width mode: Selects the HIF address bit used as column addres
5593 * s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the
5594 * HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode)
5595 * . - Quarter bus width mode: UNUSED. To make it unused, this must be tied
5596 * to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF
5597 * address bit is determined by adding the internal base to the value of t
5598 * his field. If set to 15, this column address bit is set to 0. Note: Per
5599 * JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i
5600 * ndicating auto-precharge, and hence no source address bit can be mapped
5601 * to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for
5602 * auto-precharge in the CA bus and hence column bit 10 is used.
5604 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL
5605 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT
5606 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK
5607 #define DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL 0x00000000
5608 #define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT 0
5609 #define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK 0x0000000FU
5612 * Selects the HIF address bit used as row address bit 11. Valid Range: 0 t
5613 * o 11, and 15 Internal Base: 17 The selected HIF address bit is determine
5614 * d by adding the internal base to the value of this field. If set to 15,
5615 * row address bit 11 is set to 0.
5617 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL
5618 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT
5619 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK
5620 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL 0x00000000
5621 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT 24
5622 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK 0x0F000000U
5625 * Selects the HIF address bits used as row address bits 2 to 10. Valid Ran
5626 * ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row
5627 * address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro
5628 * w address bit 10) The selected HIF address bit for each of the row addre
5629 * ss bits is determined by adding the internal base to the value of this f
5630 * ield. When value 15 is used the values of row address bits 2 to 10 are d
5631 * efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.
5633 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL
5634 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT
5635 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK
5636 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL 0x00000000
5637 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT 16
5638 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK 0x000F0000U
5641 * Selects the HIF address bits used as row address bit 1. Valid Range: 0 t
5642 * o 11 Internal Base: 7 The selected HIF address bit for each of the row a
5643 * ddress bits is determined by adding the internal base to the value of th
5646 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL
5647 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT
5648 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK
5649 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL 0x00000000
5650 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT 8
5651 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK 0x00000F00U
5654 * Selects the HIF address bits used as row address bit 0. Valid Range: 0 t
5655 * o 11 Internal Base: 6 The selected HIF address bit for each of the row a
5656 * ddress bits is determined by adding the internal base to the value of th
5659 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL
5660 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT
5661 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK
5662 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL 0x00000000
5663 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT 0
5664 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK 0x0000000FU
5667 * Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1
5668 * - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]=
5669 * =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use.
5670 * All addresses are valid Present only in designs configured to support L
5673 #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL
5674 #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT
5675 #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK
5676 #define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL 0x00000000
5677 #define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT 31
5678 #define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK 0x80000000U
5681 * Selects the HIF address bit used as row address bit 15. Valid Range: 0 t
5682 * o 11, and 15 Internal Base: 21 The selected HIF address bit is determine
5683 * d by adding the internal base to the value of this field. If set to 15,
5684 * row address bit 15 is set to 0.
5686 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL
5687 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT
5688 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK
5689 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL 0x00000000
5690 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT 24
5691 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK 0x0F000000U
5694 * Selects the HIF address bit used as row address bit 14. Valid Range: 0 t
5695 * o 11, and 15 Internal Base: 20 The selected HIF address bit is determine
5696 * d by adding the internal base to the value of this field. If set to 15,
5697 * row address bit 14 is set to 0.
5699 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL
5700 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT
5701 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK
5702 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL 0x00000000
5703 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT 16
5704 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK 0x000F0000U
5707 * Selects the HIF address bit used as row address bit 13. Valid Range: 0 t
5708 * o 11, and 15 Internal Base: 19 The selected HIF address bit is determine
5709 * d by adding the internal base to the value of this field. If set to 15,
5710 * row address bit 13 is set to 0.
5712 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL
5713 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT
5714 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK
5715 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL 0x00000000
5716 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT 8
5717 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK 0x00000F00U
5720 * Selects the HIF address bit used as row address bit 12. Valid Range: 0 t
5721 * o 11, and 15 Internal Base: 18 The selected HIF address bit is determine
5722 * d by adding the internal base to the value of this field. If set to 15,
5723 * row address bit 12 is set to 0.
5725 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL
5726 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT
5727 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK
5728 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL 0x00000000
5729 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT 0
5730 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK 0x0000000FU
5733 * Selects the HIF address bit used as row address bit 17. Valid Range: 0 t
5734 * o 10, and 15 Internal Base: 23 The selected HIF address bit is determine
5735 * d by adding the internal base to the value of this field. If set to 15,
5736 * row address bit 17 is set to 0.
5738 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL
5739 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT
5740 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK
5741 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL 0x00000000
5742 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT 8
5743 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK 0x00000F00U
5746 * Selects the HIF address bit used as row address bit 16. Valid Range: 0 t
5747 * o 11, and 15 Internal Base: 22 The selected HIF address bit is determine
5748 * d by adding the internal base to the value of this field. If set to 15,
5749 * row address bit 16 is set to 0.
5751 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL
5752 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT
5753 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK
5754 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL 0x00000000
5755 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT 0
5756 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK 0x0000000FU
5759 * Selects the HIF address bits used as bank group address bit 1. Valid Ran
5760 * ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea
5761 * ch of the bank group address bits is determined by adding the internal b
5762 * ase to the value of this field. If set to 31, bank group address bit 1 i
5765 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL
5766 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT
5767 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK
5768 #define DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL 0x00000000
5769 #define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT 8
5770 #define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK 0x00001F00U
5773 * Selects the HIF address bits used as bank group address bit 0. Valid Ran
5774 * ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th
5775 * e bank group address bits is determined by adding the internal base to t
5776 * he value of this field.
5778 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL
5779 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT
5780 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK
5781 #define DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL 0x00000000
5782 #define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT 0
5783 #define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK 0x0000001FU
5786 * Selects the HIF address bits used as row address bit 5. Valid Range: 0 t
5787 * o 11 Internal Base: 11 The selected HIF address bit for each of the row
5788 * address bits is determined by adding the internal base to the value of t
5789 * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
5790 * _10 is set to value 15.
5792 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL
5793 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT
5794 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK
5795 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL 0x00000000
5796 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT 24
5797 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK 0x0F000000U
5800 * Selects the HIF address bits used as row address bit 4. Valid Range: 0 t
5801 * o 11 Internal Base: 10 The selected HIF address bit for each of the row
5802 * address bits is determined by adding the internal base to the value of t
5803 * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
5804 * _10 is set to value 15.
5806 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL
5807 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT
5808 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK
5809 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL 0x00000000
5810 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT 16
5811 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK 0x000F0000U
5814 * Selects the HIF address bits used as row address bit 3. Valid Range: 0 t
5815 * o 11 Internal Base: 9 The selected HIF address bit for each of the row a
5816 * ddress bits is determined by adding the internal base to the value of th
5817 * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_
5818 * 10 is set to value 15.
5820 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL
5821 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT
5822 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK
5823 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL 0x00000000
5824 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT 8
5825 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK 0x00000F00U
5828 * Selects the HIF address bits used as row address bit 2. Valid Range: 0 t
5829 * o 11 Internal Base: 8 The selected HIF address bit for each of the row a
5830 * ddress bits is determined by adding the internal base to the value of th
5831 * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_
5832 * 10 is set to value 15.
5834 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL
5835 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT
5836 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK
5837 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL 0x00000000
5838 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT 0
5839 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK 0x0000000FU
5842 * Selects the HIF address bits used as row address bit 9. Valid Range: 0 t
5843 * o 11 Internal Base: 15 The selected HIF address bit for each of the row
5844 * address bits is determined by adding the internal base to the value of t
5845 * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
5846 * _10 is set to value 15.
5848 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL
5849 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT
5850 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK
5851 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL 0x00000000
5852 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT 24
5853 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK 0x0F000000U
5856 * Selects the HIF address bits used as row address bit 8. Valid Range: 0 t
5857 * o 11 Internal Base: 14 The selected HIF address bit for each of the row
5858 * address bits is determined by adding the internal base to the value of t
5859 * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
5860 * _10 is set to value 15.
5862 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL
5863 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT
5864 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK
5865 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL 0x00000000
5866 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT 16
5867 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK 0x000F0000U
5870 * Selects the HIF address bits used as row address bit 7. Valid Range: 0 t
5871 * o 11 Internal Base: 13 The selected HIF address bit for each of the row
5872 * address bits is determined by adding the internal base to the value of t
5873 * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
5874 * _10 is set to value 15.
5876 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL
5877 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT
5878 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK
5879 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL 0x00000000
5880 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT 8
5881 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK 0x00000F00U
5884 * Selects the HIF address bits used as row address bit 6. Valid Range: 0 t
5885 * o 11 Internal Base: 12 The selected HIF address bit for each of the row
5886 * address bits is determined by adding the internal base to the value of t
5887 * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
5888 * _10 is set to value 15.
5890 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL
5891 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT
5892 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK
5893 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL 0x00000000
5894 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT 0
5895 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK 0x0000000FU
5898 * Selects the HIF address bits used as row address bit 10. Valid Range: 0
5899 * to 11 Internal Base: 16 The selected HIF address bit for each of the row
5900 * address bits is determined by adding the internal base to the value of
5901 * this field. This register field is used only when ADDRMAP5.addrmap_row_b
5902 * 2_10 is set to value 15.
5904 #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL
5905 #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT
5906 #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK
5907 #define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL
5908 #define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT 0
5909 #define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK 0x0000000FU
5912 * Cycles to hold ODT for a write command. The minimum supported value is 2
5913 * . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800
5914 * ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D
5915 * DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR
5916 * EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (
5917 * not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
5919 #undef DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL
5920 #undef DDRC_ODTCFG_WR_ODT_HOLD_SHIFT
5921 #undef DDRC_ODTCFG_WR_ODT_HOLD_MASK
5922 #define DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL 0x04000400
5923 #define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT 24
5924 #define DDRC_ODTCFG_WR_ODT_HOLD_MASK 0x0F000000U
5927 * The delay, in clock cycles, from issuing a write command to setting ODT
5928 * values associated with that command. ODT setting must remain constant fo
5929 * r the entire time that DQS is driven by the uMCTL2. Recommended values:
5930 * DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL +
5931 * AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo
5932 * r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust
5933 * for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))
5935 #undef DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL
5936 #undef DDRC_ODTCFG_WR_ODT_DELAY_SHIFT
5937 #undef DDRC_ODTCFG_WR_ODT_DELAY_MASK
5938 #define DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL 0x04000400
5939 #define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT 16
5940 #define DDRC_ODTCFG_WR_ODT_DELAY_MASK 0x001F0000U
5943 * Cycles to hold ODT for a read command. The minimum supported value is 2.
5944 * Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) -
5945 * BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8
5946 * : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p
5947 * reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) +
5948 * RU(tODTon(max)/tCK)
5950 #undef DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL
5951 #undef DDRC_ODTCFG_RD_ODT_HOLD_SHIFT
5952 #undef DDRC_ODTCFG_RD_ODT_HOLD_MASK
5953 #define DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL 0x04000400
5954 #define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT 8
5955 #define DDRC_ODTCFG_RD_ODT_HOLD_MASK 0x00000F00U
5958 * The delay, in clock cycles, from issuing a read command to setting ODT v
5959 * alues associated with that command. ODT setting must remain constant for
5960 * the entire time that DQS is driven by the uMCTL2. Recommended values: D
5961 * DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL
5962 * - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C
5963 * WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat
5964 * (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK
5965 * write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre
5966 * amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su
5967 * pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R
5968 * U(tODTon(max)/tCK)
5970 #undef DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL
5971 #undef DDRC_ODTCFG_RD_ODT_DELAY_SHIFT
5972 #undef DDRC_ODTCFG_RD_ODT_DELAY_MASK
5973 #define DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL 0x04000400
5974 #define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT 2
5975 #define DDRC_ODTCFG_RD_ODT_DELAY_MASK 0x0000007CU
5978 * Indicates which remote ODTs must be turned on during a read from rank 1.
5979 * Each rank has a remote ODT (in the SDRAM) which can be turned on by set
5980 * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i
5981 * s controlled by bit next to the LSB, etc. For each rank, set its bit to
5982 * 1 to enable its ODT. Present only in configurations that have 2 or more
5985 #undef DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL
5986 #undef DDRC_ODTMAP_RANK1_RD_ODT_SHIFT
5987 #undef DDRC_ODTMAP_RANK1_RD_ODT_MASK
5988 #define DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL 0x00002211
5989 #define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT 12
5990 #define DDRC_ODTMAP_RANK1_RD_ODT_MASK 0x00003000U
5993 * Indicates which remote ODTs must be turned on during a write to rank 1.
5994 * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett
5995 * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is
5996 * controlled by bit next to the LSB, etc. For each rank, set its bit to 1
5997 * to enable its ODT. Present only in configurations that have 2 or more r
6000 #undef DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL
6001 #undef DDRC_ODTMAP_RANK1_WR_ODT_SHIFT
6002 #undef DDRC_ODTMAP_RANK1_WR_ODT_MASK
6003 #define DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL 0x00002211
6004 #define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT 8
6005 #define DDRC_ODTMAP_RANK1_WR_ODT_MASK 0x00000300U
6008 * Indicates which remote ODTs must be turned on during a read from rank 0.
6009 * Each rank has a remote ODT (in the SDRAM) which can be turned on by set
6010 * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i
6011 * s controlled by bit next to the LSB, etc. For each rank, set its bit to
6012 * 1 to enable its ODT.
6014 #undef DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL
6015 #undef DDRC_ODTMAP_RANK0_RD_ODT_SHIFT
6016 #undef DDRC_ODTMAP_RANK0_RD_ODT_MASK
6017 #define DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL 0x00002211
6018 #define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT 4
6019 #define DDRC_ODTMAP_RANK0_RD_ODT_MASK 0x00000030U
6022 * Indicates which remote ODTs must be turned on during a write to rank 0.
6023 * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett
6024 * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is
6025 * controlled by bit next to the LSB, etc. For each rank, set its bit to 1
6026 * to enable its ODT.
6028 #undef DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL
6029 #undef DDRC_ODTMAP_RANK0_WR_ODT_SHIFT
6030 #undef DDRC_ODTMAP_RANK0_WR_ODT_MASK
6031 #define DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL 0x00002211
6032 #define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT 0
6033 #define DDRC_ODTMAP_RANK0_WR_ODT_MASK 0x00000003U
6036 * When the preferred transaction store is empty for these many clock cycle
6037 * s, switch to the alternate transaction store if it is non-empty. The rea
6038 * d transaction store (both high and low priority) is the default preferre
6039 * d transaction store and the write transaction store is the alternative s
6040 * tore. When prefer write over read is set this is reversed. 0x0 is a lega
6041 * l value for this register. When set to 0x0, the transaction store switch
6042 * ing will happen immediately when the switching conditions become true. F
6043 * OR PERFORMANCE ONLY
6045 #undef DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL
6046 #undef DDRC_SCHED_RDWR_IDLE_GAP_SHIFT
6047 #undef DDRC_SCHED_RDWR_IDLE_GAP_MASK
6048 #define DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL 0x00002005
6049 #define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT 24
6050 #define DDRC_SCHED_RDWR_IDLE_GAP_MASK 0x7F000000U
6055 #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL
6056 #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT
6057 #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK
6058 #define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL 0x00002005
6059 #define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT 16
6060 #define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK 0x00FF0000U
6063 * Number of entries in the low priority transaction store is this value +
6064 * 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of ent
6065 * ries available for the high priority transaction store. Setting this to
6066 * maximum value allocates all entries to low priority transaction store. S
6067 * etting this to 0 allocates 1 entry to low priority transaction store and
6068 * the rest to high priority transaction store. Note: In ECC configuration
6069 * s, the numbers of write and low priority read credits issued is one less
6070 * than in the non-ECC case. One entry each is reserved in the write and l
6071 * ow-priority read CAMs for storing the RMW requests arising out of single
6072 * bit error correction RMW operation.
6074 #undef DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL
6075 #undef DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT
6076 #undef DDRC_SCHED_LPR_NUM_ENTRIES_MASK
6077 #define DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL 0x00002005
6078 #define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT 8
6079 #define DDRC_SCHED_LPR_NUM_ENTRIES_MASK 0x00003F00U
6082 * If true, bank is kept open only while there are page hit transactions av
6083 * ailable in the CAM to that bank. The last read or write command in the C
6084 * AM with a bank and page hit will be executed with auto-precharge if SCHE
6085 * D1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclos
6086 * e_timer is set to 0, explicit precharge (and not auto-precharge) may be
6087 * issued in some cases where there is a mode switch between Write and Read
6088 * or between LPR and HPR. The Read and Write commands that are executed a
6089 * s part of the ECC scrub requests are also executed without auto-precharg
6090 * e. If false, the bank remains open until there is a need to close it (to
6091 * open a different page, or for page timeout or refresh timeout) - also k
6092 * nown as open page policy. The open page policy can be overridden by sett
6093 * ing the per-command-autopre bit on the HIF interface (hif_cmd_autopre).
6094 * The pageclose feature provids a midway between Open and Close page polic
6095 * ies. FOR PERFORMANCE ONLY.
6097 #undef DDRC_SCHED_PAGECLOSE_DEFVAL
6098 #undef DDRC_SCHED_PAGECLOSE_SHIFT
6099 #undef DDRC_SCHED_PAGECLOSE_MASK
6100 #define DDRC_SCHED_PAGECLOSE_DEFVAL 0x00002005
6101 #define DDRC_SCHED_PAGECLOSE_SHIFT 2
6102 #define DDRC_SCHED_PAGECLOSE_MASK 0x00000004U
6105 * If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.
6107 #undef DDRC_SCHED_PREFER_WRITE_DEFVAL
6108 #undef DDRC_SCHED_PREFER_WRITE_SHIFT
6109 #undef DDRC_SCHED_PREFER_WRITE_MASK
6110 #define DDRC_SCHED_PREFER_WRITE_DEFVAL 0x00002005
6111 #define DDRC_SCHED_PREFER_WRITE_SHIFT 1
6112 #define DDRC_SCHED_PREFER_WRITE_MASK 0x00000002U
6115 * Active low signal. When asserted ('0'), all incoming transactions are fo
6116 * rced to low priority. This implies that all High Priority Read (HPR) and
6117 * Variable Priority Read commands (VPR) will be treated as Low Priority R
6118 * ead (LPR) commands. On the write side, all Variable Priority Write (VPW)
6119 * commands will be treated as Normal Priority Write (NPW) commands. Forci
6120 * ng the incoming transactions to low priority implicitly turns off Bypass
6121 * path for read commands. FOR PERFORMANCE ONLY.
6123 #undef DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL
6124 #undef DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT
6125 #undef DDRC_SCHED_FORCE_LOW_PRI_N_MASK
6126 #define DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL 0x00002005
6127 #define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT 0
6128 #define DDRC_SCHED_FORCE_LOW_PRI_N_MASK 0x00000001U
6131 * Number of transactions that are serviced once the LPR queue goes critica
6132 * l is the smaller of: - (a) This number - (b) Number of transactions avai
6133 * lable. Unit: Transaction. FOR PERFORMANCE ONLY.
6135 #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL
6136 #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT
6137 #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK
6138 #define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL 0x0F00007F
6139 #define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT 24
6140 #define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK 0xFF000000U
6143 * Number of clocks that the LPR queue can be starved before it goes critic
6144 * al. The minimum valid functional value for this register is 0x1. Program
6145 * ming it to 0x0 will disable the starvation functionality; during normal
6146 * operation, this function should not be disabled as it will cause excessi
6147 * ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
6149 #undef DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL
6150 #undef DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT
6151 #undef DDRC_PERFLPR1_LPR_MAX_STARVE_MASK
6152 #define DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL 0x0F00007F
6153 #define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT 0
6154 #define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK 0x0000FFFFU
6157 * Number of transactions that are serviced once the WR queue goes critical
6158 * is the smaller of: - (a) This number - (b) Number of transactions avail
6159 * able. Unit: Transaction. FOR PERFORMANCE ONLY.
6161 #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL
6162 #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT
6163 #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK
6164 #define DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL 0x0F00007F
6165 #define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT 24
6166 #define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK 0xFF000000U
6169 * Number of clocks that the WR queue can be starved before it goes critica
6170 * l. The minimum valid functional value for this register is 0x1. Programm
6171 * ing it to 0x0 will disable the starvation functionality; during normal o
6172 * peration, this function should not be disabled as it will cause excessiv
6173 * e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
6175 #undef DDRC_PERFWR1_W_MAX_STARVE_DEFVAL
6176 #undef DDRC_PERFWR1_W_MAX_STARVE_SHIFT
6177 #undef DDRC_PERFWR1_W_MAX_STARVE_MASK
6178 #define DDRC_PERFWR1_W_MAX_STARVE_DEFVAL 0x0F00007F
6179 #define DDRC_PERFWR1_W_MAX_STARVE_SHIFT 0
6180 #define DDRC_PERFWR1_W_MAX_STARVE_MASK 0x0000FFFFU
6183 * DQ nibble map for DQ bits [12-15] Present only in designs configured to
6186 #undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_DEFVAL
6187 #undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_SHIFT
6188 #undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_MASK
6189 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_DEFVAL 0x00000000
6190 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_SHIFT 24
6191 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_MASK 0xFF000000U
6194 * DQ nibble map for DQ bits [8-11] Present only in designs configured to s
6197 #undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_DEFVAL
6198 #undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_SHIFT
6199 #undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_MASK
6200 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_DEFVAL 0x00000000
6201 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_SHIFT 16
6202 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_MASK 0x00FF0000U
6205 * DQ nibble map for DQ bits [4-7] Present only in designs configured to su
6208 #undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_DEFVAL
6209 #undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_SHIFT
6210 #undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_MASK
6211 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_DEFVAL 0x00000000
6212 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_SHIFT 8
6213 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_MASK 0x0000FF00U
6216 * DQ nibble map for DQ bits [0-3] Present only in designs configured to su
6219 #undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_DEFVAL
6220 #undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_SHIFT
6221 #undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_MASK
6222 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_DEFVAL 0x00000000
6223 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_SHIFT 0
6224 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_MASK 0x000000FFU
6227 * DQ nibble map for DQ bits [28-31] Present only in designs configured to
6230 #undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_DEFVAL
6231 #undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_SHIFT
6232 #undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_MASK
6233 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_DEFVAL 0x00000000
6234 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_SHIFT 24
6235 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_MASK 0xFF000000U
6238 * DQ nibble map for DQ bits [24-27] Present only in designs configured to
6241 #undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_DEFVAL
6242 #undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_SHIFT
6243 #undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_MASK
6244 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_DEFVAL 0x00000000
6245 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_SHIFT 16
6246 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_MASK 0x00FF0000U
6249 * DQ nibble map for DQ bits [20-23] Present only in designs configured to
6252 #undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_DEFVAL
6253 #undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_SHIFT
6254 #undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_MASK
6255 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_DEFVAL 0x00000000
6256 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_SHIFT 8
6257 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_MASK 0x0000FF00U
6260 * DQ nibble map for DQ bits [16-19] Present only in designs configured to
6263 #undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_DEFVAL
6264 #undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_SHIFT
6265 #undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_MASK
6266 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_DEFVAL 0x00000000
6267 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_SHIFT 0
6268 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_MASK 0x000000FFU
6271 * DQ nibble map for DQ bits [44-47] Present only in designs configured to
6274 #undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_DEFVAL
6275 #undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_SHIFT
6276 #undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_MASK
6277 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_DEFVAL 0x00000000
6278 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_SHIFT 24
6279 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_MASK 0xFF000000U
6282 * DQ nibble map for DQ bits [40-43] Present only in designs configured to
6285 #undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_DEFVAL
6286 #undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_SHIFT
6287 #undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_MASK
6288 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_DEFVAL 0x00000000
6289 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_SHIFT 16
6290 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_MASK 0x00FF0000U
6293 * DQ nibble map for DQ bits [36-39] Present only in designs configured to
6296 #undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_DEFVAL
6297 #undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_SHIFT
6298 #undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_MASK
6299 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_DEFVAL 0x00000000
6300 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_SHIFT 8
6301 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_MASK 0x0000FF00U
6304 * DQ nibble map for DQ bits [32-35] Present only in designs configured to
6307 #undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_DEFVAL
6308 #undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_SHIFT
6309 #undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_MASK
6310 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_DEFVAL 0x00000000
6311 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_SHIFT 0
6312 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_MASK 0x000000FFU
6315 * DQ nibble map for DQ bits [60-63] Present only in designs configured to
6318 #undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_DEFVAL
6319 #undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_SHIFT
6320 #undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_MASK
6321 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_DEFVAL 0x00000000
6322 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_SHIFT 24
6323 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_MASK 0xFF000000U
6326 * DQ nibble map for DQ bits [56-59] Present only in designs configured to
6329 #undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_DEFVAL
6330 #undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_SHIFT
6331 #undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_MASK
6332 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_DEFVAL 0x00000000
6333 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_SHIFT 16
6334 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_MASK 0x00FF0000U
6337 * DQ nibble map for DQ bits [52-55] Present only in designs configured to
6340 #undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_DEFVAL
6341 #undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_SHIFT
6342 #undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_MASK
6343 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_DEFVAL 0x00000000
6344 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_SHIFT 8
6345 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_MASK 0x0000FF00U
6348 * DQ nibble map for DQ bits [48-51] Present only in designs configured to
6351 #undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_DEFVAL
6352 #undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_SHIFT
6353 #undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_MASK
6354 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_DEFVAL 0x00000000
6355 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_SHIFT 0
6356 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_MASK 0x000000FFU
6359 * DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf
6360 * igured to support DDR4.
6362 #undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_DEFVAL
6363 #undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_SHIFT
6364 #undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_MASK
6365 #define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_DEFVAL 0x00000000
6366 #define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_SHIFT 8
6367 #define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_MASK 0x0000FF00U
6370 * DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf
6371 * igured to support DDR4.
6373 #undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_DEFVAL
6374 #undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_SHIFT
6375 #undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_MASK
6376 #define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_DEFVAL 0x00000000
6377 #define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_SHIFT 0
6378 #define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_MASK 0x000000FFU
6381 * All even ranks have the same DQ mapping controled by DQMAP0-4 register a
6382 * s rank 0. This register provides DQ swap function for all odd ranks to s
6383 * upport CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap b
6384 * it 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank ba
6385 * sed DQ swapping 0: Enable rank based DQ swapping Present only in designs
6386 * configured to support DDR4.
6388 #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL
6389 #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT
6390 #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK
6391 #define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL
6392 #define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT 0
6393 #define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK 0x00000001U
6396 * When this is set to '0', auto-precharge is disabled for the flushed comm
6397 * and in a collision case. Collision cases are write followed by read to s
6398 * ame address, read followed by write to same address, or write followed b
6399 * y write to same address with DBG0.dis_wc bit = 1 (where same address com
6400 * parisons exclude the two address bits representing critical word). FOR D
6403 #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL
6404 #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT
6405 #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK
6406 #define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL 0x00000000
6407 #define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT 4
6408 #define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK 0x00000010U
6411 * When 1, disable write combine. FOR DEBUG ONLY
6413 #undef DDRC_DBG0_DIS_WC_DEFVAL
6414 #undef DDRC_DBG0_DIS_WC_SHIFT
6415 #undef DDRC_DBG0_DIS_WC_MASK
6416 #define DDRC_DBG0_DIS_WC_DEFVAL 0x00000000
6417 #define DDRC_DBG0_DIS_WC_SHIFT 0
6418 #define DDRC_DBG0_DIS_WC_MASK 0x00000001U
6421 * Setting this register bit to 1 allows refresh and ZQCS commands to be tr
6422 * iggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD.
6423 * zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignore
6424 * d by the uMCTL2 logic. Setting this register bit to 0 allows refresh and
6425 * ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_shor
6426 * t and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no
6427 * function, and are ignored by the uMCTL2 logic. This register is static,
6428 * and may only be changed when the DDRC reset signal, core_ddrc_rstn, is
6431 #undef DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL
6432 #undef DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT
6433 #undef DDRC_DBGCMD_HW_REF_ZQ_EN_MASK
6434 #define DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL 0x00000000
6435 #define DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT 31
6436 #define DDRC_DBGCMD_HW_REF_ZQ_EN_MASK 0x80000000U
6439 * Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ct
6440 * rlupd_req to the PHY. When this request is stored in the uMCTL2, the bit
6441 * is automatically cleared. This operation must only be performed when DF
6442 * IUPD0.dis_auto_ctrlupd=1.
6444 #undef DDRC_DBGCMD_CTRLUPD_DEFVAL
6445 #undef DDRC_DBGCMD_CTRLUPD_SHIFT
6446 #undef DDRC_DBGCMD_CTRLUPD_MASK
6447 #define DDRC_DBGCMD_CTRLUPD_DEFVAL 0x00000000
6448 #define DDRC_DBGCMD_CTRLUPD_SHIFT 5
6449 #define DDRC_DBGCMD_CTRLUPD_MASK 0x00000020U
6452 * Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (
6453 * ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When thi
6454 * s request is stored in the uMCTL2, the bit is automatically cleared. Thi
6455 * s operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recom
6456 * mended NOT to set this register bit if in Init operating mode. This regi
6457 * ster bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown
6458 * (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo
6461 #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL
6462 #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT
6463 #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK
6464 #define DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL 0x00000000
6465 #define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT 4
6466 #define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK 0x00000010U
6469 * Setting this register bit to 1 indicates to the uMCTL2 to issue a refres
6470 * h to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be
6471 * set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been s
6472 * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_
6473 * auto_refresh=1. It is recommended NOT to set this register bit if in Ini
6474 * t or Deep power-down operating modes or Maximum Power Saving Mode.
6476 #undef DDRC_DBGCMD_RANK1_REFRESH_DEFVAL
6477 #undef DDRC_DBGCMD_RANK1_REFRESH_SHIFT
6478 #undef DDRC_DBGCMD_RANK1_REFRESH_MASK
6479 #define DDRC_DBGCMD_RANK1_REFRESH_DEFVAL 0x00000000
6480 #define DDRC_DBGCMD_RANK1_REFRESH_SHIFT 1
6481 #define DDRC_DBGCMD_RANK1_REFRESH_MASK 0x00000002U
6484 * Setting this register bit to 1 indicates to the uMCTL2 to issue a refres
6485 * h to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be
6486 * set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been s
6487 * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_
6488 * auto_refresh=1. It is recommended NOT to set this register bit if in Ini
6489 * t or Deep power-down operating modes or Maximum Power Saving Mode.
6491 #undef DDRC_DBGCMD_RANK0_REFRESH_DEFVAL
6492 #undef DDRC_DBGCMD_RANK0_REFRESH_SHIFT
6493 #undef DDRC_DBGCMD_RANK0_REFRESH_MASK
6494 #define DDRC_DBGCMD_RANK0_REFRESH_DEFVAL 0x00000000
6495 #define DDRC_DBGCMD_RANK0_REFRESH_SHIFT 0
6496 #define DDRC_DBGCMD_RANK0_REFRESH_MASK 0x00000001U
6499 * Enable quasi-dynamic register programming outside reset. Program registe
6500 * r to 0 to enable quasi-dynamic programming. Set back register to 1 once
6501 * programming is done.
6503 #undef DDRC_SWCTL_SW_DONE_DEFVAL
6504 #undef DDRC_SWCTL_SW_DONE_SHIFT
6505 #undef DDRC_SWCTL_SW_DONE_MASK
6506 #define DDRC_SWCTL_SW_DONE_DEFVAL
6507 #define DDRC_SWCTL_SW_DONE_SHIFT 0
6508 #define DDRC_SWCTL_SW_DONE_MASK 0x00000001U
6511 * Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expand
6512 * s every AXI burst into multiple HIF commands, using the memory burst len
6513 * gth as a unit. If set to 1, then XPI will use half of the memory burst l
6514 * ength as a unit. This applies to both reads and writes. When MSTR.data_b
6515 * us_width==00, setting bl_exp_mode to 1 has no effect. This can be used i
6516 * n cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.d
6517 * is_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd
6518 * _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionali
6519 * ty is not supported in the following cases: - UMCTL2_PARTIAL_WR=0 - UMCT
6520 * L2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 an
6521 * d MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only) - UMCTL2_PARTIAL_WR=1, MST
6522 * R.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burs
6523 * t_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPAR
6524 * CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared
6527 #undef DDRC_PCCFG_BL_EXP_MODE_DEFVAL
6528 #undef DDRC_PCCFG_BL_EXP_MODE_SHIFT
6529 #undef DDRC_PCCFG_BL_EXP_MODE_MASK
6530 #define DDRC_PCCFG_BL_EXP_MODE_DEFVAL 0x00000000
6531 #define DDRC_PCCFG_BL_EXP_MODE_SHIFT 8
6532 #define DDRC_PCCFG_BL_EXP_MODE_MASK 0x00000100U
6535 * Page match four limit. If set to 1, limits the number of consecutive sam
6536 * e page DDRC transactions that can be granted by the Port Arbiter to four
6537 * when Page Match feature is enabled. If set to 0, there is no limit impo
6538 * sed on number of consecutive same page DDRC transactions.
6540 #undef DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL
6541 #undef DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT
6542 #undef DDRC_PCCFG_PAGEMATCH_LIMIT_MASK
6543 #define DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL 0x00000000
6544 #define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT 4
6545 #define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK 0x00000010U
6548 * If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_l
6549 * pr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (aw
6550 * urgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_
6551 * go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a
6552 * t DDRC are driven to 1b'0.
6554 #undef DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL
6555 #undef DDRC_PCCFG_GO2CRITICAL_EN_SHIFT
6556 #undef DDRC_PCCFG_GO2CRITICAL_EN_MASK
6557 #define DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL 0x00000000
6558 #define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT 0
6559 #define DDRC_PCCFG_GO2CRITICAL_EN_MASK 0x00000001U
6562 * If set to 1, enables the Page Match feature. If enabled, once a requesti
6563 * ng port is granted, the port is continued to be granted if the following
6564 * immediate commands are to the same memory page (same bank and same row)
6565 * . See also related PCCFG.pagematch_limit register.
6567 #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL
6568 #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT
6569 #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK
6570 #define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000
6571 #define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT 14
6572 #define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U
6575 * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
6576 * bled and arurgent is asserted by the master, that port becomes the highe
6577 * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
6578 * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
6579 * urgent signal can be asserted anytime and as long as required which is i
6580 * ndependent of address handshaking (it is not associated with any particu
6583 #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL
6584 #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT
6585 #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK
6586 #define DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL 0x00000000
6587 #define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT 13
6588 #define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK 0x00002000U
6591 * If set to 1, enables aging function for the read channel of the port.
6593 #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL
6594 #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT
6595 #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK
6596 #define DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL 0x00000000
6597 #define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT 12
6598 #define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK 0x00001000U
6601 * Determines the initial load value of read aging counters. These counters
6602 * will be parallel loaded after reset, or after each grant to the corresp
6603 * onding port. The aging counters down-count every clock cycle where the p
6604 * ort is requesting but not granted. The higher significant 5-bits of the
6605 * read aging counter sets the priority of the read channel of a given port
6606 * . Port's priority will increase as the higher significant 5-bits of the
6607 * counter starts to decrease. When the aging counter becomes 0, the corres
6608 * ponding port channel will have the highest priority level (timeout condi
6609 * tion - Priority0). For multi-port configurations, the aging counters can
6610 * not be used to set port priorities when external dynamic priority inputs
6611 * (arqos) are enabled (timeout is still applicable). For single port conf
6612 * igurations, the aging counters are only used when they timeout (become 0
6613 * ) to force read-write direction switching. In this case, external dynami
6614 * c priority input, arqos (for reads only) can still be used to set the DD
6615 * RC read priority (2 priority levels: low priority read - LPR, high prior
6616 * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
6617 * s register field are tied internally to 2'b00.
6619 #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL
6620 #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT
6621 #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK
6622 #define DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL 0x00000000
6623 #define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT 0
6624 #define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK 0x000003FFU
6627 * If set to 1, enables the Page Match feature. If enabled, once a requesti
6628 * ng port is granted, the port is continued to be granted if the following
6629 * immediate commands are to the same memory page (same bank and same row)
6630 * . See also related PCCFG.pagematch_limit register.
6632 #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL
6633 #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT
6634 #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK
6635 #define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000
6636 #define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT 14
6637 #define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U
6640 * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
6641 * bled and awurgent is asserted by the master, that port becomes the highe
6642 * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
6643 * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
6644 * serted anytime and as long as required which is independent of address h
6645 * andshaking (it is not associated with any particular command).
6647 #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL
6648 #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT
6649 #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK
6650 #define DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL 0x00004000
6651 #define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT 13
6652 #define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK 0x00002000U
6655 * If set to 1, enables aging function for the write channel of the port.
6657 #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL
6658 #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT
6659 #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK
6660 #define DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL 0x00004000
6661 #define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT 12
6662 #define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK 0x00001000U
6665 * Determines the initial load value of write aging counters. These counter
6666 * s will be parallel loaded after reset, or after each grant to the corres
6667 * ponding port. The aging counters down-count every clock cycle where the
6668 * port is requesting but not granted. The higher significant 5-bits of the
6669 * write aging counter sets the initial priority of the write channel of a
6670 * given port. Port's priority will increase as the higher significant 5-b
6671 * its of the counter starts to decrease. When the aging counter becomes 0,
6672 * the corresponding port channel will have the highest priority level. Fo
6673 * r multi-port configurations, the aging counters cannot be used to set po
6674 * rt priorities when external dynamic priority inputs (awqos) are enabled
6675 * (timeout is still applicable). For single port configurations, the aging
6676 * counters are only used when they timeout (become 0) to force read-write
6677 * direction switching. Note: The two LSBs of this register field are tied
6678 * internally to 2'b00.
6680 #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL
6681 #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT
6682 #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK
6683 #define DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL 0x00004000
6684 #define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT 0
6685 #define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK 0x000003FFU
6690 #undef DDRC_PCTRL_0_PORT_EN_DEFVAL
6691 #undef DDRC_PCTRL_0_PORT_EN_SHIFT
6692 #undef DDRC_PCTRL_0_PORT_EN_MASK
6693 #define DDRC_PCTRL_0_PORT_EN_DEFVAL
6694 #define DDRC_PCTRL_0_PORT_EN_SHIFT 0
6695 #define DDRC_PCTRL_0_PORT_EN_MASK 0x00000001U
6698 * This bitfield indicates the traffic class of region 1. Valid values are:
6699 * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
6700 * maps to the blue address queue. In this case, valid values are 0: LPR a
6701 * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
6702 * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
6705 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL
6706 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT
6707 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK
6708 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL 0x00000000
6709 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT 20
6710 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK 0x00300000U
6713 * This bitfield indicates the traffic class of region 0. Valid values are:
6714 * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
6715 * maps to the blue address queue. In this case, valid values are: 0: LPR
6716 * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
6717 * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
6720 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL
6721 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT
6722 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK
6723 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL 0x00000000
6724 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT 16
6725 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK 0x00030000U
6728 * Separation level1 indicating the end of region0 mapping; start of region
6729 * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
6730 * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
6731 * lues are used directly as port priorities, where the higher the value co
6732 * rresponds to higher port priority. All of the map_level* registers must
6733 * be set to distinct values.
6735 #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL
6736 #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT
6737 #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK
6738 #define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL 0x00000000
6739 #define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT 0
6740 #define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK 0x0000000FU
6743 * Specifies the timeout value for transactions mapped to the red address q
6746 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL
6747 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT
6748 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK
6749 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000
6750 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT 16
6751 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U
6754 * Specifies the timeout value for transactions mapped to the blue address
6757 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL
6758 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT
6759 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK
6760 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000
6761 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT 0
6762 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU
6765 * If set to 1, enables the Page Match feature. If enabled, once a requesti
6766 * ng port is granted, the port is continued to be granted if the following
6767 * immediate commands are to the same memory page (same bank and same row)
6768 * . See also related PCCFG.pagematch_limit register.
6770 #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL
6771 #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT
6772 #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK
6773 #define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000
6774 #define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT 14
6775 #define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U
6778 * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
6779 * bled and arurgent is asserted by the master, that port becomes the highe
6780 * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
6781 * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
6782 * urgent signal can be asserted anytime and as long as required which is i
6783 * ndependent of address handshaking (it is not associated with any particu
6786 #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL
6787 #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT
6788 #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK
6789 #define DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL 0x00000000
6790 #define DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT 13
6791 #define DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK 0x00002000U
6794 * If set to 1, enables aging function for the read channel of the port.
6796 #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL
6797 #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT
6798 #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK
6799 #define DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL 0x00000000
6800 #define DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT 12
6801 #define DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK 0x00001000U
6804 * Determines the initial load value of read aging counters. These counters
6805 * will be parallel loaded after reset, or after each grant to the corresp
6806 * onding port. The aging counters down-count every clock cycle where the p
6807 * ort is requesting but not granted. The higher significant 5-bits of the
6808 * read aging counter sets the priority of the read channel of a given port
6809 * . Port's priority will increase as the higher significant 5-bits of the
6810 * counter starts to decrease. When the aging counter becomes 0, the corres
6811 * ponding port channel will have the highest priority level (timeout condi
6812 * tion - Priority0). For multi-port configurations, the aging counters can
6813 * not be used to set port priorities when external dynamic priority inputs
6814 * (arqos) are enabled (timeout is still applicable). For single port conf
6815 * igurations, the aging counters are only used when they timeout (become 0
6816 * ) to force read-write direction switching. In this case, external dynami
6817 * c priority input, arqos (for reads only) can still be used to set the DD
6818 * RC read priority (2 priority levels: low priority read - LPR, high prior
6819 * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
6820 * s register field are tied internally to 2'b00.
6822 #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL
6823 #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT
6824 #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK
6825 #define DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL 0x00000000
6826 #define DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT 0
6827 #define DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK 0x000003FFU
6830 * If set to 1, enables the Page Match feature. If enabled, once a requesti
6831 * ng port is granted, the port is continued to be granted if the following
6832 * immediate commands are to the same memory page (same bank and same row)
6833 * . See also related PCCFG.pagematch_limit register.
6835 #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL
6836 #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT
6837 #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK
6838 #define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000
6839 #define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT 14
6840 #define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U
6843 * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
6844 * bled and awurgent is asserted by the master, that port becomes the highe
6845 * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
6846 * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
6847 * serted anytime and as long as required which is independent of address h
6848 * andshaking (it is not associated with any particular command).
6850 #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL
6851 #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT
6852 #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK
6853 #define DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL 0x00004000
6854 #define DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT 13
6855 #define DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK 0x00002000U
6858 * If set to 1, enables aging function for the write channel of the port.
6860 #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL
6861 #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT
6862 #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK
6863 #define DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL 0x00004000
6864 #define DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT 12
6865 #define DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK 0x00001000U
6868 * Determines the initial load value of write aging counters. These counter
6869 * s will be parallel loaded after reset, or after each grant to the corres
6870 * ponding port. The aging counters down-count every clock cycle where the
6871 * port is requesting but not granted. The higher significant 5-bits of the
6872 * write aging counter sets the initial priority of the write channel of a
6873 * given port. Port's priority will increase as the higher significant 5-b
6874 * its of the counter starts to decrease. When the aging counter becomes 0,
6875 * the corresponding port channel will have the highest priority level. Fo
6876 * r multi-port configurations, the aging counters cannot be used to set po
6877 * rt priorities when external dynamic priority inputs (awqos) are enabled
6878 * (timeout is still applicable). For single port configurations, the aging
6879 * counters are only used when they timeout (become 0) to force read-write
6880 * direction switching. Note: The two LSBs of this register field are tied
6881 * internally to 2'b00.
6883 #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL
6884 #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT
6885 #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK
6886 #define DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL 0x00004000
6887 #define DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT 0
6888 #define DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK 0x000003FFU
6893 #undef DDRC_PCTRL_1_PORT_EN_DEFVAL
6894 #undef DDRC_PCTRL_1_PORT_EN_SHIFT
6895 #undef DDRC_PCTRL_1_PORT_EN_MASK
6896 #define DDRC_PCTRL_1_PORT_EN_DEFVAL
6897 #define DDRC_PCTRL_1_PORT_EN_SHIFT 0
6898 #define DDRC_PCTRL_1_PORT_EN_MASK 0x00000001U
6901 * This bitfield indicates the traffic class of region2. For dual address q
6902 * ueue configurations, region2 maps to the red address queue. Valid values
6903 * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN
6904 * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali
6905 * ased to LPR traffic.
6907 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL
6908 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT
6909 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK
6910 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL 0x02000E00
6911 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT 24
6912 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK 0x03000000U
6915 * This bitfield indicates the traffic class of region 1. Valid values are:
6916 * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
6917 * maps to the blue address queue. In this case, valid values are 0: LPR a
6918 * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
6919 * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
6922 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL
6923 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT
6924 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK
6925 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL 0x02000E00
6926 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT 20
6927 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK 0x00300000U
6930 * This bitfield indicates the traffic class of region 0. Valid values are:
6931 * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
6932 * maps to the blue address queue. In this case, valid values are: 0: LPR
6933 * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
6934 * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
6937 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL
6938 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT
6939 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK
6940 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL 0x02000E00
6941 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT 16
6942 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK 0x00030000U
6945 * Separation level2 indicating the end of region1 mapping; start of region
6946 * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi
6947 * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note
6948 * that for PA, arqos values are used directly as port priorities, where t
6949 * he higher the value corresponds to higher port priority. All of the map_
6950 * level* registers must be set to distinct values.
6952 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL
6953 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT
6954 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK
6955 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00
6956 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT 8
6957 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK 0x00000F00U
6960 * Separation level1 indicating the end of region0 mapping; start of region
6961 * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
6962 * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
6963 * lues are used directly as port priorities, where the higher the value co
6964 * rresponds to higher port priority. All of the map_level* registers must
6965 * be set to distinct values.
6967 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL
6968 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT
6969 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK
6970 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00
6971 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT 0
6972 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK 0x0000000FU
6975 * Specifies the timeout value for transactions mapped to the red address q
6978 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL
6979 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT
6980 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK
6981 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000
6982 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT 16
6983 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U
6986 * Specifies the timeout value for transactions mapped to the blue address
6989 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL
6990 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT
6991 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK
6992 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000
6993 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT 0
6994 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU
6997 * If set to 1, enables the Page Match feature. If enabled, once a requesti
6998 * ng port is granted, the port is continued to be granted if the following
6999 * immediate commands are to the same memory page (same bank and same row)
7000 * . See also related PCCFG.pagematch_limit register.
7002 #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL
7003 #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT
7004 #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK
7005 #define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000
7006 #define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT 14
7007 #define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U
7010 * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
7011 * bled and arurgent is asserted by the master, that port becomes the highe
7012 * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
7013 * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
7014 * urgent signal can be asserted anytime and as long as required which is i
7015 * ndependent of address handshaking (it is not associated with any particu
7018 #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL
7019 #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT
7020 #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK
7021 #define DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL 0x00000000
7022 #define DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT 13
7023 #define DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK 0x00002000U
7026 * If set to 1, enables aging function for the read channel of the port.
7028 #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL
7029 #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT
7030 #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK
7031 #define DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL 0x00000000
7032 #define DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT 12
7033 #define DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK 0x00001000U
7036 * Determines the initial load value of read aging counters. These counters
7037 * will be parallel loaded after reset, or after each grant to the corresp
7038 * onding port. The aging counters down-count every clock cycle where the p
7039 * ort is requesting but not granted. The higher significant 5-bits of the
7040 * read aging counter sets the priority of the read channel of a given port
7041 * . Port's priority will increase as the higher significant 5-bits of the
7042 * counter starts to decrease. When the aging counter becomes 0, the corres
7043 * ponding port channel will have the highest priority level (timeout condi
7044 * tion - Priority0). For multi-port configurations, the aging counters can
7045 * not be used to set port priorities when external dynamic priority inputs
7046 * (arqos) are enabled (timeout is still applicable). For single port conf
7047 * igurations, the aging counters are only used when they timeout (become 0
7048 * ) to force read-write direction switching. In this case, external dynami
7049 * c priority input, arqos (for reads only) can still be used to set the DD
7050 * RC read priority (2 priority levels: low priority read - LPR, high prior
7051 * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
7052 * s register field are tied internally to 2'b00.
7054 #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL
7055 #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT
7056 #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK
7057 #define DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL 0x00000000
7058 #define DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT 0
7059 #define DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK 0x000003FFU
7062 * If set to 1, enables the Page Match feature. If enabled, once a requesti
7063 * ng port is granted, the port is continued to be granted if the following
7064 * immediate commands are to the same memory page (same bank and same row)
7065 * . See also related PCCFG.pagematch_limit register.
7067 #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL
7068 #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT
7069 #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK
7070 #define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000
7071 #define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT 14
7072 #define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U
7075 * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
7076 * bled and awurgent is asserted by the master, that port becomes the highe
7077 * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
7078 * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
7079 * serted anytime and as long as required which is independent of address h
7080 * andshaking (it is not associated with any particular command).
7082 #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL
7083 #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT
7084 #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK
7085 #define DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL 0x00004000
7086 #define DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT 13
7087 #define DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK 0x00002000U
7090 * If set to 1, enables aging function for the write channel of the port.
7092 #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL
7093 #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT
7094 #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK
7095 #define DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL 0x00004000
7096 #define DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT 12
7097 #define DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK 0x00001000U
7100 * Determines the initial load value of write aging counters. These counter
7101 * s will be parallel loaded after reset, or after each grant to the corres
7102 * ponding port. The aging counters down-count every clock cycle where the
7103 * port is requesting but not granted. The higher significant 5-bits of the
7104 * write aging counter sets the initial priority of the write channel of a
7105 * given port. Port's priority will increase as the higher significant 5-b
7106 * its of the counter starts to decrease. When the aging counter becomes 0,
7107 * the corresponding port channel will have the highest priority level. Fo
7108 * r multi-port configurations, the aging counters cannot be used to set po
7109 * rt priorities when external dynamic priority inputs (awqos) are enabled
7110 * (timeout is still applicable). For single port configurations, the aging
7111 * counters are only used when they timeout (become 0) to force read-write
7112 * direction switching. Note: The two LSBs of this register field are tied
7113 * internally to 2'b00.
7115 #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL
7116 #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT
7117 #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK
7118 #define DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL 0x00004000
7119 #define DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT 0
7120 #define DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK 0x000003FFU
7125 #undef DDRC_PCTRL_2_PORT_EN_DEFVAL
7126 #undef DDRC_PCTRL_2_PORT_EN_SHIFT
7127 #undef DDRC_PCTRL_2_PORT_EN_MASK
7128 #define DDRC_PCTRL_2_PORT_EN_DEFVAL
7129 #define DDRC_PCTRL_2_PORT_EN_SHIFT 0
7130 #define DDRC_PCTRL_2_PORT_EN_MASK 0x00000001U
7133 * This bitfield indicates the traffic class of region2. For dual address q
7134 * ueue configurations, region2 maps to the red address queue. Valid values
7135 * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN
7136 * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali
7137 * ased to LPR traffic.
7139 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL
7140 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT
7141 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK
7142 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL 0x02000E00
7143 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT 24
7144 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK 0x03000000U
7147 * This bitfield indicates the traffic class of region 1. Valid values are:
7148 * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
7149 * maps to the blue address queue. In this case, valid values are 0: LPR a
7150 * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
7151 * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
7154 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL
7155 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT
7156 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK
7157 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL 0x02000E00
7158 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT 20
7159 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK 0x00300000U
7162 * This bitfield indicates the traffic class of region 0. Valid values are:
7163 * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
7164 * maps to the blue address queue. In this case, valid values are: 0: LPR
7165 * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
7166 * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
7169 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL
7170 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT
7171 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK
7172 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL 0x02000E00
7173 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT 16
7174 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK 0x00030000U
7177 * Separation level2 indicating the end of region1 mapping; start of region
7178 * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi
7179 * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note
7180 * that for PA, arqos values are used directly as port priorities, where t
7181 * he higher the value corresponds to higher port priority. All of the map_
7182 * level* registers must be set to distinct values.
7184 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL
7185 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT
7186 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK
7187 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00
7188 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT 8
7189 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK 0x00000F00U
7192 * Separation level1 indicating the end of region0 mapping; start of region
7193 * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
7194 * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
7195 * lues are used directly as port priorities, where the higher the value co
7196 * rresponds to higher port priority. All of the map_level* registers must
7197 * be set to distinct values.
7199 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL
7200 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT
7201 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK
7202 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00
7203 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT 0
7204 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK 0x0000000FU
7207 * Specifies the timeout value for transactions mapped to the red address q
7210 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL
7211 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT
7212 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK
7213 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000
7214 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT 16
7215 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U
7218 * Specifies the timeout value for transactions mapped to the blue address
7221 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL
7222 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT
7223 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK
7224 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000
7225 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT 0
7226 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU
7229 * If set to 1, enables the Page Match feature. If enabled, once a requesti
7230 * ng port is granted, the port is continued to be granted if the following
7231 * immediate commands are to the same memory page (same bank and same row)
7232 * . See also related PCCFG.pagematch_limit register.
7234 #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL
7235 #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT
7236 #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK
7237 #define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000
7238 #define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT 14
7239 #define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U
7242 * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
7243 * bled and arurgent is asserted by the master, that port becomes the highe
7244 * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
7245 * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
7246 * urgent signal can be asserted anytime and as long as required which is i
7247 * ndependent of address handshaking (it is not associated with any particu
7250 #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL
7251 #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT
7252 #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK
7253 #define DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL 0x00000000
7254 #define DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT 13
7255 #define DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK 0x00002000U
7258 * If set to 1, enables aging function for the read channel of the port.
7260 #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL
7261 #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT
7262 #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK
7263 #define DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL 0x00000000
7264 #define DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT 12
7265 #define DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK 0x00001000U
7268 * Determines the initial load value of read aging counters. These counters
7269 * will be parallel loaded after reset, or after each grant to the corresp
7270 * onding port. The aging counters down-count every clock cycle where the p
7271 * ort is requesting but not granted. The higher significant 5-bits of the
7272 * read aging counter sets the priority of the read channel of a given port
7273 * . Port's priority will increase as the higher significant 5-bits of the
7274 * counter starts to decrease. When the aging counter becomes 0, the corres
7275 * ponding port channel will have the highest priority level (timeout condi
7276 * tion - Priority0). For multi-port configurations, the aging counters can
7277 * not be used to set port priorities when external dynamic priority inputs
7278 * (arqos) are enabled (timeout is still applicable). For single port conf
7279 * igurations, the aging counters are only used when they timeout (become 0
7280 * ) to force read-write direction switching. In this case, external dynami
7281 * c priority input, arqos (for reads only) can still be used to set the DD
7282 * RC read priority (2 priority levels: low priority read - LPR, high prior
7283 * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
7284 * s register field are tied internally to 2'b00.
7286 #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL
7287 #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT
7288 #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK
7289 #define DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL 0x00000000
7290 #define DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT 0
7291 #define DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK 0x000003FFU
7294 * If set to 1, enables the Page Match feature. If enabled, once a requesti
7295 * ng port is granted, the port is continued to be granted if the following
7296 * immediate commands are to the same memory page (same bank and same row)
7297 * . See also related PCCFG.pagematch_limit register.
7299 #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL
7300 #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT
7301 #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK
7302 #define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000
7303 #define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT 14
7304 #define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U
7307 * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
7308 * bled and awurgent is asserted by the master, that port becomes the highe
7309 * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
7310 * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
7311 * serted anytime and as long as required which is independent of address h
7312 * andshaking (it is not associated with any particular command).
7314 #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL
7315 #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT
7316 #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK
7317 #define DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL 0x00004000
7318 #define DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT 13
7319 #define DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK 0x00002000U
7322 * If set to 1, enables aging function for the write channel of the port.
7324 #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL
7325 #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT
7326 #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK
7327 #define DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL 0x00004000
7328 #define DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT 12
7329 #define DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK 0x00001000U
7332 * Determines the initial load value of write aging counters. These counter
7333 * s will be parallel loaded after reset, or after each grant to the corres
7334 * ponding port. The aging counters down-count every clock cycle where the
7335 * port is requesting but not granted. The higher significant 5-bits of the
7336 * write aging counter sets the initial priority of the write channel of a
7337 * given port. Port's priority will increase as the higher significant 5-b
7338 * its of the counter starts to decrease. When the aging counter becomes 0,
7339 * the corresponding port channel will have the highest priority level. Fo
7340 * r multi-port configurations, the aging counters cannot be used to set po
7341 * rt priorities when external dynamic priority inputs (awqos) are enabled
7342 * (timeout is still applicable). For single port configurations, the aging
7343 * counters are only used when they timeout (become 0) to force read-write
7344 * direction switching. Note: The two LSBs of this register field are tied
7345 * internally to 2'b00.
7347 #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL
7348 #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT
7349 #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK
7350 #define DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL 0x00004000
7351 #define DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT 0
7352 #define DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK 0x000003FFU
7357 #undef DDRC_PCTRL_3_PORT_EN_DEFVAL
7358 #undef DDRC_PCTRL_3_PORT_EN_SHIFT
7359 #undef DDRC_PCTRL_3_PORT_EN_MASK
7360 #define DDRC_PCTRL_3_PORT_EN_DEFVAL
7361 #define DDRC_PCTRL_3_PORT_EN_SHIFT 0
7362 #define DDRC_PCTRL_3_PORT_EN_MASK 0x00000001U
7365 * This bitfield indicates the traffic class of region 1. Valid values are:
7366 * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
7367 * maps to the blue address queue. In this case, valid values are 0: LPR a
7368 * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
7369 * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
7372 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL
7373 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT
7374 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK
7375 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL 0x00000000
7376 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT 20
7377 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK 0x00300000U
7380 * This bitfield indicates the traffic class of region 0. Valid values are:
7381 * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
7382 * maps to the blue address queue. In this case, valid values are: 0: LPR
7383 * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
7384 * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
7387 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL
7388 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT
7389 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK
7390 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL 0x00000000
7391 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT 16
7392 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK 0x00030000U
7395 * Separation level1 indicating the end of region0 mapping; start of region
7396 * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
7397 * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
7398 * lues are used directly as port priorities, where the higher the value co
7399 * rresponds to higher port priority. All of the map_level* registers must
7400 * be set to distinct values.
7402 #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL
7403 #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT
7404 #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK
7405 #define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL 0x00000000
7406 #define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT 0
7407 #define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK 0x0000000FU
7410 * Specifies the timeout value for transactions mapped to the red address q
7413 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL
7414 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT
7415 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK
7416 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000
7417 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT 16
7418 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U
7421 * Specifies the timeout value for transactions mapped to the blue address
7424 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL
7425 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT
7426 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK
7427 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000
7428 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT 0
7429 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU
7432 * This bitfield indicates the traffic class of region 1. Valid values are:
7433 * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
7434 * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW
7437 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL
7438 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT
7439 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK
7440 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL 0x00000000
7441 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT 20
7442 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK 0x00300000U
7445 * This bitfield indicates the traffic class of region 0. Valid values are:
7446 * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
7447 * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW
7450 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL
7451 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT
7452 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK
7453 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL 0x00000000
7454 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT 16
7455 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK 0x00030000U
7458 * Separation level indicating the end of region0 mapping; start of region0
7459 * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos
7460 * . Note that for PA, awqos values are used directly as port priorities, w
7461 * here the higher the value corresponds to higher port priority.
7463 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL
7464 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT
7465 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK
7466 #define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL 0x00000000
7467 #define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT 0
7468 #define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK 0x0000000FU
7471 * Specifies the timeout value for write transactions.
7473 #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL
7474 #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT
7475 #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK
7476 #define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL
7477 #define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT 0
7478 #define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK 0x000007FFU
7481 * If set to 1, enables the Page Match feature. If enabled, once a requesti
7482 * ng port is granted, the port is continued to be granted if the following
7483 * immediate commands are to the same memory page (same bank and same row)
7484 * . See also related PCCFG.pagematch_limit register.
7486 #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL
7487 #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT
7488 #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK
7489 #define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000
7490 #define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT 14
7491 #define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U
7494 * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
7495 * bled and arurgent is asserted by the master, that port becomes the highe
7496 * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
7497 * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
7498 * urgent signal can be asserted anytime and as long as required which is i
7499 * ndependent of address handshaking (it is not associated with any particu
7502 #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL
7503 #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT
7504 #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK
7505 #define DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL 0x00000000
7506 #define DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT 13
7507 #define DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK 0x00002000U
7510 * If set to 1, enables aging function for the read channel of the port.
7512 #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL
7513 #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT
7514 #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK
7515 #define DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL 0x00000000
7516 #define DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT 12
7517 #define DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK 0x00001000U
7520 * Determines the initial load value of read aging counters. These counters
7521 * will be parallel loaded after reset, or after each grant to the corresp
7522 * onding port. The aging counters down-count every clock cycle where the p
7523 * ort is requesting but not granted. The higher significant 5-bits of the
7524 * read aging counter sets the priority of the read channel of a given port
7525 * . Port's priority will increase as the higher significant 5-bits of the
7526 * counter starts to decrease. When the aging counter becomes 0, the corres
7527 * ponding port channel will have the highest priority level (timeout condi
7528 * tion - Priority0). For multi-port configurations, the aging counters can
7529 * not be used to set port priorities when external dynamic priority inputs
7530 * (arqos) are enabled (timeout is still applicable). For single port conf
7531 * igurations, the aging counters are only used when they timeout (become 0
7532 * ) to force read-write direction switching. In this case, external dynami
7533 * c priority input, arqos (for reads only) can still be used to set the DD
7534 * RC read priority (2 priority levels: low priority read - LPR, high prior
7535 * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
7536 * s register field are tied internally to 2'b00.
7538 #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL
7539 #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT
7540 #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK
7541 #define DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL 0x00000000
7542 #define DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT 0
7543 #define DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK 0x000003FFU
7546 * If set to 1, enables the Page Match feature. If enabled, once a requesti
7547 * ng port is granted, the port is continued to be granted if the following
7548 * immediate commands are to the same memory page (same bank and same row)
7549 * . See also related PCCFG.pagematch_limit register.
7551 #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL
7552 #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT
7553 #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK
7554 #define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000
7555 #define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT 14
7556 #define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U
7559 * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
7560 * bled and awurgent is asserted by the master, that port becomes the highe
7561 * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
7562 * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
7563 * serted anytime and as long as required which is independent of address h
7564 * andshaking (it is not associated with any particular command).
7566 #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL
7567 #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT
7568 #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK
7569 #define DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL 0x00004000
7570 #define DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT 13
7571 #define DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK 0x00002000U
7574 * If set to 1, enables aging function for the write channel of the port.
7576 #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL
7577 #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT
7578 #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK
7579 #define DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL 0x00004000
7580 #define DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT 12
7581 #define DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK 0x00001000U
7584 * Determines the initial load value of write aging counters. These counter
7585 * s will be parallel loaded after reset, or after each grant to the corres
7586 * ponding port. The aging counters down-count every clock cycle where the
7587 * port is requesting but not granted. The higher significant 5-bits of the
7588 * write aging counter sets the initial priority of the write channel of a
7589 * given port. Port's priority will increase as the higher significant 5-b
7590 * its of the counter starts to decrease. When the aging counter becomes 0,
7591 * the corresponding port channel will have the highest priority level. Fo
7592 * r multi-port configurations, the aging counters cannot be used to set po
7593 * rt priorities when external dynamic priority inputs (awqos) are enabled
7594 * (timeout is still applicable). For single port configurations, the aging
7595 * counters are only used when they timeout (become 0) to force read-write
7596 * direction switching. Note: The two LSBs of this register field are tied
7597 * internally to 2'b00.
7599 #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL
7600 #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT
7601 #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK
7602 #define DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL 0x00004000
7603 #define DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT 0
7604 #define DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK 0x000003FFU
7609 #undef DDRC_PCTRL_4_PORT_EN_DEFVAL
7610 #undef DDRC_PCTRL_4_PORT_EN_SHIFT
7611 #undef DDRC_PCTRL_4_PORT_EN_MASK
7612 #define DDRC_PCTRL_4_PORT_EN_DEFVAL
7613 #define DDRC_PCTRL_4_PORT_EN_SHIFT 0
7614 #define DDRC_PCTRL_4_PORT_EN_MASK 0x00000001U
7617 * This bitfield indicates the traffic class of region 1. Valid values are:
7618 * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
7619 * maps to the blue address queue. In this case, valid values are 0: LPR a
7620 * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
7621 * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
7624 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL
7625 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT
7626 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK
7627 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL 0x00000000
7628 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT 20
7629 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK 0x00300000U
7632 * This bitfield indicates the traffic class of region 0. Valid values are:
7633 * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
7634 * maps to the blue address queue. In this case, valid values are: 0: LPR
7635 * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
7636 * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
7639 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL
7640 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT
7641 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK
7642 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL 0x00000000
7643 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT 16
7644 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK 0x00030000U
7647 * Separation level1 indicating the end of region0 mapping; start of region
7648 * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
7649 * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
7650 * lues are used directly as port priorities, where the higher the value co
7651 * rresponds to higher port priority. All of the map_level* registers must
7652 * be set to distinct values.
7654 #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL
7655 #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT
7656 #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK
7657 #define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL 0x00000000
7658 #define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT 0
7659 #define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK 0x0000000FU
7662 * Specifies the timeout value for transactions mapped to the red address q
7665 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL
7666 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT
7667 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK
7668 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000
7669 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT 16
7670 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U
7673 * Specifies the timeout value for transactions mapped to the blue address
7676 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL
7677 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT
7678 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK
7679 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000
7680 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT 0
7681 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU
7684 * This bitfield indicates the traffic class of region 1. Valid values are:
7685 * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
7686 * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW
7689 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL
7690 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT
7691 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK
7692 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL 0x00000000
7693 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT 20
7694 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK 0x00300000U
7697 * This bitfield indicates the traffic class of region 0. Valid values are:
7698 * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
7699 * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW
7702 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL
7703 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT
7704 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK
7705 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL 0x00000000
7706 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT 16
7707 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK 0x00030000U
7710 * Separation level indicating the end of region0 mapping; start of region0
7711 * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos
7712 * . Note that for PA, awqos values are used directly as port priorities, w
7713 * here the higher the value corresponds to higher port priority.
7715 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL
7716 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT
7717 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK
7718 #define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL 0x00000000
7719 #define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT 0
7720 #define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK 0x0000000FU
7723 * Specifies the timeout value for write transactions.
7725 #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL
7726 #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT
7727 #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK
7728 #define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL
7729 #define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT 0
7730 #define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK 0x000007FFU
7733 * If set to 1, enables the Page Match feature. If enabled, once a requesti
7734 * ng port is granted, the port is continued to be granted if the following
7735 * immediate commands are to the same memory page (same bank and same row)
7736 * . See also related PCCFG.pagematch_limit register.
7738 #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL
7739 #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT
7740 #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK
7741 #define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000
7742 #define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT 14
7743 #define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U
7746 * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
7747 * bled and arurgent is asserted by the master, that port becomes the highe
7748 * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
7749 * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
7750 * urgent signal can be asserted anytime and as long as required which is i
7751 * ndependent of address handshaking (it is not associated with any particu
7754 #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL
7755 #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT
7756 #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK
7757 #define DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL 0x00000000
7758 #define DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT 13
7759 #define DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK 0x00002000U
7762 * If set to 1, enables aging function for the read channel of the port.
7764 #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL
7765 #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT
7766 #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK
7767 #define DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL 0x00000000
7768 #define DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT 12
7769 #define DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK 0x00001000U
7772 * Determines the initial load value of read aging counters. These counters
7773 * will be parallel loaded after reset, or after each grant to the corresp
7774 * onding port. The aging counters down-count every clock cycle where the p
7775 * ort is requesting but not granted. The higher significant 5-bits of the
7776 * read aging counter sets the priority of the read channel of a given port
7777 * . Port's priority will increase as the higher significant 5-bits of the
7778 * counter starts to decrease. When the aging counter becomes 0, the corres
7779 * ponding port channel will have the highest priority level (timeout condi
7780 * tion - Priority0). For multi-port configurations, the aging counters can
7781 * not be used to set port priorities when external dynamic priority inputs
7782 * (arqos) are enabled (timeout is still applicable). For single port conf
7783 * igurations, the aging counters are only used when they timeout (become 0
7784 * ) to force read-write direction switching. In this case, external dynami
7785 * c priority input, arqos (for reads only) can still be used to set the DD
7786 * RC read priority (2 priority levels: low priority read - LPR, high prior
7787 * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
7788 * s register field are tied internally to 2'b00.
7790 #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL
7791 #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT
7792 #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK
7793 #define DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL 0x00000000
7794 #define DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT 0
7795 #define DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK 0x000003FFU
7798 * If set to 1, enables the Page Match feature. If enabled, once a requesti
7799 * ng port is granted, the port is continued to be granted if the following
7800 * immediate commands are to the same memory page (same bank and same row)
7801 * . See also related PCCFG.pagematch_limit register.
7803 #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL
7804 #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT
7805 #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK
7806 #define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000
7807 #define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT 14
7808 #define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U
7811 * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
7812 * bled and awurgent is asserted by the master, that port becomes the highe
7813 * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
7814 * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
7815 * serted anytime and as long as required which is independent of address h
7816 * andshaking (it is not associated with any particular command).
7818 #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL
7819 #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT
7820 #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK
7821 #define DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL 0x00004000
7822 #define DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT 13
7823 #define DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK 0x00002000U
7826 * If set to 1, enables aging function for the write channel of the port.
7828 #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL
7829 #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT
7830 #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK
7831 #define DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL 0x00004000
7832 #define DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT 12
7833 #define DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK 0x00001000U
7836 * Determines the initial load value of write aging counters. These counter
7837 * s will be parallel loaded after reset, or after each grant to the corres
7838 * ponding port. The aging counters down-count every clock cycle where the
7839 * port is requesting but not granted. The higher significant 5-bits of the
7840 * write aging counter sets the initial priority of the write channel of a
7841 * given port. Port's priority will increase as the higher significant 5-b
7842 * its of the counter starts to decrease. When the aging counter becomes 0,
7843 * the corresponding port channel will have the highest priority level. Fo
7844 * r multi-port configurations, the aging counters cannot be used to set po
7845 * rt priorities when external dynamic priority inputs (awqos) are enabled
7846 * (timeout is still applicable). For single port configurations, the aging
7847 * counters are only used when they timeout (become 0) to force read-write
7848 * direction switching. Note: The two LSBs of this register field are tied
7849 * internally to 2'b00.
7851 #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL
7852 #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT
7853 #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK
7854 #define DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL 0x00004000
7855 #define DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT 0
7856 #define DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK 0x000003FFU
7861 #undef DDRC_PCTRL_5_PORT_EN_DEFVAL
7862 #undef DDRC_PCTRL_5_PORT_EN_SHIFT
7863 #undef DDRC_PCTRL_5_PORT_EN_MASK
7864 #define DDRC_PCTRL_5_PORT_EN_DEFVAL
7865 #define DDRC_PCTRL_5_PORT_EN_SHIFT 0
7866 #define DDRC_PCTRL_5_PORT_EN_MASK 0x00000001U
7869 * This bitfield indicates the traffic class of region 1. Valid values are:
7870 * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
7871 * maps to the blue address queue. In this case, valid values are 0: LPR a
7872 * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
7873 * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
7876 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL
7877 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT
7878 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK
7879 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL 0x00000000
7880 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT 20
7881 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK 0x00300000U
7884 * This bitfield indicates the traffic class of region 0. Valid values are:
7885 * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
7886 * maps to the blue address queue. In this case, valid values are: 0: LPR
7887 * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
7888 * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
7891 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL
7892 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT
7893 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK
7894 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL 0x00000000
7895 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT 16
7896 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK 0x00030000U
7899 * Separation level1 indicating the end of region0 mapping; start of region
7900 * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
7901 * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
7902 * lues are used directly as port priorities, where the higher the value co
7903 * rresponds to higher port priority. All of the map_level* registers must
7904 * be set to distinct values.
7906 #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL
7907 #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT
7908 #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK
7909 #define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL 0x00000000
7910 #define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT 0
7911 #define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK 0x0000000FU
7914 * Specifies the timeout value for transactions mapped to the red address q
7917 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL
7918 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT
7919 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK
7920 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000
7921 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT 16
7922 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U
7925 * Specifies the timeout value for transactions mapped to the blue address
7928 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL
7929 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT
7930 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK
7931 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000
7932 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT 0
7933 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU
7936 * This bitfield indicates the traffic class of region 1. Valid values are:
7937 * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
7938 * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW
7941 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL
7942 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT
7943 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK
7944 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL 0x00000000
7945 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT 20
7946 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK 0x00300000U
7949 * This bitfield indicates the traffic class of region 0. Valid values are:
7950 * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
7951 * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW
7954 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL
7955 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT
7956 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK
7957 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL 0x00000000
7958 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT 16
7959 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK 0x00030000U
7962 * Separation level indicating the end of region0 mapping; start of region0
7963 * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos
7964 * . Note that for PA, awqos values are used directly as port priorities, w
7965 * here the higher the value corresponds to higher port priority.
7967 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL
7968 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT
7969 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK
7970 #define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL 0x00000000
7971 #define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT 0
7972 #define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK 0x0000000FU
7975 * Specifies the timeout value for write transactions.
7977 #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL
7978 #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT
7979 #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK
7980 #define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL
7981 #define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT 0
7982 #define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK 0x000007FFU
7985 * Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x
7986 * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl
7987 * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
7989 #undef DDRC_SARBASE0_BASE_ADDR_DEFVAL
7990 #undef DDRC_SARBASE0_BASE_ADDR_SHIFT
7991 #undef DDRC_SARBASE0_BASE_ADDR_MASK
7992 #define DDRC_SARBASE0_BASE_ADDR_DEFVAL
7993 #define DDRC_SARBASE0_BASE_ADDR_SHIFT 0
7994 #define DDRC_SARBASE0_BASE_ADDR_MASK 0x000001FFU
7997 * Number of blocks for address region n. This register determines the tota
7998 * l size of the region in multiples of minimum block size as specified by
7999 * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded
8000 * as number of blocks = nblocks + 1. For example, if register is programme
8001 * d to 0, region will have 1 block.
8003 #undef DDRC_SARSIZE0_NBLOCKS_DEFVAL
8004 #undef DDRC_SARSIZE0_NBLOCKS_SHIFT
8005 #undef DDRC_SARSIZE0_NBLOCKS_MASK
8006 #define DDRC_SARSIZE0_NBLOCKS_DEFVAL
8007 #define DDRC_SARSIZE0_NBLOCKS_SHIFT 0
8008 #define DDRC_SARSIZE0_NBLOCKS_MASK 0x000000FFU
8011 * Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x
8012 * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl
8013 * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
8015 #undef DDRC_SARBASE1_BASE_ADDR_DEFVAL
8016 #undef DDRC_SARBASE1_BASE_ADDR_SHIFT
8017 #undef DDRC_SARBASE1_BASE_ADDR_MASK
8018 #define DDRC_SARBASE1_BASE_ADDR_DEFVAL
8019 #define DDRC_SARBASE1_BASE_ADDR_SHIFT 0
8020 #define DDRC_SARBASE1_BASE_ADDR_MASK 0x000001FFU
8023 * Number of blocks for address region n. This register determines the tota
8024 * l size of the region in multiples of minimum block size as specified by
8025 * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded
8026 * as number of blocks = nblocks + 1. For example, if register is programme
8027 * d to 0, region will have 1 block.
8029 #undef DDRC_SARSIZE1_NBLOCKS_DEFVAL
8030 #undef DDRC_SARSIZE1_NBLOCKS_SHIFT
8031 #undef DDRC_SARSIZE1_NBLOCKS_MASK
8032 #define DDRC_SARSIZE1_NBLOCKS_DEFVAL
8033 #define DDRC_SARSIZE1_NBLOCKS_SHIFT 0
8034 #define DDRC_SARSIZE1_NBLOCKS_MASK 0x000000FFU
8037 * Specifies the number of DFI clock cycles after an assertion or de-assert
8038 * ion of the DFI control signals that the control signals at the PHY-DRAM
8039 * interface reflect the assertion or de-assertion. If the DFI clock and th
8040 * e memory clock are not phase-aligned, this timing parameter should be ro
8041 * unded up to the next integer value. Note that if using RDIMM, it is nece
8042 * ssary to increment this parameter by RDIMM's extra cycle of latency in t
8043 * erms of DFI clock.
8045 #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL
8046 #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT
8047 #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK
8048 #define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL 0x07020002
8049 #define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT 24
8050 #define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK 0x1F000000U
8053 * Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u
8054 * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en
8055 * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles
8056 * - 1 in terms of SDR clock cycles Refer to PHY specification for correct
8059 #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL
8060 #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT
8061 #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK
8062 #define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002
8063 #define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT 23
8064 #define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK 0x00800000U
8067 * Time from the assertion of a read command on the DFI interface to the as
8068 * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr
8069 * ect value. This corresponds to the DFI parameter trddata_en. Note that,
8070 * depending on the PHY, if using RDIMM, it may be necessary to use the val
8071 * ue (CL + 1) in the calculation of trddata_en. This is to compensate for
8072 * the extra cycle of latency through the RDIMM. Unit: Clocks
8074 #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL
8075 #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT
8076 #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK
8077 #define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL 0x07020002
8078 #define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT 16
8079 #define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK 0x003F0000U
8082 * Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us
8083 * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is
8084 * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df
8085 * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR
8086 * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio
8087 * n for correct value.
8089 #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL
8090 #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT
8091 #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK
8092 #define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002
8093 #define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT 15
8094 #define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK 0x00008000U
8097 * Specifies the number of clock cycles between when dfi_wrdata_en is asser
8098 * ted to when the associated write data is driven on the dfi_wrdata signal
8099 * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY
8100 * specification for correct value. Note, max supported value is 8. Unit:
8103 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL
8104 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT
8105 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK
8106 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL 0x07020002
8107 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT 8
8108 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK 0x00003F00U
8111 * Write latency Number of clocks from the write command to write data enab
8112 * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr
8113 * lat. Refer to PHY specification for correct value.Note that, depending o
8114 * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1)
8115 * in the calculation of tphy_wrlat. This is to compensate for the extra c
8116 * ycle of latency through the RDIMM.
8118 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL
8119 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT
8120 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK
8121 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL 0x07020002
8122 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT 0
8123 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK 0x0000003FU
8126 * DDR block level reset inside of the DDR Sub System
8128 #undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL
8129 #undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT
8130 #undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK
8131 #define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F
8132 #define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3
8133 #define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U
8136 * APM block level reset inside of the DDR Sub System
8138 #undef CRF_APB_RST_DDR_SS_APM_RESET_DEFVAL
8139 #undef CRF_APB_RST_DDR_SS_APM_RESET_SHIFT
8140 #undef CRF_APB_RST_DDR_SS_APM_RESET_MASK
8141 #define CRF_APB_RST_DDR_SS_APM_RESET_DEFVAL 0x0000000F
8142 #define CRF_APB_RST_DDR_SS_APM_RESET_SHIFT 2
8143 #define CRF_APB_RST_DDR_SS_APM_RESET_MASK 0x00000004U
8148 #undef DDR_PHY_PGCR0_ADCP_DEFVAL
8149 #undef DDR_PHY_PGCR0_ADCP_SHIFT
8150 #undef DDR_PHY_PGCR0_ADCP_MASK
8151 #define DDR_PHY_PGCR0_ADCP_DEFVAL 0x07001E00
8152 #define DDR_PHY_PGCR0_ADCP_SHIFT 31
8153 #define DDR_PHY_PGCR0_ADCP_MASK 0x80000000U
8156 * Reserved. Returns zeroes on reads.
8158 #undef DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL
8159 #undef DDR_PHY_PGCR0_RESERVED_30_27_SHIFT
8160 #undef DDR_PHY_PGCR0_RESERVED_30_27_MASK
8161 #define DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL 0x07001E00
8162 #define DDR_PHY_PGCR0_RESERVED_30_27_SHIFT 27
8163 #define DDR_PHY_PGCR0_RESERVED_30_27_MASK 0x78000000U
8168 #undef DDR_PHY_PGCR0_PHYFRST_DEFVAL
8169 #undef DDR_PHY_PGCR0_PHYFRST_SHIFT
8170 #undef DDR_PHY_PGCR0_PHYFRST_MASK
8171 #define DDR_PHY_PGCR0_PHYFRST_DEFVAL 0x07001E00
8172 #define DDR_PHY_PGCR0_PHYFRST_SHIFT 26
8173 #define DDR_PHY_PGCR0_PHYFRST_MASK 0x04000000U
8176 * Oscillator Mode Address/Command Delay Line Select
8178 #undef DDR_PHY_PGCR0_OSCACDL_DEFVAL
8179 #undef DDR_PHY_PGCR0_OSCACDL_SHIFT
8180 #undef DDR_PHY_PGCR0_OSCACDL_MASK
8181 #define DDR_PHY_PGCR0_OSCACDL_DEFVAL 0x07001E00
8182 #define DDR_PHY_PGCR0_OSCACDL_SHIFT 24
8183 #define DDR_PHY_PGCR0_OSCACDL_MASK 0x03000000U
8186 * Reserved. Returns zeroes on reads.
8188 #undef DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL
8189 #undef DDR_PHY_PGCR0_RESERVED_23_19_SHIFT
8190 #undef DDR_PHY_PGCR0_RESERVED_23_19_MASK
8191 #define DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL 0x07001E00
8192 #define DDR_PHY_PGCR0_RESERVED_23_19_SHIFT 19
8193 #define DDR_PHY_PGCR0_RESERVED_23_19_MASK 0x00F80000U
8196 * Digital Test Output Select
8198 #undef DDR_PHY_PGCR0_DTOSEL_DEFVAL
8199 #undef DDR_PHY_PGCR0_DTOSEL_SHIFT
8200 #undef DDR_PHY_PGCR0_DTOSEL_MASK
8201 #define DDR_PHY_PGCR0_DTOSEL_DEFVAL 0x07001E00
8202 #define DDR_PHY_PGCR0_DTOSEL_SHIFT 14
8203 #define DDR_PHY_PGCR0_DTOSEL_MASK 0x0007C000U
8206 * Reserved. Returns zeroes on reads.
8208 #undef DDR_PHY_PGCR0_RESERVED_13_DEFVAL
8209 #undef DDR_PHY_PGCR0_RESERVED_13_SHIFT
8210 #undef DDR_PHY_PGCR0_RESERVED_13_MASK
8211 #define DDR_PHY_PGCR0_RESERVED_13_DEFVAL 0x07001E00
8212 #define DDR_PHY_PGCR0_RESERVED_13_SHIFT 13
8213 #define DDR_PHY_PGCR0_RESERVED_13_MASK 0x00002000U
8216 * Oscillator Mode Division
8218 #undef DDR_PHY_PGCR0_OSCDIV_DEFVAL
8219 #undef DDR_PHY_PGCR0_OSCDIV_SHIFT
8220 #undef DDR_PHY_PGCR0_OSCDIV_MASK
8221 #define DDR_PHY_PGCR0_OSCDIV_DEFVAL 0x07001E00
8222 #define DDR_PHY_PGCR0_OSCDIV_SHIFT 9
8223 #define DDR_PHY_PGCR0_OSCDIV_MASK 0x00001E00U
8228 #undef DDR_PHY_PGCR0_OSCEN_DEFVAL
8229 #undef DDR_PHY_PGCR0_OSCEN_SHIFT
8230 #undef DDR_PHY_PGCR0_OSCEN_MASK
8231 #define DDR_PHY_PGCR0_OSCEN_DEFVAL 0x07001E00
8232 #define DDR_PHY_PGCR0_OSCEN_SHIFT 8
8233 #define DDR_PHY_PGCR0_OSCEN_MASK 0x00000100U
8236 * Reserved. Returns zeroes on reads.
8238 #undef DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL
8239 #undef DDR_PHY_PGCR0_RESERVED_7_0_SHIFT
8240 #undef DDR_PHY_PGCR0_RESERVED_7_0_MASK
8241 #define DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL 0x07001E00
8242 #define DDR_PHY_PGCR0_RESERVED_7_0_SHIFT 0
8243 #define DDR_PHY_PGCR0_RESERVED_7_0_MASK 0x000000FFU
8246 * Clear Training Status Registers
8248 #undef DDR_PHY_PGCR2_CLRTSTAT_DEFVAL
8249 #undef DDR_PHY_PGCR2_CLRTSTAT_SHIFT
8250 #undef DDR_PHY_PGCR2_CLRTSTAT_MASK
8251 #define DDR_PHY_PGCR2_CLRTSTAT_DEFVAL 0x00F12480
8252 #define DDR_PHY_PGCR2_CLRTSTAT_SHIFT 31
8253 #define DDR_PHY_PGCR2_CLRTSTAT_MASK 0x80000000U
8256 * Clear Impedance Calibration
8258 #undef DDR_PHY_PGCR2_CLRZCAL_DEFVAL
8259 #undef DDR_PHY_PGCR2_CLRZCAL_SHIFT
8260 #undef DDR_PHY_PGCR2_CLRZCAL_MASK
8261 #define DDR_PHY_PGCR2_CLRZCAL_DEFVAL 0x00F12480
8262 #define DDR_PHY_PGCR2_CLRZCAL_SHIFT 30
8263 #define DDR_PHY_PGCR2_CLRZCAL_MASK 0x40000000U
8266 * Clear Parity Error
8268 #undef DDR_PHY_PGCR2_CLRPERR_DEFVAL
8269 #undef DDR_PHY_PGCR2_CLRPERR_SHIFT
8270 #undef DDR_PHY_PGCR2_CLRPERR_MASK
8271 #define DDR_PHY_PGCR2_CLRPERR_DEFVAL 0x00F12480
8272 #define DDR_PHY_PGCR2_CLRPERR_SHIFT 29
8273 #define DDR_PHY_PGCR2_CLRPERR_MASK 0x20000000U
8276 * Initialization Complete Pin Configuration
8278 #undef DDR_PHY_PGCR2_ICPC_DEFVAL
8279 #undef DDR_PHY_PGCR2_ICPC_SHIFT
8280 #undef DDR_PHY_PGCR2_ICPC_MASK
8281 #define DDR_PHY_PGCR2_ICPC_DEFVAL 0x00F12480
8282 #define DDR_PHY_PGCR2_ICPC_SHIFT 28
8283 #define DDR_PHY_PGCR2_ICPC_MASK 0x10000000U
8286 * Data Training PUB Mode Exit Timer
8288 #undef DDR_PHY_PGCR2_DTPMXTMR_DEFVAL
8289 #undef DDR_PHY_PGCR2_DTPMXTMR_SHIFT
8290 #undef DDR_PHY_PGCR2_DTPMXTMR_MASK
8291 #define DDR_PHY_PGCR2_DTPMXTMR_DEFVAL 0x00F12480
8292 #define DDR_PHY_PGCR2_DTPMXTMR_SHIFT 20
8293 #define DDR_PHY_PGCR2_DTPMXTMR_MASK 0x0FF00000U
8296 * Initialization Bypass
8298 #undef DDR_PHY_PGCR2_INITFSMBYP_DEFVAL
8299 #undef DDR_PHY_PGCR2_INITFSMBYP_SHIFT
8300 #undef DDR_PHY_PGCR2_INITFSMBYP_MASK
8301 #define DDR_PHY_PGCR2_INITFSMBYP_DEFVAL 0x00F12480
8302 #define DDR_PHY_PGCR2_INITFSMBYP_SHIFT 19
8303 #define DDR_PHY_PGCR2_INITFSMBYP_MASK 0x00080000U
8308 #undef DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL
8309 #undef DDR_PHY_PGCR2_PLLFSMBYP_SHIFT
8310 #undef DDR_PHY_PGCR2_PLLFSMBYP_MASK
8311 #define DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL 0x00F12480
8312 #define DDR_PHY_PGCR2_PLLFSMBYP_SHIFT 18
8313 #define DDR_PHY_PGCR2_PLLFSMBYP_MASK 0x00040000U
8318 #undef DDR_PHY_PGCR2_TREFPRD_DEFVAL
8319 #undef DDR_PHY_PGCR2_TREFPRD_SHIFT
8320 #undef DDR_PHY_PGCR2_TREFPRD_MASK
8321 #define DDR_PHY_PGCR2_TREFPRD_DEFVAL 0x00F12480
8322 #define DDR_PHY_PGCR2_TREFPRD_SHIFT 0
8323 #define DDR_PHY_PGCR2_TREFPRD_MASK 0x0003FFFFU
8328 #undef DDR_PHY_PGCR3_CKNEN_DEFVAL
8329 #undef DDR_PHY_PGCR3_CKNEN_SHIFT
8330 #undef DDR_PHY_PGCR3_CKNEN_MASK
8331 #define DDR_PHY_PGCR3_CKNEN_DEFVAL 0x55AA0080
8332 #define DDR_PHY_PGCR3_CKNEN_SHIFT 24
8333 #define DDR_PHY_PGCR3_CKNEN_MASK 0xFF000000U
8338 #undef DDR_PHY_PGCR3_CKEN_DEFVAL
8339 #undef DDR_PHY_PGCR3_CKEN_SHIFT
8340 #undef DDR_PHY_PGCR3_CKEN_MASK
8341 #define DDR_PHY_PGCR3_CKEN_DEFVAL 0x55AA0080
8342 #define DDR_PHY_PGCR3_CKEN_SHIFT 16
8343 #define DDR_PHY_PGCR3_CKEN_MASK 0x00FF0000U
8346 * Reserved. Return zeroes on reads.
8348 #undef DDR_PHY_PGCR3_RESERVED_15_DEFVAL
8349 #undef DDR_PHY_PGCR3_RESERVED_15_SHIFT
8350 #undef DDR_PHY_PGCR3_RESERVED_15_MASK
8351 #define DDR_PHY_PGCR3_RESERVED_15_DEFVAL 0x55AA0080
8352 #define DDR_PHY_PGCR3_RESERVED_15_SHIFT 15
8353 #define DDR_PHY_PGCR3_RESERVED_15_MASK 0x00008000U
8356 * Enable Clock Gating for AC [0] ctl_rd_clk
8358 #undef DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL
8359 #undef DDR_PHY_PGCR3_GATEACRDCLK_SHIFT
8360 #undef DDR_PHY_PGCR3_GATEACRDCLK_MASK
8361 #define DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL 0x55AA0080
8362 #define DDR_PHY_PGCR3_GATEACRDCLK_SHIFT 13
8363 #define DDR_PHY_PGCR3_GATEACRDCLK_MASK 0x00006000U
8366 * Enable Clock Gating for AC [0] ddr_clk
8368 #undef DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL
8369 #undef DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT
8370 #undef DDR_PHY_PGCR3_GATEACDDRCLK_MASK
8371 #define DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL 0x55AA0080
8372 #define DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT 11
8373 #define DDR_PHY_PGCR3_GATEACDDRCLK_MASK 0x00001800U
8376 * Enable Clock Gating for AC [0] ctl_clk
8378 #undef DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL
8379 #undef DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT
8380 #undef DDR_PHY_PGCR3_GATEACCTLCLK_MASK
8381 #define DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL 0x55AA0080
8382 #define DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT 9
8383 #define DDR_PHY_PGCR3_GATEACCTLCLK_MASK 0x00000600U
8386 * Reserved. Return zeroes on reads.
8388 #undef DDR_PHY_PGCR3_RESERVED_8_DEFVAL
8389 #undef DDR_PHY_PGCR3_RESERVED_8_SHIFT
8390 #undef DDR_PHY_PGCR3_RESERVED_8_MASK
8391 #define DDR_PHY_PGCR3_RESERVED_8_DEFVAL 0x55AA0080
8392 #define DDR_PHY_PGCR3_RESERVED_8_SHIFT 8
8393 #define DDR_PHY_PGCR3_RESERVED_8_MASK 0x00000100U
8396 * Controls DDL Bypass Modes
8398 #undef DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL
8399 #undef DDR_PHY_PGCR3_DDLBYPMODE_SHIFT
8400 #undef DDR_PHY_PGCR3_DDLBYPMODE_MASK
8401 #define DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL 0x55AA0080
8402 #define DDR_PHY_PGCR3_DDLBYPMODE_SHIFT 6
8403 #define DDR_PHY_PGCR3_DDLBYPMODE_MASK 0x000000C0U
8406 * IO Loop-Back Select
8408 #undef DDR_PHY_PGCR3_IOLB_DEFVAL
8409 #undef DDR_PHY_PGCR3_IOLB_SHIFT
8410 #undef DDR_PHY_PGCR3_IOLB_MASK
8411 #define DDR_PHY_PGCR3_IOLB_DEFVAL 0x55AA0080
8412 #define DDR_PHY_PGCR3_IOLB_SHIFT 5
8413 #define DDR_PHY_PGCR3_IOLB_MASK 0x00000020U
8416 * AC Receive FIFO Read Mode
8418 #undef DDR_PHY_PGCR3_RDMODE_DEFVAL
8419 #undef DDR_PHY_PGCR3_RDMODE_SHIFT
8420 #undef DDR_PHY_PGCR3_RDMODE_MASK
8421 #define DDR_PHY_PGCR3_RDMODE_DEFVAL 0x55AA0080
8422 #define DDR_PHY_PGCR3_RDMODE_SHIFT 3
8423 #define DDR_PHY_PGCR3_RDMODE_MASK 0x00000018U
8426 * Read FIFO Reset Disable
8428 #undef DDR_PHY_PGCR3_DISRST_DEFVAL
8429 #undef DDR_PHY_PGCR3_DISRST_SHIFT
8430 #undef DDR_PHY_PGCR3_DISRST_MASK
8431 #define DDR_PHY_PGCR3_DISRST_DEFVAL 0x55AA0080
8432 #define DDR_PHY_PGCR3_DISRST_SHIFT 2
8433 #define DDR_PHY_PGCR3_DISRST_MASK 0x00000004U
8436 * Clock Level when Clock Gating
8438 #undef DDR_PHY_PGCR3_CLKLEVEL_DEFVAL
8439 #undef DDR_PHY_PGCR3_CLKLEVEL_SHIFT
8440 #undef DDR_PHY_PGCR3_CLKLEVEL_MASK
8441 #define DDR_PHY_PGCR3_CLKLEVEL_DEFVAL 0x55AA0080
8442 #define DDR_PHY_PGCR3_CLKLEVEL_SHIFT 0
8443 #define DDR_PHY_PGCR3_CLKLEVEL_MASK 0x00000003U
8446 * Frequency B Ratio Term
8448 #undef DDR_PHY_PGCR5_FRQBT_DEFVAL
8449 #undef DDR_PHY_PGCR5_FRQBT_SHIFT
8450 #undef DDR_PHY_PGCR5_FRQBT_MASK
8451 #define DDR_PHY_PGCR5_FRQBT_DEFVAL 0x01010000
8452 #define DDR_PHY_PGCR5_FRQBT_SHIFT 24
8453 #define DDR_PHY_PGCR5_FRQBT_MASK 0xFF000000U
8456 * Frequency A Ratio Term
8458 #undef DDR_PHY_PGCR5_FRQAT_DEFVAL
8459 #undef DDR_PHY_PGCR5_FRQAT_SHIFT
8460 #undef DDR_PHY_PGCR5_FRQAT_MASK
8461 #define DDR_PHY_PGCR5_FRQAT_DEFVAL 0x01010000
8462 #define DDR_PHY_PGCR5_FRQAT_SHIFT 16
8463 #define DDR_PHY_PGCR5_FRQAT_MASK 0x00FF0000U
8466 * DFI Disconnect Time Period
8468 #undef DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL
8469 #undef DDR_PHY_PGCR5_DISCNPERIOD_SHIFT
8470 #undef DDR_PHY_PGCR5_DISCNPERIOD_MASK
8471 #define DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL 0x01010000
8472 #define DDR_PHY_PGCR5_DISCNPERIOD_SHIFT 8
8473 #define DDR_PHY_PGCR5_DISCNPERIOD_MASK 0x0000FF00U
8476 * Receiver bias core side control
8478 #undef DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL
8479 #undef DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT
8480 #undef DDR_PHY_PGCR5_VREF_RBCTRL_MASK
8481 #define DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL 0x01010000
8482 #define DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT 4
8483 #define DDR_PHY_PGCR5_VREF_RBCTRL_MASK 0x000000F0U
8486 * Reserved. Return zeroes on reads.
8488 #undef DDR_PHY_PGCR5_RESERVED_3_DEFVAL
8489 #undef DDR_PHY_PGCR5_RESERVED_3_SHIFT
8490 #undef DDR_PHY_PGCR5_RESERVED_3_MASK
8491 #define DDR_PHY_PGCR5_RESERVED_3_DEFVAL 0x01010000
8492 #define DDR_PHY_PGCR5_RESERVED_3_SHIFT 3
8493 #define DDR_PHY_PGCR5_RESERVED_3_MASK 0x00000008U
8496 * Internal VREF generator REFSEL ragne select
8498 #undef DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL
8499 #undef DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT
8500 #undef DDR_PHY_PGCR5_DXREFISELRANGE_MASK
8501 #define DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL 0x01010000
8502 #define DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT 2
8503 #define DDR_PHY_PGCR5_DXREFISELRANGE_MASK 0x00000004U
8506 * DDL Page Read Write select
8508 #undef DDR_PHY_PGCR5_DDLPGACT_DEFVAL
8509 #undef DDR_PHY_PGCR5_DDLPGACT_SHIFT
8510 #undef DDR_PHY_PGCR5_DDLPGACT_MASK
8511 #define DDR_PHY_PGCR5_DDLPGACT_DEFVAL 0x01010000
8512 #define DDR_PHY_PGCR5_DDLPGACT_SHIFT 1
8513 #define DDR_PHY_PGCR5_DDLPGACT_MASK 0x00000002U
8516 * DDL Page Read Write select
8518 #undef DDR_PHY_PGCR5_DDLPGRW_DEFVAL
8519 #undef DDR_PHY_PGCR5_DDLPGRW_SHIFT
8520 #undef DDR_PHY_PGCR5_DDLPGRW_MASK
8521 #define DDR_PHY_PGCR5_DDLPGRW_DEFVAL 0x01010000
8522 #define DDR_PHY_PGCR5_DDLPGRW_SHIFT 0
8523 #define DDR_PHY_PGCR5_DDLPGRW_MASK 0x00000001U
8526 * PLL Power-Down Time
8528 #undef DDR_PHY_PTR0_TPLLPD_DEFVAL
8529 #undef DDR_PHY_PTR0_TPLLPD_SHIFT
8530 #undef DDR_PHY_PTR0_TPLLPD_MASK
8531 #define DDR_PHY_PTR0_TPLLPD_DEFVAL 0x42C21590
8532 #define DDR_PHY_PTR0_TPLLPD_SHIFT 21
8533 #define DDR_PHY_PTR0_TPLLPD_MASK 0xFFE00000U
8536 * PLL Gear Shift Time
8538 #undef DDR_PHY_PTR0_TPLLGS_DEFVAL
8539 #undef DDR_PHY_PTR0_TPLLGS_SHIFT
8540 #undef DDR_PHY_PTR0_TPLLGS_MASK
8541 #define DDR_PHY_PTR0_TPLLGS_DEFVAL 0x42C21590
8542 #define DDR_PHY_PTR0_TPLLGS_SHIFT 6
8543 #define DDR_PHY_PTR0_TPLLGS_MASK 0x001FFFC0U
8548 #undef DDR_PHY_PTR0_TPHYRST_DEFVAL
8549 #undef DDR_PHY_PTR0_TPHYRST_SHIFT
8550 #undef DDR_PHY_PTR0_TPHYRST_MASK
8551 #define DDR_PHY_PTR0_TPHYRST_DEFVAL 0x42C21590
8552 #define DDR_PHY_PTR0_TPHYRST_SHIFT 0
8553 #define DDR_PHY_PTR0_TPHYRST_MASK 0x0000003FU
8558 #undef DDR_PHY_PTR1_TPLLLOCK_DEFVAL
8559 #undef DDR_PHY_PTR1_TPLLLOCK_SHIFT
8560 #undef DDR_PHY_PTR1_TPLLLOCK_MASK
8561 #define DDR_PHY_PTR1_TPLLLOCK_DEFVAL 0xD05612C0
8562 #define DDR_PHY_PTR1_TPLLLOCK_SHIFT 16
8563 #define DDR_PHY_PTR1_TPLLLOCK_MASK 0xFFFF0000U
8566 * Reserved. Returns zeroes on reads.
8568 #undef DDR_PHY_PTR1_RESERVED_15_13_DEFVAL
8569 #undef DDR_PHY_PTR1_RESERVED_15_13_SHIFT
8570 #undef DDR_PHY_PTR1_RESERVED_15_13_MASK
8571 #define DDR_PHY_PTR1_RESERVED_15_13_DEFVAL 0xD05612C0
8572 #define DDR_PHY_PTR1_RESERVED_15_13_SHIFT 13
8573 #define DDR_PHY_PTR1_RESERVED_15_13_MASK 0x0000E000U
8578 #undef DDR_PHY_PTR1_TPLLRST_DEFVAL
8579 #undef DDR_PHY_PTR1_TPLLRST_SHIFT
8580 #undef DDR_PHY_PTR1_TPLLRST_MASK
8581 #define DDR_PHY_PTR1_TPLLRST_DEFVAL 0xD05612C0
8582 #define DDR_PHY_PTR1_TPLLRST_SHIFT 0
8583 #define DDR_PHY_PTR1_TPLLRST_MASK 0x00001FFFU
8588 #undef DDR_PHY_PLLCR0_PLLBYP_DEFVAL
8589 #undef DDR_PHY_PLLCR0_PLLBYP_SHIFT
8590 #undef DDR_PHY_PLLCR0_PLLBYP_MASK
8591 #define DDR_PHY_PLLCR0_PLLBYP_DEFVAL 0x001C0000
8592 #define DDR_PHY_PLLCR0_PLLBYP_SHIFT 31
8593 #define DDR_PHY_PLLCR0_PLLBYP_MASK 0x80000000U
8598 #undef DDR_PHY_PLLCR0_PLLRST_DEFVAL
8599 #undef DDR_PHY_PLLCR0_PLLRST_SHIFT
8600 #undef DDR_PHY_PLLCR0_PLLRST_MASK
8601 #define DDR_PHY_PLLCR0_PLLRST_DEFVAL 0x001C0000
8602 #define DDR_PHY_PLLCR0_PLLRST_SHIFT 30
8603 #define DDR_PHY_PLLCR0_PLLRST_MASK 0x40000000U
8608 #undef DDR_PHY_PLLCR0_PLLPD_DEFVAL
8609 #undef DDR_PHY_PLLCR0_PLLPD_SHIFT
8610 #undef DDR_PHY_PLLCR0_PLLPD_MASK
8611 #define DDR_PHY_PLLCR0_PLLPD_DEFVAL 0x001C0000
8612 #define DDR_PHY_PLLCR0_PLLPD_SHIFT 29
8613 #define DDR_PHY_PLLCR0_PLLPD_MASK 0x20000000U
8616 * Reference Stop Mode
8618 #undef DDR_PHY_PLLCR0_RSTOPM_DEFVAL
8619 #undef DDR_PHY_PLLCR0_RSTOPM_SHIFT
8620 #undef DDR_PHY_PLLCR0_RSTOPM_MASK
8621 #define DDR_PHY_PLLCR0_RSTOPM_DEFVAL 0x001C0000
8622 #define DDR_PHY_PLLCR0_RSTOPM_SHIFT 28
8623 #define DDR_PHY_PLLCR0_RSTOPM_MASK 0x10000000U
8626 * PLL Frequency Select
8628 #undef DDR_PHY_PLLCR0_FRQSEL_DEFVAL
8629 #undef DDR_PHY_PLLCR0_FRQSEL_SHIFT
8630 #undef DDR_PHY_PLLCR0_FRQSEL_MASK
8631 #define DDR_PHY_PLLCR0_FRQSEL_DEFVAL 0x001C0000
8632 #define DDR_PHY_PLLCR0_FRQSEL_SHIFT 24
8633 #define DDR_PHY_PLLCR0_FRQSEL_MASK 0x0F000000U
8638 #undef DDR_PHY_PLLCR0_RLOCKM_DEFVAL
8639 #undef DDR_PHY_PLLCR0_RLOCKM_SHIFT
8640 #undef DDR_PHY_PLLCR0_RLOCKM_MASK
8641 #define DDR_PHY_PLLCR0_RLOCKM_DEFVAL 0x001C0000
8642 #define DDR_PHY_PLLCR0_RLOCKM_SHIFT 23
8643 #define DDR_PHY_PLLCR0_RLOCKM_MASK 0x00800000U
8646 * Charge Pump Proportional Current Control
8648 #undef DDR_PHY_PLLCR0_CPPC_DEFVAL
8649 #undef DDR_PHY_PLLCR0_CPPC_SHIFT
8650 #undef DDR_PHY_PLLCR0_CPPC_MASK
8651 #define DDR_PHY_PLLCR0_CPPC_DEFVAL 0x001C0000
8652 #define DDR_PHY_PLLCR0_CPPC_SHIFT 17
8653 #define DDR_PHY_PLLCR0_CPPC_MASK 0x007E0000U
8656 * Charge Pump Integrating Current Control
8658 #undef DDR_PHY_PLLCR0_CPIC_DEFVAL
8659 #undef DDR_PHY_PLLCR0_CPIC_SHIFT
8660 #undef DDR_PHY_PLLCR0_CPIC_MASK
8661 #define DDR_PHY_PLLCR0_CPIC_DEFVAL 0x001C0000
8662 #define DDR_PHY_PLLCR0_CPIC_SHIFT 13
8663 #define DDR_PHY_PLLCR0_CPIC_MASK 0x0001E000U
8668 #undef DDR_PHY_PLLCR0_GSHIFT_DEFVAL
8669 #undef DDR_PHY_PLLCR0_GSHIFT_SHIFT
8670 #undef DDR_PHY_PLLCR0_GSHIFT_MASK
8671 #define DDR_PHY_PLLCR0_GSHIFT_DEFVAL 0x001C0000
8672 #define DDR_PHY_PLLCR0_GSHIFT_SHIFT 12
8673 #define DDR_PHY_PLLCR0_GSHIFT_MASK 0x00001000U
8676 * Reserved. Return zeroes on reads.
8678 #undef DDR_PHY_PLLCR0_RESERVED_11_9_DEFVAL
8679 #undef DDR_PHY_PLLCR0_RESERVED_11_9_SHIFT
8680 #undef DDR_PHY_PLLCR0_RESERVED_11_9_MASK
8681 #define DDR_PHY_PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000
8682 #define DDR_PHY_PLLCR0_RESERVED_11_9_SHIFT 9
8683 #define DDR_PHY_PLLCR0_RESERVED_11_9_MASK 0x00000E00U
8686 * Analog Test Enable
8688 #undef DDR_PHY_PLLCR0_ATOEN_DEFVAL
8689 #undef DDR_PHY_PLLCR0_ATOEN_SHIFT
8690 #undef DDR_PHY_PLLCR0_ATOEN_MASK
8691 #define DDR_PHY_PLLCR0_ATOEN_DEFVAL 0x001C0000
8692 #define DDR_PHY_PLLCR0_ATOEN_SHIFT 8
8693 #define DDR_PHY_PLLCR0_ATOEN_MASK 0x00000100U
8696 * Analog Test Control
8698 #undef DDR_PHY_PLLCR0_ATC_DEFVAL
8699 #undef DDR_PHY_PLLCR0_ATC_SHIFT
8700 #undef DDR_PHY_PLLCR0_ATC_MASK
8701 #define DDR_PHY_PLLCR0_ATC_DEFVAL 0x001C0000
8702 #define DDR_PHY_PLLCR0_ATC_SHIFT 4
8703 #define DDR_PHY_PLLCR0_ATC_MASK 0x000000F0U
8706 * Digital Test Control
8708 #undef DDR_PHY_PLLCR0_DTC_DEFVAL
8709 #undef DDR_PHY_PLLCR0_DTC_SHIFT
8710 #undef DDR_PHY_PLLCR0_DTC_MASK
8711 #define DDR_PHY_PLLCR0_DTC_DEFVAL 0x001C0000
8712 #define DDR_PHY_PLLCR0_DTC_SHIFT 0
8713 #define DDR_PHY_PLLCR0_DTC_MASK 0x0000000FU
8716 * Reserved. Return zeroes on reads.
8718 #undef DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL
8719 #undef DDR_PHY_DSGCR_RESERVED_31_28_SHIFT
8720 #undef DDR_PHY_DSGCR_RESERVED_31_28_MASK
8721 #define DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL 0x02A04101
8722 #define DDR_PHY_DSGCR_RESERVED_31_28_SHIFT 28
8723 #define DDR_PHY_DSGCR_RESERVED_31_28_MASK 0xF0000000U
8726 * When RDBI enabled, this bit is used to select RDBI CL calculation, if it
8727 * is 1b1, calculation will use RDBICL, otherwise use default calculation.
8729 #undef DDR_PHY_DSGCR_RDBICLSEL_DEFVAL
8730 #undef DDR_PHY_DSGCR_RDBICLSEL_SHIFT
8731 #undef DDR_PHY_DSGCR_RDBICLSEL_MASK
8732 #define DDR_PHY_DSGCR_RDBICLSEL_DEFVAL 0x02A04101
8733 #define DDR_PHY_DSGCR_RDBICLSEL_SHIFT 27
8734 #define DDR_PHY_DSGCR_RDBICLSEL_MASK 0x08000000U
8737 * When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v
8740 #undef DDR_PHY_DSGCR_RDBICL_DEFVAL
8741 #undef DDR_PHY_DSGCR_RDBICL_SHIFT
8742 #undef DDR_PHY_DSGCR_RDBICL_MASK
8743 #define DDR_PHY_DSGCR_RDBICL_DEFVAL 0x02A04101
8744 #define DDR_PHY_DSGCR_RDBICL_SHIFT 24
8745 #define DDR_PHY_DSGCR_RDBICL_MASK 0x07000000U
8748 * PHY Impedance Update Enable
8750 #undef DDR_PHY_DSGCR_PHYZUEN_DEFVAL
8751 #undef DDR_PHY_DSGCR_PHYZUEN_SHIFT
8752 #undef DDR_PHY_DSGCR_PHYZUEN_MASK
8753 #define DDR_PHY_DSGCR_PHYZUEN_DEFVAL 0x02A04101
8754 #define DDR_PHY_DSGCR_PHYZUEN_SHIFT 23
8755 #define DDR_PHY_DSGCR_PHYZUEN_MASK 0x00800000U
8758 * Reserved. Return zeroes on reads.
8760 #undef DDR_PHY_DSGCR_RESERVED_22_DEFVAL
8761 #undef DDR_PHY_DSGCR_RESERVED_22_SHIFT
8762 #undef DDR_PHY_DSGCR_RESERVED_22_MASK
8763 #define DDR_PHY_DSGCR_RESERVED_22_DEFVAL 0x02A04101
8764 #define DDR_PHY_DSGCR_RESERVED_22_SHIFT 22
8765 #define DDR_PHY_DSGCR_RESERVED_22_MASK 0x00400000U
8768 * SDRAM Reset Output Enable
8770 #undef DDR_PHY_DSGCR_RSTOE_DEFVAL
8771 #undef DDR_PHY_DSGCR_RSTOE_SHIFT
8772 #undef DDR_PHY_DSGCR_RSTOE_MASK
8773 #define DDR_PHY_DSGCR_RSTOE_DEFVAL 0x02A04101
8774 #define DDR_PHY_DSGCR_RSTOE_SHIFT 21
8775 #define DDR_PHY_DSGCR_RSTOE_MASK 0x00200000U
8778 * Single Data Rate Mode
8780 #undef DDR_PHY_DSGCR_SDRMODE_DEFVAL
8781 #undef DDR_PHY_DSGCR_SDRMODE_SHIFT
8782 #undef DDR_PHY_DSGCR_SDRMODE_MASK
8783 #define DDR_PHY_DSGCR_SDRMODE_DEFVAL 0x02A04101
8784 #define DDR_PHY_DSGCR_SDRMODE_SHIFT 19
8785 #define DDR_PHY_DSGCR_SDRMODE_MASK 0x00180000U
8788 * Reserved. Return zeroes on reads.
8790 #undef DDR_PHY_DSGCR_RESERVED_18_DEFVAL
8791 #undef DDR_PHY_DSGCR_RESERVED_18_SHIFT
8792 #undef DDR_PHY_DSGCR_RESERVED_18_MASK
8793 #define DDR_PHY_DSGCR_RESERVED_18_DEFVAL 0x02A04101
8794 #define DDR_PHY_DSGCR_RESERVED_18_SHIFT 18
8795 #define DDR_PHY_DSGCR_RESERVED_18_MASK 0x00040000U
8798 * ATO Analog Test Enable
8800 #undef DDR_PHY_DSGCR_ATOAE_DEFVAL
8801 #undef DDR_PHY_DSGCR_ATOAE_SHIFT
8802 #undef DDR_PHY_DSGCR_ATOAE_MASK
8803 #define DDR_PHY_DSGCR_ATOAE_DEFVAL 0x02A04101
8804 #define DDR_PHY_DSGCR_ATOAE_SHIFT 17
8805 #define DDR_PHY_DSGCR_ATOAE_MASK 0x00020000U
8810 #undef DDR_PHY_DSGCR_DTOOE_DEFVAL
8811 #undef DDR_PHY_DSGCR_DTOOE_SHIFT
8812 #undef DDR_PHY_DSGCR_DTOOE_MASK
8813 #define DDR_PHY_DSGCR_DTOOE_DEFVAL 0x02A04101
8814 #define DDR_PHY_DSGCR_DTOOE_SHIFT 16
8815 #define DDR_PHY_DSGCR_DTOOE_MASK 0x00010000U
8820 #undef DDR_PHY_DSGCR_DTOIOM_DEFVAL
8821 #undef DDR_PHY_DSGCR_DTOIOM_SHIFT
8822 #undef DDR_PHY_DSGCR_DTOIOM_MASK
8823 #define DDR_PHY_DSGCR_DTOIOM_DEFVAL 0x02A04101
8824 #define DDR_PHY_DSGCR_DTOIOM_SHIFT 15
8825 #define DDR_PHY_DSGCR_DTOIOM_MASK 0x00008000U
8828 * DTO Power Down Receiver
8830 #undef DDR_PHY_DSGCR_DTOPDR_DEFVAL
8831 #undef DDR_PHY_DSGCR_DTOPDR_SHIFT
8832 #undef DDR_PHY_DSGCR_DTOPDR_MASK
8833 #define DDR_PHY_DSGCR_DTOPDR_DEFVAL 0x02A04101
8834 #define DDR_PHY_DSGCR_DTOPDR_SHIFT 14
8835 #define DDR_PHY_DSGCR_DTOPDR_MASK 0x00004000U
8838 * Reserved. Return zeroes on reads
8840 #undef DDR_PHY_DSGCR_RESERVED_13_DEFVAL
8841 #undef DDR_PHY_DSGCR_RESERVED_13_SHIFT
8842 #undef DDR_PHY_DSGCR_RESERVED_13_MASK
8843 #define DDR_PHY_DSGCR_RESERVED_13_DEFVAL 0x02A04101
8844 #define DDR_PHY_DSGCR_RESERVED_13_SHIFT 13
8845 #define DDR_PHY_DSGCR_RESERVED_13_MASK 0x00002000U
8848 * DTO On-Die Termination
8850 #undef DDR_PHY_DSGCR_DTOODT_DEFVAL
8851 #undef DDR_PHY_DSGCR_DTOODT_SHIFT
8852 #undef DDR_PHY_DSGCR_DTOODT_MASK
8853 #define DDR_PHY_DSGCR_DTOODT_DEFVAL 0x02A04101
8854 #define DDR_PHY_DSGCR_DTOODT_SHIFT 12
8855 #define DDR_PHY_DSGCR_DTOODT_MASK 0x00001000U
8858 * PHY Update Acknowledge Delay
8860 #undef DDR_PHY_DSGCR_PUAD_DEFVAL
8861 #undef DDR_PHY_DSGCR_PUAD_SHIFT
8862 #undef DDR_PHY_DSGCR_PUAD_MASK
8863 #define DDR_PHY_DSGCR_PUAD_DEFVAL 0x02A04101
8864 #define DDR_PHY_DSGCR_PUAD_SHIFT 6
8865 #define DDR_PHY_DSGCR_PUAD_MASK 0x00000FC0U
8868 * Controller Update Acknowledge Enable
8870 #undef DDR_PHY_DSGCR_CUAEN_DEFVAL
8871 #undef DDR_PHY_DSGCR_CUAEN_SHIFT
8872 #undef DDR_PHY_DSGCR_CUAEN_MASK
8873 #define DDR_PHY_DSGCR_CUAEN_DEFVAL 0x02A04101
8874 #define DDR_PHY_DSGCR_CUAEN_SHIFT 5
8875 #define DDR_PHY_DSGCR_CUAEN_MASK 0x00000020U
8878 * Reserved. Return zeroes on reads
8880 #undef DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL
8881 #undef DDR_PHY_DSGCR_RESERVED_4_3_SHIFT
8882 #undef DDR_PHY_DSGCR_RESERVED_4_3_MASK
8883 #define DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL 0x02A04101
8884 #define DDR_PHY_DSGCR_RESERVED_4_3_SHIFT 3
8885 #define DDR_PHY_DSGCR_RESERVED_4_3_MASK 0x00000018U
8888 * Controller Impedance Update Enable
8890 #undef DDR_PHY_DSGCR_CTLZUEN_DEFVAL
8891 #undef DDR_PHY_DSGCR_CTLZUEN_SHIFT
8892 #undef DDR_PHY_DSGCR_CTLZUEN_MASK
8893 #define DDR_PHY_DSGCR_CTLZUEN_DEFVAL 0x02A04101
8894 #define DDR_PHY_DSGCR_CTLZUEN_SHIFT 2
8895 #define DDR_PHY_DSGCR_CTLZUEN_MASK 0x00000004U
8898 * Reserved. Return zeroes on reads
8900 #undef DDR_PHY_DSGCR_RESERVED_1_DEFVAL
8901 #undef DDR_PHY_DSGCR_RESERVED_1_SHIFT
8902 #undef DDR_PHY_DSGCR_RESERVED_1_MASK
8903 #define DDR_PHY_DSGCR_RESERVED_1_DEFVAL 0x02A04101
8904 #define DDR_PHY_DSGCR_RESERVED_1_SHIFT 1
8905 #define DDR_PHY_DSGCR_RESERVED_1_MASK 0x00000002U
8908 * PHY Update Request Enable
8910 #undef DDR_PHY_DSGCR_PUREN_DEFVAL
8911 #undef DDR_PHY_DSGCR_PUREN_SHIFT
8912 #undef DDR_PHY_DSGCR_PUREN_MASK
8913 #define DDR_PHY_DSGCR_PUREN_DEFVAL 0x02A04101
8914 #define DDR_PHY_DSGCR_PUREN_SHIFT 0
8915 #define DDR_PHY_DSGCR_PUREN_MASK 0x00000001U
8918 * General Purpose Register 0
8920 #undef DDR_PHY_GPR0_GPR0_DEFVAL
8921 #undef DDR_PHY_GPR0_GPR0_SHIFT
8922 #undef DDR_PHY_GPR0_GPR0_MASK
8923 #define DDR_PHY_GPR0_GPR0_DEFVAL
8924 #define DDR_PHY_GPR0_GPR0_SHIFT 0
8925 #define DDR_PHY_GPR0_GPR0_MASK 0xFFFFFFFFU
8928 * DDR4 Gear Down Timing.
8930 #undef DDR_PHY_DCR_GEARDN_DEFVAL
8931 #undef DDR_PHY_DCR_GEARDN_SHIFT
8932 #undef DDR_PHY_DCR_GEARDN_MASK
8933 #define DDR_PHY_DCR_GEARDN_DEFVAL 0x0000040D
8934 #define DDR_PHY_DCR_GEARDN_SHIFT 31
8935 #define DDR_PHY_DCR_GEARDN_MASK 0x80000000U
8938 * Un-used Bank Group
8940 #undef DDR_PHY_DCR_UBG_DEFVAL
8941 #undef DDR_PHY_DCR_UBG_SHIFT
8942 #undef DDR_PHY_DCR_UBG_MASK
8943 #define DDR_PHY_DCR_UBG_DEFVAL 0x0000040D
8944 #define DDR_PHY_DCR_UBG_SHIFT 30
8945 #define DDR_PHY_DCR_UBG_MASK 0x40000000U
8948 * Un-buffered DIMM Address Mirroring
8950 #undef DDR_PHY_DCR_UDIMM_DEFVAL
8951 #undef DDR_PHY_DCR_UDIMM_SHIFT
8952 #undef DDR_PHY_DCR_UDIMM_MASK
8953 #define DDR_PHY_DCR_UDIMM_DEFVAL 0x0000040D
8954 #define DDR_PHY_DCR_UDIMM_SHIFT 29
8955 #define DDR_PHY_DCR_UDIMM_MASK 0x20000000U
8960 #undef DDR_PHY_DCR_DDR2T_DEFVAL
8961 #undef DDR_PHY_DCR_DDR2T_SHIFT
8962 #undef DDR_PHY_DCR_DDR2T_MASK
8963 #define DDR_PHY_DCR_DDR2T_DEFVAL 0x0000040D
8964 #define DDR_PHY_DCR_DDR2T_SHIFT 28
8965 #define DDR_PHY_DCR_DDR2T_MASK 0x10000000U
8968 * No Simultaneous Rank Access
8970 #undef DDR_PHY_DCR_NOSRA_DEFVAL
8971 #undef DDR_PHY_DCR_NOSRA_SHIFT
8972 #undef DDR_PHY_DCR_NOSRA_MASK
8973 #define DDR_PHY_DCR_NOSRA_DEFVAL 0x0000040D
8974 #define DDR_PHY_DCR_NOSRA_SHIFT 27
8975 #define DDR_PHY_DCR_NOSRA_MASK 0x08000000U
8978 * Reserved. Return zeroes on reads.
8980 #undef DDR_PHY_DCR_RESERVED_26_18_DEFVAL
8981 #undef DDR_PHY_DCR_RESERVED_26_18_SHIFT
8982 #undef DDR_PHY_DCR_RESERVED_26_18_MASK
8983 #define DDR_PHY_DCR_RESERVED_26_18_DEFVAL 0x0000040D
8984 #define DDR_PHY_DCR_RESERVED_26_18_SHIFT 18
8985 #define DDR_PHY_DCR_RESERVED_26_18_MASK 0x07FC0000U
8990 #undef DDR_PHY_DCR_BYTEMASK_DEFVAL
8991 #undef DDR_PHY_DCR_BYTEMASK_SHIFT
8992 #undef DDR_PHY_DCR_BYTEMASK_MASK
8993 #define DDR_PHY_DCR_BYTEMASK_DEFVAL 0x0000040D
8994 #define DDR_PHY_DCR_BYTEMASK_SHIFT 10
8995 #define DDR_PHY_DCR_BYTEMASK_MASK 0x0003FC00U
9000 #undef DDR_PHY_DCR_DDRTYPE_DEFVAL
9001 #undef DDR_PHY_DCR_DDRTYPE_SHIFT
9002 #undef DDR_PHY_DCR_DDRTYPE_MASK
9003 #define DDR_PHY_DCR_DDRTYPE_DEFVAL 0x0000040D
9004 #define DDR_PHY_DCR_DDRTYPE_SHIFT 8
9005 #define DDR_PHY_DCR_DDRTYPE_MASK 0x00000300U
9008 * Multi-Purpose Register (MPR) DQ (DDR3 Only)
9010 #undef DDR_PHY_DCR_MPRDQ_DEFVAL
9011 #undef DDR_PHY_DCR_MPRDQ_SHIFT
9012 #undef DDR_PHY_DCR_MPRDQ_MASK
9013 #define DDR_PHY_DCR_MPRDQ_DEFVAL 0x0000040D
9014 #define DDR_PHY_DCR_MPRDQ_SHIFT 7
9015 #define DDR_PHY_DCR_MPRDQ_MASK 0x00000080U
9018 * Primary DQ (DDR3 Only)
9020 #undef DDR_PHY_DCR_PDQ_DEFVAL
9021 #undef DDR_PHY_DCR_PDQ_SHIFT
9022 #undef DDR_PHY_DCR_PDQ_MASK
9023 #define DDR_PHY_DCR_PDQ_DEFVAL 0x0000040D
9024 #define DDR_PHY_DCR_PDQ_SHIFT 4
9025 #define DDR_PHY_DCR_PDQ_MASK 0x00000070U
9030 #undef DDR_PHY_DCR_DDR8BNK_DEFVAL
9031 #undef DDR_PHY_DCR_DDR8BNK_SHIFT
9032 #undef DDR_PHY_DCR_DDR8BNK_MASK
9033 #define DDR_PHY_DCR_DDR8BNK_DEFVAL 0x0000040D
9034 #define DDR_PHY_DCR_DDR8BNK_SHIFT 3
9035 #define DDR_PHY_DCR_DDR8BNK_MASK 0x00000008U
9040 #undef DDR_PHY_DCR_DDRMD_DEFVAL
9041 #undef DDR_PHY_DCR_DDRMD_SHIFT
9042 #undef DDR_PHY_DCR_DDRMD_MASK
9043 #define DDR_PHY_DCR_DDRMD_DEFVAL 0x0000040D
9044 #define DDR_PHY_DCR_DDRMD_SHIFT 0
9045 #define DDR_PHY_DCR_DDRMD_MASK 0x00000007U
9048 * Reserved. Return zeroes on reads.
9050 #undef DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL
9051 #undef DDR_PHY_DTPR0_RESERVED_31_29_SHIFT
9052 #undef DDR_PHY_DTPR0_RESERVED_31_29_MASK
9053 #define DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL 0x105A2D08
9054 #define DDR_PHY_DTPR0_RESERVED_31_29_SHIFT 29
9055 #define DDR_PHY_DTPR0_RESERVED_31_29_MASK 0xE0000000U
9058 * Activate to activate command delay (different banks)
9060 #undef DDR_PHY_DTPR0_TRRD_DEFVAL
9061 #undef DDR_PHY_DTPR0_TRRD_SHIFT
9062 #undef DDR_PHY_DTPR0_TRRD_MASK
9063 #define DDR_PHY_DTPR0_TRRD_DEFVAL 0x105A2D08
9064 #define DDR_PHY_DTPR0_TRRD_SHIFT 24
9065 #define DDR_PHY_DTPR0_TRRD_MASK 0x1F000000U
9068 * Reserved. Return zeroes on reads.
9070 #undef DDR_PHY_DTPR0_RESERVED_23_DEFVAL
9071 #undef DDR_PHY_DTPR0_RESERVED_23_SHIFT
9072 #undef DDR_PHY_DTPR0_RESERVED_23_MASK
9073 #define DDR_PHY_DTPR0_RESERVED_23_DEFVAL 0x105A2D08
9074 #define DDR_PHY_DTPR0_RESERVED_23_SHIFT 23
9075 #define DDR_PHY_DTPR0_RESERVED_23_MASK 0x00800000U
9078 * Activate to precharge command delay
9080 #undef DDR_PHY_DTPR0_TRAS_DEFVAL
9081 #undef DDR_PHY_DTPR0_TRAS_SHIFT
9082 #undef DDR_PHY_DTPR0_TRAS_MASK
9083 #define DDR_PHY_DTPR0_TRAS_DEFVAL 0x105A2D08
9084 #define DDR_PHY_DTPR0_TRAS_SHIFT 16
9085 #define DDR_PHY_DTPR0_TRAS_MASK 0x007F0000U
9088 * Reserved. Return zeroes on reads.
9090 #undef DDR_PHY_DTPR0_RESERVED_15_DEFVAL
9091 #undef DDR_PHY_DTPR0_RESERVED_15_SHIFT
9092 #undef DDR_PHY_DTPR0_RESERVED_15_MASK
9093 #define DDR_PHY_DTPR0_RESERVED_15_DEFVAL 0x105A2D08
9094 #define DDR_PHY_DTPR0_RESERVED_15_SHIFT 15
9095 #define DDR_PHY_DTPR0_RESERVED_15_MASK 0x00008000U
9098 * Precharge command period
9100 #undef DDR_PHY_DTPR0_TRP_DEFVAL
9101 #undef DDR_PHY_DTPR0_TRP_SHIFT
9102 #undef DDR_PHY_DTPR0_TRP_MASK
9103 #define DDR_PHY_DTPR0_TRP_DEFVAL 0x105A2D08
9104 #define DDR_PHY_DTPR0_TRP_SHIFT 8
9105 #define DDR_PHY_DTPR0_TRP_MASK 0x00007F00U
9108 * Reserved. Return zeroes on reads.
9110 #undef DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL
9111 #undef DDR_PHY_DTPR0_RESERVED_7_5_SHIFT
9112 #undef DDR_PHY_DTPR0_RESERVED_7_5_MASK
9113 #define DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL 0x105A2D08
9114 #define DDR_PHY_DTPR0_RESERVED_7_5_SHIFT 5
9115 #define DDR_PHY_DTPR0_RESERVED_7_5_MASK 0x000000E0U
9118 * Internal read to precharge command delay
9120 #undef DDR_PHY_DTPR0_TRTP_DEFVAL
9121 #undef DDR_PHY_DTPR0_TRTP_SHIFT
9122 #undef DDR_PHY_DTPR0_TRTP_MASK
9123 #define DDR_PHY_DTPR0_TRTP_DEFVAL 0x105A2D08
9124 #define DDR_PHY_DTPR0_TRTP_SHIFT 0
9125 #define DDR_PHY_DTPR0_TRTP_MASK 0x0000001FU
9128 * Reserved. Return zeroes on reads.
9130 #undef DDR_PHY_DTPR1_RESERVED_31_DEFVAL
9131 #undef DDR_PHY_DTPR1_RESERVED_31_SHIFT
9132 #undef DDR_PHY_DTPR1_RESERVED_31_MASK
9133 #define DDR_PHY_DTPR1_RESERVED_31_DEFVAL 0x5656041E
9134 #define DDR_PHY_DTPR1_RESERVED_31_SHIFT 31
9135 #define DDR_PHY_DTPR1_RESERVED_31_MASK 0x80000000U
9138 * Minimum delay from when write leveling mode is programmed to the first D
9139 * QS/DQS# rising edge.
9141 #undef DDR_PHY_DTPR1_TWLMRD_DEFVAL
9142 #undef DDR_PHY_DTPR1_TWLMRD_SHIFT
9143 #undef DDR_PHY_DTPR1_TWLMRD_MASK
9144 #define DDR_PHY_DTPR1_TWLMRD_DEFVAL 0x5656041E
9145 #define DDR_PHY_DTPR1_TWLMRD_SHIFT 24
9146 #define DDR_PHY_DTPR1_TWLMRD_MASK 0x7F000000U
9149 * Reserved. Return zeroes on reads.
9151 #undef DDR_PHY_DTPR1_RESERVED_23_DEFVAL
9152 #undef DDR_PHY_DTPR1_RESERVED_23_SHIFT
9153 #undef DDR_PHY_DTPR1_RESERVED_23_MASK
9154 #define DDR_PHY_DTPR1_RESERVED_23_DEFVAL 0x5656041E
9155 #define DDR_PHY_DTPR1_RESERVED_23_SHIFT 23
9156 #define DDR_PHY_DTPR1_RESERVED_23_MASK 0x00800000U
9159 * 4-bank activate period
9161 #undef DDR_PHY_DTPR1_TFAW_DEFVAL
9162 #undef DDR_PHY_DTPR1_TFAW_SHIFT
9163 #undef DDR_PHY_DTPR1_TFAW_MASK
9164 #define DDR_PHY_DTPR1_TFAW_DEFVAL 0x5656041E
9165 #define DDR_PHY_DTPR1_TFAW_SHIFT 16
9166 #define DDR_PHY_DTPR1_TFAW_MASK 0x007F0000U
9169 * Reserved. Return zeroes on reads.
9171 #undef DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL
9172 #undef DDR_PHY_DTPR1_RESERVED_15_11_SHIFT
9173 #undef DDR_PHY_DTPR1_RESERVED_15_11_MASK
9174 #define DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL 0x5656041E
9175 #define DDR_PHY_DTPR1_RESERVED_15_11_SHIFT 11
9176 #define DDR_PHY_DTPR1_RESERVED_15_11_MASK 0x0000F800U
9179 * Load mode update delay (DDR4 and DDR3 only)
9181 #undef DDR_PHY_DTPR1_TMOD_DEFVAL
9182 #undef DDR_PHY_DTPR1_TMOD_SHIFT
9183 #undef DDR_PHY_DTPR1_TMOD_MASK
9184 #define DDR_PHY_DTPR1_TMOD_DEFVAL 0x5656041E
9185 #define DDR_PHY_DTPR1_TMOD_SHIFT 8
9186 #define DDR_PHY_DTPR1_TMOD_MASK 0x00000700U
9189 * Reserved. Return zeroes on reads.
9191 #undef DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL
9192 #undef DDR_PHY_DTPR1_RESERVED_7_5_SHIFT
9193 #undef DDR_PHY_DTPR1_RESERVED_7_5_MASK
9194 #define DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL 0x5656041E
9195 #define DDR_PHY_DTPR1_RESERVED_7_5_SHIFT 5
9196 #define DDR_PHY_DTPR1_RESERVED_7_5_MASK 0x000000E0U
9199 * Load mode cycle time
9201 #undef DDR_PHY_DTPR1_TMRD_DEFVAL
9202 #undef DDR_PHY_DTPR1_TMRD_SHIFT
9203 #undef DDR_PHY_DTPR1_TMRD_MASK
9204 #define DDR_PHY_DTPR1_TMRD_DEFVAL 0x5656041E
9205 #define DDR_PHY_DTPR1_TMRD_SHIFT 0
9206 #define DDR_PHY_DTPR1_TMRD_MASK 0x0000001FU
9209 * Reserved. Return zeroes on reads.
9211 #undef DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL
9212 #undef DDR_PHY_DTPR2_RESERVED_31_29_SHIFT
9213 #undef DDR_PHY_DTPR2_RESERVED_31_29_MASK
9214 #define DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL 0x000B01D0
9215 #define DDR_PHY_DTPR2_RESERVED_31_29_SHIFT 29
9216 #define DDR_PHY_DTPR2_RESERVED_31_29_MASK 0xE0000000U
9219 * Read to Write command delay. Valid values are
9221 #undef DDR_PHY_DTPR2_TRTW_DEFVAL
9222 #undef DDR_PHY_DTPR2_TRTW_SHIFT
9223 #undef DDR_PHY_DTPR2_TRTW_MASK
9224 #define DDR_PHY_DTPR2_TRTW_DEFVAL 0x000B01D0
9225 #define DDR_PHY_DTPR2_TRTW_SHIFT 28
9226 #define DDR_PHY_DTPR2_TRTW_MASK 0x10000000U
9229 * Reserved. Return zeroes on reads.
9231 #undef DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL
9232 #undef DDR_PHY_DTPR2_RESERVED_27_25_SHIFT
9233 #undef DDR_PHY_DTPR2_RESERVED_27_25_MASK
9234 #define DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL 0x000B01D0
9235 #define DDR_PHY_DTPR2_RESERVED_27_25_SHIFT 25
9236 #define DDR_PHY_DTPR2_RESERVED_27_25_MASK 0x0E000000U
9239 * Read to ODT delay (DDR3 only)
9241 #undef DDR_PHY_DTPR2_TRTODT_DEFVAL
9242 #undef DDR_PHY_DTPR2_TRTODT_SHIFT
9243 #undef DDR_PHY_DTPR2_TRTODT_MASK
9244 #define DDR_PHY_DTPR2_TRTODT_DEFVAL 0x000B01D0
9245 #define DDR_PHY_DTPR2_TRTODT_SHIFT 24
9246 #define DDR_PHY_DTPR2_TRTODT_MASK 0x01000000U
9249 * Reserved. Return zeroes on reads.
9251 #undef DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL
9252 #undef DDR_PHY_DTPR2_RESERVED_23_20_SHIFT
9253 #undef DDR_PHY_DTPR2_RESERVED_23_20_MASK
9254 #define DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL 0x000B01D0
9255 #define DDR_PHY_DTPR2_RESERVED_23_20_SHIFT 20
9256 #define DDR_PHY_DTPR2_RESERVED_23_20_MASK 0x00F00000U
9259 * CKE minimum pulse width
9261 #undef DDR_PHY_DTPR2_TCKE_DEFVAL
9262 #undef DDR_PHY_DTPR2_TCKE_SHIFT
9263 #undef DDR_PHY_DTPR2_TCKE_MASK
9264 #define DDR_PHY_DTPR2_TCKE_DEFVAL 0x000B01D0
9265 #define DDR_PHY_DTPR2_TCKE_SHIFT 16
9266 #define DDR_PHY_DTPR2_TCKE_MASK 0x000F0000U
9269 * Reserved. Return zeroes on reads.
9271 #undef DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL
9272 #undef DDR_PHY_DTPR2_RESERVED_15_10_SHIFT
9273 #undef DDR_PHY_DTPR2_RESERVED_15_10_MASK
9274 #define DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL 0x000B01D0
9275 #define DDR_PHY_DTPR2_RESERVED_15_10_SHIFT 10
9276 #define DDR_PHY_DTPR2_RESERVED_15_10_MASK 0x0000FC00U
9279 * Self refresh exit delay
9281 #undef DDR_PHY_DTPR2_TXS_DEFVAL
9282 #undef DDR_PHY_DTPR2_TXS_SHIFT
9283 #undef DDR_PHY_DTPR2_TXS_MASK
9284 #define DDR_PHY_DTPR2_TXS_DEFVAL 0x000B01D0
9285 #define DDR_PHY_DTPR2_TXS_SHIFT 0
9286 #define DDR_PHY_DTPR2_TXS_MASK 0x000003FFU
9289 * ODT turn-off delay extension
9291 #undef DDR_PHY_DTPR3_TOFDX_DEFVAL
9292 #undef DDR_PHY_DTPR3_TOFDX_SHIFT
9293 #undef DDR_PHY_DTPR3_TOFDX_MASK
9294 #define DDR_PHY_DTPR3_TOFDX_DEFVAL 0x02000804
9295 #define DDR_PHY_DTPR3_TOFDX_SHIFT 29
9296 #define DDR_PHY_DTPR3_TOFDX_MASK 0xE0000000U
9299 * Read to read and write to write command delay
9301 #undef DDR_PHY_DTPR3_TCCD_DEFVAL
9302 #undef DDR_PHY_DTPR3_TCCD_SHIFT
9303 #undef DDR_PHY_DTPR3_TCCD_MASK
9304 #define DDR_PHY_DTPR3_TCCD_DEFVAL 0x02000804
9305 #define DDR_PHY_DTPR3_TCCD_SHIFT 26
9306 #define DDR_PHY_DTPR3_TCCD_MASK 0x1C000000U
9311 #undef DDR_PHY_DTPR3_TDLLK_DEFVAL
9312 #undef DDR_PHY_DTPR3_TDLLK_SHIFT
9313 #undef DDR_PHY_DTPR3_TDLLK_MASK
9314 #define DDR_PHY_DTPR3_TDLLK_DEFVAL 0x02000804
9315 #define DDR_PHY_DTPR3_TDLLK_SHIFT 16
9316 #define DDR_PHY_DTPR3_TDLLK_MASK 0x03FF0000U
9319 * Reserved. Return zeroes on reads.
9321 #undef DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL
9322 #undef DDR_PHY_DTPR3_RESERVED_15_12_SHIFT
9323 #undef DDR_PHY_DTPR3_RESERVED_15_12_MASK
9324 #define DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL 0x02000804
9325 #define DDR_PHY_DTPR3_RESERVED_15_12_SHIFT 12
9326 #define DDR_PHY_DTPR3_RESERVED_15_12_MASK 0x0000F000U
9329 * Maximum DQS output access time from CK/CK# (LPDDR2/3 only)
9331 #undef DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL
9332 #undef DDR_PHY_DTPR3_TDQSCKMAX_SHIFT
9333 #undef DDR_PHY_DTPR3_TDQSCKMAX_MASK
9334 #define DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL 0x02000804
9335 #define DDR_PHY_DTPR3_TDQSCKMAX_SHIFT 8
9336 #define DDR_PHY_DTPR3_TDQSCKMAX_MASK 0x00000F00U
9339 * Reserved. Return zeroes on reads.
9341 #undef DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL
9342 #undef DDR_PHY_DTPR3_RESERVED_7_3_SHIFT
9343 #undef DDR_PHY_DTPR3_RESERVED_7_3_MASK
9344 #define DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL 0x02000804
9345 #define DDR_PHY_DTPR3_RESERVED_7_3_SHIFT 3
9346 #define DDR_PHY_DTPR3_RESERVED_7_3_MASK 0x000000F8U
9349 * DQS output access time from CK/CK# (LPDDR2/3 only)
9351 #undef DDR_PHY_DTPR3_TDQSCK_DEFVAL
9352 #undef DDR_PHY_DTPR3_TDQSCK_SHIFT
9353 #undef DDR_PHY_DTPR3_TDQSCK_MASK
9354 #define DDR_PHY_DTPR3_TDQSCK_DEFVAL 0x02000804
9355 #define DDR_PHY_DTPR3_TDQSCK_SHIFT 0
9356 #define DDR_PHY_DTPR3_TDQSCK_MASK 0x00000007U
9359 * Reserved. Return zeroes on reads.
9361 #undef DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL
9362 #undef DDR_PHY_DTPR4_RESERVED_31_30_SHIFT
9363 #undef DDR_PHY_DTPR4_RESERVED_31_30_MASK
9364 #define DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL 0x01C02B10
9365 #define DDR_PHY_DTPR4_RESERVED_31_30_SHIFT 30
9366 #define DDR_PHY_DTPR4_RESERVED_31_30_MASK 0xC0000000U
9369 * ODT turn-on/turn-off delays (DDR2 only)
9371 #undef DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL
9372 #undef DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT
9373 #undef DDR_PHY_DTPR4_TAOND_TAOFD_MASK
9374 #define DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL 0x01C02B10
9375 #define DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT 28
9376 #define DDR_PHY_DTPR4_TAOND_TAOFD_MASK 0x30000000U
9379 * Reserved. Return zeroes on reads.
9381 #undef DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL
9382 #undef DDR_PHY_DTPR4_RESERVED_27_26_SHIFT
9383 #undef DDR_PHY_DTPR4_RESERVED_27_26_MASK
9384 #define DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL 0x01C02B10
9385 #define DDR_PHY_DTPR4_RESERVED_27_26_SHIFT 26
9386 #define DDR_PHY_DTPR4_RESERVED_27_26_MASK 0x0C000000U
9389 * Refresh-to-Refresh
9391 #undef DDR_PHY_DTPR4_TRFC_DEFVAL
9392 #undef DDR_PHY_DTPR4_TRFC_SHIFT
9393 #undef DDR_PHY_DTPR4_TRFC_MASK
9394 #define DDR_PHY_DTPR4_TRFC_DEFVAL 0x01C02B10
9395 #define DDR_PHY_DTPR4_TRFC_SHIFT 16
9396 #define DDR_PHY_DTPR4_TRFC_MASK 0x03FF0000U
9399 * Reserved. Return zeroes on reads.
9401 #undef DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL
9402 #undef DDR_PHY_DTPR4_RESERVED_15_14_SHIFT
9403 #undef DDR_PHY_DTPR4_RESERVED_15_14_MASK
9404 #define DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL 0x01C02B10
9405 #define DDR_PHY_DTPR4_RESERVED_15_14_SHIFT 14
9406 #define DDR_PHY_DTPR4_RESERVED_15_14_MASK 0x0000C000U
9409 * Write leveling output delay
9411 #undef DDR_PHY_DTPR4_TWLO_DEFVAL
9412 #undef DDR_PHY_DTPR4_TWLO_SHIFT
9413 #undef DDR_PHY_DTPR4_TWLO_MASK
9414 #define DDR_PHY_DTPR4_TWLO_DEFVAL 0x01C02B10
9415 #define DDR_PHY_DTPR4_TWLO_SHIFT 8
9416 #define DDR_PHY_DTPR4_TWLO_MASK 0x00003F00U
9419 * Reserved. Return zeroes on reads.
9421 #undef DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL
9422 #undef DDR_PHY_DTPR4_RESERVED_7_5_SHIFT
9423 #undef DDR_PHY_DTPR4_RESERVED_7_5_MASK
9424 #define DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL 0x01C02B10
9425 #define DDR_PHY_DTPR4_RESERVED_7_5_SHIFT 5
9426 #define DDR_PHY_DTPR4_RESERVED_7_5_MASK 0x000000E0U
9429 * Power down exit delay
9431 #undef DDR_PHY_DTPR4_TXP_DEFVAL
9432 #undef DDR_PHY_DTPR4_TXP_SHIFT
9433 #undef DDR_PHY_DTPR4_TXP_MASK
9434 #define DDR_PHY_DTPR4_TXP_DEFVAL 0x01C02B10
9435 #define DDR_PHY_DTPR4_TXP_SHIFT 0
9436 #define DDR_PHY_DTPR4_TXP_MASK 0x0000001FU
9439 * Reserved. Return zeroes on reads.
9441 #undef DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL
9442 #undef DDR_PHY_DTPR5_RESERVED_31_24_SHIFT
9443 #undef DDR_PHY_DTPR5_RESERVED_31_24_MASK
9444 #define DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL 0x00872716
9445 #define DDR_PHY_DTPR5_RESERVED_31_24_SHIFT 24
9446 #define DDR_PHY_DTPR5_RESERVED_31_24_MASK 0xFF000000U
9449 * Activate to activate command delay (same bank)
9451 #undef DDR_PHY_DTPR5_TRC_DEFVAL
9452 #undef DDR_PHY_DTPR5_TRC_SHIFT
9453 #undef DDR_PHY_DTPR5_TRC_MASK
9454 #define DDR_PHY_DTPR5_TRC_DEFVAL 0x00872716
9455 #define DDR_PHY_DTPR5_TRC_SHIFT 16
9456 #define DDR_PHY_DTPR5_TRC_MASK 0x00FF0000U
9459 * Reserved. Return zeroes on reads.
9461 #undef DDR_PHY_DTPR5_RESERVED_15_DEFVAL
9462 #undef DDR_PHY_DTPR5_RESERVED_15_SHIFT
9463 #undef DDR_PHY_DTPR5_RESERVED_15_MASK
9464 #define DDR_PHY_DTPR5_RESERVED_15_DEFVAL 0x00872716
9465 #define DDR_PHY_DTPR5_RESERVED_15_SHIFT 15
9466 #define DDR_PHY_DTPR5_RESERVED_15_MASK 0x00008000U
9469 * Activate to read or write delay
9471 #undef DDR_PHY_DTPR5_TRCD_DEFVAL
9472 #undef DDR_PHY_DTPR5_TRCD_SHIFT
9473 #undef DDR_PHY_DTPR5_TRCD_MASK
9474 #define DDR_PHY_DTPR5_TRCD_DEFVAL 0x00872716
9475 #define DDR_PHY_DTPR5_TRCD_SHIFT 8
9476 #define DDR_PHY_DTPR5_TRCD_MASK 0x00007F00U
9479 * Reserved. Return zeroes on reads.
9481 #undef DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL
9482 #undef DDR_PHY_DTPR5_RESERVED_7_5_SHIFT
9483 #undef DDR_PHY_DTPR5_RESERVED_7_5_MASK
9484 #define DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL 0x00872716
9485 #define DDR_PHY_DTPR5_RESERVED_7_5_SHIFT 5
9486 #define DDR_PHY_DTPR5_RESERVED_7_5_MASK 0x000000E0U
9489 * Internal write to read command delay
9491 #undef DDR_PHY_DTPR5_TWTR_DEFVAL
9492 #undef DDR_PHY_DTPR5_TWTR_SHIFT
9493 #undef DDR_PHY_DTPR5_TWTR_MASK
9494 #define DDR_PHY_DTPR5_TWTR_DEFVAL 0x00872716
9495 #define DDR_PHY_DTPR5_TWTR_SHIFT 0
9496 #define DDR_PHY_DTPR5_TWTR_MASK 0x0000001FU
9499 * PUB Write Latency Enable
9501 #undef DDR_PHY_DTPR6_PUBWLEN_DEFVAL
9502 #undef DDR_PHY_DTPR6_PUBWLEN_SHIFT
9503 #undef DDR_PHY_DTPR6_PUBWLEN_MASK
9504 #define DDR_PHY_DTPR6_PUBWLEN_DEFVAL 0x00000505
9505 #define DDR_PHY_DTPR6_PUBWLEN_SHIFT 31
9506 #define DDR_PHY_DTPR6_PUBWLEN_MASK 0x80000000U
9509 * PUB Read Latency Enable
9511 #undef DDR_PHY_DTPR6_PUBRLEN_DEFVAL
9512 #undef DDR_PHY_DTPR6_PUBRLEN_SHIFT
9513 #undef DDR_PHY_DTPR6_PUBRLEN_MASK
9514 #define DDR_PHY_DTPR6_PUBRLEN_DEFVAL 0x00000505
9515 #define DDR_PHY_DTPR6_PUBRLEN_SHIFT 30
9516 #define DDR_PHY_DTPR6_PUBRLEN_MASK 0x40000000U
9519 * Reserved. Return zeroes on reads.
9521 #undef DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL
9522 #undef DDR_PHY_DTPR6_RESERVED_29_14_SHIFT
9523 #undef DDR_PHY_DTPR6_RESERVED_29_14_MASK
9524 #define DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL 0x00000505
9525 #define DDR_PHY_DTPR6_RESERVED_29_14_SHIFT 14
9526 #define DDR_PHY_DTPR6_RESERVED_29_14_MASK 0x3FFFC000U
9531 #undef DDR_PHY_DTPR6_PUBWL_DEFVAL
9532 #undef DDR_PHY_DTPR6_PUBWL_SHIFT
9533 #undef DDR_PHY_DTPR6_PUBWL_MASK
9534 #define DDR_PHY_DTPR6_PUBWL_DEFVAL 0x00000505
9535 #define DDR_PHY_DTPR6_PUBWL_SHIFT 8
9536 #define DDR_PHY_DTPR6_PUBWL_MASK 0x00003F00U
9539 * Reserved. Return zeroes on reads.
9541 #undef DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL
9542 #undef DDR_PHY_DTPR6_RESERVED_7_6_SHIFT
9543 #undef DDR_PHY_DTPR6_RESERVED_7_6_MASK
9544 #define DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL 0x00000505
9545 #define DDR_PHY_DTPR6_RESERVED_7_6_SHIFT 6
9546 #define DDR_PHY_DTPR6_RESERVED_7_6_MASK 0x000000C0U
9551 #undef DDR_PHY_DTPR6_PUBRL_DEFVAL
9552 #undef DDR_PHY_DTPR6_PUBRL_SHIFT
9553 #undef DDR_PHY_DTPR6_PUBRL_MASK
9554 #define DDR_PHY_DTPR6_PUBRL_DEFVAL 0x00000505
9555 #define DDR_PHY_DTPR6_PUBRL_SHIFT 0
9556 #define DDR_PHY_DTPR6_PUBRL_MASK 0x0000003FU
9559 * Reserved. Return zeroes on reads.
9561 #undef DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL
9562 #undef DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT
9563 #undef DDR_PHY_RDIMMGCR0_RESERVED_31_MASK
9564 #define DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL 0x08400020
9565 #define DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT 31
9566 #define DDR_PHY_RDIMMGCR0_RESERVED_31_MASK 0x80000000U
9569 * RDMIMM Quad CS Enable
9571 #undef DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL
9572 #undef DDR_PHY_RDIMMGCR0_QCSEN_SHIFT
9573 #undef DDR_PHY_RDIMMGCR0_QCSEN_MASK
9574 #define DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL 0x08400020
9575 #define DDR_PHY_RDIMMGCR0_QCSEN_SHIFT 30
9576 #define DDR_PHY_RDIMMGCR0_QCSEN_MASK 0x40000000U
9579 * Reserved. Return zeroes on reads.
9581 #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL
9582 #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT
9583 #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK
9584 #define DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL 0x08400020
9585 #define DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT 28
9586 #define DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK 0x30000000U
9589 * RDIMM Outputs I/O Mode
9591 #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL
9592 #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT
9593 #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK
9594 #define DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL 0x08400020
9595 #define DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT 27
9596 #define DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK 0x08000000U
9599 * Reserved. Return zeroes on reads.
9601 #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL
9602 #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT
9603 #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK
9604 #define DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL 0x08400020
9605 #define DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT 24
9606 #define DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK 0x07000000U
9609 * ERROUT# Output Enable
9611 #undef DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL
9612 #undef DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT
9613 #undef DDR_PHY_RDIMMGCR0_ERROUTOE_MASK
9614 #define DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL 0x08400020
9615 #define DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT 23
9616 #define DDR_PHY_RDIMMGCR0_ERROUTOE_MASK 0x00800000U
9621 #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL
9622 #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT
9623 #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK
9624 #define DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL 0x08400020
9625 #define DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT 22
9626 #define DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK 0x00400000U
9629 * ERROUT# Power Down Receiver
9631 #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL
9632 #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT
9633 #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK
9634 #define DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL 0x08400020
9635 #define DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT 21
9636 #define DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK 0x00200000U
9639 * Reserved. Return zeroes on reads.
9641 #undef DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL
9642 #undef DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT
9643 #undef DDR_PHY_RDIMMGCR0_RESERVED_20_MASK
9644 #define DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL 0x08400020
9645 #define DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT 20
9646 #define DDR_PHY_RDIMMGCR0_RESERVED_20_MASK 0x00100000U
9649 * ERROUT# On-Die Termination
9651 #undef DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL
9652 #undef DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT
9653 #undef DDR_PHY_RDIMMGCR0_ERROUTODT_MASK
9654 #define DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL 0x08400020
9655 #define DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT 19
9656 #define DDR_PHY_RDIMMGCR0_ERROUTODT_MASK 0x00080000U
9661 #undef DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL
9662 #undef DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT
9663 #undef DDR_PHY_RDIMMGCR0_LRDIMM_MASK
9664 #define DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL 0x08400020
9665 #define DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT 18
9666 #define DDR_PHY_RDIMMGCR0_LRDIMM_MASK 0x00040000U
9671 #undef DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL
9672 #undef DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT
9673 #undef DDR_PHY_RDIMMGCR0_PARINIOM_MASK
9674 #define DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL 0x08400020
9675 #define DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT 17
9676 #define DDR_PHY_RDIMMGCR0_PARINIOM_MASK 0x00020000U
9679 * Reserved. Return zeroes on reads.
9681 #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL
9682 #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT
9683 #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK
9684 #define DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL 0x08400020
9685 #define DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT 8
9686 #define DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK 0x0001FF00U
9689 * Reserved. Return zeroes on reads.
9691 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL
9692 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT
9693 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK
9694 #define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL 0x08400020
9695 #define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT 6
9696 #define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK 0x000000C0U
9699 * Rank Mirror Enable.
9701 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL
9702 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT
9703 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_MASK
9704 #define DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL 0x08400020
9705 #define DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT 4
9706 #define DDR_PHY_RDIMMGCR0_RNKMRREN_MASK 0x00000030U
9709 * Reserved. Return zeroes on reads.
9711 #undef DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL
9712 #undef DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT
9713 #undef DDR_PHY_RDIMMGCR0_RESERVED_3_MASK
9714 #define DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL 0x08400020
9715 #define DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT 3
9716 #define DDR_PHY_RDIMMGCR0_RESERVED_3_MASK 0x00000008U
9719 * Stop on Parity Error
9721 #undef DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL
9722 #undef DDR_PHY_RDIMMGCR0_SOPERR_SHIFT
9723 #undef DDR_PHY_RDIMMGCR0_SOPERR_MASK
9724 #define DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL 0x08400020
9725 #define DDR_PHY_RDIMMGCR0_SOPERR_SHIFT 2
9726 #define DDR_PHY_RDIMMGCR0_SOPERR_MASK 0x00000004U
9729 * Parity Error No Registering
9731 #undef DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL
9732 #undef DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT
9733 #undef DDR_PHY_RDIMMGCR0_ERRNOREG_MASK
9734 #define DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL 0x08400020
9735 #define DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT 1
9736 #define DDR_PHY_RDIMMGCR0_ERRNOREG_MASK 0x00000002U
9741 #undef DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL
9742 #undef DDR_PHY_RDIMMGCR0_RDIMM_SHIFT
9743 #undef DDR_PHY_RDIMMGCR0_RDIMM_MASK
9744 #define DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL 0x08400020
9745 #define DDR_PHY_RDIMMGCR0_RDIMM_SHIFT 0
9746 #define DDR_PHY_RDIMMGCR0_RDIMM_MASK 0x00000001U
9749 * Reserved. Return zeroes on reads.
9751 #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL
9752 #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT
9753 #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK
9754 #define DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL 0x00000C80
9755 #define DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT 29
9756 #define DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK 0xE0000000U
9759 * Address [17] B-side Inversion Disable
9761 #undef DDR_PHY_RDIMMGCR1_A17BID_DEFVAL
9762 #undef DDR_PHY_RDIMMGCR1_A17BID_SHIFT
9763 #undef DDR_PHY_RDIMMGCR1_A17BID_MASK
9764 #define DDR_PHY_RDIMMGCR1_A17BID_DEFVAL 0x00000C80
9765 #define DDR_PHY_RDIMMGCR1_A17BID_SHIFT 28
9766 #define DDR_PHY_RDIMMGCR1_A17BID_MASK 0x10000000U
9769 * Reserved. Return zeroes on reads.
9771 #undef DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL
9772 #undef DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT
9773 #undef DDR_PHY_RDIMMGCR1_RESERVED_27_MASK
9774 #define DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL 0x00000C80
9775 #define DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT 27
9776 #define DDR_PHY_RDIMMGCR1_RESERVED_27_MASK 0x08000000U
9779 * Command word to command word programming delay
9781 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL
9782 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT
9783 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK
9784 #define DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL 0x00000C80
9785 #define DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT 24
9786 #define DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK 0x07000000U
9789 * Reserved. Return zeroes on reads.
9791 #undef DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL
9792 #undef DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT
9793 #undef DDR_PHY_RDIMMGCR1_RESERVED_23_MASK
9794 #define DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL 0x00000C80
9795 #define DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT 23
9796 #define DDR_PHY_RDIMMGCR1_RESERVED_23_MASK 0x00800000U
9799 * Command word to command word programming delay
9801 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL
9802 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT
9803 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK
9804 #define DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL 0x00000C80
9805 #define DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT 20
9806 #define DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK 0x00700000U
9809 * Reserved. Return zeroes on reads.
9811 #undef DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL
9812 #undef DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT
9813 #undef DDR_PHY_RDIMMGCR1_RESERVED_19_MASK
9814 #define DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL 0x00000C80
9815 #define DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT 19
9816 #define DDR_PHY_RDIMMGCR1_RESERVED_19_MASK 0x00080000U
9819 * Command word to command word programming delay
9821 #undef DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL
9822 #undef DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT
9823 #undef DDR_PHY_RDIMMGCR1_TBCMRD_MASK
9824 #define DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL 0x00000C80
9825 #define DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT 16
9826 #define DDR_PHY_RDIMMGCR1_TBCMRD_MASK 0x00070000U
9829 * Reserved. Return zeroes on reads.
9831 #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL
9832 #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT
9833 #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK
9834 #define DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL 0x00000C80
9835 #define DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT 14
9836 #define DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK 0x0000C000U
9839 * Stabilization time
9841 #undef DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL
9842 #undef DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT
9843 #undef DDR_PHY_RDIMMGCR1_TBCSTAB_MASK
9844 #define DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL 0x00000C80
9845 #define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT 0
9846 #define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK 0x00003FFFU
9849 * DDR4/DDR3 Control Word 7
9851 #undef DDR_PHY_RDIMMCR0_RC7_DEFVAL
9852 #undef DDR_PHY_RDIMMCR0_RC7_SHIFT
9853 #undef DDR_PHY_RDIMMCR0_RC7_MASK
9854 #define DDR_PHY_RDIMMCR0_RC7_DEFVAL 0x00000000
9855 #define DDR_PHY_RDIMMCR0_RC7_SHIFT 28
9856 #define DDR_PHY_RDIMMCR0_RC7_MASK 0xF0000000U
9859 * DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved
9861 #undef DDR_PHY_RDIMMCR0_RC6_DEFVAL
9862 #undef DDR_PHY_RDIMMCR0_RC6_SHIFT
9863 #undef DDR_PHY_RDIMMCR0_RC6_MASK
9864 #define DDR_PHY_RDIMMCR0_RC6_DEFVAL 0x00000000
9865 #define DDR_PHY_RDIMMCR0_RC6_SHIFT 24
9866 #define DDR_PHY_RDIMMCR0_RC6_MASK 0x0F000000U
9869 * DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)
9871 #undef DDR_PHY_RDIMMCR0_RC5_DEFVAL
9872 #undef DDR_PHY_RDIMMCR0_RC5_SHIFT
9873 #undef DDR_PHY_RDIMMCR0_RC5_MASK
9874 #define DDR_PHY_RDIMMCR0_RC5_DEFVAL 0x00000000
9875 #define DDR_PHY_RDIMMCR0_RC5_SHIFT 20
9876 #define DDR_PHY_RDIMMCR0_RC5_MASK 0x00F00000U
9879 * DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control
9880 * Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont
9883 #undef DDR_PHY_RDIMMCR0_RC4_DEFVAL
9884 #undef DDR_PHY_RDIMMCR0_RC4_SHIFT
9885 #undef DDR_PHY_RDIMMCR0_RC4_MASK
9886 #define DDR_PHY_RDIMMCR0_RC4_DEFVAL 0x00000000
9887 #define DDR_PHY_RDIMMCR0_RC4_SHIFT 16
9888 #define DDR_PHY_RDIMMCR0_RC4_MASK 0x000F0000U
9891 * DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Wo
9892 * rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri
9895 #undef DDR_PHY_RDIMMCR0_RC3_DEFVAL
9896 #undef DDR_PHY_RDIMMCR0_RC3_SHIFT
9897 #undef DDR_PHY_RDIMMCR0_RC3_MASK
9898 #define DDR_PHY_RDIMMCR0_RC3_DEFVAL 0x00000000
9899 #define DDR_PHY_RDIMMCR0_RC3_SHIFT 12
9900 #define DDR_PHY_RDIMMCR0_RC3_MASK 0x0000F000U
9903 * DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2
9904 * (Timing Control Word)
9906 #undef DDR_PHY_RDIMMCR0_RC2_DEFVAL
9907 #undef DDR_PHY_RDIMMCR0_RC2_SHIFT
9908 #undef DDR_PHY_RDIMMCR0_RC2_MASK
9909 #define DDR_PHY_RDIMMCR0_RC2_DEFVAL 0x00000000
9910 #define DDR_PHY_RDIMMCR0_RC2_SHIFT 8
9911 #define DDR_PHY_RDIMMCR0_RC2_MASK 0x00000F00U
9914 * DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)
9916 #undef DDR_PHY_RDIMMCR0_RC1_DEFVAL
9917 #undef DDR_PHY_RDIMMCR0_RC1_SHIFT
9918 #undef DDR_PHY_RDIMMCR0_RC1_MASK
9919 #define DDR_PHY_RDIMMCR0_RC1_DEFVAL 0x00000000
9920 #define DDR_PHY_RDIMMCR0_RC1_SHIFT 4
9921 #define DDR_PHY_RDIMMCR0_RC1_MASK 0x000000F0U
9924 * DDR4/DDR3 Control Word 0 (Global Features Control Word)
9926 #undef DDR_PHY_RDIMMCR0_RC0_DEFVAL
9927 #undef DDR_PHY_RDIMMCR0_RC0_SHIFT
9928 #undef DDR_PHY_RDIMMCR0_RC0_MASK
9929 #define DDR_PHY_RDIMMCR0_RC0_DEFVAL 0x00000000
9930 #define DDR_PHY_RDIMMCR0_RC0_SHIFT 0
9931 #define DDR_PHY_RDIMMCR0_RC0_MASK 0x0000000FU
9936 #undef DDR_PHY_RDIMMCR1_RC15_DEFVAL
9937 #undef DDR_PHY_RDIMMCR1_RC15_SHIFT
9938 #undef DDR_PHY_RDIMMCR1_RC15_MASK
9939 #define DDR_PHY_RDIMMCR1_RC15_DEFVAL 0x00000000
9940 #define DDR_PHY_RDIMMCR1_RC15_SHIFT 28
9941 #define DDR_PHY_RDIMMCR1_RC15_MASK 0xF0000000U
9944 * DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved
9946 #undef DDR_PHY_RDIMMCR1_RC14_DEFVAL
9947 #undef DDR_PHY_RDIMMCR1_RC14_SHIFT
9948 #undef DDR_PHY_RDIMMCR1_RC14_MASK
9949 #define DDR_PHY_RDIMMCR1_RC14_DEFVAL 0x00000000
9950 #define DDR_PHY_RDIMMCR1_RC14_SHIFT 24
9951 #define DDR_PHY_RDIMMCR1_RC14_MASK 0x0F000000U
9954 * DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved
9956 #undef DDR_PHY_RDIMMCR1_RC13_DEFVAL
9957 #undef DDR_PHY_RDIMMCR1_RC13_SHIFT
9958 #undef DDR_PHY_RDIMMCR1_RC13_MASK
9959 #define DDR_PHY_RDIMMCR1_RC13_DEFVAL 0x00000000
9960 #define DDR_PHY_RDIMMCR1_RC13_SHIFT 20
9961 #define DDR_PHY_RDIMMCR1_RC13_MASK 0x00F00000U
9964 * DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved
9966 #undef DDR_PHY_RDIMMCR1_RC12_DEFVAL
9967 #undef DDR_PHY_RDIMMCR1_RC12_SHIFT
9968 #undef DDR_PHY_RDIMMCR1_RC12_MASK
9969 #define DDR_PHY_RDIMMCR1_RC12_DEFVAL 0x00000000
9970 #define DDR_PHY_RDIMMCR1_RC12_SHIFT 16
9971 #define DDR_PHY_RDIMMCR1_RC12_MASK 0x000F0000U
9974 * DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo
9975 * rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word)
9977 #undef DDR_PHY_RDIMMCR1_RC11_DEFVAL
9978 #undef DDR_PHY_RDIMMCR1_RC11_SHIFT
9979 #undef DDR_PHY_RDIMMCR1_RC11_MASK
9980 #define DDR_PHY_RDIMMCR1_RC11_DEFVAL 0x00000000
9981 #define DDR_PHY_RDIMMCR1_RC11_SHIFT 12
9982 #define DDR_PHY_RDIMMCR1_RC11_MASK 0x0000F000U
9985 * DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)
9987 #undef DDR_PHY_RDIMMCR1_RC10_DEFVAL
9988 #undef DDR_PHY_RDIMMCR1_RC10_SHIFT
9989 #undef DDR_PHY_RDIMMCR1_RC10_MASK
9990 #define DDR_PHY_RDIMMCR1_RC10_DEFVAL 0x00000000
9991 #define DDR_PHY_RDIMMCR1_RC10_SHIFT 8
9992 #define DDR_PHY_RDIMMCR1_RC10_MASK 0x00000F00U
9995 * DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)
9997 #undef DDR_PHY_RDIMMCR1_RC9_DEFVAL
9998 #undef DDR_PHY_RDIMMCR1_RC9_SHIFT
9999 #undef DDR_PHY_RDIMMCR1_RC9_MASK
10000 #define DDR_PHY_RDIMMCR1_RC9_DEFVAL 0x00000000
10001 #define DDR_PHY_RDIMMCR1_RC9_SHIFT 4
10002 #define DDR_PHY_RDIMMCR1_RC9_MASK 0x000000F0U
10005 * DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con
10006 * trol Word 8 (Additional Input Bus Termination Setting Control Word)
10008 #undef DDR_PHY_RDIMMCR1_RC8_DEFVAL
10009 #undef DDR_PHY_RDIMMCR1_RC8_SHIFT
10010 #undef DDR_PHY_RDIMMCR1_RC8_MASK
10011 #define DDR_PHY_RDIMMCR1_RC8_DEFVAL 0x00000000
10012 #define DDR_PHY_RDIMMCR1_RC8_SHIFT 0
10013 #define DDR_PHY_RDIMMCR1_RC8_MASK 0x0000000FU
10016 * Reserved. Return zeroes on reads.
10018 #undef DDR_PHY_MR0_RESERVED_31_8_DEFVAL
10019 #undef DDR_PHY_MR0_RESERVED_31_8_SHIFT
10020 #undef DDR_PHY_MR0_RESERVED_31_8_MASK
10021 #define DDR_PHY_MR0_RESERVED_31_8_DEFVAL 0x00000052
10022 #define DDR_PHY_MR0_RESERVED_31_8_SHIFT 8
10023 #define DDR_PHY_MR0_RESERVED_31_8_MASK 0xFFFFFF00U
10026 * CA Terminating Rank
10028 #undef DDR_PHY_MR0_CATR_DEFVAL
10029 #undef DDR_PHY_MR0_CATR_SHIFT
10030 #undef DDR_PHY_MR0_CATR_MASK
10031 #define DDR_PHY_MR0_CATR_DEFVAL 0x00000052
10032 #define DDR_PHY_MR0_CATR_SHIFT 7
10033 #define DDR_PHY_MR0_CATR_MASK 0x00000080U
10036 * Reserved. These are JEDEC reserved bits and are recommended by JEDEC to
10037 * be programmed to 0x0.
10039 #undef DDR_PHY_MR0_RSVD_6_5_DEFVAL
10040 #undef DDR_PHY_MR0_RSVD_6_5_SHIFT
10041 #undef DDR_PHY_MR0_RSVD_6_5_MASK
10042 #define DDR_PHY_MR0_RSVD_6_5_DEFVAL 0x00000052
10043 #define DDR_PHY_MR0_RSVD_6_5_SHIFT 5
10044 #define DDR_PHY_MR0_RSVD_6_5_MASK 0x00000060U
10047 * Built-in Self-Test for RZQ
10049 #undef DDR_PHY_MR0_RZQI_DEFVAL
10050 #undef DDR_PHY_MR0_RZQI_SHIFT
10051 #undef DDR_PHY_MR0_RZQI_MASK
10052 #define DDR_PHY_MR0_RZQI_DEFVAL 0x00000052
10053 #define DDR_PHY_MR0_RZQI_SHIFT 3
10054 #define DDR_PHY_MR0_RZQI_MASK 0x00000018U
10057 * Reserved. These are JEDEC reserved bits and are recommended by JEDEC to
10058 * be programmed to 0x0.
10060 #undef DDR_PHY_MR0_RSVD_2_0_DEFVAL
10061 #undef DDR_PHY_MR0_RSVD_2_0_SHIFT
10062 #undef DDR_PHY_MR0_RSVD_2_0_MASK
10063 #define DDR_PHY_MR0_RSVD_2_0_DEFVAL 0x00000052
10064 #define DDR_PHY_MR0_RSVD_2_0_SHIFT 0
10065 #define DDR_PHY_MR0_RSVD_2_0_MASK 0x00000007U
10068 * Reserved. Return zeroes on reads.
10070 #undef DDR_PHY_MR1_RESERVED_31_8_DEFVAL
10071 #undef DDR_PHY_MR1_RESERVED_31_8_SHIFT
10072 #undef DDR_PHY_MR1_RESERVED_31_8_MASK
10073 #define DDR_PHY_MR1_RESERVED_31_8_DEFVAL 0x00000004
10074 #define DDR_PHY_MR1_RESERVED_31_8_SHIFT 8
10075 #define DDR_PHY_MR1_RESERVED_31_8_MASK 0xFFFFFF00U
10078 * Read Postamble Length
10080 #undef DDR_PHY_MR1_RDPST_DEFVAL
10081 #undef DDR_PHY_MR1_RDPST_SHIFT
10082 #undef DDR_PHY_MR1_RDPST_MASK
10083 #define DDR_PHY_MR1_RDPST_DEFVAL 0x00000004
10084 #define DDR_PHY_MR1_RDPST_SHIFT 7
10085 #define DDR_PHY_MR1_RDPST_MASK 0x00000080U
10088 * Write-recovery for auto-precharge command
10090 #undef DDR_PHY_MR1_NWR_DEFVAL
10091 #undef DDR_PHY_MR1_NWR_SHIFT
10092 #undef DDR_PHY_MR1_NWR_MASK
10093 #define DDR_PHY_MR1_NWR_DEFVAL 0x00000004
10094 #define DDR_PHY_MR1_NWR_SHIFT 4
10095 #define DDR_PHY_MR1_NWR_MASK 0x00000070U
10098 * Read Preamble Length
10100 #undef DDR_PHY_MR1_RDPRE_DEFVAL
10101 #undef DDR_PHY_MR1_RDPRE_SHIFT
10102 #undef DDR_PHY_MR1_RDPRE_MASK
10103 #define DDR_PHY_MR1_RDPRE_DEFVAL 0x00000004
10104 #define DDR_PHY_MR1_RDPRE_SHIFT 3
10105 #define DDR_PHY_MR1_RDPRE_MASK 0x00000008U
10108 * Write Preamble Length
10110 #undef DDR_PHY_MR1_WRPRE_DEFVAL
10111 #undef DDR_PHY_MR1_WRPRE_SHIFT
10112 #undef DDR_PHY_MR1_WRPRE_MASK
10113 #define DDR_PHY_MR1_WRPRE_DEFVAL 0x00000004
10114 #define DDR_PHY_MR1_WRPRE_SHIFT 2
10115 #define DDR_PHY_MR1_WRPRE_MASK 0x00000004U
10120 #undef DDR_PHY_MR1_BL_DEFVAL
10121 #undef DDR_PHY_MR1_BL_SHIFT
10122 #undef DDR_PHY_MR1_BL_MASK
10123 #define DDR_PHY_MR1_BL_DEFVAL 0x00000004
10124 #define DDR_PHY_MR1_BL_SHIFT 0
10125 #define DDR_PHY_MR1_BL_MASK 0x00000003U
10128 * Reserved. Return zeroes on reads.
10130 #undef DDR_PHY_MR2_RESERVED_31_8_DEFVAL
10131 #undef DDR_PHY_MR2_RESERVED_31_8_SHIFT
10132 #undef DDR_PHY_MR2_RESERVED_31_8_MASK
10133 #define DDR_PHY_MR2_RESERVED_31_8_DEFVAL 0x00000000
10134 #define DDR_PHY_MR2_RESERVED_31_8_SHIFT 8
10135 #define DDR_PHY_MR2_RESERVED_31_8_MASK 0xFFFFFF00U
10140 #undef DDR_PHY_MR2_WRL_DEFVAL
10141 #undef DDR_PHY_MR2_WRL_SHIFT
10142 #undef DDR_PHY_MR2_WRL_MASK
10143 #define DDR_PHY_MR2_WRL_DEFVAL 0x00000000
10144 #define DDR_PHY_MR2_WRL_SHIFT 7
10145 #define DDR_PHY_MR2_WRL_MASK 0x00000080U
10148 * Write Latency Set
10150 #undef DDR_PHY_MR2_WLS_DEFVAL
10151 #undef DDR_PHY_MR2_WLS_SHIFT
10152 #undef DDR_PHY_MR2_WLS_MASK
10153 #define DDR_PHY_MR2_WLS_DEFVAL 0x00000000
10154 #define DDR_PHY_MR2_WLS_SHIFT 6
10155 #define DDR_PHY_MR2_WLS_MASK 0x00000040U
10160 #undef DDR_PHY_MR2_WL_DEFVAL
10161 #undef DDR_PHY_MR2_WL_SHIFT
10162 #undef DDR_PHY_MR2_WL_MASK
10163 #define DDR_PHY_MR2_WL_DEFVAL 0x00000000
10164 #define DDR_PHY_MR2_WL_SHIFT 3
10165 #define DDR_PHY_MR2_WL_MASK 0x00000038U
10170 #undef DDR_PHY_MR2_RL_DEFVAL
10171 #undef DDR_PHY_MR2_RL_SHIFT
10172 #undef DDR_PHY_MR2_RL_MASK
10173 #define DDR_PHY_MR2_RL_DEFVAL 0x00000000
10174 #define DDR_PHY_MR2_RL_SHIFT 0
10175 #define DDR_PHY_MR2_RL_MASK 0x00000007U
10178 * Reserved. Return zeroes on reads.
10180 #undef DDR_PHY_MR3_RESERVED_31_8_DEFVAL
10181 #undef DDR_PHY_MR3_RESERVED_31_8_SHIFT
10182 #undef DDR_PHY_MR3_RESERVED_31_8_MASK
10183 #define DDR_PHY_MR3_RESERVED_31_8_DEFVAL 0x00000031
10184 #define DDR_PHY_MR3_RESERVED_31_8_SHIFT 8
10185 #define DDR_PHY_MR3_RESERVED_31_8_MASK 0xFFFFFF00U
10190 #undef DDR_PHY_MR3_DBIWR_DEFVAL
10191 #undef DDR_PHY_MR3_DBIWR_SHIFT
10192 #undef DDR_PHY_MR3_DBIWR_MASK
10193 #define DDR_PHY_MR3_DBIWR_DEFVAL 0x00000031
10194 #define DDR_PHY_MR3_DBIWR_SHIFT 7
10195 #define DDR_PHY_MR3_DBIWR_MASK 0x00000080U
10200 #undef DDR_PHY_MR3_DBIRD_DEFVAL
10201 #undef DDR_PHY_MR3_DBIRD_SHIFT
10202 #undef DDR_PHY_MR3_DBIRD_MASK
10203 #define DDR_PHY_MR3_DBIRD_DEFVAL 0x00000031
10204 #define DDR_PHY_MR3_DBIRD_SHIFT 6
10205 #define DDR_PHY_MR3_DBIRD_MASK 0x00000040U
10208 * Pull-down Drive Strength
10210 #undef DDR_PHY_MR3_PDDS_DEFVAL
10211 #undef DDR_PHY_MR3_PDDS_SHIFT
10212 #undef DDR_PHY_MR3_PDDS_MASK
10213 #define DDR_PHY_MR3_PDDS_DEFVAL 0x00000031
10214 #define DDR_PHY_MR3_PDDS_SHIFT 3
10215 #define DDR_PHY_MR3_PDDS_MASK 0x00000038U
10218 * These are JEDEC reserved bits and are recommended by JEDEC to be program
10221 #undef DDR_PHY_MR3_RSVD_DEFVAL
10222 #undef DDR_PHY_MR3_RSVD_SHIFT
10223 #undef DDR_PHY_MR3_RSVD_MASK
10224 #define DDR_PHY_MR3_RSVD_DEFVAL 0x00000031
10225 #define DDR_PHY_MR3_RSVD_SHIFT 2
10226 #define DDR_PHY_MR3_RSVD_MASK 0x00000004U
10229 * Write Postamble Length
10231 #undef DDR_PHY_MR3_WRPST_DEFVAL
10232 #undef DDR_PHY_MR3_WRPST_SHIFT
10233 #undef DDR_PHY_MR3_WRPST_MASK
10234 #define DDR_PHY_MR3_WRPST_DEFVAL 0x00000031
10235 #define DDR_PHY_MR3_WRPST_SHIFT 1
10236 #define DDR_PHY_MR3_WRPST_MASK 0x00000002U
10239 * Pull-up Calibration Point
10241 #undef DDR_PHY_MR3_PUCAL_DEFVAL
10242 #undef DDR_PHY_MR3_PUCAL_SHIFT
10243 #undef DDR_PHY_MR3_PUCAL_MASK
10244 #define DDR_PHY_MR3_PUCAL_DEFVAL 0x00000031
10245 #define DDR_PHY_MR3_PUCAL_SHIFT 0
10246 #define DDR_PHY_MR3_PUCAL_MASK 0x00000001U
10249 * Reserved. Return zeroes on reads.
10251 #undef DDR_PHY_MR4_RESERVED_31_16_DEFVAL
10252 #undef DDR_PHY_MR4_RESERVED_31_16_SHIFT
10253 #undef DDR_PHY_MR4_RESERVED_31_16_MASK
10254 #define DDR_PHY_MR4_RESERVED_31_16_DEFVAL 0x00000000
10255 #define DDR_PHY_MR4_RESERVED_31_16_SHIFT 16
10256 #define DDR_PHY_MR4_RESERVED_31_16_MASK 0xFFFF0000U
10259 * These are JEDEC reserved bits and are recommended by JEDEC to be program
10262 #undef DDR_PHY_MR4_RSVD_15_13_DEFVAL
10263 #undef DDR_PHY_MR4_RSVD_15_13_SHIFT
10264 #undef DDR_PHY_MR4_RSVD_15_13_MASK
10265 #define DDR_PHY_MR4_RSVD_15_13_DEFVAL 0x00000000
10266 #define DDR_PHY_MR4_RSVD_15_13_SHIFT 13
10267 #define DDR_PHY_MR4_RSVD_15_13_MASK 0x0000E000U
10272 #undef DDR_PHY_MR4_WRP_DEFVAL
10273 #undef DDR_PHY_MR4_WRP_SHIFT
10274 #undef DDR_PHY_MR4_WRP_MASK
10275 #define DDR_PHY_MR4_WRP_DEFVAL 0x00000000
10276 #define DDR_PHY_MR4_WRP_SHIFT 12
10277 #define DDR_PHY_MR4_WRP_MASK 0x00001000U
10282 #undef DDR_PHY_MR4_RDP_DEFVAL
10283 #undef DDR_PHY_MR4_RDP_SHIFT
10284 #undef DDR_PHY_MR4_RDP_MASK
10285 #define DDR_PHY_MR4_RDP_DEFVAL 0x00000000
10286 #define DDR_PHY_MR4_RDP_SHIFT 11
10287 #define DDR_PHY_MR4_RDP_MASK 0x00000800U
10290 * Read Preamble Training Mode
10292 #undef DDR_PHY_MR4_RPTM_DEFVAL
10293 #undef DDR_PHY_MR4_RPTM_SHIFT
10294 #undef DDR_PHY_MR4_RPTM_MASK
10295 #define DDR_PHY_MR4_RPTM_DEFVAL 0x00000000
10296 #define DDR_PHY_MR4_RPTM_SHIFT 10
10297 #define DDR_PHY_MR4_RPTM_MASK 0x00000400U
10300 * Self Refresh Abort
10302 #undef DDR_PHY_MR4_SRA_DEFVAL
10303 #undef DDR_PHY_MR4_SRA_SHIFT
10304 #undef DDR_PHY_MR4_SRA_MASK
10305 #define DDR_PHY_MR4_SRA_DEFVAL 0x00000000
10306 #define DDR_PHY_MR4_SRA_SHIFT 9
10307 #define DDR_PHY_MR4_SRA_MASK 0x00000200U
10310 * CS to Command Latency Mode
10312 #undef DDR_PHY_MR4_CS2CMDL_DEFVAL
10313 #undef DDR_PHY_MR4_CS2CMDL_SHIFT
10314 #undef DDR_PHY_MR4_CS2CMDL_MASK
10315 #define DDR_PHY_MR4_CS2CMDL_DEFVAL 0x00000000
10316 #define DDR_PHY_MR4_CS2CMDL_SHIFT 6
10317 #define DDR_PHY_MR4_CS2CMDL_MASK 0x000001C0U
10320 * These are JEDEC reserved bits and are recommended by JEDEC to be program
10323 #undef DDR_PHY_MR4_RSVD1_DEFVAL
10324 #undef DDR_PHY_MR4_RSVD1_SHIFT
10325 #undef DDR_PHY_MR4_RSVD1_MASK
10326 #define DDR_PHY_MR4_RSVD1_DEFVAL 0x00000000
10327 #define DDR_PHY_MR4_RSVD1_SHIFT 5
10328 #define DDR_PHY_MR4_RSVD1_MASK 0x00000020U
10331 * Internal VREF Monitor
10333 #undef DDR_PHY_MR4_IVM_DEFVAL
10334 #undef DDR_PHY_MR4_IVM_SHIFT
10335 #undef DDR_PHY_MR4_IVM_MASK
10336 #define DDR_PHY_MR4_IVM_DEFVAL 0x00000000
10337 #define DDR_PHY_MR4_IVM_SHIFT 4
10338 #define DDR_PHY_MR4_IVM_MASK 0x00000010U
10341 * Temperature Controlled Refresh Mode
10343 #undef DDR_PHY_MR4_TCRM_DEFVAL
10344 #undef DDR_PHY_MR4_TCRM_SHIFT
10345 #undef DDR_PHY_MR4_TCRM_MASK
10346 #define DDR_PHY_MR4_TCRM_DEFVAL 0x00000000
10347 #define DDR_PHY_MR4_TCRM_SHIFT 3
10348 #define DDR_PHY_MR4_TCRM_MASK 0x00000008U
10351 * Temperature Controlled Refresh Range
10353 #undef DDR_PHY_MR4_TCRR_DEFVAL
10354 #undef DDR_PHY_MR4_TCRR_SHIFT
10355 #undef DDR_PHY_MR4_TCRR_MASK
10356 #define DDR_PHY_MR4_TCRR_DEFVAL 0x00000000
10357 #define DDR_PHY_MR4_TCRR_SHIFT 2
10358 #define DDR_PHY_MR4_TCRR_MASK 0x00000004U
10361 * Maximum Power Down Mode
10363 #undef DDR_PHY_MR4_MPDM_DEFVAL
10364 #undef DDR_PHY_MR4_MPDM_SHIFT
10365 #undef DDR_PHY_MR4_MPDM_MASK
10366 #define DDR_PHY_MR4_MPDM_DEFVAL 0x00000000
10367 #define DDR_PHY_MR4_MPDM_SHIFT 1
10368 #define DDR_PHY_MR4_MPDM_MASK 0x00000002U
10371 * This is a JEDEC reserved bit and is recommended by JEDEC to be programme
10374 #undef DDR_PHY_MR4_RSVD_0_DEFVAL
10375 #undef DDR_PHY_MR4_RSVD_0_SHIFT
10376 #undef DDR_PHY_MR4_RSVD_0_MASK
10377 #define DDR_PHY_MR4_RSVD_0_DEFVAL 0x00000000
10378 #define DDR_PHY_MR4_RSVD_0_SHIFT 0
10379 #define DDR_PHY_MR4_RSVD_0_MASK 0x00000001U
10382 * Reserved. Return zeroes on reads.
10384 #undef DDR_PHY_MR5_RESERVED_31_16_DEFVAL
10385 #undef DDR_PHY_MR5_RESERVED_31_16_SHIFT
10386 #undef DDR_PHY_MR5_RESERVED_31_16_MASK
10387 #define DDR_PHY_MR5_RESERVED_31_16_DEFVAL 0x00000000
10388 #define DDR_PHY_MR5_RESERVED_31_16_SHIFT 16
10389 #define DDR_PHY_MR5_RESERVED_31_16_MASK 0xFFFF0000U
10392 * These are JEDEC reserved bits and are recommended by JEDEC to be program
10395 #undef DDR_PHY_MR5_RSVD_DEFVAL
10396 #undef DDR_PHY_MR5_RSVD_SHIFT
10397 #undef DDR_PHY_MR5_RSVD_MASK
10398 #define DDR_PHY_MR5_RSVD_DEFVAL 0x00000000
10399 #define DDR_PHY_MR5_RSVD_SHIFT 13
10400 #define DDR_PHY_MR5_RSVD_MASK 0x0000E000U
10405 #undef DDR_PHY_MR5_RDBI_DEFVAL
10406 #undef DDR_PHY_MR5_RDBI_SHIFT
10407 #undef DDR_PHY_MR5_RDBI_MASK
10408 #define DDR_PHY_MR5_RDBI_DEFVAL 0x00000000
10409 #define DDR_PHY_MR5_RDBI_SHIFT 12
10410 #define DDR_PHY_MR5_RDBI_MASK 0x00001000U
10415 #undef DDR_PHY_MR5_WDBI_DEFVAL
10416 #undef DDR_PHY_MR5_WDBI_SHIFT
10417 #undef DDR_PHY_MR5_WDBI_MASK
10418 #define DDR_PHY_MR5_WDBI_DEFVAL 0x00000000
10419 #define DDR_PHY_MR5_WDBI_SHIFT 11
10420 #define DDR_PHY_MR5_WDBI_MASK 0x00000800U
10425 #undef DDR_PHY_MR5_DM_DEFVAL
10426 #undef DDR_PHY_MR5_DM_SHIFT
10427 #undef DDR_PHY_MR5_DM_MASK
10428 #define DDR_PHY_MR5_DM_DEFVAL 0x00000000
10429 #define DDR_PHY_MR5_DM_SHIFT 10
10430 #define DDR_PHY_MR5_DM_MASK 0x00000400U
10433 * CA Parity Persistent Error
10435 #undef DDR_PHY_MR5_CAPPE_DEFVAL
10436 #undef DDR_PHY_MR5_CAPPE_SHIFT
10437 #undef DDR_PHY_MR5_CAPPE_MASK
10438 #define DDR_PHY_MR5_CAPPE_DEFVAL 0x00000000
10439 #define DDR_PHY_MR5_CAPPE_SHIFT 9
10440 #define DDR_PHY_MR5_CAPPE_MASK 0x00000200U
10445 #undef DDR_PHY_MR5_RTTPARK_DEFVAL
10446 #undef DDR_PHY_MR5_RTTPARK_SHIFT
10447 #undef DDR_PHY_MR5_RTTPARK_MASK
10448 #define DDR_PHY_MR5_RTTPARK_DEFVAL 0x00000000
10449 #define DDR_PHY_MR5_RTTPARK_SHIFT 6
10450 #define DDR_PHY_MR5_RTTPARK_MASK 0x000001C0U
10453 * ODT Input Buffer during Power Down mode
10455 #undef DDR_PHY_MR5_ODTIBPD_DEFVAL
10456 #undef DDR_PHY_MR5_ODTIBPD_SHIFT
10457 #undef DDR_PHY_MR5_ODTIBPD_MASK
10458 #define DDR_PHY_MR5_ODTIBPD_DEFVAL 0x00000000
10459 #define DDR_PHY_MR5_ODTIBPD_SHIFT 5
10460 #define DDR_PHY_MR5_ODTIBPD_MASK 0x00000020U
10463 * C/A Parity Error Status
10465 #undef DDR_PHY_MR5_CAPES_DEFVAL
10466 #undef DDR_PHY_MR5_CAPES_SHIFT
10467 #undef DDR_PHY_MR5_CAPES_MASK
10468 #define DDR_PHY_MR5_CAPES_DEFVAL 0x00000000
10469 #define DDR_PHY_MR5_CAPES_SHIFT 4
10470 #define DDR_PHY_MR5_CAPES_MASK 0x00000010U
10475 #undef DDR_PHY_MR5_CRCEC_DEFVAL
10476 #undef DDR_PHY_MR5_CRCEC_SHIFT
10477 #undef DDR_PHY_MR5_CRCEC_MASK
10478 #define DDR_PHY_MR5_CRCEC_DEFVAL 0x00000000
10479 #define DDR_PHY_MR5_CRCEC_SHIFT 3
10480 #define DDR_PHY_MR5_CRCEC_MASK 0x00000008U
10483 * C/A Parity Latency Mode
10485 #undef DDR_PHY_MR5_CAPM_DEFVAL
10486 #undef DDR_PHY_MR5_CAPM_SHIFT
10487 #undef DDR_PHY_MR5_CAPM_MASK
10488 #define DDR_PHY_MR5_CAPM_DEFVAL 0x00000000
10489 #define DDR_PHY_MR5_CAPM_SHIFT 0
10490 #define DDR_PHY_MR5_CAPM_MASK 0x00000007U
10493 * Reserved. Return zeroes on reads.
10495 #undef DDR_PHY_MR6_RESERVED_31_16_DEFVAL
10496 #undef DDR_PHY_MR6_RESERVED_31_16_SHIFT
10497 #undef DDR_PHY_MR6_RESERVED_31_16_MASK
10498 #define DDR_PHY_MR6_RESERVED_31_16_DEFVAL 0x00000000
10499 #define DDR_PHY_MR6_RESERVED_31_16_SHIFT 16
10500 #define DDR_PHY_MR6_RESERVED_31_16_MASK 0xFFFF0000U
10503 * These are JEDEC reserved bits and are recommended by JEDEC to be program
10506 #undef DDR_PHY_MR6_RSVD_15_13_DEFVAL
10507 #undef DDR_PHY_MR6_RSVD_15_13_SHIFT
10508 #undef DDR_PHY_MR6_RSVD_15_13_MASK
10509 #define DDR_PHY_MR6_RSVD_15_13_DEFVAL 0x00000000
10510 #define DDR_PHY_MR6_RSVD_15_13_SHIFT 13
10511 #define DDR_PHY_MR6_RSVD_15_13_MASK 0x0000E000U
10514 * CAS_n to CAS_n command delay for same bank group (tCCD_L)
10516 #undef DDR_PHY_MR6_TCCDL_DEFVAL
10517 #undef DDR_PHY_MR6_TCCDL_SHIFT
10518 #undef DDR_PHY_MR6_TCCDL_MASK
10519 #define DDR_PHY_MR6_TCCDL_DEFVAL 0x00000000
10520 #define DDR_PHY_MR6_TCCDL_SHIFT 10
10521 #define DDR_PHY_MR6_TCCDL_MASK 0x00001C00U
10524 * These are JEDEC reserved bits and are recommended by JEDEC to be program
10527 #undef DDR_PHY_MR6_RSVD_9_8_DEFVAL
10528 #undef DDR_PHY_MR6_RSVD_9_8_SHIFT
10529 #undef DDR_PHY_MR6_RSVD_9_8_MASK
10530 #define DDR_PHY_MR6_RSVD_9_8_DEFVAL 0x00000000
10531 #define DDR_PHY_MR6_RSVD_9_8_SHIFT 8
10532 #define DDR_PHY_MR6_RSVD_9_8_MASK 0x00000300U
10535 * VrefDQ Training Enable
10537 #undef DDR_PHY_MR6_VDDQTEN_DEFVAL
10538 #undef DDR_PHY_MR6_VDDQTEN_SHIFT
10539 #undef DDR_PHY_MR6_VDDQTEN_MASK
10540 #define DDR_PHY_MR6_VDDQTEN_DEFVAL 0x00000000
10541 #define DDR_PHY_MR6_VDDQTEN_SHIFT 7
10542 #define DDR_PHY_MR6_VDDQTEN_MASK 0x00000080U
10545 * VrefDQ Training Range
10547 #undef DDR_PHY_MR6_VDQTRG_DEFVAL
10548 #undef DDR_PHY_MR6_VDQTRG_SHIFT
10549 #undef DDR_PHY_MR6_VDQTRG_MASK
10550 #define DDR_PHY_MR6_VDQTRG_DEFVAL 0x00000000
10551 #define DDR_PHY_MR6_VDQTRG_SHIFT 6
10552 #define DDR_PHY_MR6_VDQTRG_MASK 0x00000040U
10555 * VrefDQ Training Values
10557 #undef DDR_PHY_MR6_VDQTVAL_DEFVAL
10558 #undef DDR_PHY_MR6_VDQTVAL_SHIFT
10559 #undef DDR_PHY_MR6_VDQTVAL_MASK
10560 #define DDR_PHY_MR6_VDQTVAL_DEFVAL 0x00000000
10561 #define DDR_PHY_MR6_VDQTVAL_SHIFT 0
10562 #define DDR_PHY_MR6_VDQTVAL_MASK 0x0000003FU
10565 * Reserved. Return zeroes on reads.
10567 #undef DDR_PHY_MR11_RESERVED_31_8_DEFVAL
10568 #undef DDR_PHY_MR11_RESERVED_31_8_SHIFT
10569 #undef DDR_PHY_MR11_RESERVED_31_8_MASK
10570 #define DDR_PHY_MR11_RESERVED_31_8_DEFVAL 0x00000000
10571 #define DDR_PHY_MR11_RESERVED_31_8_SHIFT 8
10572 #define DDR_PHY_MR11_RESERVED_31_8_MASK 0xFFFFFF00U
10575 * These are JEDEC reserved bits and are recommended by JEDEC to be program
10578 #undef DDR_PHY_MR11_RSVD_DEFVAL
10579 #undef DDR_PHY_MR11_RSVD_SHIFT
10580 #undef DDR_PHY_MR11_RSVD_MASK
10581 #define DDR_PHY_MR11_RSVD_DEFVAL 0x00000000
10582 #define DDR_PHY_MR11_RSVD_SHIFT 3
10583 #define DDR_PHY_MR11_RSVD_MASK 0x000000F8U
10586 * Power Down Control
10588 #undef DDR_PHY_MR11_PDCTL_DEFVAL
10589 #undef DDR_PHY_MR11_PDCTL_SHIFT
10590 #undef DDR_PHY_MR11_PDCTL_MASK
10591 #define DDR_PHY_MR11_PDCTL_DEFVAL 0x00000000
10592 #define DDR_PHY_MR11_PDCTL_SHIFT 2
10593 #define DDR_PHY_MR11_PDCTL_MASK 0x00000004U
10596 * DQ Bus Receiver On-Die-Termination
10598 #undef DDR_PHY_MR11_DQODT_DEFVAL
10599 #undef DDR_PHY_MR11_DQODT_SHIFT
10600 #undef DDR_PHY_MR11_DQODT_MASK
10601 #define DDR_PHY_MR11_DQODT_DEFVAL 0x00000000
10602 #define DDR_PHY_MR11_DQODT_SHIFT 0
10603 #define DDR_PHY_MR11_DQODT_MASK 0x00000003U
10606 * Reserved. Return zeroes on reads.
10608 #undef DDR_PHY_MR12_RESERVED_31_8_DEFVAL
10609 #undef DDR_PHY_MR12_RESERVED_31_8_SHIFT
10610 #undef DDR_PHY_MR12_RESERVED_31_8_MASK
10611 #define DDR_PHY_MR12_RESERVED_31_8_DEFVAL 0x0000004D
10612 #define DDR_PHY_MR12_RESERVED_31_8_SHIFT 8
10613 #define DDR_PHY_MR12_RESERVED_31_8_MASK 0xFFFFFF00U
10616 * These are JEDEC reserved bits and are recommended by JEDEC to be program
10619 #undef DDR_PHY_MR12_RSVD_DEFVAL
10620 #undef DDR_PHY_MR12_RSVD_SHIFT
10621 #undef DDR_PHY_MR12_RSVD_MASK
10622 #define DDR_PHY_MR12_RSVD_DEFVAL 0x0000004D
10623 #define DDR_PHY_MR12_RSVD_SHIFT 7
10624 #define DDR_PHY_MR12_RSVD_MASK 0x00000080U
10627 * VREF_CA Range Select.
10629 #undef DDR_PHY_MR12_VR_CA_DEFVAL
10630 #undef DDR_PHY_MR12_VR_CA_SHIFT
10631 #undef DDR_PHY_MR12_VR_CA_MASK
10632 #define DDR_PHY_MR12_VR_CA_DEFVAL 0x0000004D
10633 #define DDR_PHY_MR12_VR_CA_SHIFT 6
10634 #define DDR_PHY_MR12_VR_CA_MASK 0x00000040U
10637 * Controls the VREF(ca) levels for Frequency-Set-Point[1:0].
10639 #undef DDR_PHY_MR12_VREF_CA_DEFVAL
10640 #undef DDR_PHY_MR12_VREF_CA_SHIFT
10641 #undef DDR_PHY_MR12_VREF_CA_MASK
10642 #define DDR_PHY_MR12_VREF_CA_DEFVAL 0x0000004D
10643 #define DDR_PHY_MR12_VREF_CA_SHIFT 0
10644 #define DDR_PHY_MR12_VREF_CA_MASK 0x0000003FU
10647 * Reserved. Return zeroes on reads.
10649 #undef DDR_PHY_MR13_RESERVED_31_8_DEFVAL
10650 #undef DDR_PHY_MR13_RESERVED_31_8_SHIFT
10651 #undef DDR_PHY_MR13_RESERVED_31_8_MASK
10652 #define DDR_PHY_MR13_RESERVED_31_8_DEFVAL 0x00000000
10653 #define DDR_PHY_MR13_RESERVED_31_8_SHIFT 8
10654 #define DDR_PHY_MR13_RESERVED_31_8_MASK 0xFFFFFF00U
10657 * Frequency Set Point Operation Mode
10659 #undef DDR_PHY_MR13_FSPOP_DEFVAL
10660 #undef DDR_PHY_MR13_FSPOP_SHIFT
10661 #undef DDR_PHY_MR13_FSPOP_MASK
10662 #define DDR_PHY_MR13_FSPOP_DEFVAL 0x00000000
10663 #define DDR_PHY_MR13_FSPOP_SHIFT 7
10664 #define DDR_PHY_MR13_FSPOP_MASK 0x00000080U
10667 * Frequency Set Point Write Enable
10669 #undef DDR_PHY_MR13_FSPWR_DEFVAL
10670 #undef DDR_PHY_MR13_FSPWR_SHIFT
10671 #undef DDR_PHY_MR13_FSPWR_MASK
10672 #define DDR_PHY_MR13_FSPWR_DEFVAL 0x00000000
10673 #define DDR_PHY_MR13_FSPWR_SHIFT 6
10674 #define DDR_PHY_MR13_FSPWR_MASK 0x00000040U
10679 #undef DDR_PHY_MR13_DMD_DEFVAL
10680 #undef DDR_PHY_MR13_DMD_SHIFT
10681 #undef DDR_PHY_MR13_DMD_MASK
10682 #define DDR_PHY_MR13_DMD_DEFVAL 0x00000000
10683 #define DDR_PHY_MR13_DMD_SHIFT 5
10684 #define DDR_PHY_MR13_DMD_MASK 0x00000020U
10687 * Refresh Rate Option
10689 #undef DDR_PHY_MR13_RRO_DEFVAL
10690 #undef DDR_PHY_MR13_RRO_SHIFT
10691 #undef DDR_PHY_MR13_RRO_MASK
10692 #define DDR_PHY_MR13_RRO_DEFVAL 0x00000000
10693 #define DDR_PHY_MR13_RRO_SHIFT 4
10694 #define DDR_PHY_MR13_RRO_MASK 0x00000010U
10697 * VREF Current Generator
10699 #undef DDR_PHY_MR13_VRCG_DEFVAL
10700 #undef DDR_PHY_MR13_VRCG_SHIFT
10701 #undef DDR_PHY_MR13_VRCG_MASK
10702 #define DDR_PHY_MR13_VRCG_DEFVAL 0x00000000
10703 #define DDR_PHY_MR13_VRCG_SHIFT 3
10704 #define DDR_PHY_MR13_VRCG_MASK 0x00000008U
10709 #undef DDR_PHY_MR13_VRO_DEFVAL
10710 #undef DDR_PHY_MR13_VRO_SHIFT
10711 #undef DDR_PHY_MR13_VRO_MASK
10712 #define DDR_PHY_MR13_VRO_DEFVAL 0x00000000
10713 #define DDR_PHY_MR13_VRO_SHIFT 2
10714 #define DDR_PHY_MR13_VRO_MASK 0x00000004U
10717 * Read Preamble Training Mode
10719 #undef DDR_PHY_MR13_RPT_DEFVAL
10720 #undef DDR_PHY_MR13_RPT_SHIFT
10721 #undef DDR_PHY_MR13_RPT_MASK
10722 #define DDR_PHY_MR13_RPT_DEFVAL 0x00000000
10723 #define DDR_PHY_MR13_RPT_SHIFT 1
10724 #define DDR_PHY_MR13_RPT_MASK 0x00000002U
10727 * Command Bus Training
10729 #undef DDR_PHY_MR13_CBT_DEFVAL
10730 #undef DDR_PHY_MR13_CBT_SHIFT
10731 #undef DDR_PHY_MR13_CBT_MASK
10732 #define DDR_PHY_MR13_CBT_DEFVAL 0x00000000
10733 #define DDR_PHY_MR13_CBT_SHIFT 0
10734 #define DDR_PHY_MR13_CBT_MASK 0x00000001U
10737 * Reserved. Return zeroes on reads.
10739 #undef DDR_PHY_MR14_RESERVED_31_8_DEFVAL
10740 #undef DDR_PHY_MR14_RESERVED_31_8_SHIFT
10741 #undef DDR_PHY_MR14_RESERVED_31_8_MASK
10742 #define DDR_PHY_MR14_RESERVED_31_8_DEFVAL 0x0000004D
10743 #define DDR_PHY_MR14_RESERVED_31_8_SHIFT 8
10744 #define DDR_PHY_MR14_RESERVED_31_8_MASK 0xFFFFFF00U
10747 * These are JEDEC reserved bits and are recommended by JEDEC to be program
10750 #undef DDR_PHY_MR14_RSVD_DEFVAL
10751 #undef DDR_PHY_MR14_RSVD_SHIFT
10752 #undef DDR_PHY_MR14_RSVD_MASK
10753 #define DDR_PHY_MR14_RSVD_DEFVAL 0x0000004D
10754 #define DDR_PHY_MR14_RSVD_SHIFT 7
10755 #define DDR_PHY_MR14_RSVD_MASK 0x00000080U
10758 * VREFDQ Range Selects.
10760 #undef DDR_PHY_MR14_VR_DQ_DEFVAL
10761 #undef DDR_PHY_MR14_VR_DQ_SHIFT
10762 #undef DDR_PHY_MR14_VR_DQ_MASK
10763 #define DDR_PHY_MR14_VR_DQ_DEFVAL 0x0000004D
10764 #define DDR_PHY_MR14_VR_DQ_SHIFT 6
10765 #define DDR_PHY_MR14_VR_DQ_MASK 0x00000040U
10768 * Reserved. Return zeroes on reads.
10770 #undef DDR_PHY_MR14_VREF_DQ_DEFVAL
10771 #undef DDR_PHY_MR14_VREF_DQ_SHIFT
10772 #undef DDR_PHY_MR14_VREF_DQ_MASK
10773 #define DDR_PHY_MR14_VREF_DQ_DEFVAL 0x0000004D
10774 #define DDR_PHY_MR14_VREF_DQ_SHIFT 0
10775 #define DDR_PHY_MR14_VREF_DQ_MASK 0x0000003FU
10778 * Reserved. Return zeroes on reads.
10780 #undef DDR_PHY_MR22_RESERVED_31_8_DEFVAL
10781 #undef DDR_PHY_MR22_RESERVED_31_8_SHIFT
10782 #undef DDR_PHY_MR22_RESERVED_31_8_MASK
10783 #define DDR_PHY_MR22_RESERVED_31_8_DEFVAL 0x00000000
10784 #define DDR_PHY_MR22_RESERVED_31_8_SHIFT 8
10785 #define DDR_PHY_MR22_RESERVED_31_8_MASK 0xFFFFFF00U
10788 * These are JEDEC reserved bits and are recommended by JEDEC to be program
10791 #undef DDR_PHY_MR22_RSVD_DEFVAL
10792 #undef DDR_PHY_MR22_RSVD_SHIFT
10793 #undef DDR_PHY_MR22_RSVD_MASK
10794 #define DDR_PHY_MR22_RSVD_DEFVAL 0x00000000
10795 #define DDR_PHY_MR22_RSVD_SHIFT 6
10796 #define DDR_PHY_MR22_RSVD_MASK 0x000000C0U
10799 * CA ODT termination disable.
10801 #undef DDR_PHY_MR22_ODTD_CA_DEFVAL
10802 #undef DDR_PHY_MR22_ODTD_CA_SHIFT
10803 #undef DDR_PHY_MR22_ODTD_CA_MASK
10804 #define DDR_PHY_MR22_ODTD_CA_DEFVAL 0x00000000
10805 #define DDR_PHY_MR22_ODTD_CA_SHIFT 5
10806 #define DDR_PHY_MR22_ODTD_CA_MASK 0x00000020U
10811 #undef DDR_PHY_MR22_ODTE_CS_DEFVAL
10812 #undef DDR_PHY_MR22_ODTE_CS_SHIFT
10813 #undef DDR_PHY_MR22_ODTE_CS_MASK
10814 #define DDR_PHY_MR22_ODTE_CS_DEFVAL 0x00000000
10815 #define DDR_PHY_MR22_ODTE_CS_SHIFT 4
10816 #define DDR_PHY_MR22_ODTE_CS_MASK 0x00000010U
10821 #undef DDR_PHY_MR22_ODTE_CK_DEFVAL
10822 #undef DDR_PHY_MR22_ODTE_CK_SHIFT
10823 #undef DDR_PHY_MR22_ODTE_CK_MASK
10824 #define DDR_PHY_MR22_ODTE_CK_DEFVAL 0x00000000
10825 #define DDR_PHY_MR22_ODTE_CK_SHIFT 3
10826 #define DDR_PHY_MR22_ODTE_CK_MASK 0x00000008U
10829 * Controller ODT value for VOH calibration.
10831 #undef DDR_PHY_MR22_CODT_DEFVAL
10832 #undef DDR_PHY_MR22_CODT_SHIFT
10833 #undef DDR_PHY_MR22_CODT_MASK
10834 #define DDR_PHY_MR22_CODT_DEFVAL 0x00000000
10835 #define DDR_PHY_MR22_CODT_SHIFT 0
10836 #define DDR_PHY_MR22_CODT_MASK 0x00000007U
10839 * Refresh During Training
10841 #undef DDR_PHY_DTCR0_RFSHDT_DEFVAL
10842 #undef DDR_PHY_DTCR0_RFSHDT_SHIFT
10843 #undef DDR_PHY_DTCR0_RFSHDT_MASK
10844 #define DDR_PHY_DTCR0_RFSHDT_DEFVAL 0x800091C7
10845 #define DDR_PHY_DTCR0_RFSHDT_SHIFT 28
10846 #define DDR_PHY_DTCR0_RFSHDT_MASK 0xF0000000U
10849 * Reserved. Return zeroes on reads.
10851 #undef DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL
10852 #undef DDR_PHY_DTCR0_RESERVED_27_26_SHIFT
10853 #undef DDR_PHY_DTCR0_RESERVED_27_26_MASK
10854 #define DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL 0x800091C7
10855 #define DDR_PHY_DTCR0_RESERVED_27_26_SHIFT 26
10856 #define DDR_PHY_DTCR0_RESERVED_27_26_MASK 0x0C000000U
10859 * Data Training Debug Rank Select
10861 #undef DDR_PHY_DTCR0_DTDRS_DEFVAL
10862 #undef DDR_PHY_DTCR0_DTDRS_SHIFT
10863 #undef DDR_PHY_DTCR0_DTDRS_MASK
10864 #define DDR_PHY_DTCR0_DTDRS_DEFVAL 0x800091C7
10865 #define DDR_PHY_DTCR0_DTDRS_SHIFT 24
10866 #define DDR_PHY_DTCR0_DTDRS_MASK 0x03000000U
10869 * Data Training with Early/Extended Gate
10871 #undef DDR_PHY_DTCR0_DTEXG_DEFVAL
10872 #undef DDR_PHY_DTCR0_DTEXG_SHIFT
10873 #undef DDR_PHY_DTCR0_DTEXG_MASK
10874 #define DDR_PHY_DTCR0_DTEXG_DEFVAL 0x800091C7
10875 #define DDR_PHY_DTCR0_DTEXG_SHIFT 23
10876 #define DDR_PHY_DTCR0_DTEXG_MASK 0x00800000U
10879 * Data Training Extended Write DQS
10881 #undef DDR_PHY_DTCR0_DTEXD_DEFVAL
10882 #undef DDR_PHY_DTCR0_DTEXD_SHIFT
10883 #undef DDR_PHY_DTCR0_DTEXD_MASK
10884 #define DDR_PHY_DTCR0_DTEXD_DEFVAL 0x800091C7
10885 #define DDR_PHY_DTCR0_DTEXD_SHIFT 22
10886 #define DDR_PHY_DTCR0_DTEXD_MASK 0x00400000U
10889 * Data Training Debug Step
10891 #undef DDR_PHY_DTCR0_DTDSTP_DEFVAL
10892 #undef DDR_PHY_DTCR0_DTDSTP_SHIFT
10893 #undef DDR_PHY_DTCR0_DTDSTP_MASK
10894 #define DDR_PHY_DTCR0_DTDSTP_DEFVAL 0x800091C7
10895 #define DDR_PHY_DTCR0_DTDSTP_SHIFT 21
10896 #define DDR_PHY_DTCR0_DTDSTP_MASK 0x00200000U
10899 * Data Training Debug Enable
10901 #undef DDR_PHY_DTCR0_DTDEN_DEFVAL
10902 #undef DDR_PHY_DTCR0_DTDEN_SHIFT
10903 #undef DDR_PHY_DTCR0_DTDEN_MASK
10904 #define DDR_PHY_DTCR0_DTDEN_DEFVAL 0x800091C7
10905 #define DDR_PHY_DTCR0_DTDEN_SHIFT 20
10906 #define DDR_PHY_DTCR0_DTDEN_MASK 0x00100000U
10909 * Data Training Debug Byte Select
10911 #undef DDR_PHY_DTCR0_DTDBS_DEFVAL
10912 #undef DDR_PHY_DTCR0_DTDBS_SHIFT
10913 #undef DDR_PHY_DTCR0_DTDBS_MASK
10914 #define DDR_PHY_DTCR0_DTDBS_DEFVAL 0x800091C7
10915 #define DDR_PHY_DTCR0_DTDBS_SHIFT 16
10916 #define DDR_PHY_DTCR0_DTDBS_MASK 0x000F0000U
10919 * Data Training read DBI deskewing configuration
10921 #undef DDR_PHY_DTCR0_DTRDBITR_DEFVAL
10922 #undef DDR_PHY_DTCR0_DTRDBITR_SHIFT
10923 #undef DDR_PHY_DTCR0_DTRDBITR_MASK
10924 #define DDR_PHY_DTCR0_DTRDBITR_DEFVAL 0x800091C7
10925 #define DDR_PHY_DTCR0_DTRDBITR_SHIFT 14
10926 #define DDR_PHY_DTCR0_DTRDBITR_MASK 0x0000C000U
10929 * Reserved. Return zeroes on reads.
10931 #undef DDR_PHY_DTCR0_RESERVED_13_DEFVAL
10932 #undef DDR_PHY_DTCR0_RESERVED_13_SHIFT
10933 #undef DDR_PHY_DTCR0_RESERVED_13_MASK
10934 #define DDR_PHY_DTCR0_RESERVED_13_DEFVAL 0x800091C7
10935 #define DDR_PHY_DTCR0_RESERVED_13_SHIFT 13
10936 #define DDR_PHY_DTCR0_RESERVED_13_MASK 0x00002000U
10939 * Data Training Write Bit Deskew Data Mask
10941 #undef DDR_PHY_DTCR0_DTWBDDM_DEFVAL
10942 #undef DDR_PHY_DTCR0_DTWBDDM_SHIFT
10943 #undef DDR_PHY_DTCR0_DTWBDDM_MASK
10944 #define DDR_PHY_DTCR0_DTWBDDM_DEFVAL 0x800091C7
10945 #define DDR_PHY_DTCR0_DTWBDDM_SHIFT 12
10946 #define DDR_PHY_DTCR0_DTWBDDM_MASK 0x00001000U
10949 * Refreshes Issued During Entry to Training
10951 #undef DDR_PHY_DTCR0_RFSHEN_DEFVAL
10952 #undef DDR_PHY_DTCR0_RFSHEN_SHIFT
10953 #undef DDR_PHY_DTCR0_RFSHEN_MASK
10954 #define DDR_PHY_DTCR0_RFSHEN_DEFVAL 0x800091C7
10955 #define DDR_PHY_DTCR0_RFSHEN_SHIFT 8
10956 #define DDR_PHY_DTCR0_RFSHEN_MASK 0x00000F00U
10959 * Data Training Compare Data
10961 #undef DDR_PHY_DTCR0_DTCMPD_DEFVAL
10962 #undef DDR_PHY_DTCR0_DTCMPD_SHIFT
10963 #undef DDR_PHY_DTCR0_DTCMPD_MASK
10964 #define DDR_PHY_DTCR0_DTCMPD_DEFVAL 0x800091C7
10965 #define DDR_PHY_DTCR0_DTCMPD_SHIFT 7
10966 #define DDR_PHY_DTCR0_DTCMPD_MASK 0x00000080U
10969 * Data Training Using MPR
10971 #undef DDR_PHY_DTCR0_DTMPR_DEFVAL
10972 #undef DDR_PHY_DTCR0_DTMPR_SHIFT
10973 #undef DDR_PHY_DTCR0_DTMPR_MASK
10974 #define DDR_PHY_DTCR0_DTMPR_DEFVAL 0x800091C7
10975 #define DDR_PHY_DTCR0_DTMPR_SHIFT 6
10976 #define DDR_PHY_DTCR0_DTMPR_MASK 0x00000040U
10979 * Reserved. Return zeroes on reads.
10981 #undef DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL
10982 #undef DDR_PHY_DTCR0_RESERVED_5_4_SHIFT
10983 #undef DDR_PHY_DTCR0_RESERVED_5_4_MASK
10984 #define DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL 0x800091C7
10985 #define DDR_PHY_DTCR0_RESERVED_5_4_SHIFT 4
10986 #define DDR_PHY_DTCR0_RESERVED_5_4_MASK 0x00000030U
10989 * Data Training Repeat Number
10991 #undef DDR_PHY_DTCR0_DTRPTN_DEFVAL
10992 #undef DDR_PHY_DTCR0_DTRPTN_SHIFT
10993 #undef DDR_PHY_DTCR0_DTRPTN_MASK
10994 #define DDR_PHY_DTCR0_DTRPTN_DEFVAL 0x800091C7
10995 #define DDR_PHY_DTCR0_DTRPTN_SHIFT 0
10996 #define DDR_PHY_DTCR0_DTRPTN_MASK 0x0000000FU
11001 #undef DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL
11002 #undef DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT
11003 #undef DDR_PHY_DTCR1_RANKEN_RSVD_MASK
11004 #define DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL 0x00030237
11005 #define DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT 18
11006 #define DDR_PHY_DTCR1_RANKEN_RSVD_MASK 0xFFFC0000U
11011 #undef DDR_PHY_DTCR1_RANKEN_DEFVAL
11012 #undef DDR_PHY_DTCR1_RANKEN_SHIFT
11013 #undef DDR_PHY_DTCR1_RANKEN_MASK
11014 #define DDR_PHY_DTCR1_RANKEN_DEFVAL 0x00030237
11015 #define DDR_PHY_DTCR1_RANKEN_SHIFT 16
11016 #define DDR_PHY_DTCR1_RANKEN_MASK 0x00030000U
11019 * Reserved. Return zeroes on reads.
11021 #undef DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL
11022 #undef DDR_PHY_DTCR1_RESERVED_15_14_SHIFT
11023 #undef DDR_PHY_DTCR1_RESERVED_15_14_MASK
11024 #define DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL 0x00030237
11025 #define DDR_PHY_DTCR1_RESERVED_15_14_SHIFT 14
11026 #define DDR_PHY_DTCR1_RESERVED_15_14_MASK 0x0000C000U
11029 * Data Training Rank
11031 #undef DDR_PHY_DTCR1_DTRANK_DEFVAL
11032 #undef DDR_PHY_DTCR1_DTRANK_SHIFT
11033 #undef DDR_PHY_DTCR1_DTRANK_MASK
11034 #define DDR_PHY_DTCR1_DTRANK_DEFVAL 0x00030237
11035 #define DDR_PHY_DTCR1_DTRANK_SHIFT 12
11036 #define DDR_PHY_DTCR1_DTRANK_MASK 0x00003000U
11039 * Reserved. Return zeroes on reads.
11041 #undef DDR_PHY_DTCR1_RESERVED_11_DEFVAL
11042 #undef DDR_PHY_DTCR1_RESERVED_11_SHIFT
11043 #undef DDR_PHY_DTCR1_RESERVED_11_MASK
11044 #define DDR_PHY_DTCR1_RESERVED_11_DEFVAL 0x00030237
11045 #define DDR_PHY_DTCR1_RESERVED_11_SHIFT 11
11046 #define DDR_PHY_DTCR1_RESERVED_11_MASK 0x00000800U
11049 * Read Leveling Gate Sampling Difference
11051 #undef DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL
11052 #undef DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT
11053 #undef DDR_PHY_DTCR1_RDLVLGDIFF_MASK
11054 #define DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL 0x00030237
11055 #define DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT 8
11056 #define DDR_PHY_DTCR1_RDLVLGDIFF_MASK 0x00000700U
11059 * Reserved. Return zeroes on reads.
11061 #undef DDR_PHY_DTCR1_RESERVED_7_DEFVAL
11062 #undef DDR_PHY_DTCR1_RESERVED_7_SHIFT
11063 #undef DDR_PHY_DTCR1_RESERVED_7_MASK
11064 #define DDR_PHY_DTCR1_RESERVED_7_DEFVAL 0x00030237
11065 #define DDR_PHY_DTCR1_RESERVED_7_SHIFT 7
11066 #define DDR_PHY_DTCR1_RESERVED_7_MASK 0x00000080U
11069 * Read Leveling Gate Shift
11071 #undef DDR_PHY_DTCR1_RDLVLGS_DEFVAL
11072 #undef DDR_PHY_DTCR1_RDLVLGS_SHIFT
11073 #undef DDR_PHY_DTCR1_RDLVLGS_MASK
11074 #define DDR_PHY_DTCR1_RDLVLGS_DEFVAL 0x00030237
11075 #define DDR_PHY_DTCR1_RDLVLGS_SHIFT 4
11076 #define DDR_PHY_DTCR1_RDLVLGS_MASK 0x00000070U
11079 * Reserved. Return zeroes on reads.
11081 #undef DDR_PHY_DTCR1_RESERVED_3_DEFVAL
11082 #undef DDR_PHY_DTCR1_RESERVED_3_SHIFT
11083 #undef DDR_PHY_DTCR1_RESERVED_3_MASK
11084 #define DDR_PHY_DTCR1_RESERVED_3_DEFVAL 0x00030237
11085 #define DDR_PHY_DTCR1_RESERVED_3_SHIFT 3
11086 #define DDR_PHY_DTCR1_RESERVED_3_MASK 0x00000008U
11089 * Read Preamble Training enable
11091 #undef DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL
11092 #undef DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT
11093 #undef DDR_PHY_DTCR1_RDPRMVL_TRN_MASK
11094 #define DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL 0x00030237
11095 #define DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT 2
11096 #define DDR_PHY_DTCR1_RDPRMVL_TRN_MASK 0x00000004U
11099 * Read Leveling Enable
11101 #undef DDR_PHY_DTCR1_RDLVLEN_DEFVAL
11102 #undef DDR_PHY_DTCR1_RDLVLEN_SHIFT
11103 #undef DDR_PHY_DTCR1_RDLVLEN_MASK
11104 #define DDR_PHY_DTCR1_RDLVLEN_DEFVAL 0x00030237
11105 #define DDR_PHY_DTCR1_RDLVLEN_SHIFT 1
11106 #define DDR_PHY_DTCR1_RDLVLEN_MASK 0x00000002U
11109 * Basic Gate Training Enable
11111 #undef DDR_PHY_DTCR1_BSTEN_DEFVAL
11112 #undef DDR_PHY_DTCR1_BSTEN_SHIFT
11113 #undef DDR_PHY_DTCR1_BSTEN_MASK
11114 #define DDR_PHY_DTCR1_BSTEN_DEFVAL 0x00030237
11115 #define DDR_PHY_DTCR1_BSTEN_SHIFT 0
11116 #define DDR_PHY_DTCR1_BSTEN_MASK 0x00000001U
11119 * Reserved. Return zeroes on reads.
11121 #undef DDR_PHY_CATR0_RESERVED_31_21_DEFVAL
11122 #undef DDR_PHY_CATR0_RESERVED_31_21_SHIFT
11123 #undef DDR_PHY_CATR0_RESERVED_31_21_MASK
11124 #define DDR_PHY_CATR0_RESERVED_31_21_DEFVAL 0x00141054
11125 #define DDR_PHY_CATR0_RESERVED_31_21_SHIFT 21
11126 #define DDR_PHY_CATR0_RESERVED_31_21_MASK 0xFFE00000U
11129 * Minimum time (in terms of number of dram clocks) between two consectuve
11130 * CA calibration command
11132 #undef DDR_PHY_CATR0_CACD_DEFVAL
11133 #undef DDR_PHY_CATR0_CACD_SHIFT
11134 #undef DDR_PHY_CATR0_CACD_MASK
11135 #define DDR_PHY_CATR0_CACD_DEFVAL 0x00141054
11136 #define DDR_PHY_CATR0_CACD_SHIFT 16
11137 #define DDR_PHY_CATR0_CACD_MASK 0x001F0000U
11140 * Reserved. Return zeroes on reads.
11142 #undef DDR_PHY_CATR0_RESERVED_15_13_DEFVAL
11143 #undef DDR_PHY_CATR0_RESERVED_15_13_SHIFT
11144 #undef DDR_PHY_CATR0_RESERVED_15_13_MASK
11145 #define DDR_PHY_CATR0_RESERVED_15_13_DEFVAL 0x00141054
11146 #define DDR_PHY_CATR0_RESERVED_15_13_SHIFT 13
11147 #define DDR_PHY_CATR0_RESERVED_15_13_MASK 0x0000E000U
11150 * Minimum time (in terms of number of dram clocks) PUB should wait before
11151 * sampling the CA response after Calibration command has been sent to the
11154 #undef DDR_PHY_CATR0_CAADR_DEFVAL
11155 #undef DDR_PHY_CATR0_CAADR_SHIFT
11156 #undef DDR_PHY_CATR0_CAADR_MASK
11157 #define DDR_PHY_CATR0_CAADR_DEFVAL 0x00141054
11158 #define DDR_PHY_CATR0_CAADR_SHIFT 8
11159 #define DDR_PHY_CATR0_CAADR_MASK 0x00001F00U
11162 * CA_1 Response Byte Lane 1
11164 #undef DDR_PHY_CATR0_CA1BYTE1_DEFVAL
11165 #undef DDR_PHY_CATR0_CA1BYTE1_SHIFT
11166 #undef DDR_PHY_CATR0_CA1BYTE1_MASK
11167 #define DDR_PHY_CATR0_CA1BYTE1_DEFVAL 0x00141054
11168 #define DDR_PHY_CATR0_CA1BYTE1_SHIFT 4
11169 #define DDR_PHY_CATR0_CA1BYTE1_MASK 0x000000F0U
11172 * CA_1 Response Byte Lane 0
11174 #undef DDR_PHY_CATR0_CA1BYTE0_DEFVAL
11175 #undef DDR_PHY_CATR0_CA1BYTE0_SHIFT
11176 #undef DDR_PHY_CATR0_CA1BYTE0_MASK
11177 #define DDR_PHY_CATR0_CA1BYTE0_DEFVAL 0x00141054
11178 #define DDR_PHY_CATR0_CA1BYTE0_SHIFT 0
11179 #define DDR_PHY_CATR0_CA1BYTE0_MASK 0x0000000FU
11182 * Number of delay taps by which the DQS gate LCDL will be updated when DQS
11183 * drift is detected
11185 #undef DDR_PHY_DQSDR0_DFTDLY_DEFVAL
11186 #undef DDR_PHY_DQSDR0_DFTDLY_SHIFT
11187 #undef DDR_PHY_DQSDR0_DFTDLY_MASK
11188 #define DDR_PHY_DQSDR0_DFTDLY_DEFVAL 0x00088000
11189 #define DDR_PHY_DQSDR0_DFTDLY_SHIFT 28
11190 #define DDR_PHY_DQSDR0_DFTDLY_MASK 0xF0000000U
11193 * Drift Impedance Update
11195 #undef DDR_PHY_DQSDR0_DFTZQUP_DEFVAL
11196 #undef DDR_PHY_DQSDR0_DFTZQUP_SHIFT
11197 #undef DDR_PHY_DQSDR0_DFTZQUP_MASK
11198 #define DDR_PHY_DQSDR0_DFTZQUP_DEFVAL 0x00088000
11199 #define DDR_PHY_DQSDR0_DFTZQUP_SHIFT 27
11200 #define DDR_PHY_DQSDR0_DFTZQUP_MASK 0x08000000U
11205 #undef DDR_PHY_DQSDR0_DFTDDLUP_DEFVAL
11206 #undef DDR_PHY_DQSDR0_DFTDDLUP_SHIFT
11207 #undef DDR_PHY_DQSDR0_DFTDDLUP_MASK
11208 #define DDR_PHY_DQSDR0_DFTDDLUP_DEFVAL 0x00088000
11209 #define DDR_PHY_DQSDR0_DFTDDLUP_SHIFT 26
11210 #define DDR_PHY_DQSDR0_DFTDDLUP_MASK 0x04000000U
11213 * Reserved. Return zeroes on reads.
11215 #undef DDR_PHY_DQSDR0_RESERVED_25_22_DEFVAL
11216 #undef DDR_PHY_DQSDR0_RESERVED_25_22_SHIFT
11217 #undef DDR_PHY_DQSDR0_RESERVED_25_22_MASK
11218 #define DDR_PHY_DQSDR0_RESERVED_25_22_DEFVAL 0x00088000
11219 #define DDR_PHY_DQSDR0_RESERVED_25_22_SHIFT 22
11220 #define DDR_PHY_DQSDR0_RESERVED_25_22_MASK 0x03C00000U
11223 * Drift Read Spacing
11225 #undef DDR_PHY_DQSDR0_DFTRDSPC_DEFVAL
11226 #undef DDR_PHY_DQSDR0_DFTRDSPC_SHIFT
11227 #undef DDR_PHY_DQSDR0_DFTRDSPC_MASK
11228 #define DDR_PHY_DQSDR0_DFTRDSPC_DEFVAL 0x00088000
11229 #define DDR_PHY_DQSDR0_DFTRDSPC_SHIFT 20
11230 #define DDR_PHY_DQSDR0_DFTRDSPC_MASK 0x00300000U
11233 * Drift Back-to-Back Reads
11235 #undef DDR_PHY_DQSDR0_DFTB2BRD_DEFVAL
11236 #undef DDR_PHY_DQSDR0_DFTB2BRD_SHIFT
11237 #undef DDR_PHY_DQSDR0_DFTB2BRD_MASK
11238 #define DDR_PHY_DQSDR0_DFTB2BRD_DEFVAL 0x00088000
11239 #define DDR_PHY_DQSDR0_DFTB2BRD_SHIFT 16
11240 #define DDR_PHY_DQSDR0_DFTB2BRD_MASK 0x000F0000U
11245 #undef DDR_PHY_DQSDR0_DFTIDLRD_DEFVAL
11246 #undef DDR_PHY_DQSDR0_DFTIDLRD_SHIFT
11247 #undef DDR_PHY_DQSDR0_DFTIDLRD_MASK
11248 #define DDR_PHY_DQSDR0_DFTIDLRD_DEFVAL 0x00088000
11249 #define DDR_PHY_DQSDR0_DFTIDLRD_SHIFT 12
11250 #define DDR_PHY_DQSDR0_DFTIDLRD_MASK 0x0000F000U
11253 * Reserved. Return zeroes on reads.
11255 #undef DDR_PHY_DQSDR0_RESERVED_11_8_DEFVAL
11256 #undef DDR_PHY_DQSDR0_RESERVED_11_8_SHIFT
11257 #undef DDR_PHY_DQSDR0_RESERVED_11_8_MASK
11258 #define DDR_PHY_DQSDR0_RESERVED_11_8_DEFVAL 0x00088000
11259 #define DDR_PHY_DQSDR0_RESERVED_11_8_SHIFT 8
11260 #define DDR_PHY_DQSDR0_RESERVED_11_8_MASK 0x00000F00U
11263 * Gate Pulse Enable
11265 #undef DDR_PHY_DQSDR0_DFTGPULSE_DEFVAL
11266 #undef DDR_PHY_DQSDR0_DFTGPULSE_SHIFT
11267 #undef DDR_PHY_DQSDR0_DFTGPULSE_MASK
11268 #define DDR_PHY_DQSDR0_DFTGPULSE_DEFVAL 0x00088000
11269 #define DDR_PHY_DQSDR0_DFTGPULSE_SHIFT 4
11270 #define DDR_PHY_DQSDR0_DFTGPULSE_MASK 0x000000F0U
11273 * DQS Drift Update Mode
11275 #undef DDR_PHY_DQSDR0_DFTUPMODE_DEFVAL
11276 #undef DDR_PHY_DQSDR0_DFTUPMODE_SHIFT
11277 #undef DDR_PHY_DQSDR0_DFTUPMODE_MASK
11278 #define DDR_PHY_DQSDR0_DFTUPMODE_DEFVAL 0x00088000
11279 #define DDR_PHY_DQSDR0_DFTUPMODE_SHIFT 2
11280 #define DDR_PHY_DQSDR0_DFTUPMODE_MASK 0x0000000CU
11283 * DQS Drift Detection Mode
11285 #undef DDR_PHY_DQSDR0_DFTDTMODE_DEFVAL
11286 #undef DDR_PHY_DQSDR0_DFTDTMODE_SHIFT
11287 #undef DDR_PHY_DQSDR0_DFTDTMODE_MASK
11288 #define DDR_PHY_DQSDR0_DFTDTMODE_DEFVAL 0x00088000
11289 #define DDR_PHY_DQSDR0_DFTDTMODE_SHIFT 1
11290 #define DDR_PHY_DQSDR0_DFTDTMODE_MASK 0x00000002U
11293 * DQS Drift Detection Enable
11295 #undef DDR_PHY_DQSDR0_DFTDTEN_DEFVAL
11296 #undef DDR_PHY_DQSDR0_DFTDTEN_SHIFT
11297 #undef DDR_PHY_DQSDR0_DFTDTEN_MASK
11298 #define DDR_PHY_DQSDR0_DFTDTEN_DEFVAL 0x00088000
11299 #define DDR_PHY_DQSDR0_DFTDTEN_SHIFT 0
11300 #define DDR_PHY_DQSDR0_DFTDTEN_MASK 0x00000001U
11303 * LFSR seed for pseudo-random BIST patterns
11305 #undef DDR_PHY_BISTLSR_SEED_DEFVAL
11306 #undef DDR_PHY_BISTLSR_SEED_SHIFT
11307 #undef DDR_PHY_BISTLSR_SEED_MASK
11308 #define DDR_PHY_BISTLSR_SEED_DEFVAL
11309 #define DDR_PHY_BISTLSR_SEED_SHIFT 0
11310 #define DDR_PHY_BISTLSR_SEED_MASK 0xFFFFFFFFU
11313 * Reserved. Return zeroes on reads.
11315 #undef DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL
11316 #undef DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT
11317 #undef DDR_PHY_RIOCR5_RESERVED_31_16_MASK
11318 #define DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL 0x00000005
11319 #define DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT 16
11320 #define DDR_PHY_RIOCR5_RESERVED_31_16_MASK 0xFFFF0000U
11323 * Reserved. Return zeros on reads.
11325 #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL
11326 #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT
11327 #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK
11328 #define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL 0x00000005
11329 #define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT 4
11330 #define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK 0x0000FFF0U
11333 * SDRAM On-die Termination Output Enable (OE) Mode Selection.
11335 #undef DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL
11336 #undef DDR_PHY_RIOCR5_ODTOEMODE_SHIFT
11337 #undef DDR_PHY_RIOCR5_ODTOEMODE_MASK
11338 #define DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL 0x00000005
11339 #define DDR_PHY_RIOCR5_ODTOEMODE_SHIFT 0
11340 #define DDR_PHY_RIOCR5_ODTOEMODE_MASK 0x0000000FU
11343 * Address/Command Slew Rate (D3F I/O Only)
11345 #undef DDR_PHY_ACIOCR0_ACSR_DEFVAL
11346 #undef DDR_PHY_ACIOCR0_ACSR_SHIFT
11347 #undef DDR_PHY_ACIOCR0_ACSR_MASK
11348 #define DDR_PHY_ACIOCR0_ACSR_DEFVAL 0x30000000
11349 #define DDR_PHY_ACIOCR0_ACSR_SHIFT 30
11350 #define DDR_PHY_ACIOCR0_ACSR_MASK 0xC0000000U
11353 * SDRAM Reset I/O Mode
11355 #undef DDR_PHY_ACIOCR0_RSTIOM_DEFVAL
11356 #undef DDR_PHY_ACIOCR0_RSTIOM_SHIFT
11357 #undef DDR_PHY_ACIOCR0_RSTIOM_MASK
11358 #define DDR_PHY_ACIOCR0_RSTIOM_DEFVAL 0x30000000
11359 #define DDR_PHY_ACIOCR0_RSTIOM_SHIFT 29
11360 #define DDR_PHY_ACIOCR0_RSTIOM_MASK 0x20000000U
11363 * SDRAM Reset Power Down Receiver
11365 #undef DDR_PHY_ACIOCR0_RSTPDR_DEFVAL
11366 #undef DDR_PHY_ACIOCR0_RSTPDR_SHIFT
11367 #undef DDR_PHY_ACIOCR0_RSTPDR_MASK
11368 #define DDR_PHY_ACIOCR0_RSTPDR_DEFVAL 0x30000000
11369 #define DDR_PHY_ACIOCR0_RSTPDR_SHIFT 28
11370 #define DDR_PHY_ACIOCR0_RSTPDR_MASK 0x10000000U
11373 * Reserved. Return zeroes on reads.
11375 #undef DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL
11376 #undef DDR_PHY_ACIOCR0_RESERVED_27_SHIFT
11377 #undef DDR_PHY_ACIOCR0_RESERVED_27_MASK
11378 #define DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL 0x30000000
11379 #define DDR_PHY_ACIOCR0_RESERVED_27_SHIFT 27
11380 #define DDR_PHY_ACIOCR0_RESERVED_27_MASK 0x08000000U
11383 * SDRAM Reset On-Die Termination
11385 #undef DDR_PHY_ACIOCR0_RSTODT_DEFVAL
11386 #undef DDR_PHY_ACIOCR0_RSTODT_SHIFT
11387 #undef DDR_PHY_ACIOCR0_RSTODT_MASK
11388 #define DDR_PHY_ACIOCR0_RSTODT_DEFVAL 0x30000000
11389 #define DDR_PHY_ACIOCR0_RSTODT_SHIFT 26
11390 #define DDR_PHY_ACIOCR0_RSTODT_MASK 0x04000000U
11393 * Reserved. Return zeroes on reads.
11395 #undef DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL
11396 #undef DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT
11397 #undef DDR_PHY_ACIOCR0_RESERVED_25_10_MASK
11398 #define DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL 0x30000000
11399 #define DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT 10
11400 #define DDR_PHY_ACIOCR0_RESERVED_25_10_MASK 0x03FFFC00U
11403 * CK Duty Cycle Correction
11405 #undef DDR_PHY_ACIOCR0_CKDCC_DEFVAL
11406 #undef DDR_PHY_ACIOCR0_CKDCC_SHIFT
11407 #undef DDR_PHY_ACIOCR0_CKDCC_MASK
11408 #define DDR_PHY_ACIOCR0_CKDCC_DEFVAL 0x30000000
11409 #define DDR_PHY_ACIOCR0_CKDCC_SHIFT 6
11410 #define DDR_PHY_ACIOCR0_CKDCC_MASK 0x000003C0U
11413 * AC Power Down Receiver Mode
11415 #undef DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL
11416 #undef DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT
11417 #undef DDR_PHY_ACIOCR0_ACPDRMODE_MASK
11418 #define DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL 0x30000000
11419 #define DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT 4
11420 #define DDR_PHY_ACIOCR0_ACPDRMODE_MASK 0x00000030U
11423 * AC On-die Termination Mode
11425 #undef DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL
11426 #undef DDR_PHY_ACIOCR0_ACODTMODE_SHIFT
11427 #undef DDR_PHY_ACIOCR0_ACODTMODE_MASK
11428 #define DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL 0x30000000
11429 #define DDR_PHY_ACIOCR0_ACODTMODE_SHIFT 2
11430 #define DDR_PHY_ACIOCR0_ACODTMODE_MASK 0x0000000CU
11433 * Reserved. Return zeroes on reads.
11435 #undef DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL
11436 #undef DDR_PHY_ACIOCR0_RESERVED_1_SHIFT
11437 #undef DDR_PHY_ACIOCR0_RESERVED_1_MASK
11438 #define DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL 0x30000000
11439 #define DDR_PHY_ACIOCR0_RESERVED_1_SHIFT 1
11440 #define DDR_PHY_ACIOCR0_RESERVED_1_MASK 0x00000002U
11443 * Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.
11445 #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL
11446 #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT
11447 #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK
11448 #define DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL 0x30000000
11449 #define DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT 0
11450 #define DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK 0x00000001U
11453 * Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL
11456 #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL
11457 #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT
11458 #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK
11459 #define DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL 0x00000000
11460 #define DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT 31
11461 #define DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK 0x80000000U
11464 * Clock gating for Output Enable D slices [0]
11466 #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL
11467 #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT
11468 #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK
11469 #define DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL 0x00000000
11470 #define DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT 30
11471 #define DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK 0x40000000U
11474 * Clock gating for Power Down Receiver D slices [0]
11476 #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL
11477 #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT
11478 #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK
11479 #define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL 0x00000000
11480 #define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT 29
11481 #define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK 0x20000000U
11484 * Clock gating for Termination Enable D slices [0]
11486 #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL
11487 #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT
11488 #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK
11489 #define DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL 0x00000000
11490 #define DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT 28
11491 #define DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK 0x10000000U
11494 * Clock gating for CK# D slices [1:0]
11496 #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL
11497 #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT
11498 #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK
11499 #define DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL 0x00000000
11500 #define DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT 26
11501 #define DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK 0x0C000000U
11504 * Clock gating for CK D slices [1:0]
11506 #undef DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL
11507 #undef DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT
11508 #undef DDR_PHY_ACIOCR2_CKCLKGATE0_MASK
11509 #define DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL 0x00000000
11510 #define DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT 24
11511 #define DDR_PHY_ACIOCR2_CKCLKGATE0_MASK 0x03000000U
11514 * Clock gating for AC D slices [23:0]
11516 #undef DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL
11517 #undef DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT
11518 #undef DDR_PHY_ACIOCR2_ACCLKGATE0_MASK
11519 #define DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL 0x00000000
11520 #define DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT 0
11521 #define DDR_PHY_ACIOCR2_ACCLKGATE0_MASK 0x00FFFFFFU
11524 * SDRAM Parity Output Enable (OE) Mode Selection
11526 #undef DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL
11527 #undef DDR_PHY_ACIOCR3_PAROEMODE_SHIFT
11528 #undef DDR_PHY_ACIOCR3_PAROEMODE_MASK
11529 #define DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL 0x00000005
11530 #define DDR_PHY_ACIOCR3_PAROEMODE_SHIFT 30
11531 #define DDR_PHY_ACIOCR3_PAROEMODE_MASK 0xC0000000U
11534 * SDRAM Bank Group Output Enable (OE) Mode Selection
11536 #undef DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL
11537 #undef DDR_PHY_ACIOCR3_BGOEMODE_SHIFT
11538 #undef DDR_PHY_ACIOCR3_BGOEMODE_MASK
11539 #define DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL 0x00000005
11540 #define DDR_PHY_ACIOCR3_BGOEMODE_SHIFT 26
11541 #define DDR_PHY_ACIOCR3_BGOEMODE_MASK 0x3C000000U
11544 * SDRAM Bank Address Output Enable (OE) Mode Selection
11546 #undef DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL
11547 #undef DDR_PHY_ACIOCR3_BAOEMODE_SHIFT
11548 #undef DDR_PHY_ACIOCR3_BAOEMODE_MASK
11549 #define DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL 0x00000005
11550 #define DDR_PHY_ACIOCR3_BAOEMODE_SHIFT 22
11551 #define DDR_PHY_ACIOCR3_BAOEMODE_MASK 0x03C00000U
11554 * SDRAM A[17] Output Enable (OE) Mode Selection
11556 #undef DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL
11557 #undef DDR_PHY_ACIOCR3_A17OEMODE_SHIFT
11558 #undef DDR_PHY_ACIOCR3_A17OEMODE_MASK
11559 #define DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL 0x00000005
11560 #define DDR_PHY_ACIOCR3_A17OEMODE_SHIFT 20
11561 #define DDR_PHY_ACIOCR3_A17OEMODE_MASK 0x00300000U
11564 * SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection
11566 #undef DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL
11567 #undef DDR_PHY_ACIOCR3_A16OEMODE_SHIFT
11568 #undef DDR_PHY_ACIOCR3_A16OEMODE_MASK
11569 #define DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL 0x00000005
11570 #define DDR_PHY_ACIOCR3_A16OEMODE_SHIFT 18
11571 #define DDR_PHY_ACIOCR3_A16OEMODE_MASK 0x000C0000U
11574 * SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)
11576 #undef DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL
11577 #undef DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT
11578 #undef DDR_PHY_ACIOCR3_ACTOEMODE_MASK
11579 #define DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL 0x00000005
11580 #define DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT 16
11581 #define DDR_PHY_ACIOCR3_ACTOEMODE_MASK 0x00030000U
11584 * Reserved. Return zeroes on reads.
11586 #undef DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL
11587 #undef DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT
11588 #undef DDR_PHY_ACIOCR3_RESERVED_15_8_MASK
11589 #define DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL 0x00000005
11590 #define DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT 8
11591 #define DDR_PHY_ACIOCR3_RESERVED_15_8_MASK 0x0000FF00U
11594 * Reserved. Return zeros on reads.
11596 #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL
11597 #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT
11598 #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK
11599 #define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL 0x00000005
11600 #define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT 4
11601 #define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK 0x000000F0U
11604 * SDRAM CK Output Enable (OE) Mode Selection.
11606 #undef DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL
11607 #undef DDR_PHY_ACIOCR3_CKOEMODE_SHIFT
11608 #undef DDR_PHY_ACIOCR3_CKOEMODE_MASK
11609 #define DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL 0x00000005
11610 #define DDR_PHY_ACIOCR3_CKOEMODE_SHIFT 0
11611 #define DDR_PHY_ACIOCR3_CKOEMODE_MASK 0x0000000FU
11614 * Clock gating for AC LB slices and loopback read valid slices
11616 #undef DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL
11617 #undef DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT
11618 #undef DDR_PHY_ACIOCR4_LBCLKGATE_MASK
11619 #define DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL 0x00000000
11620 #define DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT 31
11621 #define DDR_PHY_ACIOCR4_LBCLKGATE_MASK 0x80000000U
11624 * Clock gating for Output Enable D slices [1]
11626 #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL
11627 #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT
11628 #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK
11629 #define DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL 0x00000000
11630 #define DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT 30
11631 #define DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK 0x40000000U
11634 * Clock gating for Power Down Receiver D slices [1]
11636 #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL
11637 #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT
11638 #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK
11639 #define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL 0x00000000
11640 #define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT 29
11641 #define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK 0x20000000U
11644 * Clock gating for Termination Enable D slices [1]
11646 #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL
11647 #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT
11648 #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK
11649 #define DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL 0x00000000
11650 #define DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT 28
11651 #define DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK 0x10000000U
11654 * Clock gating for CK# D slices [3:2]
11656 #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL
11657 #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT
11658 #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK
11659 #define DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL 0x00000000
11660 #define DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT 26
11661 #define DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK 0x0C000000U
11664 * Clock gating for CK D slices [3:2]
11666 #undef DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL
11667 #undef DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT
11668 #undef DDR_PHY_ACIOCR4_CKCLKGATE1_MASK
11669 #define DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL 0x00000000
11670 #define DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT 24
11671 #define DDR_PHY_ACIOCR4_CKCLKGATE1_MASK 0x03000000U
11674 * Clock gating for AC D slices [47:24]
11676 #undef DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL
11677 #undef DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT
11678 #undef DDR_PHY_ACIOCR4_ACCLKGATE1_MASK
11679 #define DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL 0x00000000
11680 #define DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT 0
11681 #define DDR_PHY_ACIOCR4_ACCLKGATE1_MASK 0x00FFFFFFU
11684 * Reserved. Return zeroes on reads.
11686 #undef DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL
11687 #undef DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT
11688 #undef DDR_PHY_IOVCR0_RESERVED_31_29_MASK
11689 #define DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL 0x0F000000
11690 #define DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT 29
11691 #define DDR_PHY_IOVCR0_RESERVED_31_29_MASK 0xE0000000U
11694 * Address/command lane VREF Pad Enable
11696 #undef DDR_PHY_IOVCR0_ACREFPEN_DEFVAL
11697 #undef DDR_PHY_IOVCR0_ACREFPEN_SHIFT
11698 #undef DDR_PHY_IOVCR0_ACREFPEN_MASK
11699 #define DDR_PHY_IOVCR0_ACREFPEN_DEFVAL 0x0F000000
11700 #define DDR_PHY_IOVCR0_ACREFPEN_SHIFT 28
11701 #define DDR_PHY_IOVCR0_ACREFPEN_MASK 0x10000000U
11704 * Address/command lane Internal VREF Enable
11706 #undef DDR_PHY_IOVCR0_ACREFEEN_DEFVAL
11707 #undef DDR_PHY_IOVCR0_ACREFEEN_SHIFT
11708 #undef DDR_PHY_IOVCR0_ACREFEEN_MASK
11709 #define DDR_PHY_IOVCR0_ACREFEEN_DEFVAL 0x0F000000
11710 #define DDR_PHY_IOVCR0_ACREFEEN_SHIFT 26
11711 #define DDR_PHY_IOVCR0_ACREFEEN_MASK 0x0C000000U
11714 * Address/command lane Single-End VREF Enable
11716 #undef DDR_PHY_IOVCR0_ACREFSEN_DEFVAL
11717 #undef DDR_PHY_IOVCR0_ACREFSEN_SHIFT
11718 #undef DDR_PHY_IOVCR0_ACREFSEN_MASK
11719 #define DDR_PHY_IOVCR0_ACREFSEN_DEFVAL 0x0F000000
11720 #define DDR_PHY_IOVCR0_ACREFSEN_SHIFT 25
11721 #define DDR_PHY_IOVCR0_ACREFSEN_MASK 0x02000000U
11724 * Address/command lane Internal VREF Enable
11726 #undef DDR_PHY_IOVCR0_ACREFIEN_DEFVAL
11727 #undef DDR_PHY_IOVCR0_ACREFIEN_SHIFT
11728 #undef DDR_PHY_IOVCR0_ACREFIEN_MASK
11729 #define DDR_PHY_IOVCR0_ACREFIEN_DEFVAL 0x0F000000
11730 #define DDR_PHY_IOVCR0_ACREFIEN_SHIFT 24
11731 #define DDR_PHY_IOVCR0_ACREFIEN_MASK 0x01000000U
11734 * External VREF generato REFSEL range select
11736 #undef DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL
11737 #undef DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT
11738 #undef DDR_PHY_IOVCR0_ACREFESELRANGE_MASK
11739 #define DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL 0x0F000000
11740 #define DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT 23
11741 #define DDR_PHY_IOVCR0_ACREFESELRANGE_MASK 0x00800000U
11744 * Address/command lane External VREF Select
11746 #undef DDR_PHY_IOVCR0_ACREFESEL_DEFVAL
11747 #undef DDR_PHY_IOVCR0_ACREFESEL_SHIFT
11748 #undef DDR_PHY_IOVCR0_ACREFESEL_MASK
11749 #define DDR_PHY_IOVCR0_ACREFESEL_DEFVAL 0x0F000000
11750 #define DDR_PHY_IOVCR0_ACREFESEL_SHIFT 16
11751 #define DDR_PHY_IOVCR0_ACREFESEL_MASK 0x007F0000U
11754 * Single ended VREF generator REFSEL range select
11756 #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL
11757 #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT
11758 #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK
11759 #define DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL 0x0F000000
11760 #define DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT 15
11761 #define DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK 0x00008000U
11764 * Address/command lane Single-End VREF Select
11766 #undef DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL
11767 #undef DDR_PHY_IOVCR0_ACREFSSEL_SHIFT
11768 #undef DDR_PHY_IOVCR0_ACREFSSEL_MASK
11769 #define DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL 0x0F000000
11770 #define DDR_PHY_IOVCR0_ACREFSSEL_SHIFT 8
11771 #define DDR_PHY_IOVCR0_ACREFSSEL_MASK 0x00007F00U
11774 * Internal VREF generator REFSEL ragne select
11776 #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL
11777 #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT
11778 #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK
11779 #define DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL 0x0F000000
11780 #define DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT 7
11781 #define DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK 0x00000080U
11784 * REFSEL Control for internal AC IOs
11786 #undef DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL
11787 #undef DDR_PHY_IOVCR0_ACVREFISEL_SHIFT
11788 #undef DDR_PHY_IOVCR0_ACVREFISEL_MASK
11789 #define DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL 0x0F000000
11790 #define DDR_PHY_IOVCR0_ACVREFISEL_SHIFT 0
11791 #define DDR_PHY_IOVCR0_ACVREFISEL_MASK 0x0000007FU
11794 * Number of ctl_clk required to meet (> 150ns) timing requirements during
11795 * DRAM DQ VREF training
11797 #undef DDR_PHY_VTCR0_TVREF_DEFVAL
11798 #undef DDR_PHY_VTCR0_TVREF_SHIFT
11799 #undef DDR_PHY_VTCR0_TVREF_MASK
11800 #define DDR_PHY_VTCR0_TVREF_DEFVAL 0x70032019
11801 #define DDR_PHY_VTCR0_TVREF_SHIFT 29
11802 #define DDR_PHY_VTCR0_TVREF_MASK 0xE0000000U
11805 * DRM DQ VREF training Enable
11807 #undef DDR_PHY_VTCR0_DVEN_DEFVAL
11808 #undef DDR_PHY_VTCR0_DVEN_SHIFT
11809 #undef DDR_PHY_VTCR0_DVEN_MASK
11810 #define DDR_PHY_VTCR0_DVEN_DEFVAL 0x70032019
11811 #define DDR_PHY_VTCR0_DVEN_SHIFT 28
11812 #define DDR_PHY_VTCR0_DVEN_MASK 0x10000000U
11815 * Per Device Addressability Enable
11817 #undef DDR_PHY_VTCR0_PDAEN_DEFVAL
11818 #undef DDR_PHY_VTCR0_PDAEN_SHIFT
11819 #undef DDR_PHY_VTCR0_PDAEN_MASK
11820 #define DDR_PHY_VTCR0_PDAEN_DEFVAL 0x70032019
11821 #define DDR_PHY_VTCR0_PDAEN_SHIFT 27
11822 #define DDR_PHY_VTCR0_PDAEN_MASK 0x08000000U
11825 * Reserved. Returns zeroes on reads.
11827 #undef DDR_PHY_VTCR0_RESERVED_26_DEFVAL
11828 #undef DDR_PHY_VTCR0_RESERVED_26_SHIFT
11829 #undef DDR_PHY_VTCR0_RESERVED_26_MASK
11830 #define DDR_PHY_VTCR0_RESERVED_26_DEFVAL 0x70032019
11831 #define DDR_PHY_VTCR0_RESERVED_26_SHIFT 26
11832 #define DDR_PHY_VTCR0_RESERVED_26_MASK 0x04000000U
11837 #undef DDR_PHY_VTCR0_VWCR_DEFVAL
11838 #undef DDR_PHY_VTCR0_VWCR_SHIFT
11839 #undef DDR_PHY_VTCR0_VWCR_MASK
11840 #define DDR_PHY_VTCR0_VWCR_DEFVAL 0x70032019
11841 #define DDR_PHY_VTCR0_VWCR_SHIFT 22
11842 #define DDR_PHY_VTCR0_VWCR_MASK 0x03C00000U
11845 * DRAM DQ VREF step size used during DRAM VREF training
11847 #undef DDR_PHY_VTCR0_DVSS_DEFVAL
11848 #undef DDR_PHY_VTCR0_DVSS_SHIFT
11849 #undef DDR_PHY_VTCR0_DVSS_MASK
11850 #define DDR_PHY_VTCR0_DVSS_DEFVAL 0x70032019
11851 #define DDR_PHY_VTCR0_DVSS_SHIFT 18
11852 #define DDR_PHY_VTCR0_DVSS_MASK 0x003C0000U
11855 * Maximum VREF limit value used during DRAM VREF training
11857 #undef DDR_PHY_VTCR0_DVMAX_DEFVAL
11858 #undef DDR_PHY_VTCR0_DVMAX_SHIFT
11859 #undef DDR_PHY_VTCR0_DVMAX_MASK
11860 #define DDR_PHY_VTCR0_DVMAX_DEFVAL 0x70032019
11861 #define DDR_PHY_VTCR0_DVMAX_SHIFT 12
11862 #define DDR_PHY_VTCR0_DVMAX_MASK 0x0003F000U
11865 * Minimum VREF limit value used during DRAM VREF training
11867 #undef DDR_PHY_VTCR0_DVMIN_DEFVAL
11868 #undef DDR_PHY_VTCR0_DVMIN_SHIFT
11869 #undef DDR_PHY_VTCR0_DVMIN_MASK
11870 #define DDR_PHY_VTCR0_DVMIN_DEFVAL 0x70032019
11871 #define DDR_PHY_VTCR0_DVMIN_SHIFT 6
11872 #define DDR_PHY_VTCR0_DVMIN_MASK 0x00000FC0U
11875 * Initial DRAM DQ VREF value used during DRAM VREF training
11877 #undef DDR_PHY_VTCR0_DVINIT_DEFVAL
11878 #undef DDR_PHY_VTCR0_DVINIT_SHIFT
11879 #undef DDR_PHY_VTCR0_DVINIT_MASK
11880 #define DDR_PHY_VTCR0_DVINIT_DEFVAL 0x70032019
11881 #define DDR_PHY_VTCR0_DVINIT_SHIFT 0
11882 #define DDR_PHY_VTCR0_DVINIT_MASK 0x0000003FU
11885 * Host VREF step size used during VREF training. The register value of N i
11886 * ndicates step size of (N+1)
11888 #undef DDR_PHY_VTCR1_HVSS_DEFVAL
11889 #undef DDR_PHY_VTCR1_HVSS_SHIFT
11890 #undef DDR_PHY_VTCR1_HVSS_MASK
11891 #define DDR_PHY_VTCR1_HVSS_DEFVAL 0x07F00072
11892 #define DDR_PHY_VTCR1_HVSS_SHIFT 28
11893 #define DDR_PHY_VTCR1_HVSS_MASK 0xF0000000U
11896 * Reserved. Returns zeroes on reads.
11898 #undef DDR_PHY_VTCR1_RESERVED_27_DEFVAL
11899 #undef DDR_PHY_VTCR1_RESERVED_27_SHIFT
11900 #undef DDR_PHY_VTCR1_RESERVED_27_MASK
11901 #define DDR_PHY_VTCR1_RESERVED_27_DEFVAL 0x07F00072
11902 #define DDR_PHY_VTCR1_RESERVED_27_SHIFT 27
11903 #define DDR_PHY_VTCR1_RESERVED_27_MASK 0x08000000U
11906 * Maximum VREF limit value used during DRAM VREF training.
11908 #undef DDR_PHY_VTCR1_HVMAX_DEFVAL
11909 #undef DDR_PHY_VTCR1_HVMAX_SHIFT
11910 #undef DDR_PHY_VTCR1_HVMAX_MASK
11911 #define DDR_PHY_VTCR1_HVMAX_DEFVAL 0x07F00072
11912 #define DDR_PHY_VTCR1_HVMAX_SHIFT 20
11913 #define DDR_PHY_VTCR1_HVMAX_MASK 0x07F00000U
11916 * Reserved. Returns zeroes on reads.
11918 #undef DDR_PHY_VTCR1_RESERVED_19_DEFVAL
11919 #undef DDR_PHY_VTCR1_RESERVED_19_SHIFT
11920 #undef DDR_PHY_VTCR1_RESERVED_19_MASK
11921 #define DDR_PHY_VTCR1_RESERVED_19_DEFVAL 0x07F00072
11922 #define DDR_PHY_VTCR1_RESERVED_19_SHIFT 19
11923 #define DDR_PHY_VTCR1_RESERVED_19_MASK 0x00080000U
11926 * Minimum VREF limit value used during DRAM VREF training.
11928 #undef DDR_PHY_VTCR1_HVMIN_DEFVAL
11929 #undef DDR_PHY_VTCR1_HVMIN_SHIFT
11930 #undef DDR_PHY_VTCR1_HVMIN_MASK
11931 #define DDR_PHY_VTCR1_HVMIN_DEFVAL 0x07F00072
11932 #define DDR_PHY_VTCR1_HVMIN_SHIFT 12
11933 #define DDR_PHY_VTCR1_HVMIN_MASK 0x0007F000U
11936 * Reserved. Returns zeroes on reads.
11938 #undef DDR_PHY_VTCR1_RESERVED_11_DEFVAL
11939 #undef DDR_PHY_VTCR1_RESERVED_11_SHIFT
11940 #undef DDR_PHY_VTCR1_RESERVED_11_MASK
11941 #define DDR_PHY_VTCR1_RESERVED_11_DEFVAL 0x07F00072
11942 #define DDR_PHY_VTCR1_RESERVED_11_SHIFT 11
11943 #define DDR_PHY_VTCR1_RESERVED_11_MASK 0x00000800U
11946 * Static Host Vref Rank Value
11948 #undef DDR_PHY_VTCR1_SHRNK_DEFVAL
11949 #undef DDR_PHY_VTCR1_SHRNK_SHIFT
11950 #undef DDR_PHY_VTCR1_SHRNK_MASK
11951 #define DDR_PHY_VTCR1_SHRNK_DEFVAL 0x07F00072
11952 #define DDR_PHY_VTCR1_SHRNK_SHIFT 9
11953 #define DDR_PHY_VTCR1_SHRNK_MASK 0x00000600U
11956 * Static Host Vref Rank Enable
11958 #undef DDR_PHY_VTCR1_SHREN_DEFVAL
11959 #undef DDR_PHY_VTCR1_SHREN_SHIFT
11960 #undef DDR_PHY_VTCR1_SHREN_MASK
11961 #define DDR_PHY_VTCR1_SHREN_DEFVAL 0x07F00072
11962 #define DDR_PHY_VTCR1_SHREN_SHIFT 8
11963 #define DDR_PHY_VTCR1_SHREN_MASK 0x00000100U
11966 * Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir
11967 * ements during Host IO VREF training
11969 #undef DDR_PHY_VTCR1_TVREFIO_DEFVAL
11970 #undef DDR_PHY_VTCR1_TVREFIO_SHIFT
11971 #undef DDR_PHY_VTCR1_TVREFIO_MASK
11972 #define DDR_PHY_VTCR1_TVREFIO_DEFVAL 0x07F00072
11973 #define DDR_PHY_VTCR1_TVREFIO_SHIFT 5
11974 #define DDR_PHY_VTCR1_TVREFIO_MASK 0x000000E0U
11977 * Eye LCDL Offset value for VREF training
11979 #undef DDR_PHY_VTCR1_EOFF_DEFVAL
11980 #undef DDR_PHY_VTCR1_EOFF_SHIFT
11981 #undef DDR_PHY_VTCR1_EOFF_MASK
11982 #define DDR_PHY_VTCR1_EOFF_DEFVAL 0x07F00072
11983 #define DDR_PHY_VTCR1_EOFF_SHIFT 3
11984 #define DDR_PHY_VTCR1_EOFF_MASK 0x00000018U
11987 * Number of LCDL Eye points for which VREF training is repeated
11989 #undef DDR_PHY_VTCR1_ENUM_DEFVAL
11990 #undef DDR_PHY_VTCR1_ENUM_SHIFT
11991 #undef DDR_PHY_VTCR1_ENUM_MASK
11992 #define DDR_PHY_VTCR1_ENUM_DEFVAL 0x07F00072
11993 #define DDR_PHY_VTCR1_ENUM_SHIFT 2
11994 #define DDR_PHY_VTCR1_ENUM_MASK 0x00000004U
11997 * HOST (IO) internal VREF training Enable
11999 #undef DDR_PHY_VTCR1_HVEN_DEFVAL
12000 #undef DDR_PHY_VTCR1_HVEN_SHIFT
12001 #undef DDR_PHY_VTCR1_HVEN_MASK
12002 #define DDR_PHY_VTCR1_HVEN_DEFVAL 0x07F00072
12003 #define DDR_PHY_VTCR1_HVEN_SHIFT 1
12004 #define DDR_PHY_VTCR1_HVEN_MASK 0x00000002U
12007 * Host IO Type Control
12009 #undef DDR_PHY_VTCR1_HVIO_DEFVAL
12010 #undef DDR_PHY_VTCR1_HVIO_SHIFT
12011 #undef DDR_PHY_VTCR1_HVIO_MASK
12012 #define DDR_PHY_VTCR1_HVIO_DEFVAL 0x07F00072
12013 #define DDR_PHY_VTCR1_HVIO_SHIFT 0
12014 #define DDR_PHY_VTCR1_HVIO_MASK 0x00000001U
12017 * Reserved. Return zeroes on reads.
12019 #undef DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL
12020 #undef DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT
12021 #undef DDR_PHY_ACBDLR1_RESERVED_31_30_MASK
12022 #define DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL 0x00000000
12023 #define DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT 30
12024 #define DDR_PHY_ACBDLR1_RESERVED_31_30_MASK 0xC0000000U
12027 * Delay select for the BDL on Parity.
12029 #undef DDR_PHY_ACBDLR1_PARBD_DEFVAL
12030 #undef DDR_PHY_ACBDLR1_PARBD_SHIFT
12031 #undef DDR_PHY_ACBDLR1_PARBD_MASK
12032 #define DDR_PHY_ACBDLR1_PARBD_DEFVAL 0x00000000
12033 #define DDR_PHY_ACBDLR1_PARBD_SHIFT 24
12034 #define DDR_PHY_ACBDLR1_PARBD_MASK 0x3F000000U
12037 * Reserved. Return zeroes on reads.
12039 #undef DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL
12040 #undef DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT
12041 #undef DDR_PHY_ACBDLR1_RESERVED_23_22_MASK
12042 #define DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL 0x00000000
12043 #define DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT 22
12044 #define DDR_PHY_ACBDLR1_RESERVED_23_22_MASK 0x00C00000U
12047 * Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn
12050 #undef DDR_PHY_ACBDLR1_A16BD_DEFVAL
12051 #undef DDR_PHY_ACBDLR1_A16BD_SHIFT
12052 #undef DDR_PHY_ACBDLR1_A16BD_MASK
12053 #define DDR_PHY_ACBDLR1_A16BD_DEFVAL 0x00000000
12054 #define DDR_PHY_ACBDLR1_A16BD_SHIFT 16
12055 #define DDR_PHY_ACBDLR1_A16BD_MASK 0x003F0000U
12058 * Reserved. Return zeroes on reads.
12060 #undef DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL
12061 #undef DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT
12062 #undef DDR_PHY_ACBDLR1_RESERVED_15_14_MASK
12063 #define DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL 0x00000000
12064 #define DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT 14
12065 #define DDR_PHY_ACBDLR1_RESERVED_15_14_MASK 0x0000C000U
12068 * Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi
12069 * s pin is connected to CAS.
12071 #undef DDR_PHY_ACBDLR1_A17BD_DEFVAL
12072 #undef DDR_PHY_ACBDLR1_A17BD_SHIFT
12073 #undef DDR_PHY_ACBDLR1_A17BD_MASK
12074 #define DDR_PHY_ACBDLR1_A17BD_DEFVAL 0x00000000
12075 #define DDR_PHY_ACBDLR1_A17BD_SHIFT 8
12076 #define DDR_PHY_ACBDLR1_A17BD_MASK 0x00003F00U
12079 * Reserved. Return zeroes on reads.
12081 #undef DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL
12082 #undef DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT
12083 #undef DDR_PHY_ACBDLR1_RESERVED_7_6_MASK
12084 #define DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL 0x00000000
12085 #define DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT 6
12086 #define DDR_PHY_ACBDLR1_RESERVED_7_6_MASK 0x000000C0U
12089 * Delay select for the BDL on ACTN.
12091 #undef DDR_PHY_ACBDLR1_ACTBD_DEFVAL
12092 #undef DDR_PHY_ACBDLR1_ACTBD_SHIFT
12093 #undef DDR_PHY_ACBDLR1_ACTBD_MASK
12094 #define DDR_PHY_ACBDLR1_ACTBD_DEFVAL 0x00000000
12095 #define DDR_PHY_ACBDLR1_ACTBD_SHIFT 0
12096 #define DDR_PHY_ACBDLR1_ACTBD_MASK 0x0000003FU
12099 * Reserved. Return zeroes on reads.
12101 #undef DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL
12102 #undef DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT
12103 #undef DDR_PHY_ACBDLR2_RESERVED_31_30_MASK
12104 #define DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL 0x00000000
12105 #define DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT 30
12106 #define DDR_PHY_ACBDLR2_RESERVED_31_30_MASK 0xC0000000U
12109 * Delay select for the BDL on BG[1].
12111 #undef DDR_PHY_ACBDLR2_BG1BD_DEFVAL
12112 #undef DDR_PHY_ACBDLR2_BG1BD_SHIFT
12113 #undef DDR_PHY_ACBDLR2_BG1BD_MASK
12114 #define DDR_PHY_ACBDLR2_BG1BD_DEFVAL 0x00000000
12115 #define DDR_PHY_ACBDLR2_BG1BD_SHIFT 24
12116 #define DDR_PHY_ACBDLR2_BG1BD_MASK 0x3F000000U
12119 * Reserved. Return zeroes on reads.
12121 #undef DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL
12122 #undef DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT
12123 #undef DDR_PHY_ACBDLR2_RESERVED_23_22_MASK
12124 #define DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL 0x00000000
12125 #define DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT 22
12126 #define DDR_PHY_ACBDLR2_RESERVED_23_22_MASK 0x00C00000U
12129 * Delay select for the BDL on BG[0].
12131 #undef DDR_PHY_ACBDLR2_BG0BD_DEFVAL
12132 #undef DDR_PHY_ACBDLR2_BG0BD_SHIFT
12133 #undef DDR_PHY_ACBDLR2_BG0BD_MASK
12134 #define DDR_PHY_ACBDLR2_BG0BD_DEFVAL 0x00000000
12135 #define DDR_PHY_ACBDLR2_BG0BD_SHIFT 16
12136 #define DDR_PHY_ACBDLR2_BG0BD_MASK 0x003F0000U
12139 * Reser.ved Return zeroes on reads.
12141 #undef DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL
12142 #undef DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT
12143 #undef DDR_PHY_ACBDLR2_RESERVED_15_14_MASK
12144 #define DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL 0x00000000
12145 #define DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT 14
12146 #define DDR_PHY_ACBDLR2_RESERVED_15_14_MASK 0x0000C000U
12149 * Delay select for the BDL on BA[1].
12151 #undef DDR_PHY_ACBDLR2_BA1BD_DEFVAL
12152 #undef DDR_PHY_ACBDLR2_BA1BD_SHIFT
12153 #undef DDR_PHY_ACBDLR2_BA1BD_MASK
12154 #define DDR_PHY_ACBDLR2_BA1BD_DEFVAL 0x00000000
12155 #define DDR_PHY_ACBDLR2_BA1BD_SHIFT 8
12156 #define DDR_PHY_ACBDLR2_BA1BD_MASK 0x00003F00U
12159 * Reserved. Return zeroes on reads.
12161 #undef DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL
12162 #undef DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT
12163 #undef DDR_PHY_ACBDLR2_RESERVED_7_6_MASK
12164 #define DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL 0x00000000
12165 #define DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT 6
12166 #define DDR_PHY_ACBDLR2_RESERVED_7_6_MASK 0x000000C0U
12169 * Delay select for the BDL on BA[0].
12171 #undef DDR_PHY_ACBDLR2_BA0BD_DEFVAL
12172 #undef DDR_PHY_ACBDLR2_BA0BD_SHIFT
12173 #undef DDR_PHY_ACBDLR2_BA0BD_MASK
12174 #define DDR_PHY_ACBDLR2_BA0BD_DEFVAL 0x00000000
12175 #define DDR_PHY_ACBDLR2_BA0BD_SHIFT 0
12176 #define DDR_PHY_ACBDLR2_BA0BD_MASK 0x0000003FU
12179 * Reserved. Return zeroes on reads.
12181 #undef DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL
12182 #undef DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT
12183 #undef DDR_PHY_ACBDLR6_RESERVED_31_30_MASK
12184 #define DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL 0x00000000
12185 #define DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT 30
12186 #define DDR_PHY_ACBDLR6_RESERVED_31_30_MASK 0xC0000000U
12189 * Delay select for the BDL on Address A[3].
12191 #undef DDR_PHY_ACBDLR6_A03BD_DEFVAL
12192 #undef DDR_PHY_ACBDLR6_A03BD_SHIFT
12193 #undef DDR_PHY_ACBDLR6_A03BD_MASK
12194 #define DDR_PHY_ACBDLR6_A03BD_DEFVAL 0x00000000
12195 #define DDR_PHY_ACBDLR6_A03BD_SHIFT 24
12196 #define DDR_PHY_ACBDLR6_A03BD_MASK 0x3F000000U
12199 * Reserved. Return zeroes on reads.
12201 #undef DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL
12202 #undef DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT
12203 #undef DDR_PHY_ACBDLR6_RESERVED_23_22_MASK
12204 #define DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL 0x00000000
12205 #define DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT 22
12206 #define DDR_PHY_ACBDLR6_RESERVED_23_22_MASK 0x00C00000U
12209 * Delay select for the BDL on Address A[2].
12211 #undef DDR_PHY_ACBDLR6_A02BD_DEFVAL
12212 #undef DDR_PHY_ACBDLR6_A02BD_SHIFT
12213 #undef DDR_PHY_ACBDLR6_A02BD_MASK
12214 #define DDR_PHY_ACBDLR6_A02BD_DEFVAL 0x00000000
12215 #define DDR_PHY_ACBDLR6_A02BD_SHIFT 16
12216 #define DDR_PHY_ACBDLR6_A02BD_MASK 0x003F0000U
12219 * Reserved. Return zeroes on reads.
12221 #undef DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL
12222 #undef DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT
12223 #undef DDR_PHY_ACBDLR6_RESERVED_15_14_MASK
12224 #define DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL 0x00000000
12225 #define DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT 14
12226 #define DDR_PHY_ACBDLR6_RESERVED_15_14_MASK 0x0000C000U
12229 * Delay select for the BDL on Address A[1].
12231 #undef DDR_PHY_ACBDLR6_A01BD_DEFVAL
12232 #undef DDR_PHY_ACBDLR6_A01BD_SHIFT
12233 #undef DDR_PHY_ACBDLR6_A01BD_MASK
12234 #define DDR_PHY_ACBDLR6_A01BD_DEFVAL 0x00000000
12235 #define DDR_PHY_ACBDLR6_A01BD_SHIFT 8
12236 #define DDR_PHY_ACBDLR6_A01BD_MASK 0x00003F00U
12239 * Reserved. Return zeroes on reads.
12241 #undef DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL
12242 #undef DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT
12243 #undef DDR_PHY_ACBDLR6_RESERVED_7_6_MASK
12244 #define DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL 0x00000000
12245 #define DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT 6
12246 #define DDR_PHY_ACBDLR6_RESERVED_7_6_MASK 0x000000C0U
12249 * Delay select for the BDL on Address A[0].
12251 #undef DDR_PHY_ACBDLR6_A00BD_DEFVAL
12252 #undef DDR_PHY_ACBDLR6_A00BD_SHIFT
12253 #undef DDR_PHY_ACBDLR6_A00BD_MASK
12254 #define DDR_PHY_ACBDLR6_A00BD_DEFVAL 0x00000000
12255 #define DDR_PHY_ACBDLR6_A00BD_SHIFT 0
12256 #define DDR_PHY_ACBDLR6_A00BD_MASK 0x0000003FU
12259 * Reserved. Return zeroes on reads.
12261 #undef DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL
12262 #undef DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT
12263 #undef DDR_PHY_ACBDLR7_RESERVED_31_30_MASK
12264 #define DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL 0x00000000
12265 #define DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT 30
12266 #define DDR_PHY_ACBDLR7_RESERVED_31_30_MASK 0xC0000000U
12269 * Delay select for the BDL on Address A[7].
12271 #undef DDR_PHY_ACBDLR7_A07BD_DEFVAL
12272 #undef DDR_PHY_ACBDLR7_A07BD_SHIFT
12273 #undef DDR_PHY_ACBDLR7_A07BD_MASK
12274 #define DDR_PHY_ACBDLR7_A07BD_DEFVAL 0x00000000
12275 #define DDR_PHY_ACBDLR7_A07BD_SHIFT 24
12276 #define DDR_PHY_ACBDLR7_A07BD_MASK 0x3F000000U
12279 * Reserved. Return zeroes on reads.
12281 #undef DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL
12282 #undef DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT
12283 #undef DDR_PHY_ACBDLR7_RESERVED_23_22_MASK
12284 #define DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL 0x00000000
12285 #define DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT 22
12286 #define DDR_PHY_ACBDLR7_RESERVED_23_22_MASK 0x00C00000U
12289 * Delay select for the BDL on Address A[6].
12291 #undef DDR_PHY_ACBDLR7_A06BD_DEFVAL
12292 #undef DDR_PHY_ACBDLR7_A06BD_SHIFT
12293 #undef DDR_PHY_ACBDLR7_A06BD_MASK
12294 #define DDR_PHY_ACBDLR7_A06BD_DEFVAL 0x00000000
12295 #define DDR_PHY_ACBDLR7_A06BD_SHIFT 16
12296 #define DDR_PHY_ACBDLR7_A06BD_MASK 0x003F0000U
12299 * Reserved. Return zeroes on reads.
12301 #undef DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL
12302 #undef DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT
12303 #undef DDR_PHY_ACBDLR7_RESERVED_15_14_MASK
12304 #define DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL 0x00000000
12305 #define DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT 14
12306 #define DDR_PHY_ACBDLR7_RESERVED_15_14_MASK 0x0000C000U
12309 * Delay select for the BDL on Address A[5].
12311 #undef DDR_PHY_ACBDLR7_A05BD_DEFVAL
12312 #undef DDR_PHY_ACBDLR7_A05BD_SHIFT
12313 #undef DDR_PHY_ACBDLR7_A05BD_MASK
12314 #define DDR_PHY_ACBDLR7_A05BD_DEFVAL 0x00000000
12315 #define DDR_PHY_ACBDLR7_A05BD_SHIFT 8
12316 #define DDR_PHY_ACBDLR7_A05BD_MASK 0x00003F00U
12319 * Reserved. Return zeroes on reads.
12321 #undef DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL
12322 #undef DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT
12323 #undef DDR_PHY_ACBDLR7_RESERVED_7_6_MASK
12324 #define DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL 0x00000000
12325 #define DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT 6
12326 #define DDR_PHY_ACBDLR7_RESERVED_7_6_MASK 0x000000C0U
12329 * Delay select for the BDL on Address A[4].
12331 #undef DDR_PHY_ACBDLR7_A04BD_DEFVAL
12332 #undef DDR_PHY_ACBDLR7_A04BD_SHIFT
12333 #undef DDR_PHY_ACBDLR7_A04BD_MASK
12334 #define DDR_PHY_ACBDLR7_A04BD_DEFVAL 0x00000000
12335 #define DDR_PHY_ACBDLR7_A04BD_SHIFT 0
12336 #define DDR_PHY_ACBDLR7_A04BD_MASK 0x0000003FU
12339 * Reserved. Return zeroes on reads.
12341 #undef DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL
12342 #undef DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT
12343 #undef DDR_PHY_ACBDLR8_RESERVED_31_30_MASK
12344 #define DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL 0x00000000
12345 #define DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT 30
12346 #define DDR_PHY_ACBDLR8_RESERVED_31_30_MASK 0xC0000000U
12349 * Delay select for the BDL on Address A[11].
12351 #undef DDR_PHY_ACBDLR8_A11BD_DEFVAL
12352 #undef DDR_PHY_ACBDLR8_A11BD_SHIFT
12353 #undef DDR_PHY_ACBDLR8_A11BD_MASK
12354 #define DDR_PHY_ACBDLR8_A11BD_DEFVAL 0x00000000
12355 #define DDR_PHY_ACBDLR8_A11BD_SHIFT 24
12356 #define DDR_PHY_ACBDLR8_A11BD_MASK 0x3F000000U
12359 * Reserved. Return zeroes on reads.
12361 #undef DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL
12362 #undef DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT
12363 #undef DDR_PHY_ACBDLR8_RESERVED_23_22_MASK
12364 #define DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL 0x00000000
12365 #define DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT 22
12366 #define DDR_PHY_ACBDLR8_RESERVED_23_22_MASK 0x00C00000U
12369 * Delay select for the BDL on Address A[10].
12371 #undef DDR_PHY_ACBDLR8_A10BD_DEFVAL
12372 #undef DDR_PHY_ACBDLR8_A10BD_SHIFT
12373 #undef DDR_PHY_ACBDLR8_A10BD_MASK
12374 #define DDR_PHY_ACBDLR8_A10BD_DEFVAL 0x00000000
12375 #define DDR_PHY_ACBDLR8_A10BD_SHIFT 16
12376 #define DDR_PHY_ACBDLR8_A10BD_MASK 0x003F0000U
12379 * Reserved. Return zeroes on reads.
12381 #undef DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL
12382 #undef DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT
12383 #undef DDR_PHY_ACBDLR8_RESERVED_15_14_MASK
12384 #define DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL 0x00000000
12385 #define DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT 14
12386 #define DDR_PHY_ACBDLR8_RESERVED_15_14_MASK 0x0000C000U
12389 * Delay select for the BDL on Address A[9].
12391 #undef DDR_PHY_ACBDLR8_A09BD_DEFVAL
12392 #undef DDR_PHY_ACBDLR8_A09BD_SHIFT
12393 #undef DDR_PHY_ACBDLR8_A09BD_MASK
12394 #define DDR_PHY_ACBDLR8_A09BD_DEFVAL 0x00000000
12395 #define DDR_PHY_ACBDLR8_A09BD_SHIFT 8
12396 #define DDR_PHY_ACBDLR8_A09BD_MASK 0x00003F00U
12399 * Reserved. Return zeroes on reads.
12401 #undef DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL
12402 #undef DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT
12403 #undef DDR_PHY_ACBDLR8_RESERVED_7_6_MASK
12404 #define DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL 0x00000000
12405 #define DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT 6
12406 #define DDR_PHY_ACBDLR8_RESERVED_7_6_MASK 0x000000C0U
12409 * Delay select for the BDL on Address A[8].
12411 #undef DDR_PHY_ACBDLR8_A08BD_DEFVAL
12412 #undef DDR_PHY_ACBDLR8_A08BD_SHIFT
12413 #undef DDR_PHY_ACBDLR8_A08BD_MASK
12414 #define DDR_PHY_ACBDLR8_A08BD_DEFVAL 0x00000000
12415 #define DDR_PHY_ACBDLR8_A08BD_SHIFT 0
12416 #define DDR_PHY_ACBDLR8_A08BD_MASK 0x0000003FU
12419 * Reserved. Return zeroes on reads.
12421 #undef DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL
12422 #undef DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT
12423 #undef DDR_PHY_ACBDLR9_RESERVED_31_30_MASK
12424 #define DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL 0x00000000
12425 #define DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT 30
12426 #define DDR_PHY_ACBDLR9_RESERVED_31_30_MASK 0xC0000000U
12429 * Delay select for the BDL on Address A[15].
12431 #undef DDR_PHY_ACBDLR9_A15BD_DEFVAL
12432 #undef DDR_PHY_ACBDLR9_A15BD_SHIFT
12433 #undef DDR_PHY_ACBDLR9_A15BD_MASK
12434 #define DDR_PHY_ACBDLR9_A15BD_DEFVAL 0x00000000
12435 #define DDR_PHY_ACBDLR9_A15BD_SHIFT 24
12436 #define DDR_PHY_ACBDLR9_A15BD_MASK 0x3F000000U
12439 * Reserved. Return zeroes on reads.
12441 #undef DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL
12442 #undef DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT
12443 #undef DDR_PHY_ACBDLR9_RESERVED_23_22_MASK
12444 #define DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL 0x00000000
12445 #define DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT 22
12446 #define DDR_PHY_ACBDLR9_RESERVED_23_22_MASK 0x00C00000U
12449 * Delay select for the BDL on Address A[14].
12451 #undef DDR_PHY_ACBDLR9_A14BD_DEFVAL
12452 #undef DDR_PHY_ACBDLR9_A14BD_SHIFT
12453 #undef DDR_PHY_ACBDLR9_A14BD_MASK
12454 #define DDR_PHY_ACBDLR9_A14BD_DEFVAL 0x00000000
12455 #define DDR_PHY_ACBDLR9_A14BD_SHIFT 16
12456 #define DDR_PHY_ACBDLR9_A14BD_MASK 0x003F0000U
12459 * Reserved. Return zeroes on reads.
12461 #undef DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL
12462 #undef DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT
12463 #undef DDR_PHY_ACBDLR9_RESERVED_15_14_MASK
12464 #define DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL 0x00000000
12465 #define DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT 14
12466 #define DDR_PHY_ACBDLR9_RESERVED_15_14_MASK 0x0000C000U
12469 * Delay select for the BDL on Address A[13].
12471 #undef DDR_PHY_ACBDLR9_A13BD_DEFVAL
12472 #undef DDR_PHY_ACBDLR9_A13BD_SHIFT
12473 #undef DDR_PHY_ACBDLR9_A13BD_MASK
12474 #define DDR_PHY_ACBDLR9_A13BD_DEFVAL 0x00000000
12475 #define DDR_PHY_ACBDLR9_A13BD_SHIFT 8
12476 #define DDR_PHY_ACBDLR9_A13BD_MASK 0x00003F00U
12479 * Reserved. Return zeroes on reads.
12481 #undef DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL
12482 #undef DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT
12483 #undef DDR_PHY_ACBDLR9_RESERVED_7_6_MASK
12484 #define DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL 0x00000000
12485 #define DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT 6
12486 #define DDR_PHY_ACBDLR9_RESERVED_7_6_MASK 0x000000C0U
12489 * Delay select for the BDL on Address A[12].
12491 #undef DDR_PHY_ACBDLR9_A12BD_DEFVAL
12492 #undef DDR_PHY_ACBDLR9_A12BD_SHIFT
12493 #undef DDR_PHY_ACBDLR9_A12BD_MASK
12494 #define DDR_PHY_ACBDLR9_A12BD_DEFVAL 0x00000000
12495 #define DDR_PHY_ACBDLR9_A12BD_SHIFT 0
12496 #define DDR_PHY_ACBDLR9_A12BD_MASK 0x0000003FU
12499 * Reserved. Return zeroes on reads.
12501 #undef DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL
12502 #undef DDR_PHY_ZQCR_RESERVED_31_26_SHIFT
12503 #undef DDR_PHY_ZQCR_RESERVED_31_26_MASK
12504 #define DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL 0x008A2858
12505 #define DDR_PHY_ZQCR_RESERVED_31_26_SHIFT 26
12506 #define DDR_PHY_ZQCR_RESERVED_31_26_MASK 0xFC000000U
12511 #undef DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL
12512 #undef DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT
12513 #undef DDR_PHY_ZQCR_ZQREFISELRANGE_MASK
12514 #define DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL 0x008A2858
12515 #define DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT 25
12516 #define DDR_PHY_ZQCR_ZQREFISELRANGE_MASK 0x02000000U
12519 * Programmable Wait for Frequency B
12521 #undef DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL
12522 #undef DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT
12523 #undef DDR_PHY_ZQCR_PGWAIT_FRQB_MASK
12524 #define DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL 0x008A2858
12525 #define DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT 19
12526 #define DDR_PHY_ZQCR_PGWAIT_FRQB_MASK 0x01F80000U
12529 * Programmable Wait for Frequency A
12531 #undef DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL
12532 #undef DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT
12533 #undef DDR_PHY_ZQCR_PGWAIT_FRQA_MASK
12534 #define DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL 0x008A2858
12535 #define DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT 13
12536 #define DDR_PHY_ZQCR_PGWAIT_FRQA_MASK 0x0007E000U
12539 * ZQ VREF Pad Enable
12541 #undef DDR_PHY_ZQCR_ZQREFPEN_DEFVAL
12542 #undef DDR_PHY_ZQCR_ZQREFPEN_SHIFT
12543 #undef DDR_PHY_ZQCR_ZQREFPEN_MASK
12544 #define DDR_PHY_ZQCR_ZQREFPEN_DEFVAL 0x008A2858
12545 #define DDR_PHY_ZQCR_ZQREFPEN_SHIFT 12
12546 #define DDR_PHY_ZQCR_ZQREFPEN_MASK 0x00001000U
12549 * ZQ Internal VREF Enable
12551 #undef DDR_PHY_ZQCR_ZQREFIEN_DEFVAL
12552 #undef DDR_PHY_ZQCR_ZQREFIEN_SHIFT
12553 #undef DDR_PHY_ZQCR_ZQREFIEN_MASK
12554 #define DDR_PHY_ZQCR_ZQREFIEN_DEFVAL 0x008A2858
12555 #define DDR_PHY_ZQCR_ZQREFIEN_SHIFT 11
12556 #define DDR_PHY_ZQCR_ZQREFIEN_MASK 0x00000800U
12559 * Choice of termination mode
12561 #undef DDR_PHY_ZQCR_ODT_MODE_DEFVAL
12562 #undef DDR_PHY_ZQCR_ODT_MODE_SHIFT
12563 #undef DDR_PHY_ZQCR_ODT_MODE_MASK
12564 #define DDR_PHY_ZQCR_ODT_MODE_DEFVAL 0x008A2858
12565 #define DDR_PHY_ZQCR_ODT_MODE_SHIFT 9
12566 #define DDR_PHY_ZQCR_ODT_MODE_MASK 0x00000600U
12569 * Force ZCAL VT update
12571 #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL
12572 #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT
12573 #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK
12574 #define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL 0x008A2858
12575 #define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT 8
12576 #define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK 0x00000100U
12579 * IO VT Drift Limit
12581 #undef DDR_PHY_ZQCR_IODLMT_DEFVAL
12582 #undef DDR_PHY_ZQCR_IODLMT_SHIFT
12583 #undef DDR_PHY_ZQCR_IODLMT_MASK
12584 #define DDR_PHY_ZQCR_IODLMT_DEFVAL 0x008A2858
12585 #define DDR_PHY_ZQCR_IODLMT_SHIFT 5
12586 #define DDR_PHY_ZQCR_IODLMT_MASK 0x000000E0U
12589 * Averaging algorithm enable, if set, enables averaging algorithm
12591 #undef DDR_PHY_ZQCR_AVGEN_DEFVAL
12592 #undef DDR_PHY_ZQCR_AVGEN_SHIFT
12593 #undef DDR_PHY_ZQCR_AVGEN_MASK
12594 #define DDR_PHY_ZQCR_AVGEN_DEFVAL 0x008A2858
12595 #define DDR_PHY_ZQCR_AVGEN_SHIFT 4
12596 #define DDR_PHY_ZQCR_AVGEN_MASK 0x00000010U
12599 * Maximum number of averaging rounds to be used by averaging algorithm
12601 #undef DDR_PHY_ZQCR_AVGMAX_DEFVAL
12602 #undef DDR_PHY_ZQCR_AVGMAX_SHIFT
12603 #undef DDR_PHY_ZQCR_AVGMAX_MASK
12604 #define DDR_PHY_ZQCR_AVGMAX_DEFVAL 0x008A2858
12605 #define DDR_PHY_ZQCR_AVGMAX_SHIFT 2
12606 #define DDR_PHY_ZQCR_AVGMAX_MASK 0x0000000CU
12609 * ZQ Calibration Type
12611 #undef DDR_PHY_ZQCR_ZCALT_DEFVAL
12612 #undef DDR_PHY_ZQCR_ZCALT_SHIFT
12613 #undef DDR_PHY_ZQCR_ZCALT_MASK
12614 #define DDR_PHY_ZQCR_ZCALT_DEFVAL 0x008A2858
12615 #define DDR_PHY_ZQCR_ZCALT_SHIFT 1
12616 #define DDR_PHY_ZQCR_ZCALT_MASK 0x00000002U
12621 #undef DDR_PHY_ZQCR_ZQPD_DEFVAL
12622 #undef DDR_PHY_ZQCR_ZQPD_SHIFT
12623 #undef DDR_PHY_ZQCR_ZQPD_MASK
12624 #define DDR_PHY_ZQCR_ZQPD_DEFVAL 0x008A2858
12625 #define DDR_PHY_ZQCR_ZQPD_SHIFT 0
12626 #define DDR_PHY_ZQCR_ZQPD_MASK 0x00000001U
12629 * Pull-down drive strength ZCTRL over-ride enable
12631 #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL
12632 #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT
12633 #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK
12634 #define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB
12635 #define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT 31
12636 #define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK 0x80000000U
12639 * Pull-up drive strength ZCTRL over-ride enable
12641 #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL
12642 #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT
12643 #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK
12644 #define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB
12645 #define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT 30
12646 #define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK 0x40000000U
12649 * Pull-down termination ZCTRL over-ride enable
12651 #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL
12652 #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT
12653 #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK
12654 #define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB
12655 #define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT 29
12656 #define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK 0x20000000U
12659 * Pull-up termination ZCTRL over-ride enable
12661 #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL
12662 #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT
12663 #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK
12664 #define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB
12665 #define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT 28
12666 #define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK 0x10000000U
12669 * Calibration segment bypass
12671 #undef DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL
12672 #undef DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT
12673 #undef DDR_PHY_ZQ0PR0_ZSEGBYP_MASK
12674 #define DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL 0x000077BB
12675 #define DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT 27
12676 #define DDR_PHY_ZQ0PR0_ZSEGBYP_MASK 0x08000000U
12679 * VREF latch mode controls the mode in which the ZLE pin of the PVREF cell
12680 * is driven by the PUB
12682 #undef DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL
12683 #undef DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT
12684 #undef DDR_PHY_ZQ0PR0_ZLE_MODE_MASK
12685 #define DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL 0x000077BB
12686 #define DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT 25
12687 #define DDR_PHY_ZQ0PR0_ZLE_MODE_MASK 0x06000000U
12690 * Termination adjustment
12692 #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL
12693 #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT
12694 #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK
12695 #define DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL 0x000077BB
12696 #define DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT 22
12697 #define DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK 0x01C00000U
12700 * Pulldown drive strength adjustment
12702 #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL
12703 #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT
12704 #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK
12705 #define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB
12706 #define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT 19
12707 #define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK 0x00380000U
12710 * Pullup drive strength adjustment
12712 #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL
12713 #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT
12714 #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK
12715 #define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB
12716 #define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT 16
12717 #define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK 0x00070000U
12720 * DRAM Impedance Divide Ratio
12722 #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL
12723 #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT
12724 #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK
12725 #define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB
12726 #define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT 12
12727 #define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U
12730 * HOST Impedance Divide Ratio
12732 #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL
12733 #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT
12734 #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK
12735 #define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB
12736 #define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT 8
12737 #define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK 0x00000F00U
12740 * Impedance Divide Ratio (pulldown drive calibration during asymmetric dri
12741 * ve strength calibration)
12743 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL
12744 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT
12745 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK
12746 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB
12747 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT 4
12748 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U
12751 * Impedance Divide Ratio (pullup drive calibration during asymmetric drive
12752 * strength calibration)
12754 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL
12755 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT
12756 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK
12757 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB
12758 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT 0
12759 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU
12762 * Reserved. Return zeros on reads.
12764 #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL
12765 #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT
12766 #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK
12767 #define DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL 0x00000000
12768 #define DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT 26
12769 #define DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK 0xFC000000U
12772 * Override value for the pull-up output impedance
12774 #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL
12775 #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT
12776 #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK
12777 #define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL 0x00000000
12778 #define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT 16
12779 #define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK 0x03FF0000U
12782 * Reserved. Return zeros on reads.
12784 #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL
12785 #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT
12786 #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK
12787 #define DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL 0x00000000
12788 #define DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT 10
12789 #define DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK 0x0000FC00U
12792 * Override value for the pull-down output impedance
12794 #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL
12795 #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT
12796 #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK
12797 #define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL 0x00000000
12798 #define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT 0
12799 #define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK 0x000003FFU
12802 * Reserved. Return zeros on reads.
12804 #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL
12805 #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT
12806 #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK
12807 #define DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL 0x00000000
12808 #define DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT 26
12809 #define DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK 0xFC000000U
12812 * Override value for the pull-up termination
12814 #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL
12815 #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT
12816 #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK
12817 #define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL 0x00000000
12818 #define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT 16
12819 #define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK 0x03FF0000U
12822 * Reserved. Return zeros on reads.
12824 #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL
12825 #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT
12826 #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK
12827 #define DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL 0x00000000
12828 #define DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT 10
12829 #define DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK 0x0000FC00U
12832 * Override value for the pull-down termination
12834 #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL
12835 #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT
12836 #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK
12837 #define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL 0x00000000
12838 #define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT 0
12839 #define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK 0x000003FFU
12842 * Pull-down drive strength ZCTRL over-ride enable
12844 #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL
12845 #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT
12846 #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK
12847 #define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB
12848 #define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT 31
12849 #define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK 0x80000000U
12852 * Pull-up drive strength ZCTRL over-ride enable
12854 #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL
12855 #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT
12856 #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK
12857 #define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB
12858 #define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT 30
12859 #define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK 0x40000000U
12862 * Pull-down termination ZCTRL over-ride enable
12864 #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL
12865 #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT
12866 #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK
12867 #define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB
12868 #define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT 29
12869 #define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK 0x20000000U
12872 * Pull-up termination ZCTRL over-ride enable
12874 #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL
12875 #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT
12876 #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK
12877 #define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB
12878 #define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT 28
12879 #define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK 0x10000000U
12882 * Calibration segment bypass
12884 #undef DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL
12885 #undef DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT
12886 #undef DDR_PHY_ZQ1PR0_ZSEGBYP_MASK
12887 #define DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL 0x000077BB
12888 #define DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT 27
12889 #define DDR_PHY_ZQ1PR0_ZSEGBYP_MASK 0x08000000U
12892 * VREF latch mode controls the mode in which the ZLE pin of the PVREF cell
12893 * is driven by the PUB
12895 #undef DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL
12896 #undef DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT
12897 #undef DDR_PHY_ZQ1PR0_ZLE_MODE_MASK
12898 #define DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL 0x000077BB
12899 #define DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT 25
12900 #define DDR_PHY_ZQ1PR0_ZLE_MODE_MASK 0x06000000U
12903 * Termination adjustment
12905 #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL
12906 #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT
12907 #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK
12908 #define DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL 0x000077BB
12909 #define DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT 22
12910 #define DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK 0x01C00000U
12913 * Pulldown drive strength adjustment
12915 #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL
12916 #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT
12917 #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK
12918 #define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB
12919 #define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT 19
12920 #define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK 0x00380000U
12923 * Pullup drive strength adjustment
12925 #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL
12926 #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT
12927 #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK
12928 #define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB
12929 #define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT 16
12930 #define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK 0x00070000U
12933 * DRAM Impedance Divide Ratio
12935 #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL
12936 #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT
12937 #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK
12938 #define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB
12939 #define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT 12
12940 #define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U
12943 * HOST Impedance Divide Ratio
12945 #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL
12946 #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT
12947 #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK
12948 #define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB
12949 #define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT 8
12950 #define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK 0x00000F00U
12953 * Impedance Divide Ratio (pulldown drive calibration during asymmetric dri
12954 * ve strength calibration)
12956 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL
12957 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT
12958 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK
12959 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB
12960 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT 4
12961 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U
12964 * Impedance Divide Ratio (pullup drive calibration during asymmetric drive
12965 * strength calibration)
12967 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL
12968 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT
12969 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK
12970 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB
12971 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT 0
12972 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU
12975 * Calibration Bypass
12977 #undef DDR_PHY_DX0GCR0_CALBYP_DEFVAL
12978 #undef DDR_PHY_DX0GCR0_CALBYP_SHIFT
12979 #undef DDR_PHY_DX0GCR0_CALBYP_MASK
12980 #define DDR_PHY_DX0GCR0_CALBYP_DEFVAL 0x40200204
12981 #define DDR_PHY_DX0GCR0_CALBYP_SHIFT 31
12982 #define DDR_PHY_DX0GCR0_CALBYP_MASK 0x80000000U
12985 * Master Delay Line Enable
12987 #undef DDR_PHY_DX0GCR0_MDLEN_DEFVAL
12988 #undef DDR_PHY_DX0GCR0_MDLEN_SHIFT
12989 #undef DDR_PHY_DX0GCR0_MDLEN_MASK
12990 #define DDR_PHY_DX0GCR0_MDLEN_DEFVAL 0x40200204
12991 #define DDR_PHY_DX0GCR0_MDLEN_SHIFT 30
12992 #define DDR_PHY_DX0GCR0_MDLEN_MASK 0x40000000U
12995 * Configurable ODT(TE) Phase Shift
12997 #undef DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL
12998 #undef DDR_PHY_DX0GCR0_CODTSHFT_SHIFT
12999 #undef DDR_PHY_DX0GCR0_CODTSHFT_MASK
13000 #define DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL 0x40200204
13001 #define DDR_PHY_DX0GCR0_CODTSHFT_SHIFT 28
13002 #define DDR_PHY_DX0GCR0_CODTSHFT_MASK 0x30000000U
13005 * DQS Duty Cycle Correction
13007 #undef DDR_PHY_DX0GCR0_DQSDCC_DEFVAL
13008 #undef DDR_PHY_DX0GCR0_DQSDCC_SHIFT
13009 #undef DDR_PHY_DX0GCR0_DQSDCC_MASK
13010 #define DDR_PHY_DX0GCR0_DQSDCC_DEFVAL 0x40200204
13011 #define DDR_PHY_DX0GCR0_DQSDCC_SHIFT 24
13012 #define DDR_PHY_DX0GCR0_DQSDCC_MASK 0x0F000000U
13015 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
13016 * input for the respective bypte lane of the PHY
13018 #undef DDR_PHY_DX0GCR0_RDDLY_DEFVAL
13019 #undef DDR_PHY_DX0GCR0_RDDLY_SHIFT
13020 #undef DDR_PHY_DX0GCR0_RDDLY_MASK
13021 #define DDR_PHY_DX0GCR0_RDDLY_DEFVAL 0x40200204
13022 #define DDR_PHY_DX0GCR0_RDDLY_SHIFT 20
13023 #define DDR_PHY_DX0GCR0_RDDLY_MASK 0x00F00000U
13026 * Reserved. Return zeroes on reads.
13028 #undef DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL
13029 #undef DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT
13030 #undef DDR_PHY_DX0GCR0_RESERVED_19_14_MASK
13031 #define DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL 0x40200204
13032 #define DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT 14
13033 #define DDR_PHY_DX0GCR0_RESERVED_19_14_MASK 0x000FC000U
13036 * DQSNSE Power Down Receiver
13038 #undef DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL
13039 #undef DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT
13040 #undef DDR_PHY_DX0GCR0_DQSNSEPDR_MASK
13041 #define DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL 0x40200204
13042 #define DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT 13
13043 #define DDR_PHY_DX0GCR0_DQSNSEPDR_MASK 0x00002000U
13046 * DQSSE Power Down Receiver
13048 #undef DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL
13049 #undef DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT
13050 #undef DDR_PHY_DX0GCR0_DQSSEPDR_MASK
13051 #define DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL 0x40200204
13052 #define DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT 12
13053 #define DDR_PHY_DX0GCR0_DQSSEPDR_MASK 0x00001000U
13056 * RTT On Additive Latency
13058 #undef DDR_PHY_DX0GCR0_RTTOAL_DEFVAL
13059 #undef DDR_PHY_DX0GCR0_RTTOAL_SHIFT
13060 #undef DDR_PHY_DX0GCR0_RTTOAL_MASK
13061 #define DDR_PHY_DX0GCR0_RTTOAL_DEFVAL 0x40200204
13062 #define DDR_PHY_DX0GCR0_RTTOAL_SHIFT 11
13063 #define DDR_PHY_DX0GCR0_RTTOAL_MASK 0x00000800U
13068 #undef DDR_PHY_DX0GCR0_RTTOH_DEFVAL
13069 #undef DDR_PHY_DX0GCR0_RTTOH_SHIFT
13070 #undef DDR_PHY_DX0GCR0_RTTOH_MASK
13071 #define DDR_PHY_DX0GCR0_RTTOH_DEFVAL 0x40200204
13072 #define DDR_PHY_DX0GCR0_RTTOH_SHIFT 9
13073 #define DDR_PHY_DX0GCR0_RTTOH_MASK 0x00000600U
13076 * Configurable PDR Phase Shift
13078 #undef DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL
13079 #undef DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT
13080 #undef DDR_PHY_DX0GCR0_CPDRSHFT_MASK
13081 #define DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL 0x40200204
13082 #define DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT 7
13083 #define DDR_PHY_DX0GCR0_CPDRSHFT_MASK 0x00000180U
13088 #undef DDR_PHY_DX0GCR0_DQSRPD_DEFVAL
13089 #undef DDR_PHY_DX0GCR0_DQSRPD_SHIFT
13090 #undef DDR_PHY_DX0GCR0_DQSRPD_MASK
13091 #define DDR_PHY_DX0GCR0_DQSRPD_DEFVAL 0x40200204
13092 #define DDR_PHY_DX0GCR0_DQSRPD_SHIFT 6
13093 #define DDR_PHY_DX0GCR0_DQSRPD_MASK 0x00000040U
13096 * DQSG Power Down Receiver
13098 #undef DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL
13099 #undef DDR_PHY_DX0GCR0_DQSGPDR_SHIFT
13100 #undef DDR_PHY_DX0GCR0_DQSGPDR_MASK
13101 #define DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL 0x40200204
13102 #define DDR_PHY_DX0GCR0_DQSGPDR_SHIFT 5
13103 #define DDR_PHY_DX0GCR0_DQSGPDR_MASK 0x00000020U
13106 * Reserved. Return zeroes on reads.
13108 #undef DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL
13109 #undef DDR_PHY_DX0GCR0_RESERVED_4_SHIFT
13110 #undef DDR_PHY_DX0GCR0_RESERVED_4_MASK
13111 #define DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL 0x40200204
13112 #define DDR_PHY_DX0GCR0_RESERVED_4_SHIFT 4
13113 #define DDR_PHY_DX0GCR0_RESERVED_4_MASK 0x00000010U
13116 * DQSG On-Die Termination
13118 #undef DDR_PHY_DX0GCR0_DQSGODT_DEFVAL
13119 #undef DDR_PHY_DX0GCR0_DQSGODT_SHIFT
13120 #undef DDR_PHY_DX0GCR0_DQSGODT_MASK
13121 #define DDR_PHY_DX0GCR0_DQSGODT_DEFVAL 0x40200204
13122 #define DDR_PHY_DX0GCR0_DQSGODT_SHIFT 3
13123 #define DDR_PHY_DX0GCR0_DQSGODT_MASK 0x00000008U
13126 * DQSG Output Enable
13128 #undef DDR_PHY_DX0GCR0_DQSGOE_DEFVAL
13129 #undef DDR_PHY_DX0GCR0_DQSGOE_SHIFT
13130 #undef DDR_PHY_DX0GCR0_DQSGOE_MASK
13131 #define DDR_PHY_DX0GCR0_DQSGOE_DEFVAL 0x40200204
13132 #define DDR_PHY_DX0GCR0_DQSGOE_SHIFT 2
13133 #define DDR_PHY_DX0GCR0_DQSGOE_MASK 0x00000004U
13136 * Reserved. Return zeroes on reads.
13138 #undef DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL
13139 #undef DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT
13140 #undef DDR_PHY_DX0GCR0_RESERVED_1_0_MASK
13141 #define DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL 0x40200204
13142 #define DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT 0
13143 #define DDR_PHY_DX0GCR0_RESERVED_1_0_MASK 0x00000003U
13146 * Byte lane VREF IOM (Used only by D4MU IOs)
13148 #undef DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL
13149 #undef DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT
13150 #undef DDR_PHY_DX0GCR4_RESERVED_31_29_MASK
13151 #define DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL 0x0E00003C
13152 #define DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT 29
13153 #define DDR_PHY_DX0GCR4_RESERVED_31_29_MASK 0xE0000000U
13156 * Byte Lane VREF Pad Enable
13158 #undef DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL
13159 #undef DDR_PHY_DX0GCR4_DXREFPEN_SHIFT
13160 #undef DDR_PHY_DX0GCR4_DXREFPEN_MASK
13161 #define DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL 0x0E00003C
13162 #define DDR_PHY_DX0GCR4_DXREFPEN_SHIFT 28
13163 #define DDR_PHY_DX0GCR4_DXREFPEN_MASK 0x10000000U
13166 * Byte Lane Internal VREF Enable
13168 #undef DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL
13169 #undef DDR_PHY_DX0GCR4_DXREFEEN_SHIFT
13170 #undef DDR_PHY_DX0GCR4_DXREFEEN_MASK
13171 #define DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL 0x0E00003C
13172 #define DDR_PHY_DX0GCR4_DXREFEEN_SHIFT 26
13173 #define DDR_PHY_DX0GCR4_DXREFEEN_MASK 0x0C000000U
13176 * Byte Lane Single-End VREF Enable
13178 #undef DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL
13179 #undef DDR_PHY_DX0GCR4_DXREFSEN_SHIFT
13180 #undef DDR_PHY_DX0GCR4_DXREFSEN_MASK
13181 #define DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL 0x0E00003C
13182 #define DDR_PHY_DX0GCR4_DXREFSEN_SHIFT 25
13183 #define DDR_PHY_DX0GCR4_DXREFSEN_MASK 0x02000000U
13186 * Reserved. Returns zeros on reads.
13188 #undef DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL
13189 #undef DDR_PHY_DX0GCR4_RESERVED_24_SHIFT
13190 #undef DDR_PHY_DX0GCR4_RESERVED_24_MASK
13191 #define DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL 0x0E00003C
13192 #define DDR_PHY_DX0GCR4_RESERVED_24_SHIFT 24
13193 #define DDR_PHY_DX0GCR4_RESERVED_24_MASK 0x01000000U
13196 * External VREF generator REFSEL range select
13198 #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL
13199 #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT
13200 #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK
13201 #define DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C
13202 #define DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT 23
13203 #define DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK 0x00800000U
13206 * Byte Lane External VREF Select
13208 #undef DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL
13209 #undef DDR_PHY_DX0GCR4_DXREFESEL_SHIFT
13210 #undef DDR_PHY_DX0GCR4_DXREFESEL_MASK
13211 #define DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL 0x0E00003C
13212 #define DDR_PHY_DX0GCR4_DXREFESEL_SHIFT 16
13213 #define DDR_PHY_DX0GCR4_DXREFESEL_MASK 0x007F0000U
13216 * Single ended VREF generator REFSEL range select
13218 #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL
13219 #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT
13220 #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK
13221 #define DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C
13222 #define DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT 15
13223 #define DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK 0x00008000U
13226 * Byte Lane Single-End VREF Select
13228 #undef DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL
13229 #undef DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT
13230 #undef DDR_PHY_DX0GCR4_DXREFSSEL_MASK
13231 #define DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL 0x0E00003C
13232 #define DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT 8
13233 #define DDR_PHY_DX0GCR4_DXREFSSEL_MASK 0x00007F00U
13236 * Reserved. Returns zeros on reads.
13238 #undef DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL
13239 #undef DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT
13240 #undef DDR_PHY_DX0GCR4_RESERVED_7_6_MASK
13241 #define DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL 0x0E00003C
13242 #define DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT 6
13243 #define DDR_PHY_DX0GCR4_RESERVED_7_6_MASK 0x000000C0U
13246 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
13248 #undef DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL
13249 #undef DDR_PHY_DX0GCR4_DXREFIEN_SHIFT
13250 #undef DDR_PHY_DX0GCR4_DXREFIEN_MASK
13251 #define DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL 0x0E00003C
13252 #define DDR_PHY_DX0GCR4_DXREFIEN_SHIFT 2
13253 #define DDR_PHY_DX0GCR4_DXREFIEN_MASK 0x0000003CU
13256 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
13258 #undef DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL
13259 #undef DDR_PHY_DX0GCR4_DXREFIMON_SHIFT
13260 #undef DDR_PHY_DX0GCR4_DXREFIMON_MASK
13261 #define DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL 0x0E00003C
13262 #define DDR_PHY_DX0GCR4_DXREFIMON_SHIFT 0
13263 #define DDR_PHY_DX0GCR4_DXREFIMON_MASK 0x00000003U
13266 * Reserved. Returns zeros on reads.
13268 #undef DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL
13269 #undef DDR_PHY_DX0GCR5_RESERVED_31_SHIFT
13270 #undef DDR_PHY_DX0GCR5_RESERVED_31_MASK
13271 #define DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL 0x09090909
13272 #define DDR_PHY_DX0GCR5_RESERVED_31_SHIFT 31
13273 #define DDR_PHY_DX0GCR5_RESERVED_31_MASK 0x80000000U
13276 * Byte Lane internal VREF Select for Rank 3
13278 #undef DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL
13279 #undef DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT
13280 #undef DDR_PHY_DX0GCR5_DXREFISELR3_MASK
13281 #define DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL 0x09090909
13282 #define DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT 24
13283 #define DDR_PHY_DX0GCR5_DXREFISELR3_MASK 0x7F000000U
13286 * Reserved. Returns zeros on reads.
13288 #undef DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL
13289 #undef DDR_PHY_DX0GCR5_RESERVED_23_SHIFT
13290 #undef DDR_PHY_DX0GCR5_RESERVED_23_MASK
13291 #define DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL 0x09090909
13292 #define DDR_PHY_DX0GCR5_RESERVED_23_SHIFT 23
13293 #define DDR_PHY_DX0GCR5_RESERVED_23_MASK 0x00800000U
13296 * Byte Lane internal VREF Select for Rank 2
13298 #undef DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL
13299 #undef DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT
13300 #undef DDR_PHY_DX0GCR5_DXREFISELR2_MASK
13301 #define DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL 0x09090909
13302 #define DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT 16
13303 #define DDR_PHY_DX0GCR5_DXREFISELR2_MASK 0x007F0000U
13306 * Reserved. Returns zeros on reads.
13308 #undef DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL
13309 #undef DDR_PHY_DX0GCR5_RESERVED_15_SHIFT
13310 #undef DDR_PHY_DX0GCR5_RESERVED_15_MASK
13311 #define DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL 0x09090909
13312 #define DDR_PHY_DX0GCR5_RESERVED_15_SHIFT 15
13313 #define DDR_PHY_DX0GCR5_RESERVED_15_MASK 0x00008000U
13316 * Byte Lane internal VREF Select for Rank 1
13318 #undef DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL
13319 #undef DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT
13320 #undef DDR_PHY_DX0GCR5_DXREFISELR1_MASK
13321 #define DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL 0x09090909
13322 #define DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT 8
13323 #define DDR_PHY_DX0GCR5_DXREFISELR1_MASK 0x00007F00U
13326 * Reserved. Returns zeros on reads.
13328 #undef DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL
13329 #undef DDR_PHY_DX0GCR5_RESERVED_7_SHIFT
13330 #undef DDR_PHY_DX0GCR5_RESERVED_7_MASK
13331 #define DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL 0x09090909
13332 #define DDR_PHY_DX0GCR5_RESERVED_7_SHIFT 7
13333 #define DDR_PHY_DX0GCR5_RESERVED_7_MASK 0x00000080U
13336 * Byte Lane internal VREF Select for Rank 0
13338 #undef DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL
13339 #undef DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT
13340 #undef DDR_PHY_DX0GCR5_DXREFISELR0_MASK
13341 #define DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL 0x09090909
13342 #define DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT 0
13343 #define DDR_PHY_DX0GCR5_DXREFISELR0_MASK 0x0000007FU
13346 * Reserved. Returns zeros on reads.
13348 #undef DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL
13349 #undef DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT
13350 #undef DDR_PHY_DX0GCR6_RESERVED_31_30_MASK
13351 #define DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL 0x09090909
13352 #define DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT 30
13353 #define DDR_PHY_DX0GCR6_RESERVED_31_30_MASK 0xC0000000U
13356 * DRAM DQ VREF Select for Rank3
13358 #undef DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL
13359 #undef DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT
13360 #undef DDR_PHY_DX0GCR6_DXDQVREFR3_MASK
13361 #define DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL 0x09090909
13362 #define DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT 24
13363 #define DDR_PHY_DX0GCR6_DXDQVREFR3_MASK 0x3F000000U
13366 * Reserved. Returns zeros on reads.
13368 #undef DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL
13369 #undef DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT
13370 #undef DDR_PHY_DX0GCR6_RESERVED_23_22_MASK
13371 #define DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL 0x09090909
13372 #define DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT 22
13373 #define DDR_PHY_DX0GCR6_RESERVED_23_22_MASK 0x00C00000U
13376 * DRAM DQ VREF Select for Rank2
13378 #undef DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL
13379 #undef DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT
13380 #undef DDR_PHY_DX0GCR6_DXDQVREFR2_MASK
13381 #define DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL 0x09090909
13382 #define DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT 16
13383 #define DDR_PHY_DX0GCR6_DXDQVREFR2_MASK 0x003F0000U
13386 * Reserved. Returns zeros on reads.
13388 #undef DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL
13389 #undef DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT
13390 #undef DDR_PHY_DX0GCR6_RESERVED_15_14_MASK
13391 #define DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL 0x09090909
13392 #define DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT 14
13393 #define DDR_PHY_DX0GCR6_RESERVED_15_14_MASK 0x0000C000U
13396 * DRAM DQ VREF Select for Rank1
13398 #undef DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL
13399 #undef DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT
13400 #undef DDR_PHY_DX0GCR6_DXDQVREFR1_MASK
13401 #define DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL 0x09090909
13402 #define DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT 8
13403 #define DDR_PHY_DX0GCR6_DXDQVREFR1_MASK 0x00003F00U
13406 * Reserved. Returns zeros on reads.
13408 #undef DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL
13409 #undef DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT
13410 #undef DDR_PHY_DX0GCR6_RESERVED_7_6_MASK
13411 #define DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL 0x09090909
13412 #define DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT 6
13413 #define DDR_PHY_DX0GCR6_RESERVED_7_6_MASK 0x000000C0U
13416 * DRAM DQ VREF Select for Rank0
13418 #undef DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL
13419 #undef DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT
13420 #undef DDR_PHY_DX0GCR6_DXDQVREFR0_MASK
13421 #define DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL 0x09090909
13422 #define DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT 0
13423 #define DDR_PHY_DX0GCR6_DXDQVREFR0_MASK 0x0000003FU
13426 * Calibration Bypass
13428 #undef DDR_PHY_DX1GCR0_CALBYP_DEFVAL
13429 #undef DDR_PHY_DX1GCR0_CALBYP_SHIFT
13430 #undef DDR_PHY_DX1GCR0_CALBYP_MASK
13431 #define DDR_PHY_DX1GCR0_CALBYP_DEFVAL 0x40200204
13432 #define DDR_PHY_DX1GCR0_CALBYP_SHIFT 31
13433 #define DDR_PHY_DX1GCR0_CALBYP_MASK 0x80000000U
13436 * Master Delay Line Enable
13438 #undef DDR_PHY_DX1GCR0_MDLEN_DEFVAL
13439 #undef DDR_PHY_DX1GCR0_MDLEN_SHIFT
13440 #undef DDR_PHY_DX1GCR0_MDLEN_MASK
13441 #define DDR_PHY_DX1GCR0_MDLEN_DEFVAL 0x40200204
13442 #define DDR_PHY_DX1GCR0_MDLEN_SHIFT 30
13443 #define DDR_PHY_DX1GCR0_MDLEN_MASK 0x40000000U
13446 * Configurable ODT(TE) Phase Shift
13448 #undef DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL
13449 #undef DDR_PHY_DX1GCR0_CODTSHFT_SHIFT
13450 #undef DDR_PHY_DX1GCR0_CODTSHFT_MASK
13451 #define DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL 0x40200204
13452 #define DDR_PHY_DX1GCR0_CODTSHFT_SHIFT 28
13453 #define DDR_PHY_DX1GCR0_CODTSHFT_MASK 0x30000000U
13456 * DQS Duty Cycle Correction
13458 #undef DDR_PHY_DX1GCR0_DQSDCC_DEFVAL
13459 #undef DDR_PHY_DX1GCR0_DQSDCC_SHIFT
13460 #undef DDR_PHY_DX1GCR0_DQSDCC_MASK
13461 #define DDR_PHY_DX1GCR0_DQSDCC_DEFVAL 0x40200204
13462 #define DDR_PHY_DX1GCR0_DQSDCC_SHIFT 24
13463 #define DDR_PHY_DX1GCR0_DQSDCC_MASK 0x0F000000U
13466 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
13467 * input for the respective bypte lane of the PHY
13469 #undef DDR_PHY_DX1GCR0_RDDLY_DEFVAL
13470 #undef DDR_PHY_DX1GCR0_RDDLY_SHIFT
13471 #undef DDR_PHY_DX1GCR0_RDDLY_MASK
13472 #define DDR_PHY_DX1GCR0_RDDLY_DEFVAL 0x40200204
13473 #define DDR_PHY_DX1GCR0_RDDLY_SHIFT 20
13474 #define DDR_PHY_DX1GCR0_RDDLY_MASK 0x00F00000U
13477 * Reserved. Return zeroes on reads.
13479 #undef DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL
13480 #undef DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT
13481 #undef DDR_PHY_DX1GCR0_RESERVED_19_14_MASK
13482 #define DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL 0x40200204
13483 #define DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT 14
13484 #define DDR_PHY_DX1GCR0_RESERVED_19_14_MASK 0x000FC000U
13487 * DQSNSE Power Down Receiver
13489 #undef DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL
13490 #undef DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT
13491 #undef DDR_PHY_DX1GCR0_DQSNSEPDR_MASK
13492 #define DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL 0x40200204
13493 #define DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT 13
13494 #define DDR_PHY_DX1GCR0_DQSNSEPDR_MASK 0x00002000U
13497 * DQSSE Power Down Receiver
13499 #undef DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL
13500 #undef DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT
13501 #undef DDR_PHY_DX1GCR0_DQSSEPDR_MASK
13502 #define DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL 0x40200204
13503 #define DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT 12
13504 #define DDR_PHY_DX1GCR0_DQSSEPDR_MASK 0x00001000U
13507 * RTT On Additive Latency
13509 #undef DDR_PHY_DX1GCR0_RTTOAL_DEFVAL
13510 #undef DDR_PHY_DX1GCR0_RTTOAL_SHIFT
13511 #undef DDR_PHY_DX1GCR0_RTTOAL_MASK
13512 #define DDR_PHY_DX1GCR0_RTTOAL_DEFVAL 0x40200204
13513 #define DDR_PHY_DX1GCR0_RTTOAL_SHIFT 11
13514 #define DDR_PHY_DX1GCR0_RTTOAL_MASK 0x00000800U
13519 #undef DDR_PHY_DX1GCR0_RTTOH_DEFVAL
13520 #undef DDR_PHY_DX1GCR0_RTTOH_SHIFT
13521 #undef DDR_PHY_DX1GCR0_RTTOH_MASK
13522 #define DDR_PHY_DX1GCR0_RTTOH_DEFVAL 0x40200204
13523 #define DDR_PHY_DX1GCR0_RTTOH_SHIFT 9
13524 #define DDR_PHY_DX1GCR0_RTTOH_MASK 0x00000600U
13527 * Configurable PDR Phase Shift
13529 #undef DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL
13530 #undef DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT
13531 #undef DDR_PHY_DX1GCR0_CPDRSHFT_MASK
13532 #define DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL 0x40200204
13533 #define DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT 7
13534 #define DDR_PHY_DX1GCR0_CPDRSHFT_MASK 0x00000180U
13539 #undef DDR_PHY_DX1GCR0_DQSRPD_DEFVAL
13540 #undef DDR_PHY_DX1GCR0_DQSRPD_SHIFT
13541 #undef DDR_PHY_DX1GCR0_DQSRPD_MASK
13542 #define DDR_PHY_DX1GCR0_DQSRPD_DEFVAL 0x40200204
13543 #define DDR_PHY_DX1GCR0_DQSRPD_SHIFT 6
13544 #define DDR_PHY_DX1GCR0_DQSRPD_MASK 0x00000040U
13547 * DQSG Power Down Receiver
13549 #undef DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL
13550 #undef DDR_PHY_DX1GCR0_DQSGPDR_SHIFT
13551 #undef DDR_PHY_DX1GCR0_DQSGPDR_MASK
13552 #define DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL 0x40200204
13553 #define DDR_PHY_DX1GCR0_DQSGPDR_SHIFT 5
13554 #define DDR_PHY_DX1GCR0_DQSGPDR_MASK 0x00000020U
13557 * Reserved. Return zeroes on reads.
13559 #undef DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL
13560 #undef DDR_PHY_DX1GCR0_RESERVED_4_SHIFT
13561 #undef DDR_PHY_DX1GCR0_RESERVED_4_MASK
13562 #define DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL 0x40200204
13563 #define DDR_PHY_DX1GCR0_RESERVED_4_SHIFT 4
13564 #define DDR_PHY_DX1GCR0_RESERVED_4_MASK 0x00000010U
13567 * DQSG On-Die Termination
13569 #undef DDR_PHY_DX1GCR0_DQSGODT_DEFVAL
13570 #undef DDR_PHY_DX1GCR0_DQSGODT_SHIFT
13571 #undef DDR_PHY_DX1GCR0_DQSGODT_MASK
13572 #define DDR_PHY_DX1GCR0_DQSGODT_DEFVAL 0x40200204
13573 #define DDR_PHY_DX1GCR0_DQSGODT_SHIFT 3
13574 #define DDR_PHY_DX1GCR0_DQSGODT_MASK 0x00000008U
13577 * DQSG Output Enable
13579 #undef DDR_PHY_DX1GCR0_DQSGOE_DEFVAL
13580 #undef DDR_PHY_DX1GCR0_DQSGOE_SHIFT
13581 #undef DDR_PHY_DX1GCR0_DQSGOE_MASK
13582 #define DDR_PHY_DX1GCR0_DQSGOE_DEFVAL 0x40200204
13583 #define DDR_PHY_DX1GCR0_DQSGOE_SHIFT 2
13584 #define DDR_PHY_DX1GCR0_DQSGOE_MASK 0x00000004U
13587 * Reserved. Return zeroes on reads.
13589 #undef DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL
13590 #undef DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT
13591 #undef DDR_PHY_DX1GCR0_RESERVED_1_0_MASK
13592 #define DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL 0x40200204
13593 #define DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT 0
13594 #define DDR_PHY_DX1GCR0_RESERVED_1_0_MASK 0x00000003U
13597 * Byte lane VREF IOM (Used only by D4MU IOs)
13599 #undef DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL
13600 #undef DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT
13601 #undef DDR_PHY_DX1GCR4_RESERVED_31_29_MASK
13602 #define DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL 0x0E00003C
13603 #define DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT 29
13604 #define DDR_PHY_DX1GCR4_RESERVED_31_29_MASK 0xE0000000U
13607 * Byte Lane VREF Pad Enable
13609 #undef DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL
13610 #undef DDR_PHY_DX1GCR4_DXREFPEN_SHIFT
13611 #undef DDR_PHY_DX1GCR4_DXREFPEN_MASK
13612 #define DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL 0x0E00003C
13613 #define DDR_PHY_DX1GCR4_DXREFPEN_SHIFT 28
13614 #define DDR_PHY_DX1GCR4_DXREFPEN_MASK 0x10000000U
13617 * Byte Lane Internal VREF Enable
13619 #undef DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL
13620 #undef DDR_PHY_DX1GCR4_DXREFEEN_SHIFT
13621 #undef DDR_PHY_DX1GCR4_DXREFEEN_MASK
13622 #define DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL 0x0E00003C
13623 #define DDR_PHY_DX1GCR4_DXREFEEN_SHIFT 26
13624 #define DDR_PHY_DX1GCR4_DXREFEEN_MASK 0x0C000000U
13627 * Byte Lane Single-End VREF Enable
13629 #undef DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL
13630 #undef DDR_PHY_DX1GCR4_DXREFSEN_SHIFT
13631 #undef DDR_PHY_DX1GCR4_DXREFSEN_MASK
13632 #define DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL 0x0E00003C
13633 #define DDR_PHY_DX1GCR4_DXREFSEN_SHIFT 25
13634 #define DDR_PHY_DX1GCR4_DXREFSEN_MASK 0x02000000U
13637 * Reserved. Returns zeros on reads.
13639 #undef DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL
13640 #undef DDR_PHY_DX1GCR4_RESERVED_24_SHIFT
13641 #undef DDR_PHY_DX1GCR4_RESERVED_24_MASK
13642 #define DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL 0x0E00003C
13643 #define DDR_PHY_DX1GCR4_RESERVED_24_SHIFT 24
13644 #define DDR_PHY_DX1GCR4_RESERVED_24_MASK 0x01000000U
13647 * External VREF generator REFSEL range select
13649 #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL
13650 #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT
13651 #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK
13652 #define DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C
13653 #define DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT 23
13654 #define DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK 0x00800000U
13657 * Byte Lane External VREF Select
13659 #undef DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL
13660 #undef DDR_PHY_DX1GCR4_DXREFESEL_SHIFT
13661 #undef DDR_PHY_DX1GCR4_DXREFESEL_MASK
13662 #define DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL 0x0E00003C
13663 #define DDR_PHY_DX1GCR4_DXREFESEL_SHIFT 16
13664 #define DDR_PHY_DX1GCR4_DXREFESEL_MASK 0x007F0000U
13667 * Single ended VREF generator REFSEL range select
13669 #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL
13670 #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT
13671 #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK
13672 #define DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C
13673 #define DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT 15
13674 #define DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK 0x00008000U
13677 * Byte Lane Single-End VREF Select
13679 #undef DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL
13680 #undef DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT
13681 #undef DDR_PHY_DX1GCR4_DXREFSSEL_MASK
13682 #define DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL 0x0E00003C
13683 #define DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT 8
13684 #define DDR_PHY_DX1GCR4_DXREFSSEL_MASK 0x00007F00U
13687 * Reserved. Returns zeros on reads.
13689 #undef DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL
13690 #undef DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT
13691 #undef DDR_PHY_DX1GCR4_RESERVED_7_6_MASK
13692 #define DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL 0x0E00003C
13693 #define DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT 6
13694 #define DDR_PHY_DX1GCR4_RESERVED_7_6_MASK 0x000000C0U
13697 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
13699 #undef DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL
13700 #undef DDR_PHY_DX1GCR4_DXREFIEN_SHIFT
13701 #undef DDR_PHY_DX1GCR4_DXREFIEN_MASK
13702 #define DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL 0x0E00003C
13703 #define DDR_PHY_DX1GCR4_DXREFIEN_SHIFT 2
13704 #define DDR_PHY_DX1GCR4_DXREFIEN_MASK 0x0000003CU
13707 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
13709 #undef DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL
13710 #undef DDR_PHY_DX1GCR4_DXREFIMON_SHIFT
13711 #undef DDR_PHY_DX1GCR4_DXREFIMON_MASK
13712 #define DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL 0x0E00003C
13713 #define DDR_PHY_DX1GCR4_DXREFIMON_SHIFT 0
13714 #define DDR_PHY_DX1GCR4_DXREFIMON_MASK 0x00000003U
13717 * Reserved. Returns zeros on reads.
13719 #undef DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL
13720 #undef DDR_PHY_DX1GCR5_RESERVED_31_SHIFT
13721 #undef DDR_PHY_DX1GCR5_RESERVED_31_MASK
13722 #define DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL 0x09090909
13723 #define DDR_PHY_DX1GCR5_RESERVED_31_SHIFT 31
13724 #define DDR_PHY_DX1GCR5_RESERVED_31_MASK 0x80000000U
13727 * Byte Lane internal VREF Select for Rank 3
13729 #undef DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL
13730 #undef DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT
13731 #undef DDR_PHY_DX1GCR5_DXREFISELR3_MASK
13732 #define DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL 0x09090909
13733 #define DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT 24
13734 #define DDR_PHY_DX1GCR5_DXREFISELR3_MASK 0x7F000000U
13737 * Reserved. Returns zeros on reads.
13739 #undef DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL
13740 #undef DDR_PHY_DX1GCR5_RESERVED_23_SHIFT
13741 #undef DDR_PHY_DX1GCR5_RESERVED_23_MASK
13742 #define DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL 0x09090909
13743 #define DDR_PHY_DX1GCR5_RESERVED_23_SHIFT 23
13744 #define DDR_PHY_DX1GCR5_RESERVED_23_MASK 0x00800000U
13747 * Byte Lane internal VREF Select for Rank 2
13749 #undef DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL
13750 #undef DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT
13751 #undef DDR_PHY_DX1GCR5_DXREFISELR2_MASK
13752 #define DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL 0x09090909
13753 #define DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT 16
13754 #define DDR_PHY_DX1GCR5_DXREFISELR2_MASK 0x007F0000U
13757 * Reserved. Returns zeros on reads.
13759 #undef DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL
13760 #undef DDR_PHY_DX1GCR5_RESERVED_15_SHIFT
13761 #undef DDR_PHY_DX1GCR5_RESERVED_15_MASK
13762 #define DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL 0x09090909
13763 #define DDR_PHY_DX1GCR5_RESERVED_15_SHIFT 15
13764 #define DDR_PHY_DX1GCR5_RESERVED_15_MASK 0x00008000U
13767 * Byte Lane internal VREF Select for Rank 1
13769 #undef DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL
13770 #undef DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT
13771 #undef DDR_PHY_DX1GCR5_DXREFISELR1_MASK
13772 #define DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL 0x09090909
13773 #define DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT 8
13774 #define DDR_PHY_DX1GCR5_DXREFISELR1_MASK 0x00007F00U
13777 * Reserved. Returns zeros on reads.
13779 #undef DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL
13780 #undef DDR_PHY_DX1GCR5_RESERVED_7_SHIFT
13781 #undef DDR_PHY_DX1GCR5_RESERVED_7_MASK
13782 #define DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL 0x09090909
13783 #define DDR_PHY_DX1GCR5_RESERVED_7_SHIFT 7
13784 #define DDR_PHY_DX1GCR5_RESERVED_7_MASK 0x00000080U
13787 * Byte Lane internal VREF Select for Rank 0
13789 #undef DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL
13790 #undef DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT
13791 #undef DDR_PHY_DX1GCR5_DXREFISELR0_MASK
13792 #define DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL 0x09090909
13793 #define DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT 0
13794 #define DDR_PHY_DX1GCR5_DXREFISELR0_MASK 0x0000007FU
13797 * Reserved. Returns zeros on reads.
13799 #undef DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL
13800 #undef DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT
13801 #undef DDR_PHY_DX1GCR6_RESERVED_31_30_MASK
13802 #define DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL 0x09090909
13803 #define DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT 30
13804 #define DDR_PHY_DX1GCR6_RESERVED_31_30_MASK 0xC0000000U
13807 * DRAM DQ VREF Select for Rank3
13809 #undef DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL
13810 #undef DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT
13811 #undef DDR_PHY_DX1GCR6_DXDQVREFR3_MASK
13812 #define DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL 0x09090909
13813 #define DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT 24
13814 #define DDR_PHY_DX1GCR6_DXDQVREFR3_MASK 0x3F000000U
13817 * Reserved. Returns zeros on reads.
13819 #undef DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL
13820 #undef DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT
13821 #undef DDR_PHY_DX1GCR6_RESERVED_23_22_MASK
13822 #define DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL 0x09090909
13823 #define DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT 22
13824 #define DDR_PHY_DX1GCR6_RESERVED_23_22_MASK 0x00C00000U
13827 * DRAM DQ VREF Select for Rank2
13829 #undef DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL
13830 #undef DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT
13831 #undef DDR_PHY_DX1GCR6_DXDQVREFR2_MASK
13832 #define DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL 0x09090909
13833 #define DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT 16
13834 #define DDR_PHY_DX1GCR6_DXDQVREFR2_MASK 0x003F0000U
13837 * Reserved. Returns zeros on reads.
13839 #undef DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL
13840 #undef DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT
13841 #undef DDR_PHY_DX1GCR6_RESERVED_15_14_MASK
13842 #define DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL 0x09090909
13843 #define DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT 14
13844 #define DDR_PHY_DX1GCR6_RESERVED_15_14_MASK 0x0000C000U
13847 * DRAM DQ VREF Select for Rank1
13849 #undef DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL
13850 #undef DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT
13851 #undef DDR_PHY_DX1GCR6_DXDQVREFR1_MASK
13852 #define DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL 0x09090909
13853 #define DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT 8
13854 #define DDR_PHY_DX1GCR6_DXDQVREFR1_MASK 0x00003F00U
13857 * Reserved. Returns zeros on reads.
13859 #undef DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL
13860 #undef DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT
13861 #undef DDR_PHY_DX1GCR6_RESERVED_7_6_MASK
13862 #define DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL 0x09090909
13863 #define DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT 6
13864 #define DDR_PHY_DX1GCR6_RESERVED_7_6_MASK 0x000000C0U
13867 * DRAM DQ VREF Select for Rank0
13869 #undef DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL
13870 #undef DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT
13871 #undef DDR_PHY_DX1GCR6_DXDQVREFR0_MASK
13872 #define DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL 0x09090909
13873 #define DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT 0
13874 #define DDR_PHY_DX1GCR6_DXDQVREFR0_MASK 0x0000003FU
13877 * Calibration Bypass
13879 #undef DDR_PHY_DX2GCR0_CALBYP_DEFVAL
13880 #undef DDR_PHY_DX2GCR0_CALBYP_SHIFT
13881 #undef DDR_PHY_DX2GCR0_CALBYP_MASK
13882 #define DDR_PHY_DX2GCR0_CALBYP_DEFVAL 0x40200204
13883 #define DDR_PHY_DX2GCR0_CALBYP_SHIFT 31
13884 #define DDR_PHY_DX2GCR0_CALBYP_MASK 0x80000000U
13887 * Master Delay Line Enable
13889 #undef DDR_PHY_DX2GCR0_MDLEN_DEFVAL
13890 #undef DDR_PHY_DX2GCR0_MDLEN_SHIFT
13891 #undef DDR_PHY_DX2GCR0_MDLEN_MASK
13892 #define DDR_PHY_DX2GCR0_MDLEN_DEFVAL 0x40200204
13893 #define DDR_PHY_DX2GCR0_MDLEN_SHIFT 30
13894 #define DDR_PHY_DX2GCR0_MDLEN_MASK 0x40000000U
13897 * Configurable ODT(TE) Phase Shift
13899 #undef DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL
13900 #undef DDR_PHY_DX2GCR0_CODTSHFT_SHIFT
13901 #undef DDR_PHY_DX2GCR0_CODTSHFT_MASK
13902 #define DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL 0x40200204
13903 #define DDR_PHY_DX2GCR0_CODTSHFT_SHIFT 28
13904 #define DDR_PHY_DX2GCR0_CODTSHFT_MASK 0x30000000U
13907 * DQS Duty Cycle Correction
13909 #undef DDR_PHY_DX2GCR0_DQSDCC_DEFVAL
13910 #undef DDR_PHY_DX2GCR0_DQSDCC_SHIFT
13911 #undef DDR_PHY_DX2GCR0_DQSDCC_MASK
13912 #define DDR_PHY_DX2GCR0_DQSDCC_DEFVAL 0x40200204
13913 #define DDR_PHY_DX2GCR0_DQSDCC_SHIFT 24
13914 #define DDR_PHY_DX2GCR0_DQSDCC_MASK 0x0F000000U
13917 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
13918 * input for the respective bypte lane of the PHY
13920 #undef DDR_PHY_DX2GCR0_RDDLY_DEFVAL
13921 #undef DDR_PHY_DX2GCR0_RDDLY_SHIFT
13922 #undef DDR_PHY_DX2GCR0_RDDLY_MASK
13923 #define DDR_PHY_DX2GCR0_RDDLY_DEFVAL 0x40200204
13924 #define DDR_PHY_DX2GCR0_RDDLY_SHIFT 20
13925 #define DDR_PHY_DX2GCR0_RDDLY_MASK 0x00F00000U
13928 * Reserved. Return zeroes on reads.
13930 #undef DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL
13931 #undef DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT
13932 #undef DDR_PHY_DX2GCR0_RESERVED_19_14_MASK
13933 #define DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL 0x40200204
13934 #define DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT 14
13935 #define DDR_PHY_DX2GCR0_RESERVED_19_14_MASK 0x000FC000U
13938 * DQSNSE Power Down Receiver
13940 #undef DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL
13941 #undef DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT
13942 #undef DDR_PHY_DX2GCR0_DQSNSEPDR_MASK
13943 #define DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL 0x40200204
13944 #define DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT 13
13945 #define DDR_PHY_DX2GCR0_DQSNSEPDR_MASK 0x00002000U
13948 * DQSSE Power Down Receiver
13950 #undef DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL
13951 #undef DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT
13952 #undef DDR_PHY_DX2GCR0_DQSSEPDR_MASK
13953 #define DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL 0x40200204
13954 #define DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT 12
13955 #define DDR_PHY_DX2GCR0_DQSSEPDR_MASK 0x00001000U
13958 * RTT On Additive Latency
13960 #undef DDR_PHY_DX2GCR0_RTTOAL_DEFVAL
13961 #undef DDR_PHY_DX2GCR0_RTTOAL_SHIFT
13962 #undef DDR_PHY_DX2GCR0_RTTOAL_MASK
13963 #define DDR_PHY_DX2GCR0_RTTOAL_DEFVAL 0x40200204
13964 #define DDR_PHY_DX2GCR0_RTTOAL_SHIFT 11
13965 #define DDR_PHY_DX2GCR0_RTTOAL_MASK 0x00000800U
13970 #undef DDR_PHY_DX2GCR0_RTTOH_DEFVAL
13971 #undef DDR_PHY_DX2GCR0_RTTOH_SHIFT
13972 #undef DDR_PHY_DX2GCR0_RTTOH_MASK
13973 #define DDR_PHY_DX2GCR0_RTTOH_DEFVAL 0x40200204
13974 #define DDR_PHY_DX2GCR0_RTTOH_SHIFT 9
13975 #define DDR_PHY_DX2GCR0_RTTOH_MASK 0x00000600U
13978 * Configurable PDR Phase Shift
13980 #undef DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL
13981 #undef DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT
13982 #undef DDR_PHY_DX2GCR0_CPDRSHFT_MASK
13983 #define DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL 0x40200204
13984 #define DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT 7
13985 #define DDR_PHY_DX2GCR0_CPDRSHFT_MASK 0x00000180U
13990 #undef DDR_PHY_DX2GCR0_DQSRPD_DEFVAL
13991 #undef DDR_PHY_DX2GCR0_DQSRPD_SHIFT
13992 #undef DDR_PHY_DX2GCR0_DQSRPD_MASK
13993 #define DDR_PHY_DX2GCR0_DQSRPD_DEFVAL 0x40200204
13994 #define DDR_PHY_DX2GCR0_DQSRPD_SHIFT 6
13995 #define DDR_PHY_DX2GCR0_DQSRPD_MASK 0x00000040U
13998 * DQSG Power Down Receiver
14000 #undef DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL
14001 #undef DDR_PHY_DX2GCR0_DQSGPDR_SHIFT
14002 #undef DDR_PHY_DX2GCR0_DQSGPDR_MASK
14003 #define DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL 0x40200204
14004 #define DDR_PHY_DX2GCR0_DQSGPDR_SHIFT 5
14005 #define DDR_PHY_DX2GCR0_DQSGPDR_MASK 0x00000020U
14008 * Reserved. Return zeroes on reads.
14010 #undef DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL
14011 #undef DDR_PHY_DX2GCR0_RESERVED_4_SHIFT
14012 #undef DDR_PHY_DX2GCR0_RESERVED_4_MASK
14013 #define DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL 0x40200204
14014 #define DDR_PHY_DX2GCR0_RESERVED_4_SHIFT 4
14015 #define DDR_PHY_DX2GCR0_RESERVED_4_MASK 0x00000010U
14018 * DQSG On-Die Termination
14020 #undef DDR_PHY_DX2GCR0_DQSGODT_DEFVAL
14021 #undef DDR_PHY_DX2GCR0_DQSGODT_SHIFT
14022 #undef DDR_PHY_DX2GCR0_DQSGODT_MASK
14023 #define DDR_PHY_DX2GCR0_DQSGODT_DEFVAL 0x40200204
14024 #define DDR_PHY_DX2GCR0_DQSGODT_SHIFT 3
14025 #define DDR_PHY_DX2GCR0_DQSGODT_MASK 0x00000008U
14028 * DQSG Output Enable
14030 #undef DDR_PHY_DX2GCR0_DQSGOE_DEFVAL
14031 #undef DDR_PHY_DX2GCR0_DQSGOE_SHIFT
14032 #undef DDR_PHY_DX2GCR0_DQSGOE_MASK
14033 #define DDR_PHY_DX2GCR0_DQSGOE_DEFVAL 0x40200204
14034 #define DDR_PHY_DX2GCR0_DQSGOE_SHIFT 2
14035 #define DDR_PHY_DX2GCR0_DQSGOE_MASK 0x00000004U
14038 * Reserved. Return zeroes on reads.
14040 #undef DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL
14041 #undef DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT
14042 #undef DDR_PHY_DX2GCR0_RESERVED_1_0_MASK
14043 #define DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL 0x40200204
14044 #define DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT 0
14045 #define DDR_PHY_DX2GCR0_RESERVED_1_0_MASK 0x00000003U
14048 * Enables the PDR mode for DQ[7:0]
14050 #undef DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL
14051 #undef DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT
14052 #undef DDR_PHY_DX2GCR1_DXPDRMODE_MASK
14053 #define DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL 0x00007FFF
14054 #define DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT 16
14055 #define DDR_PHY_DX2GCR1_DXPDRMODE_MASK 0xFFFF0000U
14058 * Reserved. Returns zeroes on reads.
14060 #undef DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL
14061 #undef DDR_PHY_DX2GCR1_RESERVED_15_SHIFT
14062 #undef DDR_PHY_DX2GCR1_RESERVED_15_MASK
14063 #define DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL 0x00007FFF
14064 #define DDR_PHY_DX2GCR1_RESERVED_15_SHIFT 15
14065 #define DDR_PHY_DX2GCR1_RESERVED_15_MASK 0x00008000U
14068 * Select the delayed or non-delayed read data strobe #
14070 #undef DDR_PHY_DX2GCR1_QSNSEL_DEFVAL
14071 #undef DDR_PHY_DX2GCR1_QSNSEL_SHIFT
14072 #undef DDR_PHY_DX2GCR1_QSNSEL_MASK
14073 #define DDR_PHY_DX2GCR1_QSNSEL_DEFVAL 0x00007FFF
14074 #define DDR_PHY_DX2GCR1_QSNSEL_SHIFT 14
14075 #define DDR_PHY_DX2GCR1_QSNSEL_MASK 0x00004000U
14078 * Select the delayed or non-delayed read data strobe
14080 #undef DDR_PHY_DX2GCR1_QSSEL_DEFVAL
14081 #undef DDR_PHY_DX2GCR1_QSSEL_SHIFT
14082 #undef DDR_PHY_DX2GCR1_QSSEL_MASK
14083 #define DDR_PHY_DX2GCR1_QSSEL_DEFVAL 0x00007FFF
14084 #define DDR_PHY_DX2GCR1_QSSEL_SHIFT 13
14085 #define DDR_PHY_DX2GCR1_QSSEL_MASK 0x00002000U
14088 * Enables Read Data Strobe in a byte lane
14090 #undef DDR_PHY_DX2GCR1_OEEN_DEFVAL
14091 #undef DDR_PHY_DX2GCR1_OEEN_SHIFT
14092 #undef DDR_PHY_DX2GCR1_OEEN_MASK
14093 #define DDR_PHY_DX2GCR1_OEEN_DEFVAL 0x00007FFF
14094 #define DDR_PHY_DX2GCR1_OEEN_SHIFT 12
14095 #define DDR_PHY_DX2GCR1_OEEN_MASK 0x00001000U
14098 * Enables PDR in a byte lane
14100 #undef DDR_PHY_DX2GCR1_PDREN_DEFVAL
14101 #undef DDR_PHY_DX2GCR1_PDREN_SHIFT
14102 #undef DDR_PHY_DX2GCR1_PDREN_MASK
14103 #define DDR_PHY_DX2GCR1_PDREN_DEFVAL 0x00007FFF
14104 #define DDR_PHY_DX2GCR1_PDREN_SHIFT 11
14105 #define DDR_PHY_DX2GCR1_PDREN_MASK 0x00000800U
14108 * Enables ODT/TE in a byte lane
14110 #undef DDR_PHY_DX2GCR1_TEEN_DEFVAL
14111 #undef DDR_PHY_DX2GCR1_TEEN_SHIFT
14112 #undef DDR_PHY_DX2GCR1_TEEN_MASK
14113 #define DDR_PHY_DX2GCR1_TEEN_DEFVAL 0x00007FFF
14114 #define DDR_PHY_DX2GCR1_TEEN_SHIFT 10
14115 #define DDR_PHY_DX2GCR1_TEEN_MASK 0x00000400U
14118 * Enables Write Data strobe in a byte lane
14120 #undef DDR_PHY_DX2GCR1_DSEN_DEFVAL
14121 #undef DDR_PHY_DX2GCR1_DSEN_SHIFT
14122 #undef DDR_PHY_DX2GCR1_DSEN_MASK
14123 #define DDR_PHY_DX2GCR1_DSEN_DEFVAL 0x00007FFF
14124 #define DDR_PHY_DX2GCR1_DSEN_SHIFT 9
14125 #define DDR_PHY_DX2GCR1_DSEN_MASK 0x00000200U
14128 * Enables DM pin in a byte lane
14130 #undef DDR_PHY_DX2GCR1_DMEN_DEFVAL
14131 #undef DDR_PHY_DX2GCR1_DMEN_SHIFT
14132 #undef DDR_PHY_DX2GCR1_DMEN_MASK
14133 #define DDR_PHY_DX2GCR1_DMEN_DEFVAL 0x00007FFF
14134 #define DDR_PHY_DX2GCR1_DMEN_SHIFT 8
14135 #define DDR_PHY_DX2GCR1_DMEN_MASK 0x00000100U
14138 * Enables DQ corresponding to each bit in a byte
14140 #undef DDR_PHY_DX2GCR1_DQEN_DEFVAL
14141 #undef DDR_PHY_DX2GCR1_DQEN_SHIFT
14142 #undef DDR_PHY_DX2GCR1_DQEN_MASK
14143 #define DDR_PHY_DX2GCR1_DQEN_DEFVAL 0x00007FFF
14144 #define DDR_PHY_DX2GCR1_DQEN_SHIFT 0
14145 #define DDR_PHY_DX2GCR1_DQEN_MASK 0x000000FFU
14148 * Byte lane VREF IOM (Used only by D4MU IOs)
14150 #undef DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL
14151 #undef DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT
14152 #undef DDR_PHY_DX2GCR4_RESERVED_31_29_MASK
14153 #define DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL 0x0E00003C
14154 #define DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT 29
14155 #define DDR_PHY_DX2GCR4_RESERVED_31_29_MASK 0xE0000000U
14158 * Byte Lane VREF Pad Enable
14160 #undef DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL
14161 #undef DDR_PHY_DX2GCR4_DXREFPEN_SHIFT
14162 #undef DDR_PHY_DX2GCR4_DXREFPEN_MASK
14163 #define DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL 0x0E00003C
14164 #define DDR_PHY_DX2GCR4_DXREFPEN_SHIFT 28
14165 #define DDR_PHY_DX2GCR4_DXREFPEN_MASK 0x10000000U
14168 * Byte Lane Internal VREF Enable
14170 #undef DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL
14171 #undef DDR_PHY_DX2GCR4_DXREFEEN_SHIFT
14172 #undef DDR_PHY_DX2GCR4_DXREFEEN_MASK
14173 #define DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL 0x0E00003C
14174 #define DDR_PHY_DX2GCR4_DXREFEEN_SHIFT 26
14175 #define DDR_PHY_DX2GCR4_DXREFEEN_MASK 0x0C000000U
14178 * Byte Lane Single-End VREF Enable
14180 #undef DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL
14181 #undef DDR_PHY_DX2GCR4_DXREFSEN_SHIFT
14182 #undef DDR_PHY_DX2GCR4_DXREFSEN_MASK
14183 #define DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL 0x0E00003C
14184 #define DDR_PHY_DX2GCR4_DXREFSEN_SHIFT 25
14185 #define DDR_PHY_DX2GCR4_DXREFSEN_MASK 0x02000000U
14188 * Reserved. Returns zeros on reads.
14190 #undef DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL
14191 #undef DDR_PHY_DX2GCR4_RESERVED_24_SHIFT
14192 #undef DDR_PHY_DX2GCR4_RESERVED_24_MASK
14193 #define DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL 0x0E00003C
14194 #define DDR_PHY_DX2GCR4_RESERVED_24_SHIFT 24
14195 #define DDR_PHY_DX2GCR4_RESERVED_24_MASK 0x01000000U
14198 * External VREF generator REFSEL range select
14200 #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL
14201 #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT
14202 #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK
14203 #define DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C
14204 #define DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT 23
14205 #define DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK 0x00800000U
14208 * Byte Lane External VREF Select
14210 #undef DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL
14211 #undef DDR_PHY_DX2GCR4_DXREFESEL_SHIFT
14212 #undef DDR_PHY_DX2GCR4_DXREFESEL_MASK
14213 #define DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL 0x0E00003C
14214 #define DDR_PHY_DX2GCR4_DXREFESEL_SHIFT 16
14215 #define DDR_PHY_DX2GCR4_DXREFESEL_MASK 0x007F0000U
14218 * Single ended VREF generator REFSEL range select
14220 #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL
14221 #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT
14222 #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK
14223 #define DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C
14224 #define DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT 15
14225 #define DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK 0x00008000U
14228 * Byte Lane Single-End VREF Select
14230 #undef DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL
14231 #undef DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT
14232 #undef DDR_PHY_DX2GCR4_DXREFSSEL_MASK
14233 #define DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL 0x0E00003C
14234 #define DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT 8
14235 #define DDR_PHY_DX2GCR4_DXREFSSEL_MASK 0x00007F00U
14238 * Reserved. Returns zeros on reads.
14240 #undef DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL
14241 #undef DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT
14242 #undef DDR_PHY_DX2GCR4_RESERVED_7_6_MASK
14243 #define DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL 0x0E00003C
14244 #define DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT 6
14245 #define DDR_PHY_DX2GCR4_RESERVED_7_6_MASK 0x000000C0U
14248 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
14250 #undef DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL
14251 #undef DDR_PHY_DX2GCR4_DXREFIEN_SHIFT
14252 #undef DDR_PHY_DX2GCR4_DXREFIEN_MASK
14253 #define DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL 0x0E00003C
14254 #define DDR_PHY_DX2GCR4_DXREFIEN_SHIFT 2
14255 #define DDR_PHY_DX2GCR4_DXREFIEN_MASK 0x0000003CU
14258 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
14260 #undef DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL
14261 #undef DDR_PHY_DX2GCR4_DXREFIMON_SHIFT
14262 #undef DDR_PHY_DX2GCR4_DXREFIMON_MASK
14263 #define DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL 0x0E00003C
14264 #define DDR_PHY_DX2GCR4_DXREFIMON_SHIFT 0
14265 #define DDR_PHY_DX2GCR4_DXREFIMON_MASK 0x00000003U
14268 * Reserved. Returns zeros on reads.
14270 #undef DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL
14271 #undef DDR_PHY_DX2GCR5_RESERVED_31_SHIFT
14272 #undef DDR_PHY_DX2GCR5_RESERVED_31_MASK
14273 #define DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL 0x09090909
14274 #define DDR_PHY_DX2GCR5_RESERVED_31_SHIFT 31
14275 #define DDR_PHY_DX2GCR5_RESERVED_31_MASK 0x80000000U
14278 * Byte Lane internal VREF Select for Rank 3
14280 #undef DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL
14281 #undef DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT
14282 #undef DDR_PHY_DX2GCR5_DXREFISELR3_MASK
14283 #define DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL 0x09090909
14284 #define DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT 24
14285 #define DDR_PHY_DX2GCR5_DXREFISELR3_MASK 0x7F000000U
14288 * Reserved. Returns zeros on reads.
14290 #undef DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL
14291 #undef DDR_PHY_DX2GCR5_RESERVED_23_SHIFT
14292 #undef DDR_PHY_DX2GCR5_RESERVED_23_MASK
14293 #define DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL 0x09090909
14294 #define DDR_PHY_DX2GCR5_RESERVED_23_SHIFT 23
14295 #define DDR_PHY_DX2GCR5_RESERVED_23_MASK 0x00800000U
14298 * Byte Lane internal VREF Select for Rank 2
14300 #undef DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL
14301 #undef DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT
14302 #undef DDR_PHY_DX2GCR5_DXREFISELR2_MASK
14303 #define DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL 0x09090909
14304 #define DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT 16
14305 #define DDR_PHY_DX2GCR5_DXREFISELR2_MASK 0x007F0000U
14308 * Reserved. Returns zeros on reads.
14310 #undef DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL
14311 #undef DDR_PHY_DX2GCR5_RESERVED_15_SHIFT
14312 #undef DDR_PHY_DX2GCR5_RESERVED_15_MASK
14313 #define DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL 0x09090909
14314 #define DDR_PHY_DX2GCR5_RESERVED_15_SHIFT 15
14315 #define DDR_PHY_DX2GCR5_RESERVED_15_MASK 0x00008000U
14318 * Byte Lane internal VREF Select for Rank 1
14320 #undef DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL
14321 #undef DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT
14322 #undef DDR_PHY_DX2GCR5_DXREFISELR1_MASK
14323 #define DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL 0x09090909
14324 #define DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT 8
14325 #define DDR_PHY_DX2GCR5_DXREFISELR1_MASK 0x00007F00U
14328 * Reserved. Returns zeros on reads.
14330 #undef DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL
14331 #undef DDR_PHY_DX2GCR5_RESERVED_7_SHIFT
14332 #undef DDR_PHY_DX2GCR5_RESERVED_7_MASK
14333 #define DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL 0x09090909
14334 #define DDR_PHY_DX2GCR5_RESERVED_7_SHIFT 7
14335 #define DDR_PHY_DX2GCR5_RESERVED_7_MASK 0x00000080U
14338 * Byte Lane internal VREF Select for Rank 0
14340 #undef DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL
14341 #undef DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT
14342 #undef DDR_PHY_DX2GCR5_DXREFISELR0_MASK
14343 #define DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL 0x09090909
14344 #define DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT 0
14345 #define DDR_PHY_DX2GCR5_DXREFISELR0_MASK 0x0000007FU
14348 * Reserved. Returns zeros on reads.
14350 #undef DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL
14351 #undef DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT
14352 #undef DDR_PHY_DX2GCR6_RESERVED_31_30_MASK
14353 #define DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL 0x09090909
14354 #define DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT 30
14355 #define DDR_PHY_DX2GCR6_RESERVED_31_30_MASK 0xC0000000U
14358 * DRAM DQ VREF Select for Rank3
14360 #undef DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL
14361 #undef DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT
14362 #undef DDR_PHY_DX2GCR6_DXDQVREFR3_MASK
14363 #define DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL 0x09090909
14364 #define DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT 24
14365 #define DDR_PHY_DX2GCR6_DXDQVREFR3_MASK 0x3F000000U
14368 * Reserved. Returns zeros on reads.
14370 #undef DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL
14371 #undef DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT
14372 #undef DDR_PHY_DX2GCR6_RESERVED_23_22_MASK
14373 #define DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL 0x09090909
14374 #define DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT 22
14375 #define DDR_PHY_DX2GCR6_RESERVED_23_22_MASK 0x00C00000U
14378 * DRAM DQ VREF Select for Rank2
14380 #undef DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL
14381 #undef DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT
14382 #undef DDR_PHY_DX2GCR6_DXDQVREFR2_MASK
14383 #define DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL 0x09090909
14384 #define DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT 16
14385 #define DDR_PHY_DX2GCR6_DXDQVREFR2_MASK 0x003F0000U
14388 * Reserved. Returns zeros on reads.
14390 #undef DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL
14391 #undef DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT
14392 #undef DDR_PHY_DX2GCR6_RESERVED_15_14_MASK
14393 #define DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL 0x09090909
14394 #define DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT 14
14395 #define DDR_PHY_DX2GCR6_RESERVED_15_14_MASK 0x0000C000U
14398 * DRAM DQ VREF Select for Rank1
14400 #undef DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL
14401 #undef DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT
14402 #undef DDR_PHY_DX2GCR6_DXDQVREFR1_MASK
14403 #define DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL 0x09090909
14404 #define DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT 8
14405 #define DDR_PHY_DX2GCR6_DXDQVREFR1_MASK 0x00003F00U
14408 * Reserved. Returns zeros on reads.
14410 #undef DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL
14411 #undef DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT
14412 #undef DDR_PHY_DX2GCR6_RESERVED_7_6_MASK
14413 #define DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL 0x09090909
14414 #define DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT 6
14415 #define DDR_PHY_DX2GCR6_RESERVED_7_6_MASK 0x000000C0U
14418 * DRAM DQ VREF Select for Rank0
14420 #undef DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL
14421 #undef DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT
14422 #undef DDR_PHY_DX2GCR6_DXDQVREFR0_MASK
14423 #define DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL 0x09090909
14424 #define DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT 0
14425 #define DDR_PHY_DX2GCR6_DXDQVREFR0_MASK 0x0000003FU
14428 * Calibration Bypass
14430 #undef DDR_PHY_DX3GCR0_CALBYP_DEFVAL
14431 #undef DDR_PHY_DX3GCR0_CALBYP_SHIFT
14432 #undef DDR_PHY_DX3GCR0_CALBYP_MASK
14433 #define DDR_PHY_DX3GCR0_CALBYP_DEFVAL 0x40200204
14434 #define DDR_PHY_DX3GCR0_CALBYP_SHIFT 31
14435 #define DDR_PHY_DX3GCR0_CALBYP_MASK 0x80000000U
14438 * Master Delay Line Enable
14440 #undef DDR_PHY_DX3GCR0_MDLEN_DEFVAL
14441 #undef DDR_PHY_DX3GCR0_MDLEN_SHIFT
14442 #undef DDR_PHY_DX3GCR0_MDLEN_MASK
14443 #define DDR_PHY_DX3GCR0_MDLEN_DEFVAL 0x40200204
14444 #define DDR_PHY_DX3GCR0_MDLEN_SHIFT 30
14445 #define DDR_PHY_DX3GCR0_MDLEN_MASK 0x40000000U
14448 * Configurable ODT(TE) Phase Shift
14450 #undef DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL
14451 #undef DDR_PHY_DX3GCR0_CODTSHFT_SHIFT
14452 #undef DDR_PHY_DX3GCR0_CODTSHFT_MASK
14453 #define DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL 0x40200204
14454 #define DDR_PHY_DX3GCR0_CODTSHFT_SHIFT 28
14455 #define DDR_PHY_DX3GCR0_CODTSHFT_MASK 0x30000000U
14458 * DQS Duty Cycle Correction
14460 #undef DDR_PHY_DX3GCR0_DQSDCC_DEFVAL
14461 #undef DDR_PHY_DX3GCR0_DQSDCC_SHIFT
14462 #undef DDR_PHY_DX3GCR0_DQSDCC_MASK
14463 #define DDR_PHY_DX3GCR0_DQSDCC_DEFVAL 0x40200204
14464 #define DDR_PHY_DX3GCR0_DQSDCC_SHIFT 24
14465 #define DDR_PHY_DX3GCR0_DQSDCC_MASK 0x0F000000U
14468 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
14469 * input for the respective bypte lane of the PHY
14471 #undef DDR_PHY_DX3GCR0_RDDLY_DEFVAL
14472 #undef DDR_PHY_DX3GCR0_RDDLY_SHIFT
14473 #undef DDR_PHY_DX3GCR0_RDDLY_MASK
14474 #define DDR_PHY_DX3GCR0_RDDLY_DEFVAL 0x40200204
14475 #define DDR_PHY_DX3GCR0_RDDLY_SHIFT 20
14476 #define DDR_PHY_DX3GCR0_RDDLY_MASK 0x00F00000U
14479 * Reserved. Return zeroes on reads.
14481 #undef DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL
14482 #undef DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT
14483 #undef DDR_PHY_DX3GCR0_RESERVED_19_14_MASK
14484 #define DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL 0x40200204
14485 #define DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT 14
14486 #define DDR_PHY_DX3GCR0_RESERVED_19_14_MASK 0x000FC000U
14489 * DQSNSE Power Down Receiver
14491 #undef DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL
14492 #undef DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT
14493 #undef DDR_PHY_DX3GCR0_DQSNSEPDR_MASK
14494 #define DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL 0x40200204
14495 #define DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT 13
14496 #define DDR_PHY_DX3GCR0_DQSNSEPDR_MASK 0x00002000U
14499 * DQSSE Power Down Receiver
14501 #undef DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL
14502 #undef DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT
14503 #undef DDR_PHY_DX3GCR0_DQSSEPDR_MASK
14504 #define DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL 0x40200204
14505 #define DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT 12
14506 #define DDR_PHY_DX3GCR0_DQSSEPDR_MASK 0x00001000U
14509 * RTT On Additive Latency
14511 #undef DDR_PHY_DX3GCR0_RTTOAL_DEFVAL
14512 #undef DDR_PHY_DX3GCR0_RTTOAL_SHIFT
14513 #undef DDR_PHY_DX3GCR0_RTTOAL_MASK
14514 #define DDR_PHY_DX3GCR0_RTTOAL_DEFVAL 0x40200204
14515 #define DDR_PHY_DX3GCR0_RTTOAL_SHIFT 11
14516 #define DDR_PHY_DX3GCR0_RTTOAL_MASK 0x00000800U
14521 #undef DDR_PHY_DX3GCR0_RTTOH_DEFVAL
14522 #undef DDR_PHY_DX3GCR0_RTTOH_SHIFT
14523 #undef DDR_PHY_DX3GCR0_RTTOH_MASK
14524 #define DDR_PHY_DX3GCR0_RTTOH_DEFVAL 0x40200204
14525 #define DDR_PHY_DX3GCR0_RTTOH_SHIFT 9
14526 #define DDR_PHY_DX3GCR0_RTTOH_MASK 0x00000600U
14529 * Configurable PDR Phase Shift
14531 #undef DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL
14532 #undef DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT
14533 #undef DDR_PHY_DX3GCR0_CPDRSHFT_MASK
14534 #define DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL 0x40200204
14535 #define DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT 7
14536 #define DDR_PHY_DX3GCR0_CPDRSHFT_MASK 0x00000180U
14541 #undef DDR_PHY_DX3GCR0_DQSRPD_DEFVAL
14542 #undef DDR_PHY_DX3GCR0_DQSRPD_SHIFT
14543 #undef DDR_PHY_DX3GCR0_DQSRPD_MASK
14544 #define DDR_PHY_DX3GCR0_DQSRPD_DEFVAL 0x40200204
14545 #define DDR_PHY_DX3GCR0_DQSRPD_SHIFT 6
14546 #define DDR_PHY_DX3GCR0_DQSRPD_MASK 0x00000040U
14549 * DQSG Power Down Receiver
14551 #undef DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL
14552 #undef DDR_PHY_DX3GCR0_DQSGPDR_SHIFT
14553 #undef DDR_PHY_DX3GCR0_DQSGPDR_MASK
14554 #define DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL 0x40200204
14555 #define DDR_PHY_DX3GCR0_DQSGPDR_SHIFT 5
14556 #define DDR_PHY_DX3GCR0_DQSGPDR_MASK 0x00000020U
14559 * Reserved. Return zeroes on reads.
14561 #undef DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL
14562 #undef DDR_PHY_DX3GCR0_RESERVED_4_SHIFT
14563 #undef DDR_PHY_DX3GCR0_RESERVED_4_MASK
14564 #define DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL 0x40200204
14565 #define DDR_PHY_DX3GCR0_RESERVED_4_SHIFT 4
14566 #define DDR_PHY_DX3GCR0_RESERVED_4_MASK 0x00000010U
14569 * DQSG On-Die Termination
14571 #undef DDR_PHY_DX3GCR0_DQSGODT_DEFVAL
14572 #undef DDR_PHY_DX3GCR0_DQSGODT_SHIFT
14573 #undef DDR_PHY_DX3GCR0_DQSGODT_MASK
14574 #define DDR_PHY_DX3GCR0_DQSGODT_DEFVAL 0x40200204
14575 #define DDR_PHY_DX3GCR0_DQSGODT_SHIFT 3
14576 #define DDR_PHY_DX3GCR0_DQSGODT_MASK 0x00000008U
14579 * DQSG Output Enable
14581 #undef DDR_PHY_DX3GCR0_DQSGOE_DEFVAL
14582 #undef DDR_PHY_DX3GCR0_DQSGOE_SHIFT
14583 #undef DDR_PHY_DX3GCR0_DQSGOE_MASK
14584 #define DDR_PHY_DX3GCR0_DQSGOE_DEFVAL 0x40200204
14585 #define DDR_PHY_DX3GCR0_DQSGOE_SHIFT 2
14586 #define DDR_PHY_DX3GCR0_DQSGOE_MASK 0x00000004U
14589 * Reserved. Return zeroes on reads.
14591 #undef DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL
14592 #undef DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT
14593 #undef DDR_PHY_DX3GCR0_RESERVED_1_0_MASK
14594 #define DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL 0x40200204
14595 #define DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT 0
14596 #define DDR_PHY_DX3GCR0_RESERVED_1_0_MASK 0x00000003U
14599 * Enables the PDR mode for DQ[7:0]
14601 #undef DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL
14602 #undef DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT
14603 #undef DDR_PHY_DX3GCR1_DXPDRMODE_MASK
14604 #define DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL 0x00007FFF
14605 #define DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT 16
14606 #define DDR_PHY_DX3GCR1_DXPDRMODE_MASK 0xFFFF0000U
14609 * Reserved. Returns zeroes on reads.
14611 #undef DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL
14612 #undef DDR_PHY_DX3GCR1_RESERVED_15_SHIFT
14613 #undef DDR_PHY_DX3GCR1_RESERVED_15_MASK
14614 #define DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL 0x00007FFF
14615 #define DDR_PHY_DX3GCR1_RESERVED_15_SHIFT 15
14616 #define DDR_PHY_DX3GCR1_RESERVED_15_MASK 0x00008000U
14619 * Select the delayed or non-delayed read data strobe #
14621 #undef DDR_PHY_DX3GCR1_QSNSEL_DEFVAL
14622 #undef DDR_PHY_DX3GCR1_QSNSEL_SHIFT
14623 #undef DDR_PHY_DX3GCR1_QSNSEL_MASK
14624 #define DDR_PHY_DX3GCR1_QSNSEL_DEFVAL 0x00007FFF
14625 #define DDR_PHY_DX3GCR1_QSNSEL_SHIFT 14
14626 #define DDR_PHY_DX3GCR1_QSNSEL_MASK 0x00004000U
14629 * Select the delayed or non-delayed read data strobe
14631 #undef DDR_PHY_DX3GCR1_QSSEL_DEFVAL
14632 #undef DDR_PHY_DX3GCR1_QSSEL_SHIFT
14633 #undef DDR_PHY_DX3GCR1_QSSEL_MASK
14634 #define DDR_PHY_DX3GCR1_QSSEL_DEFVAL 0x00007FFF
14635 #define DDR_PHY_DX3GCR1_QSSEL_SHIFT 13
14636 #define DDR_PHY_DX3GCR1_QSSEL_MASK 0x00002000U
14639 * Enables Read Data Strobe in a byte lane
14641 #undef DDR_PHY_DX3GCR1_OEEN_DEFVAL
14642 #undef DDR_PHY_DX3GCR1_OEEN_SHIFT
14643 #undef DDR_PHY_DX3GCR1_OEEN_MASK
14644 #define DDR_PHY_DX3GCR1_OEEN_DEFVAL 0x00007FFF
14645 #define DDR_PHY_DX3GCR1_OEEN_SHIFT 12
14646 #define DDR_PHY_DX3GCR1_OEEN_MASK 0x00001000U
14649 * Enables PDR in a byte lane
14651 #undef DDR_PHY_DX3GCR1_PDREN_DEFVAL
14652 #undef DDR_PHY_DX3GCR1_PDREN_SHIFT
14653 #undef DDR_PHY_DX3GCR1_PDREN_MASK
14654 #define DDR_PHY_DX3GCR1_PDREN_DEFVAL 0x00007FFF
14655 #define DDR_PHY_DX3GCR1_PDREN_SHIFT 11
14656 #define DDR_PHY_DX3GCR1_PDREN_MASK 0x00000800U
14659 * Enables ODT/TE in a byte lane
14661 #undef DDR_PHY_DX3GCR1_TEEN_DEFVAL
14662 #undef DDR_PHY_DX3GCR1_TEEN_SHIFT
14663 #undef DDR_PHY_DX3GCR1_TEEN_MASK
14664 #define DDR_PHY_DX3GCR1_TEEN_DEFVAL 0x00007FFF
14665 #define DDR_PHY_DX3GCR1_TEEN_SHIFT 10
14666 #define DDR_PHY_DX3GCR1_TEEN_MASK 0x00000400U
14669 * Enables Write Data strobe in a byte lane
14671 #undef DDR_PHY_DX3GCR1_DSEN_DEFVAL
14672 #undef DDR_PHY_DX3GCR1_DSEN_SHIFT
14673 #undef DDR_PHY_DX3GCR1_DSEN_MASK
14674 #define DDR_PHY_DX3GCR1_DSEN_DEFVAL 0x00007FFF
14675 #define DDR_PHY_DX3GCR1_DSEN_SHIFT 9
14676 #define DDR_PHY_DX3GCR1_DSEN_MASK 0x00000200U
14679 * Enables DM pin in a byte lane
14681 #undef DDR_PHY_DX3GCR1_DMEN_DEFVAL
14682 #undef DDR_PHY_DX3GCR1_DMEN_SHIFT
14683 #undef DDR_PHY_DX3GCR1_DMEN_MASK
14684 #define DDR_PHY_DX3GCR1_DMEN_DEFVAL 0x00007FFF
14685 #define DDR_PHY_DX3GCR1_DMEN_SHIFT 8
14686 #define DDR_PHY_DX3GCR1_DMEN_MASK 0x00000100U
14689 * Enables DQ corresponding to each bit in a byte
14691 #undef DDR_PHY_DX3GCR1_DQEN_DEFVAL
14692 #undef DDR_PHY_DX3GCR1_DQEN_SHIFT
14693 #undef DDR_PHY_DX3GCR1_DQEN_MASK
14694 #define DDR_PHY_DX3GCR1_DQEN_DEFVAL 0x00007FFF
14695 #define DDR_PHY_DX3GCR1_DQEN_SHIFT 0
14696 #define DDR_PHY_DX3GCR1_DQEN_MASK 0x000000FFU
14699 * Byte lane VREF IOM (Used only by D4MU IOs)
14701 #undef DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL
14702 #undef DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT
14703 #undef DDR_PHY_DX3GCR4_RESERVED_31_29_MASK
14704 #define DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL 0x0E00003C
14705 #define DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT 29
14706 #define DDR_PHY_DX3GCR4_RESERVED_31_29_MASK 0xE0000000U
14709 * Byte Lane VREF Pad Enable
14711 #undef DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL
14712 #undef DDR_PHY_DX3GCR4_DXREFPEN_SHIFT
14713 #undef DDR_PHY_DX3GCR4_DXREFPEN_MASK
14714 #define DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL 0x0E00003C
14715 #define DDR_PHY_DX3GCR4_DXREFPEN_SHIFT 28
14716 #define DDR_PHY_DX3GCR4_DXREFPEN_MASK 0x10000000U
14719 * Byte Lane Internal VREF Enable
14721 #undef DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL
14722 #undef DDR_PHY_DX3GCR4_DXREFEEN_SHIFT
14723 #undef DDR_PHY_DX3GCR4_DXREFEEN_MASK
14724 #define DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL 0x0E00003C
14725 #define DDR_PHY_DX3GCR4_DXREFEEN_SHIFT 26
14726 #define DDR_PHY_DX3GCR4_DXREFEEN_MASK 0x0C000000U
14729 * Byte Lane Single-End VREF Enable
14731 #undef DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL
14732 #undef DDR_PHY_DX3GCR4_DXREFSEN_SHIFT
14733 #undef DDR_PHY_DX3GCR4_DXREFSEN_MASK
14734 #define DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL 0x0E00003C
14735 #define DDR_PHY_DX3GCR4_DXREFSEN_SHIFT 25
14736 #define DDR_PHY_DX3GCR4_DXREFSEN_MASK 0x02000000U
14739 * Reserved. Returns zeros on reads.
14741 #undef DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL
14742 #undef DDR_PHY_DX3GCR4_RESERVED_24_SHIFT
14743 #undef DDR_PHY_DX3GCR4_RESERVED_24_MASK
14744 #define DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL 0x0E00003C
14745 #define DDR_PHY_DX3GCR4_RESERVED_24_SHIFT 24
14746 #define DDR_PHY_DX3GCR4_RESERVED_24_MASK 0x01000000U
14749 * External VREF generator REFSEL range select
14751 #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL
14752 #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT
14753 #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK
14754 #define DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C
14755 #define DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT 23
14756 #define DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK 0x00800000U
14759 * Byte Lane External VREF Select
14761 #undef DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL
14762 #undef DDR_PHY_DX3GCR4_DXREFESEL_SHIFT
14763 #undef DDR_PHY_DX3GCR4_DXREFESEL_MASK
14764 #define DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL 0x0E00003C
14765 #define DDR_PHY_DX3GCR4_DXREFESEL_SHIFT 16
14766 #define DDR_PHY_DX3GCR4_DXREFESEL_MASK 0x007F0000U
14769 * Single ended VREF generator REFSEL range select
14771 #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL
14772 #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT
14773 #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK
14774 #define DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C
14775 #define DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT 15
14776 #define DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK 0x00008000U
14779 * Byte Lane Single-End VREF Select
14781 #undef DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL
14782 #undef DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT
14783 #undef DDR_PHY_DX3GCR4_DXREFSSEL_MASK
14784 #define DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL 0x0E00003C
14785 #define DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT 8
14786 #define DDR_PHY_DX3GCR4_DXREFSSEL_MASK 0x00007F00U
14789 * Reserved. Returns zeros on reads.
14791 #undef DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL
14792 #undef DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT
14793 #undef DDR_PHY_DX3GCR4_RESERVED_7_6_MASK
14794 #define DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL 0x0E00003C
14795 #define DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT 6
14796 #define DDR_PHY_DX3GCR4_RESERVED_7_6_MASK 0x000000C0U
14799 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
14801 #undef DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL
14802 #undef DDR_PHY_DX3GCR4_DXREFIEN_SHIFT
14803 #undef DDR_PHY_DX3GCR4_DXREFIEN_MASK
14804 #define DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL 0x0E00003C
14805 #define DDR_PHY_DX3GCR4_DXREFIEN_SHIFT 2
14806 #define DDR_PHY_DX3GCR4_DXREFIEN_MASK 0x0000003CU
14809 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
14811 #undef DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL
14812 #undef DDR_PHY_DX3GCR4_DXREFIMON_SHIFT
14813 #undef DDR_PHY_DX3GCR4_DXREFIMON_MASK
14814 #define DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL 0x0E00003C
14815 #define DDR_PHY_DX3GCR4_DXREFIMON_SHIFT 0
14816 #define DDR_PHY_DX3GCR4_DXREFIMON_MASK 0x00000003U
14819 * Reserved. Returns zeros on reads.
14821 #undef DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL
14822 #undef DDR_PHY_DX3GCR5_RESERVED_31_SHIFT
14823 #undef DDR_PHY_DX3GCR5_RESERVED_31_MASK
14824 #define DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL 0x09090909
14825 #define DDR_PHY_DX3GCR5_RESERVED_31_SHIFT 31
14826 #define DDR_PHY_DX3GCR5_RESERVED_31_MASK 0x80000000U
14829 * Byte Lane internal VREF Select for Rank 3
14831 #undef DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL
14832 #undef DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT
14833 #undef DDR_PHY_DX3GCR5_DXREFISELR3_MASK
14834 #define DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL 0x09090909
14835 #define DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT 24
14836 #define DDR_PHY_DX3GCR5_DXREFISELR3_MASK 0x7F000000U
14839 * Reserved. Returns zeros on reads.
14841 #undef DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL
14842 #undef DDR_PHY_DX3GCR5_RESERVED_23_SHIFT
14843 #undef DDR_PHY_DX3GCR5_RESERVED_23_MASK
14844 #define DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL 0x09090909
14845 #define DDR_PHY_DX3GCR5_RESERVED_23_SHIFT 23
14846 #define DDR_PHY_DX3GCR5_RESERVED_23_MASK 0x00800000U
14849 * Byte Lane internal VREF Select for Rank 2
14851 #undef DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL
14852 #undef DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT
14853 #undef DDR_PHY_DX3GCR5_DXREFISELR2_MASK
14854 #define DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL 0x09090909
14855 #define DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT 16
14856 #define DDR_PHY_DX3GCR5_DXREFISELR2_MASK 0x007F0000U
14859 * Reserved. Returns zeros on reads.
14861 #undef DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL
14862 #undef DDR_PHY_DX3GCR5_RESERVED_15_SHIFT
14863 #undef DDR_PHY_DX3GCR5_RESERVED_15_MASK
14864 #define DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL 0x09090909
14865 #define DDR_PHY_DX3GCR5_RESERVED_15_SHIFT 15
14866 #define DDR_PHY_DX3GCR5_RESERVED_15_MASK 0x00008000U
14869 * Byte Lane internal VREF Select for Rank 1
14871 #undef DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL
14872 #undef DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT
14873 #undef DDR_PHY_DX3GCR5_DXREFISELR1_MASK
14874 #define DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL 0x09090909
14875 #define DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT 8
14876 #define DDR_PHY_DX3GCR5_DXREFISELR1_MASK 0x00007F00U
14879 * Reserved. Returns zeros on reads.
14881 #undef DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL
14882 #undef DDR_PHY_DX3GCR5_RESERVED_7_SHIFT
14883 #undef DDR_PHY_DX3GCR5_RESERVED_7_MASK
14884 #define DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL 0x09090909
14885 #define DDR_PHY_DX3GCR5_RESERVED_7_SHIFT 7
14886 #define DDR_PHY_DX3GCR5_RESERVED_7_MASK 0x00000080U
14889 * Byte Lane internal VREF Select for Rank 0
14891 #undef DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL
14892 #undef DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT
14893 #undef DDR_PHY_DX3GCR5_DXREFISELR0_MASK
14894 #define DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL 0x09090909
14895 #define DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT 0
14896 #define DDR_PHY_DX3GCR5_DXREFISELR0_MASK 0x0000007FU
14899 * Reserved. Returns zeros on reads.
14901 #undef DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL
14902 #undef DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT
14903 #undef DDR_PHY_DX3GCR6_RESERVED_31_30_MASK
14904 #define DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL 0x09090909
14905 #define DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT 30
14906 #define DDR_PHY_DX3GCR6_RESERVED_31_30_MASK 0xC0000000U
14909 * DRAM DQ VREF Select for Rank3
14911 #undef DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL
14912 #undef DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT
14913 #undef DDR_PHY_DX3GCR6_DXDQVREFR3_MASK
14914 #define DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL 0x09090909
14915 #define DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT 24
14916 #define DDR_PHY_DX3GCR6_DXDQVREFR3_MASK 0x3F000000U
14919 * Reserved. Returns zeros on reads.
14921 #undef DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL
14922 #undef DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT
14923 #undef DDR_PHY_DX3GCR6_RESERVED_23_22_MASK
14924 #define DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL 0x09090909
14925 #define DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT 22
14926 #define DDR_PHY_DX3GCR6_RESERVED_23_22_MASK 0x00C00000U
14929 * DRAM DQ VREF Select for Rank2
14931 #undef DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL
14932 #undef DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT
14933 #undef DDR_PHY_DX3GCR6_DXDQVREFR2_MASK
14934 #define DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL 0x09090909
14935 #define DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT 16
14936 #define DDR_PHY_DX3GCR6_DXDQVREFR2_MASK 0x003F0000U
14939 * Reserved. Returns zeros on reads.
14941 #undef DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL
14942 #undef DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT
14943 #undef DDR_PHY_DX3GCR6_RESERVED_15_14_MASK
14944 #define DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL 0x09090909
14945 #define DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT 14
14946 #define DDR_PHY_DX3GCR6_RESERVED_15_14_MASK 0x0000C000U
14949 * DRAM DQ VREF Select for Rank1
14951 #undef DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL
14952 #undef DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT
14953 #undef DDR_PHY_DX3GCR6_DXDQVREFR1_MASK
14954 #define DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL 0x09090909
14955 #define DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT 8
14956 #define DDR_PHY_DX3GCR6_DXDQVREFR1_MASK 0x00003F00U
14959 * Reserved. Returns zeros on reads.
14961 #undef DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL
14962 #undef DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT
14963 #undef DDR_PHY_DX3GCR6_RESERVED_7_6_MASK
14964 #define DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL 0x09090909
14965 #define DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT 6
14966 #define DDR_PHY_DX3GCR6_RESERVED_7_6_MASK 0x000000C0U
14969 * DRAM DQ VREF Select for Rank0
14971 #undef DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL
14972 #undef DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT
14973 #undef DDR_PHY_DX3GCR6_DXDQVREFR0_MASK
14974 #define DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL 0x09090909
14975 #define DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT 0
14976 #define DDR_PHY_DX3GCR6_DXDQVREFR0_MASK 0x0000003FU
14979 * Calibration Bypass
14981 #undef DDR_PHY_DX4GCR0_CALBYP_DEFVAL
14982 #undef DDR_PHY_DX4GCR0_CALBYP_SHIFT
14983 #undef DDR_PHY_DX4GCR0_CALBYP_MASK
14984 #define DDR_PHY_DX4GCR0_CALBYP_DEFVAL 0x40200204
14985 #define DDR_PHY_DX4GCR0_CALBYP_SHIFT 31
14986 #define DDR_PHY_DX4GCR0_CALBYP_MASK 0x80000000U
14989 * Master Delay Line Enable
14991 #undef DDR_PHY_DX4GCR0_MDLEN_DEFVAL
14992 #undef DDR_PHY_DX4GCR0_MDLEN_SHIFT
14993 #undef DDR_PHY_DX4GCR0_MDLEN_MASK
14994 #define DDR_PHY_DX4GCR0_MDLEN_DEFVAL 0x40200204
14995 #define DDR_PHY_DX4GCR0_MDLEN_SHIFT 30
14996 #define DDR_PHY_DX4GCR0_MDLEN_MASK 0x40000000U
14999 * Configurable ODT(TE) Phase Shift
15001 #undef DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL
15002 #undef DDR_PHY_DX4GCR0_CODTSHFT_SHIFT
15003 #undef DDR_PHY_DX4GCR0_CODTSHFT_MASK
15004 #define DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL 0x40200204
15005 #define DDR_PHY_DX4GCR0_CODTSHFT_SHIFT 28
15006 #define DDR_PHY_DX4GCR0_CODTSHFT_MASK 0x30000000U
15009 * DQS Duty Cycle Correction
15011 #undef DDR_PHY_DX4GCR0_DQSDCC_DEFVAL
15012 #undef DDR_PHY_DX4GCR0_DQSDCC_SHIFT
15013 #undef DDR_PHY_DX4GCR0_DQSDCC_MASK
15014 #define DDR_PHY_DX4GCR0_DQSDCC_DEFVAL 0x40200204
15015 #define DDR_PHY_DX4GCR0_DQSDCC_SHIFT 24
15016 #define DDR_PHY_DX4GCR0_DQSDCC_MASK 0x0F000000U
15019 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
15020 * input for the respective bypte lane of the PHY
15022 #undef DDR_PHY_DX4GCR0_RDDLY_DEFVAL
15023 #undef DDR_PHY_DX4GCR0_RDDLY_SHIFT
15024 #undef DDR_PHY_DX4GCR0_RDDLY_MASK
15025 #define DDR_PHY_DX4GCR0_RDDLY_DEFVAL 0x40200204
15026 #define DDR_PHY_DX4GCR0_RDDLY_SHIFT 20
15027 #define DDR_PHY_DX4GCR0_RDDLY_MASK 0x00F00000U
15030 * Reserved. Return zeroes on reads.
15032 #undef DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL
15033 #undef DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT
15034 #undef DDR_PHY_DX4GCR0_RESERVED_19_14_MASK
15035 #define DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL 0x40200204
15036 #define DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT 14
15037 #define DDR_PHY_DX4GCR0_RESERVED_19_14_MASK 0x000FC000U
15040 * DQSNSE Power Down Receiver
15042 #undef DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL
15043 #undef DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT
15044 #undef DDR_PHY_DX4GCR0_DQSNSEPDR_MASK
15045 #define DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL 0x40200204
15046 #define DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT 13
15047 #define DDR_PHY_DX4GCR0_DQSNSEPDR_MASK 0x00002000U
15050 * DQSSE Power Down Receiver
15052 #undef DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL
15053 #undef DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT
15054 #undef DDR_PHY_DX4GCR0_DQSSEPDR_MASK
15055 #define DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL 0x40200204
15056 #define DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT 12
15057 #define DDR_PHY_DX4GCR0_DQSSEPDR_MASK 0x00001000U
15060 * RTT On Additive Latency
15062 #undef DDR_PHY_DX4GCR0_RTTOAL_DEFVAL
15063 #undef DDR_PHY_DX4GCR0_RTTOAL_SHIFT
15064 #undef DDR_PHY_DX4GCR0_RTTOAL_MASK
15065 #define DDR_PHY_DX4GCR0_RTTOAL_DEFVAL 0x40200204
15066 #define DDR_PHY_DX4GCR0_RTTOAL_SHIFT 11
15067 #define DDR_PHY_DX4GCR0_RTTOAL_MASK 0x00000800U
15072 #undef DDR_PHY_DX4GCR0_RTTOH_DEFVAL
15073 #undef DDR_PHY_DX4GCR0_RTTOH_SHIFT
15074 #undef DDR_PHY_DX4GCR0_RTTOH_MASK
15075 #define DDR_PHY_DX4GCR0_RTTOH_DEFVAL 0x40200204
15076 #define DDR_PHY_DX4GCR0_RTTOH_SHIFT 9
15077 #define DDR_PHY_DX4GCR0_RTTOH_MASK 0x00000600U
15080 * Configurable PDR Phase Shift
15082 #undef DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL
15083 #undef DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT
15084 #undef DDR_PHY_DX4GCR0_CPDRSHFT_MASK
15085 #define DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL 0x40200204
15086 #define DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT 7
15087 #define DDR_PHY_DX4GCR0_CPDRSHFT_MASK 0x00000180U
15092 #undef DDR_PHY_DX4GCR0_DQSRPD_DEFVAL
15093 #undef DDR_PHY_DX4GCR0_DQSRPD_SHIFT
15094 #undef DDR_PHY_DX4GCR0_DQSRPD_MASK
15095 #define DDR_PHY_DX4GCR0_DQSRPD_DEFVAL 0x40200204
15096 #define DDR_PHY_DX4GCR0_DQSRPD_SHIFT 6
15097 #define DDR_PHY_DX4GCR0_DQSRPD_MASK 0x00000040U
15100 * DQSG Power Down Receiver
15102 #undef DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL
15103 #undef DDR_PHY_DX4GCR0_DQSGPDR_SHIFT
15104 #undef DDR_PHY_DX4GCR0_DQSGPDR_MASK
15105 #define DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL 0x40200204
15106 #define DDR_PHY_DX4GCR0_DQSGPDR_SHIFT 5
15107 #define DDR_PHY_DX4GCR0_DQSGPDR_MASK 0x00000020U
15110 * Reserved. Return zeroes on reads.
15112 #undef DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL
15113 #undef DDR_PHY_DX4GCR0_RESERVED_4_SHIFT
15114 #undef DDR_PHY_DX4GCR0_RESERVED_4_MASK
15115 #define DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL 0x40200204
15116 #define DDR_PHY_DX4GCR0_RESERVED_4_SHIFT 4
15117 #define DDR_PHY_DX4GCR0_RESERVED_4_MASK 0x00000010U
15120 * DQSG On-Die Termination
15122 #undef DDR_PHY_DX4GCR0_DQSGODT_DEFVAL
15123 #undef DDR_PHY_DX4GCR0_DQSGODT_SHIFT
15124 #undef DDR_PHY_DX4GCR0_DQSGODT_MASK
15125 #define DDR_PHY_DX4GCR0_DQSGODT_DEFVAL 0x40200204
15126 #define DDR_PHY_DX4GCR0_DQSGODT_SHIFT 3
15127 #define DDR_PHY_DX4GCR0_DQSGODT_MASK 0x00000008U
15130 * DQSG Output Enable
15132 #undef DDR_PHY_DX4GCR0_DQSGOE_DEFVAL
15133 #undef DDR_PHY_DX4GCR0_DQSGOE_SHIFT
15134 #undef DDR_PHY_DX4GCR0_DQSGOE_MASK
15135 #define DDR_PHY_DX4GCR0_DQSGOE_DEFVAL 0x40200204
15136 #define DDR_PHY_DX4GCR0_DQSGOE_SHIFT 2
15137 #define DDR_PHY_DX4GCR0_DQSGOE_MASK 0x00000004U
15140 * Reserved. Return zeroes on reads.
15142 #undef DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL
15143 #undef DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT
15144 #undef DDR_PHY_DX4GCR0_RESERVED_1_0_MASK
15145 #define DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL 0x40200204
15146 #define DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT 0
15147 #define DDR_PHY_DX4GCR0_RESERVED_1_0_MASK 0x00000003U
15150 * Enables the PDR mode for DQ[7:0]
15152 #undef DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL
15153 #undef DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT
15154 #undef DDR_PHY_DX4GCR1_DXPDRMODE_MASK
15155 #define DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL 0x00007FFF
15156 #define DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT 16
15157 #define DDR_PHY_DX4GCR1_DXPDRMODE_MASK 0xFFFF0000U
15160 * Reserved. Returns zeroes on reads.
15162 #undef DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL
15163 #undef DDR_PHY_DX4GCR1_RESERVED_15_SHIFT
15164 #undef DDR_PHY_DX4GCR1_RESERVED_15_MASK
15165 #define DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL 0x00007FFF
15166 #define DDR_PHY_DX4GCR1_RESERVED_15_SHIFT 15
15167 #define DDR_PHY_DX4GCR1_RESERVED_15_MASK 0x00008000U
15170 * Select the delayed or non-delayed read data strobe #
15172 #undef DDR_PHY_DX4GCR1_QSNSEL_DEFVAL
15173 #undef DDR_PHY_DX4GCR1_QSNSEL_SHIFT
15174 #undef DDR_PHY_DX4GCR1_QSNSEL_MASK
15175 #define DDR_PHY_DX4GCR1_QSNSEL_DEFVAL 0x00007FFF
15176 #define DDR_PHY_DX4GCR1_QSNSEL_SHIFT 14
15177 #define DDR_PHY_DX4GCR1_QSNSEL_MASK 0x00004000U
15180 * Select the delayed or non-delayed read data strobe
15182 #undef DDR_PHY_DX4GCR1_QSSEL_DEFVAL
15183 #undef DDR_PHY_DX4GCR1_QSSEL_SHIFT
15184 #undef DDR_PHY_DX4GCR1_QSSEL_MASK
15185 #define DDR_PHY_DX4GCR1_QSSEL_DEFVAL 0x00007FFF
15186 #define DDR_PHY_DX4GCR1_QSSEL_SHIFT 13
15187 #define DDR_PHY_DX4GCR1_QSSEL_MASK 0x00002000U
15190 * Enables Read Data Strobe in a byte lane
15192 #undef DDR_PHY_DX4GCR1_OEEN_DEFVAL
15193 #undef DDR_PHY_DX4GCR1_OEEN_SHIFT
15194 #undef DDR_PHY_DX4GCR1_OEEN_MASK
15195 #define DDR_PHY_DX4GCR1_OEEN_DEFVAL 0x00007FFF
15196 #define DDR_PHY_DX4GCR1_OEEN_SHIFT 12
15197 #define DDR_PHY_DX4GCR1_OEEN_MASK 0x00001000U
15200 * Enables PDR in a byte lane
15202 #undef DDR_PHY_DX4GCR1_PDREN_DEFVAL
15203 #undef DDR_PHY_DX4GCR1_PDREN_SHIFT
15204 #undef DDR_PHY_DX4GCR1_PDREN_MASK
15205 #define DDR_PHY_DX4GCR1_PDREN_DEFVAL 0x00007FFF
15206 #define DDR_PHY_DX4GCR1_PDREN_SHIFT 11
15207 #define DDR_PHY_DX4GCR1_PDREN_MASK 0x00000800U
15210 * Enables ODT/TE in a byte lane
15212 #undef DDR_PHY_DX4GCR1_TEEN_DEFVAL
15213 #undef DDR_PHY_DX4GCR1_TEEN_SHIFT
15214 #undef DDR_PHY_DX4GCR1_TEEN_MASK
15215 #define DDR_PHY_DX4GCR1_TEEN_DEFVAL 0x00007FFF
15216 #define DDR_PHY_DX4GCR1_TEEN_SHIFT 10
15217 #define DDR_PHY_DX4GCR1_TEEN_MASK 0x00000400U
15220 * Enables Write Data strobe in a byte lane
15222 #undef DDR_PHY_DX4GCR1_DSEN_DEFVAL
15223 #undef DDR_PHY_DX4GCR1_DSEN_SHIFT
15224 #undef DDR_PHY_DX4GCR1_DSEN_MASK
15225 #define DDR_PHY_DX4GCR1_DSEN_DEFVAL 0x00007FFF
15226 #define DDR_PHY_DX4GCR1_DSEN_SHIFT 9
15227 #define DDR_PHY_DX4GCR1_DSEN_MASK 0x00000200U
15230 * Enables DM pin in a byte lane
15232 #undef DDR_PHY_DX4GCR1_DMEN_DEFVAL
15233 #undef DDR_PHY_DX4GCR1_DMEN_SHIFT
15234 #undef DDR_PHY_DX4GCR1_DMEN_MASK
15235 #define DDR_PHY_DX4GCR1_DMEN_DEFVAL 0x00007FFF
15236 #define DDR_PHY_DX4GCR1_DMEN_SHIFT 8
15237 #define DDR_PHY_DX4GCR1_DMEN_MASK 0x00000100U
15240 * Enables DQ corresponding to each bit in a byte
15242 #undef DDR_PHY_DX4GCR1_DQEN_DEFVAL
15243 #undef DDR_PHY_DX4GCR1_DQEN_SHIFT
15244 #undef DDR_PHY_DX4GCR1_DQEN_MASK
15245 #define DDR_PHY_DX4GCR1_DQEN_DEFVAL 0x00007FFF
15246 #define DDR_PHY_DX4GCR1_DQEN_SHIFT 0
15247 #define DDR_PHY_DX4GCR1_DQEN_MASK 0x000000FFU
15250 * Byte lane VREF IOM (Used only by D4MU IOs)
15252 #undef DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL
15253 #undef DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT
15254 #undef DDR_PHY_DX4GCR4_RESERVED_31_29_MASK
15255 #define DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL 0x0E00003C
15256 #define DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT 29
15257 #define DDR_PHY_DX4GCR4_RESERVED_31_29_MASK 0xE0000000U
15260 * Byte Lane VREF Pad Enable
15262 #undef DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL
15263 #undef DDR_PHY_DX4GCR4_DXREFPEN_SHIFT
15264 #undef DDR_PHY_DX4GCR4_DXREFPEN_MASK
15265 #define DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL 0x0E00003C
15266 #define DDR_PHY_DX4GCR4_DXREFPEN_SHIFT 28
15267 #define DDR_PHY_DX4GCR4_DXREFPEN_MASK 0x10000000U
15270 * Byte Lane Internal VREF Enable
15272 #undef DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL
15273 #undef DDR_PHY_DX4GCR4_DXREFEEN_SHIFT
15274 #undef DDR_PHY_DX4GCR4_DXREFEEN_MASK
15275 #define DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL 0x0E00003C
15276 #define DDR_PHY_DX4GCR4_DXREFEEN_SHIFT 26
15277 #define DDR_PHY_DX4GCR4_DXREFEEN_MASK 0x0C000000U
15280 * Byte Lane Single-End VREF Enable
15282 #undef DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL
15283 #undef DDR_PHY_DX4GCR4_DXREFSEN_SHIFT
15284 #undef DDR_PHY_DX4GCR4_DXREFSEN_MASK
15285 #define DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL 0x0E00003C
15286 #define DDR_PHY_DX4GCR4_DXREFSEN_SHIFT 25
15287 #define DDR_PHY_DX4GCR4_DXREFSEN_MASK 0x02000000U
15290 * Reserved. Returns zeros on reads.
15292 #undef DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL
15293 #undef DDR_PHY_DX4GCR4_RESERVED_24_SHIFT
15294 #undef DDR_PHY_DX4GCR4_RESERVED_24_MASK
15295 #define DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL 0x0E00003C
15296 #define DDR_PHY_DX4GCR4_RESERVED_24_SHIFT 24
15297 #define DDR_PHY_DX4GCR4_RESERVED_24_MASK 0x01000000U
15300 * External VREF generator REFSEL range select
15302 #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL
15303 #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT
15304 #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK
15305 #define DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C
15306 #define DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT 23
15307 #define DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK 0x00800000U
15310 * Byte Lane External VREF Select
15312 #undef DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL
15313 #undef DDR_PHY_DX4GCR4_DXREFESEL_SHIFT
15314 #undef DDR_PHY_DX4GCR4_DXREFESEL_MASK
15315 #define DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL 0x0E00003C
15316 #define DDR_PHY_DX4GCR4_DXREFESEL_SHIFT 16
15317 #define DDR_PHY_DX4GCR4_DXREFESEL_MASK 0x007F0000U
15320 * Single ended VREF generator REFSEL range select
15322 #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL
15323 #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT
15324 #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK
15325 #define DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C
15326 #define DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT 15
15327 #define DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK 0x00008000U
15330 * Byte Lane Single-End VREF Select
15332 #undef DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL
15333 #undef DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT
15334 #undef DDR_PHY_DX4GCR4_DXREFSSEL_MASK
15335 #define DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL 0x0E00003C
15336 #define DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT 8
15337 #define DDR_PHY_DX4GCR4_DXREFSSEL_MASK 0x00007F00U
15340 * Reserved. Returns zeros on reads.
15342 #undef DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL
15343 #undef DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT
15344 #undef DDR_PHY_DX4GCR4_RESERVED_7_6_MASK
15345 #define DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL 0x0E00003C
15346 #define DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT 6
15347 #define DDR_PHY_DX4GCR4_RESERVED_7_6_MASK 0x000000C0U
15350 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
15352 #undef DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL
15353 #undef DDR_PHY_DX4GCR4_DXREFIEN_SHIFT
15354 #undef DDR_PHY_DX4GCR4_DXREFIEN_MASK
15355 #define DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL 0x0E00003C
15356 #define DDR_PHY_DX4GCR4_DXREFIEN_SHIFT 2
15357 #define DDR_PHY_DX4GCR4_DXREFIEN_MASK 0x0000003CU
15360 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
15362 #undef DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL
15363 #undef DDR_PHY_DX4GCR4_DXREFIMON_SHIFT
15364 #undef DDR_PHY_DX4GCR4_DXREFIMON_MASK
15365 #define DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL 0x0E00003C
15366 #define DDR_PHY_DX4GCR4_DXREFIMON_SHIFT 0
15367 #define DDR_PHY_DX4GCR4_DXREFIMON_MASK 0x00000003U
15370 * Reserved. Returns zeros on reads.
15372 #undef DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL
15373 #undef DDR_PHY_DX4GCR5_RESERVED_31_SHIFT
15374 #undef DDR_PHY_DX4GCR5_RESERVED_31_MASK
15375 #define DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL 0x09090909
15376 #define DDR_PHY_DX4GCR5_RESERVED_31_SHIFT 31
15377 #define DDR_PHY_DX4GCR5_RESERVED_31_MASK 0x80000000U
15380 * Byte Lane internal VREF Select for Rank 3
15382 #undef DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL
15383 #undef DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT
15384 #undef DDR_PHY_DX4GCR5_DXREFISELR3_MASK
15385 #define DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL 0x09090909
15386 #define DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT 24
15387 #define DDR_PHY_DX4GCR5_DXREFISELR3_MASK 0x7F000000U
15390 * Reserved. Returns zeros on reads.
15392 #undef DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL
15393 #undef DDR_PHY_DX4GCR5_RESERVED_23_SHIFT
15394 #undef DDR_PHY_DX4GCR5_RESERVED_23_MASK
15395 #define DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL 0x09090909
15396 #define DDR_PHY_DX4GCR5_RESERVED_23_SHIFT 23
15397 #define DDR_PHY_DX4GCR5_RESERVED_23_MASK 0x00800000U
15400 * Byte Lane internal VREF Select for Rank 2
15402 #undef DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL
15403 #undef DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT
15404 #undef DDR_PHY_DX4GCR5_DXREFISELR2_MASK
15405 #define DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL 0x09090909
15406 #define DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT 16
15407 #define DDR_PHY_DX4GCR5_DXREFISELR2_MASK 0x007F0000U
15410 * Reserved. Returns zeros on reads.
15412 #undef DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL
15413 #undef DDR_PHY_DX4GCR5_RESERVED_15_SHIFT
15414 #undef DDR_PHY_DX4GCR5_RESERVED_15_MASK
15415 #define DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL 0x09090909
15416 #define DDR_PHY_DX4GCR5_RESERVED_15_SHIFT 15
15417 #define DDR_PHY_DX4GCR5_RESERVED_15_MASK 0x00008000U
15420 * Byte Lane internal VREF Select for Rank 1
15422 #undef DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL
15423 #undef DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT
15424 #undef DDR_PHY_DX4GCR5_DXREFISELR1_MASK
15425 #define DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL 0x09090909
15426 #define DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT 8
15427 #define DDR_PHY_DX4GCR5_DXREFISELR1_MASK 0x00007F00U
15430 * Reserved. Returns zeros on reads.
15432 #undef DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL
15433 #undef DDR_PHY_DX4GCR5_RESERVED_7_SHIFT
15434 #undef DDR_PHY_DX4GCR5_RESERVED_7_MASK
15435 #define DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL 0x09090909
15436 #define DDR_PHY_DX4GCR5_RESERVED_7_SHIFT 7
15437 #define DDR_PHY_DX4GCR5_RESERVED_7_MASK 0x00000080U
15440 * Byte Lane internal VREF Select for Rank 0
15442 #undef DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL
15443 #undef DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT
15444 #undef DDR_PHY_DX4GCR5_DXREFISELR0_MASK
15445 #define DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL 0x09090909
15446 #define DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT 0
15447 #define DDR_PHY_DX4GCR5_DXREFISELR0_MASK 0x0000007FU
15450 * Reserved. Returns zeros on reads.
15452 #undef DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL
15453 #undef DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT
15454 #undef DDR_PHY_DX4GCR6_RESERVED_31_30_MASK
15455 #define DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL 0x09090909
15456 #define DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT 30
15457 #define DDR_PHY_DX4GCR6_RESERVED_31_30_MASK 0xC0000000U
15460 * DRAM DQ VREF Select for Rank3
15462 #undef DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL
15463 #undef DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT
15464 #undef DDR_PHY_DX4GCR6_DXDQVREFR3_MASK
15465 #define DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL 0x09090909
15466 #define DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT 24
15467 #define DDR_PHY_DX4GCR6_DXDQVREFR3_MASK 0x3F000000U
15470 * Reserved. Returns zeros on reads.
15472 #undef DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL
15473 #undef DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT
15474 #undef DDR_PHY_DX4GCR6_RESERVED_23_22_MASK
15475 #define DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL 0x09090909
15476 #define DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT 22
15477 #define DDR_PHY_DX4GCR6_RESERVED_23_22_MASK 0x00C00000U
15480 * DRAM DQ VREF Select for Rank2
15482 #undef DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL
15483 #undef DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT
15484 #undef DDR_PHY_DX4GCR6_DXDQVREFR2_MASK
15485 #define DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL 0x09090909
15486 #define DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT 16
15487 #define DDR_PHY_DX4GCR6_DXDQVREFR2_MASK 0x003F0000U
15490 * Reserved. Returns zeros on reads.
15492 #undef DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL
15493 #undef DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT
15494 #undef DDR_PHY_DX4GCR6_RESERVED_15_14_MASK
15495 #define DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL 0x09090909
15496 #define DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT 14
15497 #define DDR_PHY_DX4GCR6_RESERVED_15_14_MASK 0x0000C000U
15500 * DRAM DQ VREF Select for Rank1
15502 #undef DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL
15503 #undef DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT
15504 #undef DDR_PHY_DX4GCR6_DXDQVREFR1_MASK
15505 #define DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL 0x09090909
15506 #define DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT 8
15507 #define DDR_PHY_DX4GCR6_DXDQVREFR1_MASK 0x00003F00U
15510 * Reserved. Returns zeros on reads.
15512 #undef DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL
15513 #undef DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT
15514 #undef DDR_PHY_DX4GCR6_RESERVED_7_6_MASK
15515 #define DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL 0x09090909
15516 #define DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT 6
15517 #define DDR_PHY_DX4GCR6_RESERVED_7_6_MASK 0x000000C0U
15520 * DRAM DQ VREF Select for Rank0
15522 #undef DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL
15523 #undef DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT
15524 #undef DDR_PHY_DX4GCR6_DXDQVREFR0_MASK
15525 #define DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL 0x09090909
15526 #define DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT 0
15527 #define DDR_PHY_DX4GCR6_DXDQVREFR0_MASK 0x0000003FU
15530 * Calibration Bypass
15532 #undef DDR_PHY_DX5GCR0_CALBYP_DEFVAL
15533 #undef DDR_PHY_DX5GCR0_CALBYP_SHIFT
15534 #undef DDR_PHY_DX5GCR0_CALBYP_MASK
15535 #define DDR_PHY_DX5GCR0_CALBYP_DEFVAL 0x40200204
15536 #define DDR_PHY_DX5GCR0_CALBYP_SHIFT 31
15537 #define DDR_PHY_DX5GCR0_CALBYP_MASK 0x80000000U
15540 * Master Delay Line Enable
15542 #undef DDR_PHY_DX5GCR0_MDLEN_DEFVAL
15543 #undef DDR_PHY_DX5GCR0_MDLEN_SHIFT
15544 #undef DDR_PHY_DX5GCR0_MDLEN_MASK
15545 #define DDR_PHY_DX5GCR0_MDLEN_DEFVAL 0x40200204
15546 #define DDR_PHY_DX5GCR0_MDLEN_SHIFT 30
15547 #define DDR_PHY_DX5GCR0_MDLEN_MASK 0x40000000U
15550 * Configurable ODT(TE) Phase Shift
15552 #undef DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL
15553 #undef DDR_PHY_DX5GCR0_CODTSHFT_SHIFT
15554 #undef DDR_PHY_DX5GCR0_CODTSHFT_MASK
15555 #define DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL 0x40200204
15556 #define DDR_PHY_DX5GCR0_CODTSHFT_SHIFT 28
15557 #define DDR_PHY_DX5GCR0_CODTSHFT_MASK 0x30000000U
15560 * DQS Duty Cycle Correction
15562 #undef DDR_PHY_DX5GCR0_DQSDCC_DEFVAL
15563 #undef DDR_PHY_DX5GCR0_DQSDCC_SHIFT
15564 #undef DDR_PHY_DX5GCR0_DQSDCC_MASK
15565 #define DDR_PHY_DX5GCR0_DQSDCC_DEFVAL 0x40200204
15566 #define DDR_PHY_DX5GCR0_DQSDCC_SHIFT 24
15567 #define DDR_PHY_DX5GCR0_DQSDCC_MASK 0x0F000000U
15570 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
15571 * input for the respective bypte lane of the PHY
15573 #undef DDR_PHY_DX5GCR0_RDDLY_DEFVAL
15574 #undef DDR_PHY_DX5GCR0_RDDLY_SHIFT
15575 #undef DDR_PHY_DX5GCR0_RDDLY_MASK
15576 #define DDR_PHY_DX5GCR0_RDDLY_DEFVAL 0x40200204
15577 #define DDR_PHY_DX5GCR0_RDDLY_SHIFT 20
15578 #define DDR_PHY_DX5GCR0_RDDLY_MASK 0x00F00000U
15581 * Reserved. Return zeroes on reads.
15583 #undef DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL
15584 #undef DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT
15585 #undef DDR_PHY_DX5GCR0_RESERVED_19_14_MASK
15586 #define DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL 0x40200204
15587 #define DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT 14
15588 #define DDR_PHY_DX5GCR0_RESERVED_19_14_MASK 0x000FC000U
15591 * DQSNSE Power Down Receiver
15593 #undef DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL
15594 #undef DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT
15595 #undef DDR_PHY_DX5GCR0_DQSNSEPDR_MASK
15596 #define DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL 0x40200204
15597 #define DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT 13
15598 #define DDR_PHY_DX5GCR0_DQSNSEPDR_MASK 0x00002000U
15601 * DQSSE Power Down Receiver
15603 #undef DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL
15604 #undef DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT
15605 #undef DDR_PHY_DX5GCR0_DQSSEPDR_MASK
15606 #define DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL 0x40200204
15607 #define DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT 12
15608 #define DDR_PHY_DX5GCR0_DQSSEPDR_MASK 0x00001000U
15611 * RTT On Additive Latency
15613 #undef DDR_PHY_DX5GCR0_RTTOAL_DEFVAL
15614 #undef DDR_PHY_DX5GCR0_RTTOAL_SHIFT
15615 #undef DDR_PHY_DX5GCR0_RTTOAL_MASK
15616 #define DDR_PHY_DX5GCR0_RTTOAL_DEFVAL 0x40200204
15617 #define DDR_PHY_DX5GCR0_RTTOAL_SHIFT 11
15618 #define DDR_PHY_DX5GCR0_RTTOAL_MASK 0x00000800U
15623 #undef DDR_PHY_DX5GCR0_RTTOH_DEFVAL
15624 #undef DDR_PHY_DX5GCR0_RTTOH_SHIFT
15625 #undef DDR_PHY_DX5GCR0_RTTOH_MASK
15626 #define DDR_PHY_DX5GCR0_RTTOH_DEFVAL 0x40200204
15627 #define DDR_PHY_DX5GCR0_RTTOH_SHIFT 9
15628 #define DDR_PHY_DX5GCR0_RTTOH_MASK 0x00000600U
15631 * Configurable PDR Phase Shift
15633 #undef DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL
15634 #undef DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT
15635 #undef DDR_PHY_DX5GCR0_CPDRSHFT_MASK
15636 #define DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL 0x40200204
15637 #define DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT 7
15638 #define DDR_PHY_DX5GCR0_CPDRSHFT_MASK 0x00000180U
15643 #undef DDR_PHY_DX5GCR0_DQSRPD_DEFVAL
15644 #undef DDR_PHY_DX5GCR0_DQSRPD_SHIFT
15645 #undef DDR_PHY_DX5GCR0_DQSRPD_MASK
15646 #define DDR_PHY_DX5GCR0_DQSRPD_DEFVAL 0x40200204
15647 #define DDR_PHY_DX5GCR0_DQSRPD_SHIFT 6
15648 #define DDR_PHY_DX5GCR0_DQSRPD_MASK 0x00000040U
15651 * DQSG Power Down Receiver
15653 #undef DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL
15654 #undef DDR_PHY_DX5GCR0_DQSGPDR_SHIFT
15655 #undef DDR_PHY_DX5GCR0_DQSGPDR_MASK
15656 #define DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL 0x40200204
15657 #define DDR_PHY_DX5GCR0_DQSGPDR_SHIFT 5
15658 #define DDR_PHY_DX5GCR0_DQSGPDR_MASK 0x00000020U
15661 * Reserved. Return zeroes on reads.
15663 #undef DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL
15664 #undef DDR_PHY_DX5GCR0_RESERVED_4_SHIFT
15665 #undef DDR_PHY_DX5GCR0_RESERVED_4_MASK
15666 #define DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL 0x40200204
15667 #define DDR_PHY_DX5GCR0_RESERVED_4_SHIFT 4
15668 #define DDR_PHY_DX5GCR0_RESERVED_4_MASK 0x00000010U
15671 * DQSG On-Die Termination
15673 #undef DDR_PHY_DX5GCR0_DQSGODT_DEFVAL
15674 #undef DDR_PHY_DX5GCR0_DQSGODT_SHIFT
15675 #undef DDR_PHY_DX5GCR0_DQSGODT_MASK
15676 #define DDR_PHY_DX5GCR0_DQSGODT_DEFVAL 0x40200204
15677 #define DDR_PHY_DX5GCR0_DQSGODT_SHIFT 3
15678 #define DDR_PHY_DX5GCR0_DQSGODT_MASK 0x00000008U
15681 * DQSG Output Enable
15683 #undef DDR_PHY_DX5GCR0_DQSGOE_DEFVAL
15684 #undef DDR_PHY_DX5GCR0_DQSGOE_SHIFT
15685 #undef DDR_PHY_DX5GCR0_DQSGOE_MASK
15686 #define DDR_PHY_DX5GCR0_DQSGOE_DEFVAL 0x40200204
15687 #define DDR_PHY_DX5GCR0_DQSGOE_SHIFT 2
15688 #define DDR_PHY_DX5GCR0_DQSGOE_MASK 0x00000004U
15691 * Reserved. Return zeroes on reads.
15693 #undef DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL
15694 #undef DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT
15695 #undef DDR_PHY_DX5GCR0_RESERVED_1_0_MASK
15696 #define DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL 0x40200204
15697 #define DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT 0
15698 #define DDR_PHY_DX5GCR0_RESERVED_1_0_MASK 0x00000003U
15701 * Enables the PDR mode for DQ[7:0]
15703 #undef DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL
15704 #undef DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT
15705 #undef DDR_PHY_DX5GCR1_DXPDRMODE_MASK
15706 #define DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL 0x00007FFF
15707 #define DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT 16
15708 #define DDR_PHY_DX5GCR1_DXPDRMODE_MASK 0xFFFF0000U
15711 * Reserved. Returns zeroes on reads.
15713 #undef DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL
15714 #undef DDR_PHY_DX5GCR1_RESERVED_15_SHIFT
15715 #undef DDR_PHY_DX5GCR1_RESERVED_15_MASK
15716 #define DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL 0x00007FFF
15717 #define DDR_PHY_DX5GCR1_RESERVED_15_SHIFT 15
15718 #define DDR_PHY_DX5GCR1_RESERVED_15_MASK 0x00008000U
15721 * Select the delayed or non-delayed read data strobe #
15723 #undef DDR_PHY_DX5GCR1_QSNSEL_DEFVAL
15724 #undef DDR_PHY_DX5GCR1_QSNSEL_SHIFT
15725 #undef DDR_PHY_DX5GCR1_QSNSEL_MASK
15726 #define DDR_PHY_DX5GCR1_QSNSEL_DEFVAL 0x00007FFF
15727 #define DDR_PHY_DX5GCR1_QSNSEL_SHIFT 14
15728 #define DDR_PHY_DX5GCR1_QSNSEL_MASK 0x00004000U
15731 * Select the delayed or non-delayed read data strobe
15733 #undef DDR_PHY_DX5GCR1_QSSEL_DEFVAL
15734 #undef DDR_PHY_DX5GCR1_QSSEL_SHIFT
15735 #undef DDR_PHY_DX5GCR1_QSSEL_MASK
15736 #define DDR_PHY_DX5GCR1_QSSEL_DEFVAL 0x00007FFF
15737 #define DDR_PHY_DX5GCR1_QSSEL_SHIFT 13
15738 #define DDR_PHY_DX5GCR1_QSSEL_MASK 0x00002000U
15741 * Enables Read Data Strobe in a byte lane
15743 #undef DDR_PHY_DX5GCR1_OEEN_DEFVAL
15744 #undef DDR_PHY_DX5GCR1_OEEN_SHIFT
15745 #undef DDR_PHY_DX5GCR1_OEEN_MASK
15746 #define DDR_PHY_DX5GCR1_OEEN_DEFVAL 0x00007FFF
15747 #define DDR_PHY_DX5GCR1_OEEN_SHIFT 12
15748 #define DDR_PHY_DX5GCR1_OEEN_MASK 0x00001000U
15751 * Enables PDR in a byte lane
15753 #undef DDR_PHY_DX5GCR1_PDREN_DEFVAL
15754 #undef DDR_PHY_DX5GCR1_PDREN_SHIFT
15755 #undef DDR_PHY_DX5GCR1_PDREN_MASK
15756 #define DDR_PHY_DX5GCR1_PDREN_DEFVAL 0x00007FFF
15757 #define DDR_PHY_DX5GCR1_PDREN_SHIFT 11
15758 #define DDR_PHY_DX5GCR1_PDREN_MASK 0x00000800U
15761 * Enables ODT/TE in a byte lane
15763 #undef DDR_PHY_DX5GCR1_TEEN_DEFVAL
15764 #undef DDR_PHY_DX5GCR1_TEEN_SHIFT
15765 #undef DDR_PHY_DX5GCR1_TEEN_MASK
15766 #define DDR_PHY_DX5GCR1_TEEN_DEFVAL 0x00007FFF
15767 #define DDR_PHY_DX5GCR1_TEEN_SHIFT 10
15768 #define DDR_PHY_DX5GCR1_TEEN_MASK 0x00000400U
15771 * Enables Write Data strobe in a byte lane
15773 #undef DDR_PHY_DX5GCR1_DSEN_DEFVAL
15774 #undef DDR_PHY_DX5GCR1_DSEN_SHIFT
15775 #undef DDR_PHY_DX5GCR1_DSEN_MASK
15776 #define DDR_PHY_DX5GCR1_DSEN_DEFVAL 0x00007FFF
15777 #define DDR_PHY_DX5GCR1_DSEN_SHIFT 9
15778 #define DDR_PHY_DX5GCR1_DSEN_MASK 0x00000200U
15781 * Enables DM pin in a byte lane
15783 #undef DDR_PHY_DX5GCR1_DMEN_DEFVAL
15784 #undef DDR_PHY_DX5GCR1_DMEN_SHIFT
15785 #undef DDR_PHY_DX5GCR1_DMEN_MASK
15786 #define DDR_PHY_DX5GCR1_DMEN_DEFVAL 0x00007FFF
15787 #define DDR_PHY_DX5GCR1_DMEN_SHIFT 8
15788 #define DDR_PHY_DX5GCR1_DMEN_MASK 0x00000100U
15791 * Enables DQ corresponding to each bit in a byte
15793 #undef DDR_PHY_DX5GCR1_DQEN_DEFVAL
15794 #undef DDR_PHY_DX5GCR1_DQEN_SHIFT
15795 #undef DDR_PHY_DX5GCR1_DQEN_MASK
15796 #define DDR_PHY_DX5GCR1_DQEN_DEFVAL 0x00007FFF
15797 #define DDR_PHY_DX5GCR1_DQEN_SHIFT 0
15798 #define DDR_PHY_DX5GCR1_DQEN_MASK 0x000000FFU
15801 * Byte lane VREF IOM (Used only by D4MU IOs)
15803 #undef DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL
15804 #undef DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT
15805 #undef DDR_PHY_DX5GCR4_RESERVED_31_29_MASK
15806 #define DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL 0x0E00003C
15807 #define DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT 29
15808 #define DDR_PHY_DX5GCR4_RESERVED_31_29_MASK 0xE0000000U
15811 * Byte Lane VREF Pad Enable
15813 #undef DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL
15814 #undef DDR_PHY_DX5GCR4_DXREFPEN_SHIFT
15815 #undef DDR_PHY_DX5GCR4_DXREFPEN_MASK
15816 #define DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL 0x0E00003C
15817 #define DDR_PHY_DX5GCR4_DXREFPEN_SHIFT 28
15818 #define DDR_PHY_DX5GCR4_DXREFPEN_MASK 0x10000000U
15821 * Byte Lane Internal VREF Enable
15823 #undef DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL
15824 #undef DDR_PHY_DX5GCR4_DXREFEEN_SHIFT
15825 #undef DDR_PHY_DX5GCR4_DXREFEEN_MASK
15826 #define DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL 0x0E00003C
15827 #define DDR_PHY_DX5GCR4_DXREFEEN_SHIFT 26
15828 #define DDR_PHY_DX5GCR4_DXREFEEN_MASK 0x0C000000U
15831 * Byte Lane Single-End VREF Enable
15833 #undef DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL
15834 #undef DDR_PHY_DX5GCR4_DXREFSEN_SHIFT
15835 #undef DDR_PHY_DX5GCR4_DXREFSEN_MASK
15836 #define DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL 0x0E00003C
15837 #define DDR_PHY_DX5GCR4_DXREFSEN_SHIFT 25
15838 #define DDR_PHY_DX5GCR4_DXREFSEN_MASK 0x02000000U
15841 * Reserved. Returns zeros on reads.
15843 #undef DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL
15844 #undef DDR_PHY_DX5GCR4_RESERVED_24_SHIFT
15845 #undef DDR_PHY_DX5GCR4_RESERVED_24_MASK
15846 #define DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL 0x0E00003C
15847 #define DDR_PHY_DX5GCR4_RESERVED_24_SHIFT 24
15848 #define DDR_PHY_DX5GCR4_RESERVED_24_MASK 0x01000000U
15851 * External VREF generator REFSEL range select
15853 #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL
15854 #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT
15855 #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK
15856 #define DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C
15857 #define DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT 23
15858 #define DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK 0x00800000U
15861 * Byte Lane External VREF Select
15863 #undef DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL
15864 #undef DDR_PHY_DX5GCR4_DXREFESEL_SHIFT
15865 #undef DDR_PHY_DX5GCR4_DXREFESEL_MASK
15866 #define DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL 0x0E00003C
15867 #define DDR_PHY_DX5GCR4_DXREFESEL_SHIFT 16
15868 #define DDR_PHY_DX5GCR4_DXREFESEL_MASK 0x007F0000U
15871 * Single ended VREF generator REFSEL range select
15873 #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL
15874 #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT
15875 #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK
15876 #define DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C
15877 #define DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT 15
15878 #define DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK 0x00008000U
15881 * Byte Lane Single-End VREF Select
15883 #undef DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL
15884 #undef DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT
15885 #undef DDR_PHY_DX5GCR4_DXREFSSEL_MASK
15886 #define DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL 0x0E00003C
15887 #define DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT 8
15888 #define DDR_PHY_DX5GCR4_DXREFSSEL_MASK 0x00007F00U
15891 * Reserved. Returns zeros on reads.
15893 #undef DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL
15894 #undef DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT
15895 #undef DDR_PHY_DX5GCR4_RESERVED_7_6_MASK
15896 #define DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL 0x0E00003C
15897 #define DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT 6
15898 #define DDR_PHY_DX5GCR4_RESERVED_7_6_MASK 0x000000C0U
15901 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
15903 #undef DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL
15904 #undef DDR_PHY_DX5GCR4_DXREFIEN_SHIFT
15905 #undef DDR_PHY_DX5GCR4_DXREFIEN_MASK
15906 #define DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL 0x0E00003C
15907 #define DDR_PHY_DX5GCR4_DXREFIEN_SHIFT 2
15908 #define DDR_PHY_DX5GCR4_DXREFIEN_MASK 0x0000003CU
15911 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
15913 #undef DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL
15914 #undef DDR_PHY_DX5GCR4_DXREFIMON_SHIFT
15915 #undef DDR_PHY_DX5GCR4_DXREFIMON_MASK
15916 #define DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL 0x0E00003C
15917 #define DDR_PHY_DX5GCR4_DXREFIMON_SHIFT 0
15918 #define DDR_PHY_DX5GCR4_DXREFIMON_MASK 0x00000003U
15921 * Reserved. Returns zeros on reads.
15923 #undef DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL
15924 #undef DDR_PHY_DX5GCR5_RESERVED_31_SHIFT
15925 #undef DDR_PHY_DX5GCR5_RESERVED_31_MASK
15926 #define DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL 0x09090909
15927 #define DDR_PHY_DX5GCR5_RESERVED_31_SHIFT 31
15928 #define DDR_PHY_DX5GCR5_RESERVED_31_MASK 0x80000000U
15931 * Byte Lane internal VREF Select for Rank 3
15933 #undef DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL
15934 #undef DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT
15935 #undef DDR_PHY_DX5GCR5_DXREFISELR3_MASK
15936 #define DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL 0x09090909
15937 #define DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT 24
15938 #define DDR_PHY_DX5GCR5_DXREFISELR3_MASK 0x7F000000U
15941 * Reserved. Returns zeros on reads.
15943 #undef DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL
15944 #undef DDR_PHY_DX5GCR5_RESERVED_23_SHIFT
15945 #undef DDR_PHY_DX5GCR5_RESERVED_23_MASK
15946 #define DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL 0x09090909
15947 #define DDR_PHY_DX5GCR5_RESERVED_23_SHIFT 23
15948 #define DDR_PHY_DX5GCR5_RESERVED_23_MASK 0x00800000U
15951 * Byte Lane internal VREF Select for Rank 2
15953 #undef DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL
15954 #undef DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT
15955 #undef DDR_PHY_DX5GCR5_DXREFISELR2_MASK
15956 #define DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL 0x09090909
15957 #define DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT 16
15958 #define DDR_PHY_DX5GCR5_DXREFISELR2_MASK 0x007F0000U
15961 * Reserved. Returns zeros on reads.
15963 #undef DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL
15964 #undef DDR_PHY_DX5GCR5_RESERVED_15_SHIFT
15965 #undef DDR_PHY_DX5GCR5_RESERVED_15_MASK
15966 #define DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL 0x09090909
15967 #define DDR_PHY_DX5GCR5_RESERVED_15_SHIFT 15
15968 #define DDR_PHY_DX5GCR5_RESERVED_15_MASK 0x00008000U
15971 * Byte Lane internal VREF Select for Rank 1
15973 #undef DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL
15974 #undef DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT
15975 #undef DDR_PHY_DX5GCR5_DXREFISELR1_MASK
15976 #define DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL 0x09090909
15977 #define DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT 8
15978 #define DDR_PHY_DX5GCR5_DXREFISELR1_MASK 0x00007F00U
15981 * Reserved. Returns zeros on reads.
15983 #undef DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL
15984 #undef DDR_PHY_DX5GCR5_RESERVED_7_SHIFT
15985 #undef DDR_PHY_DX5GCR5_RESERVED_7_MASK
15986 #define DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL 0x09090909
15987 #define DDR_PHY_DX5GCR5_RESERVED_7_SHIFT 7
15988 #define DDR_PHY_DX5GCR5_RESERVED_7_MASK 0x00000080U
15991 * Byte Lane internal VREF Select for Rank 0
15993 #undef DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL
15994 #undef DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT
15995 #undef DDR_PHY_DX5GCR5_DXREFISELR0_MASK
15996 #define DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL 0x09090909
15997 #define DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT 0
15998 #define DDR_PHY_DX5GCR5_DXREFISELR0_MASK 0x0000007FU
16001 * Reserved. Returns zeros on reads.
16003 #undef DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL
16004 #undef DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT
16005 #undef DDR_PHY_DX5GCR6_RESERVED_31_30_MASK
16006 #define DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL 0x09090909
16007 #define DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT 30
16008 #define DDR_PHY_DX5GCR6_RESERVED_31_30_MASK 0xC0000000U
16011 * DRAM DQ VREF Select for Rank3
16013 #undef DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL
16014 #undef DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT
16015 #undef DDR_PHY_DX5GCR6_DXDQVREFR3_MASK
16016 #define DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL 0x09090909
16017 #define DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT 24
16018 #define DDR_PHY_DX5GCR6_DXDQVREFR3_MASK 0x3F000000U
16021 * Reserved. Returns zeros on reads.
16023 #undef DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL
16024 #undef DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT
16025 #undef DDR_PHY_DX5GCR6_RESERVED_23_22_MASK
16026 #define DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL 0x09090909
16027 #define DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT 22
16028 #define DDR_PHY_DX5GCR6_RESERVED_23_22_MASK 0x00C00000U
16031 * DRAM DQ VREF Select for Rank2
16033 #undef DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL
16034 #undef DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT
16035 #undef DDR_PHY_DX5GCR6_DXDQVREFR2_MASK
16036 #define DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL 0x09090909
16037 #define DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT 16
16038 #define DDR_PHY_DX5GCR6_DXDQVREFR2_MASK 0x003F0000U
16041 * Reserved. Returns zeros on reads.
16043 #undef DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL
16044 #undef DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT
16045 #undef DDR_PHY_DX5GCR6_RESERVED_15_14_MASK
16046 #define DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL 0x09090909
16047 #define DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT 14
16048 #define DDR_PHY_DX5GCR6_RESERVED_15_14_MASK 0x0000C000U
16051 * DRAM DQ VREF Select for Rank1
16053 #undef DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL
16054 #undef DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT
16055 #undef DDR_PHY_DX5GCR6_DXDQVREFR1_MASK
16056 #define DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL 0x09090909
16057 #define DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT 8
16058 #define DDR_PHY_DX5GCR6_DXDQVREFR1_MASK 0x00003F00U
16061 * Reserved. Returns zeros on reads.
16063 #undef DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL
16064 #undef DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT
16065 #undef DDR_PHY_DX5GCR6_RESERVED_7_6_MASK
16066 #define DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL 0x09090909
16067 #define DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT 6
16068 #define DDR_PHY_DX5GCR6_RESERVED_7_6_MASK 0x000000C0U
16071 * DRAM DQ VREF Select for Rank0
16073 #undef DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL
16074 #undef DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT
16075 #undef DDR_PHY_DX5GCR6_DXDQVREFR0_MASK
16076 #define DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL 0x09090909
16077 #define DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT 0
16078 #define DDR_PHY_DX5GCR6_DXDQVREFR0_MASK 0x0000003FU
16081 * Calibration Bypass
16083 #undef DDR_PHY_DX6GCR0_CALBYP_DEFVAL
16084 #undef DDR_PHY_DX6GCR0_CALBYP_SHIFT
16085 #undef DDR_PHY_DX6GCR0_CALBYP_MASK
16086 #define DDR_PHY_DX6GCR0_CALBYP_DEFVAL 0x40200204
16087 #define DDR_PHY_DX6GCR0_CALBYP_SHIFT 31
16088 #define DDR_PHY_DX6GCR0_CALBYP_MASK 0x80000000U
16091 * Master Delay Line Enable
16093 #undef DDR_PHY_DX6GCR0_MDLEN_DEFVAL
16094 #undef DDR_PHY_DX6GCR0_MDLEN_SHIFT
16095 #undef DDR_PHY_DX6GCR0_MDLEN_MASK
16096 #define DDR_PHY_DX6GCR0_MDLEN_DEFVAL 0x40200204
16097 #define DDR_PHY_DX6GCR0_MDLEN_SHIFT 30
16098 #define DDR_PHY_DX6GCR0_MDLEN_MASK 0x40000000U
16101 * Configurable ODT(TE) Phase Shift
16103 #undef DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL
16104 #undef DDR_PHY_DX6GCR0_CODTSHFT_SHIFT
16105 #undef DDR_PHY_DX6GCR0_CODTSHFT_MASK
16106 #define DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL 0x40200204
16107 #define DDR_PHY_DX6GCR0_CODTSHFT_SHIFT 28
16108 #define DDR_PHY_DX6GCR0_CODTSHFT_MASK 0x30000000U
16111 * DQS Duty Cycle Correction
16113 #undef DDR_PHY_DX6GCR0_DQSDCC_DEFVAL
16114 #undef DDR_PHY_DX6GCR0_DQSDCC_SHIFT
16115 #undef DDR_PHY_DX6GCR0_DQSDCC_MASK
16116 #define DDR_PHY_DX6GCR0_DQSDCC_DEFVAL 0x40200204
16117 #define DDR_PHY_DX6GCR0_DQSDCC_SHIFT 24
16118 #define DDR_PHY_DX6GCR0_DQSDCC_MASK 0x0F000000U
16121 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
16122 * input for the respective bypte lane of the PHY
16124 #undef DDR_PHY_DX6GCR0_RDDLY_DEFVAL
16125 #undef DDR_PHY_DX6GCR0_RDDLY_SHIFT
16126 #undef DDR_PHY_DX6GCR0_RDDLY_MASK
16127 #define DDR_PHY_DX6GCR0_RDDLY_DEFVAL 0x40200204
16128 #define DDR_PHY_DX6GCR0_RDDLY_SHIFT 20
16129 #define DDR_PHY_DX6GCR0_RDDLY_MASK 0x00F00000U
16132 * Reserved. Return zeroes on reads.
16134 #undef DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL
16135 #undef DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT
16136 #undef DDR_PHY_DX6GCR0_RESERVED_19_14_MASK
16137 #define DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL 0x40200204
16138 #define DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT 14
16139 #define DDR_PHY_DX6GCR0_RESERVED_19_14_MASK 0x000FC000U
16142 * DQSNSE Power Down Receiver
16144 #undef DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL
16145 #undef DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT
16146 #undef DDR_PHY_DX6GCR0_DQSNSEPDR_MASK
16147 #define DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL 0x40200204
16148 #define DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT 13
16149 #define DDR_PHY_DX6GCR0_DQSNSEPDR_MASK 0x00002000U
16152 * DQSSE Power Down Receiver
16154 #undef DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL
16155 #undef DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT
16156 #undef DDR_PHY_DX6GCR0_DQSSEPDR_MASK
16157 #define DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL 0x40200204
16158 #define DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT 12
16159 #define DDR_PHY_DX6GCR0_DQSSEPDR_MASK 0x00001000U
16162 * RTT On Additive Latency
16164 #undef DDR_PHY_DX6GCR0_RTTOAL_DEFVAL
16165 #undef DDR_PHY_DX6GCR0_RTTOAL_SHIFT
16166 #undef DDR_PHY_DX6GCR0_RTTOAL_MASK
16167 #define DDR_PHY_DX6GCR0_RTTOAL_DEFVAL 0x40200204
16168 #define DDR_PHY_DX6GCR0_RTTOAL_SHIFT 11
16169 #define DDR_PHY_DX6GCR0_RTTOAL_MASK 0x00000800U
16174 #undef DDR_PHY_DX6GCR0_RTTOH_DEFVAL
16175 #undef DDR_PHY_DX6GCR0_RTTOH_SHIFT
16176 #undef DDR_PHY_DX6GCR0_RTTOH_MASK
16177 #define DDR_PHY_DX6GCR0_RTTOH_DEFVAL 0x40200204
16178 #define DDR_PHY_DX6GCR0_RTTOH_SHIFT 9
16179 #define DDR_PHY_DX6GCR0_RTTOH_MASK 0x00000600U
16182 * Configurable PDR Phase Shift
16184 #undef DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL
16185 #undef DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT
16186 #undef DDR_PHY_DX6GCR0_CPDRSHFT_MASK
16187 #define DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL 0x40200204
16188 #define DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT 7
16189 #define DDR_PHY_DX6GCR0_CPDRSHFT_MASK 0x00000180U
16194 #undef DDR_PHY_DX6GCR0_DQSRPD_DEFVAL
16195 #undef DDR_PHY_DX6GCR0_DQSRPD_SHIFT
16196 #undef DDR_PHY_DX6GCR0_DQSRPD_MASK
16197 #define DDR_PHY_DX6GCR0_DQSRPD_DEFVAL 0x40200204
16198 #define DDR_PHY_DX6GCR0_DQSRPD_SHIFT 6
16199 #define DDR_PHY_DX6GCR0_DQSRPD_MASK 0x00000040U
16202 * DQSG Power Down Receiver
16204 #undef DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL
16205 #undef DDR_PHY_DX6GCR0_DQSGPDR_SHIFT
16206 #undef DDR_PHY_DX6GCR0_DQSGPDR_MASK
16207 #define DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL 0x40200204
16208 #define DDR_PHY_DX6GCR0_DQSGPDR_SHIFT 5
16209 #define DDR_PHY_DX6GCR0_DQSGPDR_MASK 0x00000020U
16212 * Reserved. Return zeroes on reads.
16214 #undef DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL
16215 #undef DDR_PHY_DX6GCR0_RESERVED_4_SHIFT
16216 #undef DDR_PHY_DX6GCR0_RESERVED_4_MASK
16217 #define DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL 0x40200204
16218 #define DDR_PHY_DX6GCR0_RESERVED_4_SHIFT 4
16219 #define DDR_PHY_DX6GCR0_RESERVED_4_MASK 0x00000010U
16222 * DQSG On-Die Termination
16224 #undef DDR_PHY_DX6GCR0_DQSGODT_DEFVAL
16225 #undef DDR_PHY_DX6GCR0_DQSGODT_SHIFT
16226 #undef DDR_PHY_DX6GCR0_DQSGODT_MASK
16227 #define DDR_PHY_DX6GCR0_DQSGODT_DEFVAL 0x40200204
16228 #define DDR_PHY_DX6GCR0_DQSGODT_SHIFT 3
16229 #define DDR_PHY_DX6GCR0_DQSGODT_MASK 0x00000008U
16232 * DQSG Output Enable
16234 #undef DDR_PHY_DX6GCR0_DQSGOE_DEFVAL
16235 #undef DDR_PHY_DX6GCR0_DQSGOE_SHIFT
16236 #undef DDR_PHY_DX6GCR0_DQSGOE_MASK
16237 #define DDR_PHY_DX6GCR0_DQSGOE_DEFVAL 0x40200204
16238 #define DDR_PHY_DX6GCR0_DQSGOE_SHIFT 2
16239 #define DDR_PHY_DX6GCR0_DQSGOE_MASK 0x00000004U
16242 * Reserved. Return zeroes on reads.
16244 #undef DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL
16245 #undef DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT
16246 #undef DDR_PHY_DX6GCR0_RESERVED_1_0_MASK
16247 #define DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL 0x40200204
16248 #define DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT 0
16249 #define DDR_PHY_DX6GCR0_RESERVED_1_0_MASK 0x00000003U
16252 * Enables the PDR mode for DQ[7:0]
16254 #undef DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL
16255 #undef DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT
16256 #undef DDR_PHY_DX6GCR1_DXPDRMODE_MASK
16257 #define DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL 0x00007FFF
16258 #define DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT 16
16259 #define DDR_PHY_DX6GCR1_DXPDRMODE_MASK 0xFFFF0000U
16262 * Reserved. Returns zeroes on reads.
16264 #undef DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL
16265 #undef DDR_PHY_DX6GCR1_RESERVED_15_SHIFT
16266 #undef DDR_PHY_DX6GCR1_RESERVED_15_MASK
16267 #define DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL 0x00007FFF
16268 #define DDR_PHY_DX6GCR1_RESERVED_15_SHIFT 15
16269 #define DDR_PHY_DX6GCR1_RESERVED_15_MASK 0x00008000U
16272 * Select the delayed or non-delayed read data strobe #
16274 #undef DDR_PHY_DX6GCR1_QSNSEL_DEFVAL
16275 #undef DDR_PHY_DX6GCR1_QSNSEL_SHIFT
16276 #undef DDR_PHY_DX6GCR1_QSNSEL_MASK
16277 #define DDR_PHY_DX6GCR1_QSNSEL_DEFVAL 0x00007FFF
16278 #define DDR_PHY_DX6GCR1_QSNSEL_SHIFT 14
16279 #define DDR_PHY_DX6GCR1_QSNSEL_MASK 0x00004000U
16282 * Select the delayed or non-delayed read data strobe
16284 #undef DDR_PHY_DX6GCR1_QSSEL_DEFVAL
16285 #undef DDR_PHY_DX6GCR1_QSSEL_SHIFT
16286 #undef DDR_PHY_DX6GCR1_QSSEL_MASK
16287 #define DDR_PHY_DX6GCR1_QSSEL_DEFVAL 0x00007FFF
16288 #define DDR_PHY_DX6GCR1_QSSEL_SHIFT 13
16289 #define DDR_PHY_DX6GCR1_QSSEL_MASK 0x00002000U
16292 * Enables Read Data Strobe in a byte lane
16294 #undef DDR_PHY_DX6GCR1_OEEN_DEFVAL
16295 #undef DDR_PHY_DX6GCR1_OEEN_SHIFT
16296 #undef DDR_PHY_DX6GCR1_OEEN_MASK
16297 #define DDR_PHY_DX6GCR1_OEEN_DEFVAL 0x00007FFF
16298 #define DDR_PHY_DX6GCR1_OEEN_SHIFT 12
16299 #define DDR_PHY_DX6GCR1_OEEN_MASK 0x00001000U
16302 * Enables PDR in a byte lane
16304 #undef DDR_PHY_DX6GCR1_PDREN_DEFVAL
16305 #undef DDR_PHY_DX6GCR1_PDREN_SHIFT
16306 #undef DDR_PHY_DX6GCR1_PDREN_MASK
16307 #define DDR_PHY_DX6GCR1_PDREN_DEFVAL 0x00007FFF
16308 #define DDR_PHY_DX6GCR1_PDREN_SHIFT 11
16309 #define DDR_PHY_DX6GCR1_PDREN_MASK 0x00000800U
16312 * Enables ODT/TE in a byte lane
16314 #undef DDR_PHY_DX6GCR1_TEEN_DEFVAL
16315 #undef DDR_PHY_DX6GCR1_TEEN_SHIFT
16316 #undef DDR_PHY_DX6GCR1_TEEN_MASK
16317 #define DDR_PHY_DX6GCR1_TEEN_DEFVAL 0x00007FFF
16318 #define DDR_PHY_DX6GCR1_TEEN_SHIFT 10
16319 #define DDR_PHY_DX6GCR1_TEEN_MASK 0x00000400U
16322 * Enables Write Data strobe in a byte lane
16324 #undef DDR_PHY_DX6GCR1_DSEN_DEFVAL
16325 #undef DDR_PHY_DX6GCR1_DSEN_SHIFT
16326 #undef DDR_PHY_DX6GCR1_DSEN_MASK
16327 #define DDR_PHY_DX6GCR1_DSEN_DEFVAL 0x00007FFF
16328 #define DDR_PHY_DX6GCR1_DSEN_SHIFT 9
16329 #define DDR_PHY_DX6GCR1_DSEN_MASK 0x00000200U
16332 * Enables DM pin in a byte lane
16334 #undef DDR_PHY_DX6GCR1_DMEN_DEFVAL
16335 #undef DDR_PHY_DX6GCR1_DMEN_SHIFT
16336 #undef DDR_PHY_DX6GCR1_DMEN_MASK
16337 #define DDR_PHY_DX6GCR1_DMEN_DEFVAL 0x00007FFF
16338 #define DDR_PHY_DX6GCR1_DMEN_SHIFT 8
16339 #define DDR_PHY_DX6GCR1_DMEN_MASK 0x00000100U
16342 * Enables DQ corresponding to each bit in a byte
16344 #undef DDR_PHY_DX6GCR1_DQEN_DEFVAL
16345 #undef DDR_PHY_DX6GCR1_DQEN_SHIFT
16346 #undef DDR_PHY_DX6GCR1_DQEN_MASK
16347 #define DDR_PHY_DX6GCR1_DQEN_DEFVAL 0x00007FFF
16348 #define DDR_PHY_DX6GCR1_DQEN_SHIFT 0
16349 #define DDR_PHY_DX6GCR1_DQEN_MASK 0x000000FFU
16352 * Byte lane VREF IOM (Used only by D4MU IOs)
16354 #undef DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL
16355 #undef DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT
16356 #undef DDR_PHY_DX6GCR4_RESERVED_31_29_MASK
16357 #define DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL 0x0E00003C
16358 #define DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT 29
16359 #define DDR_PHY_DX6GCR4_RESERVED_31_29_MASK 0xE0000000U
16362 * Byte Lane VREF Pad Enable
16364 #undef DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL
16365 #undef DDR_PHY_DX6GCR4_DXREFPEN_SHIFT
16366 #undef DDR_PHY_DX6GCR4_DXREFPEN_MASK
16367 #define DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL 0x0E00003C
16368 #define DDR_PHY_DX6GCR4_DXREFPEN_SHIFT 28
16369 #define DDR_PHY_DX6GCR4_DXREFPEN_MASK 0x10000000U
16372 * Byte Lane Internal VREF Enable
16374 #undef DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL
16375 #undef DDR_PHY_DX6GCR4_DXREFEEN_SHIFT
16376 #undef DDR_PHY_DX6GCR4_DXREFEEN_MASK
16377 #define DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL 0x0E00003C
16378 #define DDR_PHY_DX6GCR4_DXREFEEN_SHIFT 26
16379 #define DDR_PHY_DX6GCR4_DXREFEEN_MASK 0x0C000000U
16382 * Byte Lane Single-End VREF Enable
16384 #undef DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL
16385 #undef DDR_PHY_DX6GCR4_DXREFSEN_SHIFT
16386 #undef DDR_PHY_DX6GCR4_DXREFSEN_MASK
16387 #define DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL 0x0E00003C
16388 #define DDR_PHY_DX6GCR4_DXREFSEN_SHIFT 25
16389 #define DDR_PHY_DX6GCR4_DXREFSEN_MASK 0x02000000U
16392 * Reserved. Returns zeros on reads.
16394 #undef DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL
16395 #undef DDR_PHY_DX6GCR4_RESERVED_24_SHIFT
16396 #undef DDR_PHY_DX6GCR4_RESERVED_24_MASK
16397 #define DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL 0x0E00003C
16398 #define DDR_PHY_DX6GCR4_RESERVED_24_SHIFT 24
16399 #define DDR_PHY_DX6GCR4_RESERVED_24_MASK 0x01000000U
16402 * External VREF generator REFSEL range select
16404 #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL
16405 #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT
16406 #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK
16407 #define DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C
16408 #define DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT 23
16409 #define DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK 0x00800000U
16412 * Byte Lane External VREF Select
16414 #undef DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL
16415 #undef DDR_PHY_DX6GCR4_DXREFESEL_SHIFT
16416 #undef DDR_PHY_DX6GCR4_DXREFESEL_MASK
16417 #define DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL 0x0E00003C
16418 #define DDR_PHY_DX6GCR4_DXREFESEL_SHIFT 16
16419 #define DDR_PHY_DX6GCR4_DXREFESEL_MASK 0x007F0000U
16422 * Single ended VREF generator REFSEL range select
16424 #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL
16425 #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT
16426 #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK
16427 #define DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C
16428 #define DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT 15
16429 #define DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK 0x00008000U
16432 * Byte Lane Single-End VREF Select
16434 #undef DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL
16435 #undef DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT
16436 #undef DDR_PHY_DX6GCR4_DXREFSSEL_MASK
16437 #define DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL 0x0E00003C
16438 #define DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT 8
16439 #define DDR_PHY_DX6GCR4_DXREFSSEL_MASK 0x00007F00U
16442 * Reserved. Returns zeros on reads.
16444 #undef DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL
16445 #undef DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT
16446 #undef DDR_PHY_DX6GCR4_RESERVED_7_6_MASK
16447 #define DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL 0x0E00003C
16448 #define DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT 6
16449 #define DDR_PHY_DX6GCR4_RESERVED_7_6_MASK 0x000000C0U
16452 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
16454 #undef DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL
16455 #undef DDR_PHY_DX6GCR4_DXREFIEN_SHIFT
16456 #undef DDR_PHY_DX6GCR4_DXREFIEN_MASK
16457 #define DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL 0x0E00003C
16458 #define DDR_PHY_DX6GCR4_DXREFIEN_SHIFT 2
16459 #define DDR_PHY_DX6GCR4_DXREFIEN_MASK 0x0000003CU
16462 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
16464 #undef DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL
16465 #undef DDR_PHY_DX6GCR4_DXREFIMON_SHIFT
16466 #undef DDR_PHY_DX6GCR4_DXREFIMON_MASK
16467 #define DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL 0x0E00003C
16468 #define DDR_PHY_DX6GCR4_DXREFIMON_SHIFT 0
16469 #define DDR_PHY_DX6GCR4_DXREFIMON_MASK 0x00000003U
16472 * Reserved. Returns zeros on reads.
16474 #undef DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL
16475 #undef DDR_PHY_DX6GCR5_RESERVED_31_SHIFT
16476 #undef DDR_PHY_DX6GCR5_RESERVED_31_MASK
16477 #define DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL 0x09090909
16478 #define DDR_PHY_DX6GCR5_RESERVED_31_SHIFT 31
16479 #define DDR_PHY_DX6GCR5_RESERVED_31_MASK 0x80000000U
16482 * Byte Lane internal VREF Select for Rank 3
16484 #undef DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL
16485 #undef DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT
16486 #undef DDR_PHY_DX6GCR5_DXREFISELR3_MASK
16487 #define DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL 0x09090909
16488 #define DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT 24
16489 #define DDR_PHY_DX6GCR5_DXREFISELR3_MASK 0x7F000000U
16492 * Reserved. Returns zeros on reads.
16494 #undef DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL
16495 #undef DDR_PHY_DX6GCR5_RESERVED_23_SHIFT
16496 #undef DDR_PHY_DX6GCR5_RESERVED_23_MASK
16497 #define DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL 0x09090909
16498 #define DDR_PHY_DX6GCR5_RESERVED_23_SHIFT 23
16499 #define DDR_PHY_DX6GCR5_RESERVED_23_MASK 0x00800000U
16502 * Byte Lane internal VREF Select for Rank 2
16504 #undef DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL
16505 #undef DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT
16506 #undef DDR_PHY_DX6GCR5_DXREFISELR2_MASK
16507 #define DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL 0x09090909
16508 #define DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT 16
16509 #define DDR_PHY_DX6GCR5_DXREFISELR2_MASK 0x007F0000U
16512 * Reserved. Returns zeros on reads.
16514 #undef DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL
16515 #undef DDR_PHY_DX6GCR5_RESERVED_15_SHIFT
16516 #undef DDR_PHY_DX6GCR5_RESERVED_15_MASK
16517 #define DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL 0x09090909
16518 #define DDR_PHY_DX6GCR5_RESERVED_15_SHIFT 15
16519 #define DDR_PHY_DX6GCR5_RESERVED_15_MASK 0x00008000U
16522 * Byte Lane internal VREF Select for Rank 1
16524 #undef DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL
16525 #undef DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT
16526 #undef DDR_PHY_DX6GCR5_DXREFISELR1_MASK
16527 #define DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL 0x09090909
16528 #define DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT 8
16529 #define DDR_PHY_DX6GCR5_DXREFISELR1_MASK 0x00007F00U
16532 * Reserved. Returns zeros on reads.
16534 #undef DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL
16535 #undef DDR_PHY_DX6GCR5_RESERVED_7_SHIFT
16536 #undef DDR_PHY_DX6GCR5_RESERVED_7_MASK
16537 #define DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL 0x09090909
16538 #define DDR_PHY_DX6GCR5_RESERVED_7_SHIFT 7
16539 #define DDR_PHY_DX6GCR5_RESERVED_7_MASK 0x00000080U
16542 * Byte Lane internal VREF Select for Rank 0
16544 #undef DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL
16545 #undef DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT
16546 #undef DDR_PHY_DX6GCR5_DXREFISELR0_MASK
16547 #define DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL 0x09090909
16548 #define DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT 0
16549 #define DDR_PHY_DX6GCR5_DXREFISELR0_MASK 0x0000007FU
16552 * Reserved. Returns zeros on reads.
16554 #undef DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL
16555 #undef DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT
16556 #undef DDR_PHY_DX6GCR6_RESERVED_31_30_MASK
16557 #define DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL 0x09090909
16558 #define DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT 30
16559 #define DDR_PHY_DX6GCR6_RESERVED_31_30_MASK 0xC0000000U
16562 * DRAM DQ VREF Select for Rank3
16564 #undef DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL
16565 #undef DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT
16566 #undef DDR_PHY_DX6GCR6_DXDQVREFR3_MASK
16567 #define DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL 0x09090909
16568 #define DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT 24
16569 #define DDR_PHY_DX6GCR6_DXDQVREFR3_MASK 0x3F000000U
16572 * Reserved. Returns zeros on reads.
16574 #undef DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL
16575 #undef DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT
16576 #undef DDR_PHY_DX6GCR6_RESERVED_23_22_MASK
16577 #define DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL 0x09090909
16578 #define DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT 22
16579 #define DDR_PHY_DX6GCR6_RESERVED_23_22_MASK 0x00C00000U
16582 * DRAM DQ VREF Select for Rank2
16584 #undef DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL
16585 #undef DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT
16586 #undef DDR_PHY_DX6GCR6_DXDQVREFR2_MASK
16587 #define DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL 0x09090909
16588 #define DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT 16
16589 #define DDR_PHY_DX6GCR6_DXDQVREFR2_MASK 0x003F0000U
16592 * Reserved. Returns zeros on reads.
16594 #undef DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL
16595 #undef DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT
16596 #undef DDR_PHY_DX6GCR6_RESERVED_15_14_MASK
16597 #define DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL 0x09090909
16598 #define DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT 14
16599 #define DDR_PHY_DX6GCR6_RESERVED_15_14_MASK 0x0000C000U
16602 * DRAM DQ VREF Select for Rank1
16604 #undef DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL
16605 #undef DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT
16606 #undef DDR_PHY_DX6GCR6_DXDQVREFR1_MASK
16607 #define DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL 0x09090909
16608 #define DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT 8
16609 #define DDR_PHY_DX6GCR6_DXDQVREFR1_MASK 0x00003F00U
16612 * Reserved. Returns zeros on reads.
16614 #undef DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL
16615 #undef DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT
16616 #undef DDR_PHY_DX6GCR6_RESERVED_7_6_MASK
16617 #define DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL 0x09090909
16618 #define DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT 6
16619 #define DDR_PHY_DX6GCR6_RESERVED_7_6_MASK 0x000000C0U
16622 * DRAM DQ VREF Select for Rank0
16624 #undef DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL
16625 #undef DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT
16626 #undef DDR_PHY_DX6GCR6_DXDQVREFR0_MASK
16627 #define DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL 0x09090909
16628 #define DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT 0
16629 #define DDR_PHY_DX6GCR6_DXDQVREFR0_MASK 0x0000003FU
16632 * Calibration Bypass
16634 #undef DDR_PHY_DX7GCR0_CALBYP_DEFVAL
16635 #undef DDR_PHY_DX7GCR0_CALBYP_SHIFT
16636 #undef DDR_PHY_DX7GCR0_CALBYP_MASK
16637 #define DDR_PHY_DX7GCR0_CALBYP_DEFVAL 0x40200204
16638 #define DDR_PHY_DX7GCR0_CALBYP_SHIFT 31
16639 #define DDR_PHY_DX7GCR0_CALBYP_MASK 0x80000000U
16642 * Master Delay Line Enable
16644 #undef DDR_PHY_DX7GCR0_MDLEN_DEFVAL
16645 #undef DDR_PHY_DX7GCR0_MDLEN_SHIFT
16646 #undef DDR_PHY_DX7GCR0_MDLEN_MASK
16647 #define DDR_PHY_DX7GCR0_MDLEN_DEFVAL 0x40200204
16648 #define DDR_PHY_DX7GCR0_MDLEN_SHIFT 30
16649 #define DDR_PHY_DX7GCR0_MDLEN_MASK 0x40000000U
16652 * Configurable ODT(TE) Phase Shift
16654 #undef DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL
16655 #undef DDR_PHY_DX7GCR0_CODTSHFT_SHIFT
16656 #undef DDR_PHY_DX7GCR0_CODTSHFT_MASK
16657 #define DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL 0x40200204
16658 #define DDR_PHY_DX7GCR0_CODTSHFT_SHIFT 28
16659 #define DDR_PHY_DX7GCR0_CODTSHFT_MASK 0x30000000U
16662 * DQS Duty Cycle Correction
16664 #undef DDR_PHY_DX7GCR0_DQSDCC_DEFVAL
16665 #undef DDR_PHY_DX7GCR0_DQSDCC_SHIFT
16666 #undef DDR_PHY_DX7GCR0_DQSDCC_MASK
16667 #define DDR_PHY_DX7GCR0_DQSDCC_DEFVAL 0x40200204
16668 #define DDR_PHY_DX7GCR0_DQSDCC_SHIFT 24
16669 #define DDR_PHY_DX7GCR0_DQSDCC_MASK 0x0F000000U
16672 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
16673 * input for the respective bypte lane of the PHY
16675 #undef DDR_PHY_DX7GCR0_RDDLY_DEFVAL
16676 #undef DDR_PHY_DX7GCR0_RDDLY_SHIFT
16677 #undef DDR_PHY_DX7GCR0_RDDLY_MASK
16678 #define DDR_PHY_DX7GCR0_RDDLY_DEFVAL 0x40200204
16679 #define DDR_PHY_DX7GCR0_RDDLY_SHIFT 20
16680 #define DDR_PHY_DX7GCR0_RDDLY_MASK 0x00F00000U
16683 * Reserved. Return zeroes on reads.
16685 #undef DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL
16686 #undef DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT
16687 #undef DDR_PHY_DX7GCR0_RESERVED_19_14_MASK
16688 #define DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL 0x40200204
16689 #define DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT 14
16690 #define DDR_PHY_DX7GCR0_RESERVED_19_14_MASK 0x000FC000U
16693 * DQSNSE Power Down Receiver
16695 #undef DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL
16696 #undef DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT
16697 #undef DDR_PHY_DX7GCR0_DQSNSEPDR_MASK
16698 #define DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL 0x40200204
16699 #define DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT 13
16700 #define DDR_PHY_DX7GCR0_DQSNSEPDR_MASK 0x00002000U
16703 * DQSSE Power Down Receiver
16705 #undef DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL
16706 #undef DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT
16707 #undef DDR_PHY_DX7GCR0_DQSSEPDR_MASK
16708 #define DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL 0x40200204
16709 #define DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT 12
16710 #define DDR_PHY_DX7GCR0_DQSSEPDR_MASK 0x00001000U
16713 * RTT On Additive Latency
16715 #undef DDR_PHY_DX7GCR0_RTTOAL_DEFVAL
16716 #undef DDR_PHY_DX7GCR0_RTTOAL_SHIFT
16717 #undef DDR_PHY_DX7GCR0_RTTOAL_MASK
16718 #define DDR_PHY_DX7GCR0_RTTOAL_DEFVAL 0x40200204
16719 #define DDR_PHY_DX7GCR0_RTTOAL_SHIFT 11
16720 #define DDR_PHY_DX7GCR0_RTTOAL_MASK 0x00000800U
16725 #undef DDR_PHY_DX7GCR0_RTTOH_DEFVAL
16726 #undef DDR_PHY_DX7GCR0_RTTOH_SHIFT
16727 #undef DDR_PHY_DX7GCR0_RTTOH_MASK
16728 #define DDR_PHY_DX7GCR0_RTTOH_DEFVAL 0x40200204
16729 #define DDR_PHY_DX7GCR0_RTTOH_SHIFT 9
16730 #define DDR_PHY_DX7GCR0_RTTOH_MASK 0x00000600U
16733 * Configurable PDR Phase Shift
16735 #undef DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL
16736 #undef DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT
16737 #undef DDR_PHY_DX7GCR0_CPDRSHFT_MASK
16738 #define DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL 0x40200204
16739 #define DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT 7
16740 #define DDR_PHY_DX7GCR0_CPDRSHFT_MASK 0x00000180U
16745 #undef DDR_PHY_DX7GCR0_DQSRPD_DEFVAL
16746 #undef DDR_PHY_DX7GCR0_DQSRPD_SHIFT
16747 #undef DDR_PHY_DX7GCR0_DQSRPD_MASK
16748 #define DDR_PHY_DX7GCR0_DQSRPD_DEFVAL 0x40200204
16749 #define DDR_PHY_DX7GCR0_DQSRPD_SHIFT 6
16750 #define DDR_PHY_DX7GCR0_DQSRPD_MASK 0x00000040U
16753 * DQSG Power Down Receiver
16755 #undef DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL
16756 #undef DDR_PHY_DX7GCR0_DQSGPDR_SHIFT
16757 #undef DDR_PHY_DX7GCR0_DQSGPDR_MASK
16758 #define DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL 0x40200204
16759 #define DDR_PHY_DX7GCR0_DQSGPDR_SHIFT 5
16760 #define DDR_PHY_DX7GCR0_DQSGPDR_MASK 0x00000020U
16763 * Reserved. Return zeroes on reads.
16765 #undef DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL
16766 #undef DDR_PHY_DX7GCR0_RESERVED_4_SHIFT
16767 #undef DDR_PHY_DX7GCR0_RESERVED_4_MASK
16768 #define DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL 0x40200204
16769 #define DDR_PHY_DX7GCR0_RESERVED_4_SHIFT 4
16770 #define DDR_PHY_DX7GCR0_RESERVED_4_MASK 0x00000010U
16773 * DQSG On-Die Termination
16775 #undef DDR_PHY_DX7GCR0_DQSGODT_DEFVAL
16776 #undef DDR_PHY_DX7GCR0_DQSGODT_SHIFT
16777 #undef DDR_PHY_DX7GCR0_DQSGODT_MASK
16778 #define DDR_PHY_DX7GCR0_DQSGODT_DEFVAL 0x40200204
16779 #define DDR_PHY_DX7GCR0_DQSGODT_SHIFT 3
16780 #define DDR_PHY_DX7GCR0_DQSGODT_MASK 0x00000008U
16783 * DQSG Output Enable
16785 #undef DDR_PHY_DX7GCR0_DQSGOE_DEFVAL
16786 #undef DDR_PHY_DX7GCR0_DQSGOE_SHIFT
16787 #undef DDR_PHY_DX7GCR0_DQSGOE_MASK
16788 #define DDR_PHY_DX7GCR0_DQSGOE_DEFVAL 0x40200204
16789 #define DDR_PHY_DX7GCR0_DQSGOE_SHIFT 2
16790 #define DDR_PHY_DX7GCR0_DQSGOE_MASK 0x00000004U
16793 * Reserved. Return zeroes on reads.
16795 #undef DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL
16796 #undef DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT
16797 #undef DDR_PHY_DX7GCR0_RESERVED_1_0_MASK
16798 #define DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL 0x40200204
16799 #define DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT 0
16800 #define DDR_PHY_DX7GCR0_RESERVED_1_0_MASK 0x00000003U
16803 * Enables the PDR mode for DQ[7:0]
16805 #undef DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL
16806 #undef DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT
16807 #undef DDR_PHY_DX7GCR1_DXPDRMODE_MASK
16808 #define DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL 0x00007FFF
16809 #define DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT 16
16810 #define DDR_PHY_DX7GCR1_DXPDRMODE_MASK 0xFFFF0000U
16813 * Reserved. Returns zeroes on reads.
16815 #undef DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL
16816 #undef DDR_PHY_DX7GCR1_RESERVED_15_SHIFT
16817 #undef DDR_PHY_DX7GCR1_RESERVED_15_MASK
16818 #define DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL 0x00007FFF
16819 #define DDR_PHY_DX7GCR1_RESERVED_15_SHIFT 15
16820 #define DDR_PHY_DX7GCR1_RESERVED_15_MASK 0x00008000U
16823 * Select the delayed or non-delayed read data strobe #
16825 #undef DDR_PHY_DX7GCR1_QSNSEL_DEFVAL
16826 #undef DDR_PHY_DX7GCR1_QSNSEL_SHIFT
16827 #undef DDR_PHY_DX7GCR1_QSNSEL_MASK
16828 #define DDR_PHY_DX7GCR1_QSNSEL_DEFVAL 0x00007FFF
16829 #define DDR_PHY_DX7GCR1_QSNSEL_SHIFT 14
16830 #define DDR_PHY_DX7GCR1_QSNSEL_MASK 0x00004000U
16833 * Select the delayed or non-delayed read data strobe
16835 #undef DDR_PHY_DX7GCR1_QSSEL_DEFVAL
16836 #undef DDR_PHY_DX7GCR1_QSSEL_SHIFT
16837 #undef DDR_PHY_DX7GCR1_QSSEL_MASK
16838 #define DDR_PHY_DX7GCR1_QSSEL_DEFVAL 0x00007FFF
16839 #define DDR_PHY_DX7GCR1_QSSEL_SHIFT 13
16840 #define DDR_PHY_DX7GCR1_QSSEL_MASK 0x00002000U
16843 * Enables Read Data Strobe in a byte lane
16845 #undef DDR_PHY_DX7GCR1_OEEN_DEFVAL
16846 #undef DDR_PHY_DX7GCR1_OEEN_SHIFT
16847 #undef DDR_PHY_DX7GCR1_OEEN_MASK
16848 #define DDR_PHY_DX7GCR1_OEEN_DEFVAL 0x00007FFF
16849 #define DDR_PHY_DX7GCR1_OEEN_SHIFT 12
16850 #define DDR_PHY_DX7GCR1_OEEN_MASK 0x00001000U
16853 * Enables PDR in a byte lane
16855 #undef DDR_PHY_DX7GCR1_PDREN_DEFVAL
16856 #undef DDR_PHY_DX7GCR1_PDREN_SHIFT
16857 #undef DDR_PHY_DX7GCR1_PDREN_MASK
16858 #define DDR_PHY_DX7GCR1_PDREN_DEFVAL 0x00007FFF
16859 #define DDR_PHY_DX7GCR1_PDREN_SHIFT 11
16860 #define DDR_PHY_DX7GCR1_PDREN_MASK 0x00000800U
16863 * Enables ODT/TE in a byte lane
16865 #undef DDR_PHY_DX7GCR1_TEEN_DEFVAL
16866 #undef DDR_PHY_DX7GCR1_TEEN_SHIFT
16867 #undef DDR_PHY_DX7GCR1_TEEN_MASK
16868 #define DDR_PHY_DX7GCR1_TEEN_DEFVAL 0x00007FFF
16869 #define DDR_PHY_DX7GCR1_TEEN_SHIFT 10
16870 #define DDR_PHY_DX7GCR1_TEEN_MASK 0x00000400U
16873 * Enables Write Data strobe in a byte lane
16875 #undef DDR_PHY_DX7GCR1_DSEN_DEFVAL
16876 #undef DDR_PHY_DX7GCR1_DSEN_SHIFT
16877 #undef DDR_PHY_DX7GCR1_DSEN_MASK
16878 #define DDR_PHY_DX7GCR1_DSEN_DEFVAL 0x00007FFF
16879 #define DDR_PHY_DX7GCR1_DSEN_SHIFT 9
16880 #define DDR_PHY_DX7GCR1_DSEN_MASK 0x00000200U
16883 * Enables DM pin in a byte lane
16885 #undef DDR_PHY_DX7GCR1_DMEN_DEFVAL
16886 #undef DDR_PHY_DX7GCR1_DMEN_SHIFT
16887 #undef DDR_PHY_DX7GCR1_DMEN_MASK
16888 #define DDR_PHY_DX7GCR1_DMEN_DEFVAL 0x00007FFF
16889 #define DDR_PHY_DX7GCR1_DMEN_SHIFT 8
16890 #define DDR_PHY_DX7GCR1_DMEN_MASK 0x00000100U
16893 * Enables DQ corresponding to each bit in a byte
16895 #undef DDR_PHY_DX7GCR1_DQEN_DEFVAL
16896 #undef DDR_PHY_DX7GCR1_DQEN_SHIFT
16897 #undef DDR_PHY_DX7GCR1_DQEN_MASK
16898 #define DDR_PHY_DX7GCR1_DQEN_DEFVAL 0x00007FFF
16899 #define DDR_PHY_DX7GCR1_DQEN_SHIFT 0
16900 #define DDR_PHY_DX7GCR1_DQEN_MASK 0x000000FFU
16903 * Byte lane VREF IOM (Used only by D4MU IOs)
16905 #undef DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL
16906 #undef DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT
16907 #undef DDR_PHY_DX7GCR4_RESERVED_31_29_MASK
16908 #define DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL 0x0E00003C
16909 #define DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT 29
16910 #define DDR_PHY_DX7GCR4_RESERVED_31_29_MASK 0xE0000000U
16913 * Byte Lane VREF Pad Enable
16915 #undef DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL
16916 #undef DDR_PHY_DX7GCR4_DXREFPEN_SHIFT
16917 #undef DDR_PHY_DX7GCR4_DXREFPEN_MASK
16918 #define DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL 0x0E00003C
16919 #define DDR_PHY_DX7GCR4_DXREFPEN_SHIFT 28
16920 #define DDR_PHY_DX7GCR4_DXREFPEN_MASK 0x10000000U
16923 * Byte Lane Internal VREF Enable
16925 #undef DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL
16926 #undef DDR_PHY_DX7GCR4_DXREFEEN_SHIFT
16927 #undef DDR_PHY_DX7GCR4_DXREFEEN_MASK
16928 #define DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL 0x0E00003C
16929 #define DDR_PHY_DX7GCR4_DXREFEEN_SHIFT 26
16930 #define DDR_PHY_DX7GCR4_DXREFEEN_MASK 0x0C000000U
16933 * Byte Lane Single-End VREF Enable
16935 #undef DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL
16936 #undef DDR_PHY_DX7GCR4_DXREFSEN_SHIFT
16937 #undef DDR_PHY_DX7GCR4_DXREFSEN_MASK
16938 #define DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL 0x0E00003C
16939 #define DDR_PHY_DX7GCR4_DXREFSEN_SHIFT 25
16940 #define DDR_PHY_DX7GCR4_DXREFSEN_MASK 0x02000000U
16943 * Reserved. Returns zeros on reads.
16945 #undef DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL
16946 #undef DDR_PHY_DX7GCR4_RESERVED_24_SHIFT
16947 #undef DDR_PHY_DX7GCR4_RESERVED_24_MASK
16948 #define DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL 0x0E00003C
16949 #define DDR_PHY_DX7GCR4_RESERVED_24_SHIFT 24
16950 #define DDR_PHY_DX7GCR4_RESERVED_24_MASK 0x01000000U
16953 * External VREF generator REFSEL range select
16955 #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL
16956 #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT
16957 #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK
16958 #define DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C
16959 #define DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT 23
16960 #define DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK 0x00800000U
16963 * Byte Lane External VREF Select
16965 #undef DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL
16966 #undef DDR_PHY_DX7GCR4_DXREFESEL_SHIFT
16967 #undef DDR_PHY_DX7GCR4_DXREFESEL_MASK
16968 #define DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL 0x0E00003C
16969 #define DDR_PHY_DX7GCR4_DXREFESEL_SHIFT 16
16970 #define DDR_PHY_DX7GCR4_DXREFESEL_MASK 0x007F0000U
16973 * Single ended VREF generator REFSEL range select
16975 #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL
16976 #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT
16977 #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK
16978 #define DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C
16979 #define DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT 15
16980 #define DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK 0x00008000U
16983 * Byte Lane Single-End VREF Select
16985 #undef DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL
16986 #undef DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT
16987 #undef DDR_PHY_DX7GCR4_DXREFSSEL_MASK
16988 #define DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL 0x0E00003C
16989 #define DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT 8
16990 #define DDR_PHY_DX7GCR4_DXREFSSEL_MASK 0x00007F00U
16993 * Reserved. Returns zeros on reads.
16995 #undef DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL
16996 #undef DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT
16997 #undef DDR_PHY_DX7GCR4_RESERVED_7_6_MASK
16998 #define DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL 0x0E00003C
16999 #define DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT 6
17000 #define DDR_PHY_DX7GCR4_RESERVED_7_6_MASK 0x000000C0U
17003 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
17005 #undef DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL
17006 #undef DDR_PHY_DX7GCR4_DXREFIEN_SHIFT
17007 #undef DDR_PHY_DX7GCR4_DXREFIEN_MASK
17008 #define DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL 0x0E00003C
17009 #define DDR_PHY_DX7GCR4_DXREFIEN_SHIFT 2
17010 #define DDR_PHY_DX7GCR4_DXREFIEN_MASK 0x0000003CU
17013 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
17015 #undef DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL
17016 #undef DDR_PHY_DX7GCR4_DXREFIMON_SHIFT
17017 #undef DDR_PHY_DX7GCR4_DXREFIMON_MASK
17018 #define DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL 0x0E00003C
17019 #define DDR_PHY_DX7GCR4_DXREFIMON_SHIFT 0
17020 #define DDR_PHY_DX7GCR4_DXREFIMON_MASK 0x00000003U
17023 * Reserved. Returns zeros on reads.
17025 #undef DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL
17026 #undef DDR_PHY_DX7GCR5_RESERVED_31_SHIFT
17027 #undef DDR_PHY_DX7GCR5_RESERVED_31_MASK
17028 #define DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL 0x09090909
17029 #define DDR_PHY_DX7GCR5_RESERVED_31_SHIFT 31
17030 #define DDR_PHY_DX7GCR5_RESERVED_31_MASK 0x80000000U
17033 * Byte Lane internal VREF Select for Rank 3
17035 #undef DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL
17036 #undef DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT
17037 #undef DDR_PHY_DX7GCR5_DXREFISELR3_MASK
17038 #define DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL 0x09090909
17039 #define DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT 24
17040 #define DDR_PHY_DX7GCR5_DXREFISELR3_MASK 0x7F000000U
17043 * Reserved. Returns zeros on reads.
17045 #undef DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL
17046 #undef DDR_PHY_DX7GCR5_RESERVED_23_SHIFT
17047 #undef DDR_PHY_DX7GCR5_RESERVED_23_MASK
17048 #define DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL 0x09090909
17049 #define DDR_PHY_DX7GCR5_RESERVED_23_SHIFT 23
17050 #define DDR_PHY_DX7GCR5_RESERVED_23_MASK 0x00800000U
17053 * Byte Lane internal VREF Select for Rank 2
17055 #undef DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL
17056 #undef DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT
17057 #undef DDR_PHY_DX7GCR5_DXREFISELR2_MASK
17058 #define DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL 0x09090909
17059 #define DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT 16
17060 #define DDR_PHY_DX7GCR5_DXREFISELR2_MASK 0x007F0000U
17063 * Reserved. Returns zeros on reads.
17065 #undef DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL
17066 #undef DDR_PHY_DX7GCR5_RESERVED_15_SHIFT
17067 #undef DDR_PHY_DX7GCR5_RESERVED_15_MASK
17068 #define DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL 0x09090909
17069 #define DDR_PHY_DX7GCR5_RESERVED_15_SHIFT 15
17070 #define DDR_PHY_DX7GCR5_RESERVED_15_MASK 0x00008000U
17073 * Byte Lane internal VREF Select for Rank 1
17075 #undef DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL
17076 #undef DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT
17077 #undef DDR_PHY_DX7GCR5_DXREFISELR1_MASK
17078 #define DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL 0x09090909
17079 #define DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT 8
17080 #define DDR_PHY_DX7GCR5_DXREFISELR1_MASK 0x00007F00U
17083 * Reserved. Returns zeros on reads.
17085 #undef DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL
17086 #undef DDR_PHY_DX7GCR5_RESERVED_7_SHIFT
17087 #undef DDR_PHY_DX7GCR5_RESERVED_7_MASK
17088 #define DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL 0x09090909
17089 #define DDR_PHY_DX7GCR5_RESERVED_7_SHIFT 7
17090 #define DDR_PHY_DX7GCR5_RESERVED_7_MASK 0x00000080U
17093 * Byte Lane internal VREF Select for Rank 0
17095 #undef DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL
17096 #undef DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT
17097 #undef DDR_PHY_DX7GCR5_DXREFISELR0_MASK
17098 #define DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL 0x09090909
17099 #define DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT 0
17100 #define DDR_PHY_DX7GCR5_DXREFISELR0_MASK 0x0000007FU
17103 * Reserved. Returns zeros on reads.
17105 #undef DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL
17106 #undef DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT
17107 #undef DDR_PHY_DX7GCR6_RESERVED_31_30_MASK
17108 #define DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL 0x09090909
17109 #define DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT 30
17110 #define DDR_PHY_DX7GCR6_RESERVED_31_30_MASK 0xC0000000U
17113 * DRAM DQ VREF Select for Rank3
17115 #undef DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL
17116 #undef DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT
17117 #undef DDR_PHY_DX7GCR6_DXDQVREFR3_MASK
17118 #define DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL 0x09090909
17119 #define DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT 24
17120 #define DDR_PHY_DX7GCR6_DXDQVREFR3_MASK 0x3F000000U
17123 * Reserved. Returns zeros on reads.
17125 #undef DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL
17126 #undef DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT
17127 #undef DDR_PHY_DX7GCR6_RESERVED_23_22_MASK
17128 #define DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL 0x09090909
17129 #define DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT 22
17130 #define DDR_PHY_DX7GCR6_RESERVED_23_22_MASK 0x00C00000U
17133 * DRAM DQ VREF Select for Rank2
17135 #undef DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL
17136 #undef DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT
17137 #undef DDR_PHY_DX7GCR6_DXDQVREFR2_MASK
17138 #define DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL 0x09090909
17139 #define DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT 16
17140 #define DDR_PHY_DX7GCR6_DXDQVREFR2_MASK 0x003F0000U
17143 * Reserved. Returns zeros on reads.
17145 #undef DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL
17146 #undef DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT
17147 #undef DDR_PHY_DX7GCR6_RESERVED_15_14_MASK
17148 #define DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL 0x09090909
17149 #define DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT 14
17150 #define DDR_PHY_DX7GCR6_RESERVED_15_14_MASK 0x0000C000U
17153 * DRAM DQ VREF Select for Rank1
17155 #undef DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL
17156 #undef DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT
17157 #undef DDR_PHY_DX7GCR6_DXDQVREFR1_MASK
17158 #define DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL 0x09090909
17159 #define DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT 8
17160 #define DDR_PHY_DX7GCR6_DXDQVREFR1_MASK 0x00003F00U
17163 * Reserved. Returns zeros on reads.
17165 #undef DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL
17166 #undef DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT
17167 #undef DDR_PHY_DX7GCR6_RESERVED_7_6_MASK
17168 #define DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL 0x09090909
17169 #define DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT 6
17170 #define DDR_PHY_DX7GCR6_RESERVED_7_6_MASK 0x000000C0U
17173 * DRAM DQ VREF Select for Rank0
17175 #undef DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL
17176 #undef DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT
17177 #undef DDR_PHY_DX7GCR6_DXDQVREFR0_MASK
17178 #define DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL 0x09090909
17179 #define DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT 0
17180 #define DDR_PHY_DX7GCR6_DXDQVREFR0_MASK 0x0000003FU
17183 * Calibration Bypass
17185 #undef DDR_PHY_DX8GCR0_CALBYP_DEFVAL
17186 #undef DDR_PHY_DX8GCR0_CALBYP_SHIFT
17187 #undef DDR_PHY_DX8GCR0_CALBYP_MASK
17188 #define DDR_PHY_DX8GCR0_CALBYP_DEFVAL 0x40200204
17189 #define DDR_PHY_DX8GCR0_CALBYP_SHIFT 31
17190 #define DDR_PHY_DX8GCR0_CALBYP_MASK 0x80000000U
17193 * Master Delay Line Enable
17195 #undef DDR_PHY_DX8GCR0_MDLEN_DEFVAL
17196 #undef DDR_PHY_DX8GCR0_MDLEN_SHIFT
17197 #undef DDR_PHY_DX8GCR0_MDLEN_MASK
17198 #define DDR_PHY_DX8GCR0_MDLEN_DEFVAL 0x40200204
17199 #define DDR_PHY_DX8GCR0_MDLEN_SHIFT 30
17200 #define DDR_PHY_DX8GCR0_MDLEN_MASK 0x40000000U
17203 * Configurable ODT(TE) Phase Shift
17205 #undef DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL
17206 #undef DDR_PHY_DX8GCR0_CODTSHFT_SHIFT
17207 #undef DDR_PHY_DX8GCR0_CODTSHFT_MASK
17208 #define DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL 0x40200204
17209 #define DDR_PHY_DX8GCR0_CODTSHFT_SHIFT 28
17210 #define DDR_PHY_DX8GCR0_CODTSHFT_MASK 0x30000000U
17213 * DQS Duty Cycle Correction
17215 #undef DDR_PHY_DX8GCR0_DQSDCC_DEFVAL
17216 #undef DDR_PHY_DX8GCR0_DQSDCC_SHIFT
17217 #undef DDR_PHY_DX8GCR0_DQSDCC_MASK
17218 #define DDR_PHY_DX8GCR0_DQSDCC_DEFVAL 0x40200204
17219 #define DDR_PHY_DX8GCR0_DQSDCC_SHIFT 24
17220 #define DDR_PHY_DX8GCR0_DQSDCC_MASK 0x0F000000U
17223 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
17224 * input for the respective bypte lane of the PHY
17226 #undef DDR_PHY_DX8GCR0_RDDLY_DEFVAL
17227 #undef DDR_PHY_DX8GCR0_RDDLY_SHIFT
17228 #undef DDR_PHY_DX8GCR0_RDDLY_MASK
17229 #define DDR_PHY_DX8GCR0_RDDLY_DEFVAL 0x40200204
17230 #define DDR_PHY_DX8GCR0_RDDLY_SHIFT 20
17231 #define DDR_PHY_DX8GCR0_RDDLY_MASK 0x00F00000U
17234 * Reserved. Return zeroes on reads.
17236 #undef DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL
17237 #undef DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT
17238 #undef DDR_PHY_DX8GCR0_RESERVED_19_14_MASK
17239 #define DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL 0x40200204
17240 #define DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT 14
17241 #define DDR_PHY_DX8GCR0_RESERVED_19_14_MASK 0x000FC000U
17244 * DQSNSE Power Down Receiver
17246 #undef DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL
17247 #undef DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT
17248 #undef DDR_PHY_DX8GCR0_DQSNSEPDR_MASK
17249 #define DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL 0x40200204
17250 #define DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT 13
17251 #define DDR_PHY_DX8GCR0_DQSNSEPDR_MASK 0x00002000U
17254 * DQSSE Power Down Receiver
17256 #undef DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL
17257 #undef DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT
17258 #undef DDR_PHY_DX8GCR0_DQSSEPDR_MASK
17259 #define DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL 0x40200204
17260 #define DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT 12
17261 #define DDR_PHY_DX8GCR0_DQSSEPDR_MASK 0x00001000U
17264 * RTT On Additive Latency
17266 #undef DDR_PHY_DX8GCR0_RTTOAL_DEFVAL
17267 #undef DDR_PHY_DX8GCR0_RTTOAL_SHIFT
17268 #undef DDR_PHY_DX8GCR0_RTTOAL_MASK
17269 #define DDR_PHY_DX8GCR0_RTTOAL_DEFVAL 0x40200204
17270 #define DDR_PHY_DX8GCR0_RTTOAL_SHIFT 11
17271 #define DDR_PHY_DX8GCR0_RTTOAL_MASK 0x00000800U
17276 #undef DDR_PHY_DX8GCR0_RTTOH_DEFVAL
17277 #undef DDR_PHY_DX8GCR0_RTTOH_SHIFT
17278 #undef DDR_PHY_DX8GCR0_RTTOH_MASK
17279 #define DDR_PHY_DX8GCR0_RTTOH_DEFVAL 0x40200204
17280 #define DDR_PHY_DX8GCR0_RTTOH_SHIFT 9
17281 #define DDR_PHY_DX8GCR0_RTTOH_MASK 0x00000600U
17284 * Configurable PDR Phase Shift
17286 #undef DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL
17287 #undef DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT
17288 #undef DDR_PHY_DX8GCR0_CPDRSHFT_MASK
17289 #define DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL 0x40200204
17290 #define DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT 7
17291 #define DDR_PHY_DX8GCR0_CPDRSHFT_MASK 0x00000180U
17296 #undef DDR_PHY_DX8GCR0_DQSRPD_DEFVAL
17297 #undef DDR_PHY_DX8GCR0_DQSRPD_SHIFT
17298 #undef DDR_PHY_DX8GCR0_DQSRPD_MASK
17299 #define DDR_PHY_DX8GCR0_DQSRPD_DEFVAL 0x40200204
17300 #define DDR_PHY_DX8GCR0_DQSRPD_SHIFT 6
17301 #define DDR_PHY_DX8GCR0_DQSRPD_MASK 0x00000040U
17304 * DQSG Power Down Receiver
17306 #undef DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL
17307 #undef DDR_PHY_DX8GCR0_DQSGPDR_SHIFT
17308 #undef DDR_PHY_DX8GCR0_DQSGPDR_MASK
17309 #define DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL 0x40200204
17310 #define DDR_PHY_DX8GCR0_DQSGPDR_SHIFT 5
17311 #define DDR_PHY_DX8GCR0_DQSGPDR_MASK 0x00000020U
17314 * Reserved. Return zeroes on reads.
17316 #undef DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL
17317 #undef DDR_PHY_DX8GCR0_RESERVED_4_SHIFT
17318 #undef DDR_PHY_DX8GCR0_RESERVED_4_MASK
17319 #define DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL 0x40200204
17320 #define DDR_PHY_DX8GCR0_RESERVED_4_SHIFT 4
17321 #define DDR_PHY_DX8GCR0_RESERVED_4_MASK 0x00000010U
17324 * DQSG On-Die Termination
17326 #undef DDR_PHY_DX8GCR0_DQSGODT_DEFVAL
17327 #undef DDR_PHY_DX8GCR0_DQSGODT_SHIFT
17328 #undef DDR_PHY_DX8GCR0_DQSGODT_MASK
17329 #define DDR_PHY_DX8GCR0_DQSGODT_DEFVAL 0x40200204
17330 #define DDR_PHY_DX8GCR0_DQSGODT_SHIFT 3
17331 #define DDR_PHY_DX8GCR0_DQSGODT_MASK 0x00000008U
17334 * DQSG Output Enable
17336 #undef DDR_PHY_DX8GCR0_DQSGOE_DEFVAL
17337 #undef DDR_PHY_DX8GCR0_DQSGOE_SHIFT
17338 #undef DDR_PHY_DX8GCR0_DQSGOE_MASK
17339 #define DDR_PHY_DX8GCR0_DQSGOE_DEFVAL 0x40200204
17340 #define DDR_PHY_DX8GCR0_DQSGOE_SHIFT 2
17341 #define DDR_PHY_DX8GCR0_DQSGOE_MASK 0x00000004U
17344 * Reserved. Return zeroes on reads.
17346 #undef DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL
17347 #undef DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT
17348 #undef DDR_PHY_DX8GCR0_RESERVED_1_0_MASK
17349 #define DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL 0x40200204
17350 #define DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT 0
17351 #define DDR_PHY_DX8GCR0_RESERVED_1_0_MASK 0x00000003U
17354 * Enables the PDR mode for DQ[7:0]
17356 #undef DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL
17357 #undef DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT
17358 #undef DDR_PHY_DX8GCR1_DXPDRMODE_MASK
17359 #define DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL 0x00007FFF
17360 #define DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT 16
17361 #define DDR_PHY_DX8GCR1_DXPDRMODE_MASK 0xFFFF0000U
17364 * Reserved. Returns zeroes on reads.
17366 #undef DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL
17367 #undef DDR_PHY_DX8GCR1_RESERVED_15_SHIFT
17368 #undef DDR_PHY_DX8GCR1_RESERVED_15_MASK
17369 #define DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL 0x00007FFF
17370 #define DDR_PHY_DX8GCR1_RESERVED_15_SHIFT 15
17371 #define DDR_PHY_DX8GCR1_RESERVED_15_MASK 0x00008000U
17374 * Select the delayed or non-delayed read data strobe #
17376 #undef DDR_PHY_DX8GCR1_QSNSEL_DEFVAL
17377 #undef DDR_PHY_DX8GCR1_QSNSEL_SHIFT
17378 #undef DDR_PHY_DX8GCR1_QSNSEL_MASK
17379 #define DDR_PHY_DX8GCR1_QSNSEL_DEFVAL 0x00007FFF
17380 #define DDR_PHY_DX8GCR1_QSNSEL_SHIFT 14
17381 #define DDR_PHY_DX8GCR1_QSNSEL_MASK 0x00004000U
17384 * Select the delayed or non-delayed read data strobe
17386 #undef DDR_PHY_DX8GCR1_QSSEL_DEFVAL
17387 #undef DDR_PHY_DX8GCR1_QSSEL_SHIFT
17388 #undef DDR_PHY_DX8GCR1_QSSEL_MASK
17389 #define DDR_PHY_DX8GCR1_QSSEL_DEFVAL 0x00007FFF
17390 #define DDR_PHY_DX8GCR1_QSSEL_SHIFT 13
17391 #define DDR_PHY_DX8GCR1_QSSEL_MASK 0x00002000U
17394 * Enables Read Data Strobe in a byte lane
17396 #undef DDR_PHY_DX8GCR1_OEEN_DEFVAL
17397 #undef DDR_PHY_DX8GCR1_OEEN_SHIFT
17398 #undef DDR_PHY_DX8GCR1_OEEN_MASK
17399 #define DDR_PHY_DX8GCR1_OEEN_DEFVAL 0x00007FFF
17400 #define DDR_PHY_DX8GCR1_OEEN_SHIFT 12
17401 #define DDR_PHY_DX8GCR1_OEEN_MASK 0x00001000U
17404 * Enables PDR in a byte lane
17406 #undef DDR_PHY_DX8GCR1_PDREN_DEFVAL
17407 #undef DDR_PHY_DX8GCR1_PDREN_SHIFT
17408 #undef DDR_PHY_DX8GCR1_PDREN_MASK
17409 #define DDR_PHY_DX8GCR1_PDREN_DEFVAL 0x00007FFF
17410 #define DDR_PHY_DX8GCR1_PDREN_SHIFT 11
17411 #define DDR_PHY_DX8GCR1_PDREN_MASK 0x00000800U
17414 * Enables ODT/TE in a byte lane
17416 #undef DDR_PHY_DX8GCR1_TEEN_DEFVAL
17417 #undef DDR_PHY_DX8GCR1_TEEN_SHIFT
17418 #undef DDR_PHY_DX8GCR1_TEEN_MASK
17419 #define DDR_PHY_DX8GCR1_TEEN_DEFVAL 0x00007FFF
17420 #define DDR_PHY_DX8GCR1_TEEN_SHIFT 10
17421 #define DDR_PHY_DX8GCR1_TEEN_MASK 0x00000400U
17424 * Enables Write Data strobe in a byte lane
17426 #undef DDR_PHY_DX8GCR1_DSEN_DEFVAL
17427 #undef DDR_PHY_DX8GCR1_DSEN_SHIFT
17428 #undef DDR_PHY_DX8GCR1_DSEN_MASK
17429 #define DDR_PHY_DX8GCR1_DSEN_DEFVAL 0x00007FFF
17430 #define DDR_PHY_DX8GCR1_DSEN_SHIFT 9
17431 #define DDR_PHY_DX8GCR1_DSEN_MASK 0x00000200U
17434 * Enables DM pin in a byte lane
17436 #undef DDR_PHY_DX8GCR1_DMEN_DEFVAL
17437 #undef DDR_PHY_DX8GCR1_DMEN_SHIFT
17438 #undef DDR_PHY_DX8GCR1_DMEN_MASK
17439 #define DDR_PHY_DX8GCR1_DMEN_DEFVAL 0x00007FFF
17440 #define DDR_PHY_DX8GCR1_DMEN_SHIFT 8
17441 #define DDR_PHY_DX8GCR1_DMEN_MASK 0x00000100U
17444 * Enables DQ corresponding to each bit in a byte
17446 #undef DDR_PHY_DX8GCR1_DQEN_DEFVAL
17447 #undef DDR_PHY_DX8GCR1_DQEN_SHIFT
17448 #undef DDR_PHY_DX8GCR1_DQEN_MASK
17449 #define DDR_PHY_DX8GCR1_DQEN_DEFVAL 0x00007FFF
17450 #define DDR_PHY_DX8GCR1_DQEN_SHIFT 0
17451 #define DDR_PHY_DX8GCR1_DQEN_MASK 0x000000FFU
17454 * Byte lane VREF IOM (Used only by D4MU IOs)
17456 #undef DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL
17457 #undef DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT
17458 #undef DDR_PHY_DX8GCR4_RESERVED_31_29_MASK
17459 #define DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL 0x0E00003C
17460 #define DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT 29
17461 #define DDR_PHY_DX8GCR4_RESERVED_31_29_MASK 0xE0000000U
17464 * Byte Lane VREF Pad Enable
17466 #undef DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL
17467 #undef DDR_PHY_DX8GCR4_DXREFPEN_SHIFT
17468 #undef DDR_PHY_DX8GCR4_DXREFPEN_MASK
17469 #define DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL 0x0E00003C
17470 #define DDR_PHY_DX8GCR4_DXREFPEN_SHIFT 28
17471 #define DDR_PHY_DX8GCR4_DXREFPEN_MASK 0x10000000U
17474 * Byte Lane Internal VREF Enable
17476 #undef DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL
17477 #undef DDR_PHY_DX8GCR4_DXREFEEN_SHIFT
17478 #undef DDR_PHY_DX8GCR4_DXREFEEN_MASK
17479 #define DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL 0x0E00003C
17480 #define DDR_PHY_DX8GCR4_DXREFEEN_SHIFT 26
17481 #define DDR_PHY_DX8GCR4_DXREFEEN_MASK 0x0C000000U
17484 * Byte Lane Single-End VREF Enable
17486 #undef DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL
17487 #undef DDR_PHY_DX8GCR4_DXREFSEN_SHIFT
17488 #undef DDR_PHY_DX8GCR4_DXREFSEN_MASK
17489 #define DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL 0x0E00003C
17490 #define DDR_PHY_DX8GCR4_DXREFSEN_SHIFT 25
17491 #define DDR_PHY_DX8GCR4_DXREFSEN_MASK 0x02000000U
17494 * Reserved. Returns zeros on reads.
17496 #undef DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL
17497 #undef DDR_PHY_DX8GCR4_RESERVED_24_SHIFT
17498 #undef DDR_PHY_DX8GCR4_RESERVED_24_MASK
17499 #define DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL 0x0E00003C
17500 #define DDR_PHY_DX8GCR4_RESERVED_24_SHIFT 24
17501 #define DDR_PHY_DX8GCR4_RESERVED_24_MASK 0x01000000U
17504 * External VREF generator REFSEL range select
17506 #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL
17507 #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT
17508 #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK
17509 #define DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C
17510 #define DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT 23
17511 #define DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK 0x00800000U
17514 * Byte Lane External VREF Select
17516 #undef DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL
17517 #undef DDR_PHY_DX8GCR4_DXREFESEL_SHIFT
17518 #undef DDR_PHY_DX8GCR4_DXREFESEL_MASK
17519 #define DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL 0x0E00003C
17520 #define DDR_PHY_DX8GCR4_DXREFESEL_SHIFT 16
17521 #define DDR_PHY_DX8GCR4_DXREFESEL_MASK 0x007F0000U
17524 * Single ended VREF generator REFSEL range select
17526 #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL
17527 #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT
17528 #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK
17529 #define DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C
17530 #define DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT 15
17531 #define DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK 0x00008000U
17534 * Byte Lane Single-End VREF Select
17536 #undef DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL
17537 #undef DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT
17538 #undef DDR_PHY_DX8GCR4_DXREFSSEL_MASK
17539 #define DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL 0x0E00003C
17540 #define DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT 8
17541 #define DDR_PHY_DX8GCR4_DXREFSSEL_MASK 0x00007F00U
17544 * Reserved. Returns zeros on reads.
17546 #undef DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL
17547 #undef DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT
17548 #undef DDR_PHY_DX8GCR4_RESERVED_7_6_MASK
17549 #define DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL 0x0E00003C
17550 #define DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT 6
17551 #define DDR_PHY_DX8GCR4_RESERVED_7_6_MASK 0x000000C0U
17554 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
17556 #undef DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL
17557 #undef DDR_PHY_DX8GCR4_DXREFIEN_SHIFT
17558 #undef DDR_PHY_DX8GCR4_DXREFIEN_MASK
17559 #define DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL 0x0E00003C
17560 #define DDR_PHY_DX8GCR4_DXREFIEN_SHIFT 2
17561 #define DDR_PHY_DX8GCR4_DXREFIEN_MASK 0x0000003CU
17564 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
17566 #undef DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL
17567 #undef DDR_PHY_DX8GCR4_DXREFIMON_SHIFT
17568 #undef DDR_PHY_DX8GCR4_DXREFIMON_MASK
17569 #define DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL 0x0E00003C
17570 #define DDR_PHY_DX8GCR4_DXREFIMON_SHIFT 0
17571 #define DDR_PHY_DX8GCR4_DXREFIMON_MASK 0x00000003U
17574 * Reserved. Returns zeros on reads.
17576 #undef DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL
17577 #undef DDR_PHY_DX8GCR5_RESERVED_31_SHIFT
17578 #undef DDR_PHY_DX8GCR5_RESERVED_31_MASK
17579 #define DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL 0x09090909
17580 #define DDR_PHY_DX8GCR5_RESERVED_31_SHIFT 31
17581 #define DDR_PHY_DX8GCR5_RESERVED_31_MASK 0x80000000U
17584 * Byte Lane internal VREF Select for Rank 3
17586 #undef DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL
17587 #undef DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT
17588 #undef DDR_PHY_DX8GCR5_DXREFISELR3_MASK
17589 #define DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL 0x09090909
17590 #define DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT 24
17591 #define DDR_PHY_DX8GCR5_DXREFISELR3_MASK 0x7F000000U
17594 * Reserved. Returns zeros on reads.
17596 #undef DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL
17597 #undef DDR_PHY_DX8GCR5_RESERVED_23_SHIFT
17598 #undef DDR_PHY_DX8GCR5_RESERVED_23_MASK
17599 #define DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL 0x09090909
17600 #define DDR_PHY_DX8GCR5_RESERVED_23_SHIFT 23
17601 #define DDR_PHY_DX8GCR5_RESERVED_23_MASK 0x00800000U
17604 * Byte Lane internal VREF Select for Rank 2
17606 #undef DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL
17607 #undef DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT
17608 #undef DDR_PHY_DX8GCR5_DXREFISELR2_MASK
17609 #define DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL 0x09090909
17610 #define DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT 16
17611 #define DDR_PHY_DX8GCR5_DXREFISELR2_MASK 0x007F0000U
17614 * Reserved. Returns zeros on reads.
17616 #undef DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL
17617 #undef DDR_PHY_DX8GCR5_RESERVED_15_SHIFT
17618 #undef DDR_PHY_DX8GCR5_RESERVED_15_MASK
17619 #define DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL 0x09090909
17620 #define DDR_PHY_DX8GCR5_RESERVED_15_SHIFT 15
17621 #define DDR_PHY_DX8GCR5_RESERVED_15_MASK 0x00008000U
17624 * Byte Lane internal VREF Select for Rank 1
17626 #undef DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL
17627 #undef DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT
17628 #undef DDR_PHY_DX8GCR5_DXREFISELR1_MASK
17629 #define DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL 0x09090909
17630 #define DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT 8
17631 #define DDR_PHY_DX8GCR5_DXREFISELR1_MASK 0x00007F00U
17634 * Reserved. Returns zeros on reads.
17636 #undef DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL
17637 #undef DDR_PHY_DX8GCR5_RESERVED_7_SHIFT
17638 #undef DDR_PHY_DX8GCR5_RESERVED_7_MASK
17639 #define DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL 0x09090909
17640 #define DDR_PHY_DX8GCR5_RESERVED_7_SHIFT 7
17641 #define DDR_PHY_DX8GCR5_RESERVED_7_MASK 0x00000080U
17644 * Byte Lane internal VREF Select for Rank 0
17646 #undef DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL
17647 #undef DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT
17648 #undef DDR_PHY_DX8GCR5_DXREFISELR0_MASK
17649 #define DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL 0x09090909
17650 #define DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT 0
17651 #define DDR_PHY_DX8GCR5_DXREFISELR0_MASK 0x0000007FU
17654 * Reserved. Returns zeros on reads.
17656 #undef DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL
17657 #undef DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT
17658 #undef DDR_PHY_DX8GCR6_RESERVED_31_30_MASK
17659 #define DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL 0x09090909
17660 #define DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT 30
17661 #define DDR_PHY_DX8GCR6_RESERVED_31_30_MASK 0xC0000000U
17664 * DRAM DQ VREF Select for Rank3
17666 #undef DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL
17667 #undef DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT
17668 #undef DDR_PHY_DX8GCR6_DXDQVREFR3_MASK
17669 #define DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL 0x09090909
17670 #define DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT 24
17671 #define DDR_PHY_DX8GCR6_DXDQVREFR3_MASK 0x3F000000U
17674 * Reserved. Returns zeros on reads.
17676 #undef DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL
17677 #undef DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT
17678 #undef DDR_PHY_DX8GCR6_RESERVED_23_22_MASK
17679 #define DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL 0x09090909
17680 #define DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT 22
17681 #define DDR_PHY_DX8GCR6_RESERVED_23_22_MASK 0x00C00000U
17684 * DRAM DQ VREF Select for Rank2
17686 #undef DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL
17687 #undef DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT
17688 #undef DDR_PHY_DX8GCR6_DXDQVREFR2_MASK
17689 #define DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL 0x09090909
17690 #define DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT 16
17691 #define DDR_PHY_DX8GCR6_DXDQVREFR2_MASK 0x003F0000U
17694 * Reserved. Returns zeros on reads.
17696 #undef DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL
17697 #undef DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT
17698 #undef DDR_PHY_DX8GCR6_RESERVED_15_14_MASK
17699 #define DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL 0x09090909
17700 #define DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT 14
17701 #define DDR_PHY_DX8GCR6_RESERVED_15_14_MASK 0x0000C000U
17704 * DRAM DQ VREF Select for Rank1
17706 #undef DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL
17707 #undef DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT
17708 #undef DDR_PHY_DX8GCR6_DXDQVREFR1_MASK
17709 #define DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL 0x09090909
17710 #define DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT 8
17711 #define DDR_PHY_DX8GCR6_DXDQVREFR1_MASK 0x00003F00U
17714 * Reserved. Returns zeros on reads.
17716 #undef DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL
17717 #undef DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT
17718 #undef DDR_PHY_DX8GCR6_RESERVED_7_6_MASK
17719 #define DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL 0x09090909
17720 #define DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT 6
17721 #define DDR_PHY_DX8GCR6_RESERVED_7_6_MASK 0x000000C0U
17724 * DRAM DQ VREF Select for Rank0
17726 #undef DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL
17727 #undef DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT
17728 #undef DDR_PHY_DX8GCR6_DXDQVREFR0_MASK
17729 #define DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL 0x09090909
17730 #define DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT 0
17731 #define DDR_PHY_DX8GCR6_DXDQVREFR0_MASK 0x0000003FU
17734 * Reserved. Return zeroes on reads.
17736 #undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL
17737 #undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT
17738 #undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK
17739 #define DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL 0x00019FFE
17740 #define DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT 30
17741 #define DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK 0xC0000000U
17744 * Enable Clock Gating for DX ddr_clk
17746 #undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL
17747 #undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT
17748 #undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK
17749 #define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL 0x00019FFE
17750 #define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT 28
17751 #define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK 0x30000000U
17754 * Enable Clock Gating for DX ctl_rd_clk
17756 #undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL
17757 #undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT
17758 #undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK
17759 #define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE
17760 #define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT 26
17761 #define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK 0x0C000000U
17764 * Enable Clock Gating for DX ctl_clk
17766 #undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL
17767 #undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT
17768 #undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK
17769 #define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE
17770 #define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT 24
17771 #define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK 0x03000000U
17774 * Selects the level to which clocks will be stalled when clock gating is e
17777 #undef DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL
17778 #undef DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT
17779 #undef DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK
17780 #define DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL 0x00019FFE
17781 #define DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT 22
17782 #define DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK 0x00C00000U
17787 #undef DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL
17788 #undef DDR_PHY_DX8SL0OSC_LBMODE_SHIFT
17789 #undef DDR_PHY_DX8SL0OSC_LBMODE_MASK
17790 #define DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL 0x00019FFE
17791 #define DDR_PHY_DX8SL0OSC_LBMODE_SHIFT 21
17792 #define DDR_PHY_DX8SL0OSC_LBMODE_MASK 0x00200000U
17795 * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
17797 #undef DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL
17798 #undef DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT
17799 #undef DDR_PHY_DX8SL0OSC_LBGSDQS_MASK
17800 #define DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL 0x00019FFE
17801 #define DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT 20
17802 #define DDR_PHY_DX8SL0OSC_LBGSDQS_MASK 0x00100000U
17805 * Loopback DQS Gating
17807 #undef DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL
17808 #undef DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT
17809 #undef DDR_PHY_DX8SL0OSC_LBGDQS_MASK
17810 #define DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL 0x00019FFE
17811 #define DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT 18
17812 #define DDR_PHY_DX8SL0OSC_LBGDQS_MASK 0x000C0000U
17815 * Loopback DQS Shift
17817 #undef DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL
17818 #undef DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT
17819 #undef DDR_PHY_DX8SL0OSC_LBDQSS_MASK
17820 #define DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL 0x00019FFE
17821 #define DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT 17
17822 #define DDR_PHY_DX8SL0OSC_LBDQSS_MASK 0x00020000U
17825 * PHY High-Speed Reset
17827 #undef DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL
17828 #undef DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT
17829 #undef DDR_PHY_DX8SL0OSC_PHYHRST_MASK
17830 #define DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL 0x00019FFE
17831 #define DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT 16
17832 #define DDR_PHY_DX8SL0OSC_PHYHRST_MASK 0x00010000U
17837 #undef DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL
17838 #undef DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT
17839 #undef DDR_PHY_DX8SL0OSC_PHYFRST_MASK
17840 #define DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL 0x00019FFE
17841 #define DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT 15
17842 #define DDR_PHY_DX8SL0OSC_PHYFRST_MASK 0x00008000U
17845 * Delay Line Test Start
17847 #undef DDR_PHY_DX8SL0OSC_DLTST_DEFVAL
17848 #undef DDR_PHY_DX8SL0OSC_DLTST_SHIFT
17849 #undef DDR_PHY_DX8SL0OSC_DLTST_MASK
17850 #define DDR_PHY_DX8SL0OSC_DLTST_DEFVAL 0x00019FFE
17851 #define DDR_PHY_DX8SL0OSC_DLTST_SHIFT 14
17852 #define DDR_PHY_DX8SL0OSC_DLTST_MASK 0x00004000U
17855 * Delay Line Test Mode
17857 #undef DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL
17858 #undef DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT
17859 #undef DDR_PHY_DX8SL0OSC_DLTMODE_MASK
17860 #define DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL 0x00019FFE
17861 #define DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT 13
17862 #define DDR_PHY_DX8SL0OSC_DLTMODE_MASK 0x00002000U
17865 * Reserved. Caution, do not write to this register field.
17867 #undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL
17868 #undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT
17869 #undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK
17870 #define DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL 0x00019FFE
17871 #define DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT 11
17872 #define DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK 0x00001800U
17875 * Oscillator Mode Write-Data Delay Line Select
17877 #undef DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL
17878 #undef DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT
17879 #undef DDR_PHY_DX8SL0OSC_OSCWDDL_MASK
17880 #define DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL 0x00019FFE
17881 #define DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT 9
17882 #define DDR_PHY_DX8SL0OSC_OSCWDDL_MASK 0x00000600U
17885 * Reserved. Caution, do not write to this register field.
17887 #undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL
17888 #undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT
17889 #undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK
17890 #define DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL 0x00019FFE
17891 #define DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT 7
17892 #define DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK 0x00000180U
17895 * Oscillator Mode Write-Leveling Delay Line Select
17897 #undef DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL
17898 #undef DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT
17899 #undef DDR_PHY_DX8SL0OSC_OSCWDL_MASK
17900 #define DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL 0x00019FFE
17901 #define DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT 5
17902 #define DDR_PHY_DX8SL0OSC_OSCWDL_MASK 0x00000060U
17905 * Oscillator Mode Division
17907 #undef DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL
17908 #undef DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT
17909 #undef DDR_PHY_DX8SL0OSC_OSCDIV_MASK
17910 #define DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL 0x00019FFE
17911 #define DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT 1
17912 #define DDR_PHY_DX8SL0OSC_OSCDIV_MASK 0x0000001EU
17915 * Oscillator Enable
17917 #undef DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL
17918 #undef DDR_PHY_DX8SL0OSC_OSCEN_SHIFT
17919 #undef DDR_PHY_DX8SL0OSC_OSCEN_MASK
17920 #define DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL 0x00019FFE
17921 #define DDR_PHY_DX8SL0OSC_OSCEN_SHIFT 0
17922 #define DDR_PHY_DX8SL0OSC_OSCEN_MASK 0x00000001U
17927 #undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_DEFVAL
17928 #undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT
17929 #undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK
17930 #define DDR_PHY_DX8SL0PLLCR0_PLLBYP_DEFVAL 0x001C0000
17931 #define DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT 31
17932 #define DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK 0x80000000U
17937 #undef DDR_PHY_DX8SL0PLLCR0_PLLRST_DEFVAL
17938 #undef DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT
17939 #undef DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK
17940 #define DDR_PHY_DX8SL0PLLCR0_PLLRST_DEFVAL 0x001C0000
17941 #define DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT 30
17942 #define DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK 0x40000000U
17947 #undef DDR_PHY_DX8SL0PLLCR0_PLLPD_DEFVAL
17948 #undef DDR_PHY_DX8SL0PLLCR0_PLLPD_SHIFT
17949 #undef DDR_PHY_DX8SL0PLLCR0_PLLPD_MASK
17950 #define DDR_PHY_DX8SL0PLLCR0_PLLPD_DEFVAL 0x001C0000
17951 #define DDR_PHY_DX8SL0PLLCR0_PLLPD_SHIFT 29
17952 #define DDR_PHY_DX8SL0PLLCR0_PLLPD_MASK 0x20000000U
17955 * Reference Stop Mode
17957 #undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_DEFVAL
17958 #undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_SHIFT
17959 #undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_MASK
17960 #define DDR_PHY_DX8SL0PLLCR0_RSTOPM_DEFVAL 0x001C0000
17961 #define DDR_PHY_DX8SL0PLLCR0_RSTOPM_SHIFT 28
17962 #define DDR_PHY_DX8SL0PLLCR0_RSTOPM_MASK 0x10000000U
17965 * PLL Frequency Select
17967 #undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_DEFVAL
17968 #undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_SHIFT
17969 #undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_MASK
17970 #define DDR_PHY_DX8SL0PLLCR0_FRQSEL_DEFVAL 0x001C0000
17971 #define DDR_PHY_DX8SL0PLLCR0_FRQSEL_SHIFT 24
17972 #define DDR_PHY_DX8SL0PLLCR0_FRQSEL_MASK 0x0F000000U
17977 #undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_DEFVAL
17978 #undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_SHIFT
17979 #undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_MASK
17980 #define DDR_PHY_DX8SL0PLLCR0_RLOCKM_DEFVAL 0x001C0000
17981 #define DDR_PHY_DX8SL0PLLCR0_RLOCKM_SHIFT 23
17982 #define DDR_PHY_DX8SL0PLLCR0_RLOCKM_MASK 0x00800000U
17985 * Charge Pump Proportional Current Control
17987 #undef DDR_PHY_DX8SL0PLLCR0_CPPC_DEFVAL
17988 #undef DDR_PHY_DX8SL0PLLCR0_CPPC_SHIFT
17989 #undef DDR_PHY_DX8SL0PLLCR0_CPPC_MASK
17990 #define DDR_PHY_DX8SL0PLLCR0_CPPC_DEFVAL 0x001C0000
17991 #define DDR_PHY_DX8SL0PLLCR0_CPPC_SHIFT 17
17992 #define DDR_PHY_DX8SL0PLLCR0_CPPC_MASK 0x007E0000U
17995 * Charge Pump Integrating Current Control
17997 #undef DDR_PHY_DX8SL0PLLCR0_CPIC_DEFVAL
17998 #undef DDR_PHY_DX8SL0PLLCR0_CPIC_SHIFT
17999 #undef DDR_PHY_DX8SL0PLLCR0_CPIC_MASK
18000 #define DDR_PHY_DX8SL0PLLCR0_CPIC_DEFVAL 0x001C0000
18001 #define DDR_PHY_DX8SL0PLLCR0_CPIC_SHIFT 13
18002 #define DDR_PHY_DX8SL0PLLCR0_CPIC_MASK 0x0001E000U
18007 #undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_DEFVAL
18008 #undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_SHIFT
18009 #undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_MASK
18010 #define DDR_PHY_DX8SL0PLLCR0_GSHIFT_DEFVAL 0x001C0000
18011 #define DDR_PHY_DX8SL0PLLCR0_GSHIFT_SHIFT 12
18012 #define DDR_PHY_DX8SL0PLLCR0_GSHIFT_MASK 0x00001000U
18015 * Reserved. Return zeroes on reads.
18017 #undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_DEFVAL
18018 #undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT
18019 #undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_MASK
18020 #define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000
18021 #define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT 9
18022 #define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_MASK 0x00000E00U
18025 * Analog Test Enable (ATOEN)
18027 #undef DDR_PHY_DX8SL0PLLCR0_ATOEN_DEFVAL
18028 #undef DDR_PHY_DX8SL0PLLCR0_ATOEN_SHIFT
18029 #undef DDR_PHY_DX8SL0PLLCR0_ATOEN_MASK
18030 #define DDR_PHY_DX8SL0PLLCR0_ATOEN_DEFVAL 0x001C0000
18031 #define DDR_PHY_DX8SL0PLLCR0_ATOEN_SHIFT 8
18032 #define DDR_PHY_DX8SL0PLLCR0_ATOEN_MASK 0x00000100U
18035 * Analog Test Control
18037 #undef DDR_PHY_DX8SL0PLLCR0_ATC_DEFVAL
18038 #undef DDR_PHY_DX8SL0PLLCR0_ATC_SHIFT
18039 #undef DDR_PHY_DX8SL0PLLCR0_ATC_MASK
18040 #define DDR_PHY_DX8SL0PLLCR0_ATC_DEFVAL 0x001C0000
18041 #define DDR_PHY_DX8SL0PLLCR0_ATC_SHIFT 4
18042 #define DDR_PHY_DX8SL0PLLCR0_ATC_MASK 0x000000F0U
18045 * Digital Test Control
18047 #undef DDR_PHY_DX8SL0PLLCR0_DTC_DEFVAL
18048 #undef DDR_PHY_DX8SL0PLLCR0_DTC_SHIFT
18049 #undef DDR_PHY_DX8SL0PLLCR0_DTC_MASK
18050 #define DDR_PHY_DX8SL0PLLCR0_DTC_DEFVAL 0x001C0000
18051 #define DDR_PHY_DX8SL0PLLCR0_DTC_SHIFT 0
18052 #define DDR_PHY_DX8SL0PLLCR0_DTC_MASK 0x0000000FU
18055 * Reserved. Return zeroes on reads.
18057 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL
18058 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT
18059 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK
18060 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL 0x01264000
18061 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT 25
18062 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK 0xFE000000U
18065 * Read Path Rise-to-Rise Mode
18067 #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL
18068 #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT
18069 #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK
18070 #define DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL 0x01264000
18071 #define DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT 24
18072 #define DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK 0x01000000U
18075 * Reserved. Return zeroes on reads.
18077 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL
18078 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT
18079 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK
18080 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL 0x01264000
18081 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT 22
18082 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK 0x00C00000U
18085 * Write Path Rise-to-Rise Mode
18087 #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL
18088 #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT
18089 #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK
18090 #define DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL 0x01264000
18091 #define DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT 21
18092 #define DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK 0x00200000U
18095 * DQS Gate Extension
18097 #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL
18098 #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT
18099 #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK
18100 #define DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL 0x01264000
18101 #define DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT 19
18102 #define DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK 0x00180000U
18105 * Low Power PLL Power Down
18107 #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL
18108 #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT
18109 #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK
18110 #define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL 0x01264000
18111 #define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT 18
18112 #define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK 0x00040000U
18115 * Low Power I/O Power Down
18117 #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL
18118 #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT
18119 #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK
18120 #define DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL 0x01264000
18121 #define DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT 17
18122 #define DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK 0x00020000U
18125 * Reserved. Return zeroes on reads.
18127 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL
18128 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT
18129 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK
18130 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL 0x01264000
18131 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT 15
18132 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK 0x00018000U
18135 * QS Counter Enable
18137 #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL
18138 #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT
18139 #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK
18140 #define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL 0x01264000
18141 #define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT 14
18142 #define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK 0x00004000U
18145 * Unused DQ I/O Mode
18147 #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL
18148 #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT
18149 #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK
18150 #define DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL 0x01264000
18151 #define DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT 13
18152 #define DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK 0x00002000U
18155 * Reserved. Return zeroes on reads.
18157 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL
18158 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT
18159 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK
18160 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL 0x01264000
18161 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT 10
18162 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK 0x00001C00U
18167 #undef DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL
18168 #undef DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT
18169 #undef DDR_PHY_DX8SL0DQSCTL_DXSR_MASK
18170 #define DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL 0x01264000
18171 #define DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT 8
18172 #define DDR_PHY_DX8SL0DQSCTL_DXSR_MASK 0x00000300U
18177 #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL
18178 #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT
18179 #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK
18180 #define DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL 0x01264000
18181 #define DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT 4
18182 #define DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK 0x000000F0U
18187 #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL
18188 #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT
18189 #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK
18190 #define DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL 0x01264000
18191 #define DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT 0
18192 #define DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK 0x0000000FU
18195 * Reserved. Return zeroes on reads.
18197 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL
18198 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT
18199 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK
18200 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL 0x00141800
18201 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT 24
18202 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK 0xFF000000U
18205 * Configurable Read Data Enable
18207 #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL
18208 #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT
18209 #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK
18210 #define DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL 0x00141800
18211 #define DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT 23
18212 #define DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK 0x00800000U
18215 * OX Extension during Post-amble
18217 #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL
18218 #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT
18219 #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK
18220 #define DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL 0x00141800
18221 #define DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT 20
18222 #define DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK 0x00700000U
18225 * OE Extension during Pre-amble
18227 #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL
18228 #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT
18229 #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK
18230 #define DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL 0x00141800
18231 #define DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT 18
18232 #define DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK 0x000C0000U
18235 * Reserved. Return zeroes on reads.
18237 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL
18238 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT
18239 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK
18240 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL 0x00141800
18241 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT 17
18242 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK 0x00020000U
18245 * I/O Assisted Gate Select
18247 #undef DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL
18248 #undef DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT
18249 #undef DDR_PHY_DX8SL0DXCTL2_IOAG_MASK
18250 #define DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL 0x00141800
18251 #define DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT 16
18252 #define DDR_PHY_DX8SL0DXCTL2_IOAG_MASK 0x00010000U
18255 * I/O Loopback Select
18257 #undef DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL
18258 #undef DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT
18259 #undef DDR_PHY_DX8SL0DXCTL2_IOLB_MASK
18260 #define DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL 0x00141800
18261 #define DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT 15
18262 #define DDR_PHY_DX8SL0DXCTL2_IOLB_MASK 0x00008000U
18265 * Reserved. Return zeroes on reads.
18267 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL
18268 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT
18269 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK
18270 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL 0x00141800
18271 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT 13
18272 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK 0x00006000U
18275 * Low Power Wakeup Threshold
18277 #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL
18278 #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT
18279 #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK
18280 #define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800
18281 #define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT 9
18282 #define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U
18285 * Read Data Bus Inversion Enable
18287 #undef DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL
18288 #undef DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT
18289 #undef DDR_PHY_DX8SL0DXCTL2_RDBI_MASK
18290 #define DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL 0x00141800
18291 #define DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT 8
18292 #define DDR_PHY_DX8SL0DXCTL2_RDBI_MASK 0x00000100U
18295 * Write Data Bus Inversion Enable
18297 #undef DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL
18298 #undef DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT
18299 #undef DDR_PHY_DX8SL0DXCTL2_WDBI_MASK
18300 #define DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL 0x00141800
18301 #define DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT 7
18302 #define DDR_PHY_DX8SL0DXCTL2_WDBI_MASK 0x00000080U
18305 * PUB Read FIFO Bypass
18307 #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL
18308 #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT
18309 #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK
18310 #define DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL 0x00141800
18311 #define DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT 6
18312 #define DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK 0x00000040U
18315 * DATX8 Receive FIFO Read Mode
18317 #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL
18318 #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT
18319 #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK
18320 #define DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL 0x00141800
18321 #define DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT 4
18322 #define DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK 0x00000030U
18325 * Disables the Read FIFO Reset
18327 #undef DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL
18328 #undef DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT
18329 #undef DDR_PHY_DX8SL0DXCTL2_DISRST_MASK
18330 #define DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL 0x00141800
18331 #define DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT 3
18332 #define DDR_PHY_DX8SL0DXCTL2_DISRST_MASK 0x00000008U
18335 * Read DQS Gate I/O Loopback
18337 #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL
18338 #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT
18339 #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK
18340 #define DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL 0x00141800
18341 #define DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT 1
18342 #define DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK 0x00000006U
18345 * Reserved. Return zeroes on reads.
18347 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL
18348 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT
18349 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK
18350 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL 0x00141800
18351 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT 0
18352 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK 0x00000001U
18355 * Reserved. Return zeroes on reads.
18357 #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL
18358 #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT
18359 #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK
18360 #define DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL 0x00000000
18361 #define DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT 31
18362 #define DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK 0x80000000U
18365 * PVREF_DAC REFSEL range select
18367 #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL
18368 #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT
18369 #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK
18370 #define DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL 0x00000000
18371 #define DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT 28
18372 #define DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK 0x70000000U
18375 * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
18377 #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL
18378 #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT
18379 #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK
18380 #define DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL 0x00000000
18381 #define DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT 25
18382 #define DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK 0x0E000000U
18387 #undef DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL
18388 #undef DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT
18389 #undef DDR_PHY_DX8SL0IOCR_DXIOM_MASK
18390 #define DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL 0x00000000
18391 #define DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT 22
18392 #define DDR_PHY_DX8SL0IOCR_DXIOM_MASK 0x01C00000U
18395 * DX IO Transmitter Mode
18397 #undef DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL
18398 #undef DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT
18399 #undef DDR_PHY_DX8SL0IOCR_DXTXM_MASK
18400 #define DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL 0x00000000
18401 #define DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT 11
18402 #define DDR_PHY_DX8SL0IOCR_DXTXM_MASK 0x003FF800U
18405 * DX IO Receiver Mode
18407 #undef DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL
18408 #undef DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT
18409 #undef DDR_PHY_DX8SL0IOCR_DXRXM_MASK
18410 #define DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL 0x00000000
18411 #define DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT 0
18412 #define DDR_PHY_DX8SL0IOCR_DXRXM_MASK 0x000007FFU
18415 * Reserved. Return zeroes on reads.
18417 #undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL
18418 #undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT
18419 #undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK
18420 #define DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL 0x00019FFE
18421 #define DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT 30
18422 #define DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK 0xC0000000U
18425 * Enable Clock Gating for DX ddr_clk
18427 #undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL
18428 #undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT
18429 #undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK
18430 #define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL 0x00019FFE
18431 #define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT 28
18432 #define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK 0x30000000U
18435 * Enable Clock Gating for DX ctl_rd_clk
18437 #undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL
18438 #undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT
18439 #undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK
18440 #define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE
18441 #define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT 26
18442 #define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK 0x0C000000U
18445 * Enable Clock Gating for DX ctl_clk
18447 #undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL
18448 #undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT
18449 #undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK
18450 #define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE
18451 #define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT 24
18452 #define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK 0x03000000U
18455 * Selects the level to which clocks will be stalled when clock gating is e
18458 #undef DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL
18459 #undef DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT
18460 #undef DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK
18461 #define DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL 0x00019FFE
18462 #define DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT 22
18463 #define DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK 0x00C00000U
18468 #undef DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL
18469 #undef DDR_PHY_DX8SL1OSC_LBMODE_SHIFT
18470 #undef DDR_PHY_DX8SL1OSC_LBMODE_MASK
18471 #define DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL 0x00019FFE
18472 #define DDR_PHY_DX8SL1OSC_LBMODE_SHIFT 21
18473 #define DDR_PHY_DX8SL1OSC_LBMODE_MASK 0x00200000U
18476 * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
18478 #undef DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL
18479 #undef DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT
18480 #undef DDR_PHY_DX8SL1OSC_LBGSDQS_MASK
18481 #define DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL 0x00019FFE
18482 #define DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT 20
18483 #define DDR_PHY_DX8SL1OSC_LBGSDQS_MASK 0x00100000U
18486 * Loopback DQS Gating
18488 #undef DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL
18489 #undef DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT
18490 #undef DDR_PHY_DX8SL1OSC_LBGDQS_MASK
18491 #define DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL 0x00019FFE
18492 #define DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT 18
18493 #define DDR_PHY_DX8SL1OSC_LBGDQS_MASK 0x000C0000U
18496 * Loopback DQS Shift
18498 #undef DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL
18499 #undef DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT
18500 #undef DDR_PHY_DX8SL1OSC_LBDQSS_MASK
18501 #define DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL 0x00019FFE
18502 #define DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT 17
18503 #define DDR_PHY_DX8SL1OSC_LBDQSS_MASK 0x00020000U
18506 * PHY High-Speed Reset
18508 #undef DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL
18509 #undef DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT
18510 #undef DDR_PHY_DX8SL1OSC_PHYHRST_MASK
18511 #define DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL 0x00019FFE
18512 #define DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT 16
18513 #define DDR_PHY_DX8SL1OSC_PHYHRST_MASK 0x00010000U
18518 #undef DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL
18519 #undef DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT
18520 #undef DDR_PHY_DX8SL1OSC_PHYFRST_MASK
18521 #define DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL 0x00019FFE
18522 #define DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT 15
18523 #define DDR_PHY_DX8SL1OSC_PHYFRST_MASK 0x00008000U
18526 * Delay Line Test Start
18528 #undef DDR_PHY_DX8SL1OSC_DLTST_DEFVAL
18529 #undef DDR_PHY_DX8SL1OSC_DLTST_SHIFT
18530 #undef DDR_PHY_DX8SL1OSC_DLTST_MASK
18531 #define DDR_PHY_DX8SL1OSC_DLTST_DEFVAL 0x00019FFE
18532 #define DDR_PHY_DX8SL1OSC_DLTST_SHIFT 14
18533 #define DDR_PHY_DX8SL1OSC_DLTST_MASK 0x00004000U
18536 * Delay Line Test Mode
18538 #undef DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL
18539 #undef DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT
18540 #undef DDR_PHY_DX8SL1OSC_DLTMODE_MASK
18541 #define DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL 0x00019FFE
18542 #define DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT 13
18543 #define DDR_PHY_DX8SL1OSC_DLTMODE_MASK 0x00002000U
18546 * Reserved. Caution, do not write to this register field.
18548 #undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL
18549 #undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT
18550 #undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK
18551 #define DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL 0x00019FFE
18552 #define DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT 11
18553 #define DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK 0x00001800U
18556 * Oscillator Mode Write-Data Delay Line Select
18558 #undef DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL
18559 #undef DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT
18560 #undef DDR_PHY_DX8SL1OSC_OSCWDDL_MASK
18561 #define DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL 0x00019FFE
18562 #define DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT 9
18563 #define DDR_PHY_DX8SL1OSC_OSCWDDL_MASK 0x00000600U
18566 * Reserved. Caution, do not write to this register field.
18568 #undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL
18569 #undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT
18570 #undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK
18571 #define DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL 0x00019FFE
18572 #define DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT 7
18573 #define DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK 0x00000180U
18576 * Oscillator Mode Write-Leveling Delay Line Select
18578 #undef DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL
18579 #undef DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT
18580 #undef DDR_PHY_DX8SL1OSC_OSCWDL_MASK
18581 #define DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL 0x00019FFE
18582 #define DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT 5
18583 #define DDR_PHY_DX8SL1OSC_OSCWDL_MASK 0x00000060U
18586 * Oscillator Mode Division
18588 #undef DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL
18589 #undef DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT
18590 #undef DDR_PHY_DX8SL1OSC_OSCDIV_MASK
18591 #define DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL 0x00019FFE
18592 #define DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT 1
18593 #define DDR_PHY_DX8SL1OSC_OSCDIV_MASK 0x0000001EU
18596 * Oscillator Enable
18598 #undef DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL
18599 #undef DDR_PHY_DX8SL1OSC_OSCEN_SHIFT
18600 #undef DDR_PHY_DX8SL1OSC_OSCEN_MASK
18601 #define DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL 0x00019FFE
18602 #define DDR_PHY_DX8SL1OSC_OSCEN_SHIFT 0
18603 #define DDR_PHY_DX8SL1OSC_OSCEN_MASK 0x00000001U
18608 #undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_DEFVAL
18609 #undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_SHIFT
18610 #undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_MASK
18611 #define DDR_PHY_DX8SL1PLLCR0_PLLBYP_DEFVAL 0x001C0000
18612 #define DDR_PHY_DX8SL1PLLCR0_PLLBYP_SHIFT 31
18613 #define DDR_PHY_DX8SL1PLLCR0_PLLBYP_MASK 0x80000000U
18618 #undef DDR_PHY_DX8SL1PLLCR0_PLLRST_DEFVAL
18619 #undef DDR_PHY_DX8SL1PLLCR0_PLLRST_SHIFT
18620 #undef DDR_PHY_DX8SL1PLLCR0_PLLRST_MASK
18621 #define DDR_PHY_DX8SL1PLLCR0_PLLRST_DEFVAL 0x001C0000
18622 #define DDR_PHY_DX8SL1PLLCR0_PLLRST_SHIFT 30
18623 #define DDR_PHY_DX8SL1PLLCR0_PLLRST_MASK 0x40000000U
18628 #undef DDR_PHY_DX8SL1PLLCR0_PLLPD_DEFVAL
18629 #undef DDR_PHY_DX8SL1PLLCR0_PLLPD_SHIFT
18630 #undef DDR_PHY_DX8SL1PLLCR0_PLLPD_MASK
18631 #define DDR_PHY_DX8SL1PLLCR0_PLLPD_DEFVAL 0x001C0000
18632 #define DDR_PHY_DX8SL1PLLCR0_PLLPD_SHIFT 29
18633 #define DDR_PHY_DX8SL1PLLCR0_PLLPD_MASK 0x20000000U
18636 * Reference Stop Mode
18638 #undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_DEFVAL
18639 #undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_SHIFT
18640 #undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_MASK
18641 #define DDR_PHY_DX8SL1PLLCR0_RSTOPM_DEFVAL 0x001C0000
18642 #define DDR_PHY_DX8SL1PLLCR0_RSTOPM_SHIFT 28
18643 #define DDR_PHY_DX8SL1PLLCR0_RSTOPM_MASK 0x10000000U
18646 * PLL Frequency Select
18648 #undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_DEFVAL
18649 #undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_SHIFT
18650 #undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_MASK
18651 #define DDR_PHY_DX8SL1PLLCR0_FRQSEL_DEFVAL 0x001C0000
18652 #define DDR_PHY_DX8SL1PLLCR0_FRQSEL_SHIFT 24
18653 #define DDR_PHY_DX8SL1PLLCR0_FRQSEL_MASK 0x0F000000U
18658 #undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_DEFVAL
18659 #undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_SHIFT
18660 #undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_MASK
18661 #define DDR_PHY_DX8SL1PLLCR0_RLOCKM_DEFVAL 0x001C0000
18662 #define DDR_PHY_DX8SL1PLLCR0_RLOCKM_SHIFT 23
18663 #define DDR_PHY_DX8SL1PLLCR0_RLOCKM_MASK 0x00800000U
18666 * Charge Pump Proportional Current Control
18668 #undef DDR_PHY_DX8SL1PLLCR0_CPPC_DEFVAL
18669 #undef DDR_PHY_DX8SL1PLLCR0_CPPC_SHIFT
18670 #undef DDR_PHY_DX8SL1PLLCR0_CPPC_MASK
18671 #define DDR_PHY_DX8SL1PLLCR0_CPPC_DEFVAL 0x001C0000
18672 #define DDR_PHY_DX8SL1PLLCR0_CPPC_SHIFT 17
18673 #define DDR_PHY_DX8SL1PLLCR0_CPPC_MASK 0x007E0000U
18676 * Charge Pump Integrating Current Control
18678 #undef DDR_PHY_DX8SL1PLLCR0_CPIC_DEFVAL
18679 #undef DDR_PHY_DX8SL1PLLCR0_CPIC_SHIFT
18680 #undef DDR_PHY_DX8SL1PLLCR0_CPIC_MASK
18681 #define DDR_PHY_DX8SL1PLLCR0_CPIC_DEFVAL 0x001C0000
18682 #define DDR_PHY_DX8SL1PLLCR0_CPIC_SHIFT 13
18683 #define DDR_PHY_DX8SL1PLLCR0_CPIC_MASK 0x0001E000U
18688 #undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_DEFVAL
18689 #undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_SHIFT
18690 #undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_MASK
18691 #define DDR_PHY_DX8SL1PLLCR0_GSHIFT_DEFVAL 0x001C0000
18692 #define DDR_PHY_DX8SL1PLLCR0_GSHIFT_SHIFT 12
18693 #define DDR_PHY_DX8SL1PLLCR0_GSHIFT_MASK 0x00001000U
18696 * Reserved. Return zeroes on reads.
18698 #undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_DEFVAL
18699 #undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT
18700 #undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_MASK
18701 #define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000
18702 #define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT 9
18703 #define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_MASK 0x00000E00U
18706 * Analog Test Enable (ATOEN)
18708 #undef DDR_PHY_DX8SL1PLLCR0_ATOEN_DEFVAL
18709 #undef DDR_PHY_DX8SL1PLLCR0_ATOEN_SHIFT
18710 #undef DDR_PHY_DX8SL1PLLCR0_ATOEN_MASK
18711 #define DDR_PHY_DX8SL1PLLCR0_ATOEN_DEFVAL 0x001C0000
18712 #define DDR_PHY_DX8SL1PLLCR0_ATOEN_SHIFT 8
18713 #define DDR_PHY_DX8SL1PLLCR0_ATOEN_MASK 0x00000100U
18716 * Analog Test Control
18718 #undef DDR_PHY_DX8SL1PLLCR0_ATC_DEFVAL
18719 #undef DDR_PHY_DX8SL1PLLCR0_ATC_SHIFT
18720 #undef DDR_PHY_DX8SL1PLLCR0_ATC_MASK
18721 #define DDR_PHY_DX8SL1PLLCR0_ATC_DEFVAL 0x001C0000
18722 #define DDR_PHY_DX8SL1PLLCR0_ATC_SHIFT 4
18723 #define DDR_PHY_DX8SL1PLLCR0_ATC_MASK 0x000000F0U
18726 * Digital Test Control
18728 #undef DDR_PHY_DX8SL1PLLCR0_DTC_DEFVAL
18729 #undef DDR_PHY_DX8SL1PLLCR0_DTC_SHIFT
18730 #undef DDR_PHY_DX8SL1PLLCR0_DTC_MASK
18731 #define DDR_PHY_DX8SL1PLLCR0_DTC_DEFVAL 0x001C0000
18732 #define DDR_PHY_DX8SL1PLLCR0_DTC_SHIFT 0
18733 #define DDR_PHY_DX8SL1PLLCR0_DTC_MASK 0x0000000FU
18736 * Reserved. Return zeroes on reads.
18738 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL
18739 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT
18740 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK
18741 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL 0x01264000
18742 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT 25
18743 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK 0xFE000000U
18746 * Read Path Rise-to-Rise Mode
18748 #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL
18749 #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT
18750 #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK
18751 #define DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL 0x01264000
18752 #define DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT 24
18753 #define DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK 0x01000000U
18756 * Reserved. Return zeroes on reads.
18758 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL
18759 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT
18760 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK
18761 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL 0x01264000
18762 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT 22
18763 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK 0x00C00000U
18766 * Write Path Rise-to-Rise Mode
18768 #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL
18769 #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT
18770 #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK
18771 #define DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL 0x01264000
18772 #define DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT 21
18773 #define DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK 0x00200000U
18776 * DQS Gate Extension
18778 #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL
18779 #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT
18780 #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK
18781 #define DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL 0x01264000
18782 #define DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT 19
18783 #define DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK 0x00180000U
18786 * Low Power PLL Power Down
18788 #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL
18789 #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT
18790 #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK
18791 #define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL 0x01264000
18792 #define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT 18
18793 #define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK 0x00040000U
18796 * Low Power I/O Power Down
18798 #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL
18799 #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT
18800 #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK
18801 #define DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL 0x01264000
18802 #define DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT 17
18803 #define DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK 0x00020000U
18806 * Reserved. Return zeroes on reads.
18808 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL
18809 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT
18810 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK
18811 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL 0x01264000
18812 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT 15
18813 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK 0x00018000U
18816 * QS Counter Enable
18818 #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL
18819 #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT
18820 #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK
18821 #define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL 0x01264000
18822 #define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT 14
18823 #define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK 0x00004000U
18826 * Unused DQ I/O Mode
18828 #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL
18829 #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT
18830 #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK
18831 #define DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL 0x01264000
18832 #define DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT 13
18833 #define DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK 0x00002000U
18836 * Reserved. Return zeroes on reads.
18838 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL
18839 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT
18840 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK
18841 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL 0x01264000
18842 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT 10
18843 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK 0x00001C00U
18848 #undef DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL
18849 #undef DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT
18850 #undef DDR_PHY_DX8SL1DQSCTL_DXSR_MASK
18851 #define DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL 0x01264000
18852 #define DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT 8
18853 #define DDR_PHY_DX8SL1DQSCTL_DXSR_MASK 0x00000300U
18858 #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL
18859 #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT
18860 #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK
18861 #define DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL 0x01264000
18862 #define DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT 4
18863 #define DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK 0x000000F0U
18868 #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL
18869 #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT
18870 #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK
18871 #define DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL 0x01264000
18872 #define DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT 0
18873 #define DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK 0x0000000FU
18876 * Reserved. Return zeroes on reads.
18878 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL
18879 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT
18880 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK
18881 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL 0x00141800
18882 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT 24
18883 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK 0xFF000000U
18886 * Configurable Read Data Enable
18888 #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL
18889 #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT
18890 #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK
18891 #define DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL 0x00141800
18892 #define DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT 23
18893 #define DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK 0x00800000U
18896 * OX Extension during Post-amble
18898 #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL
18899 #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT
18900 #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK
18901 #define DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL 0x00141800
18902 #define DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT 20
18903 #define DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK 0x00700000U
18906 * OE Extension during Pre-amble
18908 #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL
18909 #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT
18910 #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK
18911 #define DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL 0x00141800
18912 #define DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT 18
18913 #define DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK 0x000C0000U
18916 * Reserved. Return zeroes on reads.
18918 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL
18919 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT
18920 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK
18921 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL 0x00141800
18922 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT 17
18923 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK 0x00020000U
18926 * I/O Assisted Gate Select
18928 #undef DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL
18929 #undef DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT
18930 #undef DDR_PHY_DX8SL1DXCTL2_IOAG_MASK
18931 #define DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL 0x00141800
18932 #define DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT 16
18933 #define DDR_PHY_DX8SL1DXCTL2_IOAG_MASK 0x00010000U
18936 * I/O Loopback Select
18938 #undef DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL
18939 #undef DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT
18940 #undef DDR_PHY_DX8SL1DXCTL2_IOLB_MASK
18941 #define DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL 0x00141800
18942 #define DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT 15
18943 #define DDR_PHY_DX8SL1DXCTL2_IOLB_MASK 0x00008000U
18946 * Reserved. Return zeroes on reads.
18948 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL
18949 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT
18950 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK
18951 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL 0x00141800
18952 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT 13
18953 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK 0x00006000U
18956 * Low Power Wakeup Threshold
18958 #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL
18959 #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT
18960 #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK
18961 #define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800
18962 #define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT 9
18963 #define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U
18966 * Read Data Bus Inversion Enable
18968 #undef DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL
18969 #undef DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT
18970 #undef DDR_PHY_DX8SL1DXCTL2_RDBI_MASK
18971 #define DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL 0x00141800
18972 #define DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT 8
18973 #define DDR_PHY_DX8SL1DXCTL2_RDBI_MASK 0x00000100U
18976 * Write Data Bus Inversion Enable
18978 #undef DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL
18979 #undef DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT
18980 #undef DDR_PHY_DX8SL1DXCTL2_WDBI_MASK
18981 #define DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL 0x00141800
18982 #define DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT 7
18983 #define DDR_PHY_DX8SL1DXCTL2_WDBI_MASK 0x00000080U
18986 * PUB Read FIFO Bypass
18988 #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL
18989 #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT
18990 #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK
18991 #define DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL 0x00141800
18992 #define DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT 6
18993 #define DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK 0x00000040U
18996 * DATX8 Receive FIFO Read Mode
18998 #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL
18999 #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT
19000 #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK
19001 #define DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL 0x00141800
19002 #define DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT 4
19003 #define DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK 0x00000030U
19006 * Disables the Read FIFO Reset
19008 #undef DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL
19009 #undef DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT
19010 #undef DDR_PHY_DX8SL1DXCTL2_DISRST_MASK
19011 #define DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL 0x00141800
19012 #define DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT 3
19013 #define DDR_PHY_DX8SL1DXCTL2_DISRST_MASK 0x00000008U
19016 * Read DQS Gate I/O Loopback
19018 #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL
19019 #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT
19020 #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK
19021 #define DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL 0x00141800
19022 #define DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT 1
19023 #define DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK 0x00000006U
19026 * Reserved. Return zeroes on reads.
19028 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL
19029 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT
19030 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK
19031 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL 0x00141800
19032 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT 0
19033 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK 0x00000001U
19036 * Reserved. Return zeroes on reads.
19038 #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL
19039 #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT
19040 #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK
19041 #define DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL 0x00000000
19042 #define DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT 31
19043 #define DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK 0x80000000U
19046 * PVREF_DAC REFSEL range select
19048 #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL
19049 #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT
19050 #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK
19051 #define DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL 0x00000000
19052 #define DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT 28
19053 #define DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK 0x70000000U
19056 * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
19058 #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL
19059 #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT
19060 #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK
19061 #define DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL 0x00000000
19062 #define DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT 25
19063 #define DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK 0x0E000000U
19068 #undef DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL
19069 #undef DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT
19070 #undef DDR_PHY_DX8SL1IOCR_DXIOM_MASK
19071 #define DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL 0x00000000
19072 #define DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT 22
19073 #define DDR_PHY_DX8SL1IOCR_DXIOM_MASK 0x01C00000U
19076 * DX IO Transmitter Mode
19078 #undef DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL
19079 #undef DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT
19080 #undef DDR_PHY_DX8SL1IOCR_DXTXM_MASK
19081 #define DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL 0x00000000
19082 #define DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT 11
19083 #define DDR_PHY_DX8SL1IOCR_DXTXM_MASK 0x003FF800U
19086 * DX IO Receiver Mode
19088 #undef DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL
19089 #undef DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT
19090 #undef DDR_PHY_DX8SL1IOCR_DXRXM_MASK
19091 #define DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL 0x00000000
19092 #define DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT 0
19093 #define DDR_PHY_DX8SL1IOCR_DXRXM_MASK 0x000007FFU
19096 * Reserved. Return zeroes on reads.
19098 #undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL
19099 #undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT
19100 #undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK
19101 #define DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL 0x00019FFE
19102 #define DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT 30
19103 #define DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK 0xC0000000U
19106 * Enable Clock Gating for DX ddr_clk
19108 #undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL
19109 #undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT
19110 #undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK
19111 #define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL 0x00019FFE
19112 #define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT 28
19113 #define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK 0x30000000U
19116 * Enable Clock Gating for DX ctl_rd_clk
19118 #undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL
19119 #undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT
19120 #undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK
19121 #define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE
19122 #define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT 26
19123 #define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK 0x0C000000U
19126 * Enable Clock Gating for DX ctl_clk
19128 #undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL
19129 #undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT
19130 #undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK
19131 #define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE
19132 #define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT 24
19133 #define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK 0x03000000U
19136 * Selects the level to which clocks will be stalled when clock gating is e
19139 #undef DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL
19140 #undef DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT
19141 #undef DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK
19142 #define DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL 0x00019FFE
19143 #define DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT 22
19144 #define DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK 0x00C00000U
19149 #undef DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL
19150 #undef DDR_PHY_DX8SL2OSC_LBMODE_SHIFT
19151 #undef DDR_PHY_DX8SL2OSC_LBMODE_MASK
19152 #define DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL 0x00019FFE
19153 #define DDR_PHY_DX8SL2OSC_LBMODE_SHIFT 21
19154 #define DDR_PHY_DX8SL2OSC_LBMODE_MASK 0x00200000U
19157 * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
19159 #undef DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL
19160 #undef DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT
19161 #undef DDR_PHY_DX8SL2OSC_LBGSDQS_MASK
19162 #define DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL 0x00019FFE
19163 #define DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT 20
19164 #define DDR_PHY_DX8SL2OSC_LBGSDQS_MASK 0x00100000U
19167 * Loopback DQS Gating
19169 #undef DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL
19170 #undef DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT
19171 #undef DDR_PHY_DX8SL2OSC_LBGDQS_MASK
19172 #define DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL 0x00019FFE
19173 #define DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT 18
19174 #define DDR_PHY_DX8SL2OSC_LBGDQS_MASK 0x000C0000U
19177 * Loopback DQS Shift
19179 #undef DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL
19180 #undef DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT
19181 #undef DDR_PHY_DX8SL2OSC_LBDQSS_MASK
19182 #define DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL 0x00019FFE
19183 #define DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT 17
19184 #define DDR_PHY_DX8SL2OSC_LBDQSS_MASK 0x00020000U
19187 * PHY High-Speed Reset
19189 #undef DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL
19190 #undef DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT
19191 #undef DDR_PHY_DX8SL2OSC_PHYHRST_MASK
19192 #define DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL 0x00019FFE
19193 #define DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT 16
19194 #define DDR_PHY_DX8SL2OSC_PHYHRST_MASK 0x00010000U
19199 #undef DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL
19200 #undef DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT
19201 #undef DDR_PHY_DX8SL2OSC_PHYFRST_MASK
19202 #define DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL 0x00019FFE
19203 #define DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT 15
19204 #define DDR_PHY_DX8SL2OSC_PHYFRST_MASK 0x00008000U
19207 * Delay Line Test Start
19209 #undef DDR_PHY_DX8SL2OSC_DLTST_DEFVAL
19210 #undef DDR_PHY_DX8SL2OSC_DLTST_SHIFT
19211 #undef DDR_PHY_DX8SL2OSC_DLTST_MASK
19212 #define DDR_PHY_DX8SL2OSC_DLTST_DEFVAL 0x00019FFE
19213 #define DDR_PHY_DX8SL2OSC_DLTST_SHIFT 14
19214 #define DDR_PHY_DX8SL2OSC_DLTST_MASK 0x00004000U
19217 * Delay Line Test Mode
19219 #undef DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL
19220 #undef DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT
19221 #undef DDR_PHY_DX8SL2OSC_DLTMODE_MASK
19222 #define DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL 0x00019FFE
19223 #define DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT 13
19224 #define DDR_PHY_DX8SL2OSC_DLTMODE_MASK 0x00002000U
19227 * Reserved. Caution, do not write to this register field.
19229 #undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL
19230 #undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT
19231 #undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK
19232 #define DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL 0x00019FFE
19233 #define DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT 11
19234 #define DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK 0x00001800U
19237 * Oscillator Mode Write-Data Delay Line Select
19239 #undef DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL
19240 #undef DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT
19241 #undef DDR_PHY_DX8SL2OSC_OSCWDDL_MASK
19242 #define DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL 0x00019FFE
19243 #define DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT 9
19244 #define DDR_PHY_DX8SL2OSC_OSCWDDL_MASK 0x00000600U
19247 * Reserved. Caution, do not write to this register field.
19249 #undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL
19250 #undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT
19251 #undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK
19252 #define DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL 0x00019FFE
19253 #define DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT 7
19254 #define DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK 0x00000180U
19257 * Oscillator Mode Write-Leveling Delay Line Select
19259 #undef DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL
19260 #undef DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT
19261 #undef DDR_PHY_DX8SL2OSC_OSCWDL_MASK
19262 #define DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL 0x00019FFE
19263 #define DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT 5
19264 #define DDR_PHY_DX8SL2OSC_OSCWDL_MASK 0x00000060U
19267 * Oscillator Mode Division
19269 #undef DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL
19270 #undef DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT
19271 #undef DDR_PHY_DX8SL2OSC_OSCDIV_MASK
19272 #define DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL 0x00019FFE
19273 #define DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT 1
19274 #define DDR_PHY_DX8SL2OSC_OSCDIV_MASK 0x0000001EU
19277 * Oscillator Enable
19279 #undef DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL
19280 #undef DDR_PHY_DX8SL2OSC_OSCEN_SHIFT
19281 #undef DDR_PHY_DX8SL2OSC_OSCEN_MASK
19282 #define DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL 0x00019FFE
19283 #define DDR_PHY_DX8SL2OSC_OSCEN_SHIFT 0
19284 #define DDR_PHY_DX8SL2OSC_OSCEN_MASK 0x00000001U
19289 #undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_DEFVAL
19290 #undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_SHIFT
19291 #undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_MASK
19292 #define DDR_PHY_DX8SL2PLLCR0_PLLBYP_DEFVAL 0x001C0000
19293 #define DDR_PHY_DX8SL2PLLCR0_PLLBYP_SHIFT 31
19294 #define DDR_PHY_DX8SL2PLLCR0_PLLBYP_MASK 0x80000000U
19299 #undef DDR_PHY_DX8SL2PLLCR0_PLLRST_DEFVAL
19300 #undef DDR_PHY_DX8SL2PLLCR0_PLLRST_SHIFT
19301 #undef DDR_PHY_DX8SL2PLLCR0_PLLRST_MASK
19302 #define DDR_PHY_DX8SL2PLLCR0_PLLRST_DEFVAL 0x001C0000
19303 #define DDR_PHY_DX8SL2PLLCR0_PLLRST_SHIFT 30
19304 #define DDR_PHY_DX8SL2PLLCR0_PLLRST_MASK 0x40000000U
19309 #undef DDR_PHY_DX8SL2PLLCR0_PLLPD_DEFVAL
19310 #undef DDR_PHY_DX8SL2PLLCR0_PLLPD_SHIFT
19311 #undef DDR_PHY_DX8SL2PLLCR0_PLLPD_MASK
19312 #define DDR_PHY_DX8SL2PLLCR0_PLLPD_DEFVAL 0x001C0000
19313 #define DDR_PHY_DX8SL2PLLCR0_PLLPD_SHIFT 29
19314 #define DDR_PHY_DX8SL2PLLCR0_PLLPD_MASK 0x20000000U
19317 * Reference Stop Mode
19319 #undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_DEFVAL
19320 #undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_SHIFT
19321 #undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_MASK
19322 #define DDR_PHY_DX8SL2PLLCR0_RSTOPM_DEFVAL 0x001C0000
19323 #define DDR_PHY_DX8SL2PLLCR0_RSTOPM_SHIFT 28
19324 #define DDR_PHY_DX8SL2PLLCR0_RSTOPM_MASK 0x10000000U
19327 * PLL Frequency Select
19329 #undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_DEFVAL
19330 #undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_SHIFT
19331 #undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_MASK
19332 #define DDR_PHY_DX8SL2PLLCR0_FRQSEL_DEFVAL 0x001C0000
19333 #define DDR_PHY_DX8SL2PLLCR0_FRQSEL_SHIFT 24
19334 #define DDR_PHY_DX8SL2PLLCR0_FRQSEL_MASK 0x0F000000U
19339 #undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_DEFVAL
19340 #undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_SHIFT
19341 #undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_MASK
19342 #define DDR_PHY_DX8SL2PLLCR0_RLOCKM_DEFVAL 0x001C0000
19343 #define DDR_PHY_DX8SL2PLLCR0_RLOCKM_SHIFT 23
19344 #define DDR_PHY_DX8SL2PLLCR0_RLOCKM_MASK 0x00800000U
19347 * Charge Pump Proportional Current Control
19349 #undef DDR_PHY_DX8SL2PLLCR0_CPPC_DEFVAL
19350 #undef DDR_PHY_DX8SL2PLLCR0_CPPC_SHIFT
19351 #undef DDR_PHY_DX8SL2PLLCR0_CPPC_MASK
19352 #define DDR_PHY_DX8SL2PLLCR0_CPPC_DEFVAL 0x001C0000
19353 #define DDR_PHY_DX8SL2PLLCR0_CPPC_SHIFT 17
19354 #define DDR_PHY_DX8SL2PLLCR0_CPPC_MASK 0x007E0000U
19357 * Charge Pump Integrating Current Control
19359 #undef DDR_PHY_DX8SL2PLLCR0_CPIC_DEFVAL
19360 #undef DDR_PHY_DX8SL2PLLCR0_CPIC_SHIFT
19361 #undef DDR_PHY_DX8SL2PLLCR0_CPIC_MASK
19362 #define DDR_PHY_DX8SL2PLLCR0_CPIC_DEFVAL 0x001C0000
19363 #define DDR_PHY_DX8SL2PLLCR0_CPIC_SHIFT 13
19364 #define DDR_PHY_DX8SL2PLLCR0_CPIC_MASK 0x0001E000U
19369 #undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_DEFVAL
19370 #undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_SHIFT
19371 #undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_MASK
19372 #define DDR_PHY_DX8SL2PLLCR0_GSHIFT_DEFVAL 0x001C0000
19373 #define DDR_PHY_DX8SL2PLLCR0_GSHIFT_SHIFT 12
19374 #define DDR_PHY_DX8SL2PLLCR0_GSHIFT_MASK 0x00001000U
19377 * Reserved. Return zeroes on reads.
19379 #undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_DEFVAL
19380 #undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT
19381 #undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_MASK
19382 #define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000
19383 #define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT 9
19384 #define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_MASK 0x00000E00U
19387 * Analog Test Enable (ATOEN)
19389 #undef DDR_PHY_DX8SL2PLLCR0_ATOEN_DEFVAL
19390 #undef DDR_PHY_DX8SL2PLLCR0_ATOEN_SHIFT
19391 #undef DDR_PHY_DX8SL2PLLCR0_ATOEN_MASK
19392 #define DDR_PHY_DX8SL2PLLCR0_ATOEN_DEFVAL 0x001C0000
19393 #define DDR_PHY_DX8SL2PLLCR0_ATOEN_SHIFT 8
19394 #define DDR_PHY_DX8SL2PLLCR0_ATOEN_MASK 0x00000100U
19397 * Analog Test Control
19399 #undef DDR_PHY_DX8SL2PLLCR0_ATC_DEFVAL
19400 #undef DDR_PHY_DX8SL2PLLCR0_ATC_SHIFT
19401 #undef DDR_PHY_DX8SL2PLLCR0_ATC_MASK
19402 #define DDR_PHY_DX8SL2PLLCR0_ATC_DEFVAL 0x001C0000
19403 #define DDR_PHY_DX8SL2PLLCR0_ATC_SHIFT 4
19404 #define DDR_PHY_DX8SL2PLLCR0_ATC_MASK 0x000000F0U
19407 * Digital Test Control
19409 #undef DDR_PHY_DX8SL2PLLCR0_DTC_DEFVAL
19410 #undef DDR_PHY_DX8SL2PLLCR0_DTC_SHIFT
19411 #undef DDR_PHY_DX8SL2PLLCR0_DTC_MASK
19412 #define DDR_PHY_DX8SL2PLLCR0_DTC_DEFVAL 0x001C0000
19413 #define DDR_PHY_DX8SL2PLLCR0_DTC_SHIFT 0
19414 #define DDR_PHY_DX8SL2PLLCR0_DTC_MASK 0x0000000FU
19417 * Reserved. Return zeroes on reads.
19419 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL
19420 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT
19421 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK
19422 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL 0x01264000
19423 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT 25
19424 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK 0xFE000000U
19427 * Read Path Rise-to-Rise Mode
19429 #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL
19430 #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT
19431 #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK
19432 #define DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL 0x01264000
19433 #define DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT 24
19434 #define DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK 0x01000000U
19437 * Reserved. Return zeroes on reads.
19439 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL
19440 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT
19441 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK
19442 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL 0x01264000
19443 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT 22
19444 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK 0x00C00000U
19447 * Write Path Rise-to-Rise Mode
19449 #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL
19450 #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT
19451 #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK
19452 #define DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL 0x01264000
19453 #define DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT 21
19454 #define DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK 0x00200000U
19457 * DQS Gate Extension
19459 #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL
19460 #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT
19461 #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK
19462 #define DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL 0x01264000
19463 #define DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT 19
19464 #define DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK 0x00180000U
19467 * Low Power PLL Power Down
19469 #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL
19470 #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT
19471 #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK
19472 #define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL 0x01264000
19473 #define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT 18
19474 #define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK 0x00040000U
19477 * Low Power I/O Power Down
19479 #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL
19480 #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT
19481 #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK
19482 #define DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL 0x01264000
19483 #define DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT 17
19484 #define DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK 0x00020000U
19487 * Reserved. Return zeroes on reads.
19489 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL
19490 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT
19491 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK
19492 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL 0x01264000
19493 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT 15
19494 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK 0x00018000U
19497 * QS Counter Enable
19499 #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL
19500 #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT
19501 #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK
19502 #define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL 0x01264000
19503 #define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT 14
19504 #define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK 0x00004000U
19507 * Unused DQ I/O Mode
19509 #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL
19510 #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT
19511 #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK
19512 #define DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL 0x01264000
19513 #define DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT 13
19514 #define DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK 0x00002000U
19517 * Reserved. Return zeroes on reads.
19519 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL
19520 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT
19521 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK
19522 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL 0x01264000
19523 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT 10
19524 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK 0x00001C00U
19529 #undef DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL
19530 #undef DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT
19531 #undef DDR_PHY_DX8SL2DQSCTL_DXSR_MASK
19532 #define DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL 0x01264000
19533 #define DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT 8
19534 #define DDR_PHY_DX8SL2DQSCTL_DXSR_MASK 0x00000300U
19539 #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL
19540 #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT
19541 #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK
19542 #define DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL 0x01264000
19543 #define DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT 4
19544 #define DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK 0x000000F0U
19549 #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL
19550 #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT
19551 #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK
19552 #define DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL 0x01264000
19553 #define DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT 0
19554 #define DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK 0x0000000FU
19557 * Reserved. Return zeroes on reads.
19559 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL
19560 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT
19561 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK
19562 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL 0x00141800
19563 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT 24
19564 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK 0xFF000000U
19567 * Configurable Read Data Enable
19569 #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL
19570 #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT
19571 #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK
19572 #define DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL 0x00141800
19573 #define DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT 23
19574 #define DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK 0x00800000U
19577 * OX Extension during Post-amble
19579 #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL
19580 #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT
19581 #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK
19582 #define DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL 0x00141800
19583 #define DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT 20
19584 #define DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK 0x00700000U
19587 * OE Extension during Pre-amble
19589 #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL
19590 #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT
19591 #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK
19592 #define DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL 0x00141800
19593 #define DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT 18
19594 #define DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK 0x000C0000U
19597 * Reserved. Return zeroes on reads.
19599 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL
19600 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT
19601 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK
19602 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL 0x00141800
19603 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT 17
19604 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK 0x00020000U
19607 * I/O Assisted Gate Select
19609 #undef DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL
19610 #undef DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT
19611 #undef DDR_PHY_DX8SL2DXCTL2_IOAG_MASK
19612 #define DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL 0x00141800
19613 #define DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT 16
19614 #define DDR_PHY_DX8SL2DXCTL2_IOAG_MASK 0x00010000U
19617 * I/O Loopback Select
19619 #undef DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL
19620 #undef DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT
19621 #undef DDR_PHY_DX8SL2DXCTL2_IOLB_MASK
19622 #define DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL 0x00141800
19623 #define DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT 15
19624 #define DDR_PHY_DX8SL2DXCTL2_IOLB_MASK 0x00008000U
19627 * Reserved. Return zeroes on reads.
19629 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL
19630 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT
19631 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK
19632 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL 0x00141800
19633 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT 13
19634 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK 0x00006000U
19637 * Low Power Wakeup Threshold
19639 #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL
19640 #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT
19641 #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK
19642 #define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800
19643 #define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT 9
19644 #define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U
19647 * Read Data Bus Inversion Enable
19649 #undef DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL
19650 #undef DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT
19651 #undef DDR_PHY_DX8SL2DXCTL2_RDBI_MASK
19652 #define DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL 0x00141800
19653 #define DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT 8
19654 #define DDR_PHY_DX8SL2DXCTL2_RDBI_MASK 0x00000100U
19657 * Write Data Bus Inversion Enable
19659 #undef DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL
19660 #undef DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT
19661 #undef DDR_PHY_DX8SL2DXCTL2_WDBI_MASK
19662 #define DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL 0x00141800
19663 #define DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT 7
19664 #define DDR_PHY_DX8SL2DXCTL2_WDBI_MASK 0x00000080U
19667 * PUB Read FIFO Bypass
19669 #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL
19670 #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT
19671 #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK
19672 #define DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL 0x00141800
19673 #define DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT 6
19674 #define DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK 0x00000040U
19677 * DATX8 Receive FIFO Read Mode
19679 #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL
19680 #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT
19681 #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK
19682 #define DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL 0x00141800
19683 #define DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT 4
19684 #define DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK 0x00000030U
19687 * Disables the Read FIFO Reset
19689 #undef DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL
19690 #undef DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT
19691 #undef DDR_PHY_DX8SL2DXCTL2_DISRST_MASK
19692 #define DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL 0x00141800
19693 #define DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT 3
19694 #define DDR_PHY_DX8SL2DXCTL2_DISRST_MASK 0x00000008U
19697 * Read DQS Gate I/O Loopback
19699 #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL
19700 #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT
19701 #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK
19702 #define DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL 0x00141800
19703 #define DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT 1
19704 #define DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK 0x00000006U
19707 * Reserved. Return zeroes on reads.
19709 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL
19710 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT
19711 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK
19712 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL 0x00141800
19713 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT 0
19714 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK 0x00000001U
19717 * Reserved. Return zeroes on reads.
19719 #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL
19720 #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT
19721 #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK
19722 #define DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL 0x00000000
19723 #define DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT 31
19724 #define DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK 0x80000000U
19727 * PVREF_DAC REFSEL range select
19729 #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL
19730 #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT
19731 #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK
19732 #define DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL 0x00000000
19733 #define DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT 28
19734 #define DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK 0x70000000U
19737 * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
19739 #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL
19740 #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT
19741 #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK
19742 #define DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL 0x00000000
19743 #define DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT 25
19744 #define DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK 0x0E000000U
19749 #undef DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL
19750 #undef DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT
19751 #undef DDR_PHY_DX8SL2IOCR_DXIOM_MASK
19752 #define DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL 0x00000000
19753 #define DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT 22
19754 #define DDR_PHY_DX8SL2IOCR_DXIOM_MASK 0x01C00000U
19757 * DX IO Transmitter Mode
19759 #undef DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL
19760 #undef DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT
19761 #undef DDR_PHY_DX8SL2IOCR_DXTXM_MASK
19762 #define DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL 0x00000000
19763 #define DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT 11
19764 #define DDR_PHY_DX8SL2IOCR_DXTXM_MASK 0x003FF800U
19767 * DX IO Receiver Mode
19769 #undef DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL
19770 #undef DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT
19771 #undef DDR_PHY_DX8SL2IOCR_DXRXM_MASK
19772 #define DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL 0x00000000
19773 #define DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT 0
19774 #define DDR_PHY_DX8SL2IOCR_DXRXM_MASK 0x000007FFU
19777 * Reserved. Return zeroes on reads.
19779 #undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL
19780 #undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT
19781 #undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK
19782 #define DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL 0x00019FFE
19783 #define DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT 30
19784 #define DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK 0xC0000000U
19787 * Enable Clock Gating for DX ddr_clk
19789 #undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL
19790 #undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT
19791 #undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK
19792 #define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL 0x00019FFE
19793 #define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT 28
19794 #define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK 0x30000000U
19797 * Enable Clock Gating for DX ctl_rd_clk
19799 #undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL
19800 #undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT
19801 #undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK
19802 #define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE
19803 #define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT 26
19804 #define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK 0x0C000000U
19807 * Enable Clock Gating for DX ctl_clk
19809 #undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL
19810 #undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT
19811 #undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK
19812 #define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE
19813 #define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT 24
19814 #define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK 0x03000000U
19817 * Selects the level to which clocks will be stalled when clock gating is e
19820 #undef DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL
19821 #undef DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT
19822 #undef DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK
19823 #define DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL 0x00019FFE
19824 #define DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT 22
19825 #define DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK 0x00C00000U
19830 #undef DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL
19831 #undef DDR_PHY_DX8SL3OSC_LBMODE_SHIFT
19832 #undef DDR_PHY_DX8SL3OSC_LBMODE_MASK
19833 #define DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL 0x00019FFE
19834 #define DDR_PHY_DX8SL3OSC_LBMODE_SHIFT 21
19835 #define DDR_PHY_DX8SL3OSC_LBMODE_MASK 0x00200000U
19838 * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
19840 #undef DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL
19841 #undef DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT
19842 #undef DDR_PHY_DX8SL3OSC_LBGSDQS_MASK
19843 #define DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL 0x00019FFE
19844 #define DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT 20
19845 #define DDR_PHY_DX8SL3OSC_LBGSDQS_MASK 0x00100000U
19848 * Loopback DQS Gating
19850 #undef DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL
19851 #undef DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT
19852 #undef DDR_PHY_DX8SL3OSC_LBGDQS_MASK
19853 #define DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL 0x00019FFE
19854 #define DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT 18
19855 #define DDR_PHY_DX8SL3OSC_LBGDQS_MASK 0x000C0000U
19858 * Loopback DQS Shift
19860 #undef DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL
19861 #undef DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT
19862 #undef DDR_PHY_DX8SL3OSC_LBDQSS_MASK
19863 #define DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL 0x00019FFE
19864 #define DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT 17
19865 #define DDR_PHY_DX8SL3OSC_LBDQSS_MASK 0x00020000U
19868 * PHY High-Speed Reset
19870 #undef DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL
19871 #undef DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT
19872 #undef DDR_PHY_DX8SL3OSC_PHYHRST_MASK
19873 #define DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL 0x00019FFE
19874 #define DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT 16
19875 #define DDR_PHY_DX8SL3OSC_PHYHRST_MASK 0x00010000U
19880 #undef DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL
19881 #undef DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT
19882 #undef DDR_PHY_DX8SL3OSC_PHYFRST_MASK
19883 #define DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL 0x00019FFE
19884 #define DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT 15
19885 #define DDR_PHY_DX8SL3OSC_PHYFRST_MASK 0x00008000U
19888 * Delay Line Test Start
19890 #undef DDR_PHY_DX8SL3OSC_DLTST_DEFVAL
19891 #undef DDR_PHY_DX8SL3OSC_DLTST_SHIFT
19892 #undef DDR_PHY_DX8SL3OSC_DLTST_MASK
19893 #define DDR_PHY_DX8SL3OSC_DLTST_DEFVAL 0x00019FFE
19894 #define DDR_PHY_DX8SL3OSC_DLTST_SHIFT 14
19895 #define DDR_PHY_DX8SL3OSC_DLTST_MASK 0x00004000U
19898 * Delay Line Test Mode
19900 #undef DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL
19901 #undef DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT
19902 #undef DDR_PHY_DX8SL3OSC_DLTMODE_MASK
19903 #define DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL 0x00019FFE
19904 #define DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT 13
19905 #define DDR_PHY_DX8SL3OSC_DLTMODE_MASK 0x00002000U
19908 * Reserved. Caution, do not write to this register field.
19910 #undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL
19911 #undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT
19912 #undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK
19913 #define DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL 0x00019FFE
19914 #define DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT 11
19915 #define DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK 0x00001800U
19918 * Oscillator Mode Write-Data Delay Line Select
19920 #undef DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL
19921 #undef DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT
19922 #undef DDR_PHY_DX8SL3OSC_OSCWDDL_MASK
19923 #define DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL 0x00019FFE
19924 #define DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT 9
19925 #define DDR_PHY_DX8SL3OSC_OSCWDDL_MASK 0x00000600U
19928 * Reserved. Caution, do not write to this register field.
19930 #undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL
19931 #undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT
19932 #undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK
19933 #define DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL 0x00019FFE
19934 #define DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT 7
19935 #define DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK 0x00000180U
19938 * Oscillator Mode Write-Leveling Delay Line Select
19940 #undef DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL
19941 #undef DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT
19942 #undef DDR_PHY_DX8SL3OSC_OSCWDL_MASK
19943 #define DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL 0x00019FFE
19944 #define DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT 5
19945 #define DDR_PHY_DX8SL3OSC_OSCWDL_MASK 0x00000060U
19948 * Oscillator Mode Division
19950 #undef DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL
19951 #undef DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT
19952 #undef DDR_PHY_DX8SL3OSC_OSCDIV_MASK
19953 #define DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL 0x00019FFE
19954 #define DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT 1
19955 #define DDR_PHY_DX8SL3OSC_OSCDIV_MASK 0x0000001EU
19958 * Oscillator Enable
19960 #undef DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL
19961 #undef DDR_PHY_DX8SL3OSC_OSCEN_SHIFT
19962 #undef DDR_PHY_DX8SL3OSC_OSCEN_MASK
19963 #define DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL 0x00019FFE
19964 #define DDR_PHY_DX8SL3OSC_OSCEN_SHIFT 0
19965 #define DDR_PHY_DX8SL3OSC_OSCEN_MASK 0x00000001U
19970 #undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_DEFVAL
19971 #undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_SHIFT
19972 #undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_MASK
19973 #define DDR_PHY_DX8SL3PLLCR0_PLLBYP_DEFVAL 0x001C0000
19974 #define DDR_PHY_DX8SL3PLLCR0_PLLBYP_SHIFT 31
19975 #define DDR_PHY_DX8SL3PLLCR0_PLLBYP_MASK 0x80000000U
19980 #undef DDR_PHY_DX8SL3PLLCR0_PLLRST_DEFVAL
19981 #undef DDR_PHY_DX8SL3PLLCR0_PLLRST_SHIFT
19982 #undef DDR_PHY_DX8SL3PLLCR0_PLLRST_MASK
19983 #define DDR_PHY_DX8SL3PLLCR0_PLLRST_DEFVAL 0x001C0000
19984 #define DDR_PHY_DX8SL3PLLCR0_PLLRST_SHIFT 30
19985 #define DDR_PHY_DX8SL3PLLCR0_PLLRST_MASK 0x40000000U
19990 #undef DDR_PHY_DX8SL3PLLCR0_PLLPD_DEFVAL
19991 #undef DDR_PHY_DX8SL3PLLCR0_PLLPD_SHIFT
19992 #undef DDR_PHY_DX8SL3PLLCR0_PLLPD_MASK
19993 #define DDR_PHY_DX8SL3PLLCR0_PLLPD_DEFVAL 0x001C0000
19994 #define DDR_PHY_DX8SL3PLLCR0_PLLPD_SHIFT 29
19995 #define DDR_PHY_DX8SL3PLLCR0_PLLPD_MASK 0x20000000U
19998 * Reference Stop Mode
20000 #undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_DEFVAL
20001 #undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_SHIFT
20002 #undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_MASK
20003 #define DDR_PHY_DX8SL3PLLCR0_RSTOPM_DEFVAL 0x001C0000
20004 #define DDR_PHY_DX8SL3PLLCR0_RSTOPM_SHIFT 28
20005 #define DDR_PHY_DX8SL3PLLCR0_RSTOPM_MASK 0x10000000U
20008 * PLL Frequency Select
20010 #undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_DEFVAL
20011 #undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_SHIFT
20012 #undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_MASK
20013 #define DDR_PHY_DX8SL3PLLCR0_FRQSEL_DEFVAL 0x001C0000
20014 #define DDR_PHY_DX8SL3PLLCR0_FRQSEL_SHIFT 24
20015 #define DDR_PHY_DX8SL3PLLCR0_FRQSEL_MASK 0x0F000000U
20020 #undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_DEFVAL
20021 #undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_SHIFT
20022 #undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_MASK
20023 #define DDR_PHY_DX8SL3PLLCR0_RLOCKM_DEFVAL 0x001C0000
20024 #define DDR_PHY_DX8SL3PLLCR0_RLOCKM_SHIFT 23
20025 #define DDR_PHY_DX8SL3PLLCR0_RLOCKM_MASK 0x00800000U
20028 * Charge Pump Proportional Current Control
20030 #undef DDR_PHY_DX8SL3PLLCR0_CPPC_DEFVAL
20031 #undef DDR_PHY_DX8SL3PLLCR0_CPPC_SHIFT
20032 #undef DDR_PHY_DX8SL3PLLCR0_CPPC_MASK
20033 #define DDR_PHY_DX8SL3PLLCR0_CPPC_DEFVAL 0x001C0000
20034 #define DDR_PHY_DX8SL3PLLCR0_CPPC_SHIFT 17
20035 #define DDR_PHY_DX8SL3PLLCR0_CPPC_MASK 0x007E0000U
20038 * Charge Pump Integrating Current Control
20040 #undef DDR_PHY_DX8SL3PLLCR0_CPIC_DEFVAL
20041 #undef DDR_PHY_DX8SL3PLLCR0_CPIC_SHIFT
20042 #undef DDR_PHY_DX8SL3PLLCR0_CPIC_MASK
20043 #define DDR_PHY_DX8SL3PLLCR0_CPIC_DEFVAL 0x001C0000
20044 #define DDR_PHY_DX8SL3PLLCR0_CPIC_SHIFT 13
20045 #define DDR_PHY_DX8SL3PLLCR0_CPIC_MASK 0x0001E000U
20050 #undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_DEFVAL
20051 #undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_SHIFT
20052 #undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_MASK
20053 #define DDR_PHY_DX8SL3PLLCR0_GSHIFT_DEFVAL 0x001C0000
20054 #define DDR_PHY_DX8SL3PLLCR0_GSHIFT_SHIFT 12
20055 #define DDR_PHY_DX8SL3PLLCR0_GSHIFT_MASK 0x00001000U
20058 * Reserved. Return zeroes on reads.
20060 #undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_DEFVAL
20061 #undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT
20062 #undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_MASK
20063 #define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000
20064 #define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT 9
20065 #define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_MASK 0x00000E00U
20068 * Analog Test Enable (ATOEN)
20070 #undef DDR_PHY_DX8SL3PLLCR0_ATOEN_DEFVAL
20071 #undef DDR_PHY_DX8SL3PLLCR0_ATOEN_SHIFT
20072 #undef DDR_PHY_DX8SL3PLLCR0_ATOEN_MASK
20073 #define DDR_PHY_DX8SL3PLLCR0_ATOEN_DEFVAL 0x001C0000
20074 #define DDR_PHY_DX8SL3PLLCR0_ATOEN_SHIFT 8
20075 #define DDR_PHY_DX8SL3PLLCR0_ATOEN_MASK 0x00000100U
20078 * Analog Test Control
20080 #undef DDR_PHY_DX8SL3PLLCR0_ATC_DEFVAL
20081 #undef DDR_PHY_DX8SL3PLLCR0_ATC_SHIFT
20082 #undef DDR_PHY_DX8SL3PLLCR0_ATC_MASK
20083 #define DDR_PHY_DX8SL3PLLCR0_ATC_DEFVAL 0x001C0000
20084 #define DDR_PHY_DX8SL3PLLCR0_ATC_SHIFT 4
20085 #define DDR_PHY_DX8SL3PLLCR0_ATC_MASK 0x000000F0U
20088 * Digital Test Control
20090 #undef DDR_PHY_DX8SL3PLLCR0_DTC_DEFVAL
20091 #undef DDR_PHY_DX8SL3PLLCR0_DTC_SHIFT
20092 #undef DDR_PHY_DX8SL3PLLCR0_DTC_MASK
20093 #define DDR_PHY_DX8SL3PLLCR0_DTC_DEFVAL 0x001C0000
20094 #define DDR_PHY_DX8SL3PLLCR0_DTC_SHIFT 0
20095 #define DDR_PHY_DX8SL3PLLCR0_DTC_MASK 0x0000000FU
20098 * Reserved. Return zeroes on reads.
20100 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL
20101 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT
20102 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK
20103 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL 0x01264000
20104 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT 25
20105 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK 0xFE000000U
20108 * Read Path Rise-to-Rise Mode
20110 #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL
20111 #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT
20112 #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK
20113 #define DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL 0x01264000
20114 #define DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT 24
20115 #define DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK 0x01000000U
20118 * Reserved. Return zeroes on reads.
20120 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL
20121 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT
20122 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK
20123 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL 0x01264000
20124 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT 22
20125 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK 0x00C00000U
20128 * Write Path Rise-to-Rise Mode
20130 #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL
20131 #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT
20132 #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK
20133 #define DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL 0x01264000
20134 #define DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT 21
20135 #define DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK 0x00200000U
20138 * DQS Gate Extension
20140 #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL
20141 #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT
20142 #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK
20143 #define DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL 0x01264000
20144 #define DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT 19
20145 #define DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK 0x00180000U
20148 * Low Power PLL Power Down
20150 #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL
20151 #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT
20152 #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK
20153 #define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL 0x01264000
20154 #define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT 18
20155 #define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK 0x00040000U
20158 * Low Power I/O Power Down
20160 #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL
20161 #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT
20162 #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK
20163 #define DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL 0x01264000
20164 #define DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT 17
20165 #define DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK 0x00020000U
20168 * Reserved. Return zeroes on reads.
20170 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL
20171 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT
20172 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK
20173 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL 0x01264000
20174 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT 15
20175 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK 0x00018000U
20178 * QS Counter Enable
20180 #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL
20181 #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT
20182 #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK
20183 #define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL 0x01264000
20184 #define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT 14
20185 #define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK 0x00004000U
20188 * Unused DQ I/O Mode
20190 #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL
20191 #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT
20192 #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK
20193 #define DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL 0x01264000
20194 #define DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT 13
20195 #define DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK 0x00002000U
20198 * Reserved. Return zeroes on reads.
20200 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL
20201 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT
20202 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK
20203 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL 0x01264000
20204 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT 10
20205 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK 0x00001C00U
20210 #undef DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL
20211 #undef DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT
20212 #undef DDR_PHY_DX8SL3DQSCTL_DXSR_MASK
20213 #define DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL 0x01264000
20214 #define DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT 8
20215 #define DDR_PHY_DX8SL3DQSCTL_DXSR_MASK 0x00000300U
20220 #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL
20221 #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT
20222 #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK
20223 #define DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL 0x01264000
20224 #define DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT 4
20225 #define DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK 0x000000F0U
20230 #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL
20231 #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT
20232 #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK
20233 #define DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL 0x01264000
20234 #define DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT 0
20235 #define DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK 0x0000000FU
20238 * Reserved. Return zeroes on reads.
20240 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL
20241 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT
20242 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK
20243 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL 0x00141800
20244 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT 24
20245 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK 0xFF000000U
20248 * Configurable Read Data Enable
20250 #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL
20251 #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT
20252 #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK
20253 #define DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL 0x00141800
20254 #define DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT 23
20255 #define DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK 0x00800000U
20258 * OX Extension during Post-amble
20260 #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL
20261 #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT
20262 #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK
20263 #define DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL 0x00141800
20264 #define DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT 20
20265 #define DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK 0x00700000U
20268 * OE Extension during Pre-amble
20270 #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL
20271 #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT
20272 #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK
20273 #define DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL 0x00141800
20274 #define DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT 18
20275 #define DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK 0x000C0000U
20278 * Reserved. Return zeroes on reads.
20280 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL
20281 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT
20282 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK
20283 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL 0x00141800
20284 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT 17
20285 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK 0x00020000U
20288 * I/O Assisted Gate Select
20290 #undef DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL
20291 #undef DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT
20292 #undef DDR_PHY_DX8SL3DXCTL2_IOAG_MASK
20293 #define DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL 0x00141800
20294 #define DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT 16
20295 #define DDR_PHY_DX8SL3DXCTL2_IOAG_MASK 0x00010000U
20298 * I/O Loopback Select
20300 #undef DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL
20301 #undef DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT
20302 #undef DDR_PHY_DX8SL3DXCTL2_IOLB_MASK
20303 #define DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL 0x00141800
20304 #define DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT 15
20305 #define DDR_PHY_DX8SL3DXCTL2_IOLB_MASK 0x00008000U
20308 * Reserved. Return zeroes on reads.
20310 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL
20311 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT
20312 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK
20313 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL 0x00141800
20314 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT 13
20315 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK 0x00006000U
20318 * Low Power Wakeup Threshold
20320 #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL
20321 #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT
20322 #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK
20323 #define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800
20324 #define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT 9
20325 #define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U
20328 * Read Data Bus Inversion Enable
20330 #undef DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL
20331 #undef DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT
20332 #undef DDR_PHY_DX8SL3DXCTL2_RDBI_MASK
20333 #define DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL 0x00141800
20334 #define DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT 8
20335 #define DDR_PHY_DX8SL3DXCTL2_RDBI_MASK 0x00000100U
20338 * Write Data Bus Inversion Enable
20340 #undef DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL
20341 #undef DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT
20342 #undef DDR_PHY_DX8SL3DXCTL2_WDBI_MASK
20343 #define DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL 0x00141800
20344 #define DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT 7
20345 #define DDR_PHY_DX8SL3DXCTL2_WDBI_MASK 0x00000080U
20348 * PUB Read FIFO Bypass
20350 #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL
20351 #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT
20352 #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK
20353 #define DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL 0x00141800
20354 #define DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT 6
20355 #define DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK 0x00000040U
20358 * DATX8 Receive FIFO Read Mode
20360 #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL
20361 #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT
20362 #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK
20363 #define DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL 0x00141800
20364 #define DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT 4
20365 #define DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK 0x00000030U
20368 * Disables the Read FIFO Reset
20370 #undef DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL
20371 #undef DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT
20372 #undef DDR_PHY_DX8SL3DXCTL2_DISRST_MASK
20373 #define DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL 0x00141800
20374 #define DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT 3
20375 #define DDR_PHY_DX8SL3DXCTL2_DISRST_MASK 0x00000008U
20378 * Read DQS Gate I/O Loopback
20380 #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL
20381 #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT
20382 #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK
20383 #define DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL 0x00141800
20384 #define DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT 1
20385 #define DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK 0x00000006U
20388 * Reserved. Return zeroes on reads.
20390 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL
20391 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT
20392 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK
20393 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL 0x00141800
20394 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT 0
20395 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK 0x00000001U
20398 * Reserved. Return zeroes on reads.
20400 #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL
20401 #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT
20402 #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK
20403 #define DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL 0x00000000
20404 #define DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT 31
20405 #define DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK 0x80000000U
20408 * PVREF_DAC REFSEL range select
20410 #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL
20411 #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT
20412 #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK
20413 #define DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL 0x00000000
20414 #define DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT 28
20415 #define DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK 0x70000000U
20418 * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
20420 #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL
20421 #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT
20422 #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK
20423 #define DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL 0x00000000
20424 #define DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT 25
20425 #define DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK 0x0E000000U
20430 #undef DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL
20431 #undef DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT
20432 #undef DDR_PHY_DX8SL3IOCR_DXIOM_MASK
20433 #define DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL 0x00000000
20434 #define DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT 22
20435 #define DDR_PHY_DX8SL3IOCR_DXIOM_MASK 0x01C00000U
20438 * DX IO Transmitter Mode
20440 #undef DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL
20441 #undef DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT
20442 #undef DDR_PHY_DX8SL3IOCR_DXTXM_MASK
20443 #define DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL 0x00000000
20444 #define DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT 11
20445 #define DDR_PHY_DX8SL3IOCR_DXTXM_MASK 0x003FF800U
20448 * DX IO Receiver Mode
20450 #undef DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL
20451 #undef DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT
20452 #undef DDR_PHY_DX8SL3IOCR_DXRXM_MASK
20453 #define DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL 0x00000000
20454 #define DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT 0
20455 #define DDR_PHY_DX8SL3IOCR_DXRXM_MASK 0x000007FFU
20458 * Reserved. Return zeroes on reads.
20460 #undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL
20461 #undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT
20462 #undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK
20463 #define DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL 0x00019FFE
20464 #define DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT 30
20465 #define DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK 0xC0000000U
20468 * Enable Clock Gating for DX ddr_clk
20470 #undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL
20471 #undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT
20472 #undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK
20473 #define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL 0x00019FFE
20474 #define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT 28
20475 #define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK 0x30000000U
20478 * Enable Clock Gating for DX ctl_rd_clk
20480 #undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL
20481 #undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT
20482 #undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK
20483 #define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE
20484 #define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT 26
20485 #define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK 0x0C000000U
20488 * Enable Clock Gating for DX ctl_clk
20490 #undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL
20491 #undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT
20492 #undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK
20493 #define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE
20494 #define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT 24
20495 #define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK 0x03000000U
20498 * Selects the level to which clocks will be stalled when clock gating is e
20501 #undef DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL
20502 #undef DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT
20503 #undef DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK
20504 #define DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL 0x00019FFE
20505 #define DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT 22
20506 #define DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK 0x00C00000U
20511 #undef DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL
20512 #undef DDR_PHY_DX8SL4OSC_LBMODE_SHIFT
20513 #undef DDR_PHY_DX8SL4OSC_LBMODE_MASK
20514 #define DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL 0x00019FFE
20515 #define DDR_PHY_DX8SL4OSC_LBMODE_SHIFT 21
20516 #define DDR_PHY_DX8SL4OSC_LBMODE_MASK 0x00200000U
20519 * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
20521 #undef DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL
20522 #undef DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT
20523 #undef DDR_PHY_DX8SL4OSC_LBGSDQS_MASK
20524 #define DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL 0x00019FFE
20525 #define DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT 20
20526 #define DDR_PHY_DX8SL4OSC_LBGSDQS_MASK 0x00100000U
20529 * Loopback DQS Gating
20531 #undef DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL
20532 #undef DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT
20533 #undef DDR_PHY_DX8SL4OSC_LBGDQS_MASK
20534 #define DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL 0x00019FFE
20535 #define DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT 18
20536 #define DDR_PHY_DX8SL4OSC_LBGDQS_MASK 0x000C0000U
20539 * Loopback DQS Shift
20541 #undef DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL
20542 #undef DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT
20543 #undef DDR_PHY_DX8SL4OSC_LBDQSS_MASK
20544 #define DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL 0x00019FFE
20545 #define DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT 17
20546 #define DDR_PHY_DX8SL4OSC_LBDQSS_MASK 0x00020000U
20549 * PHY High-Speed Reset
20551 #undef DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL
20552 #undef DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT
20553 #undef DDR_PHY_DX8SL4OSC_PHYHRST_MASK
20554 #define DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL 0x00019FFE
20555 #define DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT 16
20556 #define DDR_PHY_DX8SL4OSC_PHYHRST_MASK 0x00010000U
20561 #undef DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL
20562 #undef DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT
20563 #undef DDR_PHY_DX8SL4OSC_PHYFRST_MASK
20564 #define DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL 0x00019FFE
20565 #define DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT 15
20566 #define DDR_PHY_DX8SL4OSC_PHYFRST_MASK 0x00008000U
20569 * Delay Line Test Start
20571 #undef DDR_PHY_DX8SL4OSC_DLTST_DEFVAL
20572 #undef DDR_PHY_DX8SL4OSC_DLTST_SHIFT
20573 #undef DDR_PHY_DX8SL4OSC_DLTST_MASK
20574 #define DDR_PHY_DX8SL4OSC_DLTST_DEFVAL 0x00019FFE
20575 #define DDR_PHY_DX8SL4OSC_DLTST_SHIFT 14
20576 #define DDR_PHY_DX8SL4OSC_DLTST_MASK 0x00004000U
20579 * Delay Line Test Mode
20581 #undef DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL
20582 #undef DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT
20583 #undef DDR_PHY_DX8SL4OSC_DLTMODE_MASK
20584 #define DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL 0x00019FFE
20585 #define DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT 13
20586 #define DDR_PHY_DX8SL4OSC_DLTMODE_MASK 0x00002000U
20589 * Reserved. Caution, do not write to this register field.
20591 #undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL
20592 #undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT
20593 #undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK
20594 #define DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL 0x00019FFE
20595 #define DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT 11
20596 #define DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK 0x00001800U
20599 * Oscillator Mode Write-Data Delay Line Select
20601 #undef DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL
20602 #undef DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT
20603 #undef DDR_PHY_DX8SL4OSC_OSCWDDL_MASK
20604 #define DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL 0x00019FFE
20605 #define DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT 9
20606 #define DDR_PHY_DX8SL4OSC_OSCWDDL_MASK 0x00000600U
20609 * Reserved. Caution, do not write to this register field.
20611 #undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL
20612 #undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT
20613 #undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK
20614 #define DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL 0x00019FFE
20615 #define DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT 7
20616 #define DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK 0x00000180U
20619 * Oscillator Mode Write-Leveling Delay Line Select
20621 #undef DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL
20622 #undef DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT
20623 #undef DDR_PHY_DX8SL4OSC_OSCWDL_MASK
20624 #define DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL 0x00019FFE
20625 #define DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT 5
20626 #define DDR_PHY_DX8SL4OSC_OSCWDL_MASK 0x00000060U
20629 * Oscillator Mode Division
20631 #undef DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL
20632 #undef DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT
20633 #undef DDR_PHY_DX8SL4OSC_OSCDIV_MASK
20634 #define DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL 0x00019FFE
20635 #define DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT 1
20636 #define DDR_PHY_DX8SL4OSC_OSCDIV_MASK 0x0000001EU
20639 * Oscillator Enable
20641 #undef DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL
20642 #undef DDR_PHY_DX8SL4OSC_OSCEN_SHIFT
20643 #undef DDR_PHY_DX8SL4OSC_OSCEN_MASK
20644 #define DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL 0x00019FFE
20645 #define DDR_PHY_DX8SL4OSC_OSCEN_SHIFT 0
20646 #define DDR_PHY_DX8SL4OSC_OSCEN_MASK 0x00000001U
20651 #undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_DEFVAL
20652 #undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_SHIFT
20653 #undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_MASK
20654 #define DDR_PHY_DX8SL4PLLCR0_PLLBYP_DEFVAL 0x001C0000
20655 #define DDR_PHY_DX8SL4PLLCR0_PLLBYP_SHIFT 31
20656 #define DDR_PHY_DX8SL4PLLCR0_PLLBYP_MASK 0x80000000U
20661 #undef DDR_PHY_DX8SL4PLLCR0_PLLRST_DEFVAL
20662 #undef DDR_PHY_DX8SL4PLLCR0_PLLRST_SHIFT
20663 #undef DDR_PHY_DX8SL4PLLCR0_PLLRST_MASK
20664 #define DDR_PHY_DX8SL4PLLCR0_PLLRST_DEFVAL 0x001C0000
20665 #define DDR_PHY_DX8SL4PLLCR0_PLLRST_SHIFT 30
20666 #define DDR_PHY_DX8SL4PLLCR0_PLLRST_MASK 0x40000000U
20671 #undef DDR_PHY_DX8SL4PLLCR0_PLLPD_DEFVAL
20672 #undef DDR_PHY_DX8SL4PLLCR0_PLLPD_SHIFT
20673 #undef DDR_PHY_DX8SL4PLLCR0_PLLPD_MASK
20674 #define DDR_PHY_DX8SL4PLLCR0_PLLPD_DEFVAL 0x001C0000
20675 #define DDR_PHY_DX8SL4PLLCR0_PLLPD_SHIFT 29
20676 #define DDR_PHY_DX8SL4PLLCR0_PLLPD_MASK 0x20000000U
20679 * Reference Stop Mode
20681 #undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_DEFVAL
20682 #undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_SHIFT
20683 #undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_MASK
20684 #define DDR_PHY_DX8SL4PLLCR0_RSTOPM_DEFVAL 0x001C0000
20685 #define DDR_PHY_DX8SL4PLLCR0_RSTOPM_SHIFT 28
20686 #define DDR_PHY_DX8SL4PLLCR0_RSTOPM_MASK 0x10000000U
20689 * PLL Frequency Select
20691 #undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_DEFVAL
20692 #undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_SHIFT
20693 #undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_MASK
20694 #define DDR_PHY_DX8SL4PLLCR0_FRQSEL_DEFVAL 0x001C0000
20695 #define DDR_PHY_DX8SL4PLLCR0_FRQSEL_SHIFT 24
20696 #define DDR_PHY_DX8SL4PLLCR0_FRQSEL_MASK 0x0F000000U
20701 #undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_DEFVAL
20702 #undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_SHIFT
20703 #undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_MASK
20704 #define DDR_PHY_DX8SL4PLLCR0_RLOCKM_DEFVAL 0x001C0000
20705 #define DDR_PHY_DX8SL4PLLCR0_RLOCKM_SHIFT 23
20706 #define DDR_PHY_DX8SL4PLLCR0_RLOCKM_MASK 0x00800000U
20709 * Charge Pump Proportional Current Control
20711 #undef DDR_PHY_DX8SL4PLLCR0_CPPC_DEFVAL
20712 #undef DDR_PHY_DX8SL4PLLCR0_CPPC_SHIFT
20713 #undef DDR_PHY_DX8SL4PLLCR0_CPPC_MASK
20714 #define DDR_PHY_DX8SL4PLLCR0_CPPC_DEFVAL 0x001C0000
20715 #define DDR_PHY_DX8SL4PLLCR0_CPPC_SHIFT 17
20716 #define DDR_PHY_DX8SL4PLLCR0_CPPC_MASK 0x007E0000U
20719 * Charge Pump Integrating Current Control
20721 #undef DDR_PHY_DX8SL4PLLCR0_CPIC_DEFVAL
20722 #undef DDR_PHY_DX8SL4PLLCR0_CPIC_SHIFT
20723 #undef DDR_PHY_DX8SL4PLLCR0_CPIC_MASK
20724 #define DDR_PHY_DX8SL4PLLCR0_CPIC_DEFVAL 0x001C0000
20725 #define DDR_PHY_DX8SL4PLLCR0_CPIC_SHIFT 13
20726 #define DDR_PHY_DX8SL4PLLCR0_CPIC_MASK 0x0001E000U
20731 #undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_DEFVAL
20732 #undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_SHIFT
20733 #undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_MASK
20734 #define DDR_PHY_DX8SL4PLLCR0_GSHIFT_DEFVAL 0x001C0000
20735 #define DDR_PHY_DX8SL4PLLCR0_GSHIFT_SHIFT 12
20736 #define DDR_PHY_DX8SL4PLLCR0_GSHIFT_MASK 0x00001000U
20739 * Reserved. Return zeroes on reads.
20741 #undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_DEFVAL
20742 #undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT
20743 #undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_MASK
20744 #define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000
20745 #define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT 9
20746 #define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_MASK 0x00000E00U
20749 * Analog Test Enable (ATOEN)
20751 #undef DDR_PHY_DX8SL4PLLCR0_ATOEN_DEFVAL
20752 #undef DDR_PHY_DX8SL4PLLCR0_ATOEN_SHIFT
20753 #undef DDR_PHY_DX8SL4PLLCR0_ATOEN_MASK
20754 #define DDR_PHY_DX8SL4PLLCR0_ATOEN_DEFVAL 0x001C0000
20755 #define DDR_PHY_DX8SL4PLLCR0_ATOEN_SHIFT 8
20756 #define DDR_PHY_DX8SL4PLLCR0_ATOEN_MASK 0x00000100U
20759 * Analog Test Control
20761 #undef DDR_PHY_DX8SL4PLLCR0_ATC_DEFVAL
20762 #undef DDR_PHY_DX8SL4PLLCR0_ATC_SHIFT
20763 #undef DDR_PHY_DX8SL4PLLCR0_ATC_MASK
20764 #define DDR_PHY_DX8SL4PLLCR0_ATC_DEFVAL 0x001C0000
20765 #define DDR_PHY_DX8SL4PLLCR0_ATC_SHIFT 4
20766 #define DDR_PHY_DX8SL4PLLCR0_ATC_MASK 0x000000F0U
20769 * Digital Test Control
20771 #undef DDR_PHY_DX8SL4PLLCR0_DTC_DEFVAL
20772 #undef DDR_PHY_DX8SL4PLLCR0_DTC_SHIFT
20773 #undef DDR_PHY_DX8SL4PLLCR0_DTC_MASK
20774 #define DDR_PHY_DX8SL4PLLCR0_DTC_DEFVAL 0x001C0000
20775 #define DDR_PHY_DX8SL4PLLCR0_DTC_SHIFT 0
20776 #define DDR_PHY_DX8SL4PLLCR0_DTC_MASK 0x0000000FU
20779 * Reserved. Return zeroes on reads.
20781 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL
20782 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT
20783 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK
20784 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL 0x01264000
20785 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT 25
20786 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK 0xFE000000U
20789 * Read Path Rise-to-Rise Mode
20791 #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL
20792 #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT
20793 #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK
20794 #define DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL 0x01264000
20795 #define DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT 24
20796 #define DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK 0x01000000U
20799 * Reserved. Return zeroes on reads.
20801 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL
20802 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT
20803 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK
20804 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL 0x01264000
20805 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT 22
20806 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK 0x00C00000U
20809 * Write Path Rise-to-Rise Mode
20811 #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL
20812 #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT
20813 #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK
20814 #define DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL 0x01264000
20815 #define DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT 21
20816 #define DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK 0x00200000U
20819 * DQS Gate Extension
20821 #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL
20822 #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT
20823 #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK
20824 #define DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL 0x01264000
20825 #define DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT 19
20826 #define DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK 0x00180000U
20829 * Low Power PLL Power Down
20831 #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL
20832 #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT
20833 #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK
20834 #define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL 0x01264000
20835 #define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT 18
20836 #define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK 0x00040000U
20839 * Low Power I/O Power Down
20841 #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL
20842 #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT
20843 #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK
20844 #define DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL 0x01264000
20845 #define DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT 17
20846 #define DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK 0x00020000U
20849 * Reserved. Return zeroes on reads.
20851 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL
20852 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT
20853 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK
20854 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL 0x01264000
20855 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT 15
20856 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK 0x00018000U
20859 * QS Counter Enable
20861 #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL
20862 #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT
20863 #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK
20864 #define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL 0x01264000
20865 #define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT 14
20866 #define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK 0x00004000U
20869 * Unused DQ I/O Mode
20871 #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL
20872 #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT
20873 #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK
20874 #define DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL 0x01264000
20875 #define DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT 13
20876 #define DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK 0x00002000U
20879 * Reserved. Return zeroes on reads.
20881 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL
20882 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT
20883 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK
20884 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL 0x01264000
20885 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT 10
20886 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK 0x00001C00U
20891 #undef DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL
20892 #undef DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT
20893 #undef DDR_PHY_DX8SL4DQSCTL_DXSR_MASK
20894 #define DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL 0x01264000
20895 #define DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT 8
20896 #define DDR_PHY_DX8SL4DQSCTL_DXSR_MASK 0x00000300U
20901 #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL
20902 #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT
20903 #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK
20904 #define DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL 0x01264000
20905 #define DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT 4
20906 #define DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK 0x000000F0U
20911 #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL
20912 #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT
20913 #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK
20914 #define DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL 0x01264000
20915 #define DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT 0
20916 #define DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK 0x0000000FU
20919 * Reserved. Return zeroes on reads.
20921 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL
20922 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT
20923 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK
20924 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL 0x00141800
20925 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT 24
20926 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK 0xFF000000U
20929 * Configurable Read Data Enable
20931 #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL
20932 #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT
20933 #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK
20934 #define DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL 0x00141800
20935 #define DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT 23
20936 #define DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK 0x00800000U
20939 * OX Extension during Post-amble
20941 #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL
20942 #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT
20943 #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK
20944 #define DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL 0x00141800
20945 #define DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT 20
20946 #define DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK 0x00700000U
20949 * OE Extension during Pre-amble
20951 #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL
20952 #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT
20953 #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK
20954 #define DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL 0x00141800
20955 #define DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT 18
20956 #define DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK 0x000C0000U
20959 * Reserved. Return zeroes on reads.
20961 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL
20962 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT
20963 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK
20964 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL 0x00141800
20965 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT 17
20966 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK 0x00020000U
20969 * I/O Assisted Gate Select
20971 #undef DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL
20972 #undef DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT
20973 #undef DDR_PHY_DX8SL4DXCTL2_IOAG_MASK
20974 #define DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL 0x00141800
20975 #define DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT 16
20976 #define DDR_PHY_DX8SL4DXCTL2_IOAG_MASK 0x00010000U
20979 * I/O Loopback Select
20981 #undef DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL
20982 #undef DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT
20983 #undef DDR_PHY_DX8SL4DXCTL2_IOLB_MASK
20984 #define DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL 0x00141800
20985 #define DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT 15
20986 #define DDR_PHY_DX8SL4DXCTL2_IOLB_MASK 0x00008000U
20989 * Reserved. Return zeroes on reads.
20991 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL
20992 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT
20993 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK
20994 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL 0x00141800
20995 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT 13
20996 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK 0x00006000U
20999 * Low Power Wakeup Threshold
21001 #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL
21002 #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT
21003 #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK
21004 #define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800
21005 #define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT 9
21006 #define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U
21009 * Read Data Bus Inversion Enable
21011 #undef DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL
21012 #undef DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT
21013 #undef DDR_PHY_DX8SL4DXCTL2_RDBI_MASK
21014 #define DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL 0x00141800
21015 #define DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT 8
21016 #define DDR_PHY_DX8SL4DXCTL2_RDBI_MASK 0x00000100U
21019 * Write Data Bus Inversion Enable
21021 #undef DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL
21022 #undef DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT
21023 #undef DDR_PHY_DX8SL4DXCTL2_WDBI_MASK
21024 #define DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL 0x00141800
21025 #define DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT 7
21026 #define DDR_PHY_DX8SL4DXCTL2_WDBI_MASK 0x00000080U
21029 * PUB Read FIFO Bypass
21031 #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL
21032 #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT
21033 #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK
21034 #define DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL 0x00141800
21035 #define DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT 6
21036 #define DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK 0x00000040U
21039 * DATX8 Receive FIFO Read Mode
21041 #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL
21042 #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT
21043 #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK
21044 #define DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL 0x00141800
21045 #define DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT 4
21046 #define DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK 0x00000030U
21049 * Disables the Read FIFO Reset
21051 #undef DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL
21052 #undef DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT
21053 #undef DDR_PHY_DX8SL4DXCTL2_DISRST_MASK
21054 #define DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL 0x00141800
21055 #define DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT 3
21056 #define DDR_PHY_DX8SL4DXCTL2_DISRST_MASK 0x00000008U
21059 * Read DQS Gate I/O Loopback
21061 #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL
21062 #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT
21063 #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK
21064 #define DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL 0x00141800
21065 #define DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT 1
21066 #define DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK 0x00000006U
21069 * Reserved. Return zeroes on reads.
21071 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL
21072 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT
21073 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK
21074 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL 0x00141800
21075 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT 0
21076 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK 0x00000001U
21079 * Reserved. Return zeroes on reads.
21081 #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL
21082 #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT
21083 #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK
21084 #define DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL 0x00000000
21085 #define DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT 31
21086 #define DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK 0x80000000U
21089 * PVREF_DAC REFSEL range select
21091 #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL
21092 #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT
21093 #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK
21094 #define DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL 0x00000000
21095 #define DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT 28
21096 #define DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK 0x70000000U
21099 * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
21101 #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL
21102 #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT
21103 #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK
21104 #define DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL 0x00000000
21105 #define DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT 25
21106 #define DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK 0x0E000000U
21111 #undef DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL
21112 #undef DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT
21113 #undef DDR_PHY_DX8SL4IOCR_DXIOM_MASK
21114 #define DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL 0x00000000
21115 #define DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT 22
21116 #define DDR_PHY_DX8SL4IOCR_DXIOM_MASK 0x01C00000U
21119 * DX IO Transmitter Mode
21121 #undef DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL
21122 #undef DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT
21123 #undef DDR_PHY_DX8SL4IOCR_DXTXM_MASK
21124 #define DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL 0x00000000
21125 #define DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT 11
21126 #define DDR_PHY_DX8SL4IOCR_DXTXM_MASK 0x003FF800U
21129 * DX IO Receiver Mode
21131 #undef DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL
21132 #undef DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT
21133 #undef DDR_PHY_DX8SL4IOCR_DXRXM_MASK
21134 #define DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL 0x00000000
21135 #define DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT 0
21136 #define DDR_PHY_DX8SL4IOCR_DXRXM_MASK 0x000007FFU
21141 #undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_DEFVAL
21142 #undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_SHIFT
21143 #undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_MASK
21144 #define DDR_PHY_DX8SLBPLLCR0_PLLBYP_DEFVAL 0x00000000
21145 #define DDR_PHY_DX8SLBPLLCR0_PLLBYP_SHIFT 31
21146 #define DDR_PHY_DX8SLBPLLCR0_PLLBYP_MASK 0x80000000U
21151 #undef DDR_PHY_DX8SLBPLLCR0_PLLRST_DEFVAL
21152 #undef DDR_PHY_DX8SLBPLLCR0_PLLRST_SHIFT
21153 #undef DDR_PHY_DX8SLBPLLCR0_PLLRST_MASK
21154 #define DDR_PHY_DX8SLBPLLCR0_PLLRST_DEFVAL 0x00000000
21155 #define DDR_PHY_DX8SLBPLLCR0_PLLRST_SHIFT 30
21156 #define DDR_PHY_DX8SLBPLLCR0_PLLRST_MASK 0x40000000U
21161 #undef DDR_PHY_DX8SLBPLLCR0_PLLPD_DEFVAL
21162 #undef DDR_PHY_DX8SLBPLLCR0_PLLPD_SHIFT
21163 #undef DDR_PHY_DX8SLBPLLCR0_PLLPD_MASK
21164 #define DDR_PHY_DX8SLBPLLCR0_PLLPD_DEFVAL 0x00000000
21165 #define DDR_PHY_DX8SLBPLLCR0_PLLPD_SHIFT 29
21166 #define DDR_PHY_DX8SLBPLLCR0_PLLPD_MASK 0x20000000U
21169 * Reference Stop Mode
21171 #undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_DEFVAL
21172 #undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_SHIFT
21173 #undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_MASK
21174 #define DDR_PHY_DX8SLBPLLCR0_RSTOPM_DEFVAL 0x00000000
21175 #define DDR_PHY_DX8SLBPLLCR0_RSTOPM_SHIFT 28
21176 #define DDR_PHY_DX8SLBPLLCR0_RSTOPM_MASK 0x10000000U
21179 * PLL Frequency Select
21181 #undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_DEFVAL
21182 #undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_SHIFT
21183 #undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_MASK
21184 #define DDR_PHY_DX8SLBPLLCR0_FRQSEL_DEFVAL 0x00000000
21185 #define DDR_PHY_DX8SLBPLLCR0_FRQSEL_SHIFT 24
21186 #define DDR_PHY_DX8SLBPLLCR0_FRQSEL_MASK 0x0F000000U
21191 #undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_DEFVAL
21192 #undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_SHIFT
21193 #undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_MASK
21194 #define DDR_PHY_DX8SLBPLLCR0_RLOCKM_DEFVAL 0x00000000
21195 #define DDR_PHY_DX8SLBPLLCR0_RLOCKM_SHIFT 23
21196 #define DDR_PHY_DX8SLBPLLCR0_RLOCKM_MASK 0x00800000U
21199 * Charge Pump Proportional Current Control
21201 #undef DDR_PHY_DX8SLBPLLCR0_CPPC_DEFVAL
21202 #undef DDR_PHY_DX8SLBPLLCR0_CPPC_SHIFT
21203 #undef DDR_PHY_DX8SLBPLLCR0_CPPC_MASK
21204 #define DDR_PHY_DX8SLBPLLCR0_CPPC_DEFVAL 0x00000000
21205 #define DDR_PHY_DX8SLBPLLCR0_CPPC_SHIFT 17
21206 #define DDR_PHY_DX8SLBPLLCR0_CPPC_MASK 0x007E0000U
21209 * Charge Pump Integrating Current Control
21211 #undef DDR_PHY_DX8SLBPLLCR0_CPIC_DEFVAL
21212 #undef DDR_PHY_DX8SLBPLLCR0_CPIC_SHIFT
21213 #undef DDR_PHY_DX8SLBPLLCR0_CPIC_MASK
21214 #define DDR_PHY_DX8SLBPLLCR0_CPIC_DEFVAL 0x00000000
21215 #define DDR_PHY_DX8SLBPLLCR0_CPIC_SHIFT 13
21216 #define DDR_PHY_DX8SLBPLLCR0_CPIC_MASK 0x0001E000U
21221 #undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_DEFVAL
21222 #undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_SHIFT
21223 #undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_MASK
21224 #define DDR_PHY_DX8SLBPLLCR0_GSHIFT_DEFVAL 0x00000000
21225 #define DDR_PHY_DX8SLBPLLCR0_GSHIFT_SHIFT 12
21226 #define DDR_PHY_DX8SLBPLLCR0_GSHIFT_MASK 0x00001000U
21229 * Reserved. Return zeroes on reads.
21231 #undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_DEFVAL
21232 #undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_SHIFT
21233 #undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_MASK
21234 #define DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_DEFVAL 0x00000000
21235 #define DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_SHIFT 9
21236 #define DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_MASK 0x00000E00U
21239 * Analog Test Enable (ATOEN)
21241 #undef DDR_PHY_DX8SLBPLLCR0_ATOEN_DEFVAL
21242 #undef DDR_PHY_DX8SLBPLLCR0_ATOEN_SHIFT
21243 #undef DDR_PHY_DX8SLBPLLCR0_ATOEN_MASK
21244 #define DDR_PHY_DX8SLBPLLCR0_ATOEN_DEFVAL 0x00000000
21245 #define DDR_PHY_DX8SLBPLLCR0_ATOEN_SHIFT 8
21246 #define DDR_PHY_DX8SLBPLLCR0_ATOEN_MASK 0x00000100U
21249 * Analog Test Control
21251 #undef DDR_PHY_DX8SLBPLLCR0_ATC_DEFVAL
21252 #undef DDR_PHY_DX8SLBPLLCR0_ATC_SHIFT
21253 #undef DDR_PHY_DX8SLBPLLCR0_ATC_MASK
21254 #define DDR_PHY_DX8SLBPLLCR0_ATC_DEFVAL 0x00000000
21255 #define DDR_PHY_DX8SLBPLLCR0_ATC_SHIFT 4
21256 #define DDR_PHY_DX8SLBPLLCR0_ATC_MASK 0x000000F0U
21259 * Digital Test Control
21261 #undef DDR_PHY_DX8SLBPLLCR0_DTC_DEFVAL
21262 #undef DDR_PHY_DX8SLBPLLCR0_DTC_SHIFT
21263 #undef DDR_PHY_DX8SLBPLLCR0_DTC_MASK
21264 #define DDR_PHY_DX8SLBPLLCR0_DTC_DEFVAL 0x00000000
21265 #define DDR_PHY_DX8SLBPLLCR0_DTC_SHIFT 0
21266 #define DDR_PHY_DX8SLBPLLCR0_DTC_MASK 0x0000000FU
21269 * Reserved. Return zeroes on reads.
21271 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL
21272 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT
21273 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK
21274 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL 0x00000000
21275 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT 25
21276 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK 0xFE000000U
21279 * Read Path Rise-to-Rise Mode
21281 #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL
21282 #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT
21283 #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK
21284 #define DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL 0x00000000
21285 #define DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT 24
21286 #define DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK 0x01000000U
21289 * Reserved. Return zeroes on reads.
21291 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL
21292 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT
21293 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK
21294 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL 0x00000000
21295 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT 22
21296 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK 0x00C00000U
21299 * Write Path Rise-to-Rise Mode
21301 #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL
21302 #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT
21303 #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK
21304 #define DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL 0x00000000
21305 #define DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT 21
21306 #define DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK 0x00200000U
21309 * DQS Gate Extension
21311 #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL
21312 #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT
21313 #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK
21314 #define DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL 0x00000000
21315 #define DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT 19
21316 #define DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK 0x00180000U
21319 * Low Power PLL Power Down
21321 #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL
21322 #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT
21323 #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK
21324 #define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL 0x00000000
21325 #define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT 18
21326 #define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK 0x00040000U
21329 * Low Power I/O Power Down
21331 #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL
21332 #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT
21333 #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK
21334 #define DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL 0x00000000
21335 #define DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT 17
21336 #define DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK 0x00020000U
21339 * Reserved. Return zeroes on reads.
21341 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL
21342 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT
21343 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK
21344 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL 0x00000000
21345 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT 15
21346 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK 0x00018000U
21349 * QS Counter Enable
21351 #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL
21352 #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT
21353 #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK
21354 #define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL 0x00000000
21355 #define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT 14
21356 #define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK 0x00004000U
21359 * Unused DQ I/O Mode
21361 #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL
21362 #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT
21363 #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK
21364 #define DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL 0x00000000
21365 #define DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT 13
21366 #define DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK 0x00002000U
21369 * Reserved. Return zeroes on reads.
21371 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL
21372 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT
21373 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK
21374 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL 0x00000000
21375 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT 10
21376 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK 0x00001C00U
21381 #undef DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL
21382 #undef DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT
21383 #undef DDR_PHY_DX8SLBDQSCTL_DXSR_MASK
21384 #define DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL 0x00000000
21385 #define DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT 8
21386 #define DDR_PHY_DX8SLBDQSCTL_DXSR_MASK 0x00000300U
21391 #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL
21392 #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT
21393 #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK
21394 #define DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL 0x00000000
21395 #define DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT 4
21396 #define DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK 0x000000F0U
21401 #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL
21402 #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT
21403 #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK
21404 #define DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL 0x00000000
21405 #define DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT 0
21406 #define DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK 0x0000000FU
21407 #undef IOU_SLCR_MIO_PIN_0_OFFSET
21408 #define IOU_SLCR_MIO_PIN_0_OFFSET 0XFF180000
21409 #undef IOU_SLCR_MIO_PIN_1_OFFSET
21410 #define IOU_SLCR_MIO_PIN_1_OFFSET 0XFF180004
21411 #undef IOU_SLCR_MIO_PIN_2_OFFSET
21412 #define IOU_SLCR_MIO_PIN_2_OFFSET 0XFF180008
21413 #undef IOU_SLCR_MIO_PIN_3_OFFSET
21414 #define IOU_SLCR_MIO_PIN_3_OFFSET 0XFF18000C
21415 #undef IOU_SLCR_MIO_PIN_4_OFFSET
21416 #define IOU_SLCR_MIO_PIN_4_OFFSET 0XFF180010
21417 #undef IOU_SLCR_MIO_PIN_5_OFFSET
21418 #define IOU_SLCR_MIO_PIN_5_OFFSET 0XFF180014
21419 #undef IOU_SLCR_MIO_PIN_6_OFFSET
21420 #define IOU_SLCR_MIO_PIN_6_OFFSET 0XFF180018
21421 #undef IOU_SLCR_MIO_PIN_7_OFFSET
21422 #define IOU_SLCR_MIO_PIN_7_OFFSET 0XFF18001C
21423 #undef IOU_SLCR_MIO_PIN_8_OFFSET
21424 #define IOU_SLCR_MIO_PIN_8_OFFSET 0XFF180020
21425 #undef IOU_SLCR_MIO_PIN_9_OFFSET
21426 #define IOU_SLCR_MIO_PIN_9_OFFSET 0XFF180024
21427 #undef IOU_SLCR_MIO_PIN_10_OFFSET
21428 #define IOU_SLCR_MIO_PIN_10_OFFSET 0XFF180028
21429 #undef IOU_SLCR_MIO_PIN_11_OFFSET
21430 #define IOU_SLCR_MIO_PIN_11_OFFSET 0XFF18002C
21431 #undef IOU_SLCR_MIO_PIN_12_OFFSET
21432 #define IOU_SLCR_MIO_PIN_12_OFFSET 0XFF180030
21433 #undef IOU_SLCR_MIO_PIN_13_OFFSET
21434 #define IOU_SLCR_MIO_PIN_13_OFFSET 0XFF180034
21435 #undef IOU_SLCR_MIO_PIN_14_OFFSET
21436 #define IOU_SLCR_MIO_PIN_14_OFFSET 0XFF180038
21437 #undef IOU_SLCR_MIO_PIN_15_OFFSET
21438 #define IOU_SLCR_MIO_PIN_15_OFFSET 0XFF18003C
21439 #undef IOU_SLCR_MIO_PIN_16_OFFSET
21440 #define IOU_SLCR_MIO_PIN_16_OFFSET 0XFF180040
21441 #undef IOU_SLCR_MIO_PIN_17_OFFSET
21442 #define IOU_SLCR_MIO_PIN_17_OFFSET 0XFF180044
21443 #undef IOU_SLCR_MIO_PIN_18_OFFSET
21444 #define IOU_SLCR_MIO_PIN_18_OFFSET 0XFF180048
21445 #undef IOU_SLCR_MIO_PIN_19_OFFSET
21446 #define IOU_SLCR_MIO_PIN_19_OFFSET 0XFF18004C
21447 #undef IOU_SLCR_MIO_PIN_20_OFFSET
21448 #define IOU_SLCR_MIO_PIN_20_OFFSET 0XFF180050
21449 #undef IOU_SLCR_MIO_PIN_21_OFFSET
21450 #define IOU_SLCR_MIO_PIN_21_OFFSET 0XFF180054
21451 #undef IOU_SLCR_MIO_PIN_22_OFFSET
21452 #define IOU_SLCR_MIO_PIN_22_OFFSET 0XFF180058
21453 #undef IOU_SLCR_MIO_PIN_23_OFFSET
21454 #define IOU_SLCR_MIO_PIN_23_OFFSET 0XFF18005C
21455 #undef IOU_SLCR_MIO_PIN_24_OFFSET
21456 #define IOU_SLCR_MIO_PIN_24_OFFSET 0XFF180060
21457 #undef IOU_SLCR_MIO_PIN_25_OFFSET
21458 #define IOU_SLCR_MIO_PIN_25_OFFSET 0XFF180064
21459 #undef IOU_SLCR_MIO_PIN_26_OFFSET
21460 #define IOU_SLCR_MIO_PIN_26_OFFSET 0XFF180068
21461 #undef IOU_SLCR_MIO_PIN_27_OFFSET
21462 #define IOU_SLCR_MIO_PIN_27_OFFSET 0XFF18006C
21463 #undef IOU_SLCR_MIO_PIN_28_OFFSET
21464 #define IOU_SLCR_MIO_PIN_28_OFFSET 0XFF180070
21465 #undef IOU_SLCR_MIO_PIN_29_OFFSET
21466 #define IOU_SLCR_MIO_PIN_29_OFFSET 0XFF180074
21467 #undef IOU_SLCR_MIO_PIN_30_OFFSET
21468 #define IOU_SLCR_MIO_PIN_30_OFFSET 0XFF180078
21469 #undef IOU_SLCR_MIO_PIN_31_OFFSET
21470 #define IOU_SLCR_MIO_PIN_31_OFFSET 0XFF18007C
21471 #undef IOU_SLCR_MIO_PIN_32_OFFSET
21472 #define IOU_SLCR_MIO_PIN_32_OFFSET 0XFF180080
21473 #undef IOU_SLCR_MIO_PIN_33_OFFSET
21474 #define IOU_SLCR_MIO_PIN_33_OFFSET 0XFF180084
21475 #undef IOU_SLCR_MIO_PIN_34_OFFSET
21476 #define IOU_SLCR_MIO_PIN_34_OFFSET 0XFF180088
21477 #undef IOU_SLCR_MIO_PIN_35_OFFSET
21478 #define IOU_SLCR_MIO_PIN_35_OFFSET 0XFF18008C
21479 #undef IOU_SLCR_MIO_PIN_36_OFFSET
21480 #define IOU_SLCR_MIO_PIN_36_OFFSET 0XFF180090
21481 #undef IOU_SLCR_MIO_PIN_37_OFFSET
21482 #define IOU_SLCR_MIO_PIN_37_OFFSET 0XFF180094
21483 #undef IOU_SLCR_MIO_PIN_38_OFFSET
21484 #define IOU_SLCR_MIO_PIN_38_OFFSET 0XFF180098
21485 #undef IOU_SLCR_MIO_PIN_39_OFFSET
21486 #define IOU_SLCR_MIO_PIN_39_OFFSET 0XFF18009C
21487 #undef IOU_SLCR_MIO_PIN_40_OFFSET
21488 #define IOU_SLCR_MIO_PIN_40_OFFSET 0XFF1800A0
21489 #undef IOU_SLCR_MIO_PIN_41_OFFSET
21490 #define IOU_SLCR_MIO_PIN_41_OFFSET 0XFF1800A4
21491 #undef IOU_SLCR_MIO_PIN_42_OFFSET
21492 #define IOU_SLCR_MIO_PIN_42_OFFSET 0XFF1800A8
21493 #undef IOU_SLCR_MIO_PIN_43_OFFSET
21494 #define IOU_SLCR_MIO_PIN_43_OFFSET 0XFF1800AC
21495 #undef IOU_SLCR_MIO_PIN_44_OFFSET
21496 #define IOU_SLCR_MIO_PIN_44_OFFSET 0XFF1800B0
21497 #undef IOU_SLCR_MIO_PIN_45_OFFSET
21498 #define IOU_SLCR_MIO_PIN_45_OFFSET 0XFF1800B4
21499 #undef IOU_SLCR_MIO_PIN_46_OFFSET
21500 #define IOU_SLCR_MIO_PIN_46_OFFSET 0XFF1800B8
21501 #undef IOU_SLCR_MIO_PIN_47_OFFSET
21502 #define IOU_SLCR_MIO_PIN_47_OFFSET 0XFF1800BC
21503 #undef IOU_SLCR_MIO_PIN_48_OFFSET
21504 #define IOU_SLCR_MIO_PIN_48_OFFSET 0XFF1800C0
21505 #undef IOU_SLCR_MIO_PIN_49_OFFSET
21506 #define IOU_SLCR_MIO_PIN_49_OFFSET 0XFF1800C4
21507 #undef IOU_SLCR_MIO_PIN_50_OFFSET
21508 #define IOU_SLCR_MIO_PIN_50_OFFSET 0XFF1800C8
21509 #undef IOU_SLCR_MIO_PIN_51_OFFSET
21510 #define IOU_SLCR_MIO_PIN_51_OFFSET 0XFF1800CC
21511 #undef IOU_SLCR_MIO_PIN_52_OFFSET
21512 #define IOU_SLCR_MIO_PIN_52_OFFSET 0XFF1800D0
21513 #undef IOU_SLCR_MIO_PIN_53_OFFSET
21514 #define IOU_SLCR_MIO_PIN_53_OFFSET 0XFF1800D4
21515 #undef IOU_SLCR_MIO_PIN_54_OFFSET
21516 #define IOU_SLCR_MIO_PIN_54_OFFSET 0XFF1800D8
21517 #undef IOU_SLCR_MIO_PIN_55_OFFSET
21518 #define IOU_SLCR_MIO_PIN_55_OFFSET 0XFF1800DC
21519 #undef IOU_SLCR_MIO_PIN_56_OFFSET
21520 #define IOU_SLCR_MIO_PIN_56_OFFSET 0XFF1800E0
21521 #undef IOU_SLCR_MIO_PIN_57_OFFSET
21522 #define IOU_SLCR_MIO_PIN_57_OFFSET 0XFF1800E4
21523 #undef IOU_SLCR_MIO_PIN_58_OFFSET
21524 #define IOU_SLCR_MIO_PIN_58_OFFSET 0XFF1800E8
21525 #undef IOU_SLCR_MIO_PIN_59_OFFSET
21526 #define IOU_SLCR_MIO_PIN_59_OFFSET 0XFF1800EC
21527 #undef IOU_SLCR_MIO_PIN_60_OFFSET
21528 #define IOU_SLCR_MIO_PIN_60_OFFSET 0XFF1800F0
21529 #undef IOU_SLCR_MIO_PIN_61_OFFSET
21530 #define IOU_SLCR_MIO_PIN_61_OFFSET 0XFF1800F4
21531 #undef IOU_SLCR_MIO_PIN_62_OFFSET
21532 #define IOU_SLCR_MIO_PIN_62_OFFSET 0XFF1800F8
21533 #undef IOU_SLCR_MIO_PIN_63_OFFSET
21534 #define IOU_SLCR_MIO_PIN_63_OFFSET 0XFF1800FC
21535 #undef IOU_SLCR_MIO_PIN_64_OFFSET
21536 #define IOU_SLCR_MIO_PIN_64_OFFSET 0XFF180100
21537 #undef IOU_SLCR_MIO_PIN_65_OFFSET
21538 #define IOU_SLCR_MIO_PIN_65_OFFSET 0XFF180104
21539 #undef IOU_SLCR_MIO_PIN_66_OFFSET
21540 #define IOU_SLCR_MIO_PIN_66_OFFSET 0XFF180108
21541 #undef IOU_SLCR_MIO_PIN_67_OFFSET
21542 #define IOU_SLCR_MIO_PIN_67_OFFSET 0XFF18010C
21543 #undef IOU_SLCR_MIO_PIN_68_OFFSET
21544 #define IOU_SLCR_MIO_PIN_68_OFFSET 0XFF180110
21545 #undef IOU_SLCR_MIO_PIN_69_OFFSET
21546 #define IOU_SLCR_MIO_PIN_69_OFFSET 0XFF180114
21547 #undef IOU_SLCR_MIO_PIN_70_OFFSET
21548 #define IOU_SLCR_MIO_PIN_70_OFFSET 0XFF180118
21549 #undef IOU_SLCR_MIO_PIN_71_OFFSET
21550 #define IOU_SLCR_MIO_PIN_71_OFFSET 0XFF18011C
21551 #undef IOU_SLCR_MIO_PIN_72_OFFSET
21552 #define IOU_SLCR_MIO_PIN_72_OFFSET 0XFF180120
21553 #undef IOU_SLCR_MIO_PIN_73_OFFSET
21554 #define IOU_SLCR_MIO_PIN_73_OFFSET 0XFF180124
21555 #undef IOU_SLCR_MIO_PIN_74_OFFSET
21556 #define IOU_SLCR_MIO_PIN_74_OFFSET 0XFF180128
21557 #undef IOU_SLCR_MIO_PIN_75_OFFSET
21558 #define IOU_SLCR_MIO_PIN_75_OFFSET 0XFF18012C
21559 #undef IOU_SLCR_MIO_PIN_76_OFFSET
21560 #define IOU_SLCR_MIO_PIN_76_OFFSET 0XFF180130
21561 #undef IOU_SLCR_MIO_PIN_77_OFFSET
21562 #define IOU_SLCR_MIO_PIN_77_OFFSET 0XFF180134
21563 #undef IOU_SLCR_MIO_MST_TRI0_OFFSET
21564 #define IOU_SLCR_MIO_MST_TRI0_OFFSET 0XFF180204
21565 #undef IOU_SLCR_MIO_MST_TRI1_OFFSET
21566 #define IOU_SLCR_MIO_MST_TRI1_OFFSET 0XFF180208
21567 #undef IOU_SLCR_MIO_MST_TRI2_OFFSET
21568 #define IOU_SLCR_MIO_MST_TRI2_OFFSET 0XFF18020C
21569 #undef IOU_SLCR_BANK0_CTRL0_OFFSET
21570 #define IOU_SLCR_BANK0_CTRL0_OFFSET 0XFF180138
21571 #undef IOU_SLCR_BANK0_CTRL1_OFFSET
21572 #define IOU_SLCR_BANK0_CTRL1_OFFSET 0XFF18013C
21573 #undef IOU_SLCR_BANK0_CTRL3_OFFSET
21574 #define IOU_SLCR_BANK0_CTRL3_OFFSET 0XFF180140
21575 #undef IOU_SLCR_BANK0_CTRL4_OFFSET
21576 #define IOU_SLCR_BANK0_CTRL4_OFFSET 0XFF180144
21577 #undef IOU_SLCR_BANK0_CTRL5_OFFSET
21578 #define IOU_SLCR_BANK0_CTRL5_OFFSET 0XFF180148
21579 #undef IOU_SLCR_BANK0_CTRL6_OFFSET
21580 #define IOU_SLCR_BANK0_CTRL6_OFFSET 0XFF18014C
21581 #undef IOU_SLCR_BANK1_CTRL0_OFFSET
21582 #define IOU_SLCR_BANK1_CTRL0_OFFSET 0XFF180154
21583 #undef IOU_SLCR_BANK1_CTRL1_OFFSET
21584 #define IOU_SLCR_BANK1_CTRL1_OFFSET 0XFF180158
21585 #undef IOU_SLCR_BANK1_CTRL3_OFFSET
21586 #define IOU_SLCR_BANK1_CTRL3_OFFSET 0XFF18015C
21587 #undef IOU_SLCR_BANK1_CTRL4_OFFSET
21588 #define IOU_SLCR_BANK1_CTRL4_OFFSET 0XFF180160
21589 #undef IOU_SLCR_BANK1_CTRL5_OFFSET
21590 #define IOU_SLCR_BANK1_CTRL5_OFFSET 0XFF180164
21591 #undef IOU_SLCR_BANK1_CTRL6_OFFSET
21592 #define IOU_SLCR_BANK1_CTRL6_OFFSET 0XFF180168
21593 #undef IOU_SLCR_BANK2_CTRL0_OFFSET
21594 #define IOU_SLCR_BANK2_CTRL0_OFFSET 0XFF180170
21595 #undef IOU_SLCR_BANK2_CTRL1_OFFSET
21596 #define IOU_SLCR_BANK2_CTRL1_OFFSET 0XFF180174
21597 #undef IOU_SLCR_BANK2_CTRL3_OFFSET
21598 #define IOU_SLCR_BANK2_CTRL3_OFFSET 0XFF180178
21599 #undef IOU_SLCR_BANK2_CTRL4_OFFSET
21600 #define IOU_SLCR_BANK2_CTRL4_OFFSET 0XFF18017C
21601 #undef IOU_SLCR_BANK2_CTRL5_OFFSET
21602 #define IOU_SLCR_BANK2_CTRL5_OFFSET 0XFF180180
21603 #undef IOU_SLCR_BANK2_CTRL6_OFFSET
21604 #define IOU_SLCR_BANK2_CTRL6_OFFSET 0XFF180184
21605 #undef IOU_SLCR_MIO_LOOPBACK_OFFSET
21606 #define IOU_SLCR_MIO_LOOPBACK_OFFSET 0XFF180200
21609 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out-
21612 #undef IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL
21613 #undef IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT
21614 #undef IOU_SLCR_MIO_PIN_0_L0_SEL_MASK
21615 #define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 0x00000000
21616 #define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 1
21617 #define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK 0x00000002U
21620 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
21622 #undef IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL
21623 #undef IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT
21624 #undef IOU_SLCR_MIO_PIN_0_L1_SEL_MASK
21625 #define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 0x00000000
21626 #define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 2
21627 #define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK 0x00000004U
21630 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
21631 * , test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0
21632 * ]- (Test Scan Port) 3= Not Used
21634 #undef IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL
21635 #undef IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT
21636 #undef IOU_SLCR_MIO_PIN_0_L2_SEL_MASK
21637 #define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 0x00000000
21638 #define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 3
21639 #define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK 0x00000018U
21642 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= g
21643 * pio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy
21644 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
21645 * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
21646 * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc
21647 * lk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Out
21648 * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c
21649 * lk- (Trace Port Clock)
21651 #undef IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL
21652 #undef IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT
21653 #undef IOU_SLCR_MIO_PIN_0_L3_SEL_MASK
21654 #define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 0x00000000
21655 #define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 5
21656 #define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK 0x000000E0U
21659 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (Q
21660 * SPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus)
21662 #undef IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL
21663 #undef IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT
21664 #undef IOU_SLCR_MIO_PIN_1_L0_SEL_MASK
21665 #define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 0x00000000
21666 #define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 1
21667 #define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK 0x00000002U
21670 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
21672 #undef IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL
21673 #undef IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT
21674 #undef IOU_SLCR_MIO_PIN_1_L1_SEL_MASK
21675 #define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 0x00000000
21676 #define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 2
21677 #define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK 0x00000004U
21680 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
21681 * , test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1
21682 * ]- (Test Scan Port) 3= Not Used
21684 #undef IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL
21685 #undef IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT
21686 #undef IOU_SLCR_MIO_PIN_1_L2_SEL_MASK
21687 #define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 0x00000000
21688 #define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 3
21689 #define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK 0x00000018U
21692 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= g
21693 * pio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_
21694 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
21695 * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
21696 * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Ou
21697 * tput, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART
21698 * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
21701 #undef IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL
21702 #undef IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT
21703 #undef IOU_SLCR_MIO_PIN_1_L3_SEL_MASK
21704 #define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 0x00000000
21705 #define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 5
21706 #define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK 0x000000E0U
21709 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI
21710 * Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)
21712 #undef IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL
21713 #undef IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT
21714 #undef IOU_SLCR_MIO_PIN_2_L0_SEL_MASK
21715 #define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 0x00000000
21716 #define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 1
21717 #define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK 0x00000002U
21720 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
21722 #undef IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL
21723 #undef IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT
21724 #undef IOU_SLCR_MIO_PIN_2_L1_SEL_MASK
21725 #define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 0x00000000
21726 #define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 2
21727 #define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK 0x00000004U
21730 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
21731 * , test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2
21732 * ]- (Test Scan Port) 3= Not Used
21734 #undef IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL
21735 #undef IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT
21736 #undef IOU_SLCR_MIO_PIN_2_L2_SEL_MASK
21737 #define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 0x00000000
21738 #define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 3
21739 #define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK 0x00000018U
21742 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= g
21743 * pio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_
21744 * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
21745 * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG
21746 * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, I
21747 * nput, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se
21748 * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
21750 #undef IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL
21751 #undef IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT
21752 #undef IOU_SLCR_MIO_PIN_2_L3_SEL_MASK
21753 #define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 0x00000000
21754 #define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 5
21755 #define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK 0x000000E0U
21758 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI
21759 * Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)
21761 #undef IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL
21762 #undef IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT
21763 #undef IOU_SLCR_MIO_PIN_3_L0_SEL_MASK
21764 #define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 0x00000000
21765 #define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 1
21766 #define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK 0x00000002U
21769 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
21771 #undef IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL
21772 #undef IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT
21773 #undef IOU_SLCR_MIO_PIN_3_L1_SEL_MASK
21774 #define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 0x00000000
21775 #define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 2
21776 #define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK 0x00000004U
21779 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
21780 * , test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3
21781 * ]- (Test Scan Port) 3= Not Used
21783 #undef IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL
21784 #undef IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT
21785 #undef IOU_SLCR_MIO_PIN_3_L2_SEL_MASK
21786 #define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 0x00000000
21787 #define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 3
21788 #define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK 0x00000018U
21791 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= g
21792 * pio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy
21793 * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
21794 * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
21795 * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output
21796 * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out-
21797 * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
21798 * output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
21800 #undef IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL
21801 #undef IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT
21802 #undef IOU_SLCR_MIO_PIN_3_L3_SEL_MASK
21803 #define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 0x00000000
21804 #define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 5
21805 #define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK 0x000000E0U
21808 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (
21809 * QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus)
21811 #undef IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL
21812 #undef IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT
21813 #undef IOU_SLCR_MIO_PIN_4_L0_SEL_MASK
21814 #define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 0x00000000
21815 #define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 1
21816 #define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK 0x00000002U
21819 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
21821 #undef IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL
21822 #undef IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT
21823 #undef IOU_SLCR_MIO_PIN_4_L1_SEL_MASK
21824 #define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 0x00000000
21825 #define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 2
21826 #define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK 0x00000004U
21829 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
21830 * , test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4
21831 * ]- (Test Scan Port) 3= Not Used
21833 #undef IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL
21834 #undef IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT
21835 #undef IOU_SLCR_MIO_PIN_4_L2_SEL_MASK
21836 #define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 0x00000000
21837 #define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 3
21838 #define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK 0x00000018U
21841 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= g
21842 * pio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy
21843 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
21844 * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa
21845 * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi
21846 * 0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cloc
21847 * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O
21848 * utput, tracedq[2]- (Trace Port Databus)
21850 #undef IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL
21851 #undef IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT
21852 #undef IOU_SLCR_MIO_PIN_4_L3_SEL_MASK
21853 #define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 0x00000000
21854 #define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 5
21855 #define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK 0x000000E0U
21858 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out-
21859 * (QSPI Slave Select)
21861 #undef IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL
21862 #undef IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT
21863 #undef IOU_SLCR_MIO_PIN_5_L0_SEL_MASK
21864 #define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 0x00000000
21865 #define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 1
21866 #define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK 0x00000002U
21869 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
21871 #undef IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL
21872 #undef IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT
21873 #undef IOU_SLCR_MIO_PIN_5_L1_SEL_MASK
21874 #define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 0x00000000
21875 #define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 2
21876 #define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK 0x00000004U
21879 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
21880 * , test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5
21881 * ]- (Test Scan Port) 3= Not Used
21883 #undef IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL
21884 #undef IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT
21885 #undef IOU_SLCR_MIO_PIN_5_L2_SEL_MASK
21886 #define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 0x00000000
21887 #define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 3
21888 #define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK 0x00000018U
21891 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= g
21892 * pio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_
21893 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
21894 * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W
21895 * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4=
21896 * spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC
21897 * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7=
21898 * trace, Output, tracedq[3]- (Trace Port Databus)
21900 #undef IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL
21901 #undef IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT
21902 #undef IOU_SLCR_MIO_PIN_5_L3_SEL_MASK
21903 #define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 0x00000000
21904 #define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 5
21905 #define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK 0x000000E0U
21908 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_l
21909 * pbk- (QSPI Clock to be fed-back)
21911 #undef IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL
21912 #undef IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT
21913 #undef IOU_SLCR_MIO_PIN_6_L0_SEL_MASK
21914 #define IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 0x00000000
21915 #define IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 1
21916 #define IOU_SLCR_MIO_PIN_6_L0_SEL_MASK 0x00000002U
21919 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
21921 #undef IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL
21922 #undef IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT
21923 #undef IOU_SLCR_MIO_PIN_6_L1_SEL_MASK
21924 #define IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 0x00000000
21925 #define IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 2
21926 #define IOU_SLCR_MIO_PIN_6_L1_SEL_MASK 0x00000004U
21929 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
21930 * , test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6
21931 * ]- (Test Scan Port) 3= Not Used
21933 #undef IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL
21934 #undef IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT
21935 #undef IOU_SLCR_MIO_PIN_6_L2_SEL_MASK
21936 #define IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 0x00000000
21937 #define IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 3
21938 #define IOU_SLCR_MIO_PIN_6_L2_SEL_MASK 0x00000018U
21941 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= g
21942 * pio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_
21943 * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
21944 * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat
21945 * ch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= s
21946 * pi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TT
21947 * C Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
21948 * Output, tracedq[4]- (Trace Port Databus)
21950 #undef IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL
21951 #undef IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT
21952 #undef IOU_SLCR_MIO_PIN_6_L3_SEL_MASK
21953 #define IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 0x00000000
21954 #define IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 5
21955 #define IOU_SLCR_MIO_PIN_6_L3_SEL_MASK 0x000000E0U
21958 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_
21959 * upper- (QSPI Slave Select upper)
21961 #undef IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL
21962 #undef IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT
21963 #undef IOU_SLCR_MIO_PIN_7_L0_SEL_MASK
21964 #define IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 0x00000000
21965 #define IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 1
21966 #define IOU_SLCR_MIO_PIN_7_L0_SEL_MASK 0x00000002U
21969 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
21971 #undef IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL
21972 #undef IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT
21973 #undef IOU_SLCR_MIO_PIN_7_L1_SEL_MASK
21974 #define IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 0x00000000
21975 #define IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 2
21976 #define IOU_SLCR_MIO_PIN_7_L1_SEL_MASK 0x00000004U
21979 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
21980 * , test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7
21981 * ]- (Test Scan Port) 3= Not Used
21983 #undef IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL
21984 #undef IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT
21985 #undef IOU_SLCR_MIO_PIN_7_L2_SEL_MASK
21986 #define IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 0x00000000
21987 #define IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 3
21988 #define IOU_SLCR_MIO_PIN_7_L2_SEL_MASK 0x00000018U
21991 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= g
21992 * pio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy
21993 * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
21994 * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (
21995 * Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Ma
21996 * ster Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua
21997 * 0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, t
21998 * racedq[5]- (Trace Port Databus)
22000 #undef IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL
22001 #undef IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT
22002 #undef IOU_SLCR_MIO_PIN_7_L3_SEL_MASK
22003 #define IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 0x00000000
22004 #define IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 5
22005 #define IOU_SLCR_MIO_PIN_7_L3_SEL_MASK 0x000000E0U
22008 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0
22009 * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper D
22012 #undef IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL
22013 #undef IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT
22014 #undef IOU_SLCR_MIO_PIN_8_L0_SEL_MASK
22015 #define IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 0x00000000
22016 #define IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 1
22017 #define IOU_SLCR_MIO_PIN_8_L0_SEL_MASK 0x00000002U
22020 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
22022 #undef IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL
22023 #undef IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT
22024 #undef IOU_SLCR_MIO_PIN_8_L1_SEL_MASK
22025 #define IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 0x00000000
22026 #define IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 2
22027 #define IOU_SLCR_MIO_PIN_8_L1_SEL_MASK 0x00000004U
22030 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
22031 * , test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8
22032 * ]- (Test Scan Port) 3= Not Used
22034 #undef IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL
22035 #undef IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT
22036 #undef IOU_SLCR_MIO_PIN_8_L2_SEL_MASK
22037 #define IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 0x00000000
22038 #define IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 3
22039 #define IOU_SLCR_MIO_PIN_8_L2_SEL_MASK 0x00000018U
22042 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= g
22043 * pio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy
22044 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
22045 * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa
22046 * tch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Maste
22047 * r Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_
22048 * txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tra
22051 #undef IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL
22052 #undef IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT
22053 #undef IOU_SLCR_MIO_PIN_8_L3_SEL_MASK
22054 #define IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 0x00000000
22055 #define IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 5
22056 #define IOU_SLCR_MIO_PIN_8_L3_SEL_MASK 0x000000E0U
22059 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1
22060 * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper D
22063 #undef IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL
22064 #undef IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT
22065 #undef IOU_SLCR_MIO_PIN_9_L0_SEL_MASK
22066 #define IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 0x00000000
22067 #define IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 1
22068 #define IOU_SLCR_MIO_PIN_9_L0_SEL_MASK 0x00000002U
22071 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA
22074 #undef IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL
22075 #undef IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT
22076 #undef IOU_SLCR_MIO_PIN_9_L1_SEL_MASK
22077 #define IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 0x00000000
22078 #define IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 2
22079 #define IOU_SLCR_MIO_PIN_9_L1_SEL_MASK 0x00000004U
22082 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
22083 * , test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9
22084 * ]- (Test Scan Port) 3= Not Used
22086 #undef IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL
22087 #undef IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT
22088 #undef IOU_SLCR_MIO_PIN_9_L2_SEL_MASK
22089 #define IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 0x00000000
22090 #define IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 3
22091 #define IOU_SLCR_MIO_PIN_9_L2_SEL_MASK 0x00000018U
22094 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= g
22095 * pio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_
22096 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
22097 * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W
22098 * atch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master S
22099 * elects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3,
22100 * Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UA
22101 * RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Data
22104 #undef IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL
22105 #undef IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT
22106 #undef IOU_SLCR_MIO_PIN_9_L3_SEL_MASK
22107 #define IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 0x00000000
22108 #define IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 5
22109 #define IOU_SLCR_MIO_PIN_9_L3_SEL_MASK 0x000000E0U
22112 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2
22113 * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper D
22116 #undef IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL
22117 #undef IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT
22118 #undef IOU_SLCR_MIO_PIN_10_L0_SEL_MASK
22119 #define IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 0x00000000
22120 #define IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 1
22121 #define IOU_SLCR_MIO_PIN_10_L0_SEL_MASK 0x00000002U
22124 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N
22127 #undef IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL
22128 #undef IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT
22129 #undef IOU_SLCR_MIO_PIN_10_L1_SEL_MASK
22130 #define IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 0x00000000
22131 #define IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 2
22132 #define IOU_SLCR_MIO_PIN_10_L1_SEL_MASK 0x00000004U
22135 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
22136 * , test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[
22137 * 10]- (Test Scan Port) 3= Not Used
22139 #undef IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL
22140 #undef IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT
22141 #undef IOU_SLCR_MIO_PIN_10_L2_SEL_MASK
22142 #define IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 0x00000000
22143 #define IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 3
22144 #define IOU_SLCR_MIO_PIN_10_L2_SEL_MASK 0x00000018U
22147 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0=
22148 * gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_ph
22149 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
22150 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
22151 * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp
22152 * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo
22153 * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu
22154 * t, tracedq[8]- (Trace Port Databus)
22156 #undef IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL
22157 #undef IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT
22158 #undef IOU_SLCR_MIO_PIN_10_L3_SEL_MASK
22159 #define IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 0x00000000
22160 #define IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 5
22161 #define IOU_SLCR_MIO_PIN_10_L3_SEL_MASK 0x000000E0U
22164 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3
22165 * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper D
22168 #undef IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL
22169 #undef IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT
22170 #undef IOU_SLCR_MIO_PIN_11_L0_SEL_MASK
22171 #define IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 0x00000000
22172 #define IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 1
22173 #define IOU_SLCR_MIO_PIN_11_L0_SEL_MASK 0x00000002U
22176 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N
22179 #undef IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL
22180 #undef IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT
22181 #undef IOU_SLCR_MIO_PIN_11_L1_SEL_MASK
22182 #define IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 0x00000000
22183 #define IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 2
22184 #define IOU_SLCR_MIO_PIN_11_L1_SEL_MASK 0x00000004U
22187 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
22188 * , test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[
22189 * 11]- (Test Scan Port) 3= Not Used
22191 #undef IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL
22192 #undef IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT
22193 #undef IOU_SLCR_MIO_PIN_11_L2_SEL_MASK
22194 #define IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 0x00000000
22195 #define IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 3
22196 #define IOU_SLCR_MIO_PIN_11_L2_SEL_MASK 0x00000018U
22199 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0=
22200 * gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_p
22201 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
22202 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
22203 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal)
22204 * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (
22205 * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
22206 * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
22208 #undef IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL
22209 #undef IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT
22210 #undef IOU_SLCR_MIO_PIN_11_L3_SEL_MASK
22211 #define IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 0x00000000
22212 #define IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 5
22213 #define IOU_SLCR_MIO_PIN_11_L3_SEL_MASK 0x000000E0U
22216 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_
22217 * upper- (QSPI Upper Clock)
22219 #undef IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL
22220 #undef IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT
22221 #undef IOU_SLCR_MIO_PIN_12_L0_SEL_MASK
22222 #define IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 0x00000000
22223 #define IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 1
22224 #define IOU_SLCR_MIO_PIN_12_L0_SEL_MASK 0x00000002U
22227 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA
22228 * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe)
22230 #undef IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL
22231 #undef IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT
22232 #undef IOU_SLCR_MIO_PIN_12_L1_SEL_MASK
22233 #define IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 0x00000000
22234 #define IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 2
22235 #define IOU_SLCR_MIO_PIN_12_L1_SEL_MASK 0x00000004U
22238 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
22239 * , test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[
22240 * 12]- (Test Scan Port) 3= Not Used
22242 #undef IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL
22243 #undef IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT
22244 #undef IOU_SLCR_MIO_PIN_12_L2_SEL_MASK
22245 #define IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 0x00000000
22246 #define IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 3
22247 #define IOU_SLCR_MIO_PIN_12_L2_SEL_MASK 0x00000018U
22250 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0=
22251 * gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_p
22252 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
22253 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJT
22254 * AG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_
22255 * sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, O
22256 * utput, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace
22257 * dq[10]- (Trace Port Databus)
22259 #undef IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL
22260 #undef IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT
22261 #undef IOU_SLCR_MIO_PIN_12_L3_SEL_MASK
22262 #define IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 0x00000000
22263 #define IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 5
22264 #define IOU_SLCR_MIO_PIN_12_L3_SEL_MASK 0x000000E0U
22267 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
22269 #undef IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL
22270 #undef IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT
22271 #undef IOU_SLCR_MIO_PIN_13_L0_SEL_MASK
22272 #define IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 0x00000000
22273 #define IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 1
22274 #define IOU_SLCR_MIO_PIN_13_L0_SEL_MASK 0x00000002U
22277 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NA
22280 #undef IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL
22281 #undef IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT
22282 #undef IOU_SLCR_MIO_PIN_13_L1_SEL_MASK
22283 #define IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 0x00000000
22284 #define IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 2
22285 #define IOU_SLCR_MIO_PIN_13_L1_SEL_MASK 0x00000004U
22288 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]-
22289 * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= t
22290 * est_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output,
22291 * test_scan_out[13]- (Test Scan Port) 3= Not Used
22293 #undef IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL
22294 #undef IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT
22295 #undef IOU_SLCR_MIO_PIN_13_L2_SEL_MASK
22296 #define IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 0x00000000
22297 #define IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 3
22298 #define IOU_SLCR_MIO_PIN_13_L2_SEL_MASK 0x00000018U
22301 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0=
22302 * gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_ph
22303 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
22304 * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTA
22305 * G TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1,
22306 * Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UAR
22307 * T receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Data
22310 #undef IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL
22311 #undef IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT
22312 #undef IOU_SLCR_MIO_PIN_13_L3_SEL_MASK
22313 #define IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 0x00000000
22314 #define IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 5
22315 #define IOU_SLCR_MIO_PIN_13_L3_SEL_MASK 0x000000E0U
22318 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
22320 #undef IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL
22321 #undef IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT
22322 #undef IOU_SLCR_MIO_PIN_14_L0_SEL_MASK
22323 #define IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 0x00000000
22324 #define IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 1
22325 #define IOU_SLCR_MIO_PIN_14_L0_SEL_MASK 0x00000002U
22328 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND
22329 * Command Latch Enable)
22331 #undef IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL
22332 #undef IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT
22333 #undef IOU_SLCR_MIO_PIN_14_L1_SEL_MASK
22334 #define IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 0x00000000
22335 #define IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 2
22336 #define IOU_SLCR_MIO_PIN_14_L1_SEL_MASK 0x00000004U
22339 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]-
22340 * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= t
22341 * est_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output,
22342 * test_scan_out[14]- (Test Scan Port) 3= Not Used
22344 #undef IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL
22345 #undef IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT
22346 #undef IOU_SLCR_MIO_PIN_14_L2_SEL_MASK
22347 #define IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 0x00000000
22348 #define IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 3
22349 #define IOU_SLCR_MIO_PIN_14_L2_SEL_MASK 0x00000018U
22352 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0=
22353 * gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_ph
22354 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
22355 * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJT
22356 * AG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0,
22357 * Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver
22358 * serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)
22360 #undef IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL
22361 #undef IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT
22362 #undef IOU_SLCR_MIO_PIN_14_L3_SEL_MASK
22363 #define IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 0x00000000
22364 #define IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 5
22365 #define IOU_SLCR_MIO_PIN_14_L3_SEL_MASK 0x000000E0U
22368 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
22370 #undef IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL
22371 #undef IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT
22372 #undef IOU_SLCR_MIO_PIN_15_L0_SEL_MASK
22373 #define IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 0x00000000
22374 #define IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 1
22375 #define IOU_SLCR_MIO_PIN_15_L0_SEL_MASK 0x00000002U
22378 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND
22379 * Address Latch Enable)
22381 #undef IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL
22382 #undef IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT
22383 #undef IOU_SLCR_MIO_PIN_15_L1_SEL_MASK
22384 #define IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 0x00000000
22385 #define IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 2
22386 #define IOU_SLCR_MIO_PIN_15_L1_SEL_MASK 0x00000004U
22389 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]-
22390 * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= t
22391 * est_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output,
22392 * test_scan_out[15]- (Test Scan Port) 3= Not Used
22394 #undef IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL
22395 #undef IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT
22396 #undef IOU_SLCR_MIO_PIN_15_L2_SEL_MASK
22397 #define IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 0x00000000
22398 #define IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 3
22399 #define IOU_SLCR_MIO_PIN_15_L2_SEL_MASK 0x00000018U
22402 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0=
22403 * gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_p
22404 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
22405 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJT
22406 * AG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outp
22407 * ut, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_ou
22408 * t- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seria
22409 * l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
22411 #undef IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL
22412 #undef IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT
22413 #undef IOU_SLCR_MIO_PIN_15_L3_SEL_MASK
22414 #define IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 0x00000000
22415 #define IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 5
22416 #define IOU_SLCR_MIO_PIN_15_L3_SEL_MASK 0x000000E0U
22419 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
22421 #undef IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL
22422 #undef IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT
22423 #undef IOU_SLCR_MIO_PIN_16_L0_SEL_MASK
22424 #define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 0x00000000
22425 #define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 1
22426 #define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK 0x00000002U
22429 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (
22430 * NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus)
22432 #undef IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL
22433 #undef IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT
22434 #undef IOU_SLCR_MIO_PIN_16_L1_SEL_MASK
22435 #define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 0x00000000
22436 #define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 2
22437 #define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK 0x00000004U
22440 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]-
22441 * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= t
22442 * est_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output,
22443 * test_scan_out[16]- (Test Scan Port) 3= Not Used
22445 #undef IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL
22446 #undef IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT
22447 #undef IOU_SLCR_MIO_PIN_16_L2_SEL_MASK
22448 #define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 0x00000000
22449 #define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 3
22450 #define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK 0x00000018U
22453 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0=
22454 * gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_p
22455 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
22456 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
22457 * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s
22458 * pi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl
22459 * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
22460 * Output, tracedq[14]- (Trace Port Databus)
22462 #undef IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL
22463 #undef IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT
22464 #undef IOU_SLCR_MIO_PIN_16_L3_SEL_MASK
22465 #define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 0x00000000
22466 #define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 5
22467 #define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK 0x000000E0U
22470 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
22472 #undef IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL
22473 #undef IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT
22474 #undef IOU_SLCR_MIO_PIN_17_L0_SEL_MASK
22475 #define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 0x00000000
22476 #define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 1
22477 #define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK 0x00000002U
22480 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (
22481 * NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus)
22483 #undef IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL
22484 #undef IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT
22485 #undef IOU_SLCR_MIO_PIN_17_L1_SEL_MASK
22486 #define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 0x00000000
22487 #define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 2
22488 #define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK 0x00000004U
22491 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]-
22492 * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= t
22493 * est_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output,
22494 * test_scan_out[17]- (Test Scan Port) 3= Not Used
22496 #undef IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL
22497 #undef IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT
22498 #undef IOU_SLCR_MIO_PIN_17_L2_SEL_MASK
22499 #define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 0x00000000
22500 #define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 3
22501 #define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK 0x00000018U
22504 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0=
22505 * gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_ph
22506 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
22507 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
22508 * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4
22509 * = spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T
22510 * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
22511 * 7= trace, Output, tracedq[15]- (Trace Port Databus)
22513 #undef IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL
22514 #undef IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT
22515 #undef IOU_SLCR_MIO_PIN_17_L3_SEL_MASK
22516 #define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 0x00000000
22517 #define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 5
22518 #define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK 0x000000E0U
22521 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
22523 #undef IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL
22524 #undef IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT
22525 #undef IOU_SLCR_MIO_PIN_18_L0_SEL_MASK
22526 #define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 0x00000000
22527 #define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 1
22528 #define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK 0x00000002U
22531 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (
22532 * NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus)
22534 #undef IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL
22535 #undef IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT
22536 #undef IOU_SLCR_MIO_PIN_18_L1_SEL_MASK
22537 #define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 0x00000000
22538 #define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 2
22539 #define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK 0x00000004U
22542 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]-
22543 * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= t
22544 * est_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output,
22545 * test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU
22548 #undef IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL
22549 #undef IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT
22550 #undef IOU_SLCR_MIO_PIN_18_L2_SEL_MASK
22551 #define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 0x00000000
22552 #define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 3
22553 #define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK 0x00000018U
22556 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0=
22557 * gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_ph
22558 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
22559 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
22560 * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp
22561 * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo
22562 * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
22564 #undef IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL
22565 #undef IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT
22566 #undef IOU_SLCR_MIO_PIN_18_L3_SEL_MASK
22567 #define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 0x00000000
22568 #define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 5
22569 #define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK 0x000000E0U
22572 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
22574 #undef IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL
22575 #undef IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT
22576 #undef IOU_SLCR_MIO_PIN_19_L0_SEL_MASK
22577 #define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 0x00000000
22578 #define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 1
22579 #define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK 0x00000002U
22582 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (
22583 * NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus)
22585 #undef IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL
22586 #undef IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT
22587 #undef IOU_SLCR_MIO_PIN_19_L1_SEL_MASK
22588 #define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 0x00000000
22589 #define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 2
22590 #define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK 0x00000004U
22593 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]-
22594 * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= t
22595 * est_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output,
22596 * test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU
22599 #undef IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL
22600 #undef IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT
22601 #undef IOU_SLCR_MIO_PIN_19_L2_SEL_MASK
22602 #define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 0x00000000
22603 #define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 3
22604 #define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK 0x00000018U
22607 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0=
22608 * gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_p
22609 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
22610 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
22611 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI
22612 * Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6=
22613 * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
22615 #undef IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL
22616 #undef IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT
22617 #undef IOU_SLCR_MIO_PIN_19_L3_SEL_MASK
22618 #define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 0x00000000
22619 #define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 5
22620 #define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK 0x000000E0U
22623 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
22625 #undef IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL
22626 #undef IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT
22627 #undef IOU_SLCR_MIO_PIN_20_L0_SEL_MASK
22628 #define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 0x00000000
22629 #define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 1
22630 #define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK 0x00000002U
22633 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (
22634 * NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus)
22636 #undef IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL
22637 #undef IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT
22638 #undef IOU_SLCR_MIO_PIN_20_L1_SEL_MASK
22639 #define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 0x00000000
22640 #define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 2
22641 #define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK 0x00000004U
22644 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]-
22645 * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= t
22646 * est_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output,
22647 * test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU
22650 #undef IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL
22651 #undef IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT
22652 #undef IOU_SLCR_MIO_PIN_20_L2_SEL_MASK
22653 #define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 0x00000000
22654 #define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 3
22655 #define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK 0x00000018U
22658 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0=
22659 * gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_p
22660 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
22661 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
22662 * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas
22663 * ter Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua
22664 * 1_txd- (UART transmitter serial output) 7= Not Used
22666 #undef IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL
22667 #undef IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT
22668 #undef IOU_SLCR_MIO_PIN_20_L3_SEL_MASK
22669 #define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 0x00000000
22670 #define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 5
22671 #define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK 0x000000E0U
22674 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
22676 #undef IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL
22677 #undef IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT
22678 #undef IOU_SLCR_MIO_PIN_21_L0_SEL_MASK
22679 #define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 0x00000000
22680 #define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 1
22681 #define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK 0x00000002U
22684 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (
22685 * NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus)
22687 #undef IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL
22688 #undef IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT
22689 #undef IOU_SLCR_MIO_PIN_21_L1_SEL_MASK
22690 #define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 0x00000000
22691 #define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 2
22692 #define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK 0x00000004U
22695 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com
22696 * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= tes
22697 * t_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, t
22698 * est_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU E
22701 #undef IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL
22702 #undef IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT
22703 #undef IOU_SLCR_MIO_PIN_21_L2_SEL_MASK
22704 #define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 0x00000000
22705 #define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 3
22706 #define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK 0x00000018U
22709 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0=
22710 * gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_ph
22711 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
22712 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
22713 * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master
22714 * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc
22715 * 1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (
22716 * UART receiver serial input) 7= Not Used
22718 #undef IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL
22719 #undef IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT
22720 #undef IOU_SLCR_MIO_PIN_21_L3_SEL_MASK
22721 #define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 0x00000000
22722 #define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 5
22723 #define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK 0x000000E0U
22726 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
22728 #undef IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL
22729 #undef IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT
22730 #undef IOU_SLCR_MIO_PIN_22_L0_SEL_MASK
22731 #define IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 0x00000000
22732 #define IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 1
22733 #define IOU_SLCR_MIO_PIN_22_L0_SEL_MASK 0x00000002U
22736 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAN
22739 #undef IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL
22740 #undef IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT
22741 #undef IOU_SLCR_MIO_PIN_22_L1_SEL_MASK
22742 #define IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 0x00000000
22743 #define IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 2
22744 #define IOU_SLCR_MIO_PIN_22_L1_SEL_MASK 0x00000004U
22747 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out-
22748 * (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) =
22749 * test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, c
22750 * su_ext_tamper- (CSU Ext Tamper)
22752 #undef IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL
22753 #undef IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT
22754 #undef IOU_SLCR_MIO_PIN_22_L2_SEL_MASK
22755 #define IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 0x00000000
22756 #define IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 3
22757 #define IOU_SLCR_MIO_PIN_22_L2_SEL_MASK 0x00000018U
22760 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0=
22761 * gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_ph
22762 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
22763 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
22764 * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4=
22765 * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (
22766 * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U
22769 #undef IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL
22770 #undef IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT
22771 #undef IOU_SLCR_MIO_PIN_22_L3_SEL_MASK
22772 #define IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 0x00000000
22773 #define IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 5
22774 #define IOU_SLCR_MIO_PIN_22_L3_SEL_MASK 0x000000E0U
22777 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
22779 #undef IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL
22780 #undef IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT
22781 #undef IOU_SLCR_MIO_PIN_23_L0_SEL_MASK
22782 #define IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 0x00000000
22783 #define IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 1
22784 #define IOU_SLCR_MIO_PIN_23_L0_SEL_MASK 0x00000002U
22787 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (
22788 * NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus)
22790 #undef IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL
22791 #undef IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT
22792 #undef IOU_SLCR_MIO_PIN_23_L1_SEL_MASK
22793 #define IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 0x00000000
22794 #define IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 2
22795 #define IOU_SLCR_MIO_PIN_23_L1_SEL_MASK 0x00000004U
22798 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow-
22799 * (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Po
22800 * rt) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Inp
22801 * ut, csu_ext_tamper- (CSU Ext Tamper)
22803 #undef IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL
22804 #undef IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT
22805 #undef IOU_SLCR_MIO_PIN_23_L2_SEL_MASK
22806 #define IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 0x00000000
22807 #define IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 3
22808 #define IOU_SLCR_MIO_PIN_23_L2_SEL_MASK 0x00000018U
22811 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0=
22812 * gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_p
22813 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
22814 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
22815 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal)
22816 * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (
22817 * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
22818 * tput) 7= Not Used
22820 #undef IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL
22821 #undef IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT
22822 #undef IOU_SLCR_MIO_PIN_23_L3_SEL_MASK
22823 #define IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 0x00000000
22824 #define IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 5
22825 #define IOU_SLCR_MIO_PIN_23_L3_SEL_MASK 0x000000E0U
22828 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
22830 #undef IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL
22831 #undef IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT
22832 #undef IOU_SLCR_MIO_PIN_24_L0_SEL_MASK
22833 #define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 0x00000000
22834 #define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 1
22835 #define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK 0x00000002U
22838 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (
22839 * NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus)
22841 #undef IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL
22842 #undef IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT
22843 #undef IOU_SLCR_MIO_PIN_24_L1_SEL_MASK
22844 #define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 0x00000000
22845 #define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 2
22846 #define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK 0x00000004U
22849 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD
22850 * card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test
22851 * Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3=
22852 * csu, Input, csu_ext_tamper- (CSU Ext Tamper)
22854 #undef IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL
22855 #undef IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT
22856 #undef IOU_SLCR_MIO_PIN_24_L2_SEL_MASK
22857 #define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 0x00000000
22858 #define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 3
22859 #define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK 0x00000018U
22862 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0=
22863 * gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_p
22864 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
22865 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
22866 * Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (T
22867 * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= N
22870 #undef IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL
22871 #undef IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT
22872 #undef IOU_SLCR_MIO_PIN_24_L3_SEL_MASK
22873 #define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 0x00000000
22874 #define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 5
22875 #define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK 0x000000E0U
22878 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
22880 #undef IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL
22881 #undef IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT
22882 #undef IOU_SLCR_MIO_PIN_25_L0_SEL_MASK
22883 #define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 0x00000000
22884 #define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 1
22885 #define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK 0x00000002U
22888 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAN
22891 #undef IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL
22892 #undef IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT
22893 #undef IOU_SLCR_MIO_PIN_25_L1_SEL_MASK
22894 #define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 0x00000000
22895 #define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 2
22896 #define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK 0x00000004U
22899 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca
22900 * rd write protect from connector) 2= test_scan, Input, test_scan_in[25]-
22901 * (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port
22902 * ) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
22904 #undef IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL
22905 #undef IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT
22906 #undef IOU_SLCR_MIO_PIN_25_L2_SEL_MASK
22907 #define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 0x00000000
22908 #define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 3
22909 #define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK 0x00000018U
22912 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0=
22913 * gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_ph
22914 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
22915 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
22916 * (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_ou
22917 * t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
22920 #undef IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL
22921 #undef IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT
22922 #undef IOU_SLCR_MIO_PIN_25_L3_SEL_MASK
22923 #define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 0x00000000
22924 #define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 5
22925 #define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK 0x000000E0U
22928 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_
22929 * clk- (TX RGMII clock)
22931 #undef IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL
22932 #undef IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT
22933 #undef IOU_SLCR_MIO_PIN_26_L0_SEL_MASK
22934 #define IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 0x00000000
22935 #define IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 1
22936 #define IOU_SLCR_MIO_PIN_26_L0_SEL_MASK 0x00000002U
22939 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA
22942 #undef IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL
22943 #undef IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT
22944 #undef IOU_SLCR_MIO_PIN_26_L1_SEL_MASK
22945 #define IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 0x00000000
22946 #define IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 2
22947 #define IOU_SLCR_MIO_PIN_26_L1_SEL_MASK 0x00000004U
22950 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU
22951 * GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_sca
22952 * n, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_ta
22953 * mper- (CSU Ext Tamper)
22955 #undef IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL
22956 #undef IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT
22957 #undef IOU_SLCR_MIO_PIN_26_L2_SEL_MASK
22958 #define IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 0x00000000
22959 #define IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 3
22960 #define IOU_SLCR_MIO_PIN_26_L2_SEL_MASK 0x00000018U
22963 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= g
22964 * pio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_
22965 * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
22966 * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
22967 * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_scl
22968 * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu
22969 * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (
22970 * Trace Port Databus)
22972 #undef IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL
22973 #undef IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT
22974 #undef IOU_SLCR_MIO_PIN_26_L3_SEL_MASK
22975 #define IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 0x00000000
22976 #define IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 5
22977 #define IOU_SLCR_MIO_PIN_26_L3_SEL_MASK 0x000000E0U
22980 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
22981 * [0]- (TX RGMII data)
22983 #undef IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL
22984 #undef IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT
22985 #undef IOU_SLCR_MIO_PIN_27_L0_SEL_MASK
22986 #define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 0x00000000
22987 #define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 1
22988 #define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK 0x00000002U
22991 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N
22994 #undef IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL
22995 #undef IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT
22996 #undef IOU_SLCR_MIO_PIN_27_L1_SEL_MASK
22997 #define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 0x00000000
22998 #define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 2
22999 #define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK 0x00000004U
23002 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU
23003 * GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_sca
23004 * n, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_d
23005 * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
23007 #undef IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL
23008 #undef IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT
23009 #undef IOU_SLCR_MIO_PIN_27_L2_SEL_MASK
23010 #define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 0x00000000
23011 #define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 3
23012 #define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK 0x00000018U
23015 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= g
23016 * pio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy
23017 * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
23018 * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
23019 * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O
23020 * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR
23021 * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D
23024 #undef IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL
23025 #undef IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT
23026 #undef IOU_SLCR_MIO_PIN_27_L3_SEL_MASK
23027 #define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 0x00000000
23028 #define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 5
23029 #define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK 0x000000E0U
23032 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
23033 * [1]- (TX RGMII data)
23035 #undef IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL
23036 #undef IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT
23037 #undef IOU_SLCR_MIO_PIN_28_L0_SEL_MASK
23038 #define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 0x00000000
23039 #define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 1
23040 #define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK 0x00000002U
23043 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N
23046 #undef IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL
23047 #undef IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT
23048 #undef IOU_SLCR_MIO_PIN_28_L1_SEL_MASK
23049 #define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 0x00000000
23050 #define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 2
23051 #define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK 0x00000004U
23054 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU
23055 * GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_sca
23056 * n, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_p
23057 * lug_detect- (Dp Aux Hot Plug)
23059 #undef IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL
23060 #undef IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT
23061 #undef IOU_SLCR_MIO_PIN_28_L2_SEL_MASK
23062 #define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 0x00000000
23063 #define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 3
23064 #define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK 0x00000018U
23067 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= g
23068 * pio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy
23069 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
23070 * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA
23071 * G TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1,
23072 * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt
23073 * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
23075 #undef IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL
23076 #undef IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT
23077 #undef IOU_SLCR_MIO_PIN_28_L3_SEL_MASK
23078 #define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 0x00000000
23079 #define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 5
23080 #define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK 0x000000E0U
23083 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
23084 * [2]- (TX RGMII data)
23086 #undef IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL
23087 #undef IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT
23088 #undef IOU_SLCR_MIO_PIN_29_L0_SEL_MASK
23089 #define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 0x00000000
23090 #define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 1
23091 #define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK 0x00000002U
23094 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
23095 * PCIE Reset signal)
23097 #undef IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL
23098 #undef IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT
23099 #undef IOU_SLCR_MIO_PIN_29_L1_SEL_MASK
23100 #define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 0x00000000
23101 #define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 2
23102 #define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK 0x00000004U
23105 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU
23106 * GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_sca
23107 * n, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_d
23108 * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
23110 #undef IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL
23111 #undef IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT
23112 #undef IOU_SLCR_MIO_PIN_29_L2_SEL_MASK
23113 #define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 0x00000000
23114 #define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 3
23115 #define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK 0x00000018U
23118 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= g
23119 * pio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_
23120 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
23121 * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
23122 * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output,
23123 * spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out-
23124 * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input
23125 * ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
23127 #undef IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL
23128 #undef IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT
23129 #undef IOU_SLCR_MIO_PIN_29_L3_SEL_MASK
23130 #define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 0x00000000
23131 #define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 5
23132 #define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK 0x000000E0U
23135 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
23136 * [3]- (TX RGMII data)
23138 #undef IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL
23139 #undef IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT
23140 #undef IOU_SLCR_MIO_PIN_30_L0_SEL_MASK
23141 #define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 0x00000000
23142 #define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 1
23143 #define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK 0x00000002U
23146 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
23147 * PCIE Reset signal)
23149 #undef IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL
23150 #undef IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT
23151 #undef IOU_SLCR_MIO_PIN_30_L1_SEL_MASK
23152 #define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 0x00000000
23153 #define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 2
23154 #define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK 0x00000004U
23157 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU
23158 * GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_sca
23159 * n, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_p
23160 * lug_detect- (Dp Aux Hot Plug)
23162 #undef IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL
23163 #undef IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT
23164 #undef IOU_SLCR_MIO_PIN_30_L2_SEL_MASK
23165 #define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 0x00000000
23166 #define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 3
23167 #define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK 0x00000018U
23170 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= g
23171 * pio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_
23172 * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
23173 * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat
23174 * ch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0
23175 * , Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock
23176 * ) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output,
23177 * tracedq[8]- (Trace Port Databus)
23179 #undef IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL
23180 #undef IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT
23181 #undef IOU_SLCR_MIO_PIN_30_L3_SEL_MASK
23182 #define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 0x00000000
23183 #define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 5
23184 #define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK 0x000000E0U
23187 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_
23188 * ctl- (TX RGMII control)
23190 #undef IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL
23191 #undef IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT
23192 #undef IOU_SLCR_MIO_PIN_31_L0_SEL_MASK
23193 #define IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 0x00000000
23194 #define IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 1
23195 #define IOU_SLCR_MIO_PIN_31_L0_SEL_MASK 0x00000002U
23198 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
23199 * PCIE Reset signal)
23201 #undef IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL
23202 #undef IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT
23203 #undef IOU_SLCR_MIO_PIN_31_L1_SEL_MASK
23204 #define IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 0x00000000
23205 #define IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 2
23206 #define IOU_SLCR_MIO_PIN_31_L1_SEL_MASK 0x00000004U
23209 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU
23210 * GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_sca
23211 * n, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_ta
23212 * mper- (CSU Ext Tamper)
23214 #undef IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL
23215 #undef IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT
23216 #undef IOU_SLCR_MIO_PIN_31_L2_SEL_MASK
23217 #define IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 0x00000000
23218 #define IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 3
23219 #define IOU_SLCR_MIO_PIN_31_L2_SEL_MASK 0x00000018U
23222 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= g
23223 * pio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy
23224 * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
23225 * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (
23226 * Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4=
23227 * spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TT
23228 * C Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial outp
23229 * ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)
23231 #undef IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL
23232 #undef IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT
23233 #undef IOU_SLCR_MIO_PIN_31_L3_SEL_MASK
23234 #define IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 0x00000000
23235 #define IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 5
23236 #define IOU_SLCR_MIO_PIN_31_L3_SEL_MASK 0x000000E0U
23239 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c
23240 * lk- (RX RGMII clock)
23242 #undef IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL
23243 #undef IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT
23244 #undef IOU_SLCR_MIO_PIN_32_L0_SEL_MASK
23245 #define IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 0x00000000
23246 #define IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 1
23247 #define IOU_SLCR_MIO_PIN_32_L0_SEL_MASK 0x00000002U
23250 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA
23251 * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe)
23253 #undef IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL
23254 #undef IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT
23255 #undef IOU_SLCR_MIO_PIN_32_L1_SEL_MASK
23256 #define IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 0x00000000
23257 #define IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 2
23258 #define IOU_SLCR_MIO_PIN_32_L1_SEL_MASK 0x00000004U
23261 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PM
23262 * U GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_sc
23263 * an, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_t
23264 * amper- (CSU Ext Tamper)
23266 #undef IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL
23267 #undef IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT
23268 #undef IOU_SLCR_MIO_PIN_32_L2_SEL_MASK
23269 #define IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 0x00000000
23270 #define IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 3
23271 #define IOU_SLCR_MIO_PIN_32_L2_SEL_MASK 0x00000018U
23274 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= g
23275 * pio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy
23276 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
23277 * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa
23278 * tch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4=
23279 * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (T
23280 * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= t
23281 * race, Output, tracedq[10]- (Trace Port Databus)
23283 #undef IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL
23284 #undef IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT
23285 #undef IOU_SLCR_MIO_PIN_32_L3_SEL_MASK
23286 #define IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 0x00000000
23287 #define IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 5
23288 #define IOU_SLCR_MIO_PIN_32_L3_SEL_MASK 0x000000E0U
23291 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[
23292 * 0]- (RX RGMII data)
23294 #undef IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL
23295 #undef IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT
23296 #undef IOU_SLCR_MIO_PIN_33_L0_SEL_MASK
23297 #define IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 0x00000000
23298 #define IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 1
23299 #define IOU_SLCR_MIO_PIN_33_L0_SEL_MASK 0x00000002U
23302 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
23303 * PCIE Reset signal)
23305 #undef IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL
23306 #undef IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT
23307 #undef IOU_SLCR_MIO_PIN_33_L1_SEL_MASK
23308 #define IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 0x00000000
23309 #define IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 2
23310 #define IOU_SLCR_MIO_PIN_33_L1_SEL_MASK 0x00000004U
23313 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PM
23314 * U GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_sc
23315 * an, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_t
23316 * amper- (CSU Ext Tamper)
23318 #undef IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL
23319 #undef IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT
23320 #undef IOU_SLCR_MIO_PIN_33_L2_SEL_MASK
23321 #define IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 0x00000000
23322 #define IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 3
23323 #define IOU_SLCR_MIO_PIN_33_L2_SEL_MASK 0x00000018U
23326 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= g
23327 * pio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_
23328 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
23329 * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W
23330 * atch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Mas
23331 * ter Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1
23332 * , Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq
23333 * [11]- (Trace Port Databus)
23335 #undef IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL
23336 #undef IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT
23337 #undef IOU_SLCR_MIO_PIN_33_L3_SEL_MASK
23338 #define IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 0x00000000
23339 #define IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 5
23340 #define IOU_SLCR_MIO_PIN_33_L3_SEL_MASK 0x000000E0U
23343 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[
23344 * 1]- (RX RGMII data)
23346 #undef IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL
23347 #undef IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT
23348 #undef IOU_SLCR_MIO_PIN_34_L0_SEL_MASK
23349 #define IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 0x00000000
23350 #define IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 1
23351 #define IOU_SLCR_MIO_PIN_34_L0_SEL_MASK 0x00000002U
23354 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
23355 * PCIE Reset signal)
23357 #undef IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL
23358 #undef IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT
23359 #undef IOU_SLCR_MIO_PIN_34_L1_SEL_MASK
23360 #define IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 0x00000000
23361 #define IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 2
23362 #define IOU_SLCR_MIO_PIN_34_L1_SEL_MASK 0x00000004U
23365 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PM
23366 * U GPI) 2= test_scan, Input, test_scan_in[34]- (Test Scan Port) = test_sc
23367 * an, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_
23368 * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
23370 #undef IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL
23371 #undef IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT
23372 #undef IOU_SLCR_MIO_PIN_34_L2_SEL_MASK
23373 #define IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 0x00000000
23374 #define IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 3
23375 #define IOU_SLCR_MIO_PIN_34_L2_SEL_MASK 0x00000018U
23378 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= g
23379 * pio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can0, Input, can0_phy_
23380 * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
23381 * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat
23382 * ch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master
23383 * Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rx
23384 * d- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Po
23387 #undef IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL
23388 #undef IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT
23389 #undef IOU_SLCR_MIO_PIN_34_L3_SEL_MASK
23390 #define IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 0x00000000
23391 #define IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 5
23392 #define IOU_SLCR_MIO_PIN_34_L3_SEL_MASK 0x000000E0U
23395 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[
23396 * 2]- (RX RGMII data)
23398 #undef IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL
23399 #undef IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT
23400 #undef IOU_SLCR_MIO_PIN_35_L0_SEL_MASK
23401 #define IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 0x00000000
23402 #define IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 1
23403 #define IOU_SLCR_MIO_PIN_35_L0_SEL_MASK 0x00000002U
23406 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
23407 * PCIE Reset signal)
23409 #undef IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL
23410 #undef IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT
23411 #undef IOU_SLCR_MIO_PIN_35_L1_SEL_MASK
23412 #define IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 0x00000000
23413 #define IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 2
23414 #define IOU_SLCR_MIO_PIN_35_L1_SEL_MASK 0x00000004U
23417 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PM
23418 * U GPI) 2= test_scan, Input, test_scan_in[35]- (Test Scan Port) = test_sc
23419 * an, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_
23420 * plug_detect- (Dp Aux Hot Plug)
23422 #undef IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL
23423 #undef IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT
23424 #undef IOU_SLCR_MIO_PIN_35_L2_SEL_MASK
23425 #define IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 0x00000000
23426 #define IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 3
23427 #define IOU_SLCR_MIO_PIN_35_L2_SEL_MASK 0x00000018U
23430 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= g
23431 * pio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can0, Output, can0_phy
23432 * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
23433 * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (
23434 * Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master
23435 * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2
23436 * , Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (
23437 * UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Po
23440 #undef IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL
23441 #undef IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT
23442 #undef IOU_SLCR_MIO_PIN_35_L3_SEL_MASK
23443 #define IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 0x00000000
23444 #define IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 5
23445 #define IOU_SLCR_MIO_PIN_35_L3_SEL_MASK 0x000000E0U
23448 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[
23449 * 3]- (RX RGMII data)
23451 #undef IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL
23452 #undef IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT
23453 #undef IOU_SLCR_MIO_PIN_36_L0_SEL_MASK
23454 #define IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 0x00000000
23455 #define IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 1
23456 #define IOU_SLCR_MIO_PIN_36_L0_SEL_MASK 0x00000002U
23459 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
23460 * PCIE Reset signal)
23462 #undef IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL
23463 #undef IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT
23464 #undef IOU_SLCR_MIO_PIN_36_L1_SEL_MASK
23465 #define IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 0x00000000
23466 #define IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 2
23467 #define IOU_SLCR_MIO_PIN_36_L1_SEL_MASK 0x00000004U
23470 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PM
23471 * U GPI) 2= test_scan, Input, test_scan_in[36]- (Test Scan Port) = test_sc
23472 * an, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_
23473 * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
23475 #undef IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL
23476 #undef IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT
23477 #undef IOU_SLCR_MIO_PIN_36_L2_SEL_MASK
23478 #define IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 0x00000000
23479 #define IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 3
23480 #define IOU_SLCR_MIO_PIN_36_L2_SEL_MASK 0x00000018U
23483 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0=
23484 * gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can1, Output, can1_p
23485 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
23486 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
23487 * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s
23488 * pi1, Output, spi1_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl
23489 * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
23490 * Output, tracedq[14]- (Trace Port Databus)
23492 #undef IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL
23493 #undef IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT
23494 #undef IOU_SLCR_MIO_PIN_36_L3_SEL_MASK
23495 #define IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 0x00000000
23496 #define IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 5
23497 #define IOU_SLCR_MIO_PIN_36_L3_SEL_MASK 0x000000E0U
23500 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c
23501 * tl- (RX RGMII control )
23503 #undef IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL
23504 #undef IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT
23505 #undef IOU_SLCR_MIO_PIN_37_L0_SEL_MASK
23506 #define IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 0x00000000
23507 #define IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 1
23508 #define IOU_SLCR_MIO_PIN_37_L0_SEL_MASK 0x00000002U
23511 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
23512 * PCIE Reset signal)
23514 #undef IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL
23515 #undef IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT
23516 #undef IOU_SLCR_MIO_PIN_37_L1_SEL_MASK
23517 #define IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 0x00000000
23518 #define IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 2
23519 #define IOU_SLCR_MIO_PIN_37_L1_SEL_MASK 0x00000004U
23522 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PM
23523 * U GPI) 2= test_scan, Input, test_scan_in[37]- (Test Scan Port) = test_sc
23524 * an, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_
23525 * plug_detect- (Dp Aux Hot Plug)
23527 #undef IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL
23528 #undef IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT
23529 #undef IOU_SLCR_MIO_PIN_37_L2_SEL_MASK
23530 #define IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 0x00000000
23531 #define IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 3
23532 #define IOU_SLCR_MIO_PIN_37_L2_SEL_MASK 0x00000018U
23535 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0=
23536 * gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can1, Input, can1_ph
23537 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
23538 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
23539 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4
23540 * = spi1, Input, spi1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T
23541 * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
23542 * 7= trace, Output, tracedq[15]- (Trace Port Databus)
23544 #undef IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL
23545 #undef IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT
23546 #undef IOU_SLCR_MIO_PIN_37_L3_SEL_MASK
23547 #define IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 0x00000000
23548 #define IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 5
23549 #define IOU_SLCR_MIO_PIN_37_L3_SEL_MASK 0x000000E0U
23552 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_
23553 * clk- (TX RGMII clock)
23555 #undef IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL
23556 #undef IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT
23557 #undef IOU_SLCR_MIO_PIN_38_L0_SEL_MASK
23558 #define IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 0x00000000
23559 #define IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 1
23560 #define IOU_SLCR_MIO_PIN_38_L0_SEL_MASK 0x00000002U
23563 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
23565 #undef IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL
23566 #undef IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT
23567 #undef IOU_SLCR_MIO_PIN_38_L1_SEL_MASK
23568 #define IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 0x00000000
23569 #define IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 2
23570 #define IOU_SLCR_MIO_PIN_38_L1_SEL_MASK 0x00000004U
23573 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out-
23574 * (SDSDIO clock) 2= Not Used 3= Not Used
23576 #undef IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL
23577 #undef IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT
23578 #undef IOU_SLCR_MIO_PIN_38_L2_SEL_MASK
23579 #define IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 0x00000000
23580 #define IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 3
23581 #define IOU_SLCR_MIO_PIN_38_L2_SEL_MASK 0x00000018U
23584 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0=
23585 * gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_ph
23586 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
23587 * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTA
23588 * G TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_s
23589 * clk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, In
23590 * put, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
23591 * (Trace Port Clock)
23593 #undef IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL
23594 #undef IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT
23595 #undef IOU_SLCR_MIO_PIN_38_L3_SEL_MASK
23596 #define IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 0x00000000
23597 #define IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 5
23598 #define IOU_SLCR_MIO_PIN_38_L3_SEL_MASK 0x000000E0U
23601 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd
23602 * [0]- (TX RGMII data)
23604 #undef IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL
23605 #undef IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT
23606 #undef IOU_SLCR_MIO_PIN_39_L0_SEL_MASK
23607 #define IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 0x00000000
23608 #define IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 1
23609 #define IOU_SLCR_MIO_PIN_39_L0_SEL_MASK 0x00000002U
23612 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
23614 #undef IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL
23615 #undef IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT
23616 #undef IOU_SLCR_MIO_PIN_39_L1_SEL_MASK
23617 #define IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 0x00000000
23618 #define IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 2
23619 #define IOU_SLCR_MIO_PIN_39_L1_SEL_MASK 0x00000004U
23622 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD
23623 * card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data b
23624 * us) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used
23626 #undef IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL
23627 #undef IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT
23628 #undef IOU_SLCR_MIO_PIN_39_L2_SEL_MASK
23629 #define IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 0x00000000
23630 #define IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 3
23631 #define IOU_SLCR_MIO_PIN_39_L2_SEL_MASK 0x00000018U
23634 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0=
23635 * gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_p
23636 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
23637 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJT
23638 * AG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0,
23639 * Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (U
23640 * ART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
23643 #undef IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL
23644 #undef IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT
23645 #undef IOU_SLCR_MIO_PIN_39_L3_SEL_MASK
23646 #define IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 0x00000000
23647 #define IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 5
23648 #define IOU_SLCR_MIO_PIN_39_L3_SEL_MASK 0x000000E0U
23651 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd
23652 * [1]- (TX RGMII data)
23654 #undef IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL
23655 #undef IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT
23656 #undef IOU_SLCR_MIO_PIN_40_L0_SEL_MASK
23657 #define IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 0x00000000
23658 #define IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 1
23659 #define IOU_SLCR_MIO_PIN_40_L0_SEL_MASK 0x00000002U
23662 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
23664 #undef IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL
23665 #undef IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT
23666 #undef IOU_SLCR_MIO_PIN_40_L1_SEL_MASK
23667 #define IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 0x00000000
23668 #define IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 2
23669 #define IOU_SLCR_MIO_PIN_40_L1_SEL_MASK 0x00000004U
23672 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com
23673 * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1
23674 * , Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[
23675 * 5]- (8-bit Data bus) 3= Not Used
23677 #undef IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL
23678 #undef IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT
23679 #undef IOU_SLCR_MIO_PIN_40_L2_SEL_MASK
23680 #define IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 0x00000000
23681 #define IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 3
23682 #define IOU_SLCR_MIO_PIN_40_L2_SEL_MASK 0x00000018U
23685 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0=
23686 * gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_p
23687 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
23688 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJ
23689 * TAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3
23690 * , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmi
23691 * tter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)
23693 #undef IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL
23694 #undef IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT
23695 #undef IOU_SLCR_MIO_PIN_40_L3_SEL_MASK
23696 #define IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 0x00000000
23697 #define IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 5
23698 #define IOU_SLCR_MIO_PIN_40_L3_SEL_MASK 0x000000E0U
23701 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd
23702 * [2]- (TX RGMII data)
23704 #undef IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL
23705 #undef IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT
23706 #undef IOU_SLCR_MIO_PIN_41_L0_SEL_MASK
23707 #define IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 0x00000000
23708 #define IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 1
23709 #define IOU_SLCR_MIO_PIN_41_L0_SEL_MASK 0x00000002U
23712 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
23714 #undef IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL
23715 #undef IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT
23716 #undef IOU_SLCR_MIO_PIN_41_L1_SEL_MASK
23717 #define IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 0x00000000
23718 #define IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 2
23719 #define IOU_SLCR_MIO_PIN_41_L1_SEL_MASK 0x00000004U
23722 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]-
23723 * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= s
23724 * d1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
23725 * t[6]- (8-bit Data bus) 3= Not Used
23727 #undef IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL
23728 #undef IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT
23729 #undef IOU_SLCR_MIO_PIN_41_L2_SEL_MASK
23730 #define IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 0x00000000
23731 #define IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 3
23732 #define IOU_SLCR_MIO_PIN_41_L2_SEL_MASK 0x00000018U
23735 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0=
23736 * gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_ph
23737 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
23738 * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTA
23739 * G TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outpu
23740 * t, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out
23741 * - (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inp
23742 * ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)
23744 #undef IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL
23745 #undef IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT
23746 #undef IOU_SLCR_MIO_PIN_41_L3_SEL_MASK
23747 #define IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 0x00000000
23748 #define IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 5
23749 #define IOU_SLCR_MIO_PIN_41_L3_SEL_MASK 0x000000E0U
23752 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd
23753 * [3]- (TX RGMII data)
23755 #undef IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL
23756 #undef IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT
23757 #undef IOU_SLCR_MIO_PIN_42_L0_SEL_MASK
23758 #define IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 0x00000000
23759 #define IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 1
23760 #define IOU_SLCR_MIO_PIN_42_L0_SEL_MASK 0x00000002U
23763 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
23765 #undef IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL
23766 #undef IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT
23767 #undef IOU_SLCR_MIO_PIN_42_L1_SEL_MASK
23768 #define IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 0x00000000
23769 #define IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 2
23770 #define IOU_SLCR_MIO_PIN_42_L1_SEL_MASK 0x00000004U
23773 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]-
23774 * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= s
23775 * d1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
23776 * t[7]- (8-bit Data bus) 3= Not Used
23778 #undef IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL
23779 #undef IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT
23780 #undef IOU_SLCR_MIO_PIN_42_L2_SEL_MASK
23781 #define IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 0x00000000
23782 #define IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 3
23783 #define IOU_SLCR_MIO_PIN_42_L2_SEL_MASK 0x00000018U
23786 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0=
23787 * gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_ph
23788 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
23789 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
23790 * atch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= sp
23791 * i0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo
23792 * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu
23793 * t, tracedq[2]- (Trace Port Databus)
23795 #undef IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL
23796 #undef IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT
23797 #undef IOU_SLCR_MIO_PIN_42_L3_SEL_MASK
23798 #define IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 0x00000000
23799 #define IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 5
23800 #define IOU_SLCR_MIO_PIN_42_L3_SEL_MASK 0x000000E0U
23803 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_
23804 * ctl- (TX RGMII control)
23806 #undef IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL
23807 #undef IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT
23808 #undef IOU_SLCR_MIO_PIN_43_L0_SEL_MASK
23809 #define IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 0x00000000
23810 #define IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 1
23811 #define IOU_SLCR_MIO_PIN_43_L0_SEL_MASK 0x00000002U
23814 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
23816 #undef IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL
23817 #undef IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT
23818 #undef IOU_SLCR_MIO_PIN_43_L1_SEL_MASK
23819 #define IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 0x00000000
23820 #define IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 2
23821 #define IOU_SLCR_MIO_PIN_43_L1_SEL_MASK 0x00000004U
23824 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]-
23825 * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s
23826 * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
23828 #undef IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL
23829 #undef IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT
23830 #undef IOU_SLCR_MIO_PIN_43_L2_SEL_MASK
23831 #define IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 0x00000000
23832 #define IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 3
23833 #define IOU_SLCR_MIO_PIN_43_L2_SEL_MASK 0x00000018U
23836 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0=
23837 * gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_p
23838 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
23839 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
23840 * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal)
23841 * 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (
23842 * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
23843 * tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)
23845 #undef IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL
23846 #undef IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT
23847 #undef IOU_SLCR_MIO_PIN_43_L3_SEL_MASK
23848 #define IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 0x00000000
23849 #define IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 5
23850 #define IOU_SLCR_MIO_PIN_43_L3_SEL_MASK 0x000000E0U
23853 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c
23854 * lk- (RX RGMII clock)
23856 #undef IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL
23857 #undef IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT
23858 #undef IOU_SLCR_MIO_PIN_44_L0_SEL_MASK
23859 #define IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 0x00000000
23860 #define IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 1
23861 #define IOU_SLCR_MIO_PIN_44_L0_SEL_MASK 0x00000002U
23864 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
23866 #undef IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL
23867 #undef IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT
23868 #undef IOU_SLCR_MIO_PIN_44_L1_SEL_MASK
23869 #define IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 0x00000000
23870 #define IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 2
23871 #define IOU_SLCR_MIO_PIN_44_L1_SEL_MASK 0x00000004U
23874 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]-
23875 * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s
23876 * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
23878 #undef IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL
23879 #undef IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT
23880 #undef IOU_SLCR_MIO_PIN_44_L2_SEL_MASK
23881 #define IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 0x00000000
23882 #define IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 3
23883 #define IOU_SLCR_MIO_PIN_44_L2_SEL_MASK 0x00000018U
23886 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0=
23887 * gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_p
23888 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
23889 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
23890 * Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4
23891 * = spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in-
23892 * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7=
23895 #undef IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL
23896 #undef IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT
23897 #undef IOU_SLCR_MIO_PIN_44_L3_SEL_MASK
23898 #define IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 0x00000000
23899 #define IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 5
23900 #define IOU_SLCR_MIO_PIN_44_L3_SEL_MASK 0x000000E0U
23903 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
23904 * 0]- (RX RGMII data)
23906 #undef IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL
23907 #undef IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT
23908 #undef IOU_SLCR_MIO_PIN_45_L0_SEL_MASK
23909 #define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 0x00000000
23910 #define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 1
23911 #define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK 0x00000002U
23914 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
23916 #undef IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL
23917 #undef IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT
23918 #undef IOU_SLCR_MIO_PIN_45_L1_SEL_MASK
23919 #define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 0x00000000
23920 #define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 2
23921 #define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK 0x00000004U
23924 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]-
23925 * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s
23926 * d1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
23928 #undef IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL
23929 #undef IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT
23930 #undef IOU_SLCR_MIO_PIN_45_L2_SEL_MASK
23931 #define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 0x00000000
23932 #define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 3
23933 #define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK 0x00000018U
23936 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0=
23937 * gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_ph
23938 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
23939 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
23940 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI M
23941 * aster Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= u
23942 * a1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
23944 #undef IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL
23945 #undef IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT
23946 #undef IOU_SLCR_MIO_PIN_45_L3_SEL_MASK
23947 #define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 0x00000000
23948 #define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 5
23949 #define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK 0x000000E0U
23952 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
23953 * 1]- (RX RGMII data)
23955 #undef IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL
23956 #undef IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT
23957 #undef IOU_SLCR_MIO_PIN_46_L0_SEL_MASK
23958 #define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 0x00000000
23959 #define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 1
23960 #define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK 0x00000002U
23963 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
23965 #undef IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL
23966 #undef IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT
23967 #undef IOU_SLCR_MIO_PIN_46_L1_SEL_MASK
23968 #define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 0x00000000
23969 #define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 2
23970 #define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK 0x00000004U
23973 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]-
23974 * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s
23975 * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
23976 * t[0]- (8-bit Data bus) 3= Not Used
23978 #undef IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL
23979 #undef IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT
23980 #undef IOU_SLCR_MIO_PIN_46_L2_SEL_MASK
23981 #define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 0x00000000
23982 #define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 3
23983 #define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK 0x00000018U
23986 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0=
23987 * gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_ph
23988 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
23989 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
23990 * atch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mast
23991 * er Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_
23992 * rxd- (UART receiver serial input) 7= Not Used
23994 #undef IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL
23995 #undef IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT
23996 #undef IOU_SLCR_MIO_PIN_46_L3_SEL_MASK
23997 #define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 0x00000000
23998 #define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 5
23999 #define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK 0x000000E0U
24002 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
24003 * 2]- (RX RGMII data)
24005 #undef IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL
24006 #undef IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT
24007 #undef IOU_SLCR_MIO_PIN_47_L0_SEL_MASK
24008 #define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 0x00000000
24009 #define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 1
24010 #define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK 0x00000002U
24013 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
24015 #undef IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL
24016 #undef IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT
24017 #undef IOU_SLCR_MIO_PIN_47_L1_SEL_MASK
24018 #define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 0x00000000
24019 #define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 2
24020 #define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK 0x00000004U
24023 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]-
24024 * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s
24025 * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
24026 * t[1]- (8-bit Data bus) 3= Not Used
24028 #undef IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL
24029 #undef IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT
24030 #undef IOU_SLCR_MIO_PIN_47_L2_SEL_MASK
24031 #define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 0x00000000
24032 #define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 3
24033 #define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK 0x00000018U
24036 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0=
24037 * gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_p
24038 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
24039 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
24040 * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Maste
24041 * r Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= tt
24042 * c0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd-
24043 * (UART transmitter serial output) 7= Not Used
24045 #undef IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL
24046 #undef IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT
24047 #undef IOU_SLCR_MIO_PIN_47_L3_SEL_MASK
24048 #define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 0x00000000
24049 #define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 5
24050 #define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK 0x000000E0U
24053 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
24054 * 3]- (RX RGMII data)
24056 #undef IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL
24057 #undef IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT
24058 #undef IOU_SLCR_MIO_PIN_48_L0_SEL_MASK
24059 #define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 0x00000000
24060 #define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 1
24061 #define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK 0x00000002U
24064 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
24066 #undef IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL
24067 #undef IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT
24068 #undef IOU_SLCR_MIO_PIN_48_L1_SEL_MASK
24069 #define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 0x00000000
24070 #define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 2
24071 #define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK 0x00000004U
24074 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]-
24075 * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s
24076 * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
24077 * t[2]- (8-bit Data bus) 3= Not Used
24079 #undef IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL
24080 #undef IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT
24081 #undef IOU_SLCR_MIO_PIN_48_L2_SEL_MASK
24082 #define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 0x00000000
24083 #define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 3
24084 #define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK 0x00000018U
24087 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0=
24088 * gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_p
24089 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
24090 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
24091 * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s
24092 * pi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl
24093 * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Us
24096 #undef IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL
24097 #undef IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT
24098 #undef IOU_SLCR_MIO_PIN_48_L3_SEL_MASK
24099 #define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 0x00000000
24100 #define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 5
24101 #define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK 0x000000E0U
24104 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c
24105 * tl- (RX RGMII control )
24107 #undef IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL
24108 #undef IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT
24109 #undef IOU_SLCR_MIO_PIN_49_L0_SEL_MASK
24110 #define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 0x00000000
24111 #define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 1
24112 #define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK 0x00000002U
24115 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
24117 #undef IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL
24118 #undef IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT
24119 #undef IOU_SLCR_MIO_PIN_49_L1_SEL_MASK
24120 #define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 0x00000000
24121 #define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 2
24122 #define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK 0x00000004U
24125 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow-
24126 * (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd
24127 * 1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
24129 #undef IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL
24130 #undef IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT
24131 #undef IOU_SLCR_MIO_PIN_49_L2_SEL_MASK
24132 #define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 0x00000000
24133 #define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 3
24134 #define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK 0x00000018U
24137 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0=
24138 * gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_ph
24139 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
24140 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
24141 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4
24142 * = spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T
24143 * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
24146 #undef IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL
24147 #undef IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT
24148 #undef IOU_SLCR_MIO_PIN_49_L3_SEL_MASK
24149 #define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 0x00000000
24150 #define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 5
24151 #define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK 0x000000E0U
24154 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk-
24157 #undef IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL
24158 #undef IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT
24159 #undef IOU_SLCR_MIO_PIN_50_L0_SEL_MASK
24160 #define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 0x00000000
24161 #define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 1
24162 #define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK 0x00000002U
24165 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
24167 #undef IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL
24168 #undef IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT
24169 #undef IOU_SLCR_MIO_PIN_50_L1_SEL_MASK
24170 #define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 0x00000000
24171 #define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 2
24172 #define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK 0x00000004U
24175 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca
24176 * rd write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Ind
24177 * icator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
24179 #undef IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL
24180 #undef IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT
24181 #undef IOU_SLCR_MIO_PIN_50_L2_SEL_MASK
24182 #define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 0x00000000
24183 #define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 3
24184 #define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK 0x00000018U
24187 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0=
24188 * gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_ph
24189 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
24190 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
24191 * atch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5=
24192 * ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART rece
24193 * iver serial input) 7= Not Used
24195 #undef IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL
24196 #undef IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT
24197 #undef IOU_SLCR_MIO_PIN_50_L3_SEL_MASK
24198 #define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 0x00000000
24199 #define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 5
24200 #define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK 0x000000E0U
24203 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk-
24206 #undef IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL
24207 #undef IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT
24208 #undef IOU_SLCR_MIO_PIN_51_L0_SEL_MASK
24209 #define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 0x00000000
24210 #define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 1
24211 #define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK 0x00000002U
24214 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
24216 #undef IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL
24217 #undef IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT
24218 #undef IOU_SLCR_MIO_PIN_51_L1_SEL_MASK
24219 #define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 0x00000000
24220 #define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 2
24221 #define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK 0x00000004U
24224 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdi
24225 * o1_clk_out- (SDSDIO clock) 3= Not Used
24227 #undef IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL
24228 #undef IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT
24229 #undef IOU_SLCR_MIO_PIN_51_L2_SEL_MASK
24230 #define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 0x00000000
24231 #define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 3
24232 #define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK 0x00000018U
24235 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0=
24236 * gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_p
24237 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
24238 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
24239 * (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Dat
24240 * a) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wa
24241 * ve_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
24242 * serial output) 7= Not Used
24244 #undef IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL
24245 #undef IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT
24246 #undef IOU_SLCR_MIO_PIN_51_L3_SEL_MASK
24247 #define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 0x00000000
24248 #define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 5
24249 #define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 0x000000E0U
24252 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_
24253 * clk- (TX RGMII clock)
24255 #undef IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL
24256 #undef IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT
24257 #undef IOU_SLCR_MIO_PIN_52_L0_SEL_MASK
24258 #define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 0x00000000
24259 #define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 1
24260 #define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 0x00000002U
24263 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i
24266 #undef IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL
24267 #undef IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT
24268 #undef IOU_SLCR_MIO_PIN_52_L1_SEL_MASK
24269 #define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 0x00000000
24270 #define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 2
24271 #define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 0x00000004U
24274 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
24277 #undef IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL
24278 #undef IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT
24279 #undef IOU_SLCR_MIO_PIN_52_L2_SEL_MASK
24280 #define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 0x00000000
24281 #define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 3
24282 #define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 0x00000018U
24285 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g
24286 * pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy
24287 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
24288 * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
24289 * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc
24290 * lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out
24291 * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c
24292 * lk- (Trace Port Clock)
24294 #undef IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL
24295 #undef IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT
24296 #undef IOU_SLCR_MIO_PIN_52_L3_SEL_MASK
24297 #define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 0x00000000
24298 #define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 5
24299 #define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 0x000000E0U
24302 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
24303 * [0]- (TX RGMII data)
24305 #undef IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL
24306 #undef IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT
24307 #undef IOU_SLCR_MIO_PIN_53_L0_SEL_MASK
24308 #define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 0x00000000
24309 #define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 1
24310 #define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 0x00000002U
24313 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir-
24314 * (Data bus direction control)
24316 #undef IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL
24317 #undef IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT
24318 #undef IOU_SLCR_MIO_PIN_53_L1_SEL_MASK
24319 #define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 0x00000000
24320 #define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 2
24321 #define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 0x00000004U
24324 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
24327 #undef IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL
24328 #undef IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT
24329 #undef IOU_SLCR_MIO_PIN_53_L2_SEL_MASK
24330 #define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 0x00000000
24331 #define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 3
24332 #define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 0x00000018U
24335 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g
24336 * pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_
24337 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
24338 * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
24339 * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou
24340 * tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART
24341 * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
24344 #undef IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL
24345 #undef IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT
24346 #undef IOU_SLCR_MIO_PIN_53_L3_SEL_MASK
24347 #define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 0x00000000
24348 #define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 5
24349 #define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 0x000000E0U
24352 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
24353 * [1]- (TX RGMII data)
24355 #undef IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL
24356 #undef IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT
24357 #undef IOU_SLCR_MIO_PIN_54_L0_SEL_MASK
24358 #define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 0x00000000
24359 #define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 1
24360 #define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 0x00000002U
24363 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
24364 * ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data
24367 #undef IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL
24368 #undef IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT
24369 #undef IOU_SLCR_MIO_PIN_54_L1_SEL_MASK
24370 #define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 0x00000000
24371 #define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 2
24372 #define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 0x00000004U
24375 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
24378 #undef IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL
24379 #undef IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT
24380 #undef IOU_SLCR_MIO_PIN_54_L2_SEL_MASK
24381 #define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 0x00000000
24382 #define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 3
24383 #define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 0x00000018U
24386 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g
24387 * pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_
24388 * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
24389 * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG
24390 * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I
24391 * nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se
24392 * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
24394 #undef IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL
24395 #undef IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT
24396 #undef IOU_SLCR_MIO_PIN_54_L3_SEL_MASK
24397 #define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 0x00000000
24398 #define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 5
24399 #define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 0x000000E0U
24402 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
24403 * [2]- (TX RGMII data)
24405 #undef IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL
24406 #undef IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT
24407 #undef IOU_SLCR_MIO_PIN_55_L0_SEL_MASK
24408 #define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 0x00000000
24409 #define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 1
24410 #define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 0x00000002U
24413 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt-
24414 * (Data flow control signal from the PHY)
24416 #undef IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL
24417 #undef IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT
24418 #undef IOU_SLCR_MIO_PIN_55_L1_SEL_MASK
24419 #define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 0x00000000
24420 #define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 2
24421 #define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 0x00000004U
24424 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
24427 #undef IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL
24428 #undef IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT
24429 #undef IOU_SLCR_MIO_PIN_55_L2_SEL_MASK
24430 #define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 0x00000000
24431 #define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 3
24432 #define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 0x00000018U
24435 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g
24436 * pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy
24437 * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
24438 * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
24439 * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output
24440 * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out-
24441 * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
24442 * output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
24444 #undef IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL
24445 #undef IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT
24446 #undef IOU_SLCR_MIO_PIN_55_L3_SEL_MASK
24447 #define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 0x00000000
24448 #define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 5
24449 #define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 0x000000E0U
24452 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
24453 * [3]- (TX RGMII data)
24455 #undef IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL
24456 #undef IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT
24457 #undef IOU_SLCR_MIO_PIN_56_L0_SEL_MASK
24458 #define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 0x00000000
24459 #define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 1
24460 #define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 0x00000002U
24463 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
24464 * ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data
24467 #undef IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL
24468 #undef IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT
24469 #undef IOU_SLCR_MIO_PIN_56_L1_SEL_MASK
24470 #define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 0x00000000
24471 #define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 2
24472 #define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK 0x00000004U
24475 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
24478 #undef IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL
24479 #undef IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT
24480 #undef IOU_SLCR_MIO_PIN_56_L2_SEL_MASK
24481 #define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 0x00000000
24482 #define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 3
24483 #define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK 0x00000018U
24486 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= g
24487 * pio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy
24488 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
24489 * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa
24490 * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi
24491 * 0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cloc
24492 * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O
24493 * utput, tracedq[2]- (Trace Port Databus)
24495 #undef IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL
24496 #undef IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT
24497 #undef IOU_SLCR_MIO_PIN_56_L3_SEL_MASK
24498 #define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 0x00000000
24499 #define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 5
24500 #define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK 0x000000E0U
24503 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_
24504 * ctl- (TX RGMII control)
24506 #undef IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL
24507 #undef IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT
24508 #undef IOU_SLCR_MIO_PIN_57_L0_SEL_MASK
24509 #define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 0x00000000
24510 #define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 1
24511 #define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK 0x00000002U
24514 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
24515 * ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data
24518 #undef IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL
24519 #undef IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT
24520 #undef IOU_SLCR_MIO_PIN_57_L1_SEL_MASK
24521 #define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 0x00000000
24522 #define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 2
24523 #define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK 0x00000004U
24526 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
24529 #undef IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL
24530 #undef IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT
24531 #undef IOU_SLCR_MIO_PIN_57_L2_SEL_MASK
24532 #define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 0x00000000
24533 #define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 3
24534 #define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK 0x00000018U
24537 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= g
24538 * pio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_
24539 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
24540 * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W
24541 * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4=
24542 * spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC
24543 * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7=
24544 * trace, Output, tracedq[3]- (Trace Port Databus)
24546 #undef IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL
24547 #undef IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT
24548 #undef IOU_SLCR_MIO_PIN_57_L3_SEL_MASK
24549 #define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 0x00000000
24550 #define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 5
24551 #define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 0x000000E0U
24554 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c
24555 * lk- (RX RGMII clock)
24557 #undef IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL
24558 #undef IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT
24559 #undef IOU_SLCR_MIO_PIN_58_L0_SEL_MASK
24560 #define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 0x00000000
24561 #define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 1
24562 #define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 0x00000002U
24565 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp-
24566 * (Asserted to end or interrupt transfers)
24568 #undef IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL
24569 #undef IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT
24570 #undef IOU_SLCR_MIO_PIN_58_L1_SEL_MASK
24571 #define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 0x00000000
24572 #define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 2
24573 #define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 0x00000004U
24576 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
24579 #undef IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL
24580 #undef IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT
24581 #undef IOU_SLCR_MIO_PIN_58_L2_SEL_MASK
24582 #define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 0x00000000
24583 #define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 3
24584 #define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 0x00000018U
24587 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g
24588 * pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_
24589 * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
24590 * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
24591 * TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl
24592 * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu
24593 * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (
24594 * Trace Port Databus)
24596 #undef IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL
24597 #undef IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT
24598 #undef IOU_SLCR_MIO_PIN_58_L3_SEL_MASK
24599 #define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 0x00000000
24600 #define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 5
24601 #define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 0x000000E0U
24604 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
24605 * 0]- (RX RGMII data)
24607 #undef IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL
24608 #undef IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT
24609 #undef IOU_SLCR_MIO_PIN_59_L0_SEL_MASK
24610 #define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 0x00000000
24611 #define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 1
24612 #define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 0x00000002U
24615 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
24616 * ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data
24619 #undef IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL
24620 #undef IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT
24621 #undef IOU_SLCR_MIO_PIN_59_L1_SEL_MASK
24622 #define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 0x00000000
24623 #define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 2
24624 #define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 0x00000004U
24627 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
24630 #undef IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL
24631 #undef IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT
24632 #undef IOU_SLCR_MIO_PIN_59_L2_SEL_MASK
24633 #define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 0x00000000
24634 #define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 3
24635 #define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 0x00000018U
24638 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g
24639 * pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy
24640 * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
24641 * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
24642 * TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O
24643 * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR
24644 * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D
24647 #undef IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL
24648 #undef IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT
24649 #undef IOU_SLCR_MIO_PIN_59_L3_SEL_MASK
24650 #define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 0x00000000
24651 #define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 5
24652 #define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 0x000000E0U
24655 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
24656 * 1]- (RX RGMII data)
24658 #undef IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL
24659 #undef IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT
24660 #undef IOU_SLCR_MIO_PIN_60_L0_SEL_MASK
24661 #define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 0x00000000
24662 #define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 1
24663 #define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 0x00000002U
24666 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
24667 * ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data
24670 #undef IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL
24671 #undef IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT
24672 #undef IOU_SLCR_MIO_PIN_60_L1_SEL_MASK
24673 #define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 0x00000000
24674 #define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 2
24675 #define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 0x00000004U
24678 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
24681 #undef IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL
24682 #undef IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT
24683 #undef IOU_SLCR_MIO_PIN_60_L2_SEL_MASK
24684 #define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 0x00000000
24685 #define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 3
24686 #define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 0x00000018U
24689 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g
24690 * pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy
24691 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
24692 * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA
24693 * G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1,
24694 * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt
24695 * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
24697 #undef IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL
24698 #undef IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT
24699 #undef IOU_SLCR_MIO_PIN_60_L3_SEL_MASK
24700 #define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 0x00000000
24701 #define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 5
24702 #define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 0x000000E0U
24705 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
24706 * 2]- (RX RGMII data)
24708 #undef IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL
24709 #undef IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT
24710 #undef IOU_SLCR_MIO_PIN_61_L0_SEL_MASK
24711 #define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 0x00000000
24712 #define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 1
24713 #define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 0x00000002U
24716 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
24717 * ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data
24720 #undef IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL
24721 #undef IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT
24722 #undef IOU_SLCR_MIO_PIN_61_L1_SEL_MASK
24723 #define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 0x00000000
24724 #define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 2
24725 #define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK 0x00000004U
24728 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
24731 #undef IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL
24732 #undef IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT
24733 #undef IOU_SLCR_MIO_PIN_61_L2_SEL_MASK
24734 #define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 0x00000000
24735 #define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 3
24736 #define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK 0x00000018U
24739 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= g
24740 * pio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_
24741 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
24742 * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
24743 * TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output,
24744 * spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out-
24745 * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input
24746 * ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
24748 #undef IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL
24749 #undef IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT
24750 #undef IOU_SLCR_MIO_PIN_61_L3_SEL_MASK
24751 #define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 0x00000000
24752 #define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 5
24753 #define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK 0x000000E0U
24756 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
24757 * 3]- (RX RGMII data)
24759 #undef IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL
24760 #undef IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT
24761 #undef IOU_SLCR_MIO_PIN_62_L0_SEL_MASK
24762 #define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 0x00000000
24763 #define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 1
24764 #define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK 0x00000002U
24767 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
24768 * ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data
24771 #undef IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL
24772 #undef IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT
24773 #undef IOU_SLCR_MIO_PIN_62_L1_SEL_MASK
24774 #define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 0x00000000
24775 #define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 2
24776 #define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK 0x00000004U
24779 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
24782 #undef IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL
24783 #undef IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT
24784 #undef IOU_SLCR_MIO_PIN_62_L2_SEL_MASK
24785 #define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 0x00000000
24786 #define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 3
24787 #define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK 0x00000018U
24790 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0=
24791 * gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_ph
24792 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
24793 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
24794 * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp
24795 * i1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clo
24796 * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu
24797 * t, tracedq[8]- (Trace Port Databus)
24799 #undef IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL
24800 #undef IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT
24801 #undef IOU_SLCR_MIO_PIN_62_L3_SEL_MASK
24802 #define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 0x00000000
24803 #define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 5
24804 #define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK 0x000000E0U
24807 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c
24808 * tl- (RX RGMII control )
24810 #undef IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL
24811 #undef IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT
24812 #undef IOU_SLCR_MIO_PIN_63_L0_SEL_MASK
24813 #define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 0x00000000
24814 #define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 1
24815 #define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK 0x00000002U
24818 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
24819 * ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data
24822 #undef IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL
24823 #undef IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT
24824 #undef IOU_SLCR_MIO_PIN_63_L1_SEL_MASK
24825 #define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 0x00000000
24826 #define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 2
24827 #define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK 0x00000004U
24830 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
24833 #undef IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL
24834 #undef IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT
24835 #undef IOU_SLCR_MIO_PIN_63_L2_SEL_MASK
24836 #define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 0x00000000
24837 #define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 3
24838 #define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK 0x00000018U
24841 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0=
24842 * gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_p
24843 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
24844 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
24845 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal)
24846 * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (
24847 * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
24848 * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
24850 #undef IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL
24851 #undef IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT
24852 #undef IOU_SLCR_MIO_PIN_63_L3_SEL_MASK
24853 #define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 0x00000000
24854 #define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 5
24855 #define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK 0x000000E0U
24858 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_
24859 * clk- (TX RGMII clock)
24861 #undef IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL
24862 #undef IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT
24863 #undef IOU_SLCR_MIO_PIN_64_L0_SEL_MASK
24864 #define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 0x00000000
24865 #define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 1
24866 #define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK 0x00000002U
24869 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_i
24872 #undef IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL
24873 #undef IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT
24874 #undef IOU_SLCR_MIO_PIN_64_L1_SEL_MASK
24875 #define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 0x00000000
24876 #define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 2
24877 #define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK 0x00000004U
24880 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out-
24881 * (SDSDIO clock) 2= Not Used 3= Not Used
24883 #undef IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL
24884 #undef IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT
24885 #undef IOU_SLCR_MIO_PIN_64_L2_SEL_MASK
24886 #define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 0x00000000
24887 #define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 3
24888 #define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK 0x00000018U
24891 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0=
24892 * gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_p
24893 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
24894 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
24895 * Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4
24896 * = spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in-
24897 * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7=
24898 * trace, Output, tracedq[10]- (Trace Port Databus)
24900 #undef IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL
24901 #undef IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT
24902 #undef IOU_SLCR_MIO_PIN_64_L3_SEL_MASK
24903 #define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 0x00000000
24904 #define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 5
24905 #define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK 0x000000E0U
24908 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
24909 * [0]- (TX RGMII data)
24911 #undef IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL
24912 #undef IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT
24913 #undef IOU_SLCR_MIO_PIN_65_L0_SEL_MASK
24914 #define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 0x00000000
24915 #define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 1
24916 #define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK 0x00000002U
24919 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir-
24920 * (Data bus direction control)
24922 #undef IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL
24923 #undef IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT
24924 #undef IOU_SLCR_MIO_PIN_65_L1_SEL_MASK
24925 #define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 0x00000000
24926 #define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 2
24927 #define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK 0x00000004U
24930 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD
24931 * card detect from connector) 2= Not Used 3= Not Used
24933 #undef IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL
24934 #undef IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT
24935 #undef IOU_SLCR_MIO_PIN_65_L2_SEL_MASK
24936 #define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 0x00000000
24937 #define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 3
24938 #define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK 0x00000018U
24941 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0=
24942 * gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_ph
24943 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
24944 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
24945 * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI M
24946 * aster Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= u
24947 * a1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace
24948 * dq[11]- (Trace Port Databus)
24950 #undef IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL
24951 #undef IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT
24952 #undef IOU_SLCR_MIO_PIN_65_L3_SEL_MASK
24953 #define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 0x00000000
24954 #define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 5
24955 #define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK 0x000000E0U
24958 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
24959 * [1]- (TX RGMII data)
24961 #undef IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL
24962 #undef IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT
24963 #undef IOU_SLCR_MIO_PIN_66_L0_SEL_MASK
24964 #define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 0x00000000
24965 #define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 1
24966 #define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK 0x00000002U
24969 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
24970 * ta[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data
24973 #undef IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL
24974 #undef IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT
24975 #undef IOU_SLCR_MIO_PIN_66_L1_SEL_MASK
24976 #define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 0x00000000
24977 #define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 2
24978 #define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK 0x00000004U
24981 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com
24982 * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not
24985 #undef IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL
24986 #undef IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT
24987 #undef IOU_SLCR_MIO_PIN_66_L2_SEL_MASK
24988 #define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 0x00000000
24989 #define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 3
24990 #define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK 0x00000018U
24993 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0=
24994 * gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_ph
24995 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
24996 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
24997 * atch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Mast
24998 * er Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_
24999 * rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
25002 #undef IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL
25003 #undef IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT
25004 #undef IOU_SLCR_MIO_PIN_66_L3_SEL_MASK
25005 #define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 0x00000000
25006 #define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 5
25007 #define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK 0x000000E0U
25010 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
25011 * [2]- (TX RGMII data)
25013 #undef IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL
25014 #undef IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT
25015 #undef IOU_SLCR_MIO_PIN_67_L0_SEL_MASK
25016 #define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 0x00000000
25017 #define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 1
25018 #define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK 0x00000002U
25021 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt-
25022 * (Data flow control signal from the PHY)
25024 #undef IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL
25025 #undef IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT
25026 #undef IOU_SLCR_MIO_PIN_67_L1_SEL_MASK
25027 #define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 0x00000000
25028 #define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 2
25029 #define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK 0x00000004U
25032 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]-
25033 * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= N
25034 * ot Used 3= Not Used
25036 #undef IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL
25037 #undef IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT
25038 #undef IOU_SLCR_MIO_PIN_67_L2_SEL_MASK
25039 #define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 0x00000000
25040 #define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 3
25041 #define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK 0x00000018U
25044 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0=
25045 * gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_p
25046 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
25047 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
25048 * (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Maste
25049 * r Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= tt
25050 * c2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd-
25051 * (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace
25054 #undef IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL
25055 #undef IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT
25056 #undef IOU_SLCR_MIO_PIN_67_L3_SEL_MASK
25057 #define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 0x00000000
25058 #define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 5
25059 #define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK 0x000000E0U
25062 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
25063 * [3]- (TX RGMII data)
25065 #undef IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL
25066 #undef IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT
25067 #undef IOU_SLCR_MIO_PIN_68_L0_SEL_MASK
25068 #define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 0x00000000
25069 #define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 1
25070 #define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK 0x00000002U
25073 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
25074 * ta[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data
25077 #undef IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL
25078 #undef IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT
25079 #undef IOU_SLCR_MIO_PIN_68_L1_SEL_MASK
25080 #define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 0x00000000
25081 #define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 2
25082 #define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK 0x00000004U
25085 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]-
25086 * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= N
25087 * ot Used 3= Not Used
25089 #undef IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL
25090 #undef IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT
25091 #undef IOU_SLCR_MIO_PIN_68_L2_SEL_MASK
25092 #define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 0x00000000
25093 #define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 3
25094 #define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK 0x00000018U
25097 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0=
25098 * gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_p
25099 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
25100 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
25101 * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s
25102 * pi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl
25103 * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
25104 * Output, tracedq[14]- (Trace Port Databus)
25106 #undef IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL
25107 #undef IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT
25108 #undef IOU_SLCR_MIO_PIN_68_L3_SEL_MASK
25109 #define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 0x00000000
25110 #define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 5
25111 #define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK 0x000000E0U
25114 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_
25115 * ctl- (TX RGMII control)
25117 #undef IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL
25118 #undef IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT
25119 #undef IOU_SLCR_MIO_PIN_69_L0_SEL_MASK
25120 #define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 0x00000000
25121 #define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 1
25122 #define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK 0x00000002U
25125 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
25126 * ta[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data
25129 #undef IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL
25130 #undef IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT
25131 #undef IOU_SLCR_MIO_PIN_69_L1_SEL_MASK
25132 #define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 0x00000000
25133 #define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 2
25134 #define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK 0x00000004U
25137 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]-
25138 * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s
25139 * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
25141 #undef IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL
25142 #undef IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT
25143 #undef IOU_SLCR_MIO_PIN_69_L2_SEL_MASK
25144 #define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 0x00000000
25145 #define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 3
25146 #define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK 0x00000018U
25149 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0=
25150 * gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_ph
25151 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
25152 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
25153 * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4
25154 * = spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T
25155 * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
25156 * 7= trace, Output, tracedq[15]- (Trace Port Databus)
25158 #undef IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL
25159 #undef IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT
25160 #undef IOU_SLCR_MIO_PIN_69_L3_SEL_MASK
25161 #define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 0x00000000
25162 #define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 5
25163 #define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK 0x000000E0U
25166 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c
25167 * lk- (RX RGMII clock)
25169 #undef IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL
25170 #undef IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT
25171 #undef IOU_SLCR_MIO_PIN_70_L0_SEL_MASK
25172 #define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 0x00000000
25173 #define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 1
25174 #define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK 0x00000002U
25177 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp-
25178 * (Asserted to end or interrupt transfers)
25180 #undef IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL
25181 #undef IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT
25182 #undef IOU_SLCR_MIO_PIN_70_L1_SEL_MASK
25183 #define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 0x00000000
25184 #define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 2
25185 #define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK 0x00000004U
25188 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]-
25189 * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s
25190 * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
25192 #undef IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL
25193 #undef IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT
25194 #undef IOU_SLCR_MIO_PIN_70_L2_SEL_MASK
25195 #define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 0x00000000
25196 #define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 3
25197 #define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK 0x00000018U
25200 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0=
25201 * gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_ph
25202 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
25203 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
25204 * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4=
25205 * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (
25206 * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U
25209 #undef IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL
25210 #undef IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT
25211 #undef IOU_SLCR_MIO_PIN_70_L3_SEL_MASK
25212 #define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 0x00000000
25213 #define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 5
25214 #define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK 0x000000E0U
25217 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
25218 * 0]- (RX RGMII data)
25220 #undef IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL
25221 #undef IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT
25222 #undef IOU_SLCR_MIO_PIN_71_L0_SEL_MASK
25223 #define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 0x00000000
25224 #define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 1
25225 #define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK 0x00000002U
25228 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
25229 * ta[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data
25232 #undef IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL
25233 #undef IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT
25234 #undef IOU_SLCR_MIO_PIN_71_L1_SEL_MASK
25235 #define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 0x00000000
25236 #define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 2
25237 #define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK 0x00000004U
25240 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]-
25241 * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s
25242 * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
25243 * t[0]- (8-bit Data bus) 3= Not Used
25245 #undef IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL
25246 #undef IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT
25247 #undef IOU_SLCR_MIO_PIN_71_L2_SEL_MASK
25248 #define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 0x00000000
25249 #define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 3
25250 #define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK 0x00000018U
25253 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0=
25254 * gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_p
25255 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
25256 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
25257 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI
25258 * Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6=
25259 * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
25261 #undef IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL
25262 #undef IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT
25263 #undef IOU_SLCR_MIO_PIN_71_L3_SEL_MASK
25264 #define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 0x00000000
25265 #define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 5
25266 #define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK 0x000000E0U
25269 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
25270 * 1]- (RX RGMII data)
25272 #undef IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL
25273 #undef IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT
25274 #undef IOU_SLCR_MIO_PIN_72_L0_SEL_MASK
25275 #define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 0x00000000
25276 #define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 1
25277 #define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK 0x00000002U
25280 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
25281 * ta[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data
25284 #undef IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL
25285 #undef IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT
25286 #undef IOU_SLCR_MIO_PIN_72_L1_SEL_MASK
25287 #define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 0x00000000
25288 #define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 2
25289 #define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK 0x00000004U
25292 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]-
25293 * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s
25294 * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
25295 * t[1]- (8-bit Data bus) 3= Not Used
25297 #undef IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL
25298 #undef IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT
25299 #undef IOU_SLCR_MIO_PIN_72_L2_SEL_MASK
25300 #define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 0x00000000
25301 #define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 3
25302 #define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK 0x00000018U
25305 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0=
25306 * gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_p
25307 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
25308 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
25309 * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas
25310 * ter Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter seri
25311 * al output) 7= Not Used
25313 #undef IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL
25314 #undef IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT
25315 #undef IOU_SLCR_MIO_PIN_72_L3_SEL_MASK
25316 #define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 0x00000000
25317 #define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 5
25318 #define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK 0x000000E0U
25321 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
25322 * 2]- (RX RGMII data)
25324 #undef IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL
25325 #undef IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT
25326 #undef IOU_SLCR_MIO_PIN_73_L0_SEL_MASK
25327 #define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 0x00000000
25328 #define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 1
25329 #define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK 0x00000002U
25332 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
25333 * ta[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data
25336 #undef IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL
25337 #undef IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT
25338 #undef IOU_SLCR_MIO_PIN_73_L1_SEL_MASK
25339 #define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 0x00000000
25340 #define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 2
25341 #define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK 0x00000004U
25344 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]-
25345 * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s
25346 * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
25347 * t[2]- (8-bit Data bus) 3= Not Used
25349 #undef IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL
25350 #undef IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT
25351 #undef IOU_SLCR_MIO_PIN_73_L2_SEL_MASK
25352 #define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 0x00000000
25353 #define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 3
25354 #define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK 0x00000018U
25357 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0=
25358 * gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_ph
25359 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
25360 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
25361 * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master
25362 * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not
25363 * Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
25365 #undef IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL
25366 #undef IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT
25367 #undef IOU_SLCR_MIO_PIN_73_L3_SEL_MASK
25368 #define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 0x00000000
25369 #define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 5
25370 #define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK 0x000000E0U
25373 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
25374 * 3]- (RX RGMII data)
25376 #undef IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL
25377 #undef IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT
25378 #undef IOU_SLCR_MIO_PIN_74_L0_SEL_MASK
25379 #define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 0x00000000
25380 #define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 1
25381 #define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK 0x00000002U
25384 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
25385 * ta[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data
25388 #undef IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL
25389 #undef IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT
25390 #undef IOU_SLCR_MIO_PIN_74_L1_SEL_MASK
25391 #define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 0x00000000
25392 #define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 2
25393 #define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK 0x00000004U
25396 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]-
25397 * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s
25398 * d1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
25399 * t[3]- (8-bit Data bus) 3= Not Used
25401 #undef IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL
25402 #undef IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT
25403 #undef IOU_SLCR_MIO_PIN_74_L2_SEL_MASK
25404 #define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 0x00000000
25405 #define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 3
25406 #define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK 0x00000018U
25409 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0=
25410 * gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_ph
25411 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
25412 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
25413 * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp
25414 * i1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (
25415 * UART receiver serial input) 7= Not Used
25417 #undef IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL
25418 #undef IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT
25419 #undef IOU_SLCR_MIO_PIN_74_L3_SEL_MASK
25420 #define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 0x00000000
25421 #define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 5
25422 #define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK 0x000000E0U
25425 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c
25426 * tl- (RX RGMII control )
25428 #undef IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL
25429 #undef IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT
25430 #undef IOU_SLCR_MIO_PIN_75_L0_SEL_MASK
25431 #define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 0x00000000
25432 #define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 1
25433 #define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK 0x00000002U
25436 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
25437 * ta[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data
25440 #undef IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL
25441 #undef IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT
25442 #undef IOU_SLCR_MIO_PIN_75_L1_SEL_MASK
25443 #define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 0x00000000
25444 #define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 2
25445 #define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK 0x00000004U
25448 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow-
25449 * (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1
25450 * , Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
25452 #undef IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL
25453 #undef IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT
25454 #undef IOU_SLCR_MIO_PIN_75_L2_SEL_MASK
25455 #define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 0x00000000
25456 #define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 3
25457 #define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK 0x00000018U
25460 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0=
25461 * gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_p
25462 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
25463 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
25464 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal)
25465 * 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_t
25466 * xd- (UART transmitter serial output) 7= Not Used
25468 #undef IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL
25469 #undef IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT
25470 #undef IOU_SLCR_MIO_PIN_75_L3_SEL_MASK
25471 #define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 0x00000000
25472 #define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 5
25473 #define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK 0x000000E0U
25476 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
25478 #undef IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL
25479 #undef IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT
25480 #undef IOU_SLCR_MIO_PIN_76_L0_SEL_MASK
25481 #define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 0x00000000
25482 #define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 1
25483 #define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK 0x00000002U
25486 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
25488 #undef IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL
25489 #undef IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT
25490 #undef IOU_SLCR_MIO_PIN_76_L1_SEL_MASK
25491 #define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 0x00000000
25492 #define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 2
25493 #define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK 0x00000004U
25496 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca
25497 * rd write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO
25498 * clock) 3= Not Used
25500 #undef IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL
25501 #undef IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT
25502 #undef IOU_SLCR_MIO_PIN_76_L2_SEL_MASK
25503 #define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 0x00000000
25504 #define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 3
25505 #define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK 0x00000018U
25508 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0=
25509 * gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_p
25510 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
25511 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDI
25512 * O Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2
25513 * _mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used
25515 #undef IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL
25516 #undef IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT
25517 #undef IOU_SLCR_MIO_PIN_76_L3_SEL_MASK
25518 #define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 0x00000000
25519 #define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 5
25520 #define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK 0x000000E0U
25523 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
25525 #undef IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL
25526 #undef IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT
25527 #undef IOU_SLCR_MIO_PIN_77_L0_SEL_MASK
25528 #define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 0x00000000
25529 #define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 1
25530 #define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK 0x00000002U
25533 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
25535 #undef IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL
25536 #undef IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT
25537 #undef IOU_SLCR_MIO_PIN_77_L1_SEL_MASK
25538 #define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 0x00000000
25539 #define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 2
25540 #define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK 0x00000004U
25543 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio
25544 * 1_cd_n- (SD card detect from connector) 3= Not Used
25546 #undef IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL
25547 #undef IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT
25548 #undef IOU_SLCR_MIO_PIN_77_L2_SEL_MASK
25549 #define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 0x00000000
25550 #define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 3
25551 #define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK 0x00000018U
25554 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0=
25555 * gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_ph
25556 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
25557 * c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (M
25558 * DIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input,
25559 * gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5
25560 * = mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_ou
25561 * t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Outp
25562 * ut, gem3_mdio_out- (MDIO Data) 7= Not Used
25564 #undef IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL
25565 #undef IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT
25566 #undef IOU_SLCR_MIO_PIN_77_L3_SEL_MASK
25567 #define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 0x00000000
25568 #define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 5
25569 #define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK 0x000000E0U
25572 * Master Tri-state Enable for pin 0, active high
25574 #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL
25575 #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT
25576 #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK
25577 #define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 0xFFFFFFFF
25578 #define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 0
25579 #define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 0x00000001U
25582 * Master Tri-state Enable for pin 1, active high
25584 #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL
25585 #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT
25586 #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK
25587 #define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 0xFFFFFFFF
25588 #define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 1
25589 #define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 0x00000002U
25592 * Master Tri-state Enable for pin 2, active high
25594 #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL
25595 #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT
25596 #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK
25597 #define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 0xFFFFFFFF
25598 #define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 2
25599 #define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 0x00000004U
25602 * Master Tri-state Enable for pin 3, active high
25604 #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL
25605 #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT
25606 #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK
25607 #define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 0xFFFFFFFF
25608 #define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 3
25609 #define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 0x00000008U
25612 * Master Tri-state Enable for pin 4, active high
25614 #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL
25615 #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT
25616 #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK
25617 #define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 0xFFFFFFFF
25618 #define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 4
25619 #define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 0x00000010U
25622 * Master Tri-state Enable for pin 5, active high
25624 #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL
25625 #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT
25626 #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK
25627 #define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 0xFFFFFFFF
25628 #define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 5
25629 #define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 0x00000020U
25632 * Master Tri-state Enable for pin 6, active high
25634 #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL
25635 #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT
25636 #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK
25637 #define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 0xFFFFFFFF
25638 #define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 6
25639 #define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 0x00000040U
25642 * Master Tri-state Enable for pin 7, active high
25644 #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL
25645 #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT
25646 #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK
25647 #define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 0xFFFFFFFF
25648 #define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 7
25649 #define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 0x00000080U
25652 * Master Tri-state Enable for pin 8, active high
25654 #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL
25655 #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT
25656 #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK
25657 #define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 0xFFFFFFFF
25658 #define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 8
25659 #define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 0x00000100U
25662 * Master Tri-state Enable for pin 9, active high
25664 #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL
25665 #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT
25666 #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK
25667 #define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 0xFFFFFFFF
25668 #define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 9
25669 #define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 0x00000200U
25672 * Master Tri-state Enable for pin 10, active high
25674 #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL
25675 #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT
25676 #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK
25677 #define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 0xFFFFFFFF
25678 #define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 10
25679 #define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 0x00000400U
25682 * Master Tri-state Enable for pin 11, active high
25684 #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL
25685 #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT
25686 #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK
25687 #define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 0xFFFFFFFF
25688 #define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 11
25689 #define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 0x00000800U
25692 * Master Tri-state Enable for pin 12, active high
25694 #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL
25695 #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT
25696 #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK
25697 #define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 0xFFFFFFFF
25698 #define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 12
25699 #define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 0x00001000U
25702 * Master Tri-state Enable for pin 13, active high
25704 #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL
25705 #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT
25706 #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK
25707 #define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 0xFFFFFFFF
25708 #define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 13
25709 #define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 0x00002000U
25712 * Master Tri-state Enable for pin 14, active high
25714 #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL
25715 #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT
25716 #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK
25717 #define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 0xFFFFFFFF
25718 #define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 14
25719 #define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 0x00004000U
25722 * Master Tri-state Enable for pin 15, active high
25724 #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL
25725 #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT
25726 #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK
25727 #define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 0xFFFFFFFF
25728 #define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 15
25729 #define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 0x00008000U
25732 * Master Tri-state Enable for pin 16, active high
25734 #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL
25735 #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT
25736 #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK
25737 #define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 0xFFFFFFFF
25738 #define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 16
25739 #define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 0x00010000U
25742 * Master Tri-state Enable for pin 17, active high
25744 #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL
25745 #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT
25746 #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK
25747 #define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 0xFFFFFFFF
25748 #define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 17
25749 #define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 0x00020000U
25752 * Master Tri-state Enable for pin 18, active high
25754 #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL
25755 #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT
25756 #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK
25757 #define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 0xFFFFFFFF
25758 #define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 18
25759 #define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 0x00040000U
25762 * Master Tri-state Enable for pin 19, active high
25764 #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL
25765 #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT
25766 #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK
25767 #define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 0xFFFFFFFF
25768 #define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 19
25769 #define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 0x00080000U
25772 * Master Tri-state Enable for pin 20, active high
25774 #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL
25775 #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT
25776 #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK
25777 #define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 0xFFFFFFFF
25778 #define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 20
25779 #define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 0x00100000U
25782 * Master Tri-state Enable for pin 21, active high
25784 #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL
25785 #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT
25786 #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK
25787 #define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 0xFFFFFFFF
25788 #define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 21
25789 #define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 0x00200000U
25792 * Master Tri-state Enable for pin 22, active high
25794 #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL
25795 #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT
25796 #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK
25797 #define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 0xFFFFFFFF
25798 #define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 22
25799 #define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 0x00400000U
25802 * Master Tri-state Enable for pin 23, active high
25804 #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL
25805 #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT
25806 #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK
25807 #define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 0xFFFFFFFF
25808 #define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 23
25809 #define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 0x00800000U
25812 * Master Tri-state Enable for pin 24, active high
25814 #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL
25815 #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT
25816 #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK
25817 #define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 0xFFFFFFFF
25818 #define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 24
25819 #define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 0x01000000U
25822 * Master Tri-state Enable for pin 25, active high
25824 #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL
25825 #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT
25826 #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK
25827 #define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 0xFFFFFFFF
25828 #define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 25
25829 #define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 0x02000000U
25832 * Master Tri-state Enable for pin 26, active high
25834 #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL
25835 #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT
25836 #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK
25837 #define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 0xFFFFFFFF
25838 #define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 26
25839 #define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 0x04000000U
25842 * Master Tri-state Enable for pin 27, active high
25844 #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL
25845 #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT
25846 #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK
25847 #define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 0xFFFFFFFF
25848 #define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 27
25849 #define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 0x08000000U
25852 * Master Tri-state Enable for pin 28, active high
25854 #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL
25855 #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT
25856 #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK
25857 #define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 0xFFFFFFFF
25858 #define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 28
25859 #define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 0x10000000U
25862 * Master Tri-state Enable for pin 29, active high
25864 #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL
25865 #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT
25866 #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK
25867 #define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 0xFFFFFFFF
25868 #define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 29
25869 #define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 0x20000000U
25872 * Master Tri-state Enable for pin 30, active high
25874 #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL
25875 #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT
25876 #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK
25877 #define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 0xFFFFFFFF
25878 #define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 30
25879 #define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 0x40000000U
25882 * Master Tri-state Enable for pin 31, active high
25884 #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL
25885 #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT
25886 #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK
25887 #define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 0xFFFFFFFF
25888 #define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 31
25889 #define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 0x80000000U
25892 * Master Tri-state Enable for pin 32, active high
25894 #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL
25895 #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT
25896 #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK
25897 #define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 0xFFFFFFFF
25898 #define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 0
25899 #define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 0x00000001U
25902 * Master Tri-state Enable for pin 33, active high
25904 #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL
25905 #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT
25906 #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK
25907 #define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 0xFFFFFFFF
25908 #define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 1
25909 #define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 0x00000002U
25912 * Master Tri-state Enable for pin 34, active high
25914 #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL
25915 #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT
25916 #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK
25917 #define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 0xFFFFFFFF
25918 #define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 2
25919 #define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 0x00000004U
25922 * Master Tri-state Enable for pin 35, active high
25924 #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL
25925 #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT
25926 #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK
25927 #define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 0xFFFFFFFF
25928 #define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 3
25929 #define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 0x00000008U
25932 * Master Tri-state Enable for pin 36, active high
25934 #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL
25935 #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT
25936 #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK
25937 #define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 0xFFFFFFFF
25938 #define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 4
25939 #define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 0x00000010U
25942 * Master Tri-state Enable for pin 37, active high
25944 #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL
25945 #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT
25946 #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK
25947 #define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 0xFFFFFFFF
25948 #define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 5
25949 #define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 0x00000020U
25952 * Master Tri-state Enable for pin 38, active high
25954 #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL
25955 #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT
25956 #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK
25957 #define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 0xFFFFFFFF
25958 #define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 6
25959 #define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 0x00000040U
25962 * Master Tri-state Enable for pin 39, active high
25964 #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL
25965 #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT
25966 #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK
25967 #define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 0xFFFFFFFF
25968 #define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 7
25969 #define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 0x00000080U
25972 * Master Tri-state Enable for pin 40, active high
25974 #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL
25975 #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT
25976 #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK
25977 #define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 0xFFFFFFFF
25978 #define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 8
25979 #define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 0x00000100U
25982 * Master Tri-state Enable for pin 41, active high
25984 #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL
25985 #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT
25986 #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK
25987 #define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 0xFFFFFFFF
25988 #define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 9
25989 #define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 0x00000200U
25992 * Master Tri-state Enable for pin 42, active high
25994 #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL
25995 #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT
25996 #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK
25997 #define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 0xFFFFFFFF
25998 #define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 10
25999 #define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 0x00000400U
26002 * Master Tri-state Enable for pin 43, active high
26004 #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL
26005 #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT
26006 #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK
26007 #define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 0xFFFFFFFF
26008 #define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 11
26009 #define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 0x00000800U
26012 * Master Tri-state Enable for pin 44, active high
26014 #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL
26015 #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT
26016 #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK
26017 #define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 0xFFFFFFFF
26018 #define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 12
26019 #define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 0x00001000U
26022 * Master Tri-state Enable for pin 45, active high
26024 #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL
26025 #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT
26026 #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK
26027 #define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 0xFFFFFFFF
26028 #define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 13
26029 #define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 0x00002000U
26032 * Master Tri-state Enable for pin 46, active high
26034 #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL
26035 #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT
26036 #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK
26037 #define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 0xFFFFFFFF
26038 #define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 14
26039 #define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 0x00004000U
26042 * Master Tri-state Enable for pin 47, active high
26044 #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL
26045 #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT
26046 #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK
26047 #define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 0xFFFFFFFF
26048 #define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 15
26049 #define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 0x00008000U
26052 * Master Tri-state Enable for pin 48, active high
26054 #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL
26055 #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT
26056 #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK
26057 #define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 0xFFFFFFFF
26058 #define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 16
26059 #define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 0x00010000U
26062 * Master Tri-state Enable for pin 49, active high
26064 #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL
26065 #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT
26066 #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK
26067 #define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 0xFFFFFFFF
26068 #define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 17
26069 #define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 0x00020000U
26072 * Master Tri-state Enable for pin 50, active high
26074 #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL
26075 #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT
26076 #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK
26077 #define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 0xFFFFFFFF
26078 #define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 18
26079 #define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 0x00040000U
26082 * Master Tri-state Enable for pin 51, active high
26084 #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL
26085 #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT
26086 #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK
26087 #define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 0xFFFFFFFF
26088 #define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 19
26089 #define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 0x00080000U
26092 * Master Tri-state Enable for pin 52, active high
26094 #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL
26095 #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT
26096 #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK
26097 #define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 0xFFFFFFFF
26098 #define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 20
26099 #define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 0x00100000U
26102 * Master Tri-state Enable for pin 53, active high
26104 #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL
26105 #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT
26106 #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK
26107 #define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 0xFFFFFFFF
26108 #define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 21
26109 #define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 0x00200000U
26112 * Master Tri-state Enable for pin 54, active high
26114 #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL
26115 #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT
26116 #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK
26117 #define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 0xFFFFFFFF
26118 #define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 22
26119 #define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 0x00400000U
26122 * Master Tri-state Enable for pin 55, active high
26124 #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL
26125 #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT
26126 #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK
26127 #define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 0xFFFFFFFF
26128 #define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 23
26129 #define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 0x00800000U
26132 * Master Tri-state Enable for pin 56, active high
26134 #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL
26135 #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT
26136 #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK
26137 #define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 0xFFFFFFFF
26138 #define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 24
26139 #define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 0x01000000U
26142 * Master Tri-state Enable for pin 57, active high
26144 #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL
26145 #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT
26146 #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK
26147 #define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 0xFFFFFFFF
26148 #define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 25
26149 #define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 0x02000000U
26152 * Master Tri-state Enable for pin 58, active high
26154 #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL
26155 #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT
26156 #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK
26157 #define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 0xFFFFFFFF
26158 #define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 26
26159 #define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 0x04000000U
26162 * Master Tri-state Enable for pin 59, active high
26164 #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL
26165 #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT
26166 #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK
26167 #define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 0xFFFFFFFF
26168 #define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 27
26169 #define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 0x08000000U
26172 * Master Tri-state Enable for pin 60, active high
26174 #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL
26175 #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT
26176 #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK
26177 #define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 0xFFFFFFFF
26178 #define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 28
26179 #define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 0x10000000U
26182 * Master Tri-state Enable for pin 61, active high
26184 #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL
26185 #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT
26186 #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK
26187 #define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 0xFFFFFFFF
26188 #define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 29
26189 #define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 0x20000000U
26192 * Master Tri-state Enable for pin 62, active high
26194 #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL
26195 #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT
26196 #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK
26197 #define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 0xFFFFFFFF
26198 #define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 30
26199 #define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 0x40000000U
26202 * Master Tri-state Enable for pin 63, active high
26204 #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL
26205 #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT
26206 #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK
26207 #define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 0xFFFFFFFF
26208 #define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 31
26209 #define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 0x80000000U
26212 * Master Tri-state Enable for pin 64, active high
26214 #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL
26215 #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT
26216 #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK
26217 #define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 0x00003FFF
26218 #define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 0
26219 #define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 0x00000001U
26222 * Master Tri-state Enable for pin 65, active high
26224 #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL
26225 #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT
26226 #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK
26227 #define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 0x00003FFF
26228 #define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 1
26229 #define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 0x00000002U
26232 * Master Tri-state Enable for pin 66, active high
26234 #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL
26235 #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT
26236 #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK
26237 #define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 0x00003FFF
26238 #define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 2
26239 #define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 0x00000004U
26242 * Master Tri-state Enable for pin 67, active high
26244 #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL
26245 #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT
26246 #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK
26247 #define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 0x00003FFF
26248 #define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 3
26249 #define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 0x00000008U
26252 * Master Tri-state Enable for pin 68, active high
26254 #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL
26255 #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT
26256 #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK
26257 #define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 0x00003FFF
26258 #define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 4
26259 #define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 0x00000010U
26262 * Master Tri-state Enable for pin 69, active high
26264 #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL
26265 #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT
26266 #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK
26267 #define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 0x00003FFF
26268 #define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 5
26269 #define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 0x00000020U
26272 * Master Tri-state Enable for pin 70, active high
26274 #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL
26275 #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT
26276 #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK
26277 #define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 0x00003FFF
26278 #define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 6
26279 #define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 0x00000040U
26282 * Master Tri-state Enable for pin 71, active high
26284 #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL
26285 #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT
26286 #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK
26287 #define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 0x00003FFF
26288 #define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 7
26289 #define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 0x00000080U
26292 * Master Tri-state Enable for pin 72, active high
26294 #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL
26295 #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT
26296 #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK
26297 #define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 0x00003FFF
26298 #define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 8
26299 #define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 0x00000100U
26302 * Master Tri-state Enable for pin 73, active high
26304 #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL
26305 #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT
26306 #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK
26307 #define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 0x00003FFF
26308 #define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 9
26309 #define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 0x00000200U
26312 * Master Tri-state Enable for pin 74, active high
26314 #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL
26315 #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT
26316 #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK
26317 #define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 0x00003FFF
26318 #define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 10
26319 #define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 0x00000400U
26322 * Master Tri-state Enable for pin 75, active high
26324 #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL
26325 #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT
26326 #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK
26327 #define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 0x00003FFF
26328 #define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 11
26329 #define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 0x00000800U
26332 * Master Tri-state Enable for pin 76, active high
26334 #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL
26335 #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT
26336 #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK
26337 #define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 0x00003FFF
26338 #define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 12
26339 #define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 0x00001000U
26342 * Master Tri-state Enable for pin 77, active high
26344 #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL
26345 #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT
26346 #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK
26347 #define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 0x00003FFF
26348 #define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 13
26349 #define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 0x00002000U
26352 * Each bit applies to a single IO. Bit 0 for MIO[0].
26354 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL
26355 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT
26356 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK
26357 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL
26358 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT 0
26359 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U
26362 * Each bit applies to a single IO. Bit 0 for MIO[0].
26364 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL
26365 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT
26366 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK
26367 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL
26368 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT 1
26369 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U
26372 * Each bit applies to a single IO. Bit 0 for MIO[0].
26374 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL
26375 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT
26376 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK
26377 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL
26378 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT 2
26379 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U
26382 * Each bit applies to a single IO. Bit 0 for MIO[0].
26384 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL
26385 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT
26386 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK
26387 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL
26388 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT 3
26389 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U
26392 * Each bit applies to a single IO. Bit 0 for MIO[0].
26394 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL
26395 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT
26396 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK
26397 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL
26398 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT 4
26399 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U
26402 * Each bit applies to a single IO. Bit 0 for MIO[0].
26404 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL
26405 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT
26406 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK
26407 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL
26408 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT 5
26409 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U
26412 * Each bit applies to a single IO. Bit 0 for MIO[0].
26414 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL
26415 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT
26416 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK
26417 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL
26418 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT 6
26419 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U
26422 * Each bit applies to a single IO. Bit 0 for MIO[0].
26424 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL
26425 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT
26426 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK
26427 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL
26428 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT 7
26429 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U
26432 * Each bit applies to a single IO. Bit 0 for MIO[0].
26434 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL
26435 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT
26436 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK
26437 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL
26438 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT 8
26439 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U
26442 * Each bit applies to a single IO. Bit 0 for MIO[0].
26444 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL
26445 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT
26446 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK
26447 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL
26448 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT 9
26449 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U
26452 * Each bit applies to a single IO. Bit 0 for MIO[0].
26454 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL
26455 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT
26456 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK
26457 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL
26458 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT 10
26459 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U
26462 * Each bit applies to a single IO. Bit 0 for MIO[0].
26464 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL
26465 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT
26466 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK
26467 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL
26468 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT 11
26469 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U
26472 * Each bit applies to a single IO. Bit 0 for MIO[0].
26474 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL
26475 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT
26476 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK
26477 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL
26478 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT 12
26479 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U
26482 * Each bit applies to a single IO. Bit 0 for MIO[0].
26484 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL
26485 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT
26486 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK
26487 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL
26488 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT 13
26489 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U
26492 * Each bit applies to a single IO. Bit 0 for MIO[0].
26494 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL
26495 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT
26496 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK
26497 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL
26498 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT 14
26499 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U
26502 * Each bit applies to a single IO. Bit 0 for MIO[0].
26504 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL
26505 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT
26506 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK
26507 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL
26508 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT 15
26509 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U
26512 * Each bit applies to a single IO. Bit 0 for MIO[0].
26514 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL
26515 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT
26516 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK
26517 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL
26518 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT 16
26519 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U
26522 * Each bit applies to a single IO. Bit 0 for MIO[0].
26524 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL
26525 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT
26526 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK
26527 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL
26528 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT 17
26529 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U
26532 * Each bit applies to a single IO. Bit 0 for MIO[0].
26534 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL
26535 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT
26536 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK
26537 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL
26538 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT 18
26539 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U
26542 * Each bit applies to a single IO. Bit 0 for MIO[0].
26544 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL
26545 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT
26546 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK
26547 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL
26548 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT 19
26549 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U
26552 * Each bit applies to a single IO. Bit 0 for MIO[0].
26554 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL
26555 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT
26556 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK
26557 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL
26558 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT 20
26559 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U
26562 * Each bit applies to a single IO. Bit 0 for MIO[0].
26564 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL
26565 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT
26566 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK
26567 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL
26568 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT 21
26569 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U
26572 * Each bit applies to a single IO. Bit 0 for MIO[0].
26574 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL
26575 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT
26576 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK
26577 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL
26578 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT 22
26579 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U
26582 * Each bit applies to a single IO. Bit 0 for MIO[0].
26584 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL
26585 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT
26586 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK
26587 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL
26588 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT 23
26589 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U
26592 * Each bit applies to a single IO. Bit 0 for MIO[0].
26594 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL
26595 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT
26596 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK
26597 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL
26598 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT 24
26599 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U
26602 * Each bit applies to a single IO. Bit 0 for MIO[0].
26604 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL
26605 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT
26606 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK
26607 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL
26608 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT 25
26609 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U
26612 * Each bit applies to a single IO. Bit 0 for MIO[0].
26614 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL
26615 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT
26616 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK
26617 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL
26618 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT 0
26619 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U
26622 * Each bit applies to a single IO. Bit 0 for MIO[0].
26624 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL
26625 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT
26626 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK
26627 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL
26628 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT 1
26629 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U
26632 * Each bit applies to a single IO. Bit 0 for MIO[0].
26634 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL
26635 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT
26636 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK
26637 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL
26638 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT 2
26639 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U
26642 * Each bit applies to a single IO. Bit 0 for MIO[0].
26644 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL
26645 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT
26646 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK
26647 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL
26648 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT 3
26649 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U
26652 * Each bit applies to a single IO. Bit 0 for MIO[0].
26654 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL
26655 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT
26656 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK
26657 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL
26658 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT 4
26659 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U
26662 * Each bit applies to a single IO. Bit 0 for MIO[0].
26664 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL
26665 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT
26666 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK
26667 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL
26668 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT 5
26669 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U
26672 * Each bit applies to a single IO. Bit 0 for MIO[0].
26674 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL
26675 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT
26676 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK
26677 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL
26678 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT 6
26679 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U
26682 * Each bit applies to a single IO. Bit 0 for MIO[0].
26684 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL
26685 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT
26686 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK
26687 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL
26688 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT 7
26689 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U
26692 * Each bit applies to a single IO. Bit 0 for MIO[0].
26694 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL
26695 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT
26696 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK
26697 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL
26698 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT 8
26699 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U
26702 * Each bit applies to a single IO. Bit 0 for MIO[0].
26704 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL
26705 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT
26706 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK
26707 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL
26708 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT 9
26709 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U
26712 * Each bit applies to a single IO. Bit 0 for MIO[0].
26714 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL
26715 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT
26716 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK
26717 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL
26718 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT 10
26719 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U
26722 * Each bit applies to a single IO. Bit 0 for MIO[0].
26724 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL
26725 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT
26726 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK
26727 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL
26728 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT 11
26729 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U
26732 * Each bit applies to a single IO. Bit 0 for MIO[0].
26734 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL
26735 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT
26736 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK
26737 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL
26738 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT 12
26739 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U
26742 * Each bit applies to a single IO. Bit 0 for MIO[0].
26744 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL
26745 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT
26746 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK
26747 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL
26748 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT 13
26749 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U
26752 * Each bit applies to a single IO. Bit 0 for MIO[0].
26754 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL
26755 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT
26756 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK
26757 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL
26758 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT 14
26759 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U
26762 * Each bit applies to a single IO. Bit 0 for MIO[0].
26764 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL
26765 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT
26766 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK
26767 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL
26768 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT 15
26769 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U
26772 * Each bit applies to a single IO. Bit 0 for MIO[0].
26774 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL
26775 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT
26776 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK
26777 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL
26778 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT 16
26779 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U
26782 * Each bit applies to a single IO. Bit 0 for MIO[0].
26784 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL
26785 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT
26786 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK
26787 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL
26788 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT 17
26789 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U
26792 * Each bit applies to a single IO. Bit 0 for MIO[0].
26794 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL
26795 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT
26796 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK
26797 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL
26798 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT 18
26799 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U
26802 * Each bit applies to a single IO. Bit 0 for MIO[0].
26804 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL
26805 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT
26806 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK
26807 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL
26808 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT 19
26809 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U
26812 * Each bit applies to a single IO. Bit 0 for MIO[0].
26814 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL
26815 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT
26816 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK
26817 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL
26818 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT 20
26819 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U
26822 * Each bit applies to a single IO. Bit 0 for MIO[0].
26824 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL
26825 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT
26826 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK
26827 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL
26828 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT 21
26829 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U
26832 * Each bit applies to a single IO. Bit 0 for MIO[0].
26834 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL
26835 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT
26836 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK
26837 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL
26838 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT 22
26839 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U
26842 * Each bit applies to a single IO. Bit 0 for MIO[0].
26844 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL
26845 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT
26846 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK
26847 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL
26848 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT 23
26849 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U
26852 * Each bit applies to a single IO. Bit 0 for MIO[0].
26854 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL
26855 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT
26856 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK
26857 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL
26858 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT 24
26859 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U
26862 * Each bit applies to a single IO. Bit 0 for MIO[0].
26864 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL
26865 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT
26866 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK
26867 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL
26868 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT 25
26869 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U
26872 * Each bit applies to a single IO. Bit 0 for MIO[0].
26874 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
26875 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
26876 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK
26877 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
26878 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0
26879 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U
26882 * Each bit applies to a single IO. Bit 0 for MIO[0].
26884 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
26885 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
26886 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK
26887 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
26888 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1
26889 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U
26892 * Each bit applies to a single IO. Bit 0 for MIO[0].
26894 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
26895 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
26896 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK
26897 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
26898 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2
26899 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U
26902 * Each bit applies to a single IO. Bit 0 for MIO[0].
26904 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
26905 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
26906 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK
26907 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
26908 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3
26909 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U
26912 * Each bit applies to a single IO. Bit 0 for MIO[0].
26914 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
26915 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
26916 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK
26917 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
26918 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4
26919 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U
26922 * Each bit applies to a single IO. Bit 0 for MIO[0].
26924 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
26925 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
26926 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK
26927 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
26928 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5
26929 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U
26932 * Each bit applies to a single IO. Bit 0 for MIO[0].
26934 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
26935 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
26936 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK
26937 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
26938 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6
26939 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U
26942 * Each bit applies to a single IO. Bit 0 for MIO[0].
26944 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
26945 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
26946 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK
26947 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
26948 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7
26949 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U
26952 * Each bit applies to a single IO. Bit 0 for MIO[0].
26954 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
26955 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
26956 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK
26957 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
26958 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8
26959 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U
26962 * Each bit applies to a single IO. Bit 0 for MIO[0].
26964 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
26965 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
26966 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK
26967 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
26968 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9
26969 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U
26972 * Each bit applies to a single IO. Bit 0 for MIO[0].
26974 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
26975 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
26976 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK
26977 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
26978 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10
26979 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U
26982 * Each bit applies to a single IO. Bit 0 for MIO[0].
26984 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
26985 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
26986 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK
26987 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
26988 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11
26989 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U
26992 * Each bit applies to a single IO. Bit 0 for MIO[0].
26994 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
26995 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
26996 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK
26997 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
26998 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12
26999 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U
27002 * Each bit applies to a single IO. Bit 0 for MIO[0].
27004 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
27005 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
27006 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK
27007 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
27008 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13
27009 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U
27012 * Each bit applies to a single IO. Bit 0 for MIO[0].
27014 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
27015 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
27016 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK
27017 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
27018 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14
27019 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U
27022 * Each bit applies to a single IO. Bit 0 for MIO[0].
27024 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
27025 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
27026 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK
27027 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
27028 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15
27029 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U
27032 * Each bit applies to a single IO. Bit 0 for MIO[0].
27034 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
27035 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
27036 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK
27037 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
27038 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16
27039 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U
27042 * Each bit applies to a single IO. Bit 0 for MIO[0].
27044 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
27045 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
27046 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK
27047 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
27048 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17
27049 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U
27052 * Each bit applies to a single IO. Bit 0 for MIO[0].
27054 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
27055 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
27056 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK
27057 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
27058 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18
27059 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U
27062 * Each bit applies to a single IO. Bit 0 for MIO[0].
27064 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
27065 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
27066 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK
27067 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
27068 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19
27069 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U
27072 * Each bit applies to a single IO. Bit 0 for MIO[0].
27074 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
27075 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
27076 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK
27077 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
27078 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20
27079 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U
27082 * Each bit applies to a single IO. Bit 0 for MIO[0].
27084 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
27085 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
27086 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK
27087 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
27088 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21
27089 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U
27092 * Each bit applies to a single IO. Bit 0 for MIO[0].
27094 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
27095 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
27096 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK
27097 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
27098 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22
27099 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U
27102 * Each bit applies to a single IO. Bit 0 for MIO[0].
27104 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
27105 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
27106 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK
27107 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
27108 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23
27109 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U
27112 * Each bit applies to a single IO. Bit 0 for MIO[0].
27114 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
27115 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
27116 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK
27117 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
27118 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24
27119 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U
27122 * Each bit applies to a single IO. Bit 0 for MIO[0].
27124 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
27125 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
27126 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK
27127 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
27128 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25
27129 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U
27132 * Each bit applies to a single IO. Bit 0 for MIO[0].
27134 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
27135 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
27136 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK
27137 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
27138 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0
27139 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U
27142 * Each bit applies to a single IO. Bit 0 for MIO[0].
27144 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
27145 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
27146 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK
27147 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
27148 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1
27149 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U
27152 * Each bit applies to a single IO. Bit 0 for MIO[0].
27154 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
27155 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
27156 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK
27157 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
27158 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2
27159 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U
27162 * Each bit applies to a single IO. Bit 0 for MIO[0].
27164 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
27165 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
27166 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK
27167 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
27168 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3
27169 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U
27172 * Each bit applies to a single IO. Bit 0 for MIO[0].
27174 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
27175 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
27176 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK
27177 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
27178 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4
27179 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U
27182 * Each bit applies to a single IO. Bit 0 for MIO[0].
27184 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
27185 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
27186 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK
27187 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
27188 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5
27189 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U
27192 * Each bit applies to a single IO. Bit 0 for MIO[0].
27194 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
27195 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
27196 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK
27197 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
27198 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6
27199 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U
27202 * Each bit applies to a single IO. Bit 0 for MIO[0].
27204 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
27205 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
27206 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK
27207 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
27208 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7
27209 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U
27212 * Each bit applies to a single IO. Bit 0 for MIO[0].
27214 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
27215 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
27216 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK
27217 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
27218 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8
27219 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U
27222 * Each bit applies to a single IO. Bit 0 for MIO[0].
27224 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
27225 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
27226 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK
27227 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
27228 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9
27229 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U
27232 * Each bit applies to a single IO. Bit 0 for MIO[0].
27234 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
27235 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
27236 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK
27237 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
27238 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10
27239 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U
27242 * Each bit applies to a single IO. Bit 0 for MIO[0].
27244 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
27245 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
27246 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK
27247 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
27248 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11
27249 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U
27252 * Each bit applies to a single IO. Bit 0 for MIO[0].
27254 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
27255 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
27256 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK
27257 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
27258 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12
27259 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U
27262 * Each bit applies to a single IO. Bit 0 for MIO[0].
27264 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
27265 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
27266 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK
27267 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
27268 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13
27269 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U
27272 * Each bit applies to a single IO. Bit 0 for MIO[0].
27274 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
27275 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
27276 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK
27277 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
27278 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14
27279 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U
27282 * Each bit applies to a single IO. Bit 0 for MIO[0].
27284 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
27285 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
27286 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK
27287 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
27288 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15
27289 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U
27292 * Each bit applies to a single IO. Bit 0 for MIO[0].
27294 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
27295 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
27296 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK
27297 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
27298 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16
27299 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U
27302 * Each bit applies to a single IO. Bit 0 for MIO[0].
27304 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
27305 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
27306 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK
27307 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
27308 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17
27309 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U
27312 * Each bit applies to a single IO. Bit 0 for MIO[0].
27314 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
27315 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
27316 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK
27317 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
27318 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18
27319 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U
27322 * Each bit applies to a single IO. Bit 0 for MIO[0].
27324 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
27325 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
27326 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK
27327 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
27328 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19
27329 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U
27332 * Each bit applies to a single IO. Bit 0 for MIO[0].
27334 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
27335 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
27336 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK
27337 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
27338 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20
27339 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U
27342 * Each bit applies to a single IO. Bit 0 for MIO[0].
27344 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
27345 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
27346 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK
27347 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
27348 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21
27349 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U
27352 * Each bit applies to a single IO. Bit 0 for MIO[0].
27354 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
27355 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
27356 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK
27357 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
27358 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22
27359 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U
27362 * Each bit applies to a single IO. Bit 0 for MIO[0].
27364 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
27365 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
27366 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK
27367 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
27368 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23
27369 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U
27372 * Each bit applies to a single IO. Bit 0 for MIO[0].
27374 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
27375 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
27376 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK
27377 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
27378 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24
27379 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U
27382 * Each bit applies to a single IO. Bit 0 for MIO[0].
27384 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
27385 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
27386 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK
27387 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
27388 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25
27389 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U
27392 * Each bit applies to a single IO. Bit 0 for MIO[0].
27394 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
27395 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT
27396 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK
27397 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
27398 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0
27399 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U
27402 * Each bit applies to a single IO. Bit 0 for MIO[0].
27404 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
27405 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT
27406 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK
27407 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
27408 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1
27409 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U
27412 * Each bit applies to a single IO. Bit 0 for MIO[0].
27414 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
27415 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT
27416 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK
27417 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
27418 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2
27419 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U
27422 * Each bit applies to a single IO. Bit 0 for MIO[0].
27424 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
27425 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT
27426 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK
27427 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
27428 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3
27429 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U
27432 * Each bit applies to a single IO. Bit 0 for MIO[0].
27434 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
27435 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT
27436 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK
27437 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
27438 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4
27439 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U
27442 * Each bit applies to a single IO. Bit 0 for MIO[0].
27444 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
27445 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT
27446 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK
27447 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
27448 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5
27449 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U
27452 * Each bit applies to a single IO. Bit 0 for MIO[0].
27454 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
27455 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT
27456 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK
27457 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
27458 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6
27459 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U
27462 * Each bit applies to a single IO. Bit 0 for MIO[0].
27464 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
27465 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT
27466 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK
27467 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
27468 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7
27469 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U
27472 * Each bit applies to a single IO. Bit 0 for MIO[0].
27474 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
27475 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT
27476 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK
27477 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
27478 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8
27479 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U
27482 * Each bit applies to a single IO. Bit 0 for MIO[0].
27484 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
27485 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT
27486 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK
27487 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
27488 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9
27489 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U
27492 * Each bit applies to a single IO. Bit 0 for MIO[0].
27494 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
27495 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT
27496 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK
27497 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
27498 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10
27499 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U
27502 * Each bit applies to a single IO. Bit 0 for MIO[0].
27504 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
27505 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT
27506 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK
27507 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
27508 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11
27509 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U
27512 * Each bit applies to a single IO. Bit 0 for MIO[0].
27514 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
27515 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT
27516 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK
27517 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
27518 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12
27519 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U
27522 * Each bit applies to a single IO. Bit 0 for MIO[0].
27524 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
27525 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT
27526 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK
27527 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
27528 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13
27529 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U
27532 * Each bit applies to a single IO. Bit 0 for MIO[0].
27534 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
27535 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT
27536 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK
27537 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
27538 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14
27539 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U
27542 * Each bit applies to a single IO. Bit 0 for MIO[0].
27544 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
27545 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT
27546 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK
27547 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
27548 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15
27549 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U
27552 * Each bit applies to a single IO. Bit 0 for MIO[0].
27554 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
27555 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT
27556 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK
27557 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
27558 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16
27559 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U
27562 * Each bit applies to a single IO. Bit 0 for MIO[0].
27564 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
27565 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT
27566 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK
27567 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
27568 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17
27569 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U
27572 * Each bit applies to a single IO. Bit 0 for MIO[0].
27574 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
27575 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT
27576 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK
27577 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
27578 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18
27579 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U
27582 * Each bit applies to a single IO. Bit 0 for MIO[0].
27584 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
27585 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT
27586 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK
27587 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
27588 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19
27589 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U
27592 * Each bit applies to a single IO. Bit 0 for MIO[0].
27594 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
27595 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT
27596 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK
27597 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
27598 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20
27599 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U
27602 * Each bit applies to a single IO. Bit 0 for MIO[0].
27604 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
27605 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT
27606 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK
27607 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
27608 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21
27609 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U
27612 * Each bit applies to a single IO. Bit 0 for MIO[0].
27614 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
27615 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT
27616 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK
27617 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
27618 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22
27619 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U
27622 * Each bit applies to a single IO. Bit 0 for MIO[0].
27624 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
27625 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT
27626 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK
27627 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
27628 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23
27629 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U
27632 * Each bit applies to a single IO. Bit 0 for MIO[0].
27634 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
27635 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT
27636 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK
27637 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
27638 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24
27639 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U
27642 * Each bit applies to a single IO. Bit 0 for MIO[0].
27644 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
27645 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT
27646 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK
27647 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
27648 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25
27649 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U
27652 * Each bit applies to a single IO. Bit 0 for MIO[0].
27654 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
27655 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
27656 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK
27657 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
27658 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0
27659 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U
27662 * Each bit applies to a single IO. Bit 0 for MIO[0].
27664 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
27665 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
27666 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK
27667 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
27668 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1
27669 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U
27672 * Each bit applies to a single IO. Bit 0 for MIO[0].
27674 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
27675 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
27676 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK
27677 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
27678 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2
27679 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U
27682 * Each bit applies to a single IO. Bit 0 for MIO[0].
27684 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
27685 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
27686 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK
27687 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
27688 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3
27689 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U
27692 * Each bit applies to a single IO. Bit 0 for MIO[0].
27694 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
27695 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
27696 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK
27697 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
27698 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4
27699 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U
27702 * Each bit applies to a single IO. Bit 0 for MIO[0].
27704 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
27705 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
27706 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK
27707 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
27708 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5
27709 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U
27712 * Each bit applies to a single IO. Bit 0 for MIO[0].
27714 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
27715 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
27716 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK
27717 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
27718 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6
27719 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U
27722 * Each bit applies to a single IO. Bit 0 for MIO[0].
27724 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
27725 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
27726 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK
27727 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
27728 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7
27729 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U
27732 * Each bit applies to a single IO. Bit 0 for MIO[0].
27734 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
27735 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
27736 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK
27737 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
27738 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8
27739 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U
27742 * Each bit applies to a single IO. Bit 0 for MIO[0].
27744 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
27745 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
27746 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK
27747 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
27748 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9
27749 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U
27752 * Each bit applies to a single IO. Bit 0 for MIO[0].
27754 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
27755 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
27756 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK
27757 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
27758 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10
27759 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U
27762 * Each bit applies to a single IO. Bit 0 for MIO[0].
27764 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
27765 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
27766 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK
27767 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
27768 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11
27769 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U
27772 * Each bit applies to a single IO. Bit 0 for MIO[0].
27774 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
27775 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
27776 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK
27777 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
27778 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12
27779 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U
27782 * Each bit applies to a single IO. Bit 0 for MIO[0].
27784 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
27785 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
27786 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK
27787 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
27788 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13
27789 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U
27792 * Each bit applies to a single IO. Bit 0 for MIO[0].
27794 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
27795 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
27796 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK
27797 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
27798 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14
27799 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U
27802 * Each bit applies to a single IO. Bit 0 for MIO[0].
27804 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
27805 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
27806 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK
27807 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
27808 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15
27809 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U
27812 * Each bit applies to a single IO. Bit 0 for MIO[0].
27814 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
27815 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
27816 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK
27817 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
27818 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16
27819 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U
27822 * Each bit applies to a single IO. Bit 0 for MIO[0].
27824 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
27825 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
27826 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK
27827 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
27828 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17
27829 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U
27832 * Each bit applies to a single IO. Bit 0 for MIO[0].
27834 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
27835 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
27836 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK
27837 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
27838 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18
27839 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U
27842 * Each bit applies to a single IO. Bit 0 for MIO[0].
27844 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
27845 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
27846 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK
27847 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
27848 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19
27849 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U
27852 * Each bit applies to a single IO. Bit 0 for MIO[0].
27854 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
27855 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
27856 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK
27857 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
27858 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20
27859 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U
27862 * Each bit applies to a single IO. Bit 0 for MIO[0].
27864 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
27865 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
27866 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK
27867 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
27868 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21
27869 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U
27872 * Each bit applies to a single IO. Bit 0 for MIO[0].
27874 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
27875 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
27876 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK
27877 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
27878 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22
27879 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U
27882 * Each bit applies to a single IO. Bit 0 for MIO[0].
27884 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
27885 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
27886 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK
27887 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
27888 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23
27889 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U
27892 * Each bit applies to a single IO. Bit 0 for MIO[0].
27894 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
27895 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
27896 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK
27897 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
27898 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24
27899 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U
27902 * Each bit applies to a single IO. Bit 0 for MIO[0].
27904 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
27905 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
27906 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK
27907 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
27908 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25
27909 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U
27912 * Each bit applies to a single IO. Bit 0 for MIO[26].
27914 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL
27915 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT
27916 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK
27917 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL
27918 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT 0
27919 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U
27922 * Each bit applies to a single IO. Bit 0 for MIO[26].
27924 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL
27925 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT
27926 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK
27927 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL
27928 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT 1
27929 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U
27932 * Each bit applies to a single IO. Bit 0 for MIO[26].
27934 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL
27935 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT
27936 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK
27937 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL
27938 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT 2
27939 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U
27942 * Each bit applies to a single IO. Bit 0 for MIO[26].
27944 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL
27945 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT
27946 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK
27947 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL
27948 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT 3
27949 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U
27952 * Each bit applies to a single IO. Bit 0 for MIO[26].
27954 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL
27955 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT
27956 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK
27957 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL
27958 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT 4
27959 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U
27962 * Each bit applies to a single IO. Bit 0 for MIO[26].
27964 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL
27965 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT
27966 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK
27967 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL
27968 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT 5
27969 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U
27972 * Each bit applies to a single IO. Bit 0 for MIO[26].
27974 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL
27975 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT
27976 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK
27977 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL
27978 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT 6
27979 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U
27982 * Each bit applies to a single IO. Bit 0 for MIO[26].
27984 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL
27985 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT
27986 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK
27987 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL
27988 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT 7
27989 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U
27992 * Each bit applies to a single IO. Bit 0 for MIO[26].
27994 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL
27995 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT
27996 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK
27997 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL
27998 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT 8
27999 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U
28002 * Each bit applies to a single IO. Bit 0 for MIO[26].
28004 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL
28005 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT
28006 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK
28007 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL
28008 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT 9
28009 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U
28012 * Each bit applies to a single IO. Bit 0 for MIO[26].
28014 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL
28015 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT
28016 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK
28017 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL
28018 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT 10
28019 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U
28022 * Each bit applies to a single IO. Bit 0 for MIO[26].
28024 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL
28025 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT
28026 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK
28027 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL
28028 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT 11
28029 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U
28032 * Each bit applies to a single IO. Bit 0 for MIO[26].
28034 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL
28035 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT
28036 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK
28037 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL
28038 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT 12
28039 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U
28042 * Each bit applies to a single IO. Bit 0 for MIO[26].
28044 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL
28045 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT
28046 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK
28047 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL
28048 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT 13
28049 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U
28052 * Each bit applies to a single IO. Bit 0 for MIO[26].
28054 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL
28055 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT
28056 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK
28057 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL
28058 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT 14
28059 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U
28062 * Each bit applies to a single IO. Bit 0 for MIO[26].
28064 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL
28065 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT
28066 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK
28067 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL
28068 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT 15
28069 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U
28072 * Each bit applies to a single IO. Bit 0 for MIO[26].
28074 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL
28075 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT
28076 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK
28077 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL
28078 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT 16
28079 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U
28082 * Each bit applies to a single IO. Bit 0 for MIO[26].
28084 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL
28085 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT
28086 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK
28087 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL
28088 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT 17
28089 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U
28092 * Each bit applies to a single IO. Bit 0 for MIO[26].
28094 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL
28095 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT
28096 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK
28097 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL
28098 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT 18
28099 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U
28102 * Each bit applies to a single IO. Bit 0 for MIO[26].
28104 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL
28105 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT
28106 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK
28107 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL
28108 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT 19
28109 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U
28112 * Each bit applies to a single IO. Bit 0 for MIO[26].
28114 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL
28115 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT
28116 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK
28117 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL
28118 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT 20
28119 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U
28122 * Each bit applies to a single IO. Bit 0 for MIO[26].
28124 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL
28125 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT
28126 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK
28127 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL
28128 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT 21
28129 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U
28132 * Each bit applies to a single IO. Bit 0 for MIO[26].
28134 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL
28135 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT
28136 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK
28137 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL
28138 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT 22
28139 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U
28142 * Each bit applies to a single IO. Bit 0 for MIO[26].
28144 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL
28145 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT
28146 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK
28147 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL
28148 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT 23
28149 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U
28152 * Each bit applies to a single IO. Bit 0 for MIO[26].
28154 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL
28155 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT
28156 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK
28157 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL
28158 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT 24
28159 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U
28162 * Each bit applies to a single IO. Bit 0 for MIO[26].
28164 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL
28165 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT
28166 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK
28167 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL
28168 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT 25
28169 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U
28172 * Each bit applies to a single IO. Bit 0 for MIO[26].
28174 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL
28175 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT
28176 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK
28177 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL
28178 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT 0
28179 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U
28182 * Each bit applies to a single IO. Bit 0 for MIO[26].
28184 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL
28185 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT
28186 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK
28187 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL
28188 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT 1
28189 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U
28192 * Each bit applies to a single IO. Bit 0 for MIO[26].
28194 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL
28195 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT
28196 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK
28197 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL
28198 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT 2
28199 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U
28202 * Each bit applies to a single IO. Bit 0 for MIO[26].
28204 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL
28205 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT
28206 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK
28207 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL
28208 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT 3
28209 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U
28212 * Each bit applies to a single IO. Bit 0 for MIO[26].
28214 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL
28215 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT
28216 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK
28217 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL
28218 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT 4
28219 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U
28222 * Each bit applies to a single IO. Bit 0 for MIO[26].
28224 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL
28225 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT
28226 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK
28227 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL
28228 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT 5
28229 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U
28232 * Each bit applies to a single IO. Bit 0 for MIO[26].
28234 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL
28235 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT
28236 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK
28237 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL
28238 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT 6
28239 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U
28242 * Each bit applies to a single IO. Bit 0 for MIO[26].
28244 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL
28245 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT
28246 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK
28247 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL
28248 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT 7
28249 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U
28252 * Each bit applies to a single IO. Bit 0 for MIO[26].
28254 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL
28255 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT
28256 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK
28257 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL
28258 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT 8
28259 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U
28262 * Each bit applies to a single IO. Bit 0 for MIO[26].
28264 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL
28265 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT
28266 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK
28267 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL
28268 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT 9
28269 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U
28272 * Each bit applies to a single IO. Bit 0 for MIO[26].
28274 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL
28275 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT
28276 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK
28277 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL
28278 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT 10
28279 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U
28282 * Each bit applies to a single IO. Bit 0 for MIO[26].
28284 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL
28285 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT
28286 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK
28287 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL
28288 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT 11
28289 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U
28292 * Each bit applies to a single IO. Bit 0 for MIO[26].
28294 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL
28295 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT
28296 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK
28297 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL
28298 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT 12
28299 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U
28302 * Each bit applies to a single IO. Bit 0 for MIO[26].
28304 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL
28305 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT
28306 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK
28307 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL
28308 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT 13
28309 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U
28312 * Each bit applies to a single IO. Bit 0 for MIO[26].
28314 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL
28315 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT
28316 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK
28317 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL
28318 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT 14
28319 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U
28322 * Each bit applies to a single IO. Bit 0 for MIO[26].
28324 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL
28325 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT
28326 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK
28327 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL
28328 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT 15
28329 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U
28332 * Each bit applies to a single IO. Bit 0 for MIO[26].
28334 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL
28335 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT
28336 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK
28337 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL
28338 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT 16
28339 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U
28342 * Each bit applies to a single IO. Bit 0 for MIO[26].
28344 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL
28345 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT
28346 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK
28347 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL
28348 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT 17
28349 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U
28352 * Each bit applies to a single IO. Bit 0 for MIO[26].
28354 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL
28355 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT
28356 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK
28357 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL
28358 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT 18
28359 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U
28362 * Each bit applies to a single IO. Bit 0 for MIO[26].
28364 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL
28365 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT
28366 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK
28367 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL
28368 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT 19
28369 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U
28372 * Each bit applies to a single IO. Bit 0 for MIO[26].
28374 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL
28375 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT
28376 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK
28377 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL
28378 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT 20
28379 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U
28382 * Each bit applies to a single IO. Bit 0 for MIO[26].
28384 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL
28385 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT
28386 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK
28387 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL
28388 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT 21
28389 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U
28392 * Each bit applies to a single IO. Bit 0 for MIO[26].
28394 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL
28395 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT
28396 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK
28397 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL
28398 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT 22
28399 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U
28402 * Each bit applies to a single IO. Bit 0 for MIO[26].
28404 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL
28405 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT
28406 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK
28407 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL
28408 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT 23
28409 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U
28412 * Each bit applies to a single IO. Bit 0 for MIO[26].
28414 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL
28415 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT
28416 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK
28417 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL
28418 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT 24
28419 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U
28422 * Each bit applies to a single IO. Bit 0 for MIO[26].
28424 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL
28425 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT
28426 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK
28427 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL
28428 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT 25
28429 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U
28432 * Each bit applies to a single IO. Bit 0 for MIO[26].
28434 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
28435 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
28436 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK
28437 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
28438 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0
28439 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U
28442 * Each bit applies to a single IO. Bit 0 for MIO[26].
28444 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
28445 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
28446 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK
28447 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
28448 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1
28449 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U
28452 * Each bit applies to a single IO. Bit 0 for MIO[26].
28454 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
28455 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
28456 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK
28457 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
28458 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2
28459 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U
28462 * Each bit applies to a single IO. Bit 0 for MIO[26].
28464 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
28465 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
28466 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK
28467 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
28468 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3
28469 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U
28472 * Each bit applies to a single IO. Bit 0 for MIO[26].
28474 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
28475 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
28476 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK
28477 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
28478 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4
28479 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U
28482 * Each bit applies to a single IO. Bit 0 for MIO[26].
28484 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
28485 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
28486 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK
28487 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
28488 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5
28489 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U
28492 * Each bit applies to a single IO. Bit 0 for MIO[26].
28494 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
28495 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
28496 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK
28497 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
28498 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6
28499 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U
28502 * Each bit applies to a single IO. Bit 0 for MIO[26].
28504 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
28505 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
28506 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK
28507 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
28508 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7
28509 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U
28512 * Each bit applies to a single IO. Bit 0 for MIO[26].
28514 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
28515 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
28516 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK
28517 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
28518 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8
28519 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U
28522 * Each bit applies to a single IO. Bit 0 for MIO[26].
28524 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
28525 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
28526 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK
28527 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
28528 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9
28529 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U
28532 * Each bit applies to a single IO. Bit 0 for MIO[26].
28534 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
28535 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
28536 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK
28537 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
28538 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10
28539 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U
28542 * Each bit applies to a single IO. Bit 0 for MIO[26].
28544 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
28545 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
28546 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK
28547 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
28548 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11
28549 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U
28552 * Each bit applies to a single IO. Bit 0 for MIO[26].
28554 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
28555 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
28556 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK
28557 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
28558 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12
28559 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U
28562 * Each bit applies to a single IO. Bit 0 for MIO[26].
28564 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
28565 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
28566 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK
28567 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
28568 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13
28569 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U
28572 * Each bit applies to a single IO. Bit 0 for MIO[26].
28574 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
28575 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
28576 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK
28577 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
28578 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14
28579 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U
28582 * Each bit applies to a single IO. Bit 0 for MIO[26].
28584 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
28585 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
28586 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK
28587 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
28588 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15
28589 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U
28592 * Each bit applies to a single IO. Bit 0 for MIO[26].
28594 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
28595 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
28596 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK
28597 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
28598 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16
28599 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U
28602 * Each bit applies to a single IO. Bit 0 for MIO[26].
28604 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
28605 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
28606 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK
28607 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
28608 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17
28609 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U
28612 * Each bit applies to a single IO. Bit 0 for MIO[26].
28614 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
28615 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
28616 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK
28617 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
28618 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18
28619 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U
28622 * Each bit applies to a single IO. Bit 0 for MIO[26].
28624 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
28625 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
28626 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK
28627 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
28628 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19
28629 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U
28632 * Each bit applies to a single IO. Bit 0 for MIO[26].
28634 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
28635 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
28636 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK
28637 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
28638 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20
28639 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U
28642 * Each bit applies to a single IO. Bit 0 for MIO[26].
28644 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
28645 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
28646 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK
28647 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
28648 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21
28649 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U
28652 * Each bit applies to a single IO. Bit 0 for MIO[26].
28654 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
28655 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
28656 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK
28657 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
28658 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22
28659 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U
28662 * Each bit applies to a single IO. Bit 0 for MIO[26].
28664 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
28665 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
28666 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK
28667 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
28668 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23
28669 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U
28672 * Each bit applies to a single IO. Bit 0 for MIO[26].
28674 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
28675 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
28676 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK
28677 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
28678 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24
28679 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U
28682 * Each bit applies to a single IO. Bit 0 for MIO[26].
28684 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
28685 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
28686 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK
28687 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
28688 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25
28689 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U
28692 * Each bit applies to a single IO. Bit 0 for MIO[26].
28694 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
28695 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
28696 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK
28697 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
28698 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0
28699 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U
28702 * Each bit applies to a single IO. Bit 0 for MIO[26].
28704 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
28705 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
28706 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK
28707 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
28708 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1
28709 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U
28712 * Each bit applies to a single IO. Bit 0 for MIO[26].
28714 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
28715 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
28716 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK
28717 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
28718 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2
28719 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U
28722 * Each bit applies to a single IO. Bit 0 for MIO[26].
28724 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
28725 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
28726 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK
28727 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
28728 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3
28729 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U
28732 * Each bit applies to a single IO. Bit 0 for MIO[26].
28734 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
28735 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
28736 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK
28737 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
28738 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4
28739 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U
28742 * Each bit applies to a single IO. Bit 0 for MIO[26].
28744 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
28745 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
28746 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK
28747 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
28748 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5
28749 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U
28752 * Each bit applies to a single IO. Bit 0 for MIO[26].
28754 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
28755 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
28756 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK
28757 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
28758 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6
28759 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U
28762 * Each bit applies to a single IO. Bit 0 for MIO[26].
28764 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
28765 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
28766 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK
28767 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
28768 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7
28769 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U
28772 * Each bit applies to a single IO. Bit 0 for MIO[26].
28774 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
28775 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
28776 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK
28777 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
28778 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8
28779 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U
28782 * Each bit applies to a single IO. Bit 0 for MIO[26].
28784 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
28785 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
28786 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK
28787 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
28788 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9
28789 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U
28792 * Each bit applies to a single IO. Bit 0 for MIO[26].
28794 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
28795 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
28796 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK
28797 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
28798 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10
28799 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U
28802 * Each bit applies to a single IO. Bit 0 for MIO[26].
28804 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
28805 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
28806 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK
28807 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
28808 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11
28809 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U
28812 * Each bit applies to a single IO. Bit 0 for MIO[26].
28814 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
28815 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
28816 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK
28817 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
28818 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12
28819 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U
28822 * Each bit applies to a single IO. Bit 0 for MIO[26].
28824 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
28825 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
28826 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK
28827 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
28828 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13
28829 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U
28832 * Each bit applies to a single IO. Bit 0 for MIO[26].
28834 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
28835 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
28836 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK
28837 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
28838 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14
28839 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U
28842 * Each bit applies to a single IO. Bit 0 for MIO[26].
28844 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
28845 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
28846 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK
28847 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
28848 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15
28849 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U
28852 * Each bit applies to a single IO. Bit 0 for MIO[26].
28854 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
28855 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
28856 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK
28857 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
28858 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16
28859 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U
28862 * Each bit applies to a single IO. Bit 0 for MIO[26].
28864 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
28865 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
28866 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK
28867 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
28868 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17
28869 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U
28872 * Each bit applies to a single IO. Bit 0 for MIO[26].
28874 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
28875 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
28876 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK
28877 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
28878 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18
28879 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U
28882 * Each bit applies to a single IO. Bit 0 for MIO[26].
28884 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
28885 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
28886 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK
28887 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
28888 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19
28889 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U
28892 * Each bit applies to a single IO. Bit 0 for MIO[26].
28894 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
28895 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
28896 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK
28897 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
28898 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20
28899 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U
28902 * Each bit applies to a single IO. Bit 0 for MIO[26].
28904 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
28905 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
28906 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK
28907 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
28908 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21
28909 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U
28912 * Each bit applies to a single IO. Bit 0 for MIO[26].
28914 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
28915 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
28916 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK
28917 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
28918 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22
28919 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U
28922 * Each bit applies to a single IO. Bit 0 for MIO[26].
28924 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
28925 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
28926 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK
28927 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
28928 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23
28929 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U
28932 * Each bit applies to a single IO. Bit 0 for MIO[26].
28934 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
28935 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
28936 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK
28937 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
28938 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24
28939 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U
28942 * Each bit applies to a single IO. Bit 0 for MIO[26].
28944 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
28945 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
28946 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK
28947 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
28948 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25
28949 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U
28952 * Each bit applies to a single IO. Bit 0 for MIO[26].
28954 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
28955 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT
28956 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK
28957 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
28958 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 12
28959 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00001000U
28962 * Each bit applies to a single IO. Bit 0 for MIO[26].
28964 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
28965 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT
28966 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK
28967 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
28968 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 13
28969 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00002000U
28972 * Each bit applies to a single IO. Bit 0 for MIO[26].
28974 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
28975 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT
28976 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK
28977 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
28978 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 14
28979 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00004000U
28982 * Each bit applies to a single IO. Bit 0 for MIO[26].
28984 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
28985 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT
28986 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK
28987 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
28988 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 15
28989 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00008000U
28992 * Each bit applies to a single IO. Bit 0 for MIO[26].
28994 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
28995 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT
28996 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK
28997 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
28998 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 16
28999 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00010000U
29002 * Each bit applies to a single IO. Bit 0 for MIO[26].
29004 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
29005 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT
29006 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK
29007 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
29008 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 17
29009 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00020000U
29012 * Each bit applies to a single IO. Bit 0 for MIO[26].
29014 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
29015 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT
29016 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK
29017 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
29018 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 18
29019 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00040000U
29022 * Each bit applies to a single IO. Bit 0 for MIO[26].
29024 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
29025 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT
29026 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK
29027 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
29028 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 19
29029 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00080000U
29032 * Each bit applies to a single IO. Bit 0 for MIO[26].
29034 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
29035 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT
29036 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK
29037 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
29038 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 20
29039 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00100000U
29042 * Each bit applies to a single IO. Bit 0 for MIO[26].
29044 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
29045 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT
29046 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK
29047 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
29048 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 21
29049 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00200000U
29052 * Each bit applies to a single IO. Bit 0 for MIO[26].
29054 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
29055 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT
29056 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK
29057 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
29058 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 22
29059 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00400000U
29062 * Each bit applies to a single IO. Bit 0 for MIO[26].
29064 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
29065 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT
29066 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK
29067 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
29068 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 23
29069 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00800000U
29072 * Each bit applies to a single IO. Bit 0 for MIO[26].
29074 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
29075 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT
29076 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK
29077 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
29078 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 24
29079 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 0x01000000U
29082 * Each bit applies to a single IO. Bit 0 for MIO[26].
29084 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
29085 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT
29086 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK
29087 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
29088 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 25
29089 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 0x02000000U
29092 * Each bit applies to a single IO. Bit 0 for MIO[26].
29094 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
29095 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT
29096 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK
29097 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
29098 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 0
29099 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00000001U
29102 * Each bit applies to a single IO. Bit 0 for MIO[26].
29104 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
29105 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT
29106 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK
29107 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
29108 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 1
29109 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00000002U
29112 * Each bit applies to a single IO. Bit 0 for MIO[26].
29114 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
29115 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT
29116 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK
29117 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
29118 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 2
29119 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00000004U
29122 * Each bit applies to a single IO. Bit 0 for MIO[26].
29124 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
29125 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT
29126 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK
29127 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
29128 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 3
29129 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00000008U
29132 * Each bit applies to a single IO. Bit 0 for MIO[26].
29134 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
29135 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT
29136 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK
29137 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
29138 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 4
29139 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00000010U
29142 * Each bit applies to a single IO. Bit 0 for MIO[26].
29144 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
29145 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT
29146 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK
29147 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
29148 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 5
29149 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00000020U
29152 * Each bit applies to a single IO. Bit 0 for MIO[26].
29154 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
29155 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT
29156 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK
29157 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
29158 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 6
29159 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00000040U
29162 * Each bit applies to a single IO. Bit 0 for MIO[26].
29164 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
29165 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT
29166 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK
29167 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
29168 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 7
29169 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00000080U
29172 * Each bit applies to a single IO. Bit 0 for MIO[26].
29174 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
29175 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT
29176 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK
29177 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
29178 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 8
29179 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00000100U
29182 * Each bit applies to a single IO. Bit 0 for MIO[26].
29184 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
29185 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT
29186 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK
29187 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
29188 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 9
29189 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00000200U
29192 * Each bit applies to a single IO. Bit 0 for MIO[26].
29194 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
29195 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT
29196 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK
29197 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
29198 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 10
29199 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 0x00000400U
29202 * Each bit applies to a single IO. Bit 0 for MIO[26].
29204 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
29205 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT
29206 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK
29207 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
29208 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 11
29209 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 0x00000800U
29212 * Each bit applies to a single IO. Bit 0 for MIO[26].
29214 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
29215 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
29216 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK
29217 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
29218 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0
29219 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U
29222 * Each bit applies to a single IO. Bit 0 for MIO[26].
29224 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
29225 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
29226 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK
29227 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
29228 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1
29229 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U
29232 * Each bit applies to a single IO. Bit 0 for MIO[26].
29234 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
29235 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
29236 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK
29237 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
29238 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2
29239 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U
29242 * Each bit applies to a single IO. Bit 0 for MIO[26].
29244 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
29245 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
29246 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK
29247 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
29248 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3
29249 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U
29252 * Each bit applies to a single IO. Bit 0 for MIO[26].
29254 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
29255 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
29256 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK
29257 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
29258 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4
29259 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U
29262 * Each bit applies to a single IO. Bit 0 for MIO[26].
29264 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
29265 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
29266 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK
29267 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
29268 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5
29269 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U
29272 * Each bit applies to a single IO. Bit 0 for MIO[26].
29274 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
29275 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
29276 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK
29277 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
29278 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6
29279 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U
29282 * Each bit applies to a single IO. Bit 0 for MIO[26].
29284 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
29285 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
29286 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK
29287 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
29288 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7
29289 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U
29292 * Each bit applies to a single IO. Bit 0 for MIO[26].
29294 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
29295 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
29296 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK
29297 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
29298 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8
29299 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U
29302 * Each bit applies to a single IO. Bit 0 for MIO[26].
29304 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
29305 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
29306 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK
29307 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
29308 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9
29309 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U
29312 * Each bit applies to a single IO. Bit 0 for MIO[26].
29314 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
29315 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
29316 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK
29317 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
29318 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10
29319 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U
29322 * Each bit applies to a single IO. Bit 0 for MIO[26].
29324 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
29325 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
29326 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK
29327 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
29328 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11
29329 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U
29332 * Each bit applies to a single IO. Bit 0 for MIO[26].
29334 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
29335 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
29336 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK
29337 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
29338 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12
29339 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U
29342 * Each bit applies to a single IO. Bit 0 for MIO[26].
29344 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
29345 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
29346 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK
29347 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
29348 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13
29349 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U
29352 * Each bit applies to a single IO. Bit 0 for MIO[26].
29354 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
29355 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
29356 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK
29357 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
29358 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14
29359 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U
29362 * Each bit applies to a single IO. Bit 0 for MIO[26].
29364 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
29365 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
29366 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK
29367 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
29368 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15
29369 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U
29372 * Each bit applies to a single IO. Bit 0 for MIO[26].
29374 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
29375 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
29376 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK
29377 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
29378 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16
29379 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U
29382 * Each bit applies to a single IO. Bit 0 for MIO[26].
29384 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
29385 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
29386 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK
29387 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
29388 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17
29389 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U
29392 * Each bit applies to a single IO. Bit 0 for MIO[26].
29394 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
29395 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
29396 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK
29397 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
29398 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18
29399 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U
29402 * Each bit applies to a single IO. Bit 0 for MIO[26].
29404 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
29405 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
29406 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK
29407 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
29408 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19
29409 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U
29412 * Each bit applies to a single IO. Bit 0 for MIO[26].
29414 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
29415 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
29416 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK
29417 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
29418 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20
29419 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U
29422 * Each bit applies to a single IO. Bit 0 for MIO[26].
29424 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
29425 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
29426 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK
29427 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
29428 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21
29429 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U
29432 * Each bit applies to a single IO. Bit 0 for MIO[26].
29434 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
29435 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
29436 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK
29437 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
29438 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22
29439 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U
29442 * Each bit applies to a single IO. Bit 0 for MIO[26].
29444 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
29445 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
29446 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK
29447 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
29448 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23
29449 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U
29452 * Each bit applies to a single IO. Bit 0 for MIO[26].
29454 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
29455 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
29456 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK
29457 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
29458 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24
29459 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U
29462 * Each bit applies to a single IO. Bit 0 for MIO[26].
29464 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
29465 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
29466 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK
29467 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
29468 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25
29469 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U
29472 * Each bit applies to a single IO. Bit 0 for MIO[52].
29474 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL
29475 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT
29476 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK
29477 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL
29478 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT 0
29479 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U
29482 * Each bit applies to a single IO. Bit 0 for MIO[52].
29484 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL
29485 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT
29486 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK
29487 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL
29488 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT 1
29489 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U
29492 * Each bit applies to a single IO. Bit 0 for MIO[52].
29494 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL
29495 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT
29496 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK
29497 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL
29498 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT 2
29499 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U
29502 * Each bit applies to a single IO. Bit 0 for MIO[52].
29504 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL
29505 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT
29506 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK
29507 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL
29508 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT 3
29509 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U
29512 * Each bit applies to a single IO. Bit 0 for MIO[52].
29514 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL
29515 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT
29516 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK
29517 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL
29518 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT 4
29519 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U
29522 * Each bit applies to a single IO. Bit 0 for MIO[52].
29524 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL
29525 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT
29526 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK
29527 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL
29528 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT 5
29529 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U
29532 * Each bit applies to a single IO. Bit 0 for MIO[52].
29534 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL
29535 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT
29536 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK
29537 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL
29538 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT 6
29539 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U
29542 * Each bit applies to a single IO. Bit 0 for MIO[52].
29544 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL
29545 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT
29546 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK
29547 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL
29548 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT 7
29549 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U
29552 * Each bit applies to a single IO. Bit 0 for MIO[52].
29554 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL
29555 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT
29556 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK
29557 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL
29558 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT 8
29559 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U
29562 * Each bit applies to a single IO. Bit 0 for MIO[52].
29564 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL
29565 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT
29566 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK
29567 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL
29568 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT 9
29569 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U
29572 * Each bit applies to a single IO. Bit 0 for MIO[52].
29574 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL
29575 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT
29576 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK
29577 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL
29578 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT 10
29579 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U
29582 * Each bit applies to a single IO. Bit 0 for MIO[52].
29584 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL
29585 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT
29586 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK
29587 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL
29588 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT 11
29589 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U
29592 * Each bit applies to a single IO. Bit 0 for MIO[52].
29594 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL
29595 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT
29596 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK
29597 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL
29598 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT 12
29599 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U
29602 * Each bit applies to a single IO. Bit 0 for MIO[52].
29604 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL
29605 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT
29606 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK
29607 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL
29608 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT 13
29609 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U
29612 * Each bit applies to a single IO. Bit 0 for MIO[52].
29614 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL
29615 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT
29616 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK
29617 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL
29618 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT 14
29619 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U
29622 * Each bit applies to a single IO. Bit 0 for MIO[52].
29624 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL
29625 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT
29626 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK
29627 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL
29628 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT 15
29629 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U
29632 * Each bit applies to a single IO. Bit 0 for MIO[52].
29634 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL
29635 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT
29636 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK
29637 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL
29638 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT 16
29639 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U
29642 * Each bit applies to a single IO. Bit 0 for MIO[52].
29644 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL
29645 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT
29646 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK
29647 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL
29648 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT 17
29649 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U
29652 * Each bit applies to a single IO. Bit 0 for MIO[52].
29654 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL
29655 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT
29656 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK
29657 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL
29658 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT 18
29659 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U
29662 * Each bit applies to a single IO. Bit 0 for MIO[52].
29664 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL
29665 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT
29666 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK
29667 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL
29668 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT 19
29669 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U
29672 * Each bit applies to a single IO. Bit 0 for MIO[52].
29674 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL
29675 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT
29676 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK
29677 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL
29678 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT 20
29679 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U
29682 * Each bit applies to a single IO. Bit 0 for MIO[52].
29684 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL
29685 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT
29686 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK
29687 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL
29688 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT 21
29689 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U
29692 * Each bit applies to a single IO. Bit 0 for MIO[52].
29694 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL
29695 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT
29696 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK
29697 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL
29698 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT 22
29699 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U
29702 * Each bit applies to a single IO. Bit 0 for MIO[52].
29704 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL
29705 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT
29706 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK
29707 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL
29708 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT 23
29709 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U
29712 * Each bit applies to a single IO. Bit 0 for MIO[52].
29714 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL
29715 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT
29716 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK
29717 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL
29718 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT 24
29719 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U
29722 * Each bit applies to a single IO. Bit 0 for MIO[52].
29724 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL
29725 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT
29726 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK
29727 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL
29728 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT 25
29729 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U
29732 * Each bit applies to a single IO. Bit 0 for MIO[52].
29734 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL
29735 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT
29736 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK
29737 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL
29738 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT 0
29739 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U
29742 * Each bit applies to a single IO. Bit 0 for MIO[52].
29744 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL
29745 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT
29746 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK
29747 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL
29748 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT 1
29749 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U
29752 * Each bit applies to a single IO. Bit 0 for MIO[52].
29754 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL
29755 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT
29756 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK
29757 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL
29758 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT 2
29759 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U
29762 * Each bit applies to a single IO. Bit 0 for MIO[52].
29764 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL
29765 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT
29766 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK
29767 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL
29768 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT 3
29769 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U
29772 * Each bit applies to a single IO. Bit 0 for MIO[52].
29774 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL
29775 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT
29776 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK
29777 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL
29778 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT 4
29779 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U
29782 * Each bit applies to a single IO. Bit 0 for MIO[52].
29784 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL
29785 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT
29786 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK
29787 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL
29788 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT 5
29789 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U
29792 * Each bit applies to a single IO. Bit 0 for MIO[52].
29794 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL
29795 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT
29796 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK
29797 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL
29798 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT 6
29799 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U
29802 * Each bit applies to a single IO. Bit 0 for MIO[52].
29804 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL
29805 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT
29806 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK
29807 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL
29808 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT 7
29809 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U
29812 * Each bit applies to a single IO. Bit 0 for MIO[52].
29814 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL
29815 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT
29816 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK
29817 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL
29818 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT 8
29819 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U
29822 * Each bit applies to a single IO. Bit 0 for MIO[52].
29824 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL
29825 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT
29826 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK
29827 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL
29828 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT 9
29829 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U
29832 * Each bit applies to a single IO. Bit 0 for MIO[52].
29834 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL
29835 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT
29836 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK
29837 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL
29838 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT 10
29839 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U
29842 * Each bit applies to a single IO. Bit 0 for MIO[52].
29844 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL
29845 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT
29846 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK
29847 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL
29848 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT 11
29849 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U
29852 * Each bit applies to a single IO. Bit 0 for MIO[52].
29854 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL
29855 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT
29856 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK
29857 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL
29858 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT 12
29859 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U
29862 * Each bit applies to a single IO. Bit 0 for MIO[52].
29864 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL
29865 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT
29866 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK
29867 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL
29868 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT 13
29869 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U
29872 * Each bit applies to a single IO. Bit 0 for MIO[52].
29874 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL
29875 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT
29876 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK
29877 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL
29878 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT 14
29879 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U
29882 * Each bit applies to a single IO. Bit 0 for MIO[52].
29884 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL
29885 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT
29886 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK
29887 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL
29888 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT 15
29889 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U
29892 * Each bit applies to a single IO. Bit 0 for MIO[52].
29894 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL
29895 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT
29896 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK
29897 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL
29898 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT 16
29899 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U
29902 * Each bit applies to a single IO. Bit 0 for MIO[52].
29904 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL
29905 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT
29906 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK
29907 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL
29908 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT 17
29909 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U
29912 * Each bit applies to a single IO. Bit 0 for MIO[52].
29914 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL
29915 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT
29916 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK
29917 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL
29918 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT 18
29919 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U
29922 * Each bit applies to a single IO. Bit 0 for MIO[52].
29924 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL
29925 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT
29926 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK
29927 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL
29928 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT 19
29929 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U
29932 * Each bit applies to a single IO. Bit 0 for MIO[52].
29934 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL
29935 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT
29936 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK
29937 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL
29938 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT 20
29939 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U
29942 * Each bit applies to a single IO. Bit 0 for MIO[52].
29944 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL
29945 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT
29946 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK
29947 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL
29948 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT 21
29949 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U
29952 * Each bit applies to a single IO. Bit 0 for MIO[52].
29954 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL
29955 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT
29956 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK
29957 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL
29958 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT 22
29959 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U
29962 * Each bit applies to a single IO. Bit 0 for MIO[52].
29964 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL
29965 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT
29966 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK
29967 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL
29968 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT 23
29969 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U
29972 * Each bit applies to a single IO. Bit 0 for MIO[52].
29974 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL
29975 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT
29976 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK
29977 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL
29978 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT 24
29979 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U
29982 * Each bit applies to a single IO. Bit 0 for MIO[52].
29984 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL
29985 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT
29986 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK
29987 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL
29988 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT 25
29989 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U
29992 * Each bit applies to a single IO. Bit 0 for MIO[52].
29994 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
29995 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
29996 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK
29997 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
29998 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0
29999 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U
30002 * Each bit applies to a single IO. Bit 0 for MIO[52].
30004 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
30005 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
30006 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK
30007 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
30008 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1
30009 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U
30012 * Each bit applies to a single IO. Bit 0 for MIO[52].
30014 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
30015 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
30016 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK
30017 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
30018 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2
30019 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U
30022 * Each bit applies to a single IO. Bit 0 for MIO[52].
30024 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
30025 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
30026 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK
30027 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
30028 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3
30029 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U
30032 * Each bit applies to a single IO. Bit 0 for MIO[52].
30034 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
30035 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
30036 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK
30037 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
30038 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4
30039 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U
30042 * Each bit applies to a single IO. Bit 0 for MIO[52].
30044 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
30045 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
30046 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK
30047 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
30048 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5
30049 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U
30052 * Each bit applies to a single IO. Bit 0 for MIO[52].
30054 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
30055 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
30056 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK
30057 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
30058 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6
30059 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U
30062 * Each bit applies to a single IO. Bit 0 for MIO[52].
30064 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
30065 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
30066 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK
30067 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
30068 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7
30069 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U
30072 * Each bit applies to a single IO. Bit 0 for MIO[52].
30074 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
30075 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
30076 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK
30077 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
30078 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8
30079 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U
30082 * Each bit applies to a single IO. Bit 0 for MIO[52].
30084 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
30085 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
30086 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK
30087 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
30088 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9
30089 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U
30092 * Each bit applies to a single IO. Bit 0 for MIO[52].
30094 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
30095 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
30096 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK
30097 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
30098 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10
30099 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U
30102 * Each bit applies to a single IO. Bit 0 for MIO[52].
30104 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
30105 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
30106 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK
30107 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
30108 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11
30109 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U
30112 * Each bit applies to a single IO. Bit 0 for MIO[52].
30114 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
30115 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
30116 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK
30117 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
30118 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12
30119 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U
30122 * Each bit applies to a single IO. Bit 0 for MIO[52].
30124 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
30125 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
30126 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK
30127 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
30128 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13
30129 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U
30132 * Each bit applies to a single IO. Bit 0 for MIO[52].
30134 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
30135 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
30136 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK
30137 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
30138 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14
30139 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U
30142 * Each bit applies to a single IO. Bit 0 for MIO[52].
30144 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
30145 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
30146 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK
30147 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
30148 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15
30149 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U
30152 * Each bit applies to a single IO. Bit 0 for MIO[52].
30154 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
30155 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
30156 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK
30157 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
30158 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16
30159 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U
30162 * Each bit applies to a single IO. Bit 0 for MIO[52].
30164 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
30165 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
30166 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK
30167 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
30168 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17
30169 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U
30172 * Each bit applies to a single IO. Bit 0 for MIO[52].
30174 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
30175 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
30176 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK
30177 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
30178 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18
30179 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U
30182 * Each bit applies to a single IO. Bit 0 for MIO[52].
30184 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
30185 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
30186 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK
30187 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
30188 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19
30189 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U
30192 * Each bit applies to a single IO. Bit 0 for MIO[52].
30194 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
30195 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
30196 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK
30197 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
30198 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20
30199 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U
30202 * Each bit applies to a single IO. Bit 0 for MIO[52].
30204 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
30205 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
30206 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK
30207 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
30208 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21
30209 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U
30212 * Each bit applies to a single IO. Bit 0 for MIO[52].
30214 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
30215 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
30216 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK
30217 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
30218 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22
30219 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U
30222 * Each bit applies to a single IO. Bit 0 for MIO[52].
30224 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
30225 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
30226 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK
30227 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
30228 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23
30229 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U
30232 * Each bit applies to a single IO. Bit 0 for MIO[52].
30234 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
30235 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
30236 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK
30237 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
30238 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24
30239 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U
30242 * Each bit applies to a single IO. Bit 0 for MIO[52].
30244 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
30245 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
30246 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK
30247 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
30248 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25
30249 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U
30252 * Each bit applies to a single IO. Bit 0 for MIO[52].
30254 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
30255 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
30256 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK
30257 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
30258 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0
30259 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U
30262 * Each bit applies to a single IO. Bit 0 for MIO[52].
30264 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
30265 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
30266 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK
30267 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
30268 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1
30269 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U
30272 * Each bit applies to a single IO. Bit 0 for MIO[52].
30274 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
30275 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
30276 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK
30277 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
30278 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2
30279 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U
30282 * Each bit applies to a single IO. Bit 0 for MIO[52].
30284 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
30285 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
30286 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK
30287 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
30288 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3
30289 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U
30292 * Each bit applies to a single IO. Bit 0 for MIO[52].
30294 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
30295 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
30296 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK
30297 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
30298 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4
30299 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U
30302 * Each bit applies to a single IO. Bit 0 for MIO[52].
30304 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
30305 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
30306 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK
30307 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
30308 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5
30309 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U
30312 * Each bit applies to a single IO. Bit 0 for MIO[52].
30314 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
30315 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
30316 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK
30317 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
30318 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6
30319 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U
30322 * Each bit applies to a single IO. Bit 0 for MIO[52].
30324 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
30325 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
30326 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK
30327 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
30328 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7
30329 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U
30332 * Each bit applies to a single IO. Bit 0 for MIO[52].
30334 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
30335 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
30336 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK
30337 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
30338 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8
30339 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U
30342 * Each bit applies to a single IO. Bit 0 for MIO[52].
30344 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
30345 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
30346 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK
30347 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
30348 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9
30349 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U
30352 * Each bit applies to a single IO. Bit 0 for MIO[52].
30354 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
30355 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
30356 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK
30357 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
30358 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10
30359 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U
30362 * Each bit applies to a single IO. Bit 0 for MIO[52].
30364 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
30365 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
30366 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK
30367 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
30368 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11
30369 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U
30372 * Each bit applies to a single IO. Bit 0 for MIO[52].
30374 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
30375 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
30376 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK
30377 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
30378 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12
30379 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U
30382 * Each bit applies to a single IO. Bit 0 for MIO[52].
30384 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
30385 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
30386 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK
30387 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
30388 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13
30389 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U
30392 * Each bit applies to a single IO. Bit 0 for MIO[52].
30394 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
30395 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
30396 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK
30397 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
30398 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14
30399 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U
30402 * Each bit applies to a single IO. Bit 0 for MIO[52].
30404 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
30405 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
30406 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK
30407 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
30408 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15
30409 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U
30412 * Each bit applies to a single IO. Bit 0 for MIO[52].
30414 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
30415 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
30416 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK
30417 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
30418 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16
30419 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U
30422 * Each bit applies to a single IO. Bit 0 for MIO[52].
30424 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
30425 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
30426 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK
30427 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
30428 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17
30429 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U
30432 * Each bit applies to a single IO. Bit 0 for MIO[52].
30434 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
30435 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
30436 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK
30437 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
30438 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18
30439 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U
30442 * Each bit applies to a single IO. Bit 0 for MIO[52].
30444 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
30445 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
30446 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK
30447 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
30448 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19
30449 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U
30452 * Each bit applies to a single IO. Bit 0 for MIO[52].
30454 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
30455 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
30456 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK
30457 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
30458 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20
30459 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U
30462 * Each bit applies to a single IO. Bit 0 for MIO[52].
30464 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
30465 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
30466 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK
30467 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
30468 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21
30469 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U
30472 * Each bit applies to a single IO. Bit 0 for MIO[52].
30474 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
30475 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
30476 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK
30477 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
30478 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22
30479 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U
30482 * Each bit applies to a single IO. Bit 0 for MIO[52].
30484 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
30485 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
30486 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK
30487 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
30488 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23
30489 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U
30492 * Each bit applies to a single IO. Bit 0 for MIO[52].
30494 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
30495 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
30496 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK
30497 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
30498 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24
30499 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U
30502 * Each bit applies to a single IO. Bit 0 for MIO[52].
30504 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
30505 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
30506 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK
30507 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
30508 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25
30509 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U
30512 * Each bit applies to a single IO. Bit 0 for MIO[52].
30514 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
30515 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT
30516 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK
30517 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
30518 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0
30519 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U
30522 * Each bit applies to a single IO. Bit 0 for MIO[52].
30524 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
30525 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT
30526 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK
30527 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
30528 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1
30529 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U
30532 * Each bit applies to a single IO. Bit 0 for MIO[52].
30534 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
30535 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT
30536 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK
30537 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
30538 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2
30539 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U
30542 * Each bit applies to a single IO. Bit 0 for MIO[52].
30544 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
30545 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT
30546 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK
30547 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
30548 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3
30549 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U
30552 * Each bit applies to a single IO. Bit 0 for MIO[52].
30554 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
30555 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT
30556 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK
30557 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
30558 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4
30559 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U
30562 * Each bit applies to a single IO. Bit 0 for MIO[52].
30564 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
30565 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT
30566 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK
30567 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
30568 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5
30569 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U
30572 * Each bit applies to a single IO. Bit 0 for MIO[52].
30574 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
30575 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT
30576 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK
30577 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
30578 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6
30579 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U
30582 * Each bit applies to a single IO. Bit 0 for MIO[52].
30584 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
30585 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT
30586 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK
30587 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
30588 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7
30589 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U
30592 * Each bit applies to a single IO. Bit 0 for MIO[52].
30594 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
30595 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT
30596 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK
30597 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
30598 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8
30599 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U
30602 * Each bit applies to a single IO. Bit 0 for MIO[52].
30604 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
30605 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT
30606 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK
30607 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
30608 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9
30609 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U
30612 * Each bit applies to a single IO. Bit 0 for MIO[52].
30614 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
30615 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT
30616 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK
30617 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
30618 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10
30619 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U
30622 * Each bit applies to a single IO. Bit 0 for MIO[52].
30624 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
30625 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT
30626 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK
30627 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
30628 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11
30629 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U
30632 * Each bit applies to a single IO. Bit 0 for MIO[52].
30634 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
30635 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT
30636 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK
30637 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
30638 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12
30639 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U
30642 * Each bit applies to a single IO. Bit 0 for MIO[52].
30644 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
30645 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT
30646 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK
30647 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
30648 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13
30649 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U
30652 * Each bit applies to a single IO. Bit 0 for MIO[52].
30654 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
30655 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT
30656 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK
30657 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
30658 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14
30659 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U
30662 * Each bit applies to a single IO. Bit 0 for MIO[52].
30664 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
30665 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT
30666 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK
30667 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
30668 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15
30669 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U
30672 * Each bit applies to a single IO. Bit 0 for MIO[52].
30674 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
30675 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT
30676 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK
30677 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
30678 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16
30679 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U
30682 * Each bit applies to a single IO. Bit 0 for MIO[52].
30684 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
30685 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT
30686 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK
30687 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
30688 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17
30689 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U
30692 * Each bit applies to a single IO. Bit 0 for MIO[52].
30694 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
30695 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT
30696 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK
30697 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
30698 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18
30699 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U
30702 * Each bit applies to a single IO. Bit 0 for MIO[52].
30704 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
30705 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT
30706 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK
30707 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
30708 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19
30709 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U
30712 * Each bit applies to a single IO. Bit 0 for MIO[52].
30714 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
30715 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT
30716 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK
30717 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
30718 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20
30719 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U
30722 * Each bit applies to a single IO. Bit 0 for MIO[52].
30724 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
30725 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT
30726 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK
30727 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
30728 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21
30729 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U
30732 * Each bit applies to a single IO. Bit 0 for MIO[52].
30734 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
30735 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT
30736 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK
30737 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
30738 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22
30739 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U
30742 * Each bit applies to a single IO. Bit 0 for MIO[52].
30744 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
30745 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT
30746 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK
30747 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
30748 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23
30749 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U
30752 * Each bit applies to a single IO. Bit 0 for MIO[52].
30754 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
30755 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT
30756 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK
30757 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
30758 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24
30759 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U
30762 * Each bit applies to a single IO. Bit 0 for MIO[52].
30764 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
30765 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT
30766 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK
30767 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
30768 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25
30769 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U
30772 * Each bit applies to a single IO. Bit 0 for MIO[52].
30774 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
30775 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
30776 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK
30777 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
30778 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0
30779 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U
30782 * Each bit applies to a single IO. Bit 0 for MIO[52].
30784 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
30785 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
30786 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK
30787 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
30788 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1
30789 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U
30792 * Each bit applies to a single IO. Bit 0 for MIO[52].
30794 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
30795 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
30796 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK
30797 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
30798 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2
30799 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U
30802 * Each bit applies to a single IO. Bit 0 for MIO[52].
30804 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
30805 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
30806 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK
30807 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
30808 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3
30809 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U
30812 * Each bit applies to a single IO. Bit 0 for MIO[52].
30814 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
30815 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
30816 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK
30817 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
30818 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4
30819 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U
30822 * Each bit applies to a single IO. Bit 0 for MIO[52].
30824 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
30825 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
30826 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK
30827 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
30828 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5
30829 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U
30832 * Each bit applies to a single IO. Bit 0 for MIO[52].
30834 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
30835 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
30836 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK
30837 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
30838 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6
30839 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U
30842 * Each bit applies to a single IO. Bit 0 for MIO[52].
30844 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
30845 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
30846 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK
30847 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
30848 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7
30849 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U
30852 * Each bit applies to a single IO. Bit 0 for MIO[52].
30854 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
30855 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
30856 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK
30857 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
30858 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8
30859 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U
30862 * Each bit applies to a single IO. Bit 0 for MIO[52].
30864 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
30865 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
30866 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK
30867 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
30868 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9
30869 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U
30872 * Each bit applies to a single IO. Bit 0 for MIO[52].
30874 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
30875 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
30876 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK
30877 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
30878 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10
30879 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U
30882 * Each bit applies to a single IO. Bit 0 for MIO[52].
30884 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
30885 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
30886 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK
30887 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
30888 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11
30889 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U
30892 * Each bit applies to a single IO. Bit 0 for MIO[52].
30894 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
30895 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
30896 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK
30897 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
30898 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12
30899 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U
30902 * Each bit applies to a single IO. Bit 0 for MIO[52].
30904 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
30905 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
30906 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK
30907 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
30908 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13
30909 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U
30912 * Each bit applies to a single IO. Bit 0 for MIO[52].
30914 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
30915 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
30916 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK
30917 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
30918 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14
30919 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U
30922 * Each bit applies to a single IO. Bit 0 for MIO[52].
30924 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
30925 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
30926 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK
30927 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
30928 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15
30929 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U
30932 * Each bit applies to a single IO. Bit 0 for MIO[52].
30934 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
30935 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
30936 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK
30937 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
30938 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16
30939 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U
30942 * Each bit applies to a single IO. Bit 0 for MIO[52].
30944 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
30945 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
30946 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK
30947 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
30948 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17
30949 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U
30952 * Each bit applies to a single IO. Bit 0 for MIO[52].
30954 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
30955 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
30956 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK
30957 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
30958 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18
30959 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U
30962 * Each bit applies to a single IO. Bit 0 for MIO[52].
30964 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
30965 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
30966 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK
30967 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
30968 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19
30969 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U
30972 * Each bit applies to a single IO. Bit 0 for MIO[52].
30974 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
30975 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
30976 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK
30977 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
30978 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20
30979 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U
30982 * Each bit applies to a single IO. Bit 0 for MIO[52].
30984 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
30985 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
30986 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK
30987 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
30988 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21
30989 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U
30992 * Each bit applies to a single IO. Bit 0 for MIO[52].
30994 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
30995 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
30996 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK
30997 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
30998 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22
30999 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U
31002 * Each bit applies to a single IO. Bit 0 for MIO[52].
31004 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
31005 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
31006 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK
31007 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
31008 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23
31009 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U
31012 * Each bit applies to a single IO. Bit 0 for MIO[52].
31014 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
31015 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
31016 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK
31017 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
31018 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24
31019 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U
31022 * Each bit applies to a single IO. Bit 0 for MIO[52].
31024 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
31025 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
31026 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK
31027 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
31028 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25
31029 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U
31032 * I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1
31033 * = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs
31036 #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL
31037 #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT
31038 #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK
31039 #define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL 0x00000000
31040 #define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT 3
31041 #define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK 0x00000008U
31044 * CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1
31045 * = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx.
31047 #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL
31048 #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT
31049 #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK
31050 #define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL 0x00000000
31051 #define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT 2
31052 #define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK 0x00000004U
31055 * UART Loopback Control. 0 = Connect UART inputs according to MIO mapping.
31056 * 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0
31057 * inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD
31060 #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL
31061 #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT
31062 #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK
31063 #define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL 0x00000000
31064 #define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT 1
31065 #define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK 0x00000002U
31068 * SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1
31069 * = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs
31070 * . The other SPI core will appear on the LS Slave Select.
31072 #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL
31073 #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT
31074 #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK
31075 #define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 0x00000000
31076 #define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 0
31077 #define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 0x00000001U
31078 #undef CRF_APB_RST_FPD_TOP_OFFSET
31079 #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
31080 #undef CRL_APB_RST_LPD_IOU2_OFFSET
31081 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
31082 #undef CRL_APB_RST_LPD_TOP_OFFSET
31083 #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
31084 #undef CRL_APB_RST_LPD_IOU0_OFFSET
31085 #define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230
31086 #undef CRL_APB_RST_LPD_IOU2_OFFSET
31087 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
31088 #undef IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET
31089 #define IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET 0XFF180390
31090 #undef CRL_APB_RST_LPD_TOP_OFFSET
31091 #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
31092 #undef USB3_0_FPD_POWER_PRSNT_OFFSET
31093 #define USB3_0_FPD_POWER_PRSNT_OFFSET 0XFF9D0080
31094 #undef USB3_0_FPD_PIPE_CLK_OFFSET
31095 #define USB3_0_FPD_PIPE_CLK_OFFSET 0XFF9D007C
31096 #undef CRL_APB_RST_LPD_IOU2_OFFSET
31097 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
31098 #undef IOU_SLCR_CTRL_REG_SD_OFFSET
31099 #define IOU_SLCR_CTRL_REG_SD_OFFSET 0XFF180310
31100 #undef IOU_SLCR_SD_CONFIG_REG2_OFFSET
31101 #define IOU_SLCR_SD_CONFIG_REG2_OFFSET 0XFF180320
31102 #undef IOU_SLCR_SD_CONFIG_REG1_OFFSET
31103 #define IOU_SLCR_SD_CONFIG_REG1_OFFSET 0XFF18031C
31104 #undef IOU_SLCR_SD_DLL_CTRL_OFFSET
31105 #define IOU_SLCR_SD_DLL_CTRL_OFFSET 0XFF180358
31106 #undef IOU_SLCR_SD_CONFIG_REG3_OFFSET
31107 #define IOU_SLCR_SD_CONFIG_REG3_OFFSET 0XFF180324
31108 #undef CRL_APB_RST_LPD_IOU2_OFFSET
31109 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
31110 #undef CRL_APB_RST_LPD_IOU2_OFFSET
31111 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
31112 #undef CRL_APB_RST_LPD_IOU2_OFFSET
31113 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
31114 #undef CRL_APB_RST_LPD_IOU2_OFFSET
31115 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
31116 #undef CRL_APB_RST_LPD_IOU2_OFFSET
31117 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
31118 #undef UART0_BAUD_RATE_DIVIDER_REG0_OFFSET
31119 #define UART0_BAUD_RATE_DIVIDER_REG0_OFFSET 0XFF000034
31120 #undef UART0_BAUD_RATE_GEN_REG0_OFFSET
31121 #define UART0_BAUD_RATE_GEN_REG0_OFFSET 0XFF000018
31122 #undef UART0_CONTROL_REG0_OFFSET
31123 #define UART0_CONTROL_REG0_OFFSET 0XFF000000
31124 #undef UART0_MODE_REG0_OFFSET
31125 #define UART0_MODE_REG0_OFFSET 0XFF000004
31126 #undef UART1_BAUD_RATE_DIVIDER_REG0_OFFSET
31127 #define UART1_BAUD_RATE_DIVIDER_REG0_OFFSET 0XFF010034
31128 #undef UART1_BAUD_RATE_GEN_REG0_OFFSET
31129 #define UART1_BAUD_RATE_GEN_REG0_OFFSET 0XFF010018
31130 #undef UART1_CONTROL_REG0_OFFSET
31131 #define UART1_CONTROL_REG0_OFFSET 0XFF010000
31132 #undef UART1_MODE_REG0_OFFSET
31133 #define UART1_MODE_REG0_OFFSET 0XFF010004
31134 #undef CRL_APB_RST_LPD_IOU2_OFFSET
31135 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
31136 #undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET
31137 #define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 0XFF4B0024
31138 #undef CSU_TAMPER_STATUS_OFFSET
31139 #define CSU_TAMPER_STATUS_OFFSET 0XFFCA5000
31140 #undef APU_ACE_CTRL_OFFSET
31141 #define APU_ACE_CTRL_OFFSET 0XFD5C0060
31142 #undef RTC_CONTROL_OFFSET
31143 #define RTC_CONTROL_OFFSET 0XFFA60040
31144 #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET
31145 #define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET 0XFF260020
31146 #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET
31147 #define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET 0XFF260000
31148 #undef GPIO_DIRM_1_OFFSET
31149 #define GPIO_DIRM_1_OFFSET 0XFF0A0244
31150 #undef GPIO_OEN_1_OFFSET
31151 #define GPIO_OEN_1_OFFSET 0XFF0A0248
31152 #undef GPIO_MASK_DATA_1_LSW_OFFSET
31153 #define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008
31154 #undef GPIO_MASK_DATA_1_LSW_OFFSET
31155 #define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008
31158 * PCIE config reset
31160 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL
31161 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
31162 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK
31163 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE
31164 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19
31165 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U
31168 * PCIE control block level reset
31170 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL
31171 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
31172 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK
31173 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE
31174 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17
31175 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U
31178 * PCIE bridge block level reset (AXI interface)
31180 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL
31181 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
31182 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK
31183 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE
31184 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18
31185 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U
31188 * Display Port block level reset (includes DPDMA)
31190 #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL
31191 #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
31192 #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK
31193 #define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE
31194 #define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16
31195 #define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U
31200 #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL
31201 #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT
31202 #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK
31203 #define CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL 0x000F9FFE
31204 #define CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT 15
31205 #define CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK 0x00008000U
31208 * GDMA block level reset
31210 #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL
31211 #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT
31212 #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK
31213 #define CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL 0x000F9FFE
31214 #define CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT 6
31215 #define CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK 0x00000040U
31218 * Pixel Processor (submodule of GPU) block level reset
31220 #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL
31221 #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT
31222 #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK
31223 #define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL 0x000F9FFE
31224 #define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT 4
31225 #define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK 0x00000010U
31228 * Pixel Processor (submodule of GPU) block level reset
31230 #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL
31231 #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT
31232 #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK
31233 #define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL 0x000F9FFE
31234 #define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT 5
31235 #define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK 0x00000020U
31238 * GPU block level reset
31240 #undef CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL
31241 #undef CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT
31242 #undef CRF_APB_RST_FPD_TOP_GPU_RESET_MASK
31243 #define CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL 0x000F9FFE
31244 #define CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT 3
31245 #define CRF_APB_RST_FPD_TOP_GPU_RESET_MASK 0x00000008U
31248 * GT block level reset
31250 #undef CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL
31251 #undef CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT
31252 #undef CRF_APB_RST_FPD_TOP_GT_RESET_MASK
31253 #define CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL 0x000F9FFE
31254 #define CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT 2
31255 #define CRF_APB_RST_FPD_TOP_GT_RESET_MASK 0x00000004U
31258 * Sata block level reset
31260 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL
31261 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
31262 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK
31263 #define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE
31264 #define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1
31265 #define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U
31268 * Block level reset
31270 #undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL
31271 #undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT
31272 #undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK
31273 #define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL 0x0017FFFF
31274 #define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT 20
31275 #define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK 0x00100000U
31278 * Block level reset
31280 #undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_DEFVAL
31281 #undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_SHIFT
31282 #undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK
31283 #define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_DEFVAL 0x0017FFFF
31284 #define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_SHIFT 19
31285 #define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK 0x00080000U
31288 * Block level reset
31290 #undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_DEFVAL
31291 #undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_SHIFT
31292 #undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK
31293 #define CRL_APB_RST_LPD_IOU2_ADMA_RESET_DEFVAL 0x0017FFFF
31294 #define CRL_APB_RST_LPD_IOU2_ADMA_RESET_SHIFT 17
31295 #define CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK 0x00020000U
31298 * Reset entire full power domain.
31300 #undef CRL_APB_RST_LPD_TOP_FPD_RESET_DEFVAL
31301 #undef CRL_APB_RST_LPD_TOP_FPD_RESET_SHIFT
31302 #undef CRL_APB_RST_LPD_TOP_FPD_RESET_MASK
31303 #define CRL_APB_RST_LPD_TOP_FPD_RESET_DEFVAL 0x00188FDF
31304 #define CRL_APB_RST_LPD_TOP_FPD_RESET_SHIFT 23
31305 #define CRL_APB_RST_LPD_TOP_FPD_RESET_MASK 0x00800000U
31310 #undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_DEFVAL
31311 #undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_SHIFT
31312 #undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK
31313 #define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_DEFVAL 0x00188FDF
31314 #define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_SHIFT 20
31315 #define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK 0x00100000U
31320 #undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_DEFVAL
31321 #undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_SHIFT
31322 #undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK
31323 #define CRL_APB_RST_LPD_TOP_SYSMON_RESET_DEFVAL 0x00188FDF
31324 #define CRL_APB_RST_LPD_TOP_SYSMON_RESET_SHIFT 17
31325 #define CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK 0x00020000U
31328 * Real Time Clock reset
31330 #undef CRL_APB_RST_LPD_TOP_RTC_RESET_DEFVAL
31331 #undef CRL_APB_RST_LPD_TOP_RTC_RESET_SHIFT
31332 #undef CRL_APB_RST_LPD_TOP_RTC_RESET_MASK
31333 #define CRL_APB_RST_LPD_TOP_RTC_RESET_DEFVAL 0x00188FDF
31334 #define CRL_APB_RST_LPD_TOP_RTC_RESET_SHIFT 16
31335 #define CRL_APB_RST_LPD_TOP_RTC_RESET_MASK 0x00010000U
31340 #undef CRL_APB_RST_LPD_TOP_APM_RESET_DEFVAL
31341 #undef CRL_APB_RST_LPD_TOP_APM_RESET_SHIFT
31342 #undef CRL_APB_RST_LPD_TOP_APM_RESET_MASK
31343 #define CRL_APB_RST_LPD_TOP_APM_RESET_DEFVAL 0x00188FDF
31344 #define CRL_APB_RST_LPD_TOP_APM_RESET_SHIFT 15
31345 #define CRL_APB_RST_LPD_TOP_APM_RESET_MASK 0x00008000U
31350 #undef CRL_APB_RST_LPD_TOP_IPI_RESET_DEFVAL
31351 #undef CRL_APB_RST_LPD_TOP_IPI_RESET_SHIFT
31352 #undef CRL_APB_RST_LPD_TOP_IPI_RESET_MASK
31353 #define CRL_APB_RST_LPD_TOP_IPI_RESET_DEFVAL 0x00188FDF
31354 #define CRL_APB_RST_LPD_TOP_IPI_RESET_SHIFT 14
31355 #define CRL_APB_RST_LPD_TOP_IPI_RESET_MASK 0x00004000U
31358 * reset entire RPU power island
31360 #undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_DEFVAL
31361 #undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_SHIFT
31362 #undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK
31363 #define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_DEFVAL 0x00188FDF
31364 #define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_SHIFT 4
31365 #define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK 0x00000010U
31370 #undef CRL_APB_RST_LPD_TOP_OCM_RESET_DEFVAL
31371 #undef CRL_APB_RST_LPD_TOP_OCM_RESET_SHIFT
31372 #undef CRL_APB_RST_LPD_TOP_OCM_RESET_MASK
31373 #define CRL_APB_RST_LPD_TOP_OCM_RESET_DEFVAL 0x00188FDF
31374 #define CRL_APB_RST_LPD_TOP_OCM_RESET_SHIFT 3
31375 #define CRL_APB_RST_LPD_TOP_OCM_RESET_MASK 0x00000008U
31380 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL
31381 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
31382 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK
31383 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F
31384 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3
31385 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U
31388 * Block level reset
31390 #undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL
31391 #undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT
31392 #undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK
31393 #define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL 0x0017FFFF
31394 #define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 0
31395 #define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 0x00000001U
31398 * 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa
31399 * ss the Tap delay on the Rx clock signal of LQSPI
31401 #undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL
31402 #undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT
31403 #undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK
31404 #define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL 0x00000007
31405 #define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 2
31406 #define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U
31409 * USB 0 reset for control registers
31411 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL
31412 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
31413 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK
31414 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF
31415 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10
31416 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U
31419 * USB 0 sleep circuit reset
31421 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL
31422 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
31423 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK
31424 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF
31425 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8
31426 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U
31431 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL
31432 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
31433 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK
31434 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF
31435 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6
31436 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U
31439 * This bit is used to choose between PIPE power present and 1'b1
31441 #undef USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL
31442 #undef USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT
31443 #undef USB3_0_FPD_POWER_PRSNT_OPTION_MASK
31444 #define USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL
31445 #define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT 0
31446 #define USB3_0_FPD_POWER_PRSNT_OPTION_MASK 0x00000001U
31449 * This bit is used to choose between PIPE clock coming from SerDes and the
31452 #undef USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL
31453 #undef USB3_0_FPD_PIPE_CLK_OPTION_SHIFT
31454 #undef USB3_0_FPD_PIPE_CLK_OPTION_MASK
31455 #define USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL
31456 #define USB3_0_FPD_PIPE_CLK_OPTION_SHIFT 0
31457 #define USB3_0_FPD_PIPE_CLK_OPTION_MASK 0x00000001U
31460 * Block level reset
31462 #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL
31463 #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT
31464 #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK
31465 #define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL 0x0017FFFF
31466 #define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT 6
31467 #define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK 0x00000040U
31470 * SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled
31472 #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL
31473 #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT
31474 #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK
31475 #define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL 0x00000000
31476 #define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT 15
31477 #define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK 0x00008000U
31480 * Should be set based on the final product usage 00 - Removable SCard Slot
31481 * 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved
31483 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL
31484 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT
31485 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK
31486 #define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL 0x0FFC0FFC
31487 #define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT 28
31488 #define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK 0x30000000U
31491 * 1.8V Support 1: 1.8V supported 0: 1.8V not supported support
31493 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL
31494 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT
31495 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK
31496 #define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL 0x0FFC0FFC
31497 #define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT 25
31498 #define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK 0x02000000U
31501 * 3.0V Support 1: 3.0V supported 0: 3.0V not supported support
31503 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL
31504 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT
31505 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK
31506 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL 0x0FFC0FFC
31507 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT 24
31508 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK 0x01000000U
31511 * 3.3V Support 1: 3.3V supported 0: 3.3V not supported support
31513 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL
31514 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT
31515 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK
31516 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL 0x0FFC0FFC
31517 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT 23
31518 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK 0x00800000U
31521 * Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.
31523 #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL
31524 #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT
31525 #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK
31526 #define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL 0x32403240
31527 #define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT 23
31528 #define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK 0x7F800000U
31531 * Configures the Number of Taps (Phases) of the rxclk_in that is supported
31534 #undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_DEFVAL
31535 #undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_SHIFT
31536 #undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_MASK
31537 #define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_DEFVAL 0x32403240
31538 #define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_SHIFT 17
31539 #define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_MASK 0x007E0000U
31544 #undef IOU_SLCR_SD_DLL_CTRL_RESERVED_DEFVAL
31545 #undef IOU_SLCR_SD_DLL_CTRL_RESERVED_SHIFT
31546 #undef IOU_SLCR_SD_DLL_CTRL_RESERVED_MASK
31547 #define IOU_SLCR_SD_DLL_CTRL_RESERVED_DEFVAL 0x00080008
31548 #define IOU_SLCR_SD_DLL_CTRL_RESERVED_SHIFT 3
31549 #define IOU_SLCR_SD_DLL_CTRL_RESERVED_MASK 0x00000008U
31552 * This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. S
31553 * etting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other
31554 * source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n
31555 * = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved
31557 #undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL
31558 #undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT
31559 #undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK
31560 #define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL 0x06070607
31561 #define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT 22
31562 #define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK 0x03C00000U
31565 * Block level reset
31567 #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL
31568 #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT
31569 #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK
31570 #define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL 0x0017FFFF
31571 #define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 8
31572 #define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK 0x00000100U
31575 * Block level reset
31577 #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL
31578 #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT
31579 #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK
31580 #define CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL 0x0017FFFF
31581 #define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 9
31582 #define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK 0x00000200U
31585 * Block level reset
31587 #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL
31588 #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT
31589 #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK
31590 #define CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL 0x0017FFFF
31591 #define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT 10
31592 #define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK 0x00000400U
31595 * Block level reset
31597 #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL
31598 #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT
31599 #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK
31600 #define CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL 0x0017FFFF
31601 #define CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT 15
31602 #define CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK 0x00008000U
31605 * Block level reset
31607 #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL
31608 #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT
31609 #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK
31610 #define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL 0x0017FFFF
31611 #define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 11
31612 #define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK 0x00000800U
31615 * Block level reset
31617 #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL
31618 #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT
31619 #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK
31620 #define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL 0x0017FFFF
31621 #define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 12
31622 #define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK 0x00001000U
31625 * Block level reset
31627 #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL
31628 #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT
31629 #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK
31630 #define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL 0x0017FFFF
31631 #define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 13
31632 #define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK 0x00002000U
31635 * Block level reset
31637 #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL
31638 #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT
31639 #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK
31640 #define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL 0x0017FFFF
31641 #define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 14
31642 #define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK 0x00004000U
31645 * Block level reset
31647 #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL
31648 #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT
31649 #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK
31650 #define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL 0x0017FFFF
31651 #define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 1
31652 #define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK 0x00000002U
31655 * Block level reset
31657 #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL
31658 #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT
31659 #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK
31660 #define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL 0x0017FFFF
31661 #define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 2
31662 #define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 0x00000004U
31665 * Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
31667 #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL
31668 #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
31669 #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK
31670 #define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F
31671 #define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0
31672 #define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU
31675 * Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor
31676 * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
31678 #undef UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL
31679 #undef UART0_BAUD_RATE_GEN_REG0_CD_SHIFT
31680 #undef UART0_BAUD_RATE_GEN_REG0_CD_MASK
31681 #define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B
31682 #define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 0
31683 #define UART0_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU
31686 * Stop transmitter break: 0: no affect 1: stop transmission of the break a
31687 * fter a minimum of one character length and transmit a high level during
31688 * 12 bit periods. It can be set regardless of the value of STTBRK.
31690 #undef UART0_CONTROL_REG0_STPBRK_DEFVAL
31691 #undef UART0_CONTROL_REG0_STPBRK_SHIFT
31692 #undef UART0_CONTROL_REG0_STPBRK_MASK
31693 #define UART0_CONTROL_REG0_STPBRK_DEFVAL 0x00000128
31694 #define UART0_CONTROL_REG0_STPBRK_SHIFT 8
31695 #define UART0_CONTROL_REG0_STPBRK_MASK 0x00000100U
31698 * Start transmitter break: 0: no affect 1: start to transmit a break after
31699 * the characters currently present in the FIFO and the transmit shift reg
31700 * ister have been transmitted. It can only be set if STPBRK (Stop transmit
31701 * ter break) is not high.
31703 #undef UART0_CONTROL_REG0_STTBRK_DEFVAL
31704 #undef UART0_CONTROL_REG0_STTBRK_SHIFT
31705 #undef UART0_CONTROL_REG0_STTBRK_MASK
31706 #define UART0_CONTROL_REG0_STTBRK_DEFVAL 0x00000128
31707 #define UART0_CONTROL_REG0_STTBRK_SHIFT 7
31708 #define UART0_CONTROL_REG0_STTBRK_MASK 0x00000080U
31711 * Restart receiver timeout counter: 1: receiver timeout counter is restart
31712 * ed. This bit is self clearing once the restart has completed.
31714 #undef UART0_CONTROL_REG0_RSTTO_DEFVAL
31715 #undef UART0_CONTROL_REG0_RSTTO_SHIFT
31716 #undef UART0_CONTROL_REG0_RSTTO_MASK
31717 #define UART0_CONTROL_REG0_RSTTO_DEFVAL 0x00000128
31718 #define UART0_CONTROL_REG0_RSTTO_SHIFT 6
31719 #define UART0_CONTROL_REG0_RSTTO_MASK 0x00000040U
31722 * Transmit disable: 0: enable transmitter 1: disable transmitter
31724 #undef UART0_CONTROL_REG0_TXDIS_DEFVAL
31725 #undef UART0_CONTROL_REG0_TXDIS_SHIFT
31726 #undef UART0_CONTROL_REG0_TXDIS_MASK
31727 #define UART0_CONTROL_REG0_TXDIS_DEFVAL 0x00000128
31728 #define UART0_CONTROL_REG0_TXDIS_SHIFT 5
31729 #define UART0_CONTROL_REG0_TXDIS_MASK 0x00000020U
31732 * Transmit enable: 0: disable transmitter 1: enable transmitter, provided
31733 * the TXDIS field is set to 0.
31735 #undef UART0_CONTROL_REG0_TXEN_DEFVAL
31736 #undef UART0_CONTROL_REG0_TXEN_SHIFT
31737 #undef UART0_CONTROL_REG0_TXEN_MASK
31738 #define UART0_CONTROL_REG0_TXEN_DEFVAL 0x00000128
31739 #define UART0_CONTROL_REG0_TXEN_SHIFT 4
31740 #define UART0_CONTROL_REG0_TXEN_MASK 0x00000010U
31743 * Receive disable: 0: enable 1: disable, regardless of the value of RXEN
31745 #undef UART0_CONTROL_REG0_RXDIS_DEFVAL
31746 #undef UART0_CONTROL_REG0_RXDIS_SHIFT
31747 #undef UART0_CONTROL_REG0_RXDIS_MASK
31748 #define UART0_CONTROL_REG0_RXDIS_DEFVAL 0x00000128
31749 #define UART0_CONTROL_REG0_RXDIS_SHIFT 3
31750 #define UART0_CONTROL_REG0_RXDIS_MASK 0x00000008U
31753 * Receive enable: 0: disable 1: enable When set to one, the receiver logic
31754 * is enabled, provided the RXDIS field is set to zero.
31756 #undef UART0_CONTROL_REG0_RXEN_DEFVAL
31757 #undef UART0_CONTROL_REG0_RXEN_SHIFT
31758 #undef UART0_CONTROL_REG0_RXEN_MASK
31759 #define UART0_CONTROL_REG0_RXEN_DEFVAL 0x00000128
31760 #define UART0_CONTROL_REG0_RXEN_SHIFT 2
31761 #define UART0_CONTROL_REG0_RXEN_MASK 0x00000004U
31764 * Software reset for Tx data path: 0: no affect 1: transmitter logic is re
31765 * set and all pending transmitter data is discarded This bit is self clear
31766 * ing once the reset has completed.
31768 #undef UART0_CONTROL_REG0_TXRES_DEFVAL
31769 #undef UART0_CONTROL_REG0_TXRES_SHIFT
31770 #undef UART0_CONTROL_REG0_TXRES_MASK
31771 #define UART0_CONTROL_REG0_TXRES_DEFVAL 0x00000128
31772 #define UART0_CONTROL_REG0_TXRES_SHIFT 1
31773 #define UART0_CONTROL_REG0_TXRES_MASK 0x00000002U
31776 * Software reset for Rx data path: 0: no affect 1: receiver logic is reset
31777 * and all pending receiver data is discarded. This bit is self clearing o
31778 * nce the reset has completed.
31780 #undef UART0_CONTROL_REG0_RXRES_DEFVAL
31781 #undef UART0_CONTROL_REG0_RXRES_SHIFT
31782 #undef UART0_CONTROL_REG0_RXRES_MASK
31783 #define UART0_CONTROL_REG0_RXRES_DEFVAL 0x00000128
31784 #define UART0_CONTROL_REG0_RXRES_SHIFT 0
31785 #define UART0_CONTROL_REG0_RXRES_MASK 0x00000001U
31788 * Channel mode: Defines the mode of operation of the UART. 00: normal 01:
31789 * automatic echo 10: local loopback 11: remote loopback
31791 #undef UART0_MODE_REG0_CHMODE_DEFVAL
31792 #undef UART0_MODE_REG0_CHMODE_SHIFT
31793 #undef UART0_MODE_REG0_CHMODE_MASK
31794 #define UART0_MODE_REG0_CHMODE_DEFVAL 0x00000000
31795 #define UART0_MODE_REG0_CHMODE_SHIFT 8
31796 #define UART0_MODE_REG0_CHMODE_MASK 0x00000300U
31799 * Number of stop bits: Defines the number of stop bits to detect on receiv
31800 * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st
31801 * op bits 11: reserved
31803 #undef UART0_MODE_REG0_NBSTOP_DEFVAL
31804 #undef UART0_MODE_REG0_NBSTOP_SHIFT
31805 #undef UART0_MODE_REG0_NBSTOP_MASK
31806 #define UART0_MODE_REG0_NBSTOP_DEFVAL 0x00000000
31807 #define UART0_MODE_REG0_NBSTOP_SHIFT 6
31808 #define UART0_MODE_REG0_NBSTOP_MASK 0x000000C0U
31811 * Parity type select: Defines the expected parity to check on receive and
31812 * the parity to generate on transmit. 000: even parity 001: odd parity 010
31813 * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari
31816 #undef UART0_MODE_REG0_PAR_DEFVAL
31817 #undef UART0_MODE_REG0_PAR_SHIFT
31818 #undef UART0_MODE_REG0_PAR_MASK
31819 #define UART0_MODE_REG0_PAR_DEFVAL 0x00000000
31820 #define UART0_MODE_REG0_PAR_SHIFT 3
31821 #define UART0_MODE_REG0_PAR_MASK 0x00000038U
31824 * Character length select: Defines the number of bits in each character. 1
31825 * 1: 6 bits 10: 7 bits 0x: 8 bits
31827 #undef UART0_MODE_REG0_CHRL_DEFVAL
31828 #undef UART0_MODE_REG0_CHRL_SHIFT
31829 #undef UART0_MODE_REG0_CHRL_MASK
31830 #define UART0_MODE_REG0_CHRL_DEFVAL 0x00000000
31831 #define UART0_MODE_REG0_CHRL_SHIFT 1
31832 #define UART0_MODE_REG0_CHRL_MASK 0x00000006U
31835 * Clock source select: This field defines whether a pre-scalar of 8 is app
31836 * lied to the baud rate generator input clock. 0: clock source is uart_ref
31837 * _clk 1: clock source is uart_ref_clk/8
31839 #undef UART0_MODE_REG0_CLKS_DEFVAL
31840 #undef UART0_MODE_REG0_CLKS_SHIFT
31841 #undef UART0_MODE_REG0_CLKS_MASK
31842 #define UART0_MODE_REG0_CLKS_DEFVAL 0x00000000
31843 #define UART0_MODE_REG0_CLKS_SHIFT 0
31844 #define UART0_MODE_REG0_CLKS_MASK 0x00000001U
31847 * Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
31849 #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL
31850 #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
31851 #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK
31852 #define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F
31853 #define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0
31854 #define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU
31857 * Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor
31858 * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
31860 #undef UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL
31861 #undef UART1_BAUD_RATE_GEN_REG0_CD_SHIFT
31862 #undef UART1_BAUD_RATE_GEN_REG0_CD_MASK
31863 #define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B
31864 #define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 0
31865 #define UART1_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU
31868 * Stop transmitter break: 0: no affect 1: stop transmission of the break a
31869 * fter a minimum of one character length and transmit a high level during
31870 * 12 bit periods. It can be set regardless of the value of STTBRK.
31872 #undef UART1_CONTROL_REG0_STPBRK_DEFVAL
31873 #undef UART1_CONTROL_REG0_STPBRK_SHIFT
31874 #undef UART1_CONTROL_REG0_STPBRK_MASK
31875 #define UART1_CONTROL_REG0_STPBRK_DEFVAL 0x00000128
31876 #define UART1_CONTROL_REG0_STPBRK_SHIFT 8
31877 #define UART1_CONTROL_REG0_STPBRK_MASK 0x00000100U
31880 * Start transmitter break: 0: no affect 1: start to transmit a break after
31881 * the characters currently present in the FIFO and the transmit shift reg
31882 * ister have been transmitted. It can only be set if STPBRK (Stop transmit
31883 * ter break) is not high.
31885 #undef UART1_CONTROL_REG0_STTBRK_DEFVAL
31886 #undef UART1_CONTROL_REG0_STTBRK_SHIFT
31887 #undef UART1_CONTROL_REG0_STTBRK_MASK
31888 #define UART1_CONTROL_REG0_STTBRK_DEFVAL 0x00000128
31889 #define UART1_CONTROL_REG0_STTBRK_SHIFT 7
31890 #define UART1_CONTROL_REG0_STTBRK_MASK 0x00000080U
31893 * Restart receiver timeout counter: 1: receiver timeout counter is restart
31894 * ed. This bit is self clearing once the restart has completed.
31896 #undef UART1_CONTROL_REG0_RSTTO_DEFVAL
31897 #undef UART1_CONTROL_REG0_RSTTO_SHIFT
31898 #undef UART1_CONTROL_REG0_RSTTO_MASK
31899 #define UART1_CONTROL_REG0_RSTTO_DEFVAL 0x00000128
31900 #define UART1_CONTROL_REG0_RSTTO_SHIFT 6
31901 #define UART1_CONTROL_REG0_RSTTO_MASK 0x00000040U
31904 * Transmit disable: 0: enable transmitter 1: disable transmitter
31906 #undef UART1_CONTROL_REG0_TXDIS_DEFVAL
31907 #undef UART1_CONTROL_REG0_TXDIS_SHIFT
31908 #undef UART1_CONTROL_REG0_TXDIS_MASK
31909 #define UART1_CONTROL_REG0_TXDIS_DEFVAL 0x00000128
31910 #define UART1_CONTROL_REG0_TXDIS_SHIFT 5
31911 #define UART1_CONTROL_REG0_TXDIS_MASK 0x00000020U
31914 * Transmit enable: 0: disable transmitter 1: enable transmitter, provided
31915 * the TXDIS field is set to 0.
31917 #undef UART1_CONTROL_REG0_TXEN_DEFVAL
31918 #undef UART1_CONTROL_REG0_TXEN_SHIFT
31919 #undef UART1_CONTROL_REG0_TXEN_MASK
31920 #define UART1_CONTROL_REG0_TXEN_DEFVAL 0x00000128
31921 #define UART1_CONTROL_REG0_TXEN_SHIFT 4
31922 #define UART1_CONTROL_REG0_TXEN_MASK 0x00000010U
31925 * Receive disable: 0: enable 1: disable, regardless of the value of RXEN
31927 #undef UART1_CONTROL_REG0_RXDIS_DEFVAL
31928 #undef UART1_CONTROL_REG0_RXDIS_SHIFT
31929 #undef UART1_CONTROL_REG0_RXDIS_MASK
31930 #define UART1_CONTROL_REG0_RXDIS_DEFVAL 0x00000128
31931 #define UART1_CONTROL_REG0_RXDIS_SHIFT 3
31932 #define UART1_CONTROL_REG0_RXDIS_MASK 0x00000008U
31935 * Receive enable: 0: disable 1: enable When set to one, the receiver logic
31936 * is enabled, provided the RXDIS field is set to zero.
31938 #undef UART1_CONTROL_REG0_RXEN_DEFVAL
31939 #undef UART1_CONTROL_REG0_RXEN_SHIFT
31940 #undef UART1_CONTROL_REG0_RXEN_MASK
31941 #define UART1_CONTROL_REG0_RXEN_DEFVAL 0x00000128
31942 #define UART1_CONTROL_REG0_RXEN_SHIFT 2
31943 #define UART1_CONTROL_REG0_RXEN_MASK 0x00000004U
31946 * Software reset for Tx data path: 0: no affect 1: transmitter logic is re
31947 * set and all pending transmitter data is discarded This bit is self clear
31948 * ing once the reset has completed.
31950 #undef UART1_CONTROL_REG0_TXRES_DEFVAL
31951 #undef UART1_CONTROL_REG0_TXRES_SHIFT
31952 #undef UART1_CONTROL_REG0_TXRES_MASK
31953 #define UART1_CONTROL_REG0_TXRES_DEFVAL 0x00000128
31954 #define UART1_CONTROL_REG0_TXRES_SHIFT 1
31955 #define UART1_CONTROL_REG0_TXRES_MASK 0x00000002U
31958 * Software reset for Rx data path: 0: no affect 1: receiver logic is reset
31959 * and all pending receiver data is discarded. This bit is self clearing o
31960 * nce the reset has completed.
31962 #undef UART1_CONTROL_REG0_RXRES_DEFVAL
31963 #undef UART1_CONTROL_REG0_RXRES_SHIFT
31964 #undef UART1_CONTROL_REG0_RXRES_MASK
31965 #define UART1_CONTROL_REG0_RXRES_DEFVAL 0x00000128
31966 #define UART1_CONTROL_REG0_RXRES_SHIFT 0
31967 #define UART1_CONTROL_REG0_RXRES_MASK 0x00000001U
31970 * Channel mode: Defines the mode of operation of the UART. 00: normal 01:
31971 * automatic echo 10: local loopback 11: remote loopback
31973 #undef UART1_MODE_REG0_CHMODE_DEFVAL
31974 #undef UART1_MODE_REG0_CHMODE_SHIFT
31975 #undef UART1_MODE_REG0_CHMODE_MASK
31976 #define UART1_MODE_REG0_CHMODE_DEFVAL 0x00000000
31977 #define UART1_MODE_REG0_CHMODE_SHIFT 8
31978 #define UART1_MODE_REG0_CHMODE_MASK 0x00000300U
31981 * Number of stop bits: Defines the number of stop bits to detect on receiv
31982 * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st
31983 * op bits 11: reserved
31985 #undef UART1_MODE_REG0_NBSTOP_DEFVAL
31986 #undef UART1_MODE_REG0_NBSTOP_SHIFT
31987 #undef UART1_MODE_REG0_NBSTOP_MASK
31988 #define UART1_MODE_REG0_NBSTOP_DEFVAL 0x00000000
31989 #define UART1_MODE_REG0_NBSTOP_SHIFT 6
31990 #define UART1_MODE_REG0_NBSTOP_MASK 0x000000C0U
31993 * Parity type select: Defines the expected parity to check on receive and
31994 * the parity to generate on transmit. 000: even parity 001: odd parity 010
31995 * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari
31998 #undef UART1_MODE_REG0_PAR_DEFVAL
31999 #undef UART1_MODE_REG0_PAR_SHIFT
32000 #undef UART1_MODE_REG0_PAR_MASK
32001 #define UART1_MODE_REG0_PAR_DEFVAL 0x00000000
32002 #define UART1_MODE_REG0_PAR_SHIFT 3
32003 #define UART1_MODE_REG0_PAR_MASK 0x00000038U
32006 * Character length select: Defines the number of bits in each character. 1
32007 * 1: 6 bits 10: 7 bits 0x: 8 bits
32009 #undef UART1_MODE_REG0_CHRL_DEFVAL
32010 #undef UART1_MODE_REG0_CHRL_SHIFT
32011 #undef UART1_MODE_REG0_CHRL_MASK
32012 #define UART1_MODE_REG0_CHRL_DEFVAL 0x00000000
32013 #define UART1_MODE_REG0_CHRL_SHIFT 1
32014 #define UART1_MODE_REG0_CHRL_MASK 0x00000006U
32017 * Clock source select: This field defines whether a pre-scalar of 8 is app
32018 * lied to the baud rate generator input clock. 0: clock source is uart_ref
32019 * _clk 1: clock source is uart_ref_clk/8
32021 #undef UART1_MODE_REG0_CLKS_DEFVAL
32022 #undef UART1_MODE_REG0_CLKS_SHIFT
32023 #undef UART1_MODE_REG0_CLKS_MASK
32024 #define UART1_MODE_REG0_CLKS_DEFVAL 0x00000000
32025 #define UART1_MODE_REG0_CLKS_SHIFT 0
32026 #define UART1_MODE_REG0_CLKS_MASK 0x00000001U
32029 * Block level reset
32031 #undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_DEFVAL
32032 #undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_SHIFT
32033 #undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK
32034 #define CRL_APB_RST_LPD_IOU2_GPIO_RESET_DEFVAL 0x0017FFFF
32035 #define CRL_APB_RST_LPD_IOU2_GPIO_RESET_SHIFT 18
32036 #define CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK 0x00040000U
32039 * TrustZone Classification for ADMA
32041 #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL
32042 #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT
32043 #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK
32044 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL
32045 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 0
32046 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 0x000000FFU
32051 #undef CSU_TAMPER_STATUS_TAMPER_0_DEFVAL
32052 #undef CSU_TAMPER_STATUS_TAMPER_0_SHIFT
32053 #undef CSU_TAMPER_STATUS_TAMPER_0_MASK
32054 #define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL 0x00000000
32055 #define CSU_TAMPER_STATUS_TAMPER_0_SHIFT 0
32056 #define CSU_TAMPER_STATUS_TAMPER_0_MASK 0x00000001U
32061 #undef CSU_TAMPER_STATUS_TAMPER_1_DEFVAL
32062 #undef CSU_TAMPER_STATUS_TAMPER_1_SHIFT
32063 #undef CSU_TAMPER_STATUS_TAMPER_1_MASK
32064 #define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL 0x00000000
32065 #define CSU_TAMPER_STATUS_TAMPER_1_SHIFT 1
32066 #define CSU_TAMPER_STATUS_TAMPER_1_MASK 0x00000002U
32069 * JTAG toggle detect
32071 #undef CSU_TAMPER_STATUS_TAMPER_2_DEFVAL
32072 #undef CSU_TAMPER_STATUS_TAMPER_2_SHIFT
32073 #undef CSU_TAMPER_STATUS_TAMPER_2_MASK
32074 #define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL 0x00000000
32075 #define CSU_TAMPER_STATUS_TAMPER_2_SHIFT 2
32076 #define CSU_TAMPER_STATUS_TAMPER_2_MASK 0x00000004U
32081 #undef CSU_TAMPER_STATUS_TAMPER_3_DEFVAL
32082 #undef CSU_TAMPER_STATUS_TAMPER_3_SHIFT
32083 #undef CSU_TAMPER_STATUS_TAMPER_3_MASK
32084 #define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL 0x00000000
32085 #define CSU_TAMPER_STATUS_TAMPER_3_SHIFT 3
32086 #define CSU_TAMPER_STATUS_TAMPER_3_MASK 0x00000008U
32089 * AMS over temperature alarm for LPD
32091 #undef CSU_TAMPER_STATUS_TAMPER_4_DEFVAL
32092 #undef CSU_TAMPER_STATUS_TAMPER_4_SHIFT
32093 #undef CSU_TAMPER_STATUS_TAMPER_4_MASK
32094 #define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL 0x00000000
32095 #define CSU_TAMPER_STATUS_TAMPER_4_SHIFT 4
32096 #define CSU_TAMPER_STATUS_TAMPER_4_MASK 0x00000010U
32099 * AMS over temperature alarm for APU
32101 #undef CSU_TAMPER_STATUS_TAMPER_5_DEFVAL
32102 #undef CSU_TAMPER_STATUS_TAMPER_5_SHIFT
32103 #undef CSU_TAMPER_STATUS_TAMPER_5_MASK
32104 #define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL 0x00000000
32105 #define CSU_TAMPER_STATUS_TAMPER_5_SHIFT 5
32106 #define CSU_TAMPER_STATUS_TAMPER_5_MASK 0x00000020U
32109 * AMS voltage alarm for VCCPINT_FPD
32111 #undef CSU_TAMPER_STATUS_TAMPER_6_DEFVAL
32112 #undef CSU_TAMPER_STATUS_TAMPER_6_SHIFT
32113 #undef CSU_TAMPER_STATUS_TAMPER_6_MASK
32114 #define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL 0x00000000
32115 #define CSU_TAMPER_STATUS_TAMPER_6_SHIFT 6
32116 #define CSU_TAMPER_STATUS_TAMPER_6_MASK 0x00000040U
32119 * AMS voltage alarm for VCCPINT_LPD
32121 #undef CSU_TAMPER_STATUS_TAMPER_7_DEFVAL
32122 #undef CSU_TAMPER_STATUS_TAMPER_7_SHIFT
32123 #undef CSU_TAMPER_STATUS_TAMPER_7_MASK
32124 #define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL 0x00000000
32125 #define CSU_TAMPER_STATUS_TAMPER_7_SHIFT 7
32126 #define CSU_TAMPER_STATUS_TAMPER_7_MASK 0x00000080U
32129 * AMS voltage alarm for VCCPAUX
32131 #undef CSU_TAMPER_STATUS_TAMPER_8_DEFVAL
32132 #undef CSU_TAMPER_STATUS_TAMPER_8_SHIFT
32133 #undef CSU_TAMPER_STATUS_TAMPER_8_MASK
32134 #define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL 0x00000000
32135 #define CSU_TAMPER_STATUS_TAMPER_8_SHIFT 8
32136 #define CSU_TAMPER_STATUS_TAMPER_8_MASK 0x00000100U
32139 * AMS voltage alarm for DDRPHY
32141 #undef CSU_TAMPER_STATUS_TAMPER_9_DEFVAL
32142 #undef CSU_TAMPER_STATUS_TAMPER_9_SHIFT
32143 #undef CSU_TAMPER_STATUS_TAMPER_9_MASK
32144 #define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL 0x00000000
32145 #define CSU_TAMPER_STATUS_TAMPER_9_SHIFT 9
32146 #define CSU_TAMPER_STATUS_TAMPER_9_MASK 0x00000200U
32149 * AMS voltage alarm for PSIO bank 0/1/2
32151 #undef CSU_TAMPER_STATUS_TAMPER_10_DEFVAL
32152 #undef CSU_TAMPER_STATUS_TAMPER_10_SHIFT
32153 #undef CSU_TAMPER_STATUS_TAMPER_10_MASK
32154 #define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL 0x00000000
32155 #define CSU_TAMPER_STATUS_TAMPER_10_SHIFT 10
32156 #define CSU_TAMPER_STATUS_TAMPER_10_MASK 0x00000400U
32159 * AMS voltage alarm for PSIO bank 3 (dedicated pins)
32161 #undef CSU_TAMPER_STATUS_TAMPER_11_DEFVAL
32162 #undef CSU_TAMPER_STATUS_TAMPER_11_SHIFT
32163 #undef CSU_TAMPER_STATUS_TAMPER_11_MASK
32164 #define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL 0x00000000
32165 #define CSU_TAMPER_STATUS_TAMPER_11_SHIFT 11
32166 #define CSU_TAMPER_STATUS_TAMPER_11_MASK 0x00000800U
32169 * AMS voltaage alarm for GT
32171 #undef CSU_TAMPER_STATUS_TAMPER_12_DEFVAL
32172 #undef CSU_TAMPER_STATUS_TAMPER_12_SHIFT
32173 #undef CSU_TAMPER_STATUS_TAMPER_12_MASK
32174 #define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL 0x00000000
32175 #define CSU_TAMPER_STATUS_TAMPER_12_SHIFT 12
32176 #define CSU_TAMPER_STATUS_TAMPER_12_MASK 0x00001000U
32179 * Set ACE outgoing AWQOS value
32181 #undef APU_ACE_CTRL_AWQOS_DEFVAL
32182 #undef APU_ACE_CTRL_AWQOS_SHIFT
32183 #undef APU_ACE_CTRL_AWQOS_MASK
32184 #define APU_ACE_CTRL_AWQOS_DEFVAL 0x000F000F
32185 #define APU_ACE_CTRL_AWQOS_SHIFT 16
32186 #define APU_ACE_CTRL_AWQOS_MASK 0x000F0000U
32189 * Set ACE outgoing ARQOS value
32191 #undef APU_ACE_CTRL_ARQOS_DEFVAL
32192 #undef APU_ACE_CTRL_ARQOS_SHIFT
32193 #undef APU_ACE_CTRL_ARQOS_MASK
32194 #define APU_ACE_CTRL_ARQOS_DEFVAL 0x000F000F
32195 #define APU_ACE_CTRL_ARQOS_SHIFT 0
32196 #define APU_ACE_CTRL_ARQOS_MASK 0x0000000FU
32199 * Enables the RTC. By writing a 0 to this bit, RTC will be powered off and
32200 * the only module that potentially draws current from the battery will be
32201 * BBRAM. The value read through this bit does not necessarily reflect whe
32202 * ther RTC is enabled or not. It is expected that RTC is enabled every tim
32203 * e it is being configured. If RTC is not used in the design, FSBL will di
32204 * sable it by writing a 0 to this bit.
32206 #undef RTC_CONTROL_BATTERY_DISABLE_DEFVAL
32207 #undef RTC_CONTROL_BATTERY_DISABLE_SHIFT
32208 #undef RTC_CONTROL_BATTERY_DISABLE_MASK
32209 #define RTC_CONTROL_BATTERY_DISABLE_DEFVAL 0x01000000
32210 #define RTC_CONTROL_BATTERY_DISABLE_SHIFT 31
32211 #define RTC_CONTROL_BATTERY_DISABLE_MASK 0x80000000U
32214 * Frequency in number of ticks per second. Valid range from 10 MHz to 100
32217 #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL
32218 #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT
32219 #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK
32220 #define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL
32221 #define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT 0
32222 #define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK 0xFFFFFFFFU
32225 * Enable 0: The counter is disabled and not incrementing. 1: The counter i
32226 * s enabled and is incrementing.
32228 #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL
32229 #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT
32230 #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK
32231 #define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL 0x00000000
32232 #define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT 0
32233 #define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK 0x00000001U
32236 * Operation is the same as DIRM_0[DIRECTION_0]
32238 #undef GPIO_DIRM_1_DIRECTION_1_DEFVAL
32239 #undef GPIO_DIRM_1_DIRECTION_1_SHIFT
32240 #undef GPIO_DIRM_1_DIRECTION_1_MASK
32241 #define GPIO_DIRM_1_DIRECTION_1_DEFVAL 0x00000000
32242 #define GPIO_DIRM_1_DIRECTION_1_SHIFT 0
32243 #define GPIO_DIRM_1_DIRECTION_1_MASK 0x03FFFFFFU
32246 * Operation is the same as OEN_0[OP_ENABLE_0]
32248 #undef GPIO_OEN_1_OP_ENABLE_1_DEFVAL
32249 #undef GPIO_OEN_1_OP_ENABLE_1_SHIFT
32250 #undef GPIO_OEN_1_OP_ENABLE_1_MASK
32251 #define GPIO_OEN_1_OP_ENABLE_1_DEFVAL 0x00000000
32252 #define GPIO_OEN_1_OP_ENABLE_1_SHIFT 0
32253 #define GPIO_OEN_1_OP_ENABLE_1_MASK 0x03FFFFFFU
32256 * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
32258 #undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL
32259 #undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT
32260 #undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK
32261 #define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000
32262 #define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16
32263 #define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U
32266 * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]
32268 #undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL
32269 #undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT
32270 #undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK
32271 #define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000
32272 #define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0
32273 #define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU
32276 * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
32278 #undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL
32279 #undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT
32280 #undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK
32281 #define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000
32282 #define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16
32283 #define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U
32286 * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]
32288 #undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL
32289 #undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT
32290 #undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK
32291 #define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000
32292 #define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0
32293 #define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU
32294 #undef FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET
32295 #define FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET 0XFD690040
32296 #undef FPD_SLCR_SECURE_SLCR_PCIE_OFFSET
32297 #define FPD_SLCR_SECURE_SLCR_PCIE_OFFSET 0XFD690030
32298 #undef LPD_SLCR_SECURE_SLCR_USB_OFFSET
32299 #define LPD_SLCR_SECURE_SLCR_USB_OFFSET 0XFF4B0034
32300 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET
32301 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 0XFF240004
32302 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET
32303 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000
32304 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET
32305 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 0XFF240004
32306 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET
32307 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000
32308 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET
32309 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000
32310 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET
32311 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 0XFF240004
32312 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET
32313 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000
32314 #undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET
32315 #define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 0XFF4B0024
32316 #undef FPD_SLCR_SECURE_SLCR_GDMA_OFFSET
32317 #define FPD_SLCR_SECURE_SLCR_GDMA_OFFSET 0XFD690050
32320 * TrustZone classification for DisplayPort DMA
32322 #undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_DEFVAL
32323 #undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_SHIFT
32324 #undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_MASK
32325 #define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_DEFVAL 0x00000001
32326 #define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_SHIFT 0
32327 #define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_MASK 0x00000001U
32330 * TrustZone classification for DMA Channel 0
32332 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_DEFVAL
32333 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_SHIFT
32334 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_MASK
32335 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_DEFVAL 0x01FFFFFF
32336 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_SHIFT 21
32337 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_MASK 0x00200000U
32340 * TrustZone classification for DMA Channel 1
32342 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_DEFVAL
32343 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_SHIFT
32344 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_MASK
32345 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_DEFVAL 0x01FFFFFF
32346 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_SHIFT 22
32347 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_MASK 0x00400000U
32350 * TrustZone classification for DMA Channel 2
32352 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_DEFVAL
32353 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_SHIFT
32354 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_MASK
32355 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_DEFVAL 0x01FFFFFF
32356 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_SHIFT 23
32357 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_MASK 0x00800000U
32360 * TrustZone classification for DMA Channel 3
32362 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_DEFVAL
32363 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_SHIFT
32364 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_MASK
32365 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_DEFVAL 0x01FFFFFF
32366 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_SHIFT 24
32367 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_MASK 0x01000000U
32370 * TrustZone classification for Ingress Address Translation 0
32372 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_DEFVAL
32373 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_SHIFT
32374 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_MASK
32375 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_DEFVAL 0x01FFFFFF
32376 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_SHIFT 13
32377 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_MASK 0x00002000U
32380 * TrustZone classification for Ingress Address Translation 1
32382 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_DEFVAL
32383 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_SHIFT
32384 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_MASK
32385 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_DEFVAL 0x01FFFFFF
32386 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_SHIFT 14
32387 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_MASK 0x00004000U
32390 * TrustZone classification for Ingress Address Translation 2
32392 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_DEFVAL
32393 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_SHIFT
32394 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_MASK
32395 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_DEFVAL 0x01FFFFFF
32396 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_SHIFT 15
32397 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_MASK 0x00008000U
32400 * TrustZone classification for Ingress Address Translation 3
32402 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_DEFVAL
32403 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_SHIFT
32404 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_MASK
32405 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_DEFVAL 0x01FFFFFF
32406 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_SHIFT 16
32407 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_MASK 0x00010000U
32410 * TrustZone classification for Ingress Address Translation 4
32412 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_DEFVAL
32413 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_SHIFT
32414 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_MASK
32415 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_DEFVAL 0x01FFFFFF
32416 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_SHIFT 17
32417 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_MASK 0x00020000U
32420 * TrustZone classification for Ingress Address Translation 5
32422 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_DEFVAL
32423 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_SHIFT
32424 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_MASK
32425 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_DEFVAL 0x01FFFFFF
32426 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_SHIFT 18
32427 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_MASK 0x00040000U
32430 * TrustZone classification for Ingress Address Translation 6
32432 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_DEFVAL
32433 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_SHIFT
32434 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_MASK
32435 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_DEFVAL 0x01FFFFFF
32436 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_SHIFT 19
32437 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_MASK 0x00080000U
32440 * TrustZone classification for Ingress Address Translation 7
32442 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_DEFVAL
32443 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_SHIFT
32444 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_MASK
32445 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_DEFVAL 0x01FFFFFF
32446 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_SHIFT 20
32447 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_MASK 0x00100000U
32450 * TrustZone classification for Egress Address Translation 0
32452 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_DEFVAL
32453 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_SHIFT
32454 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_MASK
32455 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_DEFVAL 0x01FFFFFF
32456 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_SHIFT 5
32457 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_MASK 0x00000020U
32460 * TrustZone classification for Egress Address Translation 1
32462 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_DEFVAL
32463 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_SHIFT
32464 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_MASK
32465 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_DEFVAL 0x01FFFFFF
32466 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_SHIFT 6
32467 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_MASK 0x00000040U
32470 * TrustZone classification for Egress Address Translation 2
32472 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_DEFVAL
32473 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_SHIFT
32474 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_MASK
32475 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_DEFVAL 0x01FFFFFF
32476 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_SHIFT 7
32477 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_MASK 0x00000080U
32480 * TrustZone classification for Egress Address Translation 3
32482 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_DEFVAL
32483 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_SHIFT
32484 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_MASK
32485 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_DEFVAL 0x01FFFFFF
32486 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_SHIFT 8
32487 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_MASK 0x00000100U
32490 * TrustZone classification for Egress Address Translation 4
32492 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_DEFVAL
32493 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_SHIFT
32494 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_MASK
32495 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_DEFVAL 0x01FFFFFF
32496 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_SHIFT 9
32497 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_MASK 0x00000200U
32500 * TrustZone classification for Egress Address Translation 5
32502 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_DEFVAL
32503 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_SHIFT
32504 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_MASK
32505 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_DEFVAL 0x01FFFFFF
32506 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_SHIFT 10
32507 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_MASK 0x00000400U
32510 * TrustZone classification for Egress Address Translation 6
32512 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_DEFVAL
32513 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_SHIFT
32514 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_MASK
32515 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_DEFVAL 0x01FFFFFF
32516 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_SHIFT 11
32517 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_MASK 0x00000800U
32520 * TrustZone classification for Egress Address Translation 7
32522 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_DEFVAL
32523 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_SHIFT
32524 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_MASK
32525 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_DEFVAL 0x01FFFFFF
32526 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_SHIFT 12
32527 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_MASK 0x00001000U
32530 * TrustZone classification for DMA Registers
32532 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_DEFVAL
32533 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_SHIFT
32534 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_MASK
32535 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_DEFVAL 0x01FFFFFF
32536 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_SHIFT 4
32537 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_MASK 0x00000010U
32540 * TrustZone classification for MSIx Table
32542 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_DEFVAL
32543 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_SHIFT
32544 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_MASK
32545 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_DEFVAL 0x01FFFFFF
32546 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_SHIFT 2
32547 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_MASK 0x00000004U
32550 * TrustZone classification for MSIx PBA
32552 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_DEFVAL
32553 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_SHIFT
32554 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_MASK
32555 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_DEFVAL 0x01FFFFFF
32556 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_SHIFT 3
32557 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_MASK 0x00000008U
32560 * TrustZone classification for ECAM
32562 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_DEFVAL
32563 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_SHIFT
32564 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_MASK
32565 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_DEFVAL 0x01FFFFFF
32566 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_SHIFT 1
32567 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_MASK 0x00000002U
32570 * TrustZone classification for Bridge Common Registers
32572 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_DEFVAL
32573 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_SHIFT
32574 #undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_MASK
32575 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_DEFVAL 0x01FFFFFF
32576 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_SHIFT 0
32577 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_MASK 0x00000001U
32580 * TrustZone Classification for USB3_0
32582 #undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_DEFVAL
32583 #undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_SHIFT
32584 #undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_MASK
32585 #define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_DEFVAL 0x00000003
32586 #define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_SHIFT 0
32587 #define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_MASK 0x00000001U
32590 * TrustZone Classification for USB3_1
32592 #undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_DEFVAL
32593 #undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_SHIFT
32594 #undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_MASK
32595 #define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_DEFVAL 0x00000003
32596 #define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_SHIFT 1
32597 #define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_MASK 0x00000002U
32600 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
32601 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
32602 * ccess [2] = '1'' : Instruction access
32604 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_DEFVAL
32605 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_SHIFT
32606 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_MASK
32607 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_DEFVAL 0x00000000
32608 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_SHIFT 16
32609 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_MASK 0x00070000U
32612 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
32613 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
32614 * ccess [2] = '1'' : Instruction access
32616 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_DEFVAL
32617 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_SHIFT
32618 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_MASK
32619 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_DEFVAL 0x00000000
32620 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_SHIFT 19
32621 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_MASK 0x00380000U
32624 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
32625 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
32626 * ccess [2] = '1'' : Instruction access
32628 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_DEFVAL
32629 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_SHIFT
32630 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_MASK
32631 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_DEFVAL 0x00000000
32632 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_SHIFT 16
32633 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_MASK 0x00070000U
32636 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
32637 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
32638 * ccess [2] = '1'' : Instruction access
32640 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_DEFVAL
32641 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_SHIFT
32642 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_MASK
32643 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_DEFVAL 0x00000000
32644 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_SHIFT 19
32645 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_MASK 0x00380000U
32648 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
32649 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
32650 * ccess [2] = '1'' : Instruction access
32652 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_DEFVAL
32653 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_SHIFT
32654 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_MASK
32655 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_DEFVAL 0x00000000
32656 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_SHIFT 0
32657 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_MASK 0x00000007U
32660 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
32661 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
32662 * ccess [2] = '1'' : Instruction access
32664 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_DEFVAL
32665 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_SHIFT
32666 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_MASK
32667 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_DEFVAL 0x00000000
32668 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_SHIFT 3
32669 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_MASK 0x00000038U
32672 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
32673 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
32674 * ccess [2] = '1'' : Instruction access
32676 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_DEFVAL
32677 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_SHIFT
32678 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_MASK
32679 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_DEFVAL 0x00000000
32680 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_SHIFT 6
32681 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_MASK 0x000001C0U
32684 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
32685 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
32686 * ccess [2] = '1'' : Instruction access
32688 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_DEFVAL
32689 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_SHIFT
32690 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_MASK
32691 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_DEFVAL 0x00000000
32692 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_SHIFT 9
32693 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_MASK 0x00000E00U
32696 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
32697 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
32698 * ccess [2] = '1'' : Instruction access
32700 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_DEFVAL
32701 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_SHIFT
32702 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_MASK
32703 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_DEFVAL 0x00000000
32704 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_SHIFT 0
32705 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_MASK 0x00000007U
32708 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
32709 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
32710 * ccess [2] = '1'' : Instruction access
32712 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_DEFVAL
32713 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_SHIFT
32714 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_MASK
32715 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_DEFVAL 0x00000000
32716 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_SHIFT 3
32717 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_MASK 0x00000038U
32720 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
32721 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
32722 * ccess [2] = '1'' : Instruction access
32724 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_DEFVAL
32725 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_SHIFT
32726 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_MASK
32727 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_DEFVAL 0x00000000
32728 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_SHIFT 6
32729 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_MASK 0x000001C0U
32732 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
32733 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
32734 * ccess [2] = '1'' : Instruction access
32736 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_DEFVAL
32737 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_SHIFT
32738 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_MASK
32739 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_DEFVAL 0x00000000
32740 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_SHIFT 9
32741 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_MASK 0x00000E00U
32744 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
32745 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
32746 * ccess [2] = '1'' : Instruction access
32748 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_DEFVAL
32749 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_SHIFT
32750 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_MASK
32751 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_DEFVAL 0x00000000
32752 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_SHIFT 25
32753 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_MASK 0x0E000000U
32756 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
32757 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
32758 * ccess [2] = '1'' : Instruction access
32760 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_DEFVAL
32761 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_SHIFT
32762 #undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_MASK
32763 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_DEFVAL 0x00000000
32764 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_SHIFT 22
32765 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_MASK 0x01C00000U
32768 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
32769 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
32770 * ccess [2] = '1'' : Instruction access
32772 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_DEFVAL
32773 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_SHIFT
32774 #undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_MASK
32775 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_DEFVAL 0x00000000
32776 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_SHIFT 22
32777 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_MASK 0x01C00000U
32780 * TrustZone Classification for ADMA
32782 #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL
32783 #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT
32784 #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK
32785 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL
32786 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 0
32787 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 0x000000FFU
32790 * TrustZone Classification for GDMA
32792 #undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_DEFVAL
32793 #undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_SHIFT
32794 #undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_MASK
32795 #define FPD_SLCR_SECURE_SLCR_GDMA_TZ_DEFVAL
32796 #define FPD_SLCR_SECURE_SLCR_GDMA_TZ_SHIFT 0
32797 #define FPD_SLCR_SECURE_SLCR_GDMA_TZ_MASK 0x000000FFU
32798 #undef SERDES_PLL_REF_SEL0_OFFSET
32799 #define SERDES_PLL_REF_SEL0_OFFSET 0XFD410000
32800 #undef SERDES_PLL_REF_SEL1_OFFSET
32801 #define SERDES_PLL_REF_SEL1_OFFSET 0XFD410004
32802 #undef SERDES_PLL_REF_SEL2_OFFSET
32803 #define SERDES_PLL_REF_SEL2_OFFSET 0XFD410008
32804 #undef SERDES_PLL_REF_SEL3_OFFSET
32805 #define SERDES_PLL_REF_SEL3_OFFSET 0XFD41000C
32806 #undef SERDES_L0_L0_REF_CLK_SEL_OFFSET
32807 #define SERDES_L0_L0_REF_CLK_SEL_OFFSET 0XFD402860
32808 #undef SERDES_L0_L1_REF_CLK_SEL_OFFSET
32809 #define SERDES_L0_L1_REF_CLK_SEL_OFFSET 0XFD402864
32810 #undef SERDES_L0_L2_REF_CLK_SEL_OFFSET
32811 #define SERDES_L0_L2_REF_CLK_SEL_OFFSET 0XFD402868
32812 #undef SERDES_L0_L3_REF_CLK_SEL_OFFSET
32813 #define SERDES_L0_L3_REF_CLK_SEL_OFFSET 0XFD40286C
32814 #undef SERDES_L2_TM_PLL_DIG_37_OFFSET
32815 #define SERDES_L2_TM_PLL_DIG_37_OFFSET 0XFD40A094
32816 #undef SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET
32817 #define SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET 0XFD40A368
32818 #undef SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET
32819 #define SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET 0XFD40A36C
32820 #undef SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET
32821 #define SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET 0XFD40E368
32822 #undef SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET
32823 #define SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET 0XFD40E36C
32824 #undef SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET
32825 #define SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET 0XFD406368
32826 #undef SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET
32827 #define SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET 0XFD40636C
32828 #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET
32829 #define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET 0XFD406370
32830 #undef SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET
32831 #define SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET 0XFD406374
32832 #undef SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET
32833 #define SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET 0XFD406378
32834 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET
32835 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET 0XFD40637C
32836 #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET
32837 #define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET 0XFD40A370
32838 #undef SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET
32839 #define SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET 0XFD40A374
32840 #undef SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET
32841 #define SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET 0XFD40A378
32842 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET
32843 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET 0XFD40A37C
32844 #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET
32845 #define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET 0XFD40E370
32846 #undef SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET
32847 #define SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET 0XFD40E374
32848 #undef SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET
32849 #define SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET 0XFD40E378
32850 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET
32851 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET 0XFD40E37C
32852 #undef SERDES_L2_TM_DIG_6_OFFSET
32853 #define SERDES_L2_TM_DIG_6_OFFSET 0XFD40906C
32854 #undef SERDES_L2_TX_DIG_TM_61_OFFSET
32855 #define SERDES_L2_TX_DIG_TM_61_OFFSET 0XFD4080F4
32856 #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET
32857 #define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET 0XFD40E360
32858 #undef SERDES_L3_TM_DIG_6_OFFSET
32859 #define SERDES_L3_TM_DIG_6_OFFSET 0XFD40D06C
32860 #undef SERDES_L3_TX_DIG_TM_61_OFFSET
32861 #define SERDES_L3_TX_DIG_TM_61_OFFSET 0XFD40C0F4
32862 #undef SERDES_L0_TM_AUX_0_OFFSET
32863 #define SERDES_L0_TM_AUX_0_OFFSET 0XFD4010CC
32864 #undef SERDES_L2_TM_AUX_0_OFFSET
32865 #define SERDES_L2_TM_AUX_0_OFFSET 0XFD4090CC
32866 #undef SERDES_L0_TM_DIG_8_OFFSET
32867 #define SERDES_L0_TM_DIG_8_OFFSET 0XFD401074
32868 #undef SERDES_L1_TM_DIG_8_OFFSET
32869 #define SERDES_L1_TM_DIG_8_OFFSET 0XFD405074
32870 #undef SERDES_L2_TM_DIG_8_OFFSET
32871 #define SERDES_L2_TM_DIG_8_OFFSET 0XFD409074
32872 #undef SERDES_L3_TM_DIG_8_OFFSET
32873 #define SERDES_L3_TM_DIG_8_OFFSET 0XFD40D074
32874 #undef SERDES_L0_TM_MISC2_OFFSET
32875 #define SERDES_L0_TM_MISC2_OFFSET 0XFD40189C
32876 #undef SERDES_L0_TM_IQ_ILL1_OFFSET
32877 #define SERDES_L0_TM_IQ_ILL1_OFFSET 0XFD4018F8
32878 #undef SERDES_L0_TM_IQ_ILL2_OFFSET
32879 #define SERDES_L0_TM_IQ_ILL2_OFFSET 0XFD4018FC
32880 #undef SERDES_L0_TM_ILL12_OFFSET
32881 #define SERDES_L0_TM_ILL12_OFFSET 0XFD401990
32882 #undef SERDES_L0_TM_E_ILL1_OFFSET
32883 #define SERDES_L0_TM_E_ILL1_OFFSET 0XFD401924
32884 #undef SERDES_L0_TM_E_ILL2_OFFSET
32885 #define SERDES_L0_TM_E_ILL2_OFFSET 0XFD401928
32886 #undef SERDES_L0_TM_IQ_ILL3_OFFSET
32887 #define SERDES_L0_TM_IQ_ILL3_OFFSET 0XFD401900
32888 #undef SERDES_L0_TM_E_ILL3_OFFSET
32889 #define SERDES_L0_TM_E_ILL3_OFFSET 0XFD40192C
32890 #undef SERDES_L0_TM_ILL8_OFFSET
32891 #define SERDES_L0_TM_ILL8_OFFSET 0XFD401980
32892 #undef SERDES_L0_TM_IQ_ILL8_OFFSET
32893 #define SERDES_L0_TM_IQ_ILL8_OFFSET 0XFD401914
32894 #undef SERDES_L0_TM_IQ_ILL9_OFFSET
32895 #define SERDES_L0_TM_IQ_ILL9_OFFSET 0XFD401918
32896 #undef SERDES_L0_TM_E_ILL8_OFFSET
32897 #define SERDES_L0_TM_E_ILL8_OFFSET 0XFD401940
32898 #undef SERDES_L0_TM_E_ILL9_OFFSET
32899 #define SERDES_L0_TM_E_ILL9_OFFSET 0XFD401944
32900 #undef SERDES_L0_TM_ILL13_OFFSET
32901 #define SERDES_L0_TM_ILL13_OFFSET 0XFD401994
32902 #undef SERDES_L1_TM_ILL13_OFFSET
32903 #define SERDES_L1_TM_ILL13_OFFSET 0XFD405994
32904 #undef SERDES_L2_TM_MISC2_OFFSET
32905 #define SERDES_L2_TM_MISC2_OFFSET 0XFD40989C
32906 #undef SERDES_L2_TM_IQ_ILL1_OFFSET
32907 #define SERDES_L2_TM_IQ_ILL1_OFFSET 0XFD4098F8
32908 #undef SERDES_L2_TM_IQ_ILL2_OFFSET
32909 #define SERDES_L2_TM_IQ_ILL2_OFFSET 0XFD4098FC
32910 #undef SERDES_L2_TM_ILL12_OFFSET
32911 #define SERDES_L2_TM_ILL12_OFFSET 0XFD409990
32912 #undef SERDES_L2_TM_E_ILL1_OFFSET
32913 #define SERDES_L2_TM_E_ILL1_OFFSET 0XFD409924
32914 #undef SERDES_L2_TM_E_ILL2_OFFSET
32915 #define SERDES_L2_TM_E_ILL2_OFFSET 0XFD409928
32916 #undef SERDES_L2_TM_IQ_ILL3_OFFSET
32917 #define SERDES_L2_TM_IQ_ILL3_OFFSET 0XFD409900
32918 #undef SERDES_L2_TM_E_ILL3_OFFSET
32919 #define SERDES_L2_TM_E_ILL3_OFFSET 0XFD40992C
32920 #undef SERDES_L2_TM_ILL8_OFFSET
32921 #define SERDES_L2_TM_ILL8_OFFSET 0XFD409980
32922 #undef SERDES_L2_TM_IQ_ILL8_OFFSET
32923 #define SERDES_L2_TM_IQ_ILL8_OFFSET 0XFD409914
32924 #undef SERDES_L2_TM_IQ_ILL9_OFFSET
32925 #define SERDES_L2_TM_IQ_ILL9_OFFSET 0XFD409918
32926 #undef SERDES_L2_TM_E_ILL8_OFFSET
32927 #define SERDES_L2_TM_E_ILL8_OFFSET 0XFD409940
32928 #undef SERDES_L2_TM_E_ILL9_OFFSET
32929 #define SERDES_L2_TM_E_ILL9_OFFSET 0XFD409944
32930 #undef SERDES_L2_TM_ILL13_OFFSET
32931 #define SERDES_L2_TM_ILL13_OFFSET 0XFD409994
32932 #undef SERDES_L3_TM_MISC2_OFFSET
32933 #define SERDES_L3_TM_MISC2_OFFSET 0XFD40D89C
32934 #undef SERDES_L3_TM_IQ_ILL1_OFFSET
32935 #define SERDES_L3_TM_IQ_ILL1_OFFSET 0XFD40D8F8
32936 #undef SERDES_L3_TM_IQ_ILL2_OFFSET
32937 #define SERDES_L3_TM_IQ_ILL2_OFFSET 0XFD40D8FC
32938 #undef SERDES_L3_TM_ILL12_OFFSET
32939 #define SERDES_L3_TM_ILL12_OFFSET 0XFD40D990
32940 #undef SERDES_L3_TM_E_ILL1_OFFSET
32941 #define SERDES_L3_TM_E_ILL1_OFFSET 0XFD40D924
32942 #undef SERDES_L3_TM_E_ILL2_OFFSET
32943 #define SERDES_L3_TM_E_ILL2_OFFSET 0XFD40D928
32944 #undef SERDES_L3_TM_ILL11_OFFSET
32945 #define SERDES_L3_TM_ILL11_OFFSET 0XFD40D98C
32946 #undef SERDES_L3_TM_IQ_ILL3_OFFSET
32947 #define SERDES_L3_TM_IQ_ILL3_OFFSET 0XFD40D900
32948 #undef SERDES_L3_TM_E_ILL3_OFFSET
32949 #define SERDES_L3_TM_E_ILL3_OFFSET 0XFD40D92C
32950 #undef SERDES_L3_TM_ILL8_OFFSET
32951 #define SERDES_L3_TM_ILL8_OFFSET 0XFD40D980
32952 #undef SERDES_L3_TM_IQ_ILL8_OFFSET
32953 #define SERDES_L3_TM_IQ_ILL8_OFFSET 0XFD40D914
32954 #undef SERDES_L3_TM_IQ_ILL9_OFFSET
32955 #define SERDES_L3_TM_IQ_ILL9_OFFSET 0XFD40D918
32956 #undef SERDES_L3_TM_E_ILL8_OFFSET
32957 #define SERDES_L3_TM_E_ILL8_OFFSET 0XFD40D940
32958 #undef SERDES_L3_TM_E_ILL9_OFFSET
32959 #define SERDES_L3_TM_E_ILL9_OFFSET 0XFD40D944
32960 #undef SERDES_L3_TM_ILL13_OFFSET
32961 #define SERDES_L3_TM_ILL13_OFFSET 0XFD40D994
32962 #undef SERDES_L0_TM_DIG_10_OFFSET
32963 #define SERDES_L0_TM_DIG_10_OFFSET 0XFD40107C
32964 #undef SERDES_L1_TM_DIG_10_OFFSET
32965 #define SERDES_L1_TM_DIG_10_OFFSET 0XFD40507C
32966 #undef SERDES_L2_TM_DIG_10_OFFSET
32967 #define SERDES_L2_TM_DIG_10_OFFSET 0XFD40907C
32968 #undef SERDES_L3_TM_DIG_10_OFFSET
32969 #define SERDES_L3_TM_DIG_10_OFFSET 0XFD40D07C
32970 #undef SERDES_L0_TM_RST_DLY_OFFSET
32971 #define SERDES_L0_TM_RST_DLY_OFFSET 0XFD4019A4
32972 #undef SERDES_L0_TM_ANA_BYP_15_OFFSET
32973 #define SERDES_L0_TM_ANA_BYP_15_OFFSET 0XFD401038
32974 #undef SERDES_L0_TM_ANA_BYP_12_OFFSET
32975 #define SERDES_L0_TM_ANA_BYP_12_OFFSET 0XFD40102C
32976 #undef SERDES_L1_TM_RST_DLY_OFFSET
32977 #define SERDES_L1_TM_RST_DLY_OFFSET 0XFD4059A4
32978 #undef SERDES_L1_TM_ANA_BYP_15_OFFSET
32979 #define SERDES_L1_TM_ANA_BYP_15_OFFSET 0XFD405038
32980 #undef SERDES_L1_TM_ANA_BYP_12_OFFSET
32981 #define SERDES_L1_TM_ANA_BYP_12_OFFSET 0XFD40502C
32982 #undef SERDES_L2_TM_RST_DLY_OFFSET
32983 #define SERDES_L2_TM_RST_DLY_OFFSET 0XFD4099A4
32984 #undef SERDES_L2_TM_ANA_BYP_15_OFFSET
32985 #define SERDES_L2_TM_ANA_BYP_15_OFFSET 0XFD409038
32986 #undef SERDES_L2_TM_ANA_BYP_12_OFFSET
32987 #define SERDES_L2_TM_ANA_BYP_12_OFFSET 0XFD40902C
32988 #undef SERDES_L3_TM_RST_DLY_OFFSET
32989 #define SERDES_L3_TM_RST_DLY_OFFSET 0XFD40D9A4
32990 #undef SERDES_L3_TM_ANA_BYP_15_OFFSET
32991 #define SERDES_L3_TM_ANA_BYP_15_OFFSET 0XFD40D038
32992 #undef SERDES_L3_TM_ANA_BYP_12_OFFSET
32993 #define SERDES_L3_TM_ANA_BYP_12_OFFSET 0XFD40D02C
32994 #undef SERDES_L0_TM_MISC3_OFFSET
32995 #define SERDES_L0_TM_MISC3_OFFSET 0XFD4019AC
32996 #undef SERDES_L1_TM_MISC3_OFFSET
32997 #define SERDES_L1_TM_MISC3_OFFSET 0XFD4059AC
32998 #undef SERDES_L2_TM_MISC3_OFFSET
32999 #define SERDES_L2_TM_MISC3_OFFSET 0XFD4099AC
33000 #undef SERDES_L3_TM_MISC3_OFFSET
33001 #define SERDES_L3_TM_MISC3_OFFSET 0XFD40D9AC
33002 #undef SERDES_L0_TM_EQ11_OFFSET
33003 #define SERDES_L0_TM_EQ11_OFFSET 0XFD401978
33004 #undef SERDES_L1_TM_EQ11_OFFSET
33005 #define SERDES_L1_TM_EQ11_OFFSET 0XFD405978
33006 #undef SERDES_L2_TM_EQ11_OFFSET
33007 #define SERDES_L2_TM_EQ11_OFFSET 0XFD409978
33008 #undef SERDES_L3_TM_EQ11_OFFSET
33009 #define SERDES_L3_TM_EQ11_OFFSET 0XFD40D978
33010 #undef SIOU_ECO_0_OFFSET
33011 #define SIOU_ECO_0_OFFSET 0XFD3D001C
33012 #undef SERDES_ICM_CFG0_OFFSET
33013 #define SERDES_ICM_CFG0_OFFSET 0XFD410010
33014 #undef SERDES_ICM_CFG1_OFFSET
33015 #define SERDES_ICM_CFG1_OFFSET 0XFD410014
33016 #undef SERDES_L1_TXPMD_TM_45_OFFSET
33017 #define SERDES_L1_TXPMD_TM_45_OFFSET 0XFD404CB4
33018 #undef SERDES_L1_TX_ANA_TM_118_OFFSET
33019 #define SERDES_L1_TX_ANA_TM_118_OFFSET 0XFD4041D8
33020 #undef SERDES_L3_TX_ANA_TM_118_OFFSET
33021 #define SERDES_L3_TX_ANA_TM_118_OFFSET 0XFD40C1D8
33022 #undef SERDES_L3_TM_CDR5_OFFSET
33023 #define SERDES_L3_TM_CDR5_OFFSET 0XFD40DC14
33024 #undef SERDES_L3_TM_CDR16_OFFSET
33025 #define SERDES_L3_TM_CDR16_OFFSET 0XFD40DC40
33026 #undef SERDES_L3_TM_EQ0_OFFSET
33027 #define SERDES_L3_TM_EQ0_OFFSET 0XFD40D94C
33028 #undef SERDES_L3_TM_EQ1_OFFSET
33029 #define SERDES_L3_TM_EQ1_OFFSET 0XFD40D950
33030 #undef SERDES_L1_TXPMD_TM_48_OFFSET
33031 #define SERDES_L1_TXPMD_TM_48_OFFSET 0XFD404CC0
33032 #undef SERDES_L1_TX_ANA_TM_18_OFFSET
33033 #define SERDES_L1_TX_ANA_TM_18_OFFSET 0XFD404048
33034 #undef SERDES_L3_TX_ANA_TM_18_OFFSET
33035 #define SERDES_L3_TX_ANA_TM_18_OFFSET 0XFD40C048
33038 * PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1
33039 * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
33040 * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE
33041 * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
33044 #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL
33045 #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT
33046 #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK
33047 #define SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL 0x0000000D
33048 #define SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT 0
33049 #define SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK 0x0000001FU
33052 * PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1
33053 * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
33054 * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE
33055 * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
33058 #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL
33059 #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT
33060 #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK
33061 #define SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL 0x00000008
33062 #define SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT 0
33063 #define SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK 0x0000001FU
33066 * PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1
33067 * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
33068 * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE
33069 * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
33072 #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL
33073 #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT
33074 #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK
33075 #define SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL 0x0000000F
33076 #define SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT 0
33077 #define SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK 0x0000001FU
33080 * PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1
33081 * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
33082 * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE
33083 * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
33086 #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL
33087 #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT
33088 #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK
33089 #define SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL 0x0000000E
33090 #define SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT 0
33091 #define SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK 0x0000001FU
33094 * Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer outp
33095 * ut. Set to 0 to select lane0 ref clock mux output.
33097 #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL
33098 #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT
33099 #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK
33100 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL 0x00000080
33101 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT 7
33102 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK 0x00000080U
33105 * Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer outp
33106 * ut. Set to 0 to select lane1 ref clock mux output.
33108 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL
33109 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT
33110 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK
33111 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL 0x00000080
33112 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT 7
33113 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK 0x00000080U
33116 * Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 sli
33117 * cer output from ref clock network
33119 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL
33120 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT
33121 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK
33122 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL 0x00000080
33123 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT 3
33124 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK 0x00000008U
33127 * Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer outp
33128 * ut. Set to 0 to select lane2 ref clock mux output.
33130 #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL
33131 #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT
33132 #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK
33133 #define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL 0x00000080
33134 #define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT 7
33135 #define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK 0x00000080U
33138 * Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer outp
33139 * ut. Set to 0 to select lane3 ref clock mux output.
33141 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL
33142 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT
33143 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK
33144 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL 0x00000080
33145 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT 7
33146 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK 0x00000080U
33149 * Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 sli
33150 * cer output from ref clock network
33152 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL
33153 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT
33154 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK
33155 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL 0x00000080
33156 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT 1
33157 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK 0x00000002U
33160 * Enable/Disable coarse code satureation limiting logic
33162 #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL
33163 #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT
33164 #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK
33165 #define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL 0x00000000
33166 #define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT 4
33167 #define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK 0x00000010U
33170 * Spread Spectrum No of Steps [7:0]
33172 #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL
33173 #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
33174 #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK
33175 #define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000
33176 #define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0
33177 #define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU
33180 * Spread Spectrum No of Steps [10:8]
33182 #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL
33183 #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
33184 #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK
33185 #define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000
33186 #define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0
33187 #define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U
33190 * Spread Spectrum No of Steps [7:0]
33192 #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL
33193 #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
33194 #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK
33195 #define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000
33196 #define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0
33197 #define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU
33200 * Spread Spectrum No of Steps [10:8]
33202 #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL
33203 #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
33204 #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK
33205 #define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000
33206 #define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0
33207 #define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U
33210 * Spread Spectrum No of Steps [7:0]
33212 #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL
33213 #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
33214 #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK
33215 #define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000
33216 #define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0
33217 #define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU
33220 * Spread Spectrum No of Steps [10:8]
33222 #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL
33223 #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
33224 #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK
33225 #define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000
33226 #define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0
33227 #define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U
33230 * Step Size for Spread Spectrum [7:0]
33232 #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL
33233 #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
33234 #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK
33235 #define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000
33236 #define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0
33237 #define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU
33240 * Step Size for Spread Spectrum [15:8]
33242 #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL
33243 #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
33244 #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK
33245 #define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000
33246 #define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0
33247 #define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU
33250 * Step Size for Spread Spectrum [23:16]
33252 #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL
33253 #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
33254 #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK
33255 #define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000
33256 #define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0
33257 #define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU
33260 * Step Size for Spread Spectrum [25:24]
33262 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL
33263 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
33264 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK
33265 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000
33266 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0
33267 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U
33270 * Enable/Disable test mode force on SS step size
33272 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL
33273 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
33274 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK
33275 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000
33276 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4
33277 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U
33280 * Enable/Disable test mode force on SS no of steps
33282 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL
33283 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
33284 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK
33285 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000
33286 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5
33287 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U
33290 * Step Size for Spread Spectrum [7:0]
33292 #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL
33293 #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
33294 #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK
33295 #define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000
33296 #define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0
33297 #define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU
33300 * Step Size for Spread Spectrum [15:8]
33302 #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL
33303 #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
33304 #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK
33305 #define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000
33306 #define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0
33307 #define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU
33310 * Step Size for Spread Spectrum [23:16]
33312 #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL
33313 #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
33314 #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK
33315 #define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000
33316 #define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0
33317 #define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU
33320 * Step Size for Spread Spectrum [25:24]
33322 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL
33323 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
33324 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK
33325 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000
33326 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0
33327 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U
33330 * Enable/Disable test mode force on SS step size
33332 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL
33333 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
33334 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK
33335 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000
33336 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4
33337 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U
33340 * Enable/Disable test mode force on SS no of steps
33342 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL
33343 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
33344 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK
33345 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000
33346 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5
33347 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U
33350 * Step Size for Spread Spectrum [7:0]
33352 #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL
33353 #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
33354 #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK
33355 #define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000
33356 #define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0
33357 #define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU
33360 * Step Size for Spread Spectrum [15:8]
33362 #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL
33363 #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
33364 #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK
33365 #define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000
33366 #define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0
33367 #define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU
33370 * Step Size for Spread Spectrum [23:16]
33372 #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL
33373 #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
33374 #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK
33375 #define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000
33376 #define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0
33377 #define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU
33380 * Step Size for Spread Spectrum [25:24]
33382 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL
33383 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
33384 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK
33385 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000
33386 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0
33387 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U
33390 * Enable/Disable test mode force on SS step size
33392 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL
33393 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
33394 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK
33395 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000
33396 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4
33397 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U
33400 * Enable/Disable test mode force on SS no of steps
33402 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL
33403 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
33404 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK
33405 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000
33406 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5
33407 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U
33410 * Enable test mode forcing on enable Spread Spectrum
33412 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL
33413 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT
33414 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK
33415 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL 0x00000000
33416 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT 7
33417 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK 0x00000080U
33420 * Bypass Descrambler
33422 #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL
33423 #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT
33424 #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK
33425 #define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000
33426 #define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1
33427 #define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U
33430 * Enable Bypass for <1> TM_DIG_CTRL_6
33432 #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL
33433 #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
33434 #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK
33435 #define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000
33436 #define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0
33437 #define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U
33440 * Bypass scrambler signal
33442 #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL
33443 #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
33444 #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK
33445 #define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000
33446 #define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1
33447 #define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U
33450 * Enable/disable scrambler bypass signal
33452 #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL
33453 #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
33454 #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK
33455 #define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000
33456 #define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0
33457 #define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U
33460 * Enable test mode force on fractional mode enable
33462 #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL
33463 #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT
33464 #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK
33465 #define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL 0x00000000
33466 #define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT 6
33467 #define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK 0x00000040U
33470 * Bypass 8b10b decoder
33472 #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL
33473 #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT
33474 #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK
33475 #define SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL 0x00000000
33476 #define SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT 3
33477 #define SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK 0x00000008U
33480 * Enable Bypass for <3> TM_DIG_CTRL_6
33482 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL
33483 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT
33484 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK
33485 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL 0x00000000
33486 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT 2
33487 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK 0x00000004U
33490 * Bypass Descrambler
33492 #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL
33493 #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT
33494 #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK
33495 #define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000
33496 #define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1
33497 #define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U
33500 * Enable Bypass for <1> TM_DIG_CTRL_6
33502 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL
33503 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
33504 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK
33505 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000
33506 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0
33507 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U
33510 * Enable/disable encoder bypass signal
33512 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL
33513 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT
33514 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK
33515 #define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL 0x00000000
33516 #define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT 3
33517 #define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK 0x00000008U
33520 * Bypass scrambler signal
33522 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL
33523 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
33524 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK
33525 #define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000
33526 #define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1
33527 #define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U
33530 * Enable/disable scrambler bypass signal
33532 #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL
33533 #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
33534 #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK
33535 #define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000
33536 #define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0
33537 #define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U
33542 #undef SERDES_L0_TM_AUX_0_BIT_2_DEFVAL
33543 #undef SERDES_L0_TM_AUX_0_BIT_2_SHIFT
33544 #undef SERDES_L0_TM_AUX_0_BIT_2_MASK
33545 #define SERDES_L0_TM_AUX_0_BIT_2_DEFVAL 0x00000000
33546 #define SERDES_L0_TM_AUX_0_BIT_2_SHIFT 5
33547 #define SERDES_L0_TM_AUX_0_BIT_2_MASK 0x00000020U
33552 #undef SERDES_L2_TM_AUX_0_BIT_2_DEFVAL
33553 #undef SERDES_L2_TM_AUX_0_BIT_2_SHIFT
33554 #undef SERDES_L2_TM_AUX_0_BIT_2_MASK
33555 #define SERDES_L2_TM_AUX_0_BIT_2_DEFVAL 0x00000000
33556 #define SERDES_L2_TM_AUX_0_BIT_2_SHIFT 5
33557 #define SERDES_L2_TM_AUX_0_BIT_2_MASK 0x00000020U
33562 #undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL
33563 #undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT
33564 #undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK
33565 #define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000
33566 #define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT 4
33567 #define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U
33572 #undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL
33573 #undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT
33574 #undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK
33575 #define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000
33576 #define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT 4
33577 #define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U
33582 #undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL
33583 #undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT
33584 #undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK
33585 #define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000
33586 #define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT 4
33587 #define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U
33592 #undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL
33593 #undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT
33594 #undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK
33595 #define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000
33596 #define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT 4
33597 #define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U
33600 * ILL calib counts BYPASSED with calcode bits
33602 #undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL
33603 #undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
33604 #undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK
33605 #define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000
33606 #define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7
33607 #define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U
33610 * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 ,
33613 #undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL
33614 #undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
33615 #undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK
33616 #define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000
33617 #define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0
33618 #define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU
33621 * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
33623 #undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL
33624 #undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
33625 #undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK
33626 #define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000
33627 #define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0
33628 #define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU
33631 * G1A pll ctr bypass value
33633 #undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL
33634 #undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
33635 #undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK
33636 #define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000
33637 #define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0
33638 #define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU
33641 * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U
33644 #undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL
33645 #undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
33646 #undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK
33647 #define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000
33648 #define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0
33649 #define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU
33652 * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
33654 #undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL
33655 #undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
33656 #undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK
33657 #define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000
33658 #define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0
33659 #define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU
33662 * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
33664 #undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL
33665 #undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
33666 #undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK
33667 #define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000
33668 #define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0
33669 #define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU
33672 * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
33674 #undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL
33675 #undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
33676 #undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK
33677 #define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000
33678 #define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0
33679 #define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU
33682 * ILL calibration code change wait time
33684 #undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL
33685 #undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
33686 #undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK
33687 #define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002
33688 #define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0
33689 #define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU
33692 * IQ ILL polytrim bypass value
33694 #undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL
33695 #undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
33696 #undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK
33697 #define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000
33698 #define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0
33699 #define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU
33702 * bypass IQ polytrim
33704 #undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL
33705 #undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
33706 #undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK
33707 #define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000
33708 #define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0
33709 #define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U
33712 * E ILL polytrim bypass value
33714 #undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL
33715 #undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
33716 #undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK
33717 #define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000
33718 #define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0
33719 #define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU
33722 * bypass E polytrim
33724 #undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL
33725 #undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
33726 #undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK
33727 #define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000
33728 #define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0
33729 #define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U
33732 * ILL cal idle val refcnt
33734 #undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL
33735 #undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT
33736 #undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK
33737 #define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001
33738 #define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0
33739 #define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U
33742 * ILL cal idle val refcnt
33744 #undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL
33745 #undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT
33746 #undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK
33747 #define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001
33748 #define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0
33749 #define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U
33752 * ILL calib counts BYPASSED with calcode bits
33754 #undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL
33755 #undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
33756 #undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK
33757 #define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000
33758 #define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7
33759 #define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U
33762 * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 ,
33765 #undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL
33766 #undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
33767 #undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK
33768 #define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000
33769 #define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0
33770 #define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU
33773 * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
33775 #undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL
33776 #undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
33777 #undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK
33778 #define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000
33779 #define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0
33780 #define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU
33783 * G1A pll ctr bypass value
33785 #undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL
33786 #undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
33787 #undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK
33788 #define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000
33789 #define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0
33790 #define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU
33793 * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U
33796 #undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL
33797 #undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
33798 #undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK
33799 #define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000
33800 #define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0
33801 #define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU
33804 * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
33806 #undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL
33807 #undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
33808 #undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK
33809 #define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000
33810 #define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0
33811 #define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU
33814 * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
33816 #undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL
33817 #undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
33818 #undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK
33819 #define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000
33820 #define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0
33821 #define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU
33824 * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
33826 #undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL
33827 #undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
33828 #undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK
33829 #define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000
33830 #define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0
33831 #define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU
33834 * ILL calibration code change wait time
33836 #undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL
33837 #undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
33838 #undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK
33839 #define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002
33840 #define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0
33841 #define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU
33844 * IQ ILL polytrim bypass value
33846 #undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL
33847 #undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
33848 #undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK
33849 #define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000
33850 #define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0
33851 #define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU
33854 * bypass IQ polytrim
33856 #undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL
33857 #undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
33858 #undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK
33859 #define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000
33860 #define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0
33861 #define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U
33864 * E ILL polytrim bypass value
33866 #undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL
33867 #undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
33868 #undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK
33869 #define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000
33870 #define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0
33871 #define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU
33874 * bypass E polytrim
33876 #undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL
33877 #undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
33878 #undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK
33879 #define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000
33880 #define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0
33881 #define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U
33884 * ILL cal idle val refcnt
33886 #undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL
33887 #undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT
33888 #undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK
33889 #define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001
33890 #define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0
33891 #define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U
33894 * ILL calib counts BYPASSED with calcode bits
33896 #undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL
33897 #undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
33898 #undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK
33899 #define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000
33900 #define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7
33901 #define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U
33904 * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 ,
33907 #undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL
33908 #undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
33909 #undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK
33910 #define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000
33911 #define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0
33912 #define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU
33915 * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
33917 #undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL
33918 #undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
33919 #undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK
33920 #define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000
33921 #define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0
33922 #define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU
33925 * G1A pll ctr bypass value
33927 #undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL
33928 #undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
33929 #undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK
33930 #define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000
33931 #define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0
33932 #define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU
33935 * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U
33938 #undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL
33939 #undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
33940 #undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK
33941 #define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000
33942 #define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0
33943 #define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU
33946 * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
33948 #undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL
33949 #undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
33950 #undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK
33951 #define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000
33952 #define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0
33953 #define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU
33956 * G2A_PCIe1 PLL ctr bypass value
33958 #undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL
33959 #undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT
33960 #undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK
33961 #define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL 0x00000000
33962 #define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT 4
33963 #define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK 0x000000F0U
33966 * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
33968 #undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL
33969 #undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
33970 #undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK
33971 #define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000
33972 #define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0
33973 #define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU
33976 * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
33978 #undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL
33979 #undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
33980 #undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK
33981 #define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000
33982 #define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0
33983 #define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU
33986 * ILL calibration code change wait time
33988 #undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL
33989 #undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
33990 #undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK
33991 #define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002
33992 #define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0
33993 #define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU
33996 * IQ ILL polytrim bypass value
33998 #undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL
33999 #undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
34000 #undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK
34001 #define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000
34002 #define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0
34003 #define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU
34006 * bypass IQ polytrim
34008 #undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL
34009 #undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
34010 #undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK
34011 #define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000
34012 #define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0
34013 #define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U
34016 * E ILL polytrim bypass value
34018 #undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL
34019 #undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
34020 #undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK
34021 #define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000
34022 #define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0
34023 #define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU
34026 * bypass E polytrim
34028 #undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL
34029 #undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
34030 #undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK
34031 #define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000
34032 #define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0
34033 #define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U
34036 * ILL cal idle val refcnt
34038 #undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL
34039 #undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT
34040 #undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK
34041 #define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001
34042 #define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0
34043 #define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U
34046 * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
34048 #undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL
34049 #undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
34050 #undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK
34051 #define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001
34052 #define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0
34053 #define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU
34056 * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
34058 #undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL
34059 #undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
34060 #undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK
34061 #define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001
34062 #define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0
34063 #define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU
34066 * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
34068 #undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL
34069 #undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
34070 #undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK
34071 #define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001
34072 #define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0
34073 #define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU
34076 * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
34078 #undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL
34079 #undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
34080 #undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK
34081 #define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001
34082 #define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0
34083 #define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU
34086 * Delay apb reset by specified amount
34088 #undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL
34089 #undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT
34090 #undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK
34091 #define SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
34092 #define SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT 0
34093 #define SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
34096 * Enable Bypass for <7> of TM_ANA_BYPS_15
34098 #undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
34099 #undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
34100 #undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
34101 #define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
34102 #define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
34103 #define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
34106 * Enable Bypass for <7> of TM_ANA_BYPS_12
34108 #undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
34109 #undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
34110 #undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
34111 #define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
34112 #define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
34113 #define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
34116 * Delay apb reset by specified amount
34118 #undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL
34119 #undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT
34120 #undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK
34121 #define SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
34122 #define SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT 0
34123 #define SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
34126 * Enable Bypass for <7> of TM_ANA_BYPS_15
34128 #undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
34129 #undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
34130 #undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
34131 #define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
34132 #define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
34133 #define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
34136 * Enable Bypass for <7> of TM_ANA_BYPS_12
34138 #undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
34139 #undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
34140 #undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
34141 #define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
34142 #define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
34143 #define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
34146 * Delay apb reset by specified amount
34148 #undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL
34149 #undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT
34150 #undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK
34151 #define SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
34152 #define SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT 0
34153 #define SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
34156 * Enable Bypass for <7> of TM_ANA_BYPS_15
34158 #undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
34159 #undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
34160 #undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
34161 #define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
34162 #define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
34163 #define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
34166 * Enable Bypass for <7> of TM_ANA_BYPS_12
34168 #undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
34169 #undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
34170 #undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
34171 #define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
34172 #define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
34173 #define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
34176 * Delay apb reset by specified amount
34178 #undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL
34179 #undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT
34180 #undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK
34181 #define SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
34182 #define SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT 0
34183 #define SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
34186 * Enable Bypass for <7> of TM_ANA_BYPS_15
34188 #undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
34189 #undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
34190 #undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
34191 #define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
34192 #define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
34193 #define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
34196 * Enable Bypass for <7> of TM_ANA_BYPS_12
34198 #undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
34199 #undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
34200 #undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
34201 #define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
34202 #define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
34203 #define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
34206 * CDR fast phase lock control
34208 #undef SERDES_L0_TM_MISC3_CDR_EN_FPL_DEFVAL
34209 #undef SERDES_L0_TM_MISC3_CDR_EN_FPL_SHIFT
34210 #undef SERDES_L0_TM_MISC3_CDR_EN_FPL_MASK
34211 #define SERDES_L0_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003
34212 #define SERDES_L0_TM_MISC3_CDR_EN_FPL_SHIFT 1
34213 #define SERDES_L0_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U
34216 * CDR fast frequency lock control
34218 #undef SERDES_L0_TM_MISC3_CDR_EN_FFL_DEFVAL
34219 #undef SERDES_L0_TM_MISC3_CDR_EN_FFL_SHIFT
34220 #undef SERDES_L0_TM_MISC3_CDR_EN_FFL_MASK
34221 #define SERDES_L0_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003
34222 #define SERDES_L0_TM_MISC3_CDR_EN_FFL_SHIFT 0
34223 #define SERDES_L0_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U
34226 * CDR fast phase lock control
34228 #undef SERDES_L1_TM_MISC3_CDR_EN_FPL_DEFVAL
34229 #undef SERDES_L1_TM_MISC3_CDR_EN_FPL_SHIFT
34230 #undef SERDES_L1_TM_MISC3_CDR_EN_FPL_MASK
34231 #define SERDES_L1_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003
34232 #define SERDES_L1_TM_MISC3_CDR_EN_FPL_SHIFT 1
34233 #define SERDES_L1_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U
34236 * CDR fast frequency lock control
34238 #undef SERDES_L1_TM_MISC3_CDR_EN_FFL_DEFVAL
34239 #undef SERDES_L1_TM_MISC3_CDR_EN_FFL_SHIFT
34240 #undef SERDES_L1_TM_MISC3_CDR_EN_FFL_MASK
34241 #define SERDES_L1_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003
34242 #define SERDES_L1_TM_MISC3_CDR_EN_FFL_SHIFT 0
34243 #define SERDES_L1_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U
34246 * CDR fast phase lock control
34248 #undef SERDES_L2_TM_MISC3_CDR_EN_FPL_DEFVAL
34249 #undef SERDES_L2_TM_MISC3_CDR_EN_FPL_SHIFT
34250 #undef SERDES_L2_TM_MISC3_CDR_EN_FPL_MASK
34251 #define SERDES_L2_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003
34252 #define SERDES_L2_TM_MISC3_CDR_EN_FPL_SHIFT 1
34253 #define SERDES_L2_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U
34256 * CDR fast frequency lock control
34258 #undef SERDES_L2_TM_MISC3_CDR_EN_FFL_DEFVAL
34259 #undef SERDES_L2_TM_MISC3_CDR_EN_FFL_SHIFT
34260 #undef SERDES_L2_TM_MISC3_CDR_EN_FFL_MASK
34261 #define SERDES_L2_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003
34262 #define SERDES_L2_TM_MISC3_CDR_EN_FFL_SHIFT 0
34263 #define SERDES_L2_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U
34266 * CDR fast phase lock control
34268 #undef SERDES_L3_TM_MISC3_CDR_EN_FPL_DEFVAL
34269 #undef SERDES_L3_TM_MISC3_CDR_EN_FPL_SHIFT
34270 #undef SERDES_L3_TM_MISC3_CDR_EN_FPL_MASK
34271 #define SERDES_L3_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003
34272 #define SERDES_L3_TM_MISC3_CDR_EN_FPL_SHIFT 1
34273 #define SERDES_L3_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U
34276 * CDR fast frequency lock control
34278 #undef SERDES_L3_TM_MISC3_CDR_EN_FFL_DEFVAL
34279 #undef SERDES_L3_TM_MISC3_CDR_EN_FFL_SHIFT
34280 #undef SERDES_L3_TM_MISC3_CDR_EN_FFL_MASK
34281 #define SERDES_L3_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003
34282 #define SERDES_L3_TM_MISC3_CDR_EN_FFL_SHIFT 0
34283 #define SERDES_L3_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U
34286 * Force EQ offset correction algo off if not forced on
34288 #undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL
34289 #undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT
34290 #undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK
34291 #define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000
34292 #define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4
34293 #define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U
34296 * Force EQ offset correction algo off if not forced on
34298 #undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL
34299 #undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT
34300 #undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK
34301 #define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000
34302 #define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4
34303 #define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U
34306 * Force EQ offset correction algo off if not forced on
34308 #undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL
34309 #undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT
34310 #undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK
34311 #define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000
34312 #define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4
34313 #define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U
34316 * Force EQ offset correction algo off if not forced on
34318 #undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL
34319 #undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT
34320 #undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK
34321 #define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000
34322 #define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4
34323 #define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U
34328 #undef SIOU_ECO_0_FIELD_DEFVAL
34329 #undef SIOU_ECO_0_FIELD_SHIFT
34330 #undef SIOU_ECO_0_FIELD_MASK
34331 #define SIOU_ECO_0_FIELD_DEFVAL
34332 #define SIOU_ECO_0_FIELD_SHIFT 0
34333 #define SIOU_ECO_0_FIELD_MASK 0xFFFFFFFFU
34336 * Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0,
34337 * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unused, 7 - Unused
34339 #undef SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL
34340 #undef SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT
34341 #undef SERDES_ICM_CFG0_L0_ICM_CFG_MASK
34342 #define SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL 0x00000000
34343 #define SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT 0
34344 #define SERDES_ICM_CFG0_L0_ICM_CFG_MASK 0x00000007U
34347 * Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1,
34348 * 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused, 7 - Unused
34350 #undef SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL
34351 #undef SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT
34352 #undef SERDES_ICM_CFG0_L1_ICM_CFG_MASK
34353 #define SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL 0x00000000
34354 #define SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT 4
34355 #define SERDES_ICM_CFG0_L1_ICM_CFG_MASK 0x00000070U
34358 * Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1,
34359 * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused, 7 - Unused
34361 #undef SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL
34362 #undef SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT
34363 #undef SERDES_ICM_CFG1_L2_ICM_CFG_MASK
34364 #define SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL 0x00000000
34365 #define SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT 0
34366 #define SERDES_ICM_CFG1_L2_ICM_CFG_MASK 0x00000007U
34369 * Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3,
34370 * 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused, 7 - Unused
34372 #undef SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL
34373 #undef SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT
34374 #undef SERDES_ICM_CFG1_L3_ICM_CFG_MASK
34375 #define SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL 0x00000000
34376 #define SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT 4
34377 #define SERDES_ICM_CFG1_L3_ICM_CFG_MASK 0x00000070U
34380 * Enable/disable DP post2 path
34382 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL
34383 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
34384 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK
34385 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000
34386 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT 5
34387 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK 0x00000020U
34390 * Override enable/disable of DP post2 path
34392 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL
34393 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT
34394 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK
34395 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000
34396 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT 4
34397 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK 0x00000010U
34400 * Override enable/disable of DP post1 path
34402 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL
34403 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT
34404 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK
34405 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL 0x00000000
34406 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT 2
34407 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK 0x00000004U
34410 * Enable/disable DP main path
34412 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL
34413 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT
34414 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK
34415 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000
34416 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT 1
34417 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK 0x00000002U
34420 * Override enable/disable of DP main path
34422 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL
34423 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT
34424 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK
34425 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000
34426 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT 0
34427 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK 0x00000001U
34430 * Test register force for enabling/disablign TX deemphasis bits <17:0>
34432 #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL
34433 #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
34434 #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK
34435 #define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000
34436 #define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0
34437 #define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U
34440 * Test register force for enabling/disablign TX deemphasis bits <17:0>
34442 #undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL
34443 #undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
34444 #undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK
34445 #define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000
34446 #define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0
34447 #define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U
34450 * FPHL FSM accumulate cycles
34452 #undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL
34453 #undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT
34454 #undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK
34455 #define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL 0x00000000
34456 #define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT 5
34457 #define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK 0x000000E0U
34460 * FFL Phase0 int gain aka 2ol SD update rate
34462 #undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL
34463 #undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT
34464 #undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK
34465 #define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL 0x00000000
34466 #define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT 0
34467 #define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK 0x0000001FU
34470 * FFL Phase0 prop gain aka 1ol SD update rate
34472 #undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL
34473 #undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT
34474 #undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK
34475 #define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL 0x00000000
34476 #define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT 0
34477 #define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK 0x0000001FU
34480 * EQ stg 2 controls BYPASSED
34482 #undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL
34483 #undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT
34484 #undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK
34485 #define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL 0x00000000
34486 #define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT 5
34487 #define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK 0x00000020U
34492 #undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL
34493 #undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT
34494 #undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK
34495 #define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL 0x00000000
34496 #define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT 0
34497 #define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK 0x00000003U
34500 * EQ stg 2 preamp mode val
34502 #undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL
34503 #undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT
34504 #undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK
34505 #define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL 0x00000000
34506 #define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT 2
34507 #define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK 0x00000004U
34510 * Margining factor value
34512 #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL
34513 #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT
34514 #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK
34515 #define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL 0x00000000
34516 #define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT 0
34517 #define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK 0x0000001FU
34520 * pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em
34521 * phasis, Others: reserved
34523 #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL
34524 #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
34525 #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK
34526 #define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002
34527 #define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0
34528 #define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU
34531 * pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em
34532 * phasis, Others: reserved
34534 #undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL
34535 #undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
34536 #undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK
34537 #define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002
34538 #define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0
34539 #define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU
34540 #undef CRL_APB_RST_LPD_TOP_OFFSET
34541 #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
34542 #undef CRL_APB_RST_LPD_TOP_OFFSET
34543 #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
34544 #undef CRL_APB_RST_LPD_IOU0_OFFSET
34545 #define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230
34546 #undef SIOU_SATA_MISC_CTRL_OFFSET
34547 #define SIOU_SATA_MISC_CTRL_OFFSET 0XFD3D0100
34548 #undef CRF_APB_RST_FPD_TOP_OFFSET
34549 #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
34550 #undef CRF_APB_RST_FPD_TOP_OFFSET
34551 #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
34552 #undef CRF_APB_RST_FPD_TOP_OFFSET
34553 #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
34554 #undef DP_DP_PHY_RESET_OFFSET
34555 #define DP_DP_PHY_RESET_OFFSET 0XFD4A0200
34556 #undef DP_DP_TX_PHY_POWER_DOWN_OFFSET
34557 #define DP_DP_TX_PHY_POWER_DOWN_OFFSET 0XFD4A0238
34558 #undef USB3_0_XHCI_GUSB2PHYCFG_OFFSET
34559 #define USB3_0_XHCI_GUSB2PHYCFG_OFFSET 0XFE20C200
34560 #undef USB3_0_XHCI_GFLADJ_OFFSET
34561 #define USB3_0_XHCI_GFLADJ_OFFSET 0XFE20C630
34562 #undef USB3_0_XHCI_GUCTL1_OFFSET
34563 #define USB3_0_XHCI_GUCTL1_OFFSET 0XFE20C11C
34564 #undef USB3_0_XHCI_GUCTL_OFFSET
34565 #define USB3_0_XHCI_GUCTL_OFFSET 0XFE20C12C
34566 #undef PCIE_ATTRIB_ATTR_25_OFFSET
34567 #define PCIE_ATTRIB_ATTR_25_OFFSET 0XFD480064
34568 #undef PCIE_ATTRIB_ATTR_7_OFFSET
34569 #define PCIE_ATTRIB_ATTR_7_OFFSET 0XFD48001C
34570 #undef PCIE_ATTRIB_ATTR_8_OFFSET
34571 #define PCIE_ATTRIB_ATTR_8_OFFSET 0XFD480020
34572 #undef PCIE_ATTRIB_ATTR_9_OFFSET
34573 #define PCIE_ATTRIB_ATTR_9_OFFSET 0XFD480024
34574 #undef PCIE_ATTRIB_ATTR_10_OFFSET
34575 #define PCIE_ATTRIB_ATTR_10_OFFSET 0XFD480028
34576 #undef PCIE_ATTRIB_ATTR_11_OFFSET
34577 #define PCIE_ATTRIB_ATTR_11_OFFSET 0XFD48002C
34578 #undef PCIE_ATTRIB_ATTR_12_OFFSET
34579 #define PCIE_ATTRIB_ATTR_12_OFFSET 0XFD480030
34580 #undef PCIE_ATTRIB_ATTR_13_OFFSET
34581 #define PCIE_ATTRIB_ATTR_13_OFFSET 0XFD480034
34582 #undef PCIE_ATTRIB_ATTR_14_OFFSET
34583 #define PCIE_ATTRIB_ATTR_14_OFFSET 0XFD480038
34584 #undef PCIE_ATTRIB_ATTR_15_OFFSET
34585 #define PCIE_ATTRIB_ATTR_15_OFFSET 0XFD48003C
34586 #undef PCIE_ATTRIB_ATTR_16_OFFSET
34587 #define PCIE_ATTRIB_ATTR_16_OFFSET 0XFD480040
34588 #undef PCIE_ATTRIB_ATTR_17_OFFSET
34589 #define PCIE_ATTRIB_ATTR_17_OFFSET 0XFD480044
34590 #undef PCIE_ATTRIB_ATTR_18_OFFSET
34591 #define PCIE_ATTRIB_ATTR_18_OFFSET 0XFD480048
34592 #undef PCIE_ATTRIB_ATTR_27_OFFSET
34593 #define PCIE_ATTRIB_ATTR_27_OFFSET 0XFD48006C
34594 #undef PCIE_ATTRIB_ATTR_50_OFFSET
34595 #define PCIE_ATTRIB_ATTR_50_OFFSET 0XFD4800C8
34596 #undef PCIE_ATTRIB_ATTR_105_OFFSET
34597 #define PCIE_ATTRIB_ATTR_105_OFFSET 0XFD4801A4
34598 #undef PCIE_ATTRIB_ATTR_106_OFFSET
34599 #define PCIE_ATTRIB_ATTR_106_OFFSET 0XFD4801A8
34600 #undef PCIE_ATTRIB_ATTR_107_OFFSET
34601 #define PCIE_ATTRIB_ATTR_107_OFFSET 0XFD4801AC
34602 #undef PCIE_ATTRIB_ATTR_108_OFFSET
34603 #define PCIE_ATTRIB_ATTR_108_OFFSET 0XFD4801B0
34604 #undef PCIE_ATTRIB_ATTR_109_OFFSET
34605 #define PCIE_ATTRIB_ATTR_109_OFFSET 0XFD4801B4
34606 #undef PCIE_ATTRIB_ATTR_34_OFFSET
34607 #define PCIE_ATTRIB_ATTR_34_OFFSET 0XFD480088
34608 #undef PCIE_ATTRIB_ATTR_53_OFFSET
34609 #define PCIE_ATTRIB_ATTR_53_OFFSET 0XFD4800D4
34610 #undef PCIE_ATTRIB_ATTR_41_OFFSET
34611 #define PCIE_ATTRIB_ATTR_41_OFFSET 0XFD4800A4
34612 #undef PCIE_ATTRIB_ATTR_97_OFFSET
34613 #define PCIE_ATTRIB_ATTR_97_OFFSET 0XFD480184
34614 #undef PCIE_ATTRIB_ATTR_100_OFFSET
34615 #define PCIE_ATTRIB_ATTR_100_OFFSET 0XFD480190
34616 #undef PCIE_ATTRIB_ATTR_101_OFFSET
34617 #define PCIE_ATTRIB_ATTR_101_OFFSET 0XFD480194
34618 #undef PCIE_ATTRIB_ATTR_37_OFFSET
34619 #define PCIE_ATTRIB_ATTR_37_OFFSET 0XFD480094
34620 #undef PCIE_ATTRIB_ATTR_93_OFFSET
34621 #define PCIE_ATTRIB_ATTR_93_OFFSET 0XFD480174
34622 #undef PCIE_ATTRIB_ID_OFFSET
34623 #define PCIE_ATTRIB_ID_OFFSET 0XFD480200
34624 #undef PCIE_ATTRIB_SUBSYS_ID_OFFSET
34625 #define PCIE_ATTRIB_SUBSYS_ID_OFFSET 0XFD480204
34626 #undef PCIE_ATTRIB_REV_ID_OFFSET
34627 #define PCIE_ATTRIB_REV_ID_OFFSET 0XFD480208
34628 #undef PCIE_ATTRIB_ATTR_24_OFFSET
34629 #define PCIE_ATTRIB_ATTR_24_OFFSET 0XFD480060
34630 #undef PCIE_ATTRIB_ATTR_25_OFFSET
34631 #define PCIE_ATTRIB_ATTR_25_OFFSET 0XFD480064
34632 #undef PCIE_ATTRIB_ATTR_4_OFFSET
34633 #define PCIE_ATTRIB_ATTR_4_OFFSET 0XFD480010
34634 #undef PCIE_ATTRIB_ATTR_89_OFFSET
34635 #define PCIE_ATTRIB_ATTR_89_OFFSET 0XFD480164
34636 #undef PCIE_ATTRIB_ATTR_79_OFFSET
34637 #define PCIE_ATTRIB_ATTR_79_OFFSET 0XFD48013C
34638 #undef PCIE_ATTRIB_ATTR_43_OFFSET
34639 #define PCIE_ATTRIB_ATTR_43_OFFSET 0XFD4800AC
34640 #undef PCIE_ATTRIB_ATTR_48_OFFSET
34641 #define PCIE_ATTRIB_ATTR_48_OFFSET 0XFD4800C0
34642 #undef PCIE_ATTRIB_ATTR_46_OFFSET
34643 #define PCIE_ATTRIB_ATTR_46_OFFSET 0XFD4800B8
34644 #undef PCIE_ATTRIB_ATTR_47_OFFSET
34645 #define PCIE_ATTRIB_ATTR_47_OFFSET 0XFD4800BC
34646 #undef PCIE_ATTRIB_ATTR_44_OFFSET
34647 #define PCIE_ATTRIB_ATTR_44_OFFSET 0XFD4800B0
34648 #undef PCIE_ATTRIB_ATTR_45_OFFSET
34649 #define PCIE_ATTRIB_ATTR_45_OFFSET 0XFD4800B4
34650 #undef PCIE_ATTRIB_CB_OFFSET
34651 #define PCIE_ATTRIB_CB_OFFSET 0XFD48031C
34652 #undef PCIE_ATTRIB_ATTR_35_OFFSET
34653 #define PCIE_ATTRIB_ATTR_35_OFFSET 0XFD48008C
34654 #undef CRF_APB_RST_FPD_TOP_OFFSET
34655 #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
34656 #undef GPIO_MASK_DATA_1_LSW_OFFSET
34657 #define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008
34658 #undef SATA_AHCI_VENDOR_PP2C_OFFSET
34659 #define SATA_AHCI_VENDOR_PP2C_OFFSET 0XFD0C00AC
34660 #undef SATA_AHCI_VENDOR_PP3C_OFFSET
34661 #define SATA_AHCI_VENDOR_PP3C_OFFSET 0XFD0C00B0
34662 #undef SATA_AHCI_VENDOR_PP4C_OFFSET
34663 #define SATA_AHCI_VENDOR_PP4C_OFFSET 0XFD0C00B4
34664 #undef SATA_AHCI_VENDOR_PP5C_OFFSET
34665 #define SATA_AHCI_VENDOR_PP5C_OFFSET 0XFD0C00B8
34668 * USB 0 reset for control registers
34670 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL
34671 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
34672 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK
34673 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF
34674 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10
34675 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U
34678 * USB 0 sleep circuit reset
34680 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL
34681 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
34682 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK
34683 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF
34684 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8
34685 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U
34690 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL
34691 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
34692 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK
34693 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF
34694 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6
34695 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U
34700 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL
34701 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
34702 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK
34703 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F
34704 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3
34705 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U
34708 * Sata PM clock control select
34710 #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL
34711 #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT
34712 #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK
34713 #define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL
34714 #define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT 0
34715 #define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK 0x00000003U
34718 * Sata block level reset
34720 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL
34721 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
34722 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK
34723 #define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE
34724 #define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1
34725 #define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U
34728 * PCIE config reset
34730 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL
34731 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
34732 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK
34733 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE
34734 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19
34735 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U
34738 * PCIE bridge block level reset (AXI interface)
34740 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL
34741 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
34742 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK
34743 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE
34744 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18
34745 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U
34748 * Display Port block level reset (includes DPDMA)
34750 #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL
34751 #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
34752 #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK
34753 #define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE
34754 #define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16
34755 #define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U
34758 * Set to '1' to hold the GT in reset. Clear to release.
34760 #undef DP_DP_PHY_RESET_GT_RESET_DEFVAL
34761 #undef DP_DP_PHY_RESET_GT_RESET_SHIFT
34762 #undef DP_DP_PHY_RESET_GT_RESET_MASK
34763 #define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003
34764 #define DP_DP_PHY_RESET_GT_RESET_SHIFT 1
34765 #define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U
34768 * Two bits per lane. When set to 11, moves the GT to power down mode. When
34769 * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] -
34772 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL
34773 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
34774 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK
34775 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000
34776 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0
34777 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU
34780 * USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY cloc
34781 * ks. Specifies the response time for a MAC request to the Packet FIFO Con
34782 * troller (PFC) to fetch data from the DFIFO (SPRAM). The following are th
34783 * e required values for the minimum SoC bus frequency of 60 MHz. USB turna
34784 * round time is a critical certification criteria when using long cables a
34785 * nd five hub levels. The required values for this field: - 4'h5: When the
34786 * MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
34787 * UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround tim
34788 * e is not critical, this field can be set to a larger value. Note: This f
34789 * ield is valid only in device mode.
34791 #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL
34792 #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT
34793 #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK
34794 #define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL 0x00000000
34795 #define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT 10
34796 #define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK 0x00003C00U
34799 * Transceiver Delay: Enables a delay between the assertion of the UTMI/ULP
34800 * I Transceiver Select signal (for HS) and the assertion of the TxValid si
34801 * gnal during a HS Chirp. When this bit is set to 1, a delay (of approxima
34802 * tely 2.5 us) is introduced from the time when the Transceiver Select is
34803 * set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the
34804 * chirp-K. This delay is required for some UTMI/ULPI PHYs. Note: - If you
34805 * enable the hibernation feature when the device core comes out of power-
34806 * off, you must re-initialize this bit with the appropriate value because
34807 * the core does not save and restore this bit value during hibernation. -
34808 * This bit is valid only in device mode.
34810 #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL
34811 #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT
34812 #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK
34813 #define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL 0x00000000
34814 #define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT 9
34815 #define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK 0x00000200U
34818 * Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application use
34819 * s this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to th
34820 * e PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assert
34821 * ion from the core is not transferred to the external PHY. - 1'b1: utmi_s
34822 * leep_n and utmi_l1_suspend_n assertion from the core is transferred to t
34823 * he external PHY. Note: This bit must be set high for Port0 if PHY is use
34824 * d. Note: In Device mode - Before issuing any device endpoint command whe
34825 * n operating in 2.0 speeds, disable this bit and enable it after the comm
34826 * and completes. Without disabling this bit, if a command is issued when t
34827 * he device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated of
34828 * f, the command will not get completed.
34830 #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL
34831 #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT
34832 #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK
34833 #define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL 0x00000000
34834 #define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT 8
34835 #define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK 0x00000100U
34838 * USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select T
34839 * he application uses this bit to select a high-speed PHY or a full-speed
34840 * transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is a
34841 * lways 0, with Write Only access. - 1'b1: USB 1.1 full-speed serial trans
34842 * ceiver. This bit is always 1, with Write Only access. If both interface
34843 * types are selected in coreConsultant (that is, parameters' values are no
34844 * t zero), the application uses this bit to select the active interface is
34845 * active, with Read-Write bit access. Note: USB 1.1 full-serial transceiv
34846 * er is not supported. This bit always reads as 1'b0.
34848 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL
34849 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT
34850 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK
34851 #define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL 0x00000000
34852 #define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 7
34853 #define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK 0x00000080U
34856 * Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend
34857 * mode if Suspend conditions are valid. For DRD/OTG configurations, it is
34858 * recommended that this bit is set to 0 during coreConsultant configurati
34859 * on. If it is set to 1, then the application must clear this bit after po
34860 * wer-on reset. Application needs to set it to 1 after the core initializa
34861 * tion completes. For all other configurations, this bit can be set to 1 d
34862 * uring core configuration. Note: - In host mode, on reset, this bit is se
34863 * t to 1. Software can override this bit after reset. - In device mode, be
34864 * fore issuing any device endpoint command when operating in 2.0 speeds, d
34865 * isable this bit and enable it after the command completes. If you issue
34866 * a command without disabling this bit when the device is in L2 state and
34867 * if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get c
34870 #undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL
34871 #undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT
34872 #undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK
34873 #define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL 0x00000000
34874 #define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT 6
34875 #define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK 0x00000040U
34878 * Full-Speed Serial Interface Select (FSIntf) The application uses this bi
34879 * t to select a unidirectional or bidirectional USB 1.1 full-speed serial
34880 * transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial in
34881 * terface. This bit is set to 0 with Read Only access. - 1'b1: 3-pin bidir
34882 * ectional full-speed serial interface. This bit is set to 0 with Read Onl
34883 * y access. Note: USB 1.1 full-speed serial interface is not supported. Th
34884 * is bit always reads as 1'b0.
34886 #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL
34887 #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT
34888 #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK
34889 #define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL 0x00000000
34890 #define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT 5
34891 #define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK 0x00000020U
34894 * ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to se
34895 * lect a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Int
34896 * erface This bit is writable only if UTMI+ and ULPI is specified for High
34897 * -Speed PHY Interface(s) in coreConsultant configuration (DWC_USB3_HSPHY_
34898 * INTERFACE = 3). Otherwise, this bit is read-only and the value depends o
34899 * n the interface selected through DWC_USB3_HSPHY_INTERFACE.
34901 #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL
34902 #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT
34903 #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK
34904 #define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL 0x00000000
34905 #define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT 4
34906 #define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK 0x00000010U
34909 * PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bi
34910 * t to configure the core to support a UTMI+ PHY with an 8- or 16-bit inte
34911 * rface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the en
34912 * abled 2.0 ports must have the same clock frequency as Port0 clock freque
34913 * ncy (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used toge
34914 * ther for different ports at the same time (that is, all the ports must b
34915 * e in 8-bit mode, or all of them must be in 16-bit mode, at a time). - If
34916 * any of the USB 2.0 ports is selected as ULPI port for operation, then a
34917 * ll the USB 2.0 ports must be operating at 60 MHz.
34919 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL
34920 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT
34921 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK
34922 #define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL 0x00000000
34923 #define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT 3
34924 #define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK 0x00000008U
34927 * HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicat
34928 * ed by the application in this field, is multiplied by a bit-time factor;
34929 * this factor is added to the high-speed/full-speed interpacket timeout d
34930 * uration in the core to account for additional delays introduced by the P
34931 * HY. This may be required, since the delay introduced by the PHY in gener
34932 * ating the linestate condition may vary among PHYs. The USB standard time
34933 * out value for high-speed operation is 736 to 816 (inclusive) bit times.
34934 * The USB standard timeout value for full-speed operation is 16 to 18 (inc
34935 * lusive) bit times. The application must program this field based on the
34936 * speed of connection. The number of bit times added per PHY clock are: Hi
34937 * gh-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz P
34938 * HY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.
34939 * 4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY cloc
34940 * k = 0.25 bit times
34942 #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL
34943 #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT
34944 #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK
34945 #define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL 0x00000000
34946 #define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT 0
34947 #define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK 0x00000007U
34950 * ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive
34951 * 5V on VBUS, in the ULPI PHY. - 1'b0: PHY drives VBUS with internal char
34952 * ge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Onl
34953 * y when RTL parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3)
34955 #undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_DEFVAL
34956 #undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT
34957 #undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK
34958 #define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_DEFVAL 0x00000000
34959 #define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT 17
34960 #define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK 0x00020000U
34963 * This field indicates the frame length adjustment to be applied when SOF/
34964 * ITP counter is running on the ref_clk. This register value is used to ad
34965 * just the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP i
34966 * nterval when GLADJ.GFLADJ_REFCLK_LPM_SEL is set to '1'. This field must
34967 * be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set t
34968 * o '1' or GCTL.SOFITPSYNC is set to '1'. The value is derived as follows:
34969 * FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_pe
34970 * riod)) * ref_clk_period where - the ref_clk_period_integer is the intege
34971 * r value of the ref_clk period got by truncating the decimal (fractional)
34972 * value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_c
34973 * lk_period is the ref_clk period including the fractional value. Examples
34974 * : If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLA
34975 * DJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignorin
34976 * g the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_PE
34977 * RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*2
34978 * 0.8333 = 5208 (ignoring the fractional value)
34980 #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL
34981 #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT
34982 #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK
34983 #define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL 0x00000000
34984 #define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 8
34985 #define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 0x003FFF00U
34988 * When this bit is set to '0', termsel, xcvrsel will become 0 during end o
34989 * f resume while the opmode will become 0 once controller completes end of
34990 * resume and enters U0 state (2 separate commandswill be issued). When th
34991 * is bit is set to '1', all the termsel, xcvrsel, opmode becomes 0 during
34992 * end of resume itself (only 1 command will be issued)
34994 #undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_DEFVAL
34995 #undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_SHIFT
34996 #undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_MASK
34997 #define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_DEFVAL 0x00000000
34998 #define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_SHIFT 10
34999 #define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_MASK 0x00000400U
35004 #undef USB3_0_XHCI_GUCTL1_RESERVED_9_DEFVAL
35005 #undef USB3_0_XHCI_GUCTL1_RESERVED_9_SHIFT
35006 #undef USB3_0_XHCI_GUCTL1_RESERVED_9_MASK
35007 #define USB3_0_XHCI_GUCTL1_RESERVED_9_DEFVAL 0x00000000
35008 #define USB3_0_XHCI_GUCTL1_RESERVED_9_SHIFT 9
35009 #define USB3_0_XHCI_GUCTL1_RESERVED_9_MASK 0x00000200U
35012 * Host IN Auto Retry (USBHstInAutoRetryEn) When set, this field enables th
35013 * e Auto Retry feature. For IN transfers (non-isochronous) that encounter
35014 * data packets with CRC errors or internal overrun scenarios, the auto ret
35015 * ry feature causes the Host core to reply to the device with a non-termin
35016 * ating retry ACK (that is, an ACK transaction packet with Retry = 1 and N
35017 * umP != 0). If the Auto Retry feature is disabled (default), the core wil
35018 * l respond with a terminating retry ACK (that is, an ACK transaction pack
35019 * et with Retry = 1 and NumP = 0). - 1'b0: Auto Retry Disabled - 1'b1: Aut
35020 * o Retry Enabled Note: This bit is also applicable to the device mode.
35022 #undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_DEFVAL
35023 #undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_SHIFT
35024 #undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_MASK
35025 #define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_DEFVAL 0x00000000
35026 #define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_SHIFT 14
35027 #define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_MASK 0x00004000U
35030 * If TRUE Completion Timeout Disable is supported. This is required to be
35031 * TRUE for Endpoint and either setting allowed for Root ports. Drives Devi
35032 * ce Capability 2 [4]; EP=0x0001; RP=0x0001
35034 #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL
35035 #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT
35036 #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK
35037 #define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL 0x00000905
35038 #define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT 9
35039 #define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK 0x00000200U
35042 * Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not
35043 * to be implemented, set to 32'h00000000. Bits are defined as follows: Me
35044 * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (
35045 * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask
35046 * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w
35047 * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:
35048 * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator (
35049 * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B
35050 * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.;
35051 * EP=0x0004; RP=0x0000
35053 #undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL
35054 #undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT
35055 #undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK
35056 #define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL
35057 #define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT 0
35058 #define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK 0x0000FFFFU
35061 * Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not
35062 * to be implemented, set to 32'h00000000. Bits are defined as follows: Me
35063 * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (
35064 * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask
35065 * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w
35066 * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:
35067 * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator (
35068 * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B
35069 * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.;
35070 * EP=0xFFF0; RP=0x0000
35072 #undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL
35073 #undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT
35074 #undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK
35075 #define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL
35076 #define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT 0
35077 #define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK 0x0000FFFFU
35080 * Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3
35081 * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA
35082 * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri
35083 * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi
35084 * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac
35085 * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit)
35086 * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
35087 * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size
35088 * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t
35089 * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set
35090 * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t
35091 * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
35093 #undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL
35094 #undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT
35095 #undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK
35096 #define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL
35097 #define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT 0
35098 #define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK 0x0000FFFFU
35101 * Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3
35102 * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA
35103 * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri
35104 * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi
35105 * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac
35106 * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit)
35107 * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
35108 * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size
35109 * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t
35110 * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set
35111 * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t
35112 * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
35114 #undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL
35115 #undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT
35116 #undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK
35117 #define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL
35118 #define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT 0
35119 #define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK 0x0000FFFFU
35122 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
35123 * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA
35124 * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
35125 * et to 32'h00000000. See BAR1 description if this functions as the upper
35126 * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF
35127 * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u
35128 * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie
35129 * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M
35130 * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to
35131 * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost
35132 * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat
35133 * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits
35134 * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt
35135 * es.; EP=0x0004; RP=0xFFFF
35137 #undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL
35138 #undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT
35139 #undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK
35140 #define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL
35141 #define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT 0
35142 #define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK 0x0000FFFFU
35145 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
35146 * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA
35147 * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
35148 * et to 32'h00000000. See BAR1 description if this functions as the upper
35149 * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF
35150 * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u
35151 * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie
35152 * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M
35153 * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to
35154 * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost
35155 * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat
35156 * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits
35157 * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt
35158 * es.; EP=0xFFF0; RP=0x00FF
35160 #undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL
35161 #undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT
35162 #undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK
35163 #define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL
35164 #define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT 0
35165 #define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK 0x0000FFFFU
35168 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
35169 * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA
35170 * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
35171 * et to 32'h00000000. See BAR2 description if this functions as the upper
35172 * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00
35173 * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R
35174 * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi
35175 * t decode For an endpoint, bits are defined as follows: Memory Space BAR
35176 * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty
35177 * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:
35178 * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi
35179 * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp
35180 * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I
35181 * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable
35182 * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size
35183 * in bytes.; EP=0xFFFF; RP=0x0000
35185 #undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL
35186 #undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT
35187 #undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK
35188 #define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL
35189 #define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT 0
35190 #define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK 0x0000FFFFU
35193 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
35194 * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA
35195 * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
35196 * et to 32'h00000000. See BAR2 description if this functions as the upper
35197 * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00
35198 * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R
35199 * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi
35200 * t decode For an endpoint, bits are defined as follows: Memory Space BAR
35201 * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty
35202 * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:
35203 * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi
35204 * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp
35205 * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I
35206 * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable
35207 * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size
35208 * in bytes.; EP=0xFFFF; RP=0xFFFF
35210 #undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL
35211 #undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT
35212 #undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK
35213 #define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL
35214 #define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT 0
35215 #define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK 0x0000FFFFU
35218 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
35219 * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA
35220 * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
35221 * et to 32'h00000000. See BAR3 description if this functions as the upper
35222 * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF
35223 * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u
35224 * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie
35225 * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M
35226 * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to
35227 * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost
35228 * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat
35229 * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits
35230 * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt
35231 * es.; EP=0x0004; RP=0xFFF0
35233 #undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL
35234 #undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT
35235 #undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK
35236 #define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL
35237 #define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT 0
35238 #define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK 0x0000FFFFU
35241 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
35242 * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA
35243 * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
35244 * et to 32'h00000000. See BAR3 description if this functions as the upper
35245 * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF
35246 * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u
35247 * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie
35248 * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M
35249 * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to
35250 * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost
35251 * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat
35252 * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits
35253 * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt
35254 * es.; EP=0xFFF0; RP=0xFFF0
35256 #undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL
35257 #undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT
35258 #undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK
35259 #define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL
35260 #define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT 0
35261 #define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK 0x0000FFFFU
35264 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
35265 * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA
35266 * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
35267 * et to 32'h00000000. See BAR4 description if this functions as the upper
35268 * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00
35269 * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0
35270 * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P
35271 * refetchable Memory Limit/Base implemented For an endpoint, bits are defi
35272 * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac
35273 * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be
35274 * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f
35275 * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory
35276 * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1)
35277 * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up
35278 * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF
35281 #undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL
35282 #undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT
35283 #undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK
35284 #define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL
35285 #define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT 0
35286 #define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK 0x0000FFFFU
35289 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
35290 * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA
35291 * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
35292 * et to 32'h00000000. See BAR4 description if this functions as the upper
35293 * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00
35294 * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0
35295 * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P
35296 * refetchable Memory Limit/Base implemented For an endpoint, bits are defi
35297 * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac
35298 * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be
35299 * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f
35300 * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory
35301 * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1)
35302 * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up
35303 * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF
35306 #undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL
35307 #undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT
35308 #undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK
35309 #define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL
35310 #define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT 0
35311 #define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK 0x0000FFFFU
35314 * Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1
35315 * - 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred to the Device Capa
35316 * bilities register. The values: 4-2048 bytes, 5- 4096 bytes are not suppo
35317 * rted; EP=0x0001; RP=0x0001
35319 #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL
35320 #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT
35321 #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK
35322 #define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL 0x00002138
35323 #define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT 8
35324 #define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK 0x00000700U
35327 * Endpoint L1 Acceptable Latency. Records the latency that the endpoint ca
35328 * n withstand on transitions from L1 state to L0 (if L1 state supported).
35329 * Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to
35330 * 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For
35331 * Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000
35333 #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL
35334 #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT
35335 #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK
35336 #define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL 0x00002138
35337 #define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT 3
35338 #define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK 0x00000038U
35341 * Identifies the type of device/port as follows: 0000b PCI Express Endpoin
35342 * t device, 0001b Legacy PCI Express Endpoint device, 0100b Root Port of P
35343 * CI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110
35344 * b Downstream Port of PCI Express Switch, 0111b PCIE Express to PCI/PCI-X
35345 * Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Expre
35346 * ss Capabilities register. Must be consistent with IS_SWITCH and UPSTREAM
35347 * _FACING settings.; EP=0x0000; RP=0x0004
35349 #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL
35350 #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT
35351 #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK
35352 #define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL 0x00009C02
35353 #define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT 4
35354 #define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK 0x000000F0U
35357 * PCIe Capability's Next Capability Offset pointer to the next item in the
35358 * capabilities list, or 00h if this is the final capability.; EP=0x009C;
35361 #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL
35362 #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT
35363 #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK
35364 #define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL 0x00009C02
35365 #define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT 8
35366 #define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK 0x0000FF00U
35369 * Number of credits that should be advertised for Completion data received
35370 * on Virtual Channel 0. The bytes advertised must be less than or equal t
35371 * o the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD
35373 #undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL
35374 #undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT
35375 #undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK
35376 #define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL
35377 #define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT 0
35378 #define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK 0x000007FFU
35381 * Number of credits that should be advertised for Completion headers recei
35382 * ved on Virtual Channel 0. The sum of the posted, non posted, and complet
35383 * ion header credits must be <= 80; EP=0x0048; RP=0x0024
35385 #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL
35386 #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT
35387 #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK
35388 #define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL 0x00000248
35389 #define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT 0
35390 #define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK 0x0000007FU
35393 * Number of credits that should be advertised for Non-Posted headers recei
35394 * ved on Virtual Channel 0. The number of non posted data credits advertis
35395 * ed by the block is equal to the number of non posted header credits. The
35396 * sum of the posted, non posted, and completion header credits must be <=
35397 * 80; EP=0x0004; RP=0x000C
35399 #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL
35400 #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT
35401 #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK
35402 #define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL 0x00000248
35403 #define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT 7
35404 #define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK 0x00003F80U
35407 * Number of credits that should be advertised for Non-Posted data received
35408 * on Virtual Channel 0. The number of non posted data credits advertised
35409 * by the block is equal to two times the number of non posted header credi
35410 * ts if atomic operations are supported or is equal to the number of non p
35411 * osted header credits if atomic operations are not supported. The bytes a
35412 * dvertised must be less than or equal to the bram bytes available. See VC
35413 * 0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018
35415 #undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL
35416 #undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT
35417 #undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK
35418 #define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL
35419 #define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT 0
35420 #define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK 0x000007FFU
35423 * Number of credits that should be advertised for Posted data received on
35424 * Virtual Channel 0. The bytes advertised must be less than or equal to th
35425 * e bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5
35427 #undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL
35428 #undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT
35429 #undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK
35430 #define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL
35431 #define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT 0
35432 #define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK 0x000007FFU
35435 * Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_
35436 * n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x0000
35438 #undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL
35439 #undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT
35440 #undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK
35441 #define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL 0x00007E04
35442 #define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT 15
35443 #define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK 0x00008000U
35446 * Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim
35447 * TRUE == trim.; EP=0x0001; RP=0x0001
35449 #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL
35450 #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT
35451 #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK
35452 #define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL 0x00007E04
35453 #define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT 14
35454 #define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK 0x00004000U
35457 * Enables ECRC check on received TLP's 0 == don't check 1 == always check
35458 * 3 == check if enabled by ECRC check enable bit of AER cap structure; EP=
35459 * 0x0003; RP=0x0003
35461 #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL
35462 #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT
35463 #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK
35464 #define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL 0x00007E04
35465 #define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT 12
35466 #define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK 0x00003000U
35469 * Index of last packet buffer used by TX TLM (i.e. number of buffers - 1).
35470 * Calculated from max payload size supported and the number of brams conf
35471 * igured for transmit; EP=0x001C; RP=0x001C
35473 #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL
35474 #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT
35475 #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK
35476 #define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL 0x00007E04
35477 #define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT 7
35478 #define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK 0x00000F80U
35481 * Number of credits that should be advertised for Posted headers received
35482 * on Virtual Channel 0. The sum of the posted, non posted, and completion
35483 * header credits must be <= 80; EP=0x0004; RP=0x0020
35485 #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL
35486 #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT
35487 #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK
35488 #define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL 0x00007E04
35489 #define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT 0
35490 #define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK 0x0000007FU
35493 * Specifies values to be transferred to Header Type register. Bit 7 should
35494 * be set to '0' indicating single-function device. Bit 0 identifies heade
35495 * r as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000;
35498 #undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL
35499 #undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT
35500 #undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK
35501 #define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL 0x00000100
35502 #define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT 0
35503 #define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK 0x000000FFU
35506 * PM Capability's Next Capability Offset pointer to the next item in the c
35507 * apabilities list, or 00h if this is the final capability.; EP=0x0048; RP
35510 #undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL
35511 #undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT
35512 #undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK
35513 #define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL 0x00003D48
35514 #define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT 0
35515 #define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK 0x000000FFU
35518 * MSI Per-Vector Masking Capable. The value is transferred to the MSI Cont
35519 * rol Register[8]. When set, adds Mask and Pending Dword to Cap structure;
35520 * EP=0x0000; RP=0x0000
35522 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL
35523 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT
35524 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK
35525 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL 0x00000160
35526 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT 9
35527 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK 0x00000200U
35530 * Indicates that the MSI structures exists. If this is FALSE, then the MSI
35531 * structure cannot be accessed via either the link or the management port
35532 * .; EP=0x0001; RP=0x0000
35534 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL
35535 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT
35536 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK
35537 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160
35538 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8
35539 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U
35542 * MSI Capability's Next Capability Offset pointer to the next item in the
35543 * capabilities list, or 00h if this is the final capability.; EP=0x0060; R
35546 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL
35547 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT
35548 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK
35549 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL 0x00000160
35550 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT 0
35551 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK 0x000000FFU
35554 * Indicates that the MSI structures exists. If this is FALSE, then the MSI
35555 * structure cannot be accessed via either the link or the management port
35556 * .; EP=0x0001; RP=0x0000
35558 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL
35559 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT
35560 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK
35561 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160
35562 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8
35563 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U
35566 * Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b
35567 * x4, 001000b x8.; EP=0x0004; RP=0x0004
35569 #undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL
35570 #undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT
35571 #undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK
35572 #define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL 0x00000104
35573 #define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT 0
35574 #define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK 0x0000003FU
35577 * Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1
35578 * ], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x0004; RP=0x0004
35580 #undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL
35581 #undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT
35582 #undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK
35583 #define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL 0x00000104
35584 #define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT 6
35585 #define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK 0x00000FC0U
35588 * TRUE specifies upstream-facing port. FALSE specifies downstream-facing p
35589 * ort.; EP=0x0001; RP=0x0000
35591 #undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL
35592 #undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT
35593 #undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK
35594 #define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL 0x000000F0
35595 #define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT 6
35596 #define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK 0x00000040U
35599 * Enable the routing of message TLPs to the user through the TRN RX interf
35600 * ace. A bit value of 1 enables routing of the message TLP to the user. Me
35601 * ssages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1
35602 * - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - I
35603 * NTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit
35604 * 10 PME_Turn_Off; EP=0x0000; RP=0x07FF
35606 #undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL
35607 #undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT
35608 #undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK
35609 #define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL 0x00000000
35610 #define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT 5
35611 #define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK 0x0000FFE0U
35614 * Disable BAR filtering. Does not change the behavior of the bar hit outpu
35615 * ts; EP=0x0000; RP=0x0001
35617 #undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL
35618 #undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT
35619 #undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK
35620 #define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL 0x00000000
35621 #define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT 1
35622 #define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK 0x00000002U
35625 * Link Bandwidth notification capability. Indicates support for the link b
35626 * andwidth notification status and interrupt mechanism. Required for Root.
35627 * ; EP=0x0000; RP=0x0001
35629 #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL
35630 #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT
35631 #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK
35632 #define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL 0x000009FF
35633 #define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT 9
35634 #define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK 0x00000200U
35637 * Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Op
35638 * tionality ECN. Transferred to the Link Capabilities register.; EP=0x0001
35641 #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL
35642 #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT
35643 #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK
35644 #define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 0x000009FF
35645 #define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 14
35646 #define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 0x00004000U
35649 * Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value
35650 * (or combined with the built-in value, depending on LL_REPLAY_TIMEOUT_FU
35651 * NC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000
35653 #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL
35654 #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT
35655 #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK
35656 #define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL 0x00000000
35657 #define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT 15
35658 #define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK 0x00008000U
35661 * Sets a user-defined timeout for the Replay Timer to force cause the retr
35662 * ansmission of unacknowledged TLPs; refer to LL_REPLAY_TIMEOUT_EN and LL_
35663 * REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this att
35664 * ribute is in symbol times, which is 4ns at GEN1 speeds and 2ns at GEN2.;
35665 * EP=0x0000; RP=0x0000
35667 #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL
35668 #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT
35669 #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK
35670 #define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL 0x00000000
35671 #define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT 0
35672 #define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK 0x00007FFFU
35675 * Device ID for the the PCIe Cap Structure Device ID field
35677 #undef PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL
35678 #undef PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT
35679 #undef PCIE_ATTRIB_ID_CFG_DEV_ID_MASK
35680 #define PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL 0x10EE7024
35681 #define PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT 0
35682 #define PCIE_ATTRIB_ID_CFG_DEV_ID_MASK 0x0000FFFFU
35685 * Vendor ID for the PCIe Cap Structure Vendor ID field
35687 #undef PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL
35688 #undef PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT
35689 #undef PCIE_ATTRIB_ID_CFG_VEND_ID_MASK
35690 #define PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL 0x10EE7024
35691 #define PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT 16
35692 #define PCIE_ATTRIB_ID_CFG_VEND_ID_MASK 0xFFFF0000U
35695 * Subsystem ID for the the PCIe Cap Structure Subsystem ID field
35697 #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL
35698 #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT
35699 #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK
35700 #define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL 0x10EE0007
35701 #define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT 0
35702 #define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK 0x0000FFFFU
35705 * Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field
35707 #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL
35708 #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT
35709 #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK
35710 #define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL 0x10EE0007
35711 #define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT 16
35712 #define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK 0xFFFF0000U
35715 * Revision ID for the the PCIe Cap Structure
35717 #undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL
35718 #undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT
35719 #undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK
35720 #define PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL
35721 #define PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT 0
35722 #define PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK 0x000000FFU
35725 * Code identifying basic function, subclass and applicable programming int
35726 * erface. Transferred to the Class Code register.; EP=0x8000; RP=0x8000
35728 #undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL
35729 #undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT
35730 #undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK
35731 #define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL
35732 #define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT 0
35733 #define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK 0x0000FFFFU
35736 * Code identifying basic function, subclass and applicable programming int
35737 * erface. Transferred to the Class Code register.; EP=0x0005; RP=0x0006
35739 #undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL
35740 #undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT
35741 #undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK
35742 #define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL 0x00000905
35743 #define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT 0
35744 #define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK 0x000000FFU
35747 * INTX Interrupt Generation Capable. If FALSE, this will cause Command[10]
35748 * to be hardwired to 0.; EP=0x0001; RP=0x0001
35750 #undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL
35751 #undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT
35752 #undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK
35753 #define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL 0x00000905
35754 #define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT 8
35755 #define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK 0x00000100U
35758 * Indicates that the AER structures exists. If this is FALSE, then the AER
35759 * structure cannot be accessed via either the link or the management port
35760 * , and AER will be considered to not be present for error management task
35761 * s (such as what types of error messages are sent if an error is detected
35762 * ).; EP=0x0001; RP=0x0001
35764 #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL
35765 #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT
35766 #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK
35767 #define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000
35768 #define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12
35769 #define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U
35772 * Indicates that the AER structures exists. If this is FALSE, then the AER
35773 * structure cannot be accessed via either the link or the management port
35774 * , and AER will be considered to not be present for error management task
35775 * s (such as what types of error messages are sent if an error is detected
35776 * ).; EP=0x0001; RP=0x0001
35778 #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL
35779 #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT
35780 #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK
35781 #define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000
35782 #define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12
35783 #define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U
35786 * VSEC's Next Capability Offset pointer to the next item in the capabiliti
35787 * es list, or 000h if this is the final capability.; EP=0x0140; RP=0x0140
35789 #undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL
35790 #undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT
35791 #undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK
35792 #define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL 0x00002281
35793 #define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT 1
35794 #define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK 0x00001FFEU
35797 * CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the
35798 * Root Capabilities register.; EP=0x0000; RP=0x0000
35800 #undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL
35801 #undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT
35802 #undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK
35803 #define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL 0x00000000
35804 #define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT 5
35805 #define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK 0x00000020U
35808 * Indicates that the MSIX structures exists. If this is FALSE, then the MS
35809 * IX structure cannot be accessed via either the link or the management po
35810 * rt.; EP=0x0001; RP=0x0000
35812 #undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL
35813 #undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT
35814 #undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK
35815 #define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL 0x00000100
35816 #define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT 8
35817 #define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK 0x00000100U
35820 * MSI-X Table Size. This value is transferred to the MSI-X Message Control
35821 * [10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does
35822 * not implement the table; that must be implemented in user logic.; EP=0x0
35825 #undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL
35826 #undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT
35827 #undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK
35828 #define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL
35829 #define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT 0
35830 #define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK 0x000007FFU
35833 * MSI-X Table Offset. This value is transferred to the MSI-X Table Offset
35834 * field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000
35836 #undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL
35837 #undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT
35838 #undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK
35839 #define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL
35840 #define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0
35841 #define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x0000FFFFU
35844 * MSI-X Table Offset. This value is transferred to the MSI-X Table Offset
35845 * field. Set to 0 if MSI-X is not enabled.; EP=0x0000; RP=0x0000
35847 #undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL
35848 #undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT
35849 #undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK
35850 #define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL
35851 #define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0
35852 #define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x00001FFFU
35855 * MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB
35856 * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000
35858 #undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL
35859 #undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT
35860 #undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK
35861 #define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL
35862 #define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 0
35863 #define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFFFU
35866 * MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB
35867 * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x1000; RP=0x0000
35869 #undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL
35870 #undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT
35871 #undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK
35872 #define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL 0x00008000
35873 #define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 3
35874 #define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFF8U
35879 #undef PCIE_ATTRIB_CB_CB1_DEFVAL
35880 #undef PCIE_ATTRIB_CB_CB1_SHIFT
35881 #undef PCIE_ATTRIB_CB_CB1_MASK
35882 #define PCIE_ATTRIB_CB_CB1_DEFVAL 0x00000001
35883 #define PCIE_ATTRIB_CB_CB1_SHIFT 1
35884 #define PCIE_ATTRIB_CB_CB1_MASK 0x00000002U
35887 * Active State PM Support. Indicates the level of active state power manag
35888 * ement supported by the selected PCI Express Link, encoded as follows: 0
35889 * Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supporte
35890 * d.; EP=0x0001; RP=0x0001
35892 #undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL
35893 #undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT
35894 #undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK
35895 #define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL 0x00001FFD
35896 #define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT 12
35897 #define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK 0x00003000U
35900 * PCIE control block level reset
35902 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL
35903 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
35904 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK
35905 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE
35906 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17
35907 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U
35910 * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
35912 #undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL
35913 #undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT
35914 #undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK
35915 #define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000
35916 #define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16
35917 #define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U
35920 * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]
35922 #undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL
35923 #undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT
35924 #undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK
35925 #define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000
35926 #define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0
35927 #define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU
35930 * Status Read value of PLL Lock
35932 #undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
35933 #undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
35934 #undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
35935 #define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
35936 #define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
35937 #define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
35938 #define SERDES_L0_PLL_STATUS_READ_1_OFFSET 0XFD4023E4
35941 * Status Read value of PLL Lock
35943 #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
35944 #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
35945 #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
35946 #define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
35947 #define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
35948 #define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
35949 #define SERDES_L1_PLL_STATUS_READ_1_OFFSET 0XFD4063E4
35952 * Status Read value of PLL Lock
35954 #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
35955 #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
35956 #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
35957 #define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
35958 #define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
35959 #define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
35960 #define SERDES_L2_PLL_STATUS_READ_1_OFFSET 0XFD40A3E4
35963 * Status Read value of PLL Lock
35965 #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
35966 #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
35967 #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
35968 #define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
35969 #define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
35970 #define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
35971 #define SERDES_L3_PLL_STATUS_READ_1_OFFSET 0XFD40E3E4
35974 * CIBGMN: COMINIT Burst Gap Minimum.
35976 #undef SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL
35977 #undef SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT
35978 #undef SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK
35979 #define SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL 0x28184D1B
35980 #define SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT 0
35981 #define SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK 0x000000FFU
35984 * CIBGMX: COMINIT Burst Gap Maximum.
35986 #undef SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL
35987 #undef SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT
35988 #undef SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK
35989 #define SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL 0x28184D1B
35990 #define SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT 8
35991 #define SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK 0x0000FF00U
35994 * CIBGN: COMINIT Burst Gap Nominal.
35996 #undef SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL
35997 #undef SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT
35998 #undef SATA_AHCI_VENDOR_PP2C_CIBGN_MASK
35999 #define SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL 0x28184D1B
36000 #define SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT 16
36001 #define SATA_AHCI_VENDOR_PP2C_CIBGN_MASK 0x00FF0000U
36004 * CINMP: COMINIT Negate Minimum Period.
36006 #undef SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL
36007 #undef SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT
36008 #undef SATA_AHCI_VENDOR_PP2C_CINMP_MASK
36009 #define SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL 0x28184D1B
36010 #define SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT 24
36011 #define SATA_AHCI_VENDOR_PP2C_CINMP_MASK 0xFF000000U
36014 * CWBGMN: COMWAKE Burst Gap Minimum.
36016 #undef SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL
36017 #undef SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT
36018 #undef SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK
36019 #define SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL 0x0E081906
36020 #define SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT 0
36021 #define SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK 0x000000FFU
36024 * CWBGMX: COMWAKE Burst Gap Maximum.
36026 #undef SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL
36027 #undef SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT
36028 #undef SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK
36029 #define SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL 0x0E081906
36030 #define SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT 8
36031 #define SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK 0x0000FF00U
36034 * CWBGN: COMWAKE Burst Gap Nominal.
36036 #undef SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL
36037 #undef SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT
36038 #undef SATA_AHCI_VENDOR_PP3C_CWBGN_MASK
36039 #define SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL 0x0E081906
36040 #define SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT 16
36041 #define SATA_AHCI_VENDOR_PP3C_CWBGN_MASK 0x00FF0000U
36044 * CWNMP: COMWAKE Negate Minimum Period.
36046 #undef SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL
36047 #undef SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT
36048 #undef SATA_AHCI_VENDOR_PP3C_CWNMP_MASK
36049 #define SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL 0x0E081906
36050 #define SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT 24
36051 #define SATA_AHCI_VENDOR_PP3C_CWNMP_MASK 0xFF000000U
36054 * BMX: COM Burst Maximum.
36056 #undef SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL
36057 #undef SATA_AHCI_VENDOR_PP4C_BMX_SHIFT
36058 #undef SATA_AHCI_VENDOR_PP4C_BMX_MASK
36059 #define SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL 0x064A0813
36060 #define SATA_AHCI_VENDOR_PP4C_BMX_SHIFT 0
36061 #define SATA_AHCI_VENDOR_PP4C_BMX_MASK 0x000000FFU
36064 * BNM: COM Burst Nominal.
36066 #undef SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL
36067 #undef SATA_AHCI_VENDOR_PP4C_BNM_SHIFT
36068 #undef SATA_AHCI_VENDOR_PP4C_BNM_MASK
36069 #define SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL 0x064A0813
36070 #define SATA_AHCI_VENDOR_PP4C_BNM_SHIFT 8
36071 #define SATA_AHCI_VENDOR_PP4C_BNM_MASK 0x0000FF00U
36074 * SFD: Signal Failure Detection, if the signal detection de-asserts for a
36075 * time greater than this then the OOB detector will determine this is a li
36076 * ne idle and cause the PhyInit state machine to exit the Phy Ready State.
36077 * A value of zero disables the Signal Failure Detector. The value is base
36078 * d on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving
36079 * a nominal time of 500ns based on a 150MHz PMCLK.
36081 #undef SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL
36082 #undef SATA_AHCI_VENDOR_PP4C_SFD_SHIFT
36083 #undef SATA_AHCI_VENDOR_PP4C_SFD_MASK
36084 #define SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL 0x064A0813
36085 #define SATA_AHCI_VENDOR_PP4C_SFD_SHIFT 16
36086 #define SATA_AHCI_VENDOR_PP4C_SFD_MASK 0x00FF0000U
36089 * PTST: Partial to Slumber timer value, specific delay the controller shou
36090 * ld apply while in partial before entering slumber. The value is bases on
36091 * the system clock divided by 128, total delay = (Sys Clock Period) * PTS
36094 #undef SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL
36095 #undef SATA_AHCI_VENDOR_PP4C_PTST_SHIFT
36096 #undef SATA_AHCI_VENDOR_PP4C_PTST_MASK
36097 #define SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL 0x064A0813
36098 #define SATA_AHCI_VENDOR_PP4C_PTST_SHIFT 24
36099 #define SATA_AHCI_VENDOR_PP4C_PTST_MASK 0xFF000000U
36102 * RIT: Retry Interval Timer. The calculated value divided by two, the lowe
36103 * r digit of precision is not needed.
36105 #undef SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL
36106 #undef SATA_AHCI_VENDOR_PP5C_RIT_SHIFT
36107 #undef SATA_AHCI_VENDOR_PP5C_RIT_MASK
36108 #define SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL 0x3FFC96A4
36109 #define SATA_AHCI_VENDOR_PP5C_RIT_SHIFT 0
36110 #define SATA_AHCI_VENDOR_PP5C_RIT_MASK 0x000FFFFFU
36113 * RCT: Rate Change Timer, a value based on the 54.2us for which a SATA dev
36114 * ice will transmit at a fixed rate ALIGNp after OOB has completed, for a
36115 * fast SERDES it is suggested that this value be 54.2us / 4
36117 #undef SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL
36118 #undef SATA_AHCI_VENDOR_PP5C_RCT_SHIFT
36119 #undef SATA_AHCI_VENDOR_PP5C_RCT_MASK
36120 #define SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL 0x3FFC96A4
36121 #define SATA_AHCI_VENDOR_PP5C_RCT_SHIFT 20
36122 #define SATA_AHCI_VENDOR_PP5C_RCT_MASK 0xFFF00000U
36123 #undef CRL_APB_RST_LPD_TOP_OFFSET
36124 #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
36125 #undef CRL_APB_RST_LPD_IOU0_OFFSET
36126 #define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230
36127 #undef CRF_APB_RST_FPD_TOP_OFFSET
36128 #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
36129 #undef CRF_APB_RST_FPD_TOP_OFFSET
36130 #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
36131 #undef DP_DP_TX_PHY_POWER_DOWN_OFFSET
36132 #define DP_DP_TX_PHY_POWER_DOWN_OFFSET 0XFD4A0238
36133 #undef DP_DP_PHY_RESET_OFFSET
36134 #define DP_DP_PHY_RESET_OFFSET 0XFD4A0200
36135 #undef CRF_APB_RST_FPD_TOP_OFFSET
36136 #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
36139 * USB 0 reset for control registers
36141 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL
36142 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
36143 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK
36144 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF
36145 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10
36146 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U
36149 * USB 0 sleep circuit reset
36151 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL
36152 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
36153 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK
36154 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF
36155 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8
36156 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U
36161 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL
36162 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
36163 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK
36164 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF
36165 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6
36166 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U
36171 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL
36172 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
36173 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK
36174 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F
36175 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3
36176 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U
36179 * Sata block level reset
36181 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL
36182 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
36183 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK
36184 #define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE
36185 #define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1
36186 #define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U
36189 * PCIE config reset
36191 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL
36192 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
36193 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK
36194 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE
36195 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19
36196 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U
36199 * PCIE control block level reset
36201 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL
36202 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
36203 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK
36204 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE
36205 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17
36206 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U
36209 * PCIE bridge block level reset (AXI interface)
36211 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL
36212 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
36213 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK
36214 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE
36215 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18
36216 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U
36219 * Two bits per lane. When set to 11, moves the GT to power down mode. When
36220 * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] -
36223 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL
36224 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
36225 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK
36226 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000
36227 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0
36228 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU
36231 * Set to '1' to hold the GT in reset. Clear to release.
36233 #undef DP_DP_PHY_RESET_GT_RESET_DEFVAL
36234 #undef DP_DP_PHY_RESET_GT_RESET_SHIFT
36235 #undef DP_DP_PHY_RESET_GT_RESET_MASK
36236 #define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003
36237 #define DP_DP_PHY_RESET_GT_RESET_SHIFT 1
36238 #define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U
36241 * Display Port block level reset (includes DPDMA)
36243 #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL
36244 #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
36245 #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK
36246 #define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE
36247 #define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16
36248 #define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U
36249 #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET
36250 #define PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET 0XFFD80118
36251 #undef PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET
36252 #define PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET 0XFFD80120
36255 * Power-up Request Interrupt Enable for PL
36257 #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL
36258 #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT
36259 #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK
36260 #define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL 0x00000000
36261 #define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT 23
36262 #define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK 0x00800000U
36265 * Power-up Request Trigger for PL
36267 #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL
36268 #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT
36269 #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK
36270 #define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL 0x00000000
36271 #define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT 23
36272 #define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK 0x00800000U
36275 * Power-up Request Status for PL
36277 #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL
36278 #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT
36279 #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK
36280 #define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL 0x00000000
36281 #define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT 23
36282 #define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK 0x00800000U
36283 #define PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET 0XFFD80110
36284 #undef CRF_APB_RST_FPD_TOP_OFFSET
36285 #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
36286 #undef CRL_APB_RST_LPD_TOP_OFFSET
36287 #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
36288 #undef FPD_SLCR_AFI_FS_OFFSET
36289 #define FPD_SLCR_AFI_FS_OFFSET 0XFD615000
36292 * AF_FM0 block level reset
36294 #undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL
36295 #undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT
36296 #undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK
36297 #define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL 0x000F9FFE
36298 #define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT 7
36299 #define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK 0x00000080U
36302 * AF_FM1 block level reset
36304 #undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL
36305 #undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT
36306 #undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK
36307 #define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL 0x000F9FFE
36308 #define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT 8
36309 #define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK 0x00000100U
36312 * AF_FM2 block level reset
36314 #undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL
36315 #undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT
36316 #undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK
36317 #define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL 0x000F9FFE
36318 #define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT 9
36319 #define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK 0x00000200U
36322 * AF_FM3 block level reset
36324 #undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL
36325 #undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT
36326 #undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK
36327 #define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL 0x000F9FFE
36328 #define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT 10
36329 #define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK 0x00000400U
36332 * AF_FM4 block level reset
36334 #undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL
36335 #undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT
36336 #undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK
36337 #define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL 0x000F9FFE
36338 #define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT 11
36339 #define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK 0x00000800U
36342 * AF_FM5 block level reset
36344 #undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL
36345 #undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT
36346 #undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK
36347 #define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL 0x000F9FFE
36348 #define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT 12
36349 #define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK 0x00001000U
36354 #undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL
36355 #undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT
36356 #undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK
36357 #define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL 0x00188FDF
36358 #define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT 19
36359 #define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK 0x00080000U
36362 * Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit
36363 * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data
36364 * width 11: reserved
36366 #undef FPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL
36367 #undef FPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT
36368 #undef FPD_SLCR_AFI_FS_DW_SS0_SEL_MASK
36369 #define FPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL 0x00000A00
36370 #define FPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT 8
36371 #define FPD_SLCR_AFI_FS_DW_SS0_SEL_MASK 0x00000300U
36374 * Select the 32/64/128-bit data width selection for the Slave 1 00: 32-bit
36375 * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data
36376 * width 11: reserved
36378 #undef FPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL
36379 #undef FPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT
36380 #undef FPD_SLCR_AFI_FS_DW_SS1_SEL_MASK
36381 #define FPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL 0x00000A00
36382 #define FPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT 10
36383 #define FPD_SLCR_AFI_FS_DW_SS1_SEL_MASK 0x00000C00U
36384 #undef GPIO_MASK_DATA_5_MSW_OFFSET
36385 #define GPIO_MASK_DATA_5_MSW_OFFSET 0XFF0A002C
36386 #undef GPIO_DIRM_5_OFFSET
36387 #define GPIO_DIRM_5_OFFSET 0XFF0A0344
36388 #undef GPIO_OEN_5_OFFSET
36389 #define GPIO_OEN_5_OFFSET 0XFF0A0348
36390 #undef GPIO_DATA_5_OFFSET
36391 #define GPIO_DATA_5_OFFSET 0XFF0A0054
36392 #undef GPIO_DATA_5_OFFSET
36393 #define GPIO_DATA_5_OFFSET 0XFF0A0054
36394 #undef GPIO_DATA_5_OFFSET
36395 #define GPIO_DATA_5_OFFSET 0XFF0A0054
36398 * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
36400 #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL
36401 #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT
36402 #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK
36403 #define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL 0x00000000
36404 #define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT 16
36405 #define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK 0xFFFF0000U
36408 * Operation is the same as DIRM_0[DIRECTION_0]
36410 #undef GPIO_DIRM_5_DIRECTION_5_DEFVAL
36411 #undef GPIO_DIRM_5_DIRECTION_5_SHIFT
36412 #undef GPIO_DIRM_5_DIRECTION_5_MASK
36413 #define GPIO_DIRM_5_DIRECTION_5_DEFVAL
36414 #define GPIO_DIRM_5_DIRECTION_5_SHIFT 0
36415 #define GPIO_DIRM_5_DIRECTION_5_MASK 0xFFFFFFFFU
36418 * Operation is the same as OEN_0[OP_ENABLE_0]
36420 #undef GPIO_OEN_5_OP_ENABLE_5_DEFVAL
36421 #undef GPIO_OEN_5_OP_ENABLE_5_SHIFT
36422 #undef GPIO_OEN_5_OP_ENABLE_5_MASK
36423 #define GPIO_OEN_5_OP_ENABLE_5_DEFVAL
36424 #define GPIO_OEN_5_OP_ENABLE_5_SHIFT 0
36425 #define GPIO_OEN_5_OP_ENABLE_5_MASK 0xFFFFFFFFU
36430 #undef GPIO_DATA_5_DATA_5_DEFVAL
36431 #undef GPIO_DATA_5_DATA_5_SHIFT
36432 #undef GPIO_DATA_5_DATA_5_MASK
36433 #define GPIO_DATA_5_DATA_5_DEFVAL
36434 #define GPIO_DATA_5_DATA_5_SHIFT 0
36435 #define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU
36440 #undef GPIO_DATA_5_DATA_5_DEFVAL
36441 #undef GPIO_DATA_5_DATA_5_SHIFT
36442 #undef GPIO_DATA_5_DATA_5_MASK
36443 #define GPIO_DATA_5_DATA_5_DEFVAL
36444 #define GPIO_DATA_5_DATA_5_SHIFT 0
36445 #define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU
36450 #undef GPIO_DATA_5_DATA_5_DEFVAL
36451 #undef GPIO_DATA_5_DATA_5_SHIFT
36452 #undef GPIO_DATA_5_DATA_5_MASK
36453 #define GPIO_DATA_5_DATA_5_DEFVAL
36454 #define GPIO_DATA_5_DATA_5_SHIFT 0
36455 #define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU
36460 unsigned long psu_ps_pl_isolation_removal_data();
36461 unsigned long psu_ps_pl_reset_config_data();
36462 int psu_protection();
36463 int psu_fpd_protection();
36464 int psu_ocm_protection();
36465 int psu_ddr_protection();
36466 int psu_lpd_protection();
36467 int psu_protection_lock();
36468 unsigned long psu_ddr_qos_init_data(void);
36469 unsigned long psu_apply_master_tz();