1 /******************************************************************************
3 * Copyright (C) 2015 Xilinx, Inc. All rights reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * Use of the Software is limited solely to applications:
16 * (a) running on a Xilinx device, or
17 * (b) that interact with a Xilinx device through a bus or interconnect.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
22 * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27 * Except as contained in this notice, the name of the Xilinx shall not be used
28 * in advertising or otherwise to promote the sale, use or other dealings in
29 * this Software without prior written authorization from Xilinx.
31 ******************************************************************************/
32 /****************************************************************************/
37 * This file is automatically generated
39 *****************************************************************************/
42 #undef CRL_APB_RPLL_CFG_OFFSET
43 #define CRL_APB_RPLL_CFG_OFFSET 0XFF5E0034
44 #undef CRL_APB_RPLL_CTRL_OFFSET
45 #define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030
46 #undef CRL_APB_RPLL_CTRL_OFFSET
47 #define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030
48 #undef CRL_APB_RPLL_CTRL_OFFSET
49 #define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030
50 #undef CRL_APB_RPLL_CTRL_OFFSET
51 #define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030
52 #undef CRL_APB_RPLL_CTRL_OFFSET
53 #define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030
54 #undef CRL_APB_RPLL_TO_FPD_CTRL_OFFSET
55 #define CRL_APB_RPLL_TO_FPD_CTRL_OFFSET 0XFF5E0048
56 #undef CRL_APB_RPLL_FRAC_CFG_OFFSET
57 #define CRL_APB_RPLL_FRAC_CFG_OFFSET 0XFF5E0038
58 #undef CRL_APB_IOPLL_CFG_OFFSET
59 #define CRL_APB_IOPLL_CFG_OFFSET 0XFF5E0024
60 #undef CRL_APB_IOPLL_CTRL_OFFSET
61 #define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020
62 #undef CRL_APB_IOPLL_CTRL_OFFSET
63 #define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020
64 #undef CRL_APB_IOPLL_CTRL_OFFSET
65 #define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020
66 #undef CRL_APB_IOPLL_CTRL_OFFSET
67 #define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020
68 #undef CRL_APB_IOPLL_CTRL_OFFSET
69 #define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020
70 #undef CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET
71 #define CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET 0XFF5E0044
72 #undef CRL_APB_IOPLL_FRAC_CFG_OFFSET
73 #define CRL_APB_IOPLL_FRAC_CFG_OFFSET 0XFF5E0028
74 #undef CRF_APB_APLL_CFG_OFFSET
75 #define CRF_APB_APLL_CFG_OFFSET 0XFD1A0024
76 #undef CRF_APB_APLL_CTRL_OFFSET
77 #define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020
78 #undef CRF_APB_APLL_CTRL_OFFSET
79 #define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020
80 #undef CRF_APB_APLL_CTRL_OFFSET
81 #define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020
82 #undef CRF_APB_APLL_CTRL_OFFSET
83 #define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020
84 #undef CRF_APB_APLL_CTRL_OFFSET
85 #define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020
86 #undef CRF_APB_APLL_TO_LPD_CTRL_OFFSET
87 #define CRF_APB_APLL_TO_LPD_CTRL_OFFSET 0XFD1A0048
88 #undef CRF_APB_APLL_FRAC_CFG_OFFSET
89 #define CRF_APB_APLL_FRAC_CFG_OFFSET 0XFD1A0028
90 #undef CRF_APB_DPLL_CFG_OFFSET
91 #define CRF_APB_DPLL_CFG_OFFSET 0XFD1A0030
92 #undef CRF_APB_DPLL_CTRL_OFFSET
93 #define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C
94 #undef CRF_APB_DPLL_CTRL_OFFSET
95 #define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C
96 #undef CRF_APB_DPLL_CTRL_OFFSET
97 #define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C
98 #undef CRF_APB_DPLL_CTRL_OFFSET
99 #define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C
100 #undef CRF_APB_DPLL_CTRL_OFFSET
101 #define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C
102 #undef CRF_APB_DPLL_TO_LPD_CTRL_OFFSET
103 #define CRF_APB_DPLL_TO_LPD_CTRL_OFFSET 0XFD1A004C
104 #undef CRF_APB_DPLL_FRAC_CFG_OFFSET
105 #define CRF_APB_DPLL_FRAC_CFG_OFFSET 0XFD1A0034
106 #undef CRF_APB_VPLL_CFG_OFFSET
107 #define CRF_APB_VPLL_CFG_OFFSET 0XFD1A003C
108 #undef CRF_APB_VPLL_CTRL_OFFSET
109 #define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038
110 #undef CRF_APB_VPLL_CTRL_OFFSET
111 #define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038
112 #undef CRF_APB_VPLL_CTRL_OFFSET
113 #define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038
114 #undef CRF_APB_VPLL_CTRL_OFFSET
115 #define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038
116 #undef CRF_APB_VPLL_CTRL_OFFSET
117 #define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038
118 #undef CRF_APB_VPLL_TO_LPD_CTRL_OFFSET
119 #define CRF_APB_VPLL_TO_LPD_CTRL_OFFSET 0XFD1A0050
120 #undef CRF_APB_VPLL_FRAC_CFG_OFFSET
121 #define CRF_APB_VPLL_FRAC_CFG_OFFSET 0XFD1A0040
123 /*PLL loop filter resistor control*/
124 #undef CRL_APB_RPLL_CFG_RES_DEFVAL
125 #undef CRL_APB_RPLL_CFG_RES_SHIFT
126 #undef CRL_APB_RPLL_CFG_RES_MASK
127 #define CRL_APB_RPLL_CFG_RES_DEFVAL 0x00000000
128 #define CRL_APB_RPLL_CFG_RES_SHIFT 0
129 #define CRL_APB_RPLL_CFG_RES_MASK 0x0000000FU
131 /*PLL charge pump control*/
132 #undef CRL_APB_RPLL_CFG_CP_DEFVAL
133 #undef CRL_APB_RPLL_CFG_CP_SHIFT
134 #undef CRL_APB_RPLL_CFG_CP_MASK
135 #define CRL_APB_RPLL_CFG_CP_DEFVAL 0x00000000
136 #define CRL_APB_RPLL_CFG_CP_SHIFT 5
137 #define CRL_APB_RPLL_CFG_CP_MASK 0x000001E0U
139 /*PLL loop filter high frequency capacitor control*/
140 #undef CRL_APB_RPLL_CFG_LFHF_DEFVAL
141 #undef CRL_APB_RPLL_CFG_LFHF_SHIFT
142 #undef CRL_APB_RPLL_CFG_LFHF_MASK
143 #define CRL_APB_RPLL_CFG_LFHF_DEFVAL 0x00000000
144 #define CRL_APB_RPLL_CFG_LFHF_SHIFT 10
145 #define CRL_APB_RPLL_CFG_LFHF_MASK 0x00000C00U
147 /*Lock circuit counter setting*/
148 #undef CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL
149 #undef CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT
150 #undef CRL_APB_RPLL_CFG_LOCK_CNT_MASK
151 #define CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL 0x00000000
152 #define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 13
153 #define CRL_APB_RPLL_CFG_LOCK_CNT_MASK 0x007FE000U
155 /*Lock circuit configuration settings for lock windowsize*/
156 #undef CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL
157 #undef CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT
158 #undef CRL_APB_RPLL_CFG_LOCK_DLY_MASK
159 #define CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL 0x00000000
160 #define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 25
161 #define CRL_APB_RPLL_CFG_LOCK_DLY_MASK 0xFE000000U
163 /*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
164 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
165 #undef CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL
166 #undef CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT
167 #undef CRL_APB_RPLL_CTRL_PRE_SRC_MASK
168 #define CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09
169 #define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 20
170 #define CRL_APB_RPLL_CTRL_PRE_SRC_MASK 0x00700000U
172 /*The integer portion of the feedback divider to the PLL*/
173 #undef CRL_APB_RPLL_CTRL_FBDIV_DEFVAL
174 #undef CRL_APB_RPLL_CTRL_FBDIV_SHIFT
175 #undef CRL_APB_RPLL_CTRL_FBDIV_MASK
176 #define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 0x00012C09
177 #define CRL_APB_RPLL_CTRL_FBDIV_SHIFT 8
178 #define CRL_APB_RPLL_CTRL_FBDIV_MASK 0x00007F00U
180 /*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
181 #undef CRL_APB_RPLL_CTRL_DIV2_DEFVAL
182 #undef CRL_APB_RPLL_CTRL_DIV2_SHIFT
183 #undef CRL_APB_RPLL_CTRL_DIV2_MASK
184 #define CRL_APB_RPLL_CTRL_DIV2_DEFVAL 0x00012C09
185 #define CRL_APB_RPLL_CTRL_DIV2_SHIFT 16
186 #define CRL_APB_RPLL_CTRL_DIV2_MASK 0x00010000U
188 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
189 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
190 #undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL
191 #undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT
192 #undef CRL_APB_RPLL_CTRL_BYPASS_MASK
193 #define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09
194 #define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3
195 #define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U
197 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
198 #undef CRL_APB_RPLL_CTRL_RESET_DEFVAL
199 #undef CRL_APB_RPLL_CTRL_RESET_SHIFT
200 #undef CRL_APB_RPLL_CTRL_RESET_MASK
201 #define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09
202 #define CRL_APB_RPLL_CTRL_RESET_SHIFT 0
203 #define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U
205 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
206 #undef CRL_APB_RPLL_CTRL_RESET_DEFVAL
207 #undef CRL_APB_RPLL_CTRL_RESET_SHIFT
208 #undef CRL_APB_RPLL_CTRL_RESET_MASK
209 #define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09
210 #define CRL_APB_RPLL_CTRL_RESET_SHIFT 0
211 #define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U
214 #undef CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL
215 #undef CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT
216 #undef CRL_APB_PLL_STATUS_RPLL_LOCK_MASK
217 #define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 0x00000018
218 #define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 1
219 #define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 0x00000002U
220 #define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040
222 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
223 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
224 #undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL
225 #undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT
226 #undef CRL_APB_RPLL_CTRL_BYPASS_MASK
227 #define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09
228 #define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3
229 #define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U
231 /*Divisor value for this clock.*/
232 #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL
233 #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
234 #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK
235 #define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400
236 #define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8
237 #define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U
239 /*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
240 mode and uses DATA of this register for the fractional portion of the feedback divider.*/
241 #undef CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL
242 #undef CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT
243 #undef CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK
244 #define CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000
245 #define CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT 31
246 #define CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK 0x80000000U
248 /*Fractional value for the Feedback value.*/
249 #undef CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL
250 #undef CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT
251 #undef CRL_APB_RPLL_FRAC_CFG_DATA_MASK
252 #define CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL 0x00000000
253 #define CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT 0
254 #define CRL_APB_RPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU
256 /*PLL loop filter resistor control*/
257 #undef CRL_APB_IOPLL_CFG_RES_DEFVAL
258 #undef CRL_APB_IOPLL_CFG_RES_SHIFT
259 #undef CRL_APB_IOPLL_CFG_RES_MASK
260 #define CRL_APB_IOPLL_CFG_RES_DEFVAL 0x00000000
261 #define CRL_APB_IOPLL_CFG_RES_SHIFT 0
262 #define CRL_APB_IOPLL_CFG_RES_MASK 0x0000000FU
264 /*PLL charge pump control*/
265 #undef CRL_APB_IOPLL_CFG_CP_DEFVAL
266 #undef CRL_APB_IOPLL_CFG_CP_SHIFT
267 #undef CRL_APB_IOPLL_CFG_CP_MASK
268 #define CRL_APB_IOPLL_CFG_CP_DEFVAL 0x00000000
269 #define CRL_APB_IOPLL_CFG_CP_SHIFT 5
270 #define CRL_APB_IOPLL_CFG_CP_MASK 0x000001E0U
272 /*PLL loop filter high frequency capacitor control*/
273 #undef CRL_APB_IOPLL_CFG_LFHF_DEFVAL
274 #undef CRL_APB_IOPLL_CFG_LFHF_SHIFT
275 #undef CRL_APB_IOPLL_CFG_LFHF_MASK
276 #define CRL_APB_IOPLL_CFG_LFHF_DEFVAL 0x00000000
277 #define CRL_APB_IOPLL_CFG_LFHF_SHIFT 10
278 #define CRL_APB_IOPLL_CFG_LFHF_MASK 0x00000C00U
280 /*Lock circuit counter setting*/
281 #undef CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL
282 #undef CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT
283 #undef CRL_APB_IOPLL_CFG_LOCK_CNT_MASK
284 #define CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL 0x00000000
285 #define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 13
286 #define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK 0x007FE000U
288 /*Lock circuit configuration settings for lock windowsize*/
289 #undef CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL
290 #undef CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT
291 #undef CRL_APB_IOPLL_CFG_LOCK_DLY_MASK
292 #define CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL 0x00000000
293 #define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 25
294 #define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK 0xFE000000U
296 /*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
297 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
298 #undef CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL
299 #undef CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT
300 #undef CRL_APB_IOPLL_CTRL_PRE_SRC_MASK
301 #define CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09
302 #define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 20
303 #define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK 0x00700000U
305 /*The integer portion of the feedback divider to the PLL*/
306 #undef CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL
307 #undef CRL_APB_IOPLL_CTRL_FBDIV_SHIFT
308 #undef CRL_APB_IOPLL_CTRL_FBDIV_MASK
309 #define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 0x00012C09
310 #define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 8
311 #define CRL_APB_IOPLL_CTRL_FBDIV_MASK 0x00007F00U
313 /*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
314 #undef CRL_APB_IOPLL_CTRL_DIV2_DEFVAL
315 #undef CRL_APB_IOPLL_CTRL_DIV2_SHIFT
316 #undef CRL_APB_IOPLL_CTRL_DIV2_MASK
317 #define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 0x00012C09
318 #define CRL_APB_IOPLL_CTRL_DIV2_SHIFT 16
319 #define CRL_APB_IOPLL_CTRL_DIV2_MASK 0x00010000U
321 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
322 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
323 #undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL
324 #undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
325 #undef CRL_APB_IOPLL_CTRL_BYPASS_MASK
326 #define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09
327 #define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3
328 #define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U
330 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
331 #undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL
332 #undef CRL_APB_IOPLL_CTRL_RESET_SHIFT
333 #undef CRL_APB_IOPLL_CTRL_RESET_MASK
334 #define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09
335 #define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0
336 #define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U
338 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
339 #undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL
340 #undef CRL_APB_IOPLL_CTRL_RESET_SHIFT
341 #undef CRL_APB_IOPLL_CTRL_RESET_MASK
342 #define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09
343 #define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0
344 #define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U
347 #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL
348 #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT
349 #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK
350 #define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 0x00000018
351 #define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 0
352 #define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 0x00000001U
353 #define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040
355 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
356 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
357 #undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL
358 #undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
359 #undef CRL_APB_IOPLL_CTRL_BYPASS_MASK
360 #define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09
361 #define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3
362 #define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U
364 /*Divisor value for this clock.*/
365 #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL
366 #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
367 #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK
368 #define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400
369 #define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8
370 #define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U
372 /*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
373 mode and uses DATA of this register for the fractional portion of the feedback divider.*/
374 #undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL
375 #undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT
376 #undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK
377 #define CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000
378 #define CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT 31
379 #define CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK 0x80000000U
381 /*Fractional value for the Feedback value.*/
382 #undef CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL
383 #undef CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT
384 #undef CRL_APB_IOPLL_FRAC_CFG_DATA_MASK
385 #define CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL 0x00000000
386 #define CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT 0
387 #define CRL_APB_IOPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU
389 /*PLL loop filter resistor control*/
390 #undef CRF_APB_APLL_CFG_RES_DEFVAL
391 #undef CRF_APB_APLL_CFG_RES_SHIFT
392 #undef CRF_APB_APLL_CFG_RES_MASK
393 #define CRF_APB_APLL_CFG_RES_DEFVAL 0x00000000
394 #define CRF_APB_APLL_CFG_RES_SHIFT 0
395 #define CRF_APB_APLL_CFG_RES_MASK 0x0000000FU
397 /*PLL charge pump control*/
398 #undef CRF_APB_APLL_CFG_CP_DEFVAL
399 #undef CRF_APB_APLL_CFG_CP_SHIFT
400 #undef CRF_APB_APLL_CFG_CP_MASK
401 #define CRF_APB_APLL_CFG_CP_DEFVAL 0x00000000
402 #define CRF_APB_APLL_CFG_CP_SHIFT 5
403 #define CRF_APB_APLL_CFG_CP_MASK 0x000001E0U
405 /*PLL loop filter high frequency capacitor control*/
406 #undef CRF_APB_APLL_CFG_LFHF_DEFVAL
407 #undef CRF_APB_APLL_CFG_LFHF_SHIFT
408 #undef CRF_APB_APLL_CFG_LFHF_MASK
409 #define CRF_APB_APLL_CFG_LFHF_DEFVAL 0x00000000
410 #define CRF_APB_APLL_CFG_LFHF_SHIFT 10
411 #define CRF_APB_APLL_CFG_LFHF_MASK 0x00000C00U
413 /*Lock circuit counter setting*/
414 #undef CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL
415 #undef CRF_APB_APLL_CFG_LOCK_CNT_SHIFT
416 #undef CRF_APB_APLL_CFG_LOCK_CNT_MASK
417 #define CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL 0x00000000
418 #define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 13
419 #define CRF_APB_APLL_CFG_LOCK_CNT_MASK 0x007FE000U
421 /*Lock circuit configuration settings for lock windowsize*/
422 #undef CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL
423 #undef CRF_APB_APLL_CFG_LOCK_DLY_SHIFT
424 #undef CRF_APB_APLL_CFG_LOCK_DLY_MASK
425 #define CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL 0x00000000
426 #define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 25
427 #define CRF_APB_APLL_CFG_LOCK_DLY_MASK 0xFE000000U
429 /*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
430 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
431 #undef CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL
432 #undef CRF_APB_APLL_CTRL_PRE_SRC_SHIFT
433 #undef CRF_APB_APLL_CTRL_PRE_SRC_MASK
434 #define CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL 0x00012C09
435 #define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 20
436 #define CRF_APB_APLL_CTRL_PRE_SRC_MASK 0x00700000U
438 /*The integer portion of the feedback divider to the PLL*/
439 #undef CRF_APB_APLL_CTRL_FBDIV_DEFVAL
440 #undef CRF_APB_APLL_CTRL_FBDIV_SHIFT
441 #undef CRF_APB_APLL_CTRL_FBDIV_MASK
442 #define CRF_APB_APLL_CTRL_FBDIV_DEFVAL 0x00012C09
443 #define CRF_APB_APLL_CTRL_FBDIV_SHIFT 8
444 #define CRF_APB_APLL_CTRL_FBDIV_MASK 0x00007F00U
446 /*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
447 #undef CRF_APB_APLL_CTRL_DIV2_DEFVAL
448 #undef CRF_APB_APLL_CTRL_DIV2_SHIFT
449 #undef CRF_APB_APLL_CTRL_DIV2_MASK
450 #define CRF_APB_APLL_CTRL_DIV2_DEFVAL 0x00012C09
451 #define CRF_APB_APLL_CTRL_DIV2_SHIFT 16
452 #define CRF_APB_APLL_CTRL_DIV2_MASK 0x00010000U
454 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
455 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
456 #undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL
457 #undef CRF_APB_APLL_CTRL_BYPASS_SHIFT
458 #undef CRF_APB_APLL_CTRL_BYPASS_MASK
459 #define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09
460 #define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3
461 #define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U
463 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
464 #undef CRF_APB_APLL_CTRL_RESET_DEFVAL
465 #undef CRF_APB_APLL_CTRL_RESET_SHIFT
466 #undef CRF_APB_APLL_CTRL_RESET_MASK
467 #define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09
468 #define CRF_APB_APLL_CTRL_RESET_SHIFT 0
469 #define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U
471 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
472 #undef CRF_APB_APLL_CTRL_RESET_DEFVAL
473 #undef CRF_APB_APLL_CTRL_RESET_SHIFT
474 #undef CRF_APB_APLL_CTRL_RESET_MASK
475 #define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09
476 #define CRF_APB_APLL_CTRL_RESET_SHIFT 0
477 #define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U
480 #undef CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL
481 #undef CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT
482 #undef CRF_APB_PLL_STATUS_APLL_LOCK_MASK
483 #define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 0x00000038
484 #define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 0
485 #define CRF_APB_PLL_STATUS_APLL_LOCK_MASK 0x00000001U
486 #define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044
488 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
489 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
490 #undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL
491 #undef CRF_APB_APLL_CTRL_BYPASS_SHIFT
492 #undef CRF_APB_APLL_CTRL_BYPASS_MASK
493 #define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09
494 #define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3
495 #define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U
497 /*Divisor value for this clock.*/
498 #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL
499 #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT
500 #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK
501 #define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400
502 #define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8
503 #define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U
505 /*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
506 mode and uses DATA of this register for the fractional portion of the feedback divider.*/
507 #undef CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL
508 #undef CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT
509 #undef CRF_APB_APLL_FRAC_CFG_ENABLED_MASK
510 #define CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000
511 #define CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT 31
512 #define CRF_APB_APLL_FRAC_CFG_ENABLED_MASK 0x80000000U
514 /*Fractional value for the Feedback value.*/
515 #undef CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL
516 #undef CRF_APB_APLL_FRAC_CFG_DATA_SHIFT
517 #undef CRF_APB_APLL_FRAC_CFG_DATA_MASK
518 #define CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL 0x00000000
519 #define CRF_APB_APLL_FRAC_CFG_DATA_SHIFT 0
520 #define CRF_APB_APLL_FRAC_CFG_DATA_MASK 0x0000FFFFU
522 /*PLL loop filter resistor control*/
523 #undef CRF_APB_DPLL_CFG_RES_DEFVAL
524 #undef CRF_APB_DPLL_CFG_RES_SHIFT
525 #undef CRF_APB_DPLL_CFG_RES_MASK
526 #define CRF_APB_DPLL_CFG_RES_DEFVAL 0x00000000
527 #define CRF_APB_DPLL_CFG_RES_SHIFT 0
528 #define CRF_APB_DPLL_CFG_RES_MASK 0x0000000FU
530 /*PLL charge pump control*/
531 #undef CRF_APB_DPLL_CFG_CP_DEFVAL
532 #undef CRF_APB_DPLL_CFG_CP_SHIFT
533 #undef CRF_APB_DPLL_CFG_CP_MASK
534 #define CRF_APB_DPLL_CFG_CP_DEFVAL 0x00000000
535 #define CRF_APB_DPLL_CFG_CP_SHIFT 5
536 #define CRF_APB_DPLL_CFG_CP_MASK 0x000001E0U
538 /*PLL loop filter high frequency capacitor control*/
539 #undef CRF_APB_DPLL_CFG_LFHF_DEFVAL
540 #undef CRF_APB_DPLL_CFG_LFHF_SHIFT
541 #undef CRF_APB_DPLL_CFG_LFHF_MASK
542 #define CRF_APB_DPLL_CFG_LFHF_DEFVAL 0x00000000
543 #define CRF_APB_DPLL_CFG_LFHF_SHIFT 10
544 #define CRF_APB_DPLL_CFG_LFHF_MASK 0x00000C00U
546 /*Lock circuit counter setting*/
547 #undef CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL
548 #undef CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT
549 #undef CRF_APB_DPLL_CFG_LOCK_CNT_MASK
550 #define CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL 0x00000000
551 #define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13
552 #define CRF_APB_DPLL_CFG_LOCK_CNT_MASK 0x007FE000U
554 /*Lock circuit configuration settings for lock windowsize*/
555 #undef CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL
556 #undef CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT
557 #undef CRF_APB_DPLL_CFG_LOCK_DLY_MASK
558 #define CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL 0x00000000
559 #define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25
560 #define CRF_APB_DPLL_CFG_LOCK_DLY_MASK 0xFE000000U
562 /*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
563 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
564 #undef CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL
565 #undef CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT
566 #undef CRF_APB_DPLL_CTRL_PRE_SRC_MASK
567 #define CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL 0x00002C09
568 #define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 20
569 #define CRF_APB_DPLL_CTRL_PRE_SRC_MASK 0x00700000U
571 /*The integer portion of the feedback divider to the PLL*/
572 #undef CRF_APB_DPLL_CTRL_FBDIV_DEFVAL
573 #undef CRF_APB_DPLL_CTRL_FBDIV_SHIFT
574 #undef CRF_APB_DPLL_CTRL_FBDIV_MASK
575 #define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 0x00002C09
576 #define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8
577 #define CRF_APB_DPLL_CTRL_FBDIV_MASK 0x00007F00U
579 /*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
580 #undef CRF_APB_DPLL_CTRL_DIV2_DEFVAL
581 #undef CRF_APB_DPLL_CTRL_DIV2_SHIFT
582 #undef CRF_APB_DPLL_CTRL_DIV2_MASK
583 #define CRF_APB_DPLL_CTRL_DIV2_DEFVAL 0x00002C09
584 #define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16
585 #define CRF_APB_DPLL_CTRL_DIV2_MASK 0x00010000U
587 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
588 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
589 #undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL
590 #undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT
591 #undef CRF_APB_DPLL_CTRL_BYPASS_MASK
592 #define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09
593 #define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3
594 #define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U
596 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
597 #undef CRF_APB_DPLL_CTRL_RESET_DEFVAL
598 #undef CRF_APB_DPLL_CTRL_RESET_SHIFT
599 #undef CRF_APB_DPLL_CTRL_RESET_MASK
600 #define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09
601 #define CRF_APB_DPLL_CTRL_RESET_SHIFT 0
602 #define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U
604 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
605 #undef CRF_APB_DPLL_CTRL_RESET_DEFVAL
606 #undef CRF_APB_DPLL_CTRL_RESET_SHIFT
607 #undef CRF_APB_DPLL_CTRL_RESET_MASK
608 #define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09
609 #define CRF_APB_DPLL_CTRL_RESET_SHIFT 0
610 #define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U
613 #undef CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL
614 #undef CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT
615 #undef CRF_APB_PLL_STATUS_DPLL_LOCK_MASK
616 #define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 0x00000038
617 #define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 1
618 #define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 0x00000002U
619 #define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044
621 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
622 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
623 #undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL
624 #undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT
625 #undef CRF_APB_DPLL_CTRL_BYPASS_MASK
626 #define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09
627 #define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3
628 #define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U
630 /*Divisor value for this clock.*/
631 #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL
632 #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
633 #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK
634 #define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400
635 #define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8
636 #define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U
638 /*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
639 mode and uses DATA of this register for the fractional portion of the feedback divider.*/
640 #undef CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL
641 #undef CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT
642 #undef CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK
643 #define CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000
644 #define CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT 31
645 #define CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK 0x80000000U
647 /*Fractional value for the Feedback value.*/
648 #undef CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL
649 #undef CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT
650 #undef CRF_APB_DPLL_FRAC_CFG_DATA_MASK
651 #define CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL 0x00000000
652 #define CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT 0
653 #define CRF_APB_DPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU
655 /*PLL loop filter resistor control*/
656 #undef CRF_APB_VPLL_CFG_RES_DEFVAL
657 #undef CRF_APB_VPLL_CFG_RES_SHIFT
658 #undef CRF_APB_VPLL_CFG_RES_MASK
659 #define CRF_APB_VPLL_CFG_RES_DEFVAL 0x00000000
660 #define CRF_APB_VPLL_CFG_RES_SHIFT 0
661 #define CRF_APB_VPLL_CFG_RES_MASK 0x0000000FU
663 /*PLL charge pump control*/
664 #undef CRF_APB_VPLL_CFG_CP_DEFVAL
665 #undef CRF_APB_VPLL_CFG_CP_SHIFT
666 #undef CRF_APB_VPLL_CFG_CP_MASK
667 #define CRF_APB_VPLL_CFG_CP_DEFVAL 0x00000000
668 #define CRF_APB_VPLL_CFG_CP_SHIFT 5
669 #define CRF_APB_VPLL_CFG_CP_MASK 0x000001E0U
671 /*PLL loop filter high frequency capacitor control*/
672 #undef CRF_APB_VPLL_CFG_LFHF_DEFVAL
673 #undef CRF_APB_VPLL_CFG_LFHF_SHIFT
674 #undef CRF_APB_VPLL_CFG_LFHF_MASK
675 #define CRF_APB_VPLL_CFG_LFHF_DEFVAL 0x00000000
676 #define CRF_APB_VPLL_CFG_LFHF_SHIFT 10
677 #define CRF_APB_VPLL_CFG_LFHF_MASK 0x00000C00U
679 /*Lock circuit counter setting*/
680 #undef CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL
681 #undef CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT
682 #undef CRF_APB_VPLL_CFG_LOCK_CNT_MASK
683 #define CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL 0x00000000
684 #define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 13
685 #define CRF_APB_VPLL_CFG_LOCK_CNT_MASK 0x007FE000U
687 /*Lock circuit configuration settings for lock windowsize*/
688 #undef CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL
689 #undef CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT
690 #undef CRF_APB_VPLL_CFG_LOCK_DLY_MASK
691 #define CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL 0x00000000
692 #define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 25
693 #define CRF_APB_VPLL_CFG_LOCK_DLY_MASK 0xFE000000U
695 /*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
696 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
697 #undef CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL
698 #undef CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT
699 #undef CRF_APB_VPLL_CTRL_PRE_SRC_MASK
700 #define CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL 0x00012809
701 #define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 20
702 #define CRF_APB_VPLL_CTRL_PRE_SRC_MASK 0x00700000U
704 /*The integer portion of the feedback divider to the PLL*/
705 #undef CRF_APB_VPLL_CTRL_FBDIV_DEFVAL
706 #undef CRF_APB_VPLL_CTRL_FBDIV_SHIFT
707 #undef CRF_APB_VPLL_CTRL_FBDIV_MASK
708 #define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 0x00012809
709 #define CRF_APB_VPLL_CTRL_FBDIV_SHIFT 8
710 #define CRF_APB_VPLL_CTRL_FBDIV_MASK 0x00007F00U
712 /*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
713 #undef CRF_APB_VPLL_CTRL_DIV2_DEFVAL
714 #undef CRF_APB_VPLL_CTRL_DIV2_SHIFT
715 #undef CRF_APB_VPLL_CTRL_DIV2_MASK
716 #define CRF_APB_VPLL_CTRL_DIV2_DEFVAL 0x00012809
717 #define CRF_APB_VPLL_CTRL_DIV2_SHIFT 16
718 #define CRF_APB_VPLL_CTRL_DIV2_MASK 0x00010000U
720 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
721 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
722 #undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL
723 #undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT
724 #undef CRF_APB_VPLL_CTRL_BYPASS_MASK
725 #define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809
726 #define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3
727 #define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U
729 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
730 #undef CRF_APB_VPLL_CTRL_RESET_DEFVAL
731 #undef CRF_APB_VPLL_CTRL_RESET_SHIFT
732 #undef CRF_APB_VPLL_CTRL_RESET_MASK
733 #define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809
734 #define CRF_APB_VPLL_CTRL_RESET_SHIFT 0
735 #define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U
737 /*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
738 #undef CRF_APB_VPLL_CTRL_RESET_DEFVAL
739 #undef CRF_APB_VPLL_CTRL_RESET_SHIFT
740 #undef CRF_APB_VPLL_CTRL_RESET_MASK
741 #define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809
742 #define CRF_APB_VPLL_CTRL_RESET_SHIFT 0
743 #define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U
746 #undef CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL
747 #undef CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT
748 #undef CRF_APB_PLL_STATUS_VPLL_LOCK_MASK
749 #define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 0x00000038
750 #define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 2
751 #define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 0x00000004U
752 #define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044
754 /*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
755 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
756 #undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL
757 #undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT
758 #undef CRF_APB_VPLL_CTRL_BYPASS_MASK
759 #define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809
760 #define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3
761 #define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U
763 /*Divisor value for this clock.*/
764 #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL
765 #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
766 #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK
767 #define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400
768 #define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8
769 #define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U
771 /*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
772 mode and uses DATA of this register for the fractional portion of the feedback divider.*/
773 #undef CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL
774 #undef CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT
775 #undef CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK
776 #define CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000
777 #define CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT 31
778 #define CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK 0x80000000U
780 /*Fractional value for the Feedback value.*/
781 #undef CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL
782 #undef CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT
783 #undef CRF_APB_VPLL_FRAC_CFG_DATA_MASK
784 #define CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL 0x00000000
785 #define CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT 0
786 #define CRF_APB_VPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU
787 #undef CRL_APB_GEM3_REF_CTRL_OFFSET
788 #define CRL_APB_GEM3_REF_CTRL_OFFSET 0XFF5E005C
789 #undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET
790 #define CRL_APB_USB0_BUS_REF_CTRL_OFFSET 0XFF5E0060
791 #undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET
792 #define CRL_APB_USB3_DUAL_REF_CTRL_OFFSET 0XFF5E004C
793 #undef CRL_APB_QSPI_REF_CTRL_OFFSET
794 #define CRL_APB_QSPI_REF_CTRL_OFFSET 0XFF5E0068
795 #undef CRL_APB_SDIO1_REF_CTRL_OFFSET
796 #define CRL_APB_SDIO1_REF_CTRL_OFFSET 0XFF5E0070
797 #undef IOU_SLCR_SDIO_CLK_CTRL_OFFSET
798 #define IOU_SLCR_SDIO_CLK_CTRL_OFFSET 0XFF18030C
799 #undef CRL_APB_UART0_REF_CTRL_OFFSET
800 #define CRL_APB_UART0_REF_CTRL_OFFSET 0XFF5E0074
801 #undef CRL_APB_UART1_REF_CTRL_OFFSET
802 #define CRL_APB_UART1_REF_CTRL_OFFSET 0XFF5E0078
803 #undef CRL_APB_I2C0_REF_CTRL_OFFSET
804 #define CRL_APB_I2C0_REF_CTRL_OFFSET 0XFF5E0120
805 #undef CRL_APB_I2C1_REF_CTRL_OFFSET
806 #define CRL_APB_I2C1_REF_CTRL_OFFSET 0XFF5E0124
807 #undef CRL_APB_CAN1_REF_CTRL_OFFSET
808 #define CRL_APB_CAN1_REF_CTRL_OFFSET 0XFF5E0088
809 #undef CRL_APB_CPU_R5_CTRL_OFFSET
810 #define CRL_APB_CPU_R5_CTRL_OFFSET 0XFF5E0090
811 #undef CRL_APB_IOU_SWITCH_CTRL_OFFSET
812 #define CRL_APB_IOU_SWITCH_CTRL_OFFSET 0XFF5E009C
813 #undef CRL_APB_PCAP_CTRL_OFFSET
814 #define CRL_APB_PCAP_CTRL_OFFSET 0XFF5E00A4
815 #undef CRL_APB_LPD_SWITCH_CTRL_OFFSET
816 #define CRL_APB_LPD_SWITCH_CTRL_OFFSET 0XFF5E00A8
817 #undef CRL_APB_LPD_LSBUS_CTRL_OFFSET
818 #define CRL_APB_LPD_LSBUS_CTRL_OFFSET 0XFF5E00AC
819 #undef CRL_APB_DBG_LPD_CTRL_OFFSET
820 #define CRL_APB_DBG_LPD_CTRL_OFFSET 0XFF5E00B0
821 #undef CRL_APB_ADMA_REF_CTRL_OFFSET
822 #define CRL_APB_ADMA_REF_CTRL_OFFSET 0XFF5E00B8
823 #undef CRL_APB_PL0_REF_CTRL_OFFSET
824 #define CRL_APB_PL0_REF_CTRL_OFFSET 0XFF5E00C0
825 #undef CRL_APB_PL1_REF_CTRL_OFFSET
826 #define CRL_APB_PL1_REF_CTRL_OFFSET 0XFF5E00C4
827 #undef CRL_APB_PL2_REF_CTRL_OFFSET
828 #define CRL_APB_PL2_REF_CTRL_OFFSET 0XFF5E00C8
829 #undef CRL_APB_PL3_REF_CTRL_OFFSET
830 #define CRL_APB_PL3_REF_CTRL_OFFSET 0XFF5E00CC
831 #undef CRL_APB_AMS_REF_CTRL_OFFSET
832 #define CRL_APB_AMS_REF_CTRL_OFFSET 0XFF5E0108
833 #undef CRL_APB_DLL_REF_CTRL_OFFSET
834 #define CRL_APB_DLL_REF_CTRL_OFFSET 0XFF5E0104
835 #undef CRL_APB_TIMESTAMP_REF_CTRL_OFFSET
836 #define CRL_APB_TIMESTAMP_REF_CTRL_OFFSET 0XFF5E0128
837 #undef CRF_APB_SATA_REF_CTRL_OFFSET
838 #define CRF_APB_SATA_REF_CTRL_OFFSET 0XFD1A00A0
839 #undef CRF_APB_PCIE_REF_CTRL_OFFSET
840 #define CRF_APB_PCIE_REF_CTRL_OFFSET 0XFD1A00B4
841 #undef CRF_APB_DP_VIDEO_REF_CTRL_OFFSET
842 #define CRF_APB_DP_VIDEO_REF_CTRL_OFFSET 0XFD1A0070
843 #undef CRF_APB_DP_AUDIO_REF_CTRL_OFFSET
844 #define CRF_APB_DP_AUDIO_REF_CTRL_OFFSET 0XFD1A0074
845 #undef CRF_APB_DP_STC_REF_CTRL_OFFSET
846 #define CRF_APB_DP_STC_REF_CTRL_OFFSET 0XFD1A007C
847 #undef CRF_APB_ACPU_CTRL_OFFSET
848 #define CRF_APB_ACPU_CTRL_OFFSET 0XFD1A0060
849 #undef CRF_APB_DBG_TRACE_CTRL_OFFSET
850 #define CRF_APB_DBG_TRACE_CTRL_OFFSET 0XFD1A0064
851 #undef CRF_APB_DBG_FPD_CTRL_OFFSET
852 #define CRF_APB_DBG_FPD_CTRL_OFFSET 0XFD1A0068
853 #undef CRF_APB_DDR_CTRL_OFFSET
854 #define CRF_APB_DDR_CTRL_OFFSET 0XFD1A0080
855 #undef CRF_APB_GPU_REF_CTRL_OFFSET
856 #define CRF_APB_GPU_REF_CTRL_OFFSET 0XFD1A0084
857 #undef CRF_APB_GDMA_REF_CTRL_OFFSET
858 #define CRF_APB_GDMA_REF_CTRL_OFFSET 0XFD1A00B8
859 #undef CRF_APB_DPDMA_REF_CTRL_OFFSET
860 #define CRF_APB_DPDMA_REF_CTRL_OFFSET 0XFD1A00BC
861 #undef CRF_APB_TOPSW_MAIN_CTRL_OFFSET
862 #define CRF_APB_TOPSW_MAIN_CTRL_OFFSET 0XFD1A00C0
863 #undef CRF_APB_TOPSW_LSBUS_CTRL_OFFSET
864 #define CRF_APB_TOPSW_LSBUS_CTRL_OFFSET 0XFD1A00C4
865 #undef CRF_APB_DBG_TSTMP_CTRL_OFFSET
866 #define CRF_APB_DBG_TSTMP_CTRL_OFFSET 0XFD1A00F8
867 #undef IOU_SLCR_IOU_TTC_APB_CLK_OFFSET
868 #define IOU_SLCR_IOU_TTC_APB_CLK_OFFSET 0XFF180380
869 #undef FPD_SLCR_WDT_CLK_SEL_OFFSET
870 #define FPD_SLCR_WDT_CLK_SEL_OFFSET 0XFD610100
871 #undef IOU_SLCR_WDT_CLK_SEL_OFFSET
872 #define IOU_SLCR_WDT_CLK_SEL_OFFSET 0XFF180300
873 #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET
874 #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET 0XFF410050
876 /*Clock active for the RX channel*/
877 #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL
878 #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT
879 #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK
880 #define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500
881 #define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 26
882 #define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 0x04000000U
884 /*Clock active signal. Switch to 0 to disable the clock*/
885 #undef CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL
886 #undef CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT
887 #undef CRL_APB_GEM3_REF_CTRL_CLKACT_MASK
888 #define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 0x00002500
889 #define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 25
890 #define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 0x02000000U
893 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL
894 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT
895 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK
896 #define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 0x00002500
897 #define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 16
898 #define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 0x003F0000U
901 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL
902 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT
903 #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK
904 #define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 0x00002500
905 #define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 8
906 #define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 0x00003F00U
908 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
909 clock. This is not usually an issue, but designers must be aware.)*/
910 #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL
911 #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT
912 #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK
913 #define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 0x00002500
914 #define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 0
915 #define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 0x00000007U
917 /*Clock active signal. Switch to 0 to disable the clock*/
918 #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL
919 #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT
920 #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK
921 #define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 0x00052000
922 #define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 25
923 #define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 0x02000000U
926 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL
927 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT
928 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK
929 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 0x00052000
930 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 16
931 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 0x003F0000U
934 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL
935 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT
936 #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK
937 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 0x00052000
938 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 8
939 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 0x00003F00U
941 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
942 clock. This is not usually an issue, but designers must be aware.)*/
943 #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL
944 #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT
945 #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK
946 #define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 0x00052000
947 #define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 0
948 #define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 0x00000007U
950 /*Clock active signal. Switch to 0 to disable the clock*/
951 #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL
952 #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT
953 #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK
954 #define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 0x00052000
955 #define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 25
956 #define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 0x02000000U
959 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL
960 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT
961 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK
962 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 0x00052000
963 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 16
964 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 0x003F0000U
967 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL
968 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT
969 #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK
970 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 0x00052000
971 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 8
972 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 0x00003F00U
974 /*000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
975 clock. This is not usually an issue, but designers must be aware.)*/
976 #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL
977 #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT
978 #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK
979 #define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 0x00052000
980 #define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 0
981 #define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 0x00000007U
983 /*Clock active signal. Switch to 0 to disable the clock*/
984 #undef CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL
985 #undef CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT
986 #undef CRL_APB_QSPI_REF_CTRL_CLKACT_MASK
987 #define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 0x01000800
988 #define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 24
989 #define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 0x01000000U
992 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL
993 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT
994 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK
995 #define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 0x01000800
996 #define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 16
997 #define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1000 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL
1001 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT
1002 #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK
1003 #define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 0x01000800
1004 #define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 8
1005 #define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1007 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1008 clock. This is not usually an issue, but designers must be aware.)*/
1009 #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL
1010 #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT
1011 #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK
1012 #define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 0x01000800
1013 #define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 0
1014 #define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 0x00000007U
1016 /*Clock active signal. Switch to 0 to disable the clock*/
1017 #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL
1018 #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT
1019 #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK
1020 #define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 0x01000F00
1021 #define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 24
1022 #define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 0x01000000U
1025 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL
1026 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT
1027 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK
1028 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 0x01000F00
1029 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 16
1030 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1033 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL
1034 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT
1035 #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK
1036 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 0x01000F00
1037 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 8
1038 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1040 /*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1041 clock. This is not usually an issue, but designers must be aware.)*/
1042 #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL
1043 #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT
1044 #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK
1045 #define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 0x01000F00
1046 #define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 0
1047 #define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 0x00000007U
1049 /*MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76]*/
1050 #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL
1051 #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT
1052 #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK
1053 #define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 0x00000000
1054 #define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 17
1055 #define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 0x00020000U
1057 /*Clock active signal. Switch to 0 to disable the clock*/
1058 #undef CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL
1059 #undef CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT
1060 #undef CRL_APB_UART0_REF_CTRL_CLKACT_MASK
1061 #define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 0x01001800
1062 #define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 24
1063 #define CRL_APB_UART0_REF_CTRL_CLKACT_MASK 0x01000000U
1066 #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL
1067 #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT
1068 #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK
1069 #define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
1070 #define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 16
1071 #define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1074 #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL
1075 #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT
1076 #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK
1077 #define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
1078 #define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 8
1079 #define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1081 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1082 clock. This is not usually an issue, but designers must be aware.)*/
1083 #undef CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL
1084 #undef CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT
1085 #undef CRL_APB_UART0_REF_CTRL_SRCSEL_MASK
1086 #define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 0x01001800
1087 #define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 0
1088 #define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 0x00000007U
1090 /*Clock active signal. Switch to 0 to disable the clock*/
1091 #undef CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL
1092 #undef CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT
1093 #undef CRL_APB_UART1_REF_CTRL_CLKACT_MASK
1094 #define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 0x01001800
1095 #define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 24
1096 #define CRL_APB_UART1_REF_CTRL_CLKACT_MASK 0x01000000U
1099 #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL
1100 #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT
1101 #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK
1102 #define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
1103 #define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 16
1104 #define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1107 #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL
1108 #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT
1109 #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK
1110 #define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
1111 #define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 8
1112 #define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1114 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1115 clock. This is not usually an issue, but designers must be aware.)*/
1116 #undef CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL
1117 #undef CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT
1118 #undef CRL_APB_UART1_REF_CTRL_SRCSEL_MASK
1119 #define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 0x01001800
1120 #define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 0
1121 #define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 0x00000007U
1123 /*Clock active signal. Switch to 0 to disable the clock*/
1124 #undef CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL
1125 #undef CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT
1126 #undef CRL_APB_I2C0_REF_CTRL_CLKACT_MASK
1127 #define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 0x01000500
1128 #define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 24
1129 #define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 0x01000000U
1132 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL
1133 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT
1134 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK
1135 #define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 0x01000500
1136 #define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 16
1137 #define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1140 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL
1141 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT
1142 #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK
1143 #define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 0x01000500
1144 #define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 8
1145 #define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1147 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1148 clock. This is not usually an issue, but designers must be aware.)*/
1149 #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL
1150 #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT
1151 #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK
1152 #define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 0x01000500
1153 #define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 0
1154 #define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 0x00000007U
1156 /*Clock active signal. Switch to 0 to disable the clock*/
1157 #undef CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL
1158 #undef CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT
1159 #undef CRL_APB_I2C1_REF_CTRL_CLKACT_MASK
1160 #define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 0x01000500
1161 #define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 24
1162 #define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 0x01000000U
1165 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL
1166 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT
1167 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK
1168 #define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 0x01000500
1169 #define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 16
1170 #define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1173 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL
1174 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT
1175 #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK
1176 #define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 0x01000500
1177 #define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 8
1178 #define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1180 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1181 clock. This is not usually an issue, but designers must be aware.)*/
1182 #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL
1183 #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT
1184 #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK
1185 #define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 0x01000500
1186 #define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 0
1187 #define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 0x00000007U
1189 /*Clock active signal. Switch to 0 to disable the clock*/
1190 #undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL
1191 #undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT
1192 #undef CRL_APB_CAN1_REF_CTRL_CLKACT_MASK
1193 #define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 0x01001800
1194 #define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 24
1195 #define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 0x01000000U
1198 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL
1199 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT
1200 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK
1201 #define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
1202 #define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 16
1203 #define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1206 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL
1207 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT
1208 #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK
1209 #define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
1210 #define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 8
1211 #define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1213 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1214 clock. This is not usually an issue, but designers must be aware.)*/
1215 #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL
1216 #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT
1217 #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK
1218 #define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 0x01001800
1219 #define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 0
1220 #define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 0x00000007U
1222 /*Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou
1223 d lead to system hang*/
1224 #undef CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL
1225 #undef CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT
1226 #undef CRL_APB_CPU_R5_CTRL_CLKACT_MASK
1227 #define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 0x03000600
1228 #define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 24
1229 #define CRL_APB_CPU_R5_CTRL_CLKACT_MASK 0x01000000U
1232 #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL
1233 #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT
1234 #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK
1235 #define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 0x03000600
1236 #define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 8
1237 #define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 0x00003F00U
1239 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1240 clock. This is not usually an issue, but designers must be aware.)*/
1241 #undef CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL
1242 #undef CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT
1243 #undef CRL_APB_CPU_R5_CTRL_SRCSEL_MASK
1244 #define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 0x03000600
1245 #define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 0
1246 #define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 0x00000007U
1248 /*Clock active signal. Switch to 0 to disable the clock*/
1249 #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL
1250 #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT
1251 #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK
1252 #define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 0x00001500
1253 #define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 24
1254 #define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 0x01000000U
1257 #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL
1258 #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT
1259 #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK
1260 #define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 0x00001500
1261 #define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8
1262 #define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U
1264 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1265 clock. This is not usually an issue, but designers must be aware.)*/
1266 #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL
1267 #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT
1268 #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK
1269 #define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 0x00001500
1270 #define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 0
1271 #define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 0x00000007U
1273 /*Clock active signal. Switch to 0 to disable the clock*/
1274 #undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL
1275 #undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT
1276 #undef CRL_APB_PCAP_CTRL_CLKACT_MASK
1277 #define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 0x00001500
1278 #define CRL_APB_PCAP_CTRL_CLKACT_SHIFT 24
1279 #define CRL_APB_PCAP_CTRL_CLKACT_MASK 0x01000000U
1282 #undef CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL
1283 #undef CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT
1284 #undef CRL_APB_PCAP_CTRL_DIVISOR0_MASK
1285 #define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 0x00001500
1286 #define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 8
1287 #define CRL_APB_PCAP_CTRL_DIVISOR0_MASK 0x00003F00U
1289 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1290 clock. This is not usually an issue, but designers must be aware.)*/
1291 #undef CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL
1292 #undef CRL_APB_PCAP_CTRL_SRCSEL_SHIFT
1293 #undef CRL_APB_PCAP_CTRL_SRCSEL_MASK
1294 #define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 0x00001500
1295 #define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 0
1296 #define CRL_APB_PCAP_CTRL_SRCSEL_MASK 0x00000007U
1298 /*Clock active signal. Switch to 0 to disable the clock*/
1299 #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL
1300 #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT
1301 #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK
1302 #define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 0x01000500
1303 #define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 24
1304 #define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 0x01000000U
1307 #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL
1308 #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT
1309 #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK
1310 #define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 0x01000500
1311 #define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 8
1312 #define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U
1314 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1315 clock. This is not usually an issue, but designers must be aware.)*/
1316 #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL
1317 #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT
1318 #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK
1319 #define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 0x01000500
1320 #define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 0
1321 #define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 0x00000007U
1323 /*Clock active signal. Switch to 0 to disable the clock*/
1324 #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL
1325 #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT
1326 #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK
1327 #define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 0x01001800
1328 #define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 24
1329 #define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 0x01000000U
1332 #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL
1333 #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT
1334 #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK
1335 #define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01001800
1336 #define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 8
1337 #define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U
1339 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1340 clock. This is not usually an issue, but designers must be aware.)*/
1341 #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL
1342 #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT
1343 #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK
1344 #define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 0x01001800
1345 #define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 0
1346 #define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 0x00000007U
1348 /*Clock active signal. Switch to 0 to disable the clock*/
1349 #undef CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL
1350 #undef CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT
1351 #undef CRL_APB_DBG_LPD_CTRL_CLKACT_MASK
1352 #define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 0x01002000
1353 #define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 24
1354 #define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 0x01000000U
1357 #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL
1358 #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT
1359 #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK
1360 #define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 0x01002000
1361 #define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 8
1362 #define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 0x00003F00U
1364 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1365 clock. This is not usually an issue, but designers must be aware.)*/
1366 #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL
1367 #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT
1368 #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK
1369 #define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 0x01002000
1370 #define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 0
1371 #define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 0x00000007U
1373 /*Clock active signal. Switch to 0 to disable the clock*/
1374 #undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL
1375 #undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT
1376 #undef CRL_APB_ADMA_REF_CTRL_CLKACT_MASK
1377 #define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 0x00002000
1378 #define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 24
1379 #define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 0x01000000U
1382 #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL
1383 #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT
1384 #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK
1385 #define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 0x00002000
1386 #define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 8
1387 #define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1389 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1390 clock. This is not usually an issue, but designers must be aware.)*/
1391 #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL
1392 #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT
1393 #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK
1394 #define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 0x00002000
1395 #define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 0
1396 #define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 0x00000007U
1398 /*Clock active signal. Switch to 0 to disable the clock*/
1399 #undef CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL
1400 #undef CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT
1401 #undef CRL_APB_PL0_REF_CTRL_CLKACT_MASK
1402 #define CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL 0x00052000
1403 #define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 24
1404 #define CRL_APB_PL0_REF_CTRL_CLKACT_MASK 0x01000000U
1407 #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL
1408 #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT
1409 #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK
1410 #define CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL 0x00052000
1411 #define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 16
1412 #define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1415 #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL
1416 #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT
1417 #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK
1418 #define CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL 0x00052000
1419 #define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 8
1420 #define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1422 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1423 clock. This is not usually an issue, but designers must be aware.)*/
1424 #undef CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL
1425 #undef CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT
1426 #undef CRL_APB_PL0_REF_CTRL_SRCSEL_MASK
1427 #define CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL 0x00052000
1428 #define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 0
1429 #define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK 0x00000007U
1431 /*Clock active signal. Switch to 0 to disable the clock*/
1432 #undef CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL
1433 #undef CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT
1434 #undef CRL_APB_PL1_REF_CTRL_CLKACT_MASK
1435 #define CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL 0x00052000
1436 #define CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT 24
1437 #define CRL_APB_PL1_REF_CTRL_CLKACT_MASK 0x01000000U
1440 #undef CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL
1441 #undef CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT
1442 #undef CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK
1443 #define CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL 0x00052000
1444 #define CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT 16
1445 #define CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1448 #undef CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL
1449 #undef CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT
1450 #undef CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK
1451 #define CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL 0x00052000
1452 #define CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT 8
1453 #define CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1455 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1456 clock. This is not usually an issue, but designers must be aware.)*/
1457 #undef CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL
1458 #undef CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT
1459 #undef CRL_APB_PL1_REF_CTRL_SRCSEL_MASK
1460 #define CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL 0x00052000
1461 #define CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT 0
1462 #define CRL_APB_PL1_REF_CTRL_SRCSEL_MASK 0x00000007U
1464 /*Clock active signal. Switch to 0 to disable the clock*/
1465 #undef CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL
1466 #undef CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT
1467 #undef CRL_APB_PL2_REF_CTRL_CLKACT_MASK
1468 #define CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL 0x00052000
1469 #define CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT 24
1470 #define CRL_APB_PL2_REF_CTRL_CLKACT_MASK 0x01000000U
1473 #undef CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL
1474 #undef CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT
1475 #undef CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK
1476 #define CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL 0x00052000
1477 #define CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT 16
1478 #define CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1481 #undef CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL
1482 #undef CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT
1483 #undef CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK
1484 #define CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL 0x00052000
1485 #define CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT 8
1486 #define CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1488 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1489 clock. This is not usually an issue, but designers must be aware.)*/
1490 #undef CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL
1491 #undef CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT
1492 #undef CRL_APB_PL2_REF_CTRL_SRCSEL_MASK
1493 #define CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL 0x00052000
1494 #define CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT 0
1495 #define CRL_APB_PL2_REF_CTRL_SRCSEL_MASK 0x00000007U
1497 /*Clock active signal. Switch to 0 to disable the clock*/
1498 #undef CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL
1499 #undef CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT
1500 #undef CRL_APB_PL3_REF_CTRL_CLKACT_MASK
1501 #define CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL 0x00052000
1502 #define CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT 24
1503 #define CRL_APB_PL3_REF_CTRL_CLKACT_MASK 0x01000000U
1506 #undef CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL
1507 #undef CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT
1508 #undef CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK
1509 #define CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL 0x00052000
1510 #define CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT 16
1511 #define CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1514 #undef CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL
1515 #undef CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT
1516 #undef CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK
1517 #define CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL 0x00052000
1518 #define CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT 8
1519 #define CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1521 /*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1522 clock. This is not usually an issue, but designers must be aware.)*/
1523 #undef CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL
1524 #undef CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT
1525 #undef CRL_APB_PL3_REF_CTRL_SRCSEL_MASK
1526 #define CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL 0x00052000
1527 #define CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT 0
1528 #define CRL_APB_PL3_REF_CTRL_SRCSEL_MASK 0x00000007U
1531 #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL
1532 #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT
1533 #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK
1534 #define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 0x01001800
1535 #define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16
1536 #define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1539 #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL
1540 #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT
1541 #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK
1542 #define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 0x01001800
1543 #define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8
1544 #define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1546 /*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1547 clock. This is not usually an issue, but designers must be aware.)*/
1548 #undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL
1549 #undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT
1550 #undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK
1551 #define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 0x01001800
1552 #define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0
1553 #define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 0x00000007U
1555 /*Clock active signal. Switch to 0 to disable the clock*/
1556 #undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL
1557 #undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT
1558 #undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK
1559 #define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 0x01001800
1560 #define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24
1561 #define CRL_APB_AMS_REF_CTRL_CLKACT_MASK 0x01000000U
1563 /*000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
1564 is not usually an issue, but designers must be aware.)*/
1565 #undef CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL
1566 #undef CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT
1567 #undef CRL_APB_DLL_REF_CTRL_SRCSEL_MASK
1568 #define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 0x00000000
1569 #define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 0
1570 #define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 0x00000007U
1573 #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL
1574 #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT
1575 #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK
1576 #define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 0x00001800
1577 #define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 8
1578 #define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1580 /*1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and
1581 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
1582 #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL
1583 #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT
1584 #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK
1585 #define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 0x00001800
1586 #define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 0
1587 #define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 0x00000007U
1589 /*Clock active signal. Switch to 0 to disable the clock*/
1590 #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL
1591 #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT
1592 #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK
1593 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 0x00001800
1594 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 24
1595 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 0x01000000U
1597 /*000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1598 he new clock. This is not usually an issue, but designers must be aware.)*/
1599 #undef CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL
1600 #undef CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT
1601 #undef CRF_APB_SATA_REF_CTRL_SRCSEL_MASK
1602 #define CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL 0x01001600
1603 #define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 0
1604 #define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK 0x00000007U
1606 /*Clock active signal. Switch to 0 to disable the clock*/
1607 #undef CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL
1608 #undef CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT
1609 #undef CRF_APB_SATA_REF_CTRL_CLKACT_MASK
1610 #define CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL 0x01001600
1611 #define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 24
1612 #define CRF_APB_SATA_REF_CTRL_CLKACT_MASK 0x01000000U
1615 #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL
1616 #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT
1617 #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK
1618 #define CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL 0x01001600
1619 #define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 8
1620 #define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1622 /*000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc
1623 es of the new clock. This is not usually an issue, but designers must be aware.)*/
1624 #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL
1625 #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT
1626 #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK
1627 #define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 0x00001500
1628 #define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 0
1629 #define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 0x00000007U
1631 /*Clock active signal. Switch to 0 to disable the clock*/
1632 #undef CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL
1633 #undef CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT
1634 #undef CRF_APB_PCIE_REF_CTRL_CLKACT_MASK
1635 #define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 0x00001500
1636 #define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 24
1637 #define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 0x01000000U
1640 #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL
1641 #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT
1642 #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK
1643 #define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 0x00001500
1644 #define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 8
1645 #define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1648 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL
1649 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT
1650 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK
1651 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 0x01002300
1652 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16
1653 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1656 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL
1657 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT
1658 #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK
1659 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 0x01002300
1660 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8
1661 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1663 /*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the
1664 ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
1665 #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL
1666 #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT
1667 #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK
1668 #define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 0x01002300
1669 #define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 0
1670 #define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007U
1672 /*Clock active signal. Switch to 0 to disable the clock*/
1673 #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL
1674 #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT
1675 #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK
1676 #define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 0x01002300
1677 #define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 24
1678 #define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000U
1681 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL
1682 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT
1683 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK
1684 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 0x01032300
1685 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 16
1686 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1689 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL
1690 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT
1691 #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK
1692 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 0x01032300
1693 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 8
1694 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1696 /*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the
1697 ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
1698 #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL
1699 #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT
1700 #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK
1701 #define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 0x01032300
1702 #define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 0
1703 #define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 0x00000007U
1705 /*Clock active signal. Switch to 0 to disable the clock*/
1706 #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL
1707 #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT
1708 #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK
1709 #define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 0x01032300
1710 #define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 24
1711 #define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 0x01000000U
1714 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL
1715 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT
1716 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK
1717 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 0x01203200
1718 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 16
1719 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 0x003F0000U
1722 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL
1723 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT
1724 #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK
1725 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 0x01203200
1726 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 8
1727 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1729 /*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t
1730 e new clock. This is not usually an issue, but designers must be aware.)*/
1731 #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL
1732 #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT
1733 #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK
1734 #define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 0x01203200
1735 #define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 0
1736 #define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 0x00000007U
1738 /*Clock active signal. Switch to 0 to disable the clock*/
1739 #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL
1740 #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT
1741 #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK
1742 #define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 0x01203200
1743 #define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 24
1744 #define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 0x01000000U
1747 #undef CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL
1748 #undef CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT
1749 #undef CRF_APB_ACPU_CTRL_DIVISOR0_MASK
1750 #define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 0x03000400
1751 #define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 8
1752 #define CRF_APB_ACPU_CTRL_DIVISOR0_MASK 0x00003F00U
1754 /*000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1755 lock. This is not usually an issue, but designers must be aware.)*/
1756 #undef CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL
1757 #undef CRF_APB_ACPU_CTRL_SRCSEL_SHIFT
1758 #undef CRF_APB_ACPU_CTRL_SRCSEL_MASK
1759 #define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 0x03000400
1760 #define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 0
1761 #define CRF_APB_ACPU_CTRL_SRCSEL_MASK 0x00000007U
1763 /*Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock*/
1764 #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL
1765 #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT
1766 #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK
1767 #define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 0x03000400
1768 #define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 25
1769 #define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 0x02000000U
1771 /*Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc
1773 #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL
1774 #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT
1775 #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK
1776 #define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 0x03000400
1777 #define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 24
1778 #define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 0x01000000U
1781 #undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL
1782 #undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT
1783 #undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK
1784 #define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL 0x00002500
1785 #define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT 8
1786 #define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK 0x00003F00U
1788 /*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1789 he new clock. This is not usually an issue, but designers must be aware.)*/
1790 #undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL
1791 #undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT
1792 #undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK
1793 #define CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL 0x00002500
1794 #define CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT 0
1795 #define CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK 0x00000007U
1797 /*Clock active signal. Switch to 0 to disable the clock*/
1798 #undef CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL
1799 #undef CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT
1800 #undef CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK
1801 #define CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL 0x00002500
1802 #define CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT 24
1803 #define CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK 0x01000000U
1806 #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL
1807 #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT
1808 #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK
1809 #define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 0x01002500
1810 #define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 8
1811 #define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 0x00003F00U
1813 /*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1814 he new clock. This is not usually an issue, but designers must be aware.)*/
1815 #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL
1816 #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT
1817 #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK
1818 #define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 0x01002500
1819 #define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 0
1820 #define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 0x00000007U
1822 /*Clock active signal. Switch to 0 to disable the clock*/
1823 #undef CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL
1824 #undef CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT
1825 #undef CRF_APB_DBG_FPD_CTRL_CLKACT_MASK
1826 #define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 0x01002500
1827 #define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 24
1828 #define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 0x01000000U
1831 #undef CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL
1832 #undef CRF_APB_DDR_CTRL_DIVISOR0_SHIFT
1833 #undef CRF_APB_DDR_CTRL_DIVISOR0_MASK
1834 #define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 0x01000500
1835 #define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 8
1836 #define CRF_APB_DDR_CTRL_DIVISOR0_MASK 0x00003F00U
1838 /*000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
1839 s not usually an issue, but designers must be aware.)*/
1840 #undef CRF_APB_DDR_CTRL_SRCSEL_DEFVAL
1841 #undef CRF_APB_DDR_CTRL_SRCSEL_SHIFT
1842 #undef CRF_APB_DDR_CTRL_SRCSEL_MASK
1843 #define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 0x01000500
1844 #define CRF_APB_DDR_CTRL_SRCSEL_SHIFT 0
1845 #define CRF_APB_DDR_CTRL_SRCSEL_MASK 0x00000007U
1848 #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL
1849 #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT
1850 #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK
1851 #define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 0x00001500
1852 #define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 8
1853 #define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1855 /*000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1856 he new clock. This is not usually an issue, but designers must be aware.)*/
1857 #undef CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL
1858 #undef CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT
1859 #undef CRF_APB_GPU_REF_CTRL_SRCSEL_MASK
1860 #define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 0x00001500
1861 #define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 0
1862 #define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 0x00000007U
1864 /*Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors).*/
1865 #undef CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL
1866 #undef CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT
1867 #undef CRF_APB_GPU_REF_CTRL_CLKACT_MASK
1868 #define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 0x00001500
1869 #define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 24
1870 #define CRF_APB_GPU_REF_CTRL_CLKACT_MASK 0x01000000U
1872 /*Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor*/
1873 #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL
1874 #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT
1875 #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK
1876 #define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 0x00001500
1877 #define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 25
1878 #define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 0x02000000U
1880 /*Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor*/
1881 #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL
1882 #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT
1883 #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK
1884 #define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 0x00001500
1885 #define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 26
1886 #define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 0x04000000U
1889 #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL
1890 #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT
1891 #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK
1892 #define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500
1893 #define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 8
1894 #define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1896 /*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1897 lock. This is not usually an issue, but designers must be aware.)*/
1898 #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL
1899 #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT
1900 #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK
1901 #define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500
1902 #define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 0
1903 #define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 0x00000007U
1905 /*Clock active signal. Switch to 0 to disable the clock*/
1906 #undef CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL
1907 #undef CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT
1908 #undef CRF_APB_GDMA_REF_CTRL_CLKACT_MASK
1909 #define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500
1910 #define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 24
1911 #define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 0x01000000U
1914 #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL
1915 #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT
1916 #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK
1917 #define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500
1918 #define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 8
1919 #define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U
1921 /*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1922 lock. This is not usually an issue, but designers must be aware.)*/
1923 #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL
1924 #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT
1925 #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK
1926 #define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500
1927 #define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 0
1928 #define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 0x00000007U
1930 /*Clock active signal. Switch to 0 to disable the clock*/
1931 #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL
1932 #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT
1933 #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK
1934 #define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500
1935 #define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 24
1936 #define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 0x01000000U
1939 #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL
1940 #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT
1941 #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK
1942 #define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 0x01000400
1943 #define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 8
1944 #define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 0x00003F00U
1946 /*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1947 lock. This is not usually an issue, but designers must be aware.)*/
1948 #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL
1949 #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT
1950 #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK
1951 #define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 0x01000400
1952 #define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 0
1953 #define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 0x00000007U
1955 /*Clock active signal. Switch to 0 to disable the clock*/
1956 #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL
1957 #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT
1958 #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK
1959 #define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 0x01000400
1960 #define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 24
1961 #define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 0x01000000U
1964 #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL
1965 #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT
1966 #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK
1967 #define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01000800
1968 #define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 8
1969 #define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U
1971 /*000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1972 he new clock. This is not usually an issue, but designers must be aware.)*/
1973 #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL
1974 #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT
1975 #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK
1976 #define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 0x01000800
1977 #define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 0
1978 #define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 0x00000007U
1980 /*Clock active signal. Switch to 0 to disable the clock*/
1981 #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL
1982 #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT
1983 #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK
1984 #define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 0x01000800
1985 #define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 24
1986 #define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 0x01000000U
1989 #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL
1990 #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT
1991 #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK
1992 #define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 0x00000A00
1993 #define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 8
1994 #define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 0x00003F00U
1996 /*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1997 he new clock. This is not usually an issue, but designers must be aware.)*/
1998 #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL
1999 #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT
2000 #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK
2001 #define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 0x00000A00
2002 #define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 0
2003 #define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 0x00000007U
2005 /*00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0'
2006 0" = Select the R5 clock for the APB interface of TTC0*/
2007 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL
2008 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT
2009 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK
2010 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL 0x00000000
2011 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT 0
2012 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK 0x00000003U
2014 /*00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1'
2015 0" = Select the R5 clock for the APB interface of TTC1*/
2016 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL
2017 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT
2018 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK
2019 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL 0x00000000
2020 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT 2
2021 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK 0x0000000CU
2023 /*00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2'
2024 0" = Select the R5 clock for the APB interface of TTC2*/
2025 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL
2026 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT
2027 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK
2028 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL 0x00000000
2029 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT 4
2030 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK 0x00000030U
2032 /*00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3'
2033 0" = Select the R5 clock for the APB interface of TTC3*/
2034 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL
2035 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT
2036 #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK
2037 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL 0x00000000
2038 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT 6
2039 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK 0x000000C0U
2041 /*System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO)*/
2042 #undef FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL
2043 #undef FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT
2044 #undef FPD_SLCR_WDT_CLK_SEL_SELECT_MASK
2045 #define FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000
2046 #define FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0
2047 #define FPD_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U
2049 /*System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout
2051 #undef IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL
2052 #undef IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT
2053 #undef IOU_SLCR_WDT_CLK_SEL_SELECT_MASK
2054 #define IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000
2055 #define IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0
2056 #define IOU_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U
2058 /*System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk*/
2059 #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL
2060 #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT
2061 #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK
2062 #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000
2063 #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 0
2064 #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK 0x00000001U
2065 #undef CRF_APB_RST_DDR_SS_OFFSET
2066 #define CRF_APB_RST_DDR_SS_OFFSET 0XFD1A0108
2067 #undef DDRC_MSTR_OFFSET
2068 #define DDRC_MSTR_OFFSET 0XFD070000
2069 #undef DDRC_MRCTRL0_OFFSET
2070 #define DDRC_MRCTRL0_OFFSET 0XFD070010
2071 #undef DDRC_DERATEEN_OFFSET
2072 #define DDRC_DERATEEN_OFFSET 0XFD070020
2073 #undef DDRC_DERATEINT_OFFSET
2074 #define DDRC_DERATEINT_OFFSET 0XFD070024
2075 #undef DDRC_PWRCTL_OFFSET
2076 #define DDRC_PWRCTL_OFFSET 0XFD070030
2077 #undef DDRC_PWRTMG_OFFSET
2078 #define DDRC_PWRTMG_OFFSET 0XFD070034
2079 #undef DDRC_RFSHCTL0_OFFSET
2080 #define DDRC_RFSHCTL0_OFFSET 0XFD070050
2081 #undef DDRC_RFSHCTL3_OFFSET
2082 #define DDRC_RFSHCTL3_OFFSET 0XFD070060
2083 #undef DDRC_RFSHTMG_OFFSET
2084 #define DDRC_RFSHTMG_OFFSET 0XFD070064
2085 #undef DDRC_ECCCFG0_OFFSET
2086 #define DDRC_ECCCFG0_OFFSET 0XFD070070
2087 #undef DDRC_ECCCFG1_OFFSET
2088 #define DDRC_ECCCFG1_OFFSET 0XFD070074
2089 #undef DDRC_CRCPARCTL1_OFFSET
2090 #define DDRC_CRCPARCTL1_OFFSET 0XFD0700C4
2091 #undef DDRC_CRCPARCTL2_OFFSET
2092 #define DDRC_CRCPARCTL2_OFFSET 0XFD0700C8
2093 #undef DDRC_INIT0_OFFSET
2094 #define DDRC_INIT0_OFFSET 0XFD0700D0
2095 #undef DDRC_INIT1_OFFSET
2096 #define DDRC_INIT1_OFFSET 0XFD0700D4
2097 #undef DDRC_INIT2_OFFSET
2098 #define DDRC_INIT2_OFFSET 0XFD0700D8
2099 #undef DDRC_INIT3_OFFSET
2100 #define DDRC_INIT3_OFFSET 0XFD0700DC
2101 #undef DDRC_INIT4_OFFSET
2102 #define DDRC_INIT4_OFFSET 0XFD0700E0
2103 #undef DDRC_INIT5_OFFSET
2104 #define DDRC_INIT5_OFFSET 0XFD0700E4
2105 #undef DDRC_INIT6_OFFSET
2106 #define DDRC_INIT6_OFFSET 0XFD0700E8
2107 #undef DDRC_INIT7_OFFSET
2108 #define DDRC_INIT7_OFFSET 0XFD0700EC
2109 #undef DDRC_DIMMCTL_OFFSET
2110 #define DDRC_DIMMCTL_OFFSET 0XFD0700F0
2111 #undef DDRC_RANKCTL_OFFSET
2112 #define DDRC_RANKCTL_OFFSET 0XFD0700F4
2113 #undef DDRC_DRAMTMG0_OFFSET
2114 #define DDRC_DRAMTMG0_OFFSET 0XFD070100
2115 #undef DDRC_DRAMTMG1_OFFSET
2116 #define DDRC_DRAMTMG1_OFFSET 0XFD070104
2117 #undef DDRC_DRAMTMG2_OFFSET
2118 #define DDRC_DRAMTMG2_OFFSET 0XFD070108
2119 #undef DDRC_DRAMTMG3_OFFSET
2120 #define DDRC_DRAMTMG3_OFFSET 0XFD07010C
2121 #undef DDRC_DRAMTMG4_OFFSET
2122 #define DDRC_DRAMTMG4_OFFSET 0XFD070110
2123 #undef DDRC_DRAMTMG5_OFFSET
2124 #define DDRC_DRAMTMG5_OFFSET 0XFD070114
2125 #undef DDRC_DRAMTMG6_OFFSET
2126 #define DDRC_DRAMTMG6_OFFSET 0XFD070118
2127 #undef DDRC_DRAMTMG7_OFFSET
2128 #define DDRC_DRAMTMG7_OFFSET 0XFD07011C
2129 #undef DDRC_DRAMTMG8_OFFSET
2130 #define DDRC_DRAMTMG8_OFFSET 0XFD070120
2131 #undef DDRC_DRAMTMG9_OFFSET
2132 #define DDRC_DRAMTMG9_OFFSET 0XFD070124
2133 #undef DDRC_DRAMTMG11_OFFSET
2134 #define DDRC_DRAMTMG11_OFFSET 0XFD07012C
2135 #undef DDRC_DRAMTMG12_OFFSET
2136 #define DDRC_DRAMTMG12_OFFSET 0XFD070130
2137 #undef DDRC_ZQCTL0_OFFSET
2138 #define DDRC_ZQCTL0_OFFSET 0XFD070180
2139 #undef DDRC_ZQCTL1_OFFSET
2140 #define DDRC_ZQCTL1_OFFSET 0XFD070184
2141 #undef DDRC_DFITMG0_OFFSET
2142 #define DDRC_DFITMG0_OFFSET 0XFD070190
2143 #undef DDRC_DFITMG1_OFFSET
2144 #define DDRC_DFITMG1_OFFSET 0XFD070194
2145 #undef DDRC_DFILPCFG0_OFFSET
2146 #define DDRC_DFILPCFG0_OFFSET 0XFD070198
2147 #undef DDRC_DFILPCFG1_OFFSET
2148 #define DDRC_DFILPCFG1_OFFSET 0XFD07019C
2149 #undef DDRC_DFIUPD1_OFFSET
2150 #define DDRC_DFIUPD1_OFFSET 0XFD0701A4
2151 #undef DDRC_DFIMISC_OFFSET
2152 #define DDRC_DFIMISC_OFFSET 0XFD0701B0
2153 #undef DDRC_DFITMG2_OFFSET
2154 #define DDRC_DFITMG2_OFFSET 0XFD0701B4
2155 #undef DDRC_DBICTL_OFFSET
2156 #define DDRC_DBICTL_OFFSET 0XFD0701C0
2157 #undef DDRC_ADDRMAP0_OFFSET
2158 #define DDRC_ADDRMAP0_OFFSET 0XFD070200
2159 #undef DDRC_ADDRMAP1_OFFSET
2160 #define DDRC_ADDRMAP1_OFFSET 0XFD070204
2161 #undef DDRC_ADDRMAP2_OFFSET
2162 #define DDRC_ADDRMAP2_OFFSET 0XFD070208
2163 #undef DDRC_ADDRMAP3_OFFSET
2164 #define DDRC_ADDRMAP3_OFFSET 0XFD07020C
2165 #undef DDRC_ADDRMAP4_OFFSET
2166 #define DDRC_ADDRMAP4_OFFSET 0XFD070210
2167 #undef DDRC_ADDRMAP5_OFFSET
2168 #define DDRC_ADDRMAP5_OFFSET 0XFD070214
2169 #undef DDRC_ADDRMAP6_OFFSET
2170 #define DDRC_ADDRMAP6_OFFSET 0XFD070218
2171 #undef DDRC_ADDRMAP7_OFFSET
2172 #define DDRC_ADDRMAP7_OFFSET 0XFD07021C
2173 #undef DDRC_ADDRMAP8_OFFSET
2174 #define DDRC_ADDRMAP8_OFFSET 0XFD070220
2175 #undef DDRC_ADDRMAP9_OFFSET
2176 #define DDRC_ADDRMAP9_OFFSET 0XFD070224
2177 #undef DDRC_ADDRMAP10_OFFSET
2178 #define DDRC_ADDRMAP10_OFFSET 0XFD070228
2179 #undef DDRC_ADDRMAP11_OFFSET
2180 #define DDRC_ADDRMAP11_OFFSET 0XFD07022C
2181 #undef DDRC_ODTCFG_OFFSET
2182 #define DDRC_ODTCFG_OFFSET 0XFD070240
2183 #undef DDRC_ODTMAP_OFFSET
2184 #define DDRC_ODTMAP_OFFSET 0XFD070244
2185 #undef DDRC_SCHED_OFFSET
2186 #define DDRC_SCHED_OFFSET 0XFD070250
2187 #undef DDRC_PERFLPR1_OFFSET
2188 #define DDRC_PERFLPR1_OFFSET 0XFD070264
2189 #undef DDRC_PERFWR1_OFFSET
2190 #define DDRC_PERFWR1_OFFSET 0XFD07026C
2191 #undef DDRC_DQMAP5_OFFSET
2192 #define DDRC_DQMAP5_OFFSET 0XFD070294
2193 #undef DDRC_DBG0_OFFSET
2194 #define DDRC_DBG0_OFFSET 0XFD070300
2195 #undef DDRC_DBGCMD_OFFSET
2196 #define DDRC_DBGCMD_OFFSET 0XFD07030C
2197 #undef DDRC_SWCTL_OFFSET
2198 #define DDRC_SWCTL_OFFSET 0XFD070320
2199 #undef DDRC_PCCFG_OFFSET
2200 #define DDRC_PCCFG_OFFSET 0XFD070400
2201 #undef DDRC_PCFGR_0_OFFSET
2202 #define DDRC_PCFGR_0_OFFSET 0XFD070404
2203 #undef DDRC_PCFGW_0_OFFSET
2204 #define DDRC_PCFGW_0_OFFSET 0XFD070408
2205 #undef DDRC_PCTRL_0_OFFSET
2206 #define DDRC_PCTRL_0_OFFSET 0XFD070490
2207 #undef DDRC_PCFGQOS0_0_OFFSET
2208 #define DDRC_PCFGQOS0_0_OFFSET 0XFD070494
2209 #undef DDRC_PCFGQOS1_0_OFFSET
2210 #define DDRC_PCFGQOS1_0_OFFSET 0XFD070498
2211 #undef DDRC_PCFGR_1_OFFSET
2212 #define DDRC_PCFGR_1_OFFSET 0XFD0704B4
2213 #undef DDRC_PCFGW_1_OFFSET
2214 #define DDRC_PCFGW_1_OFFSET 0XFD0704B8
2215 #undef DDRC_PCTRL_1_OFFSET
2216 #define DDRC_PCTRL_1_OFFSET 0XFD070540
2217 #undef DDRC_PCFGQOS0_1_OFFSET
2218 #define DDRC_PCFGQOS0_1_OFFSET 0XFD070544
2219 #undef DDRC_PCFGQOS1_1_OFFSET
2220 #define DDRC_PCFGQOS1_1_OFFSET 0XFD070548
2221 #undef DDRC_PCFGR_2_OFFSET
2222 #define DDRC_PCFGR_2_OFFSET 0XFD070564
2223 #undef DDRC_PCFGW_2_OFFSET
2224 #define DDRC_PCFGW_2_OFFSET 0XFD070568
2225 #undef DDRC_PCTRL_2_OFFSET
2226 #define DDRC_PCTRL_2_OFFSET 0XFD0705F0
2227 #undef DDRC_PCFGQOS0_2_OFFSET
2228 #define DDRC_PCFGQOS0_2_OFFSET 0XFD0705F4
2229 #undef DDRC_PCFGQOS1_2_OFFSET
2230 #define DDRC_PCFGQOS1_2_OFFSET 0XFD0705F8
2231 #undef DDRC_PCFGR_3_OFFSET
2232 #define DDRC_PCFGR_3_OFFSET 0XFD070614
2233 #undef DDRC_PCFGW_3_OFFSET
2234 #define DDRC_PCFGW_3_OFFSET 0XFD070618
2235 #undef DDRC_PCTRL_3_OFFSET
2236 #define DDRC_PCTRL_3_OFFSET 0XFD0706A0
2237 #undef DDRC_PCFGQOS0_3_OFFSET
2238 #define DDRC_PCFGQOS0_3_OFFSET 0XFD0706A4
2239 #undef DDRC_PCFGQOS1_3_OFFSET
2240 #define DDRC_PCFGQOS1_3_OFFSET 0XFD0706A8
2241 #undef DDRC_PCFGWQOS0_3_OFFSET
2242 #define DDRC_PCFGWQOS0_3_OFFSET 0XFD0706AC
2243 #undef DDRC_PCFGWQOS1_3_OFFSET
2244 #define DDRC_PCFGWQOS1_3_OFFSET 0XFD0706B0
2245 #undef DDRC_PCFGR_4_OFFSET
2246 #define DDRC_PCFGR_4_OFFSET 0XFD0706C4
2247 #undef DDRC_PCFGW_4_OFFSET
2248 #define DDRC_PCFGW_4_OFFSET 0XFD0706C8
2249 #undef DDRC_PCTRL_4_OFFSET
2250 #define DDRC_PCTRL_4_OFFSET 0XFD070750
2251 #undef DDRC_PCFGQOS0_4_OFFSET
2252 #define DDRC_PCFGQOS0_4_OFFSET 0XFD070754
2253 #undef DDRC_PCFGQOS1_4_OFFSET
2254 #define DDRC_PCFGQOS1_4_OFFSET 0XFD070758
2255 #undef DDRC_PCFGWQOS0_4_OFFSET
2256 #define DDRC_PCFGWQOS0_4_OFFSET 0XFD07075C
2257 #undef DDRC_PCFGWQOS1_4_OFFSET
2258 #define DDRC_PCFGWQOS1_4_OFFSET 0XFD070760
2259 #undef DDRC_PCFGR_5_OFFSET
2260 #define DDRC_PCFGR_5_OFFSET 0XFD070774
2261 #undef DDRC_PCFGW_5_OFFSET
2262 #define DDRC_PCFGW_5_OFFSET 0XFD070778
2263 #undef DDRC_PCTRL_5_OFFSET
2264 #define DDRC_PCTRL_5_OFFSET 0XFD070800
2265 #undef DDRC_PCFGQOS0_5_OFFSET
2266 #define DDRC_PCFGQOS0_5_OFFSET 0XFD070804
2267 #undef DDRC_PCFGQOS1_5_OFFSET
2268 #define DDRC_PCFGQOS1_5_OFFSET 0XFD070808
2269 #undef DDRC_PCFGWQOS0_5_OFFSET
2270 #define DDRC_PCFGWQOS0_5_OFFSET 0XFD07080C
2271 #undef DDRC_PCFGWQOS1_5_OFFSET
2272 #define DDRC_PCFGWQOS1_5_OFFSET 0XFD070810
2273 #undef DDRC_SARBASE0_OFFSET
2274 #define DDRC_SARBASE0_OFFSET 0XFD070F04
2275 #undef DDRC_SARSIZE0_OFFSET
2276 #define DDRC_SARSIZE0_OFFSET 0XFD070F08
2277 #undef DDRC_SARBASE1_OFFSET
2278 #define DDRC_SARBASE1_OFFSET 0XFD070F0C
2279 #undef DDRC_SARSIZE1_OFFSET
2280 #define DDRC_SARSIZE1_OFFSET 0XFD070F10
2281 #undef DDRC_DFITMG0_SHADOW_OFFSET
2282 #define DDRC_DFITMG0_SHADOW_OFFSET 0XFD072190
2283 #undef CRF_APB_RST_DDR_SS_OFFSET
2284 #define CRF_APB_RST_DDR_SS_OFFSET 0XFD1A0108
2285 #undef DDR_PHY_PGCR0_OFFSET
2286 #define DDR_PHY_PGCR0_OFFSET 0XFD080010
2287 #undef DDR_PHY_PGCR2_OFFSET
2288 #define DDR_PHY_PGCR2_OFFSET 0XFD080018
2289 #undef DDR_PHY_PGCR3_OFFSET
2290 #define DDR_PHY_PGCR3_OFFSET 0XFD08001C
2291 #undef DDR_PHY_PGCR5_OFFSET
2292 #define DDR_PHY_PGCR5_OFFSET 0XFD080024
2293 #undef DDR_PHY_PTR0_OFFSET
2294 #define DDR_PHY_PTR0_OFFSET 0XFD080040
2295 #undef DDR_PHY_PTR1_OFFSET
2296 #define DDR_PHY_PTR1_OFFSET 0XFD080044
2297 #undef DDR_PHY_DSGCR_OFFSET
2298 #define DDR_PHY_DSGCR_OFFSET 0XFD080090
2299 #undef DDR_PHY_DCR_OFFSET
2300 #define DDR_PHY_DCR_OFFSET 0XFD080100
2301 #undef DDR_PHY_DTPR0_OFFSET
2302 #define DDR_PHY_DTPR0_OFFSET 0XFD080110
2303 #undef DDR_PHY_DTPR1_OFFSET
2304 #define DDR_PHY_DTPR1_OFFSET 0XFD080114
2305 #undef DDR_PHY_DTPR2_OFFSET
2306 #define DDR_PHY_DTPR2_OFFSET 0XFD080118
2307 #undef DDR_PHY_DTPR3_OFFSET
2308 #define DDR_PHY_DTPR3_OFFSET 0XFD08011C
2309 #undef DDR_PHY_DTPR4_OFFSET
2310 #define DDR_PHY_DTPR4_OFFSET 0XFD080120
2311 #undef DDR_PHY_DTPR5_OFFSET
2312 #define DDR_PHY_DTPR5_OFFSET 0XFD080124
2313 #undef DDR_PHY_DTPR6_OFFSET
2314 #define DDR_PHY_DTPR6_OFFSET 0XFD080128
2315 #undef DDR_PHY_RDIMMGCR0_OFFSET
2316 #define DDR_PHY_RDIMMGCR0_OFFSET 0XFD080140
2317 #undef DDR_PHY_RDIMMGCR1_OFFSET
2318 #define DDR_PHY_RDIMMGCR1_OFFSET 0XFD080144
2319 #undef DDR_PHY_RDIMMCR0_OFFSET
2320 #define DDR_PHY_RDIMMCR0_OFFSET 0XFD080150
2321 #undef DDR_PHY_RDIMMCR1_OFFSET
2322 #define DDR_PHY_RDIMMCR1_OFFSET 0XFD080154
2323 #undef DDR_PHY_MR0_OFFSET
2324 #define DDR_PHY_MR0_OFFSET 0XFD080180
2325 #undef DDR_PHY_MR1_OFFSET
2326 #define DDR_PHY_MR1_OFFSET 0XFD080184
2327 #undef DDR_PHY_MR2_OFFSET
2328 #define DDR_PHY_MR2_OFFSET 0XFD080188
2329 #undef DDR_PHY_MR3_OFFSET
2330 #define DDR_PHY_MR3_OFFSET 0XFD08018C
2331 #undef DDR_PHY_MR4_OFFSET
2332 #define DDR_PHY_MR4_OFFSET 0XFD080190
2333 #undef DDR_PHY_MR5_OFFSET
2334 #define DDR_PHY_MR5_OFFSET 0XFD080194
2335 #undef DDR_PHY_MR6_OFFSET
2336 #define DDR_PHY_MR6_OFFSET 0XFD080198
2337 #undef DDR_PHY_MR11_OFFSET
2338 #define DDR_PHY_MR11_OFFSET 0XFD0801AC
2339 #undef DDR_PHY_MR12_OFFSET
2340 #define DDR_PHY_MR12_OFFSET 0XFD0801B0
2341 #undef DDR_PHY_MR13_OFFSET
2342 #define DDR_PHY_MR13_OFFSET 0XFD0801B4
2343 #undef DDR_PHY_MR14_OFFSET
2344 #define DDR_PHY_MR14_OFFSET 0XFD0801B8
2345 #undef DDR_PHY_MR22_OFFSET
2346 #define DDR_PHY_MR22_OFFSET 0XFD0801D8
2347 #undef DDR_PHY_DTCR0_OFFSET
2348 #define DDR_PHY_DTCR0_OFFSET 0XFD080200
2349 #undef DDR_PHY_DTCR1_OFFSET
2350 #define DDR_PHY_DTCR1_OFFSET 0XFD080204
2351 #undef DDR_PHY_CATR0_OFFSET
2352 #define DDR_PHY_CATR0_OFFSET 0XFD080240
2353 #undef DDR_PHY_BISTLSR_OFFSET
2354 #define DDR_PHY_BISTLSR_OFFSET 0XFD080414
2355 #undef DDR_PHY_RIOCR5_OFFSET
2356 #define DDR_PHY_RIOCR5_OFFSET 0XFD0804F4
2357 #undef DDR_PHY_ACIOCR0_OFFSET
2358 #define DDR_PHY_ACIOCR0_OFFSET 0XFD080500
2359 #undef DDR_PHY_ACIOCR2_OFFSET
2360 #define DDR_PHY_ACIOCR2_OFFSET 0XFD080508
2361 #undef DDR_PHY_ACIOCR3_OFFSET
2362 #define DDR_PHY_ACIOCR3_OFFSET 0XFD08050C
2363 #undef DDR_PHY_ACIOCR4_OFFSET
2364 #define DDR_PHY_ACIOCR4_OFFSET 0XFD080510
2365 #undef DDR_PHY_IOVCR0_OFFSET
2366 #define DDR_PHY_IOVCR0_OFFSET 0XFD080520
2367 #undef DDR_PHY_VTCR0_OFFSET
2368 #define DDR_PHY_VTCR0_OFFSET 0XFD080528
2369 #undef DDR_PHY_VTCR1_OFFSET
2370 #define DDR_PHY_VTCR1_OFFSET 0XFD08052C
2371 #undef DDR_PHY_ACBDLR1_OFFSET
2372 #define DDR_PHY_ACBDLR1_OFFSET 0XFD080544
2373 #undef DDR_PHY_ACBDLR2_OFFSET
2374 #define DDR_PHY_ACBDLR2_OFFSET 0XFD080548
2375 #undef DDR_PHY_ACBDLR6_OFFSET
2376 #define DDR_PHY_ACBDLR6_OFFSET 0XFD080558
2377 #undef DDR_PHY_ACBDLR7_OFFSET
2378 #define DDR_PHY_ACBDLR7_OFFSET 0XFD08055C
2379 #undef DDR_PHY_ACBDLR8_OFFSET
2380 #define DDR_PHY_ACBDLR8_OFFSET 0XFD080560
2381 #undef DDR_PHY_ACBDLR9_OFFSET
2382 #define DDR_PHY_ACBDLR9_OFFSET 0XFD080564
2383 #undef DDR_PHY_ZQCR_OFFSET
2384 #define DDR_PHY_ZQCR_OFFSET 0XFD080680
2385 #undef DDR_PHY_ZQ0PR0_OFFSET
2386 #define DDR_PHY_ZQ0PR0_OFFSET 0XFD080684
2387 #undef DDR_PHY_ZQ0OR0_OFFSET
2388 #define DDR_PHY_ZQ0OR0_OFFSET 0XFD080694
2389 #undef DDR_PHY_ZQ0OR1_OFFSET
2390 #define DDR_PHY_ZQ0OR1_OFFSET 0XFD080698
2391 #undef DDR_PHY_ZQ1PR0_OFFSET
2392 #define DDR_PHY_ZQ1PR0_OFFSET 0XFD0806A4
2393 #undef DDR_PHY_DX0GCR0_OFFSET
2394 #define DDR_PHY_DX0GCR0_OFFSET 0XFD080700
2395 #undef DDR_PHY_DX0GCR4_OFFSET
2396 #define DDR_PHY_DX0GCR4_OFFSET 0XFD080710
2397 #undef DDR_PHY_DX0GCR5_OFFSET
2398 #define DDR_PHY_DX0GCR5_OFFSET 0XFD080714
2399 #undef DDR_PHY_DX0GCR6_OFFSET
2400 #define DDR_PHY_DX0GCR6_OFFSET 0XFD080718
2401 #undef DDR_PHY_DX0LCDLR2_OFFSET
2402 #define DDR_PHY_DX0LCDLR2_OFFSET 0XFD080788
2403 #undef DDR_PHY_DX0GTR0_OFFSET
2404 #define DDR_PHY_DX0GTR0_OFFSET 0XFD0807C0
2405 #undef DDR_PHY_DX1GCR0_OFFSET
2406 #define DDR_PHY_DX1GCR0_OFFSET 0XFD080800
2407 #undef DDR_PHY_DX1GCR4_OFFSET
2408 #define DDR_PHY_DX1GCR4_OFFSET 0XFD080810
2409 #undef DDR_PHY_DX1GCR5_OFFSET
2410 #define DDR_PHY_DX1GCR5_OFFSET 0XFD080814
2411 #undef DDR_PHY_DX1GCR6_OFFSET
2412 #define DDR_PHY_DX1GCR6_OFFSET 0XFD080818
2413 #undef DDR_PHY_DX1LCDLR2_OFFSET
2414 #define DDR_PHY_DX1LCDLR2_OFFSET 0XFD080888
2415 #undef DDR_PHY_DX1GTR0_OFFSET
2416 #define DDR_PHY_DX1GTR0_OFFSET 0XFD0808C0
2417 #undef DDR_PHY_DX2GCR0_OFFSET
2418 #define DDR_PHY_DX2GCR0_OFFSET 0XFD080900
2419 #undef DDR_PHY_DX2GCR1_OFFSET
2420 #define DDR_PHY_DX2GCR1_OFFSET 0XFD080904
2421 #undef DDR_PHY_DX2GCR4_OFFSET
2422 #define DDR_PHY_DX2GCR4_OFFSET 0XFD080910
2423 #undef DDR_PHY_DX2GCR5_OFFSET
2424 #define DDR_PHY_DX2GCR5_OFFSET 0XFD080914
2425 #undef DDR_PHY_DX2GCR6_OFFSET
2426 #define DDR_PHY_DX2GCR6_OFFSET 0XFD080918
2427 #undef DDR_PHY_DX2LCDLR2_OFFSET
2428 #define DDR_PHY_DX2LCDLR2_OFFSET 0XFD080988
2429 #undef DDR_PHY_DX2GTR0_OFFSET
2430 #define DDR_PHY_DX2GTR0_OFFSET 0XFD0809C0
2431 #undef DDR_PHY_DX3GCR0_OFFSET
2432 #define DDR_PHY_DX3GCR0_OFFSET 0XFD080A00
2433 #undef DDR_PHY_DX3GCR1_OFFSET
2434 #define DDR_PHY_DX3GCR1_OFFSET 0XFD080A04
2435 #undef DDR_PHY_DX3GCR4_OFFSET
2436 #define DDR_PHY_DX3GCR4_OFFSET 0XFD080A10
2437 #undef DDR_PHY_DX3GCR5_OFFSET
2438 #define DDR_PHY_DX3GCR5_OFFSET 0XFD080A14
2439 #undef DDR_PHY_DX3GCR6_OFFSET
2440 #define DDR_PHY_DX3GCR6_OFFSET 0XFD080A18
2441 #undef DDR_PHY_DX3LCDLR2_OFFSET
2442 #define DDR_PHY_DX3LCDLR2_OFFSET 0XFD080A88
2443 #undef DDR_PHY_DX3GTR0_OFFSET
2444 #define DDR_PHY_DX3GTR0_OFFSET 0XFD080AC0
2445 #undef DDR_PHY_DX4GCR0_OFFSET
2446 #define DDR_PHY_DX4GCR0_OFFSET 0XFD080B00
2447 #undef DDR_PHY_DX4GCR1_OFFSET
2448 #define DDR_PHY_DX4GCR1_OFFSET 0XFD080B04
2449 #undef DDR_PHY_DX4GCR4_OFFSET
2450 #define DDR_PHY_DX4GCR4_OFFSET 0XFD080B10
2451 #undef DDR_PHY_DX4GCR5_OFFSET
2452 #define DDR_PHY_DX4GCR5_OFFSET 0XFD080B14
2453 #undef DDR_PHY_DX4GCR6_OFFSET
2454 #define DDR_PHY_DX4GCR6_OFFSET 0XFD080B18
2455 #undef DDR_PHY_DX4LCDLR2_OFFSET
2456 #define DDR_PHY_DX4LCDLR2_OFFSET 0XFD080B88
2457 #undef DDR_PHY_DX4GTR0_OFFSET
2458 #define DDR_PHY_DX4GTR0_OFFSET 0XFD080BC0
2459 #undef DDR_PHY_DX5GCR0_OFFSET
2460 #define DDR_PHY_DX5GCR0_OFFSET 0XFD080C00
2461 #undef DDR_PHY_DX5GCR1_OFFSET
2462 #define DDR_PHY_DX5GCR1_OFFSET 0XFD080C04
2463 #undef DDR_PHY_DX5GCR4_OFFSET
2464 #define DDR_PHY_DX5GCR4_OFFSET 0XFD080C10
2465 #undef DDR_PHY_DX5GCR5_OFFSET
2466 #define DDR_PHY_DX5GCR5_OFFSET 0XFD080C14
2467 #undef DDR_PHY_DX5GCR6_OFFSET
2468 #define DDR_PHY_DX5GCR6_OFFSET 0XFD080C18
2469 #undef DDR_PHY_DX5LCDLR2_OFFSET
2470 #define DDR_PHY_DX5LCDLR2_OFFSET 0XFD080C88
2471 #undef DDR_PHY_DX5GTR0_OFFSET
2472 #define DDR_PHY_DX5GTR0_OFFSET 0XFD080CC0
2473 #undef DDR_PHY_DX6GCR0_OFFSET
2474 #define DDR_PHY_DX6GCR0_OFFSET 0XFD080D00
2475 #undef DDR_PHY_DX6GCR1_OFFSET
2476 #define DDR_PHY_DX6GCR1_OFFSET 0XFD080D04
2477 #undef DDR_PHY_DX6GCR4_OFFSET
2478 #define DDR_PHY_DX6GCR4_OFFSET 0XFD080D10
2479 #undef DDR_PHY_DX6GCR5_OFFSET
2480 #define DDR_PHY_DX6GCR5_OFFSET 0XFD080D14
2481 #undef DDR_PHY_DX6GCR6_OFFSET
2482 #define DDR_PHY_DX6GCR6_OFFSET 0XFD080D18
2483 #undef DDR_PHY_DX6LCDLR2_OFFSET
2484 #define DDR_PHY_DX6LCDLR2_OFFSET 0XFD080D88
2485 #undef DDR_PHY_DX6GTR0_OFFSET
2486 #define DDR_PHY_DX6GTR0_OFFSET 0XFD080DC0
2487 #undef DDR_PHY_DX7GCR0_OFFSET
2488 #define DDR_PHY_DX7GCR0_OFFSET 0XFD080E00
2489 #undef DDR_PHY_DX7GCR1_OFFSET
2490 #define DDR_PHY_DX7GCR1_OFFSET 0XFD080E04
2491 #undef DDR_PHY_DX7GCR4_OFFSET
2492 #define DDR_PHY_DX7GCR4_OFFSET 0XFD080E10
2493 #undef DDR_PHY_DX7GCR5_OFFSET
2494 #define DDR_PHY_DX7GCR5_OFFSET 0XFD080E14
2495 #undef DDR_PHY_DX7GCR6_OFFSET
2496 #define DDR_PHY_DX7GCR6_OFFSET 0XFD080E18
2497 #undef DDR_PHY_DX7LCDLR2_OFFSET
2498 #define DDR_PHY_DX7LCDLR2_OFFSET 0XFD080E88
2499 #undef DDR_PHY_DX7GTR0_OFFSET
2500 #define DDR_PHY_DX7GTR0_OFFSET 0XFD080EC0
2501 #undef DDR_PHY_DX8GCR0_OFFSET
2502 #define DDR_PHY_DX8GCR0_OFFSET 0XFD080F00
2503 #undef DDR_PHY_DX8GCR1_OFFSET
2504 #define DDR_PHY_DX8GCR1_OFFSET 0XFD080F04
2505 #undef DDR_PHY_DX8GCR4_OFFSET
2506 #define DDR_PHY_DX8GCR4_OFFSET 0XFD080F10
2507 #undef DDR_PHY_DX8GCR5_OFFSET
2508 #define DDR_PHY_DX8GCR5_OFFSET 0XFD080F14
2509 #undef DDR_PHY_DX8GCR6_OFFSET
2510 #define DDR_PHY_DX8GCR6_OFFSET 0XFD080F18
2511 #undef DDR_PHY_DX8LCDLR2_OFFSET
2512 #define DDR_PHY_DX8LCDLR2_OFFSET 0XFD080F88
2513 #undef DDR_PHY_DX8GTR0_OFFSET
2514 #define DDR_PHY_DX8GTR0_OFFSET 0XFD080FC0
2515 #undef DDR_PHY_DX8SL0OSC_OFFSET
2516 #define DDR_PHY_DX8SL0OSC_OFFSET 0XFD081400
2517 #undef DDR_PHY_DX8SL0DQSCTL_OFFSET
2518 #define DDR_PHY_DX8SL0DQSCTL_OFFSET 0XFD08141C
2519 #undef DDR_PHY_DX8SL0DXCTL2_OFFSET
2520 #define DDR_PHY_DX8SL0DXCTL2_OFFSET 0XFD08142C
2521 #undef DDR_PHY_DX8SL0IOCR_OFFSET
2522 #define DDR_PHY_DX8SL0IOCR_OFFSET 0XFD081430
2523 #undef DDR_PHY_DX8SL1OSC_OFFSET
2524 #define DDR_PHY_DX8SL1OSC_OFFSET 0XFD081440
2525 #undef DDR_PHY_DX8SL1DQSCTL_OFFSET
2526 #define DDR_PHY_DX8SL1DQSCTL_OFFSET 0XFD08145C
2527 #undef DDR_PHY_DX8SL1DXCTL2_OFFSET
2528 #define DDR_PHY_DX8SL1DXCTL2_OFFSET 0XFD08146C
2529 #undef DDR_PHY_DX8SL1IOCR_OFFSET
2530 #define DDR_PHY_DX8SL1IOCR_OFFSET 0XFD081470
2531 #undef DDR_PHY_DX8SL2OSC_OFFSET
2532 #define DDR_PHY_DX8SL2OSC_OFFSET 0XFD081480
2533 #undef DDR_PHY_DX8SL2DQSCTL_OFFSET
2534 #define DDR_PHY_DX8SL2DQSCTL_OFFSET 0XFD08149C
2535 #undef DDR_PHY_DX8SL2DXCTL2_OFFSET
2536 #define DDR_PHY_DX8SL2DXCTL2_OFFSET 0XFD0814AC
2537 #undef DDR_PHY_DX8SL2IOCR_OFFSET
2538 #define DDR_PHY_DX8SL2IOCR_OFFSET 0XFD0814B0
2539 #undef DDR_PHY_DX8SL3OSC_OFFSET
2540 #define DDR_PHY_DX8SL3OSC_OFFSET 0XFD0814C0
2541 #undef DDR_PHY_DX8SL3DQSCTL_OFFSET
2542 #define DDR_PHY_DX8SL3DQSCTL_OFFSET 0XFD0814DC
2543 #undef DDR_PHY_DX8SL3DXCTL2_OFFSET
2544 #define DDR_PHY_DX8SL3DXCTL2_OFFSET 0XFD0814EC
2545 #undef DDR_PHY_DX8SL3IOCR_OFFSET
2546 #define DDR_PHY_DX8SL3IOCR_OFFSET 0XFD0814F0
2547 #undef DDR_PHY_DX8SL4OSC_OFFSET
2548 #define DDR_PHY_DX8SL4OSC_OFFSET 0XFD081500
2549 #undef DDR_PHY_DX8SL4DQSCTL_OFFSET
2550 #define DDR_PHY_DX8SL4DQSCTL_OFFSET 0XFD08151C
2551 #undef DDR_PHY_DX8SL4DXCTL2_OFFSET
2552 #define DDR_PHY_DX8SL4DXCTL2_OFFSET 0XFD08152C
2553 #undef DDR_PHY_DX8SL4IOCR_OFFSET
2554 #define DDR_PHY_DX8SL4IOCR_OFFSET 0XFD081530
2555 #undef DDR_PHY_DX8SLBDQSCTL_OFFSET
2556 #define DDR_PHY_DX8SLBDQSCTL_OFFSET 0XFD0817DC
2557 #undef DDR_PHY_PIR_OFFSET
2558 #define DDR_PHY_PIR_OFFSET 0XFD080004
2560 /*DDR block level reset inside of the DDR Sub System*/
2561 #undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL
2562 #undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT
2563 #undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK
2564 #define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F
2565 #define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3
2566 #define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U
2568 /*Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32
2570 #undef DDRC_MSTR_DEVICE_CONFIG_DEFVAL
2571 #undef DDRC_MSTR_DEVICE_CONFIG_SHIFT
2572 #undef DDRC_MSTR_DEVICE_CONFIG_MASK
2573 #define DDRC_MSTR_DEVICE_CONFIG_DEFVAL 0x03040001
2574 #define DDRC_MSTR_DEVICE_CONFIG_SHIFT 30
2575 #define DDRC_MSTR_DEVICE_CONFIG_MASK 0xC0000000U
2577 /*Choose which registers are used. - 0 - Original registers - 1 - Shadow registers*/
2578 #undef DDRC_MSTR_FREQUENCY_MODE_DEFVAL
2579 #undef DDRC_MSTR_FREQUENCY_MODE_SHIFT
2580 #undef DDRC_MSTR_FREQUENCY_MODE_MASK
2581 #define DDRC_MSTR_FREQUENCY_MODE_DEFVAL 0x03040001
2582 #define DDRC_MSTR_FREQUENCY_MODE_SHIFT 29
2583 #define DDRC_MSTR_FREQUENCY_MODE_MASK 0x20000000U
2585 /*Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p
2586 esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 -
2587 ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra
2588 ks - 1111 - Four ranks*/
2589 #undef DDRC_MSTR_ACTIVE_RANKS_DEFVAL
2590 #undef DDRC_MSTR_ACTIVE_RANKS_SHIFT
2591 #undef DDRC_MSTR_ACTIVE_RANKS_MASK
2592 #define DDRC_MSTR_ACTIVE_RANKS_DEFVAL 0x03040001
2593 #define DDRC_MSTR_ACTIVE_RANKS_SHIFT 24
2594 #define DDRC_MSTR_ACTIVE_RANKS_MASK 0x03000000U
2596 /*SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt
2597 of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls
2598 he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th
2599 -fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT
2600 is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1*/
2601 #undef DDRC_MSTR_BURST_RDWR_DEFVAL
2602 #undef DDRC_MSTR_BURST_RDWR_SHIFT
2603 #undef DDRC_MSTR_BURST_RDWR_MASK
2604 #define DDRC_MSTR_BURST_RDWR_DEFVAL 0x03040001
2605 #define DDRC_MSTR_BURST_RDWR_SHIFT 16
2606 #define DDRC_MSTR_BURST_RDWR_MASK 0x000F0000U
2608 /*Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM
2609 n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d
2610 l_off_mode is not supported, and this bit must be set to '0'.*/
2611 #undef DDRC_MSTR_DLL_OFF_MODE_DEFVAL
2612 #undef DDRC_MSTR_DLL_OFF_MODE_SHIFT
2613 #undef DDRC_MSTR_DLL_OFF_MODE_MASK
2614 #define DDRC_MSTR_DLL_OFF_MODE_DEFVAL 0x03040001
2615 #define DDRC_MSTR_DLL_OFF_MODE_SHIFT 15
2616 #define DDRC_MSTR_DLL_OFF_MODE_MASK 0x00008000U
2618 /*Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD
2619 AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w
2620 dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co
2621 figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width).*/
2622 #undef DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL
2623 #undef DDRC_MSTR_DATA_BUS_WIDTH_SHIFT
2624 #undef DDRC_MSTR_DATA_BUS_WIDTH_MASK
2625 #define DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL 0x03040001
2626 #define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 12
2627 #define DDRC_MSTR_DATA_BUS_WIDTH_MASK 0x00003000U
2629 /*1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed
2630 only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode
2631 s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set*/
2632 #undef DDRC_MSTR_GEARDOWN_MODE_DEFVAL
2633 #undef DDRC_MSTR_GEARDOWN_MODE_SHIFT
2634 #undef DDRC_MSTR_GEARDOWN_MODE_MASK
2635 #define DDRC_MSTR_GEARDOWN_MODE_DEFVAL 0x03040001
2636 #define DDRC_MSTR_GEARDOWN_MODE_SHIFT 11
2637 #define DDRC_MSTR_GEARDOWN_MODE_MASK 0x00000800U
2639 /*If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held
2640 or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in
2641 PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti
2642 ing is not supported in DDR4 geardown mode.*/
2643 #undef DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL
2644 #undef DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT
2645 #undef DDRC_MSTR_EN_2T_TIMING_MODE_MASK
2646 #define DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL 0x03040001
2647 #define DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT 10
2648 #define DDRC_MSTR_EN_2T_TIMING_MODE_MASK 0x00000400U
2650 /*When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s
2651 t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable
2652 (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr
2653 _parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0'*/
2654 #undef DDRC_MSTR_BURSTCHOP_DEFVAL
2655 #undef DDRC_MSTR_BURSTCHOP_SHIFT
2656 #undef DDRC_MSTR_BURSTCHOP_MASK
2657 #define DDRC_MSTR_BURSTCHOP_DEFVAL 0x03040001
2658 #define DDRC_MSTR_BURSTCHOP_SHIFT 9
2659 #define DDRC_MSTR_BURSTCHOP_MASK 0x00000200U
2661 /*Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su
2663 #undef DDRC_MSTR_LPDDR4_DEFVAL
2664 #undef DDRC_MSTR_LPDDR4_SHIFT
2665 #undef DDRC_MSTR_LPDDR4_MASK
2666 #define DDRC_MSTR_LPDDR4_DEFVAL 0x03040001
2667 #define DDRC_MSTR_LPDDR4_SHIFT 5
2668 #define DDRC_MSTR_LPDDR4_MASK 0x00000020U
2670 /*Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support
2672 #undef DDRC_MSTR_DDR4_DEFVAL
2673 #undef DDRC_MSTR_DDR4_SHIFT
2674 #undef DDRC_MSTR_DDR4_MASK
2675 #define DDRC_MSTR_DDR4_DEFVAL 0x03040001
2676 #define DDRC_MSTR_DDR4_SHIFT 4
2677 #define DDRC_MSTR_DDR4_MASK 0x00000010U
2679 /*Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su
2681 #undef DDRC_MSTR_LPDDR3_DEFVAL
2682 #undef DDRC_MSTR_LPDDR3_SHIFT
2683 #undef DDRC_MSTR_LPDDR3_MASK
2684 #define DDRC_MSTR_LPDDR3_DEFVAL 0x03040001
2685 #define DDRC_MSTR_LPDDR3_SHIFT 3
2686 #define DDRC_MSTR_LPDDR3_MASK 0x00000008U
2688 /*Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su
2690 #undef DDRC_MSTR_LPDDR2_DEFVAL
2691 #undef DDRC_MSTR_LPDDR2_SHIFT
2692 #undef DDRC_MSTR_LPDDR2_MASK
2693 #define DDRC_MSTR_LPDDR2_DEFVAL 0x03040001
2694 #define DDRC_MSTR_LPDDR2_SHIFT 2
2695 #define DDRC_MSTR_LPDDR2_MASK 0x00000004U
2697 /*Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3
2699 #undef DDRC_MSTR_DDR3_DEFVAL
2700 #undef DDRC_MSTR_DDR3_SHIFT
2701 #undef DDRC_MSTR_DDR3_MASK
2702 #define DDRC_MSTR_DDR3_DEFVAL 0x03040001
2703 #define DDRC_MSTR_DDR3_SHIFT 0
2704 #define DDRC_MSTR_DDR3_MASK 0x00000001U
2706 /*Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL
2707 automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef
2708 re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.*/
2709 #undef DDRC_MRCTRL0_MR_WR_DEFVAL
2710 #undef DDRC_MRCTRL0_MR_WR_SHIFT
2711 #undef DDRC_MRCTRL0_MR_WR_MASK
2712 #define DDRC_MRCTRL0_MR_WR_DEFVAL 0x00000030
2713 #define DDRC_MRCTRL0_MR_WR_SHIFT 31
2714 #define DDRC_MRCTRL0_MR_WR_MASK 0x80000000U
2716 /*Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010
2717 - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD
2718 R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a
2719 dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well
2720 s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou
2721 put Inversion of RDIMMs.*/
2722 #undef DDRC_MRCTRL0_MR_ADDR_DEFVAL
2723 #undef DDRC_MRCTRL0_MR_ADDR_SHIFT
2724 #undef DDRC_MRCTRL0_MR_ADDR_MASK
2725 #define DDRC_MRCTRL0_MR_ADDR_DEFVAL 0x00000030
2726 #define DDRC_MRCTRL0_MR_ADDR_SHIFT 12
2727 #define DDRC_MRCTRL0_MR_ADDR_MASK 0x0000F000U
2729 /*Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1
2730 However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E
2731 amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks
2732 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3*/
2733 #undef DDRC_MRCTRL0_MR_RANK_DEFVAL
2734 #undef DDRC_MRCTRL0_MR_RANK_SHIFT
2735 #undef DDRC_MRCTRL0_MR_RANK_MASK
2736 #define DDRC_MRCTRL0_MR_RANK_DEFVAL 0x00000030
2737 #define DDRC_MRCTRL0_MR_RANK_SHIFT 4
2738 #define DDRC_MRCTRL0_MR_RANK_MASK 0x00000030U
2740 /*Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not.
2741 or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca
2742 be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared
2743 o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi
2744 n is not allowed - 1 - Software intervention is allowed*/
2745 #undef DDRC_MRCTRL0_SW_INIT_INT_DEFVAL
2746 #undef DDRC_MRCTRL0_SW_INIT_INT_SHIFT
2747 #undef DDRC_MRCTRL0_SW_INIT_INT_MASK
2748 #define DDRC_MRCTRL0_SW_INIT_INT_DEFVAL 0x00000030
2749 #define DDRC_MRCTRL0_SW_INIT_INT_SHIFT 3
2750 #define DDRC_MRCTRL0_SW_INIT_INT_MASK 0x00000008U
2752 /*Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode*/
2753 #undef DDRC_MRCTRL0_PDA_EN_DEFVAL
2754 #undef DDRC_MRCTRL0_PDA_EN_SHIFT
2755 #undef DDRC_MRCTRL0_PDA_EN_MASK
2756 #define DDRC_MRCTRL0_PDA_EN_DEFVAL 0x00000030
2757 #define DDRC_MRCTRL0_PDA_EN_SHIFT 2
2758 #define DDRC_MRCTRL0_PDA_EN_MASK 0x00000004U
2760 /*Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR*/
2761 #undef DDRC_MRCTRL0_MPR_EN_DEFVAL
2762 #undef DDRC_MRCTRL0_MPR_EN_SHIFT
2763 #undef DDRC_MRCTRL0_MPR_EN_MASK
2764 #define DDRC_MRCTRL0_MPR_EN_DEFVAL 0x00000030
2765 #define DDRC_MRCTRL0_MPR_EN_SHIFT 1
2766 #define DDRC_MRCTRL0_MPR_EN_MASK 0x00000002U
2768 /*Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re
2770 #undef DDRC_MRCTRL0_MR_TYPE_DEFVAL
2771 #undef DDRC_MRCTRL0_MR_TYPE_SHIFT
2772 #undef DDRC_MRCTRL0_MR_TYPE_MASK
2773 #define DDRC_MRCTRL0_MR_TYPE_DEFVAL 0x00000030
2774 #define DDRC_MRCTRL0_MR_TYPE_SHIFT 0
2775 #define DDRC_MRCTRL0_MR_TYPE_MASK 0x00000001U
2777 /*Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4
2778 Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi
2779 g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer.*/
2780 #undef DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL
2781 #undef DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT
2782 #undef DDRC_DERATEEN_RC_DERATE_VALUE_MASK
2783 #define DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL 0x00000000
2784 #define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT 8
2785 #define DDRC_DERATEEN_RC_DERATE_VALUE_MASK 0x00000300U
2787 /*Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f
2788 r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.*/
2789 #undef DDRC_DERATEEN_DERATE_BYTE_DEFVAL
2790 #undef DDRC_DERATEEN_DERATE_BYTE_SHIFT
2791 #undef DDRC_DERATEEN_DERATE_BYTE_MASK
2792 #define DDRC_DERATEEN_DERATE_BYTE_DEFVAL 0x00000000
2793 #define DDRC_DERATEEN_DERATE_BYTE_SHIFT 4
2794 #define DDRC_DERATEEN_DERATE_BYTE_MASK 0x000000F0U
2796 /*Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD
2797 4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1
2798 for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not.*/
2799 #undef DDRC_DERATEEN_DERATE_VALUE_DEFVAL
2800 #undef DDRC_DERATEEN_DERATE_VALUE_SHIFT
2801 #undef DDRC_DERATEEN_DERATE_VALUE_MASK
2802 #define DDRC_DERATEEN_DERATE_VALUE_DEFVAL 0x00000000
2803 #define DDRC_DERATEEN_DERATE_VALUE_SHIFT 1
2804 #define DDRC_DERATEEN_DERATE_VALUE_MASK 0x00000002U
2806 /*Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value.
2807 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4
2809 #undef DDRC_DERATEEN_DERATE_ENABLE_DEFVAL
2810 #undef DDRC_DERATEEN_DERATE_ENABLE_SHIFT
2811 #undef DDRC_DERATEEN_DERATE_ENABLE_MASK
2812 #define DDRC_DERATEEN_DERATE_ENABLE_DEFVAL 0x00000000
2813 #define DDRC_DERATEEN_DERATE_ENABLE_SHIFT 0
2814 #define DDRC_DERATEEN_DERATE_ENABLE_MASK 0x00000001U
2816 /*Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP
2817 DR3/LPDDR4. This register must not be set to zero*/
2818 #undef DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL
2819 #undef DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT
2820 #undef DDRC_DERATEINT_MR4_READ_INTERVAL_MASK
2821 #define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL
2822 #define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 0
2823 #define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 0xFFFFFFFFU
2825 /*Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f
2826 r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state -
2827 - Allow transition from Self refresh state*/
2828 #undef DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL
2829 #undef DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT
2830 #undef DDRC_PWRCTL_STAY_IN_SELFREF_MASK
2831 #define DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL 0x00000000
2832 #define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT 6
2833 #define DDRC_PWRCTL_STAY_IN_SELFREF_MASK 0x00000040U
2835 /*A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP
2836 M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft
2837 are Exit from Self Refresh*/
2838 #undef DDRC_PWRCTL_SELFREF_SW_DEFVAL
2839 #undef DDRC_PWRCTL_SELFREF_SW_SHIFT
2840 #undef DDRC_PWRCTL_SELFREF_SW_MASK
2841 #define DDRC_PWRCTL_SELFREF_SW_DEFVAL 0x00000000
2842 #define DDRC_PWRCTL_SELFREF_SW_SHIFT 5
2843 #define DDRC_PWRCTL_SELFREF_SW_MASK 0x00000020U
2845 /*When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m
2846 st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For
2847 on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter
2848 DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY.*/
2849 #undef DDRC_PWRCTL_MPSM_EN_DEFVAL
2850 #undef DDRC_PWRCTL_MPSM_EN_SHIFT
2851 #undef DDRC_PWRCTL_MPSM_EN_MASK
2852 #define DDRC_PWRCTL_MPSM_EN_DEFVAL 0x00000000
2853 #define DDRC_PWRCTL_MPSM_EN_SHIFT 4
2854 #define DDRC_PWRCTL_MPSM_EN_MASK 0x00000010U
2856 /*Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable
2857 is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD
2858 4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in
2859 ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass
2860 rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop)*/
2861 #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL
2862 #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT
2863 #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK
2864 #define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL 0x00000000
2865 #define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 3
2866 #define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 0x00000008U
2868 /*When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re
2869 et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down
2870 xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe
2871 should not be set to 1. FOR PERFORMANCE ONLY.*/
2872 #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL
2873 #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT
2874 #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK
2875 #define DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL 0x00000000
2876 #define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT 2
2877 #define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK 0x00000004U
2879 /*If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P
2880 RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation.*/
2881 #undef DDRC_PWRCTL_POWERDOWN_EN_DEFVAL
2882 #undef DDRC_PWRCTL_POWERDOWN_EN_SHIFT
2883 #undef DDRC_PWRCTL_POWERDOWN_EN_MASK
2884 #define DDRC_PWRCTL_POWERDOWN_EN_DEFVAL 0x00000000
2885 #define DDRC_PWRCTL_POWERDOWN_EN_SHIFT 1
2886 #define DDRC_PWRCTL_POWERDOWN_EN_MASK 0x00000002U
2888 /*If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se
2889 f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation.*/
2890 #undef DDRC_PWRCTL_SELFREF_EN_DEFVAL
2891 #undef DDRC_PWRCTL_SELFREF_EN_SHIFT
2892 #undef DDRC_PWRCTL_SELFREF_EN_MASK
2893 #define DDRC_PWRCTL_SELFREF_EN_DEFVAL 0x00000000
2894 #define DDRC_PWRCTL_SELFREF_EN_SHIFT 0
2895 #define DDRC_PWRCTL_SELFREF_EN_MASK 0x00000001U
2897 /*After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in
2898 he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.*/
2899 #undef DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL
2900 #undef DDRC_PWRTMG_SELFREF_TO_X32_SHIFT
2901 #undef DDRC_PWRTMG_SELFREF_TO_X32_MASK
2902 #define DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL 0x00402010
2903 #define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT 16
2904 #define DDRC_PWRTMG_SELFREF_TO_X32_MASK 0x00FF0000U
2906 /*Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed
2907 ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul
2908 iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY.*/
2909 #undef DDRC_PWRTMG_T_DPD_X4096_DEFVAL
2910 #undef DDRC_PWRTMG_T_DPD_X4096_SHIFT
2911 #undef DDRC_PWRTMG_T_DPD_X4096_MASK
2912 #define DDRC_PWRTMG_T_DPD_X4096_DEFVAL 0x00402010
2913 #define DDRC_PWRTMG_T_DPD_X4096_SHIFT 8
2914 #define DDRC_PWRTMG_T_DPD_X4096_MASK 0x0000FF00U
2916 /*After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th
2917 PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.*/
2918 #undef DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL
2919 #undef DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT
2920 #undef DDRC_PWRTMG_POWERDOWN_TO_X32_MASK
2921 #define DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL 0x00402010
2922 #define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT 0
2923 #define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK 0x0000001FU
2925 /*Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu
2926 d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2
2927 It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32
2928 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_
2929 om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks.*/
2930 #undef DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL
2931 #undef DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT
2932 #undef DDRC_RFSHCTL0_REFRESH_MARGIN_MASK
2933 #define DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL 0x00210000
2934 #define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT 20
2935 #define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK 0x00F00000U
2937 /*If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst
2938 1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres
2939 would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF
2940 HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe
2941 formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is
2942 ued to the uMCTL2. FOR PERFORMANCE ONLY.*/
2943 #undef DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL
2944 #undef DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT
2945 #undef DDRC_RFSHCTL0_REFRESH_TO_X32_MASK
2946 #define DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL 0x00210000
2947 #define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT 12
2948 #define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK 0x0001F000U
2950 /*The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re
2951 reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re
2952 reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for
2953 RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe
2954 . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se
2955 tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r
2956 fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea
2957 ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd
2958 tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat
2959 d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY
2960 initiated update is complete.*/
2961 #undef DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL
2962 #undef DDRC_RFSHCTL0_REFRESH_BURST_SHIFT
2963 #undef DDRC_RFSHCTL0_REFRESH_BURST_MASK
2964 #define DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL 0x00210000
2965 #define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT 4
2966 #define DDRC_RFSHCTL0_REFRESH_BURST_MASK 0x000001F0U
2968 /*- 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n
2969 t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to
2970 support LPDDR2/LPDDR3/LPDDR4*/
2971 #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL
2972 #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT
2973 #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK
2974 #define DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL 0x00210000
2975 #define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT 2
2976 #define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK 0x00000004U
2978 /*Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (
2979 ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup
2980 orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in
2981 self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in
2982 uture version of the uMCTL2.*/
2983 #undef DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL
2984 #undef DDRC_RFSHCTL3_REFRESH_MODE_SHIFT
2985 #undef DDRC_RFSHCTL3_REFRESH_MODE_MASK
2986 #define DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL 0x00000000
2987 #define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT 4
2988 #define DDRC_RFSHCTL3_REFRESH_MODE_MASK 0x00000070U
2990 /*Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value
2991 s automatically updated when exiting reset, so it does not need to be toggled initially.*/
2992 #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL
2993 #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT
2994 #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK
2995 #define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL 0x00000000
2996 #define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 1
2997 #define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK 0x00000002U
2999 /*When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u
3000 ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis
3001 auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry
3002 is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'.
3003 his register field is changeable on the fly.*/
3004 #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL
3005 #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT
3006 #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK
3007 #define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL 0x00000000
3008 #define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT 0
3009 #define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK 0x00000001U
3011 /*tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio
3012 for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0
3013 , this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should
3014 e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va
3015 ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value
3016 programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS
3017 TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks.*/
3018 #undef DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL
3019 #undef DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT
3020 #undef DDRC_RFSHTMG_T_RFC_NOM_X32_MASK
3021 #define DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL 0x0062008C
3022 #define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 16
3023 #define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK 0x0FFF0000U
3025 /*Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the
3026 REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not
3027 - 0 - tREFBW parameter not used - 1 - tREFBW parameter used*/
3028 #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL
3029 #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT
3030 #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK
3031 #define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL 0x0062008C
3032 #define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT 15
3033 #define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK 0x00008000U
3035 /*tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t
3036 RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L
3037 DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin
3038 per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above
3039 equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app
3040 opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks.*/
3041 #undef DDRC_RFSHTMG_T_RFC_MIN_DEFVAL
3042 #undef DDRC_RFSHTMG_T_RFC_MIN_SHIFT
3043 #undef DDRC_RFSHTMG_T_RFC_MIN_MASK
3044 #define DDRC_RFSHTMG_T_RFC_MIN_DEFVAL 0x0062008C
3045 #define DDRC_RFSHTMG_T_RFC_MIN_SHIFT 0
3046 #define DDRC_RFSHTMG_T_RFC_MIN_MASK 0x000003FFU
3048 /*Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined*/
3049 #undef DDRC_ECCCFG0_DIS_SCRUB_DEFVAL
3050 #undef DDRC_ECCCFG0_DIS_SCRUB_SHIFT
3051 #undef DDRC_ECCCFG0_DIS_SCRUB_MASK
3052 #define DDRC_ECCCFG0_DIS_SCRUB_DEFVAL 0x00000000
3053 #define DDRC_ECCCFG0_DIS_SCRUB_SHIFT 4
3054 #define DDRC_ECCCFG0_DIS_SCRUB_MASK 0x00000010U
3056 /*ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur
3058 #undef DDRC_ECCCFG0_ECC_MODE_DEFVAL
3059 #undef DDRC_ECCCFG0_ECC_MODE_SHIFT
3060 #undef DDRC_ECCCFG0_ECC_MODE_MASK
3061 #define DDRC_ECCCFG0_ECC_MODE_DEFVAL 0x00000000
3062 #define DDRC_ECCCFG0_ECC_MODE_SHIFT 0
3063 #define DDRC_ECCCFG0_ECC_MODE_MASK 0x00000007U
3065 /*Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison
3066 ng, if ECCCFG1.data_poison_en=1*/
3067 #undef DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL
3068 #undef DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT
3069 #undef DDRC_ECCCFG1_DATA_POISON_BIT_MASK
3070 #define DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL 0x00000000
3071 #define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT 1
3072 #define DDRC_ECCCFG1_DATA_POISON_BIT_MASK 0x00000002U
3074 /*Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers*/
3075 #undef DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL
3076 #undef DDRC_ECCCFG1_DATA_POISON_EN_SHIFT
3077 #undef DDRC_ECCCFG1_DATA_POISON_EN_MASK
3078 #define DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL 0x00000000
3079 #define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT 0
3080 #define DDRC_ECCCFG1_DATA_POISON_EN_MASK 0x00000001U
3082 /*The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of
3083 the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY
3084 pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC
3085 L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_
3086 dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo
3087 e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks*/
3088 #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL
3089 #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT
3090 #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK
3091 #define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL 0x10000200
3092 #define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT 24
3093 #define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK 0x3F000000U
3095 /*After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR
3096 M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins
3097 the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin
3098 the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P
3099 RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte
3100 handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P
3101 rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re
3102 ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in
3103 he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is
3104 one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in
3105 PR Page 1 should be treated as 'Don't care'.*/
3106 #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL
3107 #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT
3108 #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK
3109 #define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL 0x10000200
3110 #define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT 9
3111 #define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK 0x00000200U
3113 /*- 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o
3114 CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o
3115 disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1)*/
3116 #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL
3117 #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT
3118 #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK
3119 #define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL 0x10000200
3120 #define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT 8
3121 #define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK 0x00000100U
3123 /*CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur
3124 d to support DDR4.*/
3125 #undef DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL
3126 #undef DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT
3127 #undef DDRC_CRCPARCTL1_CRC_INC_DM_MASK
3128 #define DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL 0x10000200
3129 #define DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT 7
3130 #define DDRC_CRCPARCTL1_CRC_INC_DM_MASK 0x00000080U
3132 /*CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th
3133 CRC mode register setting in the DRAM.*/
3134 #undef DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL
3135 #undef DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT
3136 #undef DDRC_CRCPARCTL1_CRC_ENABLE_MASK
3137 #define DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL 0x10000200
3138 #define DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT 4
3139 #define DDRC_CRCPARCTL1_CRC_ENABLE_MASK 0x00000010U
3141 /*C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of
3142 /A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t
3143 is register should be 1.*/
3144 #undef DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL
3145 #undef DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT
3146 #undef DDRC_CRCPARCTL1_PARITY_ENABLE_MASK
3147 #define DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL 0x10000200
3148 #define DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT 0
3149 #define DDRC_CRCPARCTL1_PARITY_ENABLE_MASK 0x00000001U
3151 /*Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values
3152 - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte
3153 er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.*/
3154 #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL
3155 #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT
3156 #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK
3157 #define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL 0x0030050C
3158 #define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT 16
3159 #define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK 0x01FF0000U
3161 /*Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: -
3162 tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer
3163 value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.*/
3164 #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL
3165 #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT
3166 #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK
3167 #define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL 0x0030050C
3168 #define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT 8
3169 #define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK 0x00001F00U
3171 /*Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be
3172 ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis
3173 er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy
3174 les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er
3175 or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme
3176 ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON
3177 max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en
3178 bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK)
3179 + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de
3180 ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The
3181 ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set
3182 to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-
3183 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D
3184 PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM
3185 _FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C
3186 C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo
3187 e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte
3188 bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP
3189 H-6 Values of 0, 1 and 2 are illegal.*/
3190 #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL
3191 #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT
3192 #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK
3193 #define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL 0x0030050C
3194 #define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT 0
3195 #define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK 0x0000003FU
3197 /*If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u
3198 in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip
3199 ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll
3200 r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported
3201 or LPDDR4 in this version of the uMCTL2.*/
3202 #undef DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL
3203 #undef DDRC_INIT0_SKIP_DRAM_INIT_SHIFT
3204 #undef DDRC_INIT0_SKIP_DRAM_INIT_MASK
3205 #define DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL 0x0002004E
3206 #define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT 30
3207 #define DDRC_INIT0_SKIP_DRAM_INIT_MASK 0xC0000000U
3209 /*Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires
3210 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr
3211 grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M
3212 MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value.*/
3213 #undef DDRC_INIT0_POST_CKE_X1024_DEFVAL
3214 #undef DDRC_INIT0_POST_CKE_X1024_SHIFT
3215 #undef DDRC_INIT0_POST_CKE_X1024_MASK
3216 #define DDRC_INIT0_POST_CKE_X1024_DEFVAL 0x0002004E
3217 #define DDRC_INIT0_POST_CKE_X1024_SHIFT 16
3218 #define DDRC_INIT0_POST_CKE_X1024_MASK 0x03FF0000U
3220 /*Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2
3221 pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4:
3222 tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u
3223 to next integer value.*/
3224 #undef DDRC_INIT0_PRE_CKE_X1024_DEFVAL
3225 #undef DDRC_INIT0_PRE_CKE_X1024_SHIFT
3226 #undef DDRC_INIT0_PRE_CKE_X1024_MASK
3227 #define DDRC_INIT0_PRE_CKE_X1024_DEFVAL 0x0002004E
3228 #define DDRC_INIT0_PRE_CKE_X1024_SHIFT 0
3229 #define DDRC_INIT0_PRE_CKE_X1024_MASK 0x00000FFFU
3231 /*Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or
3232 LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1*/
3233 #undef DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL
3234 #undef DDRC_INIT1_DRAM_RSTN_X1024_SHIFT
3235 #undef DDRC_INIT1_DRAM_RSTN_X1024_MASK
3236 #define DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL 0x00000000
3237 #define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT 16
3238 #define DDRC_INIT1_DRAM_RSTN_X1024_MASK 0x01FF0000U
3240 /*Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl
3241 bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero.*/
3242 #undef DDRC_INIT1_FINAL_WAIT_X32_DEFVAL
3243 #undef DDRC_INIT1_FINAL_WAIT_X32_SHIFT
3244 #undef DDRC_INIT1_FINAL_WAIT_X32_MASK
3245 #define DDRC_INIT1_FINAL_WAIT_X32_DEFVAL 0x00000000
3246 #define DDRC_INIT1_FINAL_WAIT_X32_SHIFT 8
3247 #define DDRC_INIT1_FINAL_WAIT_X32_MASK 0x00007F00U
3249 /*Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle
3250 . There is no known specific requirement for this; it may be set to zero.*/
3251 #undef DDRC_INIT1_PRE_OCD_X32_DEFVAL
3252 #undef DDRC_INIT1_PRE_OCD_X32_SHIFT
3253 #undef DDRC_INIT1_PRE_OCD_X32_MASK
3254 #define DDRC_INIT1_PRE_OCD_X32_DEFVAL 0x00000000
3255 #define DDRC_INIT1_PRE_OCD_X32_SHIFT 0
3256 #define DDRC_INIT1_PRE_OCD_X32_MASK 0x0000000FU
3258 /*Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles.*/
3259 #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL
3260 #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT
3261 #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK
3262 #define DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL 0x00000D05
3263 #define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT 8
3264 #define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK 0x0000FF00U
3266 /*Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc
3267 e. LPDDR2/LPDDR3 typically requires 5 x tCK delay.*/
3268 #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL
3269 #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT
3270 #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK
3271 #define DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL 0x00000D05
3272 #define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT 0
3273 #define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK 0x0000000FU
3275 /*DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately
3276 DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1
3278 #undef DDRC_INIT3_MR_DEFVAL
3279 #undef DDRC_INIT3_MR_SHIFT
3280 #undef DDRC_INIT3_MR_MASK
3281 #define DDRC_INIT3_MR_DEFVAL 0x00000510
3282 #define DDRC_INIT3_MR_SHIFT 16
3283 #define DDRC_INIT3_MR_MASK 0xFFFF0000U
3285 /*DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those
3286 bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi
3287 bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V
3288 lue to write to MR2 register*/
3289 #undef DDRC_INIT3_EMR_DEFVAL
3290 #undef DDRC_INIT3_EMR_SHIFT
3291 #undef DDRC_INIT3_EMR_MASK
3292 #define DDRC_INIT3_EMR_DEFVAL 0x00000510
3293 #define DDRC_INIT3_EMR_SHIFT 0
3294 #define DDRC_INIT3_EMR_MASK 0x0000FFFFU
3296 /*DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3
3297 egister mDDR: Unused*/
3298 #undef DDRC_INIT4_EMR2_DEFVAL
3299 #undef DDRC_INIT4_EMR2_SHIFT
3300 #undef DDRC_INIT4_EMR2_MASK
3301 #define DDRC_INIT4_EMR2_DEFVAL 0x00000000
3302 #define DDRC_INIT4_EMR2_SHIFT 16
3303 #define DDRC_INIT4_EMR2_MASK 0xFFFF0000U
3305 /*DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to
3306 rite to MR13 register*/
3307 #undef DDRC_INIT4_EMR3_DEFVAL
3308 #undef DDRC_INIT4_EMR3_SHIFT
3309 #undef DDRC_INIT4_EMR3_MASK
3310 #define DDRC_INIT4_EMR3_DEFVAL 0x00000000
3311 #define DDRC_INIT4_EMR3_SHIFT 0
3312 #define DDRC_INIT4_EMR3_MASK 0x0000FFFFU
3314 /*ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock
3315 ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us.*/
3316 #undef DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL
3317 #undef DDRC_INIT5_DEV_ZQINIT_X32_SHIFT
3318 #undef DDRC_INIT5_DEV_ZQINIT_X32_MASK
3319 #define DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL 0x00100004
3320 #define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT 16
3321 #define DDRC_INIT5_DEV_ZQINIT_X32_MASK 0x00FF0000U
3323 /*Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD
3324 3 typically requires 10 us.*/
3325 #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL
3326 #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT
3327 #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK
3328 #define DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL 0x00100004
3329 #define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT 0
3330 #define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK 0x000003FFU
3332 /*DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.*/
3333 #undef DDRC_INIT6_MR4_DEFVAL
3334 #undef DDRC_INIT6_MR4_SHIFT
3335 #undef DDRC_INIT6_MR4_MASK
3336 #define DDRC_INIT6_MR4_DEFVAL 0x00000000
3337 #define DDRC_INIT6_MR4_SHIFT 16
3338 #define DDRC_INIT6_MR4_MASK 0xFFFF0000U
3340 /*DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.*/
3341 #undef DDRC_INIT6_MR5_DEFVAL
3342 #undef DDRC_INIT6_MR5_SHIFT
3343 #undef DDRC_INIT6_MR5_MASK
3344 #define DDRC_INIT6_MR5_DEFVAL 0x00000000
3345 #define DDRC_INIT6_MR5_SHIFT 0
3346 #define DDRC_INIT6_MR5_MASK 0x0000FFFFU
3348 /*DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.*/
3349 #undef DDRC_INIT7_MR6_DEFVAL
3350 #undef DDRC_INIT7_MR6_SHIFT
3351 #undef DDRC_INIT7_MR6_MASK
3352 #define DDRC_INIT7_MR6_DEFVAL
3353 #define DDRC_INIT7_MR6_SHIFT 16
3354 #define DDRC_INIT7_MR6_MASK 0xFFFF0000U
3356 /*Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab
3357 ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i
3358 address mirroring is enabled.*/
3359 #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL
3360 #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT
3361 #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK
3362 #define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL 0x00000000
3363 #define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT 5
3364 #define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK 0x00000020U
3366 /*Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
3367 be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output
3368 nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no
3369 effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena
3370 led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled*/
3371 #undef DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL
3372 #undef DDRC_DIMMCTL_MRS_BG1_EN_SHIFT
3373 #undef DDRC_DIMMCTL_MRS_BG1_EN_MASK
3374 #define DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL 0x00000000
3375 #define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT 4
3376 #define DDRC_DIMMCTL_MRS_BG1_EN_MASK 0x00000010U
3378 /*Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
3379 be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled,
3380 his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address
3381 f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled*/
3382 #undef DDRC_DIMMCTL_MRS_A17_EN_DEFVAL
3383 #undef DDRC_DIMMCTL_MRS_A17_EN_SHIFT
3384 #undef DDRC_DIMMCTL_MRS_A17_EN_MASK
3385 #define DDRC_DIMMCTL_MRS_A17_EN_DEFVAL 0x00000000
3386 #define DDRC_DIMMCTL_MRS_A17_EN_SHIFT 3
3387 #define DDRC_DIMMCTL_MRS_A17_EN_MASK 0x00000008U
3389 /*Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default,
3390 which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17,
3391 A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi
3392 lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated.
3393 or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi
3394 has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out
3395 ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs.*/
3396 #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL
3397 #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT
3398 #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK
3399 #define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL 0x00000000
3400 #define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT 2
3401 #define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK 0x00000004U
3403 /*Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD
3404 4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits
3405 re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t
3406 at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe
3407 sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar
3408 swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr
3409 ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3
3410 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid,
3411 hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d
3412 ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do
3413 not implement address mirroring*/
3414 #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL
3415 #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT
3416 #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK
3417 #define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL 0x00000000
3418 #define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT 1
3419 #define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK 0x00000002U
3421 /*Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD
3422 R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M
3423 CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t
3424 each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses*/
3425 #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL
3426 #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT
3427 #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK
3428 #define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL 0x00000000
3429 #define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT 0
3430 #define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK 0x00000001U
3432 /*Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
3433 e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c
3434 nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs
3435 ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa
3436 ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed
3437 n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi
3438 ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement
3439 or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u
3440 to the next integer.*/
3441 #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL
3442 #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT
3443 #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK
3444 #define DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL 0x0000066F
3445 #define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT 8
3446 #define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK 0x00000F00U
3448 /*Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
3449 e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co
3450 sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg
3451 p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl
3452 ), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing
3453 requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r
3454 quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and
3455 ound it up to the next integer.*/
3456 #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL
3457 #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT
3458 #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK
3459 #define DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL 0x0000066F
3460 #define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT 4
3461 #define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK 0x000000F0U
3463 /*Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ
3464 nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content
3465 on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl
3466 -by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran
3467 _rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f
3468 om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv
3469 ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to
3470 llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair
3471 ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as
3472 ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x
3473 . FOR PERFORMANCE ONLY.*/
3474 #undef DDRC_RANKCTL_MAX_RANK_RD_DEFVAL
3475 #undef DDRC_RANKCTL_MAX_RANK_RD_SHIFT
3476 #undef DDRC_RANKCTL_MAX_RANK_RD_MASK
3477 #define DDRC_RANKCTL_MAX_RANK_RD_DEFVAL 0x0000066F
3478 #define DDRC_RANKCTL_MAX_RANK_RD_SHIFT 0
3479 #define DDRC_RANKCTL_MAX_RANK_RD_MASK 0x0000000FU
3481 /*Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles
3482 15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th
3483 value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR =
3484 Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this
3485 arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations
3486 with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.*/
3487 #undef DDRC_DRAMTMG0_WR2PRE_DEFVAL
3488 #undef DDRC_DRAMTMG0_WR2PRE_SHIFT
3489 #undef DDRC_DRAMTMG0_WR2PRE_MASK
3490 #define DDRC_DRAMTMG0_WR2PRE_DEFVAL 0x0F101B0F
3491 #define DDRC_DRAMTMG0_WR2PRE_SHIFT 24
3492 #define DDRC_DRAMTMG0_WR2PRE_MASK 0x7F000000U
3494 /*tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated
3495 in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next
3496 nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks*/
3497 #undef DDRC_DRAMTMG0_T_FAW_DEFVAL
3498 #undef DDRC_DRAMTMG0_T_FAW_SHIFT
3499 #undef DDRC_DRAMTMG0_T_FAW_MASK
3500 #define DDRC_DRAMTMG0_T_FAW_DEFVAL 0x0F101B0F
3501 #define DDRC_DRAMTMG0_T_FAW_SHIFT 16
3502 #define DDRC_DRAMTMG0_T_FAW_MASK 0x003F0000U
3504 /*tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi
3505 imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2
3506 No rounding up. Unit: Multiples of 1024 clocks.*/
3507 #undef DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL
3508 #undef DDRC_DRAMTMG0_T_RAS_MAX_SHIFT
3509 #undef DDRC_DRAMTMG0_T_RAS_MAX_MASK
3510 #define DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL 0x0F101B0F
3511 #define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT 8
3512 #define DDRC_DRAMTMG0_T_RAS_MAX_MASK 0x00007F00U
3514 /*tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode,
3515 rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t
3516 (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks*/
3517 #undef DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL
3518 #undef DDRC_DRAMTMG0_T_RAS_MIN_SHIFT
3519 #undef DDRC_DRAMTMG0_T_RAS_MIN_MASK
3520 #define DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL 0x0F101B0F
3521 #define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT 0
3522 #define DDRC_DRAMTMG0_T_RAS_MIN_MASK 0x0000003FU
3524 /*tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi
3525 is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2,
3526 rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks*/
3527 #undef DDRC_DRAMTMG1_T_XP_DEFVAL
3528 #undef DDRC_DRAMTMG1_T_XP_SHIFT
3529 #undef DDRC_DRAMTMG1_T_XP_MASK
3530 #define DDRC_DRAMTMG1_T_XP_DEFVAL 0x00080414
3531 #define DDRC_DRAMTMG1_T_XP_SHIFT 16
3532 #define DDRC_DRAMTMG1_T_XP_MASK 0x001F0000U
3534 /*tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D
3535 R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2
3536 S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL
3537 2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf
3538 gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val
3540 #undef DDRC_DRAMTMG1_RD2PRE_DEFVAL
3541 #undef DDRC_DRAMTMG1_RD2PRE_SHIFT
3542 #undef DDRC_DRAMTMG1_RD2PRE_MASK
3543 #define DDRC_DRAMTMG1_RD2PRE_DEFVAL 0x00080414
3544 #define DDRC_DRAMTMG1_RD2PRE_SHIFT 8
3545 #define DDRC_DRAMTMG1_RD2PRE_MASK 0x00001F00U
3547 /*tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun
3548 up to next integer value. Unit: Clocks.*/
3549 #undef DDRC_DRAMTMG1_T_RC_DEFVAL
3550 #undef DDRC_DRAMTMG1_T_RC_SHIFT
3551 #undef DDRC_DRAMTMG1_T_RC_MASK
3552 #define DDRC_DRAMTMG1_T_RC_DEFVAL 0x00080414
3553 #define DDRC_DRAMTMG1_T_RC_SHIFT 0
3554 #define DDRC_DRAMTMG1_T_RC_MASK 0x0000007FU
3556 /*Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s
3557 t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e
3558 tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above
3559 equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ
3560 is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks*/
3561 #undef DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL
3562 #undef DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT
3563 #undef DDRC_DRAMTMG2_WRITE_LATENCY_MASK
3564 #define DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL 0x0305060D
3565 #define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT 24
3566 #define DDRC_DRAMTMG2_WRITE_LATENCY_MASK 0x3F000000U
3568 /*Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if
3569 using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For
3570 onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte
3571 er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci
3572 s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks*/
3573 #undef DDRC_DRAMTMG2_READ_LATENCY_DEFVAL
3574 #undef DDRC_DRAMTMG2_READ_LATENCY_SHIFT
3575 #undef DDRC_DRAMTMG2_READ_LATENCY_MASK
3576 #define DDRC_DRAMTMG2_READ_LATENCY_DEFVAL 0x0305060D
3577 #define DDRC_DRAMTMG2_READ_LATENCY_SHIFT 16
3578 #define DDRC_DRAMTMG2_READ_LATENCY_MASK 0x003F0000U
3580 /*DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL
3581 PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B
3582 /2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include
3583 time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL =
3584 urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l
3585 tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L
3586 DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf
3587 gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.*/
3588 #undef DDRC_DRAMTMG2_RD2WR_DEFVAL
3589 #undef DDRC_DRAMTMG2_RD2WR_SHIFT
3590 #undef DDRC_DRAMTMG2_RD2WR_MASK
3591 #define DDRC_DRAMTMG2_RD2WR_DEFVAL 0x0305060D
3592 #define DDRC_DRAMTMG2_RD2WR_SHIFT 8
3593 #define DDRC_DRAMTMG2_RD2WR_MASK 0x00003F00U
3595 /*DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba
3596 k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al
3597 per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs
3598 length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re
3599 d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman
3600 delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu
3601 ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.*/
3602 #undef DDRC_DRAMTMG2_WR2RD_DEFVAL
3603 #undef DDRC_DRAMTMG2_WR2RD_SHIFT
3604 #undef DDRC_DRAMTMG2_WR2RD_MASK
3605 #define DDRC_DRAMTMG2_WR2RD_DEFVAL 0x0305060D
3606 #define DDRC_DRAMTMG2_WR2RD_SHIFT 0
3607 #define DDRC_DRAMTMG2_WR2RD_MASK 0x0000003FU
3609 /*Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o
3610 LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW
3611 nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i
3612 used for the time from a MRW/MRR to a MRW/MRR.*/
3613 #undef DDRC_DRAMTMG3_T_MRW_DEFVAL
3614 #undef DDRC_DRAMTMG3_T_MRW_SHIFT
3615 #undef DDRC_DRAMTMG3_T_MRW_MASK
3616 #define DDRC_DRAMTMG3_T_MRW_DEFVAL 0x0050400C
3617 #define DDRC_DRAMTMG3_T_MRW_SHIFT 20
3618 #define DDRC_DRAMTMG3_T_MRW_MASK 0x3FF00000U
3620 /*tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time
3621 rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c
3622 nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD
3623 4 is used, set to tMRD_PAR(tMOD+PL) instead.*/
3624 #undef DDRC_DRAMTMG3_T_MRD_DEFVAL
3625 #undef DDRC_DRAMTMG3_T_MRD_SHIFT
3626 #undef DDRC_DRAMTMG3_T_MRD_MASK
3627 #define DDRC_DRAMTMG3_T_MRD_DEFVAL 0x0050400C
3628 #define DDRC_DRAMTMG3_T_MRD_SHIFT 12
3629 #define DDRC_DRAMTMG3_T_MRD_MASK 0x0003F000U
3631 /*tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari
3632 y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer
3633 if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO
3634 + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip.*/
3635 #undef DDRC_DRAMTMG3_T_MOD_DEFVAL
3636 #undef DDRC_DRAMTMG3_T_MOD_SHIFT
3637 #undef DDRC_DRAMTMG3_T_MOD_MASK
3638 #define DDRC_DRAMTMG3_T_MOD_DEFVAL 0x0050400C
3639 #define DDRC_DRAMTMG3_T_MOD_SHIFT 0
3640 #define DDRC_DRAMTMG3_T_MOD_MASK 0x000003FFU
3642 /*tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog
3643 am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im
3644 lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.*/
3645 #undef DDRC_DRAMTMG4_T_RCD_DEFVAL
3646 #undef DDRC_DRAMTMG4_T_RCD_SHIFT
3647 #undef DDRC_DRAMTMG4_T_RCD_MASK
3648 #define DDRC_DRAMTMG4_T_RCD_DEFVAL 0x05040405
3649 #define DDRC_DRAMTMG4_T_RCD_SHIFT 24
3650 #define DDRC_DRAMTMG4_T_RCD_MASK 0x1F000000U
3652 /*DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum
3653 time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou
3654 d it up to the next integer value. Unit: clocks.*/
3655 #undef DDRC_DRAMTMG4_T_CCD_DEFVAL
3656 #undef DDRC_DRAMTMG4_T_CCD_SHIFT
3657 #undef DDRC_DRAMTMG4_T_CCD_MASK
3658 #define DDRC_DRAMTMG4_T_CCD_DEFVAL 0x05040405
3659 #define DDRC_DRAMTMG4_T_CCD_SHIFT 16
3660 #define DDRC_DRAMTMG4_T_CCD_MASK 0x000F0000U
3662 /*DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee
3663 activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round
3664 it up to the next integer value. Unit: Clocks.*/
3665 #undef DDRC_DRAMTMG4_T_RRD_DEFVAL
3666 #undef DDRC_DRAMTMG4_T_RRD_SHIFT
3667 #undef DDRC_DRAMTMG4_T_RRD_MASK
3668 #define DDRC_DRAMTMG4_T_RRD_DEFVAL 0x05040405
3669 #define DDRC_DRAMTMG4_T_RRD_SHIFT 8
3670 #define DDRC_DRAMTMG4_T_RRD_MASK 0x00000F00U
3672 /*tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU
3673 (tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO
3674 2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.*/
3675 #undef DDRC_DRAMTMG4_T_RP_DEFVAL
3676 #undef DDRC_DRAMTMG4_T_RP_SHIFT
3677 #undef DDRC_DRAMTMG4_T_RP_MASK
3678 #define DDRC_DRAMTMG4_T_RP_DEFVAL 0x05040405
3679 #define DDRC_DRAMTMG4_T_RP_SHIFT 0
3680 #define DDRC_DRAMTMG4_T_RP_MASK 0x0000001FU
3682 /*This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab
3683 e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4:
3684 tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in
3686 #undef DDRC_DRAMTMG5_T_CKSRX_DEFVAL
3687 #undef DDRC_DRAMTMG5_T_CKSRX_SHIFT
3688 #undef DDRC_DRAMTMG5_T_CKSRX_MASK
3689 #define DDRC_DRAMTMG5_T_CKSRX_DEFVAL 0x05050403
3690 #define DDRC_DRAMTMG5_T_CKSRX_SHIFT 24
3691 #define DDRC_DRAMTMG5_T_CKSRX_MASK 0x0F000000U
3693 /*This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte
3694 SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4:
3695 ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up
3697 #undef DDRC_DRAMTMG5_T_CKSRE_DEFVAL
3698 #undef DDRC_DRAMTMG5_T_CKSRE_SHIFT
3699 #undef DDRC_DRAMTMG5_T_CKSRE_MASK
3700 #define DDRC_DRAMTMG5_T_CKSRE_DEFVAL 0x05050403
3701 #define DDRC_DRAMTMG5_T_CKSRE_SHIFT 16
3702 #define DDRC_DRAMTMG5_T_CKSRE_MASK 0x000F0000U
3704 /*Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se
3705 tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE
3706 1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege
3708 #undef DDRC_DRAMTMG5_T_CKESR_DEFVAL
3709 #undef DDRC_DRAMTMG5_T_CKESR_SHIFT
3710 #undef DDRC_DRAMTMG5_T_CKESR_MASK
3711 #define DDRC_DRAMTMG5_T_CKESR_DEFVAL 0x05050403
3712 #define DDRC_DRAMTMG5_T_CKESR_SHIFT 8
3713 #define DDRC_DRAMTMG5_T_CKESR_MASK 0x00003F00U
3715 /*Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of
3716 CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set
3717 his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th
3718 next integer value. Unit: Clocks.*/
3719 #undef DDRC_DRAMTMG5_T_CKE_DEFVAL
3720 #undef DDRC_DRAMTMG5_T_CKE_SHIFT
3721 #undef DDRC_DRAMTMG5_T_CKE_MASK
3722 #define DDRC_DRAMTMG5_T_CKE_DEFVAL 0x05050403
3723 #define DDRC_DRAMTMG5_T_CKE_SHIFT 0
3724 #define DDRC_DRAMTMG5_T_CKE_MASK 0x0000001FU
3726 /*This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after
3727 PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom
3728 ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3
3730 #undef DDRC_DRAMTMG6_T_CKDPDE_DEFVAL
3731 #undef DDRC_DRAMTMG6_T_CKDPDE_SHIFT
3732 #undef DDRC_DRAMTMG6_T_CKDPDE_MASK
3733 #define DDRC_DRAMTMG6_T_CKDPDE_DEFVAL 0x02020005
3734 #define DDRC_DRAMTMG6_T_CKDPDE_SHIFT 24
3735 #define DDRC_DRAMTMG6_T_CKDPDE_MASK 0x0F000000U
3737 /*This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock
3738 table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr
3739 gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD
3740 R or LPDDR2 devices.*/
3741 #undef DDRC_DRAMTMG6_T_CKDPDX_DEFVAL
3742 #undef DDRC_DRAMTMG6_T_CKDPDX_SHIFT
3743 #undef DDRC_DRAMTMG6_T_CKDPDX_MASK
3744 #define DDRC_DRAMTMG6_T_CKDPDX_DEFVAL 0x02020005
3745 #define DDRC_DRAMTMG6_T_CKDPDX_SHIFT 16
3746 #define DDRC_DRAMTMG6_T_CKDPDX_MASK 0x000F0000U
3748 /*This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the
3749 lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP +
3750 2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it
3751 p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.*/
3752 #undef DDRC_DRAMTMG6_T_CKCSX_DEFVAL
3753 #undef DDRC_DRAMTMG6_T_CKCSX_SHIFT
3754 #undef DDRC_DRAMTMG6_T_CKCSX_MASK
3755 #define DDRC_DRAMTMG6_T_CKCSX_DEFVAL 0x02020005
3756 #define DDRC_DRAMTMG6_T_CKCSX_SHIFT 0
3757 #define DDRC_DRAMTMG6_T_CKCSX_MASK 0x0000000FU
3759 /*This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE.
3760 ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t
3761 is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L
3762 DDR2/LPDDR3/LPDDR4 devices.*/
3763 #undef DDRC_DRAMTMG7_T_CKPDE_DEFVAL
3764 #undef DDRC_DRAMTMG7_T_CKPDE_SHIFT
3765 #undef DDRC_DRAMTMG7_T_CKPDE_MASK
3766 #define DDRC_DRAMTMG7_T_CKPDE_DEFVAL 0x00000202
3767 #define DDRC_DRAMTMG7_T_CKPDE_SHIFT 8
3768 #define DDRC_DRAMTMG7_T_CKPDE_MASK 0x00000F00U
3770 /*This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable
3771 time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO=
3772 , program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti
3773 g mDDR or LPDDR2/LPDDR3/LPDDR4 devices.*/
3774 #undef DDRC_DRAMTMG7_T_CKPDX_DEFVAL
3775 #undef DDRC_DRAMTMG7_T_CKPDX_SHIFT
3776 #undef DDRC_DRAMTMG7_T_CKPDX_MASK
3777 #define DDRC_DRAMTMG7_T_CKPDX_DEFVAL 0x00000202
3778 #define DDRC_DRAMTMG7_T_CKPDX_SHIFT 0
3779 #define DDRC_DRAMTMG7_T_CKPDX_MASK 0x0000000FU
3781 /*tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT
3782 O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi
3783 is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32.*/
3784 #undef DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL
3785 #undef DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT
3786 #undef DDRC_DRAMTMG8_T_XS_FAST_X32_MASK
3787 #define DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL 0x03034405
3788 #define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT 24
3789 #define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK 0x7F000000U
3791 /*tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_
3792 ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note:
3793 nsure this is less than or equal to t_xs_x32.*/
3794 #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL
3795 #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT
3796 #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK
3797 #define DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL 0x03034405
3798 #define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT 16
3799 #define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK 0x007F0000U
3801 /*tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the
3802 bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
3804 #undef DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL
3805 #undef DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT
3806 #undef DDRC_DRAMTMG8_T_XS_DLL_X32_MASK
3807 #define DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL 0x03034405
3808 #define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT 8
3809 #define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK 0x00007F00U
3811 /*tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the
3812 above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
3814 #undef DDRC_DRAMTMG8_T_XS_X32_DEFVAL
3815 #undef DDRC_DRAMTMG8_T_XS_X32_SHIFT
3816 #undef DDRC_DRAMTMG8_T_XS_X32_MASK
3817 #define DDRC_DRAMTMG8_T_XS_X32_DEFVAL 0x03034405
3818 #define DDRC_DRAMTMG8_T_XS_X32_SHIFT 0
3819 #define DDRC_DRAMTMG8_T_XS_X32_MASK 0x0000007FU
3821 /*DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2*/
3822 #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL
3823 #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT
3824 #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK
3825 #define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL 0x0004040D
3826 #define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT 30
3827 #define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK 0x40000000U
3829 /*tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a'
3830 o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro
3831 nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks.*/
3832 #undef DDRC_DRAMTMG9_T_CCD_S_DEFVAL
3833 #undef DDRC_DRAMTMG9_T_CCD_S_SHIFT
3834 #undef DDRC_DRAMTMG9_T_CCD_S_MASK
3835 #define DDRC_DRAMTMG9_T_CCD_S_DEFVAL 0x0004040D
3836 #define DDRC_DRAMTMG9_T_CCD_S_SHIFT 16
3837 #define DDRC_DRAMTMG9_T_CCD_S_MASK 0x00070000U
3839 /*tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_
3840 ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D
3842 #undef DDRC_DRAMTMG9_T_RRD_S_DEFVAL
3843 #undef DDRC_DRAMTMG9_T_RRD_S_SHIFT
3844 #undef DDRC_DRAMTMG9_T_RRD_S_MASK
3845 #define DDRC_DRAMTMG9_T_RRD_S_DEFVAL 0x0004040D
3846 #define DDRC_DRAMTMG9_T_RRD_S_SHIFT 8
3847 #define DDRC_DRAMTMG9_T_RRD_S_MASK 0x00000F00U
3849 /*CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn
3850 round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4
3851 Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm
3852 d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T
3853 is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using
3854 he above equation by 2, and round it up to next integer.*/
3855 #undef DDRC_DRAMTMG9_WR2RD_S_DEFVAL
3856 #undef DDRC_DRAMTMG9_WR2RD_S_SHIFT
3857 #undef DDRC_DRAMTMG9_WR2RD_S_MASK
3858 #define DDRC_DRAMTMG9_WR2RD_S_DEFVAL 0x0004040D
3859 #define DDRC_DRAMTMG9_WR2RD_S_SHIFT 0
3860 #define DDRC_DRAMTMG9_WR2RD_S_MASK 0x0000003FU
3862 /*tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program
3863 this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult
3864 ples of 32 clocks.*/
3865 #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL
3866 #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT
3867 #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK
3868 #define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL 0x440C021C
3869 #define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT 24
3870 #define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK 0x7F000000U
3872 /*tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t
3873 RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks.*/
3874 #undef DDRC_DRAMTMG11_T_MPX_LH_DEFVAL
3875 #undef DDRC_DRAMTMG11_T_MPX_LH_SHIFT
3876 #undef DDRC_DRAMTMG11_T_MPX_LH_MASK
3877 #define DDRC_DRAMTMG11_T_MPX_LH_DEFVAL 0x440C021C
3878 #define DDRC_DRAMTMG11_T_MPX_LH_SHIFT 16
3879 #define DDRC_DRAMTMG11_T_MPX_LH_MASK 0x001F0000U
3881 /*tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it
3882 up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks.*/
3883 #undef DDRC_DRAMTMG11_T_MPX_S_DEFVAL
3884 #undef DDRC_DRAMTMG11_T_MPX_S_SHIFT
3885 #undef DDRC_DRAMTMG11_T_MPX_S_MASK
3886 #define DDRC_DRAMTMG11_T_MPX_S_DEFVAL 0x440C021C
3887 #define DDRC_DRAMTMG11_T_MPX_S_SHIFT 8
3888 #define DDRC_DRAMTMG11_T_MPX_S_MASK 0x00000300U
3890 /*tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F
3891 r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i
3893 #undef DDRC_DRAMTMG11_T_CKMPE_DEFVAL
3894 #undef DDRC_DRAMTMG11_T_CKMPE_SHIFT
3895 #undef DDRC_DRAMTMG11_T_CKMPE_MASK
3896 #define DDRC_DRAMTMG11_T_CKMPE_DEFVAL 0x440C021C
3897 #define DDRC_DRAMTMG11_T_CKMPE_SHIFT 0
3898 #define DDRC_DRAMTMG11_T_CKMPE_MASK 0x0000001FU
3900 /*tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_
3901 REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value.*/
3902 #undef DDRC_DRAMTMG12_T_CMDCKE_DEFVAL
3903 #undef DDRC_DRAMTMG12_T_CMDCKE_SHIFT
3904 #undef DDRC_DRAMTMG12_T_CMDCKE_MASK
3905 #define DDRC_DRAMTMG12_T_CMDCKE_DEFVAL 0x00020610
3906 #define DDRC_DRAMTMG12_T_CMDCKE_SHIFT 16
3907 #define DDRC_DRAMTMG12_T_CMDCKE_MASK 0x00030000U
3909 /*tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM
3910 /2) and round it up to next integer value.*/
3911 #undef DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL
3912 #undef DDRC_DRAMTMG12_T_CKEHCMD_SHIFT
3913 #undef DDRC_DRAMTMG12_T_CKEHCMD_MASK
3914 #define DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL 0x00020610
3915 #define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT 8
3916 #define DDRC_DRAMTMG12_T_CKEHCMD_MASK 0x00000F00U
3918 /*tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th
3919 s to (tMRD_PDA/2) and round it up to next integer value.*/
3920 #undef DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL
3921 #undef DDRC_DRAMTMG12_T_MRD_PDA_SHIFT
3922 #undef DDRC_DRAMTMG12_T_MRD_PDA_MASK
3923 #define DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL 0x00020610
3924 #define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT 0
3925 #define DDRC_DRAMTMG12_T_MRD_PDA_MASK 0x0000001FU
3927 /*- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is
3928 ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s
3929 ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
3930 #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL
3931 #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT
3932 #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK
3933 #define DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL 0x02000040
3934 #define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT 31
3935 #define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK 0x80000000U
3937 /*- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3
3938 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power
3939 own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo
3940 ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
3941 #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL
3942 #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT
3943 #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK
3944 #define DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL 0x02000040
3945 #define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT 30
3946 #define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK 0x40000000U
3948 /*- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r
3949 nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov
3950 rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
3951 #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL
3952 #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT
3953 #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK
3954 #define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL 0x02000040
3955 #define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT 29
3956 #define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK 0x20000000U
3958 /*- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable
3959 ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des
3960 gns supporting DDR4 devices.*/
3961 #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL
3962 #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT
3963 #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK
3964 #define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL 0x02000040
3965 #define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT 28
3966 #define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK 0x10000000U
3968 /*tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat
3969 on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo
3970 er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va
3971 ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for
3972 esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
3973 #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL
3974 #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT
3975 #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK
3976 #define DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL 0x02000040
3977 #define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT 16
3978 #define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK 0x07FF0000U
3980 /*tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC
3981 ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t
3982 e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic
3984 #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL
3985 #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT
3986 #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK
3987 #define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL 0x02000040
3988 #define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT 0
3989 #define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK 0x000003FFU
3991 /*tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati
3992 ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is
3993 nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.*/
3994 #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL
3995 #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT
3996 #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK
3997 #define DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL 0x02000100
3998 #define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT 20
3999 #define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK 0x3FF00000U
4001 /*Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/
4002 PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs
4003 upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
4004 #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL
4005 #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT
4006 #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK
4007 #define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL 0x02000100
4008 #define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT 0
4009 #define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK 0x000FFFFFU
4011 /*Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
4012 s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
4013 , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
4014 this parameter by RDIMM's extra cycle of latency in terms of DFI clock.*/
4015 #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL
4016 #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT
4017 #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK
4018 #define DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL 0x07020002
4019 #define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT 24
4020 #define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK 0x1F000000U
4022 /*Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
4023 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
4024 fer to PHY specification for correct value.*/
4025 #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL
4026 #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT
4027 #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK
4028 #define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002
4029 #define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT 23
4030 #define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK 0x00800000U
4032 /*Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
4033 ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
4034 , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
4035 latency through the RDIMM. Unit: Clocks*/
4036 #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL
4037 #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT
4038 #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK
4039 #define DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL 0x07020002
4040 #define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT 16
4041 #define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK 0x003F0000U
4043 /*Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
4044 .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
4045 HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
4047 #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL
4048 #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT
4049 #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK
4050 #define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002
4051 #define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT 15
4052 #define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK 0x00008000U
4054 /*Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
4055 dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
4056 te, max supported value is 8. Unit: Clocks*/
4057 #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL
4058 #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT
4059 #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK
4060 #define DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL 0x07020002
4061 #define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT 8
4062 #define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK 0x00003F00U
4064 /*Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
4065 parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
4066 necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
4068 #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL
4069 #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT
4070 #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK
4071 #define DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL 0x07020002
4072 #define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT 0
4073 #define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK 0x0000003FU
4075 /*Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven.
4076 his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If
4077 the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8*/
4078 #undef DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL
4079 #undef DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT
4080 #undef DDRC_DFITMG1_DFI_T_CMD_LAT_MASK
4081 #define DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL 0x00000404
4082 #define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT 28
4083 #define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK 0xF0000000U
4085 /*Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa
4087 #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL
4088 #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT
4089 #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK
4090 #define DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL 0x00000404
4091 #define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT 24
4092 #define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK 0x03000000U
4094 /*Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr
4095 nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo
4096 correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to
4097 phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ
4098 RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni
4100 #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL
4101 #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT
4102 #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK
4103 #define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL 0x00000404
4104 #define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT 16
4105 #define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK 0x001F0000U
4107 /*Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to
4108 he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase
4109 ligned, this timing parameter should be rounded up to the next integer value.*/
4110 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL
4111 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT
4112 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK
4113 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL 0x00000404
4114 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT 8
4115 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK 0x00000F00U
4117 /*Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first
4118 alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are
4119 not phase aligned, this timing parameter should be rounded up to the next integer value.*/
4120 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL
4121 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT
4122 #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK
4123 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL 0x00000404
4124 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT 0
4125 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK 0x0000000FU
4127 /*Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi
4128 g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always.*/
4129 #undef DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL
4130 #undef DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT
4131 #undef DDRC_DFILPCFG0_DFI_TLP_RESP_MASK
4132 #define DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL 0x07000000
4133 #define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT 24
4134 #define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK 0x0F000000U
4136 /*Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16
4137 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7
4138 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD -
4139 31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device
4141 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL
4142 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT
4143 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK
4144 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL 0x07000000
4145 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT 20
4146 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK 0x00F00000U
4148 /*Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres
4149 nt for designs supporting mDDR or LPDDR2/LPDDR3 devices.*/
4150 #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL
4151 #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT
4152 #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK
4153 #define DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL 0x07000000
4154 #define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT 16
4155 #define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK 0x00010000U
4157 /*Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy
4158 les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 -
4159 048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131
4160 72 cycles - 0xE - 262144 cycles - 0xF - Unlimited*/
4161 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL
4162 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT
4163 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK
4164 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL 0x07000000
4165 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT 12
4166 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK 0x0000F000U
4168 /*Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled*/
4169 #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL
4170 #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT
4171 #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK
4172 #define DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL 0x07000000
4173 #define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT 8
4174 #define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK 0x00000100U
4176 /*Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl
4177 s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20
4178 8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107
4179 cycles - 0xE - 262144 cycles - 0xF - Unlimited*/
4180 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL
4181 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT
4182 #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK
4183 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL 0x07000000
4184 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT 4
4185 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK 0x000000F0U
4187 /*Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled*/
4188 #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL
4189 #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT
4190 #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK
4191 #define DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL 0x07000000
4192 #define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT 0
4193 #define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK 0x00000001U
4195 /*Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0
4196 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles
4197 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0
4198 D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices.*/
4199 #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL
4200 #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT
4201 #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK
4202 #define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL 0x00000000
4203 #define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT 4
4204 #define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK 0x000000F0U
4206 /*Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is
4207 only present for designs supporting DDR4 devices.*/
4208 #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL
4209 #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT
4210 #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK
4211 #define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL 0x00000000
4212 #define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT 0
4213 #define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK 0x00000001U
4215 /*This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl
4216 ). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir
4217 t read request when the uMCTL2 is idle. Unit: 1024 clocks*/
4218 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL
4219 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT
4220 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK
4221 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL 0x00000000
4222 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT 16
4223 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK 0x00FF0000U
4225 /*This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request;
4226 hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this
4227 idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca
4228 e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance.
4229 Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x
4230 024. Unit: 1024 clocks*/
4231 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL
4232 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT
4233 #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK
4234 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL 0x00000000
4235 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT 0
4236 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK 0x000000FFU
4238 /*Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high*/
4239 #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL
4240 #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT
4241 #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK
4242 #define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL 0x00000001
4243 #define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT 2
4244 #define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK 0x00000004U
4246 /*DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only
4247 in designs configured to support DDR4 and LPDDR4.*/
4248 #undef DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL
4249 #undef DDRC_DFIMISC_PHY_DBI_MODE_SHIFT
4250 #undef DDRC_DFIMISC_PHY_DBI_MODE_MASK
4251 #define DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL 0x00000001
4252 #define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT 1
4253 #define DDRC_DFIMISC_PHY_DBI_MODE_MASK 0x00000002U
4255 /*PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa
4257 #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL
4258 #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT
4259 #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK
4260 #define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL 0x00000001
4261 #define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT 0
4262 #define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK 0x00000001U
4264 /*>Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign
4265 l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.*/
4266 #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL
4267 #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT
4268 #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK
4269 #define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL 0x00000202
4270 #define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT 8
4271 #define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK 0x00003F00U
4273 /*Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign
4274 l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.*/
4275 #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL
4276 #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT
4277 #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK
4278 #define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL 0x00000202
4279 #define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT 0
4280 #define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK 0x0000003FU
4282 /*Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value
4283 as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]*/
4284 #undef DDRC_DBICTL_RD_DBI_EN_DEFVAL
4285 #undef DDRC_DBICTL_RD_DBI_EN_SHIFT
4286 #undef DDRC_DBICTL_RD_DBI_EN_MASK
4287 #define DDRC_DBICTL_RD_DBI_EN_DEFVAL 0x00000001
4288 #define DDRC_DBICTL_RD_DBI_EN_SHIFT 2
4289 #define DDRC_DBICTL_RD_DBI_EN_MASK 0x00000004U
4291 /*Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va
4292 ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]*/
4293 #undef DDRC_DBICTL_WR_DBI_EN_DEFVAL
4294 #undef DDRC_DBICTL_WR_DBI_EN_SHIFT
4295 #undef DDRC_DBICTL_WR_DBI_EN_MASK
4296 #define DDRC_DBICTL_WR_DBI_EN_DEFVAL 0x00000001
4297 #define DDRC_DBICTL_WR_DBI_EN_SHIFT 1
4298 #define DDRC_DBICTL_WR_DBI_EN_MASK 0x00000002U
4300 /*DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's
4301 mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR
4302 : Set this to inverted value of MR13[5] which is opposite polarity from this signal*/
4303 #undef DDRC_DBICTL_DM_EN_DEFVAL
4304 #undef DDRC_DBICTL_DM_EN_SHIFT
4305 #undef DDRC_DBICTL_DM_EN_MASK
4306 #define DDRC_DBICTL_DM_EN_DEFVAL 0x00000001
4307 #define DDRC_DBICTL_DM_EN_SHIFT 0
4308 #define DDRC_DBICTL_DM_EN_MASK 0x00000001U
4310 /*Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres
4311 bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0.*/
4312 #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL
4313 #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT
4314 #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK
4315 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL
4316 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT 0
4317 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK 0x0000001FU
4319 /*Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address
4320 bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0.*/
4321 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL
4322 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT
4323 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK
4324 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL 0x00000000
4325 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT 16
4326 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK 0x001F0000U
4328 /*Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f
4329 r each of the bank address bits is determined by adding the internal base to the value of this field.*/
4330 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL
4331 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT
4332 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK
4333 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL 0x00000000
4334 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT 8
4335 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK 0x00001F00U
4337 /*Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f
4338 r each of the bank address bits is determined by adding the internal base to the value of this field.*/
4339 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL
4340 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT
4341 #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK
4342 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL 0x00000000
4343 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT 0
4344 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK 0x0000001FU
4346 /*- Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre
4347 s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali
4348 Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o
4349 this field. If set to 15, this column address bit is set to 0.*/
4350 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL
4351 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT
4352 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK
4353 #define DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL 0x00000000
4354 #define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT 24
4355 #define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK 0x0F000000U
4357 /*- Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre
4358 s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid
4359 Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of
4360 this field. If set to 15, this column address bit is set to 0.*/
4361 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL
4362 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT
4363 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK
4364 #define DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL 0x00000000
4365 #define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT 16
4366 #define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK 0x000F0000U
4368 /*- Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre
4369 s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid
4370 Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi
4371 ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i
4373 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL
4374 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT
4375 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK
4376 #define DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL 0x00000000
4377 #define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT 8
4378 #define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK 0x00000F00U
4380 /*- Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre
4381 s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid
4382 Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi
4383 ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0.*/
4384 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL
4385 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT
4386 #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK
4387 #define DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL 0x00000000
4388 #define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT 0
4389 #define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK 0x0000000FU
4391 /*- Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre
4392 s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as
4393 column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i
4394 determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note:
4395 er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr
4396 ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an
4397 hence column bit 10 is used.*/
4398 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL
4399 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT
4400 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK
4401 #define DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL 0x00000000
4402 #define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT 24
4403 #define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK 0x0F000000U
4405 /*- Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre
4406 s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i
4407 LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i
4408 ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif
4409 cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col
4410 mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use
4412 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL
4413 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT
4414 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK
4415 #define DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL 0x00000000
4416 #define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT 16
4417 #define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK 0x000F0000U
4419 /*- Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre
4420 s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid
4421 Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of
4422 this field. If set to 15, this column address bit is set to 0.*/
4423 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL
4424 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT
4425 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK
4426 #define DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL 0x00000000
4427 #define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT 8
4428 #define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK 0x00000F00U
4430 /*- Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre
4431 s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid
4432 Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of
4433 this field. If set to 15, this column address bit is set to 0.*/
4434 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL
4435 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT
4436 #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK
4437 #define DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL 0x00000000
4438 #define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT 0
4439 #define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK 0x0000000FU
4441 /*- Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width
4442 mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must
4443 e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern
4444 l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati
4445 n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a
4446 dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.*/
4447 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL
4448 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT
4449 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK
4450 #define DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL 0x00000000
4451 #define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT 8
4452 #define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK 0x00000F00U
4454 /*- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width
4455 mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED.
4456 To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d
4457 termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per
4458 JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address
4459 bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h
4460 nce column bit 10 is used.*/
4461 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL
4462 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT
4463 #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK
4464 #define DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL 0x00000000
4465 #define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT 0
4466 #define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK 0x0000000FU
4468 /*Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre
4469 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0.*/
4470 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL
4471 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT
4472 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK
4473 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL 0x00000000
4474 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT 24
4475 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK 0x0F000000U
4477 /*Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address
4478 bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF
4479 ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value
4480 5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.*/
4481 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL
4482 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT
4483 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK
4484 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL 0x00000000
4485 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT 16
4486 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK 0x000F0000U
4488 /*Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo
4489 each of the row address bits is determined by adding the internal base to the value of this field.*/
4490 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL
4491 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT
4492 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK
4493 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL 0x00000000
4494 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT 8
4495 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK 0x00000F00U
4497 /*Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo
4498 each of the row address bits is determined by adding the internal base to the value of this field.*/
4499 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL
4500 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT
4501 #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK
4502 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL 0x00000000
4503 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT 0
4504 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK 0x0000000FU
4506 /*Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address
4507 having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on
4508 y in designs configured to support LPDDR3.*/
4509 #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL
4510 #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT
4511 #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK
4512 #define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL 0x00000000
4513 #define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT 31
4514 #define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK 0x80000000U
4516 /*Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre
4517 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0.*/
4518 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL
4519 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT
4520 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK
4521 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL 0x00000000
4522 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT 24
4523 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK 0x0F000000U
4525 /*Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre
4526 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0.*/
4527 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL
4528 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT
4529 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK
4530 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL 0x00000000
4531 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT 16
4532 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK 0x000F0000U
4534 /*Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre
4535 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0.*/
4536 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL
4537 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT
4538 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK
4539 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL 0x00000000
4540 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT 8
4541 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK 0x00000F00U
4543 /*Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre
4544 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0.*/
4545 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL
4546 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT
4547 #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK
4548 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL 0x00000000
4549 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT 0
4550 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK 0x0000000FU
4552 /*Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre
4553 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0.*/
4554 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL
4555 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT
4556 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK
4557 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL 0x00000000
4558 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT 8
4559 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK 0x00000F00U
4561 /*Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre
4562 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0.*/
4563 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL
4564 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT
4565 #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK
4566 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL 0x00000000
4567 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT 0
4568 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK 0x0000000FU
4570 /*Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF
4571 address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If
4572 et to 31, bank group address bit 1 is set to 0.*/
4573 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL
4574 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT
4575 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK
4576 #define DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL 0x00000000
4577 #define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT 8
4578 #define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK 0x00001F00U
4580 /*Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address
4581 bit for each of the bank group address bits is determined by adding the internal base to the value of this field.*/
4582 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL
4583 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT
4584 #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK
4585 #define DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL 0x00000000
4586 #define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT 0
4587 #define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK 0x0000001FU
4589 /*Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f
4590 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
4591 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
4592 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL
4593 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT
4594 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK
4595 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL 0x00000000
4596 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT 24
4597 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK 0x0F000000U
4599 /*Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f
4600 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
4601 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
4602 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL
4603 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT
4604 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK
4605 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL 0x00000000
4606 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT 16
4607 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK 0x000F0000U
4609 /*Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo
4610 each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
4611 d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
4612 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL
4613 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT
4614 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK
4615 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL 0x00000000
4616 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT 8
4617 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK 0x00000F00U
4619 /*Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo
4620 each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
4621 d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
4622 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL
4623 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT
4624 #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK
4625 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL 0x00000000
4626 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT 0
4627 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK 0x0000000FU
4629 /*Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f
4630 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
4631 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
4632 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL
4633 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT
4634 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK
4635 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL 0x00000000
4636 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT 24
4637 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK 0x0F000000U
4639 /*Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f
4640 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
4641 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
4642 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL
4643 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT
4644 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK
4645 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL 0x00000000
4646 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT 16
4647 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK 0x000F0000U
4649 /*Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f
4650 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
4651 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
4652 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL
4653 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT
4654 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK
4655 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL 0x00000000
4656 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT 8
4657 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK 0x00000F00U
4659 /*Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f
4660 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
4661 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
4662 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL
4663 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT
4664 #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK
4665 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL 0x00000000
4666 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT 0
4667 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK 0x0000000FU
4669 /*Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit
4670 or each of the row address bits is determined by adding the internal base to the value of this field. This register field is
4671 sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
4672 #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL
4673 #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT
4674 #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK
4675 #define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL
4676 #define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT 0
4677 #define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK 0x0000000FU
4679 /*Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/
4680 67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: -
4681 L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1
4682 CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)*/
4683 #undef DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL
4684 #undef DDRC_ODTCFG_WR_ODT_HOLD_SHIFT
4685 #undef DDRC_ODTCFG_WR_ODT_HOLD_MASK
4686 #define DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL 0x04000400
4687 #define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT 24
4688 #define DDRC_ODTCFG_WR_ODT_HOLD_MASK 0x0F000000U
4690 /*The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must
4691 remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/
4692 67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation
4693 DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))*/
4694 #undef DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL
4695 #undef DDRC_ODTCFG_WR_ODT_DELAY_SHIFT
4696 #undef DDRC_ODTCFG_WR_ODT_DELAY_MASK
4697 #define DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL 0x04000400
4698 #define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT 16
4699 #define DDRC_ODTCFG_WR_ODT_DELAY_MASK 0x001F0000U
4701 /*Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066)
4702 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (
4703 tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC
4705 #undef DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL
4706 #undef DDRC_ODTCFG_RD_ODT_HOLD_SHIFT
4707 #undef DDRC_ODTCFG_RD_ODT_HOLD_MASK
4708 #define DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL 0x04000400
4709 #define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT 8
4710 #define DDRC_ODTCFG_RD_ODT_HOLD_MASK 0x00000F00U
4712 /*The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must
4713 emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066),
4714 CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C
4715 L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK
4716 write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0,
4717 uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)*/
4718 #undef DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL
4719 #undef DDRC_ODTCFG_RD_ODT_DELAY_SHIFT
4720 #undef DDRC_ODTCFG_RD_ODT_DELAY_MASK
4721 #define DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL 0x04000400
4722 #define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT 2
4723 #define DDRC_ODTCFG_RD_ODT_DELAY_MASK 0x0000007CU
4725 /*Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can
4726 e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
4727 etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks*/
4728 #undef DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL
4729 #undef DDRC_ODTMAP_RANK1_RD_ODT_SHIFT
4730 #undef DDRC_ODTMAP_RANK1_RD_ODT_MASK
4731 #define DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL 0x00002211
4732 #define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT 12
4733 #define DDRC_ODTMAP_RANK1_RD_ODT_MASK 0x00003000U
4735 /*Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b
4736 turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
4737 etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks*/
4738 #undef DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL
4739 #undef DDRC_ODTMAP_RANK1_WR_ODT_SHIFT
4740 #undef DDRC_ODTMAP_RANK1_WR_ODT_MASK
4741 #define DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL 0x00002211
4742 #define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT 8
4743 #define DDRC_ODTMAP_RANK1_WR_ODT_MASK 0x00000300U
4745 /*Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can
4746 e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
4747 etc. For each rank, set its bit to 1 to enable its ODT.*/
4748 #undef DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL
4749 #undef DDRC_ODTMAP_RANK0_RD_ODT_SHIFT
4750 #undef DDRC_ODTMAP_RANK0_RD_ODT_MASK
4751 #define DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL 0x00002211
4752 #define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT 4
4753 #define DDRC_ODTMAP_RANK0_RD_ODT_MASK 0x00000030U
4755 /*Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b
4756 turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
4757 etc. For each rank, set its bit to 1 to enable its ODT.*/
4758 #undef DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL
4759 #undef DDRC_ODTMAP_RANK0_WR_ODT_SHIFT
4760 #undef DDRC_ODTMAP_RANK0_WR_ODT_MASK
4761 #define DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL 0x00002211
4762 #define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT 0
4763 #define DDRC_ODTMAP_RANK0_WR_ODT_MASK 0x00000003U
4765 /*When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is
4766 non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t
4767 ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this
4768 egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true.
4769 OR PERFORMANCE ONLY*/
4770 #undef DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL
4771 #undef DDRC_SCHED_RDWR_IDLE_GAP_SHIFT
4772 #undef DDRC_SCHED_RDWR_IDLE_GAP_MASK
4773 #define DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL 0x00002005
4774 #define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT 24
4775 #define DDRC_SCHED_RDWR_IDLE_GAP_MASK 0x7F000000U
4778 #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL
4779 #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT
4780 #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK
4781 #define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL 0x00002005
4782 #define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT 16
4783 #define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK 0x00FF0000U
4785 /*Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i
4786 the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries
4787 to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high
4788 priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les
4789 than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar
4790 sing out of single bit error correction RMW operation.*/
4791 #undef DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL
4792 #undef DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT
4793 #undef DDRC_SCHED_LPR_NUM_ENTRIES_MASK
4794 #define DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL 0x00002005
4795 #define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT 8
4796 #define DDRC_SCHED_LPR_NUM_ENTRIES_MASK 0x00003F00U
4798 /*If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri
4799 e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this
4800 egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca
4801 es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed
4802 s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n
4803 ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open
4804 age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea
4805 ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY.*/
4806 #undef DDRC_SCHED_PAGECLOSE_DEFVAL
4807 #undef DDRC_SCHED_PAGECLOSE_SHIFT
4808 #undef DDRC_SCHED_PAGECLOSE_MASK
4809 #define DDRC_SCHED_PAGECLOSE_DEFVAL 0x00002005
4810 #define DDRC_SCHED_PAGECLOSE_SHIFT 2
4811 #define DDRC_SCHED_PAGECLOSE_MASK 0x00000004U
4813 /*If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.*/
4814 #undef DDRC_SCHED_PREFER_WRITE_DEFVAL
4815 #undef DDRC_SCHED_PREFER_WRITE_SHIFT
4816 #undef DDRC_SCHED_PREFER_WRITE_MASK
4817 #define DDRC_SCHED_PREFER_WRITE_DEFVAL 0x00002005
4818 #define DDRC_SCHED_PREFER_WRITE_SHIFT 1
4819 #define DDRC_SCHED_PREFER_WRITE_MASK 0x00000002U
4821 /*Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio
4822 ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si
4823 e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t
4824 ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY.*/
4825 #undef DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL
4826 #undef DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT
4827 #undef DDRC_SCHED_FORCE_LOW_PRI_N_MASK
4828 #define DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL 0x00002005
4829 #define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT 0
4830 #define DDRC_SCHED_FORCE_LOW_PRI_N_MASK 0x00000001U
4832 /*Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o
4833 transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.*/
4834 #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL
4835 #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT
4836 #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK
4837 #define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL 0x0F00007F
4838 #define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT 24
4839 #define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK 0xFF000000U
4841 /*Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis
4842 er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not
4843 be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.*/
4844 #undef DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL
4845 #undef DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT
4846 #undef DDRC_PERFLPR1_LPR_MAX_STARVE_MASK
4847 #define DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL 0x0F00007F
4848 #define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT 0
4849 #define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK 0x0000FFFFU
4851 /*Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of
4852 transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.*/
4853 #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL
4854 #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT
4855 #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK
4856 #define DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL 0x0F00007F
4857 #define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT 24
4858 #define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK 0xFF000000U
4860 /*Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist
4861 r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not
4862 e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.*/
4863 #undef DDRC_PERFWR1_W_MAX_STARVE_DEFVAL
4864 #undef DDRC_PERFWR1_W_MAX_STARVE_SHIFT
4865 #undef DDRC_PERFWR1_W_MAX_STARVE_MASK
4866 #define DDRC_PERFWR1_W_MAX_STARVE_DEFVAL 0x0F00007F
4867 #define DDRC_PERFWR1_W_MAX_STARVE_SHIFT 0
4868 #define DDRC_PERFWR1_W_MAX_STARVE_MASK 0x0000FFFFU
4870 /*All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for
4871 all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and
4872 wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su
4874 #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL
4875 #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT
4876 #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK
4877 #define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL
4878 #define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT 0
4879 #define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK 0x00000001U
4881 /*When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo
4882 lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d
4883 s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY.*/
4884 #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL
4885 #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT
4886 #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK
4887 #define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL 0x00000000
4888 #define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT 4
4889 #define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK 0x00000010U
4891 /*When 1, disable write combine. FOR DEBUG ONLY*/
4892 #undef DDRC_DBG0_DIS_WC_DEFVAL
4893 #undef DDRC_DBG0_DIS_WC_SHIFT
4894 #undef DDRC_DBG0_DIS_WC_MASK
4895 #define DDRC_DBG0_DIS_WC_DEFVAL 0x00000000
4896 #define DDRC_DBG0_DIS_WC_SHIFT 0
4897 #define DDRC_DBG0_DIS_WC_MASK 0x00000001U
4899 /*Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1,
4900 the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this
4901 register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank
4902 _refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static
4903 and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0).*/
4904 #undef DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL
4905 #undef DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT
4906 #undef DDRC_DBGCMD_HW_REF_ZQ_EN_MASK
4907 #define DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL 0x00000000
4908 #define DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT 31
4909 #define DDRC_DBGCMD_HW_REF_ZQ_EN_MASK 0x80000000U
4911 /*Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in
4912 he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.*/
4913 #undef DDRC_DBGCMD_CTRLUPD_DEFVAL
4914 #undef DDRC_DBGCMD_CTRLUPD_SHIFT
4915 #undef DDRC_DBGCMD_CTRLUPD_MASK
4916 #define DDRC_DBGCMD_CTRLUPD_DEFVAL 0x00000000
4917 #define DDRC_DBGCMD_CTRLUPD_SHIFT 5
4918 #define DDRC_DBGCMD_CTRLUPD_MASK 0x00000020U
4920 /*Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to
4921 he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w
4922 en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor
4923 d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M
4925 #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL
4926 #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT
4927 #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK
4928 #define DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL 0x00000000
4929 #define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT 4
4930 #define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK 0x00000010U
4932 /*Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1
4933 refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
4934 be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
4935 wn operating modes or Maximum Power Saving Mode.*/
4936 #undef DDRC_DBGCMD_RANK1_REFRESH_DEFVAL
4937 #undef DDRC_DBGCMD_RANK1_REFRESH_SHIFT
4938 #undef DDRC_DBGCMD_RANK1_REFRESH_MASK
4939 #define DDRC_DBGCMD_RANK1_REFRESH_DEFVAL 0x00000000
4940 #define DDRC_DBGCMD_RANK1_REFRESH_SHIFT 1
4941 #define DDRC_DBGCMD_RANK1_REFRESH_MASK 0x00000002U
4943 /*Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0
4944 refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
4945 be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
4946 wn operating modes or Maximum Power Saving Mode.*/
4947 #undef DDRC_DBGCMD_RANK0_REFRESH_DEFVAL
4948 #undef DDRC_DBGCMD_RANK0_REFRESH_SHIFT
4949 #undef DDRC_DBGCMD_RANK0_REFRESH_MASK
4950 #define DDRC_DBGCMD_RANK0_REFRESH_DEFVAL 0x00000000
4951 #define DDRC_DBGCMD_RANK0_REFRESH_SHIFT 0
4952 #define DDRC_DBGCMD_RANK0_REFRESH_MASK 0x00000001U
4954 /*Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back
4955 egister to 1 once programming is done.*/
4956 #undef DDRC_SWCTL_SW_DONE_DEFVAL
4957 #undef DDRC_SWCTL_SW_DONE_SHIFT
4958 #undef DDRC_SWCTL_SW_DONE_MASK
4959 #define DDRC_SWCTL_SW_DONE_DEFVAL
4960 #define DDRC_SWCTL_SW_DONE_SHIFT 0
4961 #define DDRC_SWCTL_SW_DONE_MASK 0x00000001U
4963 /*Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t
4964 e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo
4965 h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par
4966 ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc
4967 _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_
4968 ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP
4969 DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4
4970 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share
4972 #undef DDRC_PCCFG_BL_EXP_MODE_DEFVAL
4973 #undef DDRC_PCCFG_BL_EXP_MODE_SHIFT
4974 #undef DDRC_PCCFG_BL_EXP_MODE_MASK
4975 #define DDRC_PCCFG_BL_EXP_MODE_DEFVAL 0x00000000
4976 #define DDRC_PCCFG_BL_EXP_MODE_SHIFT 8
4977 #define DDRC_PCCFG_BL_EXP_MODE_MASK 0x00000100U
4979 /*Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P
4980 rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p
4981 ge DDRC transactions.*/
4982 #undef DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL
4983 #undef DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT
4984 #undef DDRC_PCCFG_PAGEMATCH_LIMIT_MASK
4985 #define DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL 0x00000000
4986 #define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT 4
4987 #define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK 0x00000010U
4989 /*If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based
4990 n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica
4991 _lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.*/
4992 #undef DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL
4993 #undef DDRC_PCCFG_GO2CRITICAL_EN_SHIFT
4994 #undef DDRC_PCCFG_GO2CRITICAL_EN_MASK
4995 #define DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL 0x00000000
4996 #define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT 0
4997 #define DDRC_PCCFG_GO2CRITICAL_EN_MASK 0x00000001U
4999 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5000 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5002 #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL
5003 #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT
5004 #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK
5005 #define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000
5006 #define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT 14
5007 #define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U
5009 /*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
5010 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
5011 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
5012 ess handshaking (it is not associated with any particular command).*/
5013 #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL
5014 #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT
5015 #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK
5016 #define DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL 0x00000000
5017 #define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT 13
5018 #define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK 0x00002000U
5020 /*If set to 1, enables aging function for the read channel of the port.*/
5021 #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL
5022 #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT
5023 #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK
5024 #define DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL 0x00000000
5025 #define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT 12
5026 #define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK 0x00001000U
5028 /*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
5029 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5030 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
5031 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
5032 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
5033 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
5034 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
5035 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
5036 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
5037 he two LSBs of this register field are tied internally to 2'b00.*/
5038 #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL
5039 #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT
5040 #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK
5041 #define DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL 0x00000000
5042 #define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT 0
5043 #define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK 0x000003FFU
5045 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5046 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5048 #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL
5049 #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT
5050 #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK
5051 #define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000
5052 #define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT 14
5053 #define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U
5055 /*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
5056 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
5057 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
5058 not associated with any particular command).*/
5059 #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL
5060 #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT
5061 #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK
5062 #define DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL 0x00004000
5063 #define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT 13
5064 #define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK 0x00002000U
5066 /*If set to 1, enables aging function for the write channel of the port.*/
5067 #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL
5068 #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT
5069 #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK
5070 #define DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL 0x00004000
5071 #define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT 12
5072 #define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK 0x00001000U
5074 /*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
5075 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5076 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
5077 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
5078 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
5079 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
5080 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
5081 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
5082 #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL
5083 #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT
5084 #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK
5085 #define DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL 0x00004000
5086 #define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT 0
5087 #define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK 0x000003FFU
5090 #undef DDRC_PCTRL_0_PORT_EN_DEFVAL
5091 #undef DDRC_PCTRL_0_PORT_EN_SHIFT
5092 #undef DDRC_PCTRL_0_PORT_EN_MASK
5093 #define DDRC_PCTRL_0_PORT_EN_DEFVAL
5094 #define DDRC_PCTRL_0_PORT_EN_SHIFT 0
5095 #define DDRC_PCTRL_0_PORT_EN_MASK 0x00000001U
5097 /*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
5098 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
5099 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5100 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL
5101 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT
5102 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK
5103 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL 0x00000000
5104 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT 20
5105 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK 0x00300000U
5107 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
5108 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
5109 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5110 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL
5111 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT
5112 #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK
5113 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL 0x00000000
5114 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT 16
5115 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK 0x00030000U
5117 /*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
5118 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
5119 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
5121 #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL
5122 #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT
5123 #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK
5124 #define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL 0x00000000
5125 #define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT 0
5126 #define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK 0x0000000FU
5128 /*Specifies the timeout value for transactions mapped to the red address queue.*/
5129 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL
5130 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT
5131 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK
5132 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000
5133 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT 16
5134 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U
5136 /*Specifies the timeout value for transactions mapped to the blue address queue.*/
5137 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL
5138 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT
5139 #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK
5140 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000
5141 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT 0
5142 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU
5144 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5145 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5147 #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL
5148 #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT
5149 #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK
5150 #define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000
5151 #define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT 14
5152 #define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U
5154 /*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
5155 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
5156 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
5157 ess handshaking (it is not associated with any particular command).*/
5158 #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL
5159 #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT
5160 #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK
5161 #define DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL 0x00000000
5162 #define DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT 13
5163 #define DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK 0x00002000U
5165 /*If set to 1, enables aging function for the read channel of the port.*/
5166 #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL
5167 #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT
5168 #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK
5169 #define DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL 0x00000000
5170 #define DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT 12
5171 #define DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK 0x00001000U
5173 /*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
5174 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5175 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
5176 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
5177 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
5178 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
5179 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
5180 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
5181 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
5182 he two LSBs of this register field are tied internally to 2'b00.*/
5183 #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL
5184 #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT
5185 #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK
5186 #define DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL 0x00000000
5187 #define DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT 0
5188 #define DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK 0x000003FFU
5190 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5191 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5193 #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL
5194 #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT
5195 #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK
5196 #define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000
5197 #define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT 14
5198 #define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U
5200 /*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
5201 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
5202 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
5203 not associated with any particular command).*/
5204 #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL
5205 #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT
5206 #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK
5207 #define DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL 0x00004000
5208 #define DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT 13
5209 #define DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK 0x00002000U
5211 /*If set to 1, enables aging function for the write channel of the port.*/
5212 #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL
5213 #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT
5214 #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK
5215 #define DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL 0x00004000
5216 #define DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT 12
5217 #define DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK 0x00001000U
5219 /*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
5220 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5221 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
5222 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
5223 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
5224 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
5225 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
5226 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
5227 #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL
5228 #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT
5229 #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK
5230 #define DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL 0x00004000
5231 #define DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT 0
5232 #define DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK 0x000003FFU
5235 #undef DDRC_PCTRL_1_PORT_EN_DEFVAL
5236 #undef DDRC_PCTRL_1_PORT_EN_SHIFT
5237 #undef DDRC_PCTRL_1_PORT_EN_MASK
5238 #define DDRC_PCTRL_1_PORT_EN_DEFVAL
5239 #define DDRC_PCTRL_1_PORT_EN_SHIFT 0
5240 #define DDRC_PCTRL_1_PORT_EN_MASK 0x00000001U
5242 /*This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address
5243 ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2
5244 s set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5245 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL
5246 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT
5247 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK
5248 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL 0x02000E00
5249 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT 24
5250 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK 0x03000000U
5252 /*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
5253 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
5254 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5255 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL
5256 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT
5257 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK
5258 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL 0x02000E00
5259 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT 20
5260 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK 0x00300000U
5262 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
5263 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
5264 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5265 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL
5266 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT
5267 #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK
5268 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL 0x02000E00
5269 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT 16
5270 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK 0x00030000U
5272 /*Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
5273 el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
5274 directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers
5275 ust be set to distinct values.*/
5276 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL
5277 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT
5278 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK
5279 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00
5280 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT 8
5281 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK 0x00000F00U
5283 /*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
5284 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
5285 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
5287 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL
5288 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT
5289 #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK
5290 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00
5291 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT 0
5292 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK 0x0000000FU
5294 /*Specifies the timeout value for transactions mapped to the red address queue.*/
5295 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL
5296 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT
5297 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK
5298 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000
5299 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT 16
5300 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U
5302 /*Specifies the timeout value for transactions mapped to the blue address queue.*/
5303 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL
5304 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT
5305 #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK
5306 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000
5307 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT 0
5308 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU
5310 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5311 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5313 #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL
5314 #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT
5315 #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK
5316 #define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000
5317 #define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT 14
5318 #define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U
5320 /*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
5321 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
5322 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
5323 ess handshaking (it is not associated with any particular command).*/
5324 #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL
5325 #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT
5326 #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK
5327 #define DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL 0x00000000
5328 #define DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT 13
5329 #define DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK 0x00002000U
5331 /*If set to 1, enables aging function for the read channel of the port.*/
5332 #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL
5333 #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT
5334 #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK
5335 #define DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL 0x00000000
5336 #define DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT 12
5337 #define DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK 0x00001000U
5339 /*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
5340 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5341 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
5342 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
5343 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
5344 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
5345 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
5346 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
5347 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
5348 he two LSBs of this register field are tied internally to 2'b00.*/
5349 #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL
5350 #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT
5351 #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK
5352 #define DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL 0x00000000
5353 #define DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT 0
5354 #define DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK 0x000003FFU
5356 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5357 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5359 #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL
5360 #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT
5361 #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK
5362 #define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000
5363 #define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT 14
5364 #define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U
5366 /*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
5367 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
5368 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
5369 not associated with any particular command).*/
5370 #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL
5371 #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT
5372 #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK
5373 #define DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL 0x00004000
5374 #define DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT 13
5375 #define DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK 0x00002000U
5377 /*If set to 1, enables aging function for the write channel of the port.*/
5378 #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL
5379 #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT
5380 #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK
5381 #define DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL 0x00004000
5382 #define DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT 12
5383 #define DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK 0x00001000U
5385 /*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
5386 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5387 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
5388 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
5389 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
5390 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
5391 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
5392 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
5393 #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL
5394 #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT
5395 #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK
5396 #define DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL 0x00004000
5397 #define DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT 0
5398 #define DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK 0x000003FFU
5401 #undef DDRC_PCTRL_2_PORT_EN_DEFVAL
5402 #undef DDRC_PCTRL_2_PORT_EN_SHIFT
5403 #undef DDRC_PCTRL_2_PORT_EN_MASK
5404 #define DDRC_PCTRL_2_PORT_EN_DEFVAL
5405 #define DDRC_PCTRL_2_PORT_EN_SHIFT 0
5406 #define DDRC_PCTRL_2_PORT_EN_MASK 0x00000001U
5408 /*This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address
5409 ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2
5410 s set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5411 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL
5412 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT
5413 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK
5414 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL 0x02000E00
5415 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT 24
5416 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK 0x03000000U
5418 /*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
5419 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
5420 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5421 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL
5422 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT
5423 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK
5424 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL 0x02000E00
5425 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT 20
5426 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK 0x00300000U
5428 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
5429 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
5430 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5431 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL
5432 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT
5433 #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK
5434 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL 0x02000E00
5435 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT 16
5436 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK 0x00030000U
5438 /*Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
5439 el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
5440 directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers
5441 ust be set to distinct values.*/
5442 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL
5443 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT
5444 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK
5445 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00
5446 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT 8
5447 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK 0x00000F00U
5449 /*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
5450 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
5451 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
5453 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL
5454 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT
5455 #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK
5456 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00
5457 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT 0
5458 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK 0x0000000FU
5460 /*Specifies the timeout value for transactions mapped to the red address queue.*/
5461 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL
5462 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT
5463 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK
5464 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000
5465 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT 16
5466 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U
5468 /*Specifies the timeout value for transactions mapped to the blue address queue.*/
5469 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL
5470 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT
5471 #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK
5472 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000
5473 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT 0
5474 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU
5476 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5477 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5479 #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL
5480 #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT
5481 #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK
5482 #define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000
5483 #define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT 14
5484 #define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U
5486 /*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
5487 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
5488 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
5489 ess handshaking (it is not associated with any particular command).*/
5490 #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL
5491 #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT
5492 #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK
5493 #define DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL 0x00000000
5494 #define DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT 13
5495 #define DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK 0x00002000U
5497 /*If set to 1, enables aging function for the read channel of the port.*/
5498 #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL
5499 #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT
5500 #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK
5501 #define DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL 0x00000000
5502 #define DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT 12
5503 #define DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK 0x00001000U
5505 /*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
5506 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5507 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
5508 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
5509 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
5510 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
5511 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
5512 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
5513 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
5514 he two LSBs of this register field are tied internally to 2'b00.*/
5515 #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL
5516 #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT
5517 #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK
5518 #define DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL 0x00000000
5519 #define DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT 0
5520 #define DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK 0x000003FFU
5522 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5523 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5525 #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL
5526 #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT
5527 #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK
5528 #define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000
5529 #define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT 14
5530 #define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U
5532 /*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
5533 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
5534 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
5535 not associated with any particular command).*/
5536 #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL
5537 #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT
5538 #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK
5539 #define DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL 0x00004000
5540 #define DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT 13
5541 #define DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK 0x00002000U
5543 /*If set to 1, enables aging function for the write channel of the port.*/
5544 #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL
5545 #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT
5546 #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK
5547 #define DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL 0x00004000
5548 #define DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT 12
5549 #define DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK 0x00001000U
5551 /*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
5552 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5553 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
5554 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
5555 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
5556 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
5557 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
5558 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
5559 #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL
5560 #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT
5561 #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK
5562 #define DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL 0x00004000
5563 #define DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT 0
5564 #define DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK 0x000003FFU
5567 #undef DDRC_PCTRL_3_PORT_EN_DEFVAL
5568 #undef DDRC_PCTRL_3_PORT_EN_SHIFT
5569 #undef DDRC_PCTRL_3_PORT_EN_MASK
5570 #define DDRC_PCTRL_3_PORT_EN_DEFVAL
5571 #define DDRC_PCTRL_3_PORT_EN_SHIFT 0
5572 #define DDRC_PCTRL_3_PORT_EN_MASK 0x00000001U
5574 /*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
5575 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
5576 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5577 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL
5578 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT
5579 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK
5580 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL 0x00000000
5581 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT 20
5582 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK 0x00300000U
5584 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
5585 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
5586 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5587 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL
5588 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT
5589 #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK
5590 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL 0x00000000
5591 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT 16
5592 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK 0x00030000U
5594 /*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
5595 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
5596 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
5598 #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL
5599 #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT
5600 #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK
5601 #define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL 0x00000000
5602 #define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT 0
5603 #define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK 0x0000000FU
5605 /*Specifies the timeout value for transactions mapped to the red address queue.*/
5606 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL
5607 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT
5608 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK
5609 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000
5610 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT 16
5611 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U
5613 /*Specifies the timeout value for transactions mapped to the blue address queue.*/
5614 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL
5615 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT
5616 #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK
5617 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000
5618 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT 0
5619 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU
5621 /*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5622 VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/
5623 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL
5624 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT
5625 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK
5626 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL 0x00000000
5627 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT 20
5628 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK 0x00300000U
5630 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5631 VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/
5632 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL
5633 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT
5634 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK
5635 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL 0x00000000
5636 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT 16
5637 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK 0x00030000U
5639 /*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
5640 rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
5641 s to higher port priority.*/
5642 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL
5643 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT
5644 #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK
5645 #define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL 0x00000000
5646 #define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT 0
5647 #define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK 0x0000000FU
5649 /*Specifies the timeout value for write transactions.*/
5650 #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL
5651 #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT
5652 #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK
5653 #define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL
5654 #define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT 0
5655 #define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK 0x000007FFU
5657 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5658 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5660 #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL
5661 #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT
5662 #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK
5663 #define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000
5664 #define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT 14
5665 #define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U
5667 /*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
5668 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
5669 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
5670 ess handshaking (it is not associated with any particular command).*/
5671 #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL
5672 #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT
5673 #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK
5674 #define DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL 0x00000000
5675 #define DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT 13
5676 #define DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK 0x00002000U
5678 /*If set to 1, enables aging function for the read channel of the port.*/
5679 #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL
5680 #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT
5681 #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK
5682 #define DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL 0x00000000
5683 #define DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT 12
5684 #define DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK 0x00001000U
5686 /*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
5687 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5688 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
5689 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
5690 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
5691 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
5692 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
5693 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
5694 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
5695 he two LSBs of this register field are tied internally to 2'b00.*/
5696 #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL
5697 #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT
5698 #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK
5699 #define DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL 0x00000000
5700 #define DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT 0
5701 #define DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK 0x000003FFU
5703 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5704 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5706 #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL
5707 #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT
5708 #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK
5709 #define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000
5710 #define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT 14
5711 #define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U
5713 /*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
5714 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
5715 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
5716 not associated with any particular command).*/
5717 #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL
5718 #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT
5719 #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK
5720 #define DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL 0x00004000
5721 #define DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT 13
5722 #define DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK 0x00002000U
5724 /*If set to 1, enables aging function for the write channel of the port.*/
5725 #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL
5726 #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT
5727 #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK
5728 #define DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL 0x00004000
5729 #define DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT 12
5730 #define DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK 0x00001000U
5732 /*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
5733 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5734 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
5735 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
5736 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
5737 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
5738 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
5739 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
5740 #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL
5741 #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT
5742 #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK
5743 #define DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL 0x00004000
5744 #define DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT 0
5745 #define DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK 0x000003FFU
5748 #undef DDRC_PCTRL_4_PORT_EN_DEFVAL
5749 #undef DDRC_PCTRL_4_PORT_EN_SHIFT
5750 #undef DDRC_PCTRL_4_PORT_EN_MASK
5751 #define DDRC_PCTRL_4_PORT_EN_DEFVAL
5752 #define DDRC_PCTRL_4_PORT_EN_SHIFT 0
5753 #define DDRC_PCTRL_4_PORT_EN_MASK 0x00000001U
5755 /*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
5756 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
5757 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5758 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL
5759 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT
5760 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK
5761 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL 0x00000000
5762 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT 20
5763 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK 0x00300000U
5765 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
5766 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
5767 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5768 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL
5769 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT
5770 #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK
5771 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL 0x00000000
5772 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT 16
5773 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK 0x00030000U
5775 /*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
5776 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
5777 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
5779 #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL
5780 #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT
5781 #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK
5782 #define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL 0x00000000
5783 #define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT 0
5784 #define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK 0x0000000FU
5786 /*Specifies the timeout value for transactions mapped to the red address queue.*/
5787 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL
5788 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT
5789 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK
5790 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000
5791 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT 16
5792 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U
5794 /*Specifies the timeout value for transactions mapped to the blue address queue.*/
5795 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL
5796 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT
5797 #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK
5798 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000
5799 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT 0
5800 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU
5802 /*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5803 VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/
5804 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL
5805 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT
5806 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK
5807 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL 0x00000000
5808 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT 20
5809 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK 0x00300000U
5811 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5812 VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/
5813 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL
5814 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT
5815 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK
5816 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL 0x00000000
5817 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT 16
5818 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK 0x00030000U
5820 /*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
5821 rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
5822 s to higher port priority.*/
5823 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL
5824 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT
5825 #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK
5826 #define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL 0x00000000
5827 #define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT 0
5828 #define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK 0x0000000FU
5830 /*Specifies the timeout value for write transactions.*/
5831 #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL
5832 #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT
5833 #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK
5834 #define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL
5835 #define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT 0
5836 #define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK 0x000007FFU
5838 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5839 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5841 #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL
5842 #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT
5843 #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK
5844 #define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000
5845 #define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT 14
5846 #define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U
5848 /*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
5849 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
5850 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
5851 ess handshaking (it is not associated with any particular command).*/
5852 #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL
5853 #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT
5854 #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK
5855 #define DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL 0x00000000
5856 #define DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT 13
5857 #define DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK 0x00002000U
5859 /*If set to 1, enables aging function for the read channel of the port.*/
5860 #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL
5861 #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT
5862 #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK
5863 #define DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL 0x00000000
5864 #define DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT 12
5865 #define DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK 0x00001000U
5867 /*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
5868 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5869 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
5870 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
5871 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
5872 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
5873 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
5874 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
5875 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
5876 he two LSBs of this register field are tied internally to 2'b00.*/
5877 #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL
5878 #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT
5879 #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK
5880 #define DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL 0x00000000
5881 #define DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT 0
5882 #define DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK 0x000003FFU
5884 /*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5885 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5887 #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL
5888 #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT
5889 #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK
5890 #define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000
5891 #define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT 14
5892 #define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U
5894 /*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
5895 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
5896 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
5897 not associated with any particular command).*/
5898 #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL
5899 #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT
5900 #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK
5901 #define DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL 0x00004000
5902 #define DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT 13
5903 #define DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK 0x00002000U
5905 /*If set to 1, enables aging function for the write channel of the port.*/
5906 #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL
5907 #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT
5908 #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK
5909 #define DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL 0x00004000
5910 #define DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT 12
5911 #define DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK 0x00001000U
5913 /*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
5914 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5915 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
5916 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
5917 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
5918 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
5919 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
5920 ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
5921 #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL
5922 #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT
5923 #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK
5924 #define DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL 0x00004000
5925 #define DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT 0
5926 #define DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK 0x000003FFU
5929 #undef DDRC_PCTRL_5_PORT_EN_DEFVAL
5930 #undef DDRC_PCTRL_5_PORT_EN_SHIFT
5931 #undef DDRC_PCTRL_5_PORT_EN_MASK
5932 #define DDRC_PCTRL_5_PORT_EN_DEFVAL
5933 #define DDRC_PCTRL_5_PORT_EN_SHIFT 0
5934 #define DDRC_PCTRL_5_PORT_EN_MASK 0x00000001U
5936 /*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
5937 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
5938 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5939 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL
5940 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT
5941 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK
5942 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL 0x00000000
5943 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT 20
5944 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK 0x00300000U
5946 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
5947 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
5948 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
5949 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL
5950 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT
5951 #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK
5952 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL 0x00000000
5953 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT 16
5954 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK 0x00030000U
5956 /*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
5957 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
5958 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
5960 #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL
5961 #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT
5962 #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK
5963 #define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL 0x00000000
5964 #define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT 0
5965 #define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK 0x0000000FU
5967 /*Specifies the timeout value for transactions mapped to the red address queue.*/
5968 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL
5969 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT
5970 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK
5971 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000
5972 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT 16
5973 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U
5975 /*Specifies the timeout value for transactions mapped to the blue address queue.*/
5976 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL
5977 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT
5978 #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK
5979 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000
5980 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT 0
5981 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU
5983 /*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5984 VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/
5985 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL
5986 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT
5987 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK
5988 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL 0x00000000
5989 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT 20
5990 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK 0x00300000U
5992 /*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5993 VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/
5994 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL
5995 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT
5996 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK
5997 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL 0x00000000
5998 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT 16
5999 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK 0x00030000U
6001 /*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
6002 rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
6003 s to higher port priority.*/
6004 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL
6005 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT
6006 #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK
6007 #define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL 0x00000000
6008 #define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT 0
6009 #define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK 0x0000000FU
6011 /*Specifies the timeout value for write transactions.*/
6012 #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL
6013 #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT
6014 #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK
6015 #define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL
6016 #define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT 0
6017 #define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK 0x000007FFU
6019 /*Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
6020 by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).*/
6021 #undef DDRC_SARBASE0_BASE_ADDR_DEFVAL
6022 #undef DDRC_SARBASE0_BASE_ADDR_SHIFT
6023 #undef DDRC_SARBASE0_BASE_ADDR_MASK
6024 #define DDRC_SARBASE0_BASE_ADDR_DEFVAL
6025 #define DDRC_SARBASE0_BASE_ADDR_SHIFT 0
6026 #define DDRC_SARBASE0_BASE_ADDR_MASK 0x000001FFU
6028 /*Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
6029 e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1.
6030 or example, if register is programmed to 0, region will have 1 block.*/
6031 #undef DDRC_SARSIZE0_NBLOCKS_DEFVAL
6032 #undef DDRC_SARSIZE0_NBLOCKS_SHIFT
6033 #undef DDRC_SARSIZE0_NBLOCKS_MASK
6034 #define DDRC_SARSIZE0_NBLOCKS_DEFVAL
6035 #define DDRC_SARSIZE0_NBLOCKS_SHIFT 0
6036 #define DDRC_SARSIZE0_NBLOCKS_MASK 0x000000FFU
6038 /*Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
6039 by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).*/
6040 #undef DDRC_SARBASE1_BASE_ADDR_DEFVAL
6041 #undef DDRC_SARBASE1_BASE_ADDR_SHIFT
6042 #undef DDRC_SARBASE1_BASE_ADDR_MASK
6043 #define DDRC_SARBASE1_BASE_ADDR_DEFVAL
6044 #define DDRC_SARBASE1_BASE_ADDR_SHIFT 0
6045 #define DDRC_SARBASE1_BASE_ADDR_MASK 0x000001FFU
6047 /*Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
6048 e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1.
6049 or example, if register is programmed to 0, region will have 1 block.*/
6050 #undef DDRC_SARSIZE1_NBLOCKS_DEFVAL
6051 #undef DDRC_SARSIZE1_NBLOCKS_SHIFT
6052 #undef DDRC_SARSIZE1_NBLOCKS_MASK
6053 #define DDRC_SARSIZE1_NBLOCKS_DEFVAL
6054 #define DDRC_SARSIZE1_NBLOCKS_SHIFT 0
6055 #define DDRC_SARSIZE1_NBLOCKS_MASK 0x000000FFU
6057 /*Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
6058 s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
6059 , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
6060 this parameter by RDIMM's extra cycle of latency in terms of DFI clock.*/
6061 #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL
6062 #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT
6063 #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK
6064 #define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL 0x07020002
6065 #define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT 24
6066 #define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK 0x1F000000U
6068 /*Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
6069 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
6070 fer to PHY specification for correct value.*/
6071 #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL
6072 #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT
6073 #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK
6074 #define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002
6075 #define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT 23
6076 #define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK 0x00800000U
6078 /*Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
6079 ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
6080 , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
6081 latency through the RDIMM. Unit: Clocks*/
6082 #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL
6083 #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT
6084 #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK
6085 #define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL 0x07020002
6086 #define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT 16
6087 #define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK 0x003F0000U
6089 /*Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
6090 .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
6091 HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
6093 #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL
6094 #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT
6095 #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK
6096 #define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002
6097 #define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT 15
6098 #define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK 0x00008000U
6100 /*Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
6101 dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
6102 te, max supported value is 8. Unit: Clocks*/
6103 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL
6104 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT
6105 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK
6106 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL 0x07020002
6107 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT 8
6108 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK 0x00003F00U
6110 /*Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
6111 parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
6112 necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
6114 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL
6115 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT
6116 #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK
6117 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL 0x07020002
6118 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT 0
6119 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK 0x0000003FU
6121 /*DDR block level reset inside of the DDR Sub System*/
6122 #undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL
6123 #undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT
6124 #undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK
6125 #define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F
6126 #define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3
6127 #define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U
6130 #undef DDR_PHY_PGCR0_ADCP_DEFVAL
6131 #undef DDR_PHY_PGCR0_ADCP_SHIFT
6132 #undef DDR_PHY_PGCR0_ADCP_MASK
6133 #define DDR_PHY_PGCR0_ADCP_DEFVAL 0x07001E00
6134 #define DDR_PHY_PGCR0_ADCP_SHIFT 31
6135 #define DDR_PHY_PGCR0_ADCP_MASK 0x80000000U
6137 /*Reserved. Returns zeroes on reads.*/
6138 #undef DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL
6139 #undef DDR_PHY_PGCR0_RESERVED_30_27_SHIFT
6140 #undef DDR_PHY_PGCR0_RESERVED_30_27_MASK
6141 #define DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL 0x07001E00
6142 #define DDR_PHY_PGCR0_RESERVED_30_27_SHIFT 27
6143 #define DDR_PHY_PGCR0_RESERVED_30_27_MASK 0x78000000U
6146 #undef DDR_PHY_PGCR0_PHYFRST_DEFVAL
6147 #undef DDR_PHY_PGCR0_PHYFRST_SHIFT
6148 #undef DDR_PHY_PGCR0_PHYFRST_MASK
6149 #define DDR_PHY_PGCR0_PHYFRST_DEFVAL 0x07001E00
6150 #define DDR_PHY_PGCR0_PHYFRST_SHIFT 26
6151 #define DDR_PHY_PGCR0_PHYFRST_MASK 0x04000000U
6153 /*Oscillator Mode Address/Command Delay Line Select*/
6154 #undef DDR_PHY_PGCR0_OSCACDL_DEFVAL
6155 #undef DDR_PHY_PGCR0_OSCACDL_SHIFT
6156 #undef DDR_PHY_PGCR0_OSCACDL_MASK
6157 #define DDR_PHY_PGCR0_OSCACDL_DEFVAL 0x07001E00
6158 #define DDR_PHY_PGCR0_OSCACDL_SHIFT 24
6159 #define DDR_PHY_PGCR0_OSCACDL_MASK 0x03000000U
6161 /*Reserved. Returns zeroes on reads.*/
6162 #undef DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL
6163 #undef DDR_PHY_PGCR0_RESERVED_23_19_SHIFT
6164 #undef DDR_PHY_PGCR0_RESERVED_23_19_MASK
6165 #define DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL 0x07001E00
6166 #define DDR_PHY_PGCR0_RESERVED_23_19_SHIFT 19
6167 #define DDR_PHY_PGCR0_RESERVED_23_19_MASK 0x00F80000U
6169 /*Digital Test Output Select*/
6170 #undef DDR_PHY_PGCR0_DTOSEL_DEFVAL
6171 #undef DDR_PHY_PGCR0_DTOSEL_SHIFT
6172 #undef DDR_PHY_PGCR0_DTOSEL_MASK
6173 #define DDR_PHY_PGCR0_DTOSEL_DEFVAL 0x07001E00
6174 #define DDR_PHY_PGCR0_DTOSEL_SHIFT 14
6175 #define DDR_PHY_PGCR0_DTOSEL_MASK 0x0007C000U
6177 /*Reserved. Returns zeroes on reads.*/
6178 #undef DDR_PHY_PGCR0_RESERVED_13_DEFVAL
6179 #undef DDR_PHY_PGCR0_RESERVED_13_SHIFT
6180 #undef DDR_PHY_PGCR0_RESERVED_13_MASK
6181 #define DDR_PHY_PGCR0_RESERVED_13_DEFVAL 0x07001E00
6182 #define DDR_PHY_PGCR0_RESERVED_13_SHIFT 13
6183 #define DDR_PHY_PGCR0_RESERVED_13_MASK 0x00002000U
6185 /*Oscillator Mode Division*/
6186 #undef DDR_PHY_PGCR0_OSCDIV_DEFVAL
6187 #undef DDR_PHY_PGCR0_OSCDIV_SHIFT
6188 #undef DDR_PHY_PGCR0_OSCDIV_MASK
6189 #define DDR_PHY_PGCR0_OSCDIV_DEFVAL 0x07001E00
6190 #define DDR_PHY_PGCR0_OSCDIV_SHIFT 9
6191 #define DDR_PHY_PGCR0_OSCDIV_MASK 0x00001E00U
6193 /*Oscillator Enable*/
6194 #undef DDR_PHY_PGCR0_OSCEN_DEFVAL
6195 #undef DDR_PHY_PGCR0_OSCEN_SHIFT
6196 #undef DDR_PHY_PGCR0_OSCEN_MASK
6197 #define DDR_PHY_PGCR0_OSCEN_DEFVAL 0x07001E00
6198 #define DDR_PHY_PGCR0_OSCEN_SHIFT 8
6199 #define DDR_PHY_PGCR0_OSCEN_MASK 0x00000100U
6201 /*Reserved. Returns zeroes on reads.*/
6202 #undef DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL
6203 #undef DDR_PHY_PGCR0_RESERVED_7_0_SHIFT
6204 #undef DDR_PHY_PGCR0_RESERVED_7_0_MASK
6205 #define DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL 0x07001E00
6206 #define DDR_PHY_PGCR0_RESERVED_7_0_SHIFT 0
6207 #define DDR_PHY_PGCR0_RESERVED_7_0_MASK 0x000000FFU
6209 /*Clear Training Status Registers*/
6210 #undef DDR_PHY_PGCR2_CLRTSTAT_DEFVAL
6211 #undef DDR_PHY_PGCR2_CLRTSTAT_SHIFT
6212 #undef DDR_PHY_PGCR2_CLRTSTAT_MASK
6213 #define DDR_PHY_PGCR2_CLRTSTAT_DEFVAL 0x00F12480
6214 #define DDR_PHY_PGCR2_CLRTSTAT_SHIFT 31
6215 #define DDR_PHY_PGCR2_CLRTSTAT_MASK 0x80000000U
6217 /*Clear Impedance Calibration*/
6218 #undef DDR_PHY_PGCR2_CLRZCAL_DEFVAL
6219 #undef DDR_PHY_PGCR2_CLRZCAL_SHIFT
6220 #undef DDR_PHY_PGCR2_CLRZCAL_MASK
6221 #define DDR_PHY_PGCR2_CLRZCAL_DEFVAL 0x00F12480
6222 #define DDR_PHY_PGCR2_CLRZCAL_SHIFT 30
6223 #define DDR_PHY_PGCR2_CLRZCAL_MASK 0x40000000U
6225 /*Clear Parity Error*/
6226 #undef DDR_PHY_PGCR2_CLRPERR_DEFVAL
6227 #undef DDR_PHY_PGCR2_CLRPERR_SHIFT
6228 #undef DDR_PHY_PGCR2_CLRPERR_MASK
6229 #define DDR_PHY_PGCR2_CLRPERR_DEFVAL 0x00F12480
6230 #define DDR_PHY_PGCR2_CLRPERR_SHIFT 29
6231 #define DDR_PHY_PGCR2_CLRPERR_MASK 0x20000000U
6233 /*Initialization Complete Pin Configuration*/
6234 #undef DDR_PHY_PGCR2_ICPC_DEFVAL
6235 #undef DDR_PHY_PGCR2_ICPC_SHIFT
6236 #undef DDR_PHY_PGCR2_ICPC_MASK
6237 #define DDR_PHY_PGCR2_ICPC_DEFVAL 0x00F12480
6238 #define DDR_PHY_PGCR2_ICPC_SHIFT 28
6239 #define DDR_PHY_PGCR2_ICPC_MASK 0x10000000U
6241 /*Data Training PUB Mode Exit Timer*/
6242 #undef DDR_PHY_PGCR2_DTPMXTMR_DEFVAL
6243 #undef DDR_PHY_PGCR2_DTPMXTMR_SHIFT
6244 #undef DDR_PHY_PGCR2_DTPMXTMR_MASK
6245 #define DDR_PHY_PGCR2_DTPMXTMR_DEFVAL 0x00F12480
6246 #define DDR_PHY_PGCR2_DTPMXTMR_SHIFT 20
6247 #define DDR_PHY_PGCR2_DTPMXTMR_MASK 0x0FF00000U
6249 /*Initialization Bypass*/
6250 #undef DDR_PHY_PGCR2_INITFSMBYP_DEFVAL
6251 #undef DDR_PHY_PGCR2_INITFSMBYP_SHIFT
6252 #undef DDR_PHY_PGCR2_INITFSMBYP_MASK
6253 #define DDR_PHY_PGCR2_INITFSMBYP_DEFVAL 0x00F12480
6254 #define DDR_PHY_PGCR2_INITFSMBYP_SHIFT 19
6255 #define DDR_PHY_PGCR2_INITFSMBYP_MASK 0x00080000U
6258 #undef DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL
6259 #undef DDR_PHY_PGCR2_PLLFSMBYP_SHIFT
6260 #undef DDR_PHY_PGCR2_PLLFSMBYP_MASK
6261 #define DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL 0x00F12480
6262 #define DDR_PHY_PGCR2_PLLFSMBYP_SHIFT 18
6263 #define DDR_PHY_PGCR2_PLLFSMBYP_MASK 0x00040000U
6266 #undef DDR_PHY_PGCR2_TREFPRD_DEFVAL
6267 #undef DDR_PHY_PGCR2_TREFPRD_SHIFT
6268 #undef DDR_PHY_PGCR2_TREFPRD_MASK
6269 #define DDR_PHY_PGCR2_TREFPRD_DEFVAL 0x00F12480
6270 #define DDR_PHY_PGCR2_TREFPRD_SHIFT 0
6271 #define DDR_PHY_PGCR2_TREFPRD_MASK 0x0003FFFFU
6274 #undef DDR_PHY_PGCR3_CKNEN_DEFVAL
6275 #undef DDR_PHY_PGCR3_CKNEN_SHIFT
6276 #undef DDR_PHY_PGCR3_CKNEN_MASK
6277 #define DDR_PHY_PGCR3_CKNEN_DEFVAL 0x55AA0080
6278 #define DDR_PHY_PGCR3_CKNEN_SHIFT 24
6279 #define DDR_PHY_PGCR3_CKNEN_MASK 0xFF000000U
6282 #undef DDR_PHY_PGCR3_CKEN_DEFVAL
6283 #undef DDR_PHY_PGCR3_CKEN_SHIFT
6284 #undef DDR_PHY_PGCR3_CKEN_MASK
6285 #define DDR_PHY_PGCR3_CKEN_DEFVAL 0x55AA0080
6286 #define DDR_PHY_PGCR3_CKEN_SHIFT 16
6287 #define DDR_PHY_PGCR3_CKEN_MASK 0x00FF0000U
6289 /*Reserved. Return zeroes on reads.*/
6290 #undef DDR_PHY_PGCR3_RESERVED_15_DEFVAL
6291 #undef DDR_PHY_PGCR3_RESERVED_15_SHIFT
6292 #undef DDR_PHY_PGCR3_RESERVED_15_MASK
6293 #define DDR_PHY_PGCR3_RESERVED_15_DEFVAL 0x55AA0080
6294 #define DDR_PHY_PGCR3_RESERVED_15_SHIFT 15
6295 #define DDR_PHY_PGCR3_RESERVED_15_MASK 0x00008000U
6297 /*Enable Clock Gating for AC [0] ctl_rd_clk*/
6298 #undef DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL
6299 #undef DDR_PHY_PGCR3_GATEACRDCLK_SHIFT
6300 #undef DDR_PHY_PGCR3_GATEACRDCLK_MASK
6301 #define DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL 0x55AA0080
6302 #define DDR_PHY_PGCR3_GATEACRDCLK_SHIFT 13
6303 #define DDR_PHY_PGCR3_GATEACRDCLK_MASK 0x00006000U
6305 /*Enable Clock Gating for AC [0] ddr_clk*/
6306 #undef DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL
6307 #undef DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT
6308 #undef DDR_PHY_PGCR3_GATEACDDRCLK_MASK
6309 #define DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL 0x55AA0080
6310 #define DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT 11
6311 #define DDR_PHY_PGCR3_GATEACDDRCLK_MASK 0x00001800U
6313 /*Enable Clock Gating for AC [0] ctl_clk*/
6314 #undef DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL
6315 #undef DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT
6316 #undef DDR_PHY_PGCR3_GATEACCTLCLK_MASK
6317 #define DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL 0x55AA0080
6318 #define DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT 9
6319 #define DDR_PHY_PGCR3_GATEACCTLCLK_MASK 0x00000600U
6321 /*Reserved. Return zeroes on reads.*/
6322 #undef DDR_PHY_PGCR3_RESERVED_8_DEFVAL
6323 #undef DDR_PHY_PGCR3_RESERVED_8_SHIFT
6324 #undef DDR_PHY_PGCR3_RESERVED_8_MASK
6325 #define DDR_PHY_PGCR3_RESERVED_8_DEFVAL 0x55AA0080
6326 #define DDR_PHY_PGCR3_RESERVED_8_SHIFT 8
6327 #define DDR_PHY_PGCR3_RESERVED_8_MASK 0x00000100U
6329 /*Controls DDL Bypass Modes*/
6330 #undef DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL
6331 #undef DDR_PHY_PGCR3_DDLBYPMODE_SHIFT
6332 #undef DDR_PHY_PGCR3_DDLBYPMODE_MASK
6333 #define DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL 0x55AA0080
6334 #define DDR_PHY_PGCR3_DDLBYPMODE_SHIFT 6
6335 #define DDR_PHY_PGCR3_DDLBYPMODE_MASK 0x000000C0U
6337 /*IO Loop-Back Select*/
6338 #undef DDR_PHY_PGCR3_IOLB_DEFVAL
6339 #undef DDR_PHY_PGCR3_IOLB_SHIFT
6340 #undef DDR_PHY_PGCR3_IOLB_MASK
6341 #define DDR_PHY_PGCR3_IOLB_DEFVAL 0x55AA0080
6342 #define DDR_PHY_PGCR3_IOLB_SHIFT 5
6343 #define DDR_PHY_PGCR3_IOLB_MASK 0x00000020U
6345 /*AC Receive FIFO Read Mode*/
6346 #undef DDR_PHY_PGCR3_RDMODE_DEFVAL
6347 #undef DDR_PHY_PGCR3_RDMODE_SHIFT
6348 #undef DDR_PHY_PGCR3_RDMODE_MASK
6349 #define DDR_PHY_PGCR3_RDMODE_DEFVAL 0x55AA0080
6350 #define DDR_PHY_PGCR3_RDMODE_SHIFT 3
6351 #define DDR_PHY_PGCR3_RDMODE_MASK 0x00000018U
6353 /*Read FIFO Reset Disable*/
6354 #undef DDR_PHY_PGCR3_DISRST_DEFVAL
6355 #undef DDR_PHY_PGCR3_DISRST_SHIFT
6356 #undef DDR_PHY_PGCR3_DISRST_MASK
6357 #define DDR_PHY_PGCR3_DISRST_DEFVAL 0x55AA0080
6358 #define DDR_PHY_PGCR3_DISRST_SHIFT 2
6359 #define DDR_PHY_PGCR3_DISRST_MASK 0x00000004U
6361 /*Clock Level when Clock Gating*/
6362 #undef DDR_PHY_PGCR3_CLKLEVEL_DEFVAL
6363 #undef DDR_PHY_PGCR3_CLKLEVEL_SHIFT
6364 #undef DDR_PHY_PGCR3_CLKLEVEL_MASK
6365 #define DDR_PHY_PGCR3_CLKLEVEL_DEFVAL 0x55AA0080
6366 #define DDR_PHY_PGCR3_CLKLEVEL_SHIFT 0
6367 #define DDR_PHY_PGCR3_CLKLEVEL_MASK 0x00000003U
6369 /*Frequency B Ratio Term*/
6370 #undef DDR_PHY_PGCR5_FRQBT_DEFVAL
6371 #undef DDR_PHY_PGCR5_FRQBT_SHIFT
6372 #undef DDR_PHY_PGCR5_FRQBT_MASK
6373 #define DDR_PHY_PGCR5_FRQBT_DEFVAL 0x01010000
6374 #define DDR_PHY_PGCR5_FRQBT_SHIFT 24
6375 #define DDR_PHY_PGCR5_FRQBT_MASK 0xFF000000U
6377 /*Frequency A Ratio Term*/
6378 #undef DDR_PHY_PGCR5_FRQAT_DEFVAL
6379 #undef DDR_PHY_PGCR5_FRQAT_SHIFT
6380 #undef DDR_PHY_PGCR5_FRQAT_MASK
6381 #define DDR_PHY_PGCR5_FRQAT_DEFVAL 0x01010000
6382 #define DDR_PHY_PGCR5_FRQAT_SHIFT 16
6383 #define DDR_PHY_PGCR5_FRQAT_MASK 0x00FF0000U
6385 /*DFI Disconnect Time Period*/
6386 #undef DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL
6387 #undef DDR_PHY_PGCR5_DISCNPERIOD_SHIFT
6388 #undef DDR_PHY_PGCR5_DISCNPERIOD_MASK
6389 #define DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL 0x01010000
6390 #define DDR_PHY_PGCR5_DISCNPERIOD_SHIFT 8
6391 #define DDR_PHY_PGCR5_DISCNPERIOD_MASK 0x0000FF00U
6393 /*Receiver bias core side control*/
6394 #undef DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL
6395 #undef DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT
6396 #undef DDR_PHY_PGCR5_VREF_RBCTRL_MASK
6397 #define DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL 0x01010000
6398 #define DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT 4
6399 #define DDR_PHY_PGCR5_VREF_RBCTRL_MASK 0x000000F0U
6401 /*Reserved. Return zeroes on reads.*/
6402 #undef DDR_PHY_PGCR5_RESERVED_3_DEFVAL
6403 #undef DDR_PHY_PGCR5_RESERVED_3_SHIFT
6404 #undef DDR_PHY_PGCR5_RESERVED_3_MASK
6405 #define DDR_PHY_PGCR5_RESERVED_3_DEFVAL 0x01010000
6406 #define DDR_PHY_PGCR5_RESERVED_3_SHIFT 3
6407 #define DDR_PHY_PGCR5_RESERVED_3_MASK 0x00000008U
6409 /*Internal VREF generator REFSEL ragne select*/
6410 #undef DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL
6411 #undef DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT
6412 #undef DDR_PHY_PGCR5_DXREFISELRANGE_MASK
6413 #define DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL 0x01010000
6414 #define DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT 2
6415 #define DDR_PHY_PGCR5_DXREFISELRANGE_MASK 0x00000004U
6417 /*DDL Page Read Write select*/
6418 #undef DDR_PHY_PGCR5_DDLPGACT_DEFVAL
6419 #undef DDR_PHY_PGCR5_DDLPGACT_SHIFT
6420 #undef DDR_PHY_PGCR5_DDLPGACT_MASK
6421 #define DDR_PHY_PGCR5_DDLPGACT_DEFVAL 0x01010000
6422 #define DDR_PHY_PGCR5_DDLPGACT_SHIFT 1
6423 #define DDR_PHY_PGCR5_DDLPGACT_MASK 0x00000002U
6425 /*DDL Page Read Write select*/
6426 #undef DDR_PHY_PGCR5_DDLPGRW_DEFVAL
6427 #undef DDR_PHY_PGCR5_DDLPGRW_SHIFT
6428 #undef DDR_PHY_PGCR5_DDLPGRW_MASK
6429 #define DDR_PHY_PGCR5_DDLPGRW_DEFVAL 0x01010000
6430 #define DDR_PHY_PGCR5_DDLPGRW_SHIFT 0
6431 #define DDR_PHY_PGCR5_DDLPGRW_MASK 0x00000001U
6433 /*PLL Power-Down Time*/
6434 #undef DDR_PHY_PTR0_TPLLPD_DEFVAL
6435 #undef DDR_PHY_PTR0_TPLLPD_SHIFT
6436 #undef DDR_PHY_PTR0_TPLLPD_MASK
6437 #define DDR_PHY_PTR0_TPLLPD_DEFVAL 0x42C21590
6438 #define DDR_PHY_PTR0_TPLLPD_SHIFT 21
6439 #define DDR_PHY_PTR0_TPLLPD_MASK 0xFFE00000U
6441 /*PLL Gear Shift Time*/
6442 #undef DDR_PHY_PTR0_TPLLGS_DEFVAL
6443 #undef DDR_PHY_PTR0_TPLLGS_SHIFT
6444 #undef DDR_PHY_PTR0_TPLLGS_MASK
6445 #define DDR_PHY_PTR0_TPLLGS_DEFVAL 0x42C21590
6446 #define DDR_PHY_PTR0_TPLLGS_SHIFT 6
6447 #define DDR_PHY_PTR0_TPLLGS_MASK 0x001FFFC0U
6450 #undef DDR_PHY_PTR0_TPHYRST_DEFVAL
6451 #undef DDR_PHY_PTR0_TPHYRST_SHIFT
6452 #undef DDR_PHY_PTR0_TPHYRST_MASK
6453 #define DDR_PHY_PTR0_TPHYRST_DEFVAL 0x42C21590
6454 #define DDR_PHY_PTR0_TPHYRST_SHIFT 0
6455 #define DDR_PHY_PTR0_TPHYRST_MASK 0x0000003FU
6458 #undef DDR_PHY_PTR1_TPLLLOCK_DEFVAL
6459 #undef DDR_PHY_PTR1_TPLLLOCK_SHIFT
6460 #undef DDR_PHY_PTR1_TPLLLOCK_MASK
6461 #define DDR_PHY_PTR1_TPLLLOCK_DEFVAL 0xD05612C0
6462 #define DDR_PHY_PTR1_TPLLLOCK_SHIFT 16
6463 #define DDR_PHY_PTR1_TPLLLOCK_MASK 0xFFFF0000U
6465 /*Reserved. Returns zeroes on reads.*/
6466 #undef DDR_PHY_PTR1_RESERVED_15_13_DEFVAL
6467 #undef DDR_PHY_PTR1_RESERVED_15_13_SHIFT
6468 #undef DDR_PHY_PTR1_RESERVED_15_13_MASK
6469 #define DDR_PHY_PTR1_RESERVED_15_13_DEFVAL 0xD05612C0
6470 #define DDR_PHY_PTR1_RESERVED_15_13_SHIFT 13
6471 #define DDR_PHY_PTR1_RESERVED_15_13_MASK 0x0000E000U
6474 #undef DDR_PHY_PTR1_TPLLRST_DEFVAL
6475 #undef DDR_PHY_PTR1_TPLLRST_SHIFT
6476 #undef DDR_PHY_PTR1_TPLLRST_MASK
6477 #define DDR_PHY_PTR1_TPLLRST_DEFVAL 0xD05612C0
6478 #define DDR_PHY_PTR1_TPLLRST_SHIFT 0
6479 #define DDR_PHY_PTR1_TPLLRST_MASK 0x00001FFFU
6481 /*Reserved. Return zeroes on reads.*/
6482 #undef DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL
6483 #undef DDR_PHY_DSGCR_RESERVED_31_28_SHIFT
6484 #undef DDR_PHY_DSGCR_RESERVED_31_28_MASK
6485 #define DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL 0x02A04101
6486 #define DDR_PHY_DSGCR_RESERVED_31_28_SHIFT 28
6487 #define DDR_PHY_DSGCR_RESERVED_31_28_MASK 0xF0000000U
6489 /*When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d
6490 fault calculation.*/
6491 #undef DDR_PHY_DSGCR_RDBICLSEL_DEFVAL
6492 #undef DDR_PHY_DSGCR_RDBICLSEL_SHIFT
6493 #undef DDR_PHY_DSGCR_RDBICLSEL_MASK
6494 #define DDR_PHY_DSGCR_RDBICLSEL_DEFVAL 0x02A04101
6495 #define DDR_PHY_DSGCR_RDBICLSEL_SHIFT 27
6496 #define DDR_PHY_DSGCR_RDBICLSEL_MASK 0x08000000U
6498 /*When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value.*/
6499 #undef DDR_PHY_DSGCR_RDBICL_DEFVAL
6500 #undef DDR_PHY_DSGCR_RDBICL_SHIFT
6501 #undef DDR_PHY_DSGCR_RDBICL_MASK
6502 #define DDR_PHY_DSGCR_RDBICL_DEFVAL 0x02A04101
6503 #define DDR_PHY_DSGCR_RDBICL_SHIFT 24
6504 #define DDR_PHY_DSGCR_RDBICL_MASK 0x07000000U
6506 /*PHY Impedance Update Enable*/
6507 #undef DDR_PHY_DSGCR_PHYZUEN_DEFVAL
6508 #undef DDR_PHY_DSGCR_PHYZUEN_SHIFT
6509 #undef DDR_PHY_DSGCR_PHYZUEN_MASK
6510 #define DDR_PHY_DSGCR_PHYZUEN_DEFVAL 0x02A04101
6511 #define DDR_PHY_DSGCR_PHYZUEN_SHIFT 23
6512 #define DDR_PHY_DSGCR_PHYZUEN_MASK 0x00800000U
6514 /*Reserved. Return zeroes on reads.*/
6515 #undef DDR_PHY_DSGCR_RESERVED_22_DEFVAL
6516 #undef DDR_PHY_DSGCR_RESERVED_22_SHIFT
6517 #undef DDR_PHY_DSGCR_RESERVED_22_MASK
6518 #define DDR_PHY_DSGCR_RESERVED_22_DEFVAL 0x02A04101
6519 #define DDR_PHY_DSGCR_RESERVED_22_SHIFT 22
6520 #define DDR_PHY_DSGCR_RESERVED_22_MASK 0x00400000U
6522 /*SDRAM Reset Output Enable*/
6523 #undef DDR_PHY_DSGCR_RSTOE_DEFVAL
6524 #undef DDR_PHY_DSGCR_RSTOE_SHIFT
6525 #undef DDR_PHY_DSGCR_RSTOE_MASK
6526 #define DDR_PHY_DSGCR_RSTOE_DEFVAL 0x02A04101
6527 #define DDR_PHY_DSGCR_RSTOE_SHIFT 21
6528 #define DDR_PHY_DSGCR_RSTOE_MASK 0x00200000U
6530 /*Single Data Rate Mode*/
6531 #undef DDR_PHY_DSGCR_SDRMODE_DEFVAL
6532 #undef DDR_PHY_DSGCR_SDRMODE_SHIFT
6533 #undef DDR_PHY_DSGCR_SDRMODE_MASK
6534 #define DDR_PHY_DSGCR_SDRMODE_DEFVAL 0x02A04101
6535 #define DDR_PHY_DSGCR_SDRMODE_SHIFT 19
6536 #define DDR_PHY_DSGCR_SDRMODE_MASK 0x00180000U
6538 /*Reserved. Return zeroes on reads.*/
6539 #undef DDR_PHY_DSGCR_RESERVED_18_DEFVAL
6540 #undef DDR_PHY_DSGCR_RESERVED_18_SHIFT
6541 #undef DDR_PHY_DSGCR_RESERVED_18_MASK
6542 #define DDR_PHY_DSGCR_RESERVED_18_DEFVAL 0x02A04101
6543 #define DDR_PHY_DSGCR_RESERVED_18_SHIFT 18
6544 #define DDR_PHY_DSGCR_RESERVED_18_MASK 0x00040000U
6546 /*ATO Analog Test Enable*/
6547 #undef DDR_PHY_DSGCR_ATOAE_DEFVAL
6548 #undef DDR_PHY_DSGCR_ATOAE_SHIFT
6549 #undef DDR_PHY_DSGCR_ATOAE_MASK
6550 #define DDR_PHY_DSGCR_ATOAE_DEFVAL 0x02A04101
6551 #define DDR_PHY_DSGCR_ATOAE_SHIFT 17
6552 #define DDR_PHY_DSGCR_ATOAE_MASK 0x00020000U
6554 /*DTO Output Enable*/
6555 #undef DDR_PHY_DSGCR_DTOOE_DEFVAL
6556 #undef DDR_PHY_DSGCR_DTOOE_SHIFT
6557 #undef DDR_PHY_DSGCR_DTOOE_MASK
6558 #define DDR_PHY_DSGCR_DTOOE_DEFVAL 0x02A04101
6559 #define DDR_PHY_DSGCR_DTOOE_SHIFT 16
6560 #define DDR_PHY_DSGCR_DTOOE_MASK 0x00010000U
6563 #undef DDR_PHY_DSGCR_DTOIOM_DEFVAL
6564 #undef DDR_PHY_DSGCR_DTOIOM_SHIFT
6565 #undef DDR_PHY_DSGCR_DTOIOM_MASK
6566 #define DDR_PHY_DSGCR_DTOIOM_DEFVAL 0x02A04101
6567 #define DDR_PHY_DSGCR_DTOIOM_SHIFT 15
6568 #define DDR_PHY_DSGCR_DTOIOM_MASK 0x00008000U
6570 /*DTO Power Down Receiver*/
6571 #undef DDR_PHY_DSGCR_DTOPDR_DEFVAL
6572 #undef DDR_PHY_DSGCR_DTOPDR_SHIFT
6573 #undef DDR_PHY_DSGCR_DTOPDR_MASK
6574 #define DDR_PHY_DSGCR_DTOPDR_DEFVAL 0x02A04101
6575 #define DDR_PHY_DSGCR_DTOPDR_SHIFT 14
6576 #define DDR_PHY_DSGCR_DTOPDR_MASK 0x00004000U
6578 /*Reserved. Return zeroes on reads*/
6579 #undef DDR_PHY_DSGCR_RESERVED_13_DEFVAL
6580 #undef DDR_PHY_DSGCR_RESERVED_13_SHIFT
6581 #undef DDR_PHY_DSGCR_RESERVED_13_MASK
6582 #define DDR_PHY_DSGCR_RESERVED_13_DEFVAL 0x02A04101
6583 #define DDR_PHY_DSGCR_RESERVED_13_SHIFT 13
6584 #define DDR_PHY_DSGCR_RESERVED_13_MASK 0x00002000U
6586 /*DTO On-Die Termination*/
6587 #undef DDR_PHY_DSGCR_DTOODT_DEFVAL
6588 #undef DDR_PHY_DSGCR_DTOODT_SHIFT
6589 #undef DDR_PHY_DSGCR_DTOODT_MASK
6590 #define DDR_PHY_DSGCR_DTOODT_DEFVAL 0x02A04101
6591 #define DDR_PHY_DSGCR_DTOODT_SHIFT 12
6592 #define DDR_PHY_DSGCR_DTOODT_MASK 0x00001000U
6594 /*PHY Update Acknowledge Delay*/
6595 #undef DDR_PHY_DSGCR_PUAD_DEFVAL
6596 #undef DDR_PHY_DSGCR_PUAD_SHIFT
6597 #undef DDR_PHY_DSGCR_PUAD_MASK
6598 #define DDR_PHY_DSGCR_PUAD_DEFVAL 0x02A04101
6599 #define DDR_PHY_DSGCR_PUAD_SHIFT 6
6600 #define DDR_PHY_DSGCR_PUAD_MASK 0x00000FC0U
6602 /*Controller Update Acknowledge Enable*/
6603 #undef DDR_PHY_DSGCR_CUAEN_DEFVAL
6604 #undef DDR_PHY_DSGCR_CUAEN_SHIFT
6605 #undef DDR_PHY_DSGCR_CUAEN_MASK
6606 #define DDR_PHY_DSGCR_CUAEN_DEFVAL 0x02A04101
6607 #define DDR_PHY_DSGCR_CUAEN_SHIFT 5
6608 #define DDR_PHY_DSGCR_CUAEN_MASK 0x00000020U
6610 /*Reserved. Return zeroes on reads*/
6611 #undef DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL
6612 #undef DDR_PHY_DSGCR_RESERVED_4_3_SHIFT
6613 #undef DDR_PHY_DSGCR_RESERVED_4_3_MASK
6614 #define DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL 0x02A04101
6615 #define DDR_PHY_DSGCR_RESERVED_4_3_SHIFT 3
6616 #define DDR_PHY_DSGCR_RESERVED_4_3_MASK 0x00000018U
6618 /*Controller Impedance Update Enable*/
6619 #undef DDR_PHY_DSGCR_CTLZUEN_DEFVAL
6620 #undef DDR_PHY_DSGCR_CTLZUEN_SHIFT
6621 #undef DDR_PHY_DSGCR_CTLZUEN_MASK
6622 #define DDR_PHY_DSGCR_CTLZUEN_DEFVAL 0x02A04101
6623 #define DDR_PHY_DSGCR_CTLZUEN_SHIFT 2
6624 #define DDR_PHY_DSGCR_CTLZUEN_MASK 0x00000004U
6626 /*Reserved. Return zeroes on reads*/
6627 #undef DDR_PHY_DSGCR_RESERVED_1_DEFVAL
6628 #undef DDR_PHY_DSGCR_RESERVED_1_SHIFT
6629 #undef DDR_PHY_DSGCR_RESERVED_1_MASK
6630 #define DDR_PHY_DSGCR_RESERVED_1_DEFVAL 0x02A04101
6631 #define DDR_PHY_DSGCR_RESERVED_1_SHIFT 1
6632 #define DDR_PHY_DSGCR_RESERVED_1_MASK 0x00000002U
6634 /*PHY Update Request Enable*/
6635 #undef DDR_PHY_DSGCR_PUREN_DEFVAL
6636 #undef DDR_PHY_DSGCR_PUREN_SHIFT
6637 #undef DDR_PHY_DSGCR_PUREN_MASK
6638 #define DDR_PHY_DSGCR_PUREN_DEFVAL 0x02A04101
6639 #define DDR_PHY_DSGCR_PUREN_SHIFT 0
6640 #define DDR_PHY_DSGCR_PUREN_MASK 0x00000001U
6642 /*DDR4 Gear Down Timing.*/
6643 #undef DDR_PHY_DCR_GEARDN_DEFVAL
6644 #undef DDR_PHY_DCR_GEARDN_SHIFT
6645 #undef DDR_PHY_DCR_GEARDN_MASK
6646 #define DDR_PHY_DCR_GEARDN_DEFVAL 0x0000040D
6647 #define DDR_PHY_DCR_GEARDN_SHIFT 31
6648 #define DDR_PHY_DCR_GEARDN_MASK 0x80000000U
6650 /*Un-used Bank Group*/
6651 #undef DDR_PHY_DCR_UBG_DEFVAL
6652 #undef DDR_PHY_DCR_UBG_SHIFT
6653 #undef DDR_PHY_DCR_UBG_MASK
6654 #define DDR_PHY_DCR_UBG_DEFVAL 0x0000040D
6655 #define DDR_PHY_DCR_UBG_SHIFT 30
6656 #define DDR_PHY_DCR_UBG_MASK 0x40000000U
6658 /*Un-buffered DIMM Address Mirroring*/
6659 #undef DDR_PHY_DCR_UDIMM_DEFVAL
6660 #undef DDR_PHY_DCR_UDIMM_SHIFT
6661 #undef DDR_PHY_DCR_UDIMM_MASK
6662 #define DDR_PHY_DCR_UDIMM_DEFVAL 0x0000040D
6663 #define DDR_PHY_DCR_UDIMM_SHIFT 29
6664 #define DDR_PHY_DCR_UDIMM_MASK 0x20000000U
6667 #undef DDR_PHY_DCR_DDR2T_DEFVAL
6668 #undef DDR_PHY_DCR_DDR2T_SHIFT
6669 #undef DDR_PHY_DCR_DDR2T_MASK
6670 #define DDR_PHY_DCR_DDR2T_DEFVAL 0x0000040D
6671 #define DDR_PHY_DCR_DDR2T_SHIFT 28
6672 #define DDR_PHY_DCR_DDR2T_MASK 0x10000000U
6674 /*No Simultaneous Rank Access*/
6675 #undef DDR_PHY_DCR_NOSRA_DEFVAL
6676 #undef DDR_PHY_DCR_NOSRA_SHIFT
6677 #undef DDR_PHY_DCR_NOSRA_MASK
6678 #define DDR_PHY_DCR_NOSRA_DEFVAL 0x0000040D
6679 #define DDR_PHY_DCR_NOSRA_SHIFT 27
6680 #define DDR_PHY_DCR_NOSRA_MASK 0x08000000U
6682 /*Reserved. Return zeroes on reads.*/
6683 #undef DDR_PHY_DCR_RESERVED_26_18_DEFVAL
6684 #undef DDR_PHY_DCR_RESERVED_26_18_SHIFT
6685 #undef DDR_PHY_DCR_RESERVED_26_18_MASK
6686 #define DDR_PHY_DCR_RESERVED_26_18_DEFVAL 0x0000040D
6687 #define DDR_PHY_DCR_RESERVED_26_18_SHIFT 18
6688 #define DDR_PHY_DCR_RESERVED_26_18_MASK 0x07FC0000U
6691 #undef DDR_PHY_DCR_BYTEMASK_DEFVAL
6692 #undef DDR_PHY_DCR_BYTEMASK_SHIFT
6693 #undef DDR_PHY_DCR_BYTEMASK_MASK
6694 #define DDR_PHY_DCR_BYTEMASK_DEFVAL 0x0000040D
6695 #define DDR_PHY_DCR_BYTEMASK_SHIFT 10
6696 #define DDR_PHY_DCR_BYTEMASK_MASK 0x0003FC00U
6699 #undef DDR_PHY_DCR_DDRTYPE_DEFVAL
6700 #undef DDR_PHY_DCR_DDRTYPE_SHIFT
6701 #undef DDR_PHY_DCR_DDRTYPE_MASK
6702 #define DDR_PHY_DCR_DDRTYPE_DEFVAL 0x0000040D
6703 #define DDR_PHY_DCR_DDRTYPE_SHIFT 8
6704 #define DDR_PHY_DCR_DDRTYPE_MASK 0x00000300U
6706 /*Multi-Purpose Register (MPR) DQ (DDR3 Only)*/
6707 #undef DDR_PHY_DCR_MPRDQ_DEFVAL
6708 #undef DDR_PHY_DCR_MPRDQ_SHIFT
6709 #undef DDR_PHY_DCR_MPRDQ_MASK
6710 #define DDR_PHY_DCR_MPRDQ_DEFVAL 0x0000040D
6711 #define DDR_PHY_DCR_MPRDQ_SHIFT 7
6712 #define DDR_PHY_DCR_MPRDQ_MASK 0x00000080U
6714 /*Primary DQ (DDR3 Only)*/
6715 #undef DDR_PHY_DCR_PDQ_DEFVAL
6716 #undef DDR_PHY_DCR_PDQ_SHIFT
6717 #undef DDR_PHY_DCR_PDQ_MASK
6718 #define DDR_PHY_DCR_PDQ_DEFVAL 0x0000040D
6719 #define DDR_PHY_DCR_PDQ_SHIFT 4
6720 #define DDR_PHY_DCR_PDQ_MASK 0x00000070U
6723 #undef DDR_PHY_DCR_DDR8BNK_DEFVAL
6724 #undef DDR_PHY_DCR_DDR8BNK_SHIFT
6725 #undef DDR_PHY_DCR_DDR8BNK_MASK
6726 #define DDR_PHY_DCR_DDR8BNK_DEFVAL 0x0000040D
6727 #define DDR_PHY_DCR_DDR8BNK_SHIFT 3
6728 #define DDR_PHY_DCR_DDR8BNK_MASK 0x00000008U
6731 #undef DDR_PHY_DCR_DDRMD_DEFVAL
6732 #undef DDR_PHY_DCR_DDRMD_SHIFT
6733 #undef DDR_PHY_DCR_DDRMD_MASK
6734 #define DDR_PHY_DCR_DDRMD_DEFVAL 0x0000040D
6735 #define DDR_PHY_DCR_DDRMD_SHIFT 0
6736 #define DDR_PHY_DCR_DDRMD_MASK 0x00000007U
6738 /*Reserved. Return zeroes on reads.*/
6739 #undef DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL
6740 #undef DDR_PHY_DTPR0_RESERVED_31_29_SHIFT
6741 #undef DDR_PHY_DTPR0_RESERVED_31_29_MASK
6742 #define DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL 0x105A2D08
6743 #define DDR_PHY_DTPR0_RESERVED_31_29_SHIFT 29
6744 #define DDR_PHY_DTPR0_RESERVED_31_29_MASK 0xE0000000U
6746 /*Activate to activate command delay (different banks)*/
6747 #undef DDR_PHY_DTPR0_TRRD_DEFVAL
6748 #undef DDR_PHY_DTPR0_TRRD_SHIFT
6749 #undef DDR_PHY_DTPR0_TRRD_MASK
6750 #define DDR_PHY_DTPR0_TRRD_DEFVAL 0x105A2D08
6751 #define DDR_PHY_DTPR0_TRRD_SHIFT 24
6752 #define DDR_PHY_DTPR0_TRRD_MASK 0x1F000000U
6754 /*Reserved. Return zeroes on reads.*/
6755 #undef DDR_PHY_DTPR0_RESERVED_23_DEFVAL
6756 #undef DDR_PHY_DTPR0_RESERVED_23_SHIFT
6757 #undef DDR_PHY_DTPR0_RESERVED_23_MASK
6758 #define DDR_PHY_DTPR0_RESERVED_23_DEFVAL 0x105A2D08
6759 #define DDR_PHY_DTPR0_RESERVED_23_SHIFT 23
6760 #define DDR_PHY_DTPR0_RESERVED_23_MASK 0x00800000U
6762 /*Activate to precharge command delay*/
6763 #undef DDR_PHY_DTPR0_TRAS_DEFVAL
6764 #undef DDR_PHY_DTPR0_TRAS_SHIFT
6765 #undef DDR_PHY_DTPR0_TRAS_MASK
6766 #define DDR_PHY_DTPR0_TRAS_DEFVAL 0x105A2D08
6767 #define DDR_PHY_DTPR0_TRAS_SHIFT 16
6768 #define DDR_PHY_DTPR0_TRAS_MASK 0x007F0000U
6770 /*Reserved. Return zeroes on reads.*/
6771 #undef DDR_PHY_DTPR0_RESERVED_15_DEFVAL
6772 #undef DDR_PHY_DTPR0_RESERVED_15_SHIFT
6773 #undef DDR_PHY_DTPR0_RESERVED_15_MASK
6774 #define DDR_PHY_DTPR0_RESERVED_15_DEFVAL 0x105A2D08
6775 #define DDR_PHY_DTPR0_RESERVED_15_SHIFT 15
6776 #define DDR_PHY_DTPR0_RESERVED_15_MASK 0x00008000U
6778 /*Precharge command period*/
6779 #undef DDR_PHY_DTPR0_TRP_DEFVAL
6780 #undef DDR_PHY_DTPR0_TRP_SHIFT
6781 #undef DDR_PHY_DTPR0_TRP_MASK
6782 #define DDR_PHY_DTPR0_TRP_DEFVAL 0x105A2D08
6783 #define DDR_PHY_DTPR0_TRP_SHIFT 8
6784 #define DDR_PHY_DTPR0_TRP_MASK 0x00007F00U
6786 /*Reserved. Return zeroes on reads.*/
6787 #undef DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL
6788 #undef DDR_PHY_DTPR0_RESERVED_7_5_SHIFT
6789 #undef DDR_PHY_DTPR0_RESERVED_7_5_MASK
6790 #define DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL 0x105A2D08
6791 #define DDR_PHY_DTPR0_RESERVED_7_5_SHIFT 5
6792 #define DDR_PHY_DTPR0_RESERVED_7_5_MASK 0x000000E0U
6794 /*Internal read to precharge command delay*/
6795 #undef DDR_PHY_DTPR0_TRTP_DEFVAL
6796 #undef DDR_PHY_DTPR0_TRTP_SHIFT
6797 #undef DDR_PHY_DTPR0_TRTP_MASK
6798 #define DDR_PHY_DTPR0_TRTP_DEFVAL 0x105A2D08
6799 #define DDR_PHY_DTPR0_TRTP_SHIFT 0
6800 #define DDR_PHY_DTPR0_TRTP_MASK 0x0000001FU
6802 /*Reserved. Return zeroes on reads.*/
6803 #undef DDR_PHY_DTPR1_RESERVED_31_DEFVAL
6804 #undef DDR_PHY_DTPR1_RESERVED_31_SHIFT
6805 #undef DDR_PHY_DTPR1_RESERVED_31_MASK
6806 #define DDR_PHY_DTPR1_RESERVED_31_DEFVAL 0x5656041E
6807 #define DDR_PHY_DTPR1_RESERVED_31_SHIFT 31
6808 #define DDR_PHY_DTPR1_RESERVED_31_MASK 0x80000000U
6810 /*Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge.*/
6811 #undef DDR_PHY_DTPR1_TWLMRD_DEFVAL
6812 #undef DDR_PHY_DTPR1_TWLMRD_SHIFT
6813 #undef DDR_PHY_DTPR1_TWLMRD_MASK
6814 #define DDR_PHY_DTPR1_TWLMRD_DEFVAL 0x5656041E
6815 #define DDR_PHY_DTPR1_TWLMRD_SHIFT 24
6816 #define DDR_PHY_DTPR1_TWLMRD_MASK 0x7F000000U
6818 /*Reserved. Return zeroes on reads.*/
6819 #undef DDR_PHY_DTPR1_RESERVED_23_DEFVAL
6820 #undef DDR_PHY_DTPR1_RESERVED_23_SHIFT
6821 #undef DDR_PHY_DTPR1_RESERVED_23_MASK
6822 #define DDR_PHY_DTPR1_RESERVED_23_DEFVAL 0x5656041E
6823 #define DDR_PHY_DTPR1_RESERVED_23_SHIFT 23
6824 #define DDR_PHY_DTPR1_RESERVED_23_MASK 0x00800000U
6826 /*4-bank activate period*/
6827 #undef DDR_PHY_DTPR1_TFAW_DEFVAL
6828 #undef DDR_PHY_DTPR1_TFAW_SHIFT
6829 #undef DDR_PHY_DTPR1_TFAW_MASK
6830 #define DDR_PHY_DTPR1_TFAW_DEFVAL 0x5656041E
6831 #define DDR_PHY_DTPR1_TFAW_SHIFT 16
6832 #define DDR_PHY_DTPR1_TFAW_MASK 0x007F0000U
6834 /*Reserved. Return zeroes on reads.*/
6835 #undef DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL
6836 #undef DDR_PHY_DTPR1_RESERVED_15_11_SHIFT
6837 #undef DDR_PHY_DTPR1_RESERVED_15_11_MASK
6838 #define DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL 0x5656041E
6839 #define DDR_PHY_DTPR1_RESERVED_15_11_SHIFT 11
6840 #define DDR_PHY_DTPR1_RESERVED_15_11_MASK 0x0000F800U
6842 /*Load mode update delay (DDR4 and DDR3 only)*/
6843 #undef DDR_PHY_DTPR1_TMOD_DEFVAL
6844 #undef DDR_PHY_DTPR1_TMOD_SHIFT
6845 #undef DDR_PHY_DTPR1_TMOD_MASK
6846 #define DDR_PHY_DTPR1_TMOD_DEFVAL 0x5656041E
6847 #define DDR_PHY_DTPR1_TMOD_SHIFT 8
6848 #define DDR_PHY_DTPR1_TMOD_MASK 0x00000700U
6850 /*Reserved. Return zeroes on reads.*/
6851 #undef DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL
6852 #undef DDR_PHY_DTPR1_RESERVED_7_5_SHIFT
6853 #undef DDR_PHY_DTPR1_RESERVED_7_5_MASK
6854 #define DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL 0x5656041E
6855 #define DDR_PHY_DTPR1_RESERVED_7_5_SHIFT 5
6856 #define DDR_PHY_DTPR1_RESERVED_7_5_MASK 0x000000E0U
6858 /*Load mode cycle time*/
6859 #undef DDR_PHY_DTPR1_TMRD_DEFVAL
6860 #undef DDR_PHY_DTPR1_TMRD_SHIFT
6861 #undef DDR_PHY_DTPR1_TMRD_MASK
6862 #define DDR_PHY_DTPR1_TMRD_DEFVAL 0x5656041E
6863 #define DDR_PHY_DTPR1_TMRD_SHIFT 0
6864 #define DDR_PHY_DTPR1_TMRD_MASK 0x0000001FU
6866 /*Reserved. Return zeroes on reads.*/
6867 #undef DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL
6868 #undef DDR_PHY_DTPR2_RESERVED_31_29_SHIFT
6869 #undef DDR_PHY_DTPR2_RESERVED_31_29_MASK
6870 #define DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL 0x000B01D0
6871 #define DDR_PHY_DTPR2_RESERVED_31_29_SHIFT 29
6872 #define DDR_PHY_DTPR2_RESERVED_31_29_MASK 0xE0000000U
6874 /*Read to Write command delay. Valid values are*/
6875 #undef DDR_PHY_DTPR2_TRTW_DEFVAL
6876 #undef DDR_PHY_DTPR2_TRTW_SHIFT
6877 #undef DDR_PHY_DTPR2_TRTW_MASK
6878 #define DDR_PHY_DTPR2_TRTW_DEFVAL 0x000B01D0
6879 #define DDR_PHY_DTPR2_TRTW_SHIFT 28
6880 #define DDR_PHY_DTPR2_TRTW_MASK 0x10000000U
6882 /*Reserved. Return zeroes on reads.*/
6883 #undef DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL
6884 #undef DDR_PHY_DTPR2_RESERVED_27_25_SHIFT
6885 #undef DDR_PHY_DTPR2_RESERVED_27_25_MASK
6886 #define DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL 0x000B01D0
6887 #define DDR_PHY_DTPR2_RESERVED_27_25_SHIFT 25
6888 #define DDR_PHY_DTPR2_RESERVED_27_25_MASK 0x0E000000U
6890 /*Read to ODT delay (DDR3 only)*/
6891 #undef DDR_PHY_DTPR2_TRTODT_DEFVAL
6892 #undef DDR_PHY_DTPR2_TRTODT_SHIFT
6893 #undef DDR_PHY_DTPR2_TRTODT_MASK
6894 #define DDR_PHY_DTPR2_TRTODT_DEFVAL 0x000B01D0
6895 #define DDR_PHY_DTPR2_TRTODT_SHIFT 24
6896 #define DDR_PHY_DTPR2_TRTODT_MASK 0x01000000U
6898 /*Reserved. Return zeroes on reads.*/
6899 #undef DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL
6900 #undef DDR_PHY_DTPR2_RESERVED_23_20_SHIFT
6901 #undef DDR_PHY_DTPR2_RESERVED_23_20_MASK
6902 #define DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL 0x000B01D0
6903 #define DDR_PHY_DTPR2_RESERVED_23_20_SHIFT 20
6904 #define DDR_PHY_DTPR2_RESERVED_23_20_MASK 0x00F00000U
6906 /*CKE minimum pulse width*/
6907 #undef DDR_PHY_DTPR2_TCKE_DEFVAL
6908 #undef DDR_PHY_DTPR2_TCKE_SHIFT
6909 #undef DDR_PHY_DTPR2_TCKE_MASK
6910 #define DDR_PHY_DTPR2_TCKE_DEFVAL 0x000B01D0
6911 #define DDR_PHY_DTPR2_TCKE_SHIFT 16
6912 #define DDR_PHY_DTPR2_TCKE_MASK 0x000F0000U
6914 /*Reserved. Return zeroes on reads.*/
6915 #undef DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL
6916 #undef DDR_PHY_DTPR2_RESERVED_15_10_SHIFT
6917 #undef DDR_PHY_DTPR2_RESERVED_15_10_MASK
6918 #define DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL 0x000B01D0
6919 #define DDR_PHY_DTPR2_RESERVED_15_10_SHIFT 10
6920 #define DDR_PHY_DTPR2_RESERVED_15_10_MASK 0x0000FC00U
6922 /*Self refresh exit delay*/
6923 #undef DDR_PHY_DTPR2_TXS_DEFVAL
6924 #undef DDR_PHY_DTPR2_TXS_SHIFT
6925 #undef DDR_PHY_DTPR2_TXS_MASK
6926 #define DDR_PHY_DTPR2_TXS_DEFVAL 0x000B01D0
6927 #define DDR_PHY_DTPR2_TXS_SHIFT 0
6928 #define DDR_PHY_DTPR2_TXS_MASK 0x000003FFU
6930 /*ODT turn-off delay extension*/
6931 #undef DDR_PHY_DTPR3_TOFDX_DEFVAL
6932 #undef DDR_PHY_DTPR3_TOFDX_SHIFT
6933 #undef DDR_PHY_DTPR3_TOFDX_MASK
6934 #define DDR_PHY_DTPR3_TOFDX_DEFVAL 0x02000804
6935 #define DDR_PHY_DTPR3_TOFDX_SHIFT 29
6936 #define DDR_PHY_DTPR3_TOFDX_MASK 0xE0000000U
6938 /*Read to read and write to write command delay*/
6939 #undef DDR_PHY_DTPR3_TCCD_DEFVAL
6940 #undef DDR_PHY_DTPR3_TCCD_SHIFT
6941 #undef DDR_PHY_DTPR3_TCCD_MASK
6942 #define DDR_PHY_DTPR3_TCCD_DEFVAL 0x02000804
6943 #define DDR_PHY_DTPR3_TCCD_SHIFT 26
6944 #define DDR_PHY_DTPR3_TCCD_MASK 0x1C000000U
6946 /*DLL locking time*/
6947 #undef DDR_PHY_DTPR3_TDLLK_DEFVAL
6948 #undef DDR_PHY_DTPR3_TDLLK_SHIFT
6949 #undef DDR_PHY_DTPR3_TDLLK_MASK
6950 #define DDR_PHY_DTPR3_TDLLK_DEFVAL 0x02000804
6951 #define DDR_PHY_DTPR3_TDLLK_SHIFT 16
6952 #define DDR_PHY_DTPR3_TDLLK_MASK 0x03FF0000U
6954 /*Reserved. Return zeroes on reads.*/
6955 #undef DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL
6956 #undef DDR_PHY_DTPR3_RESERVED_15_12_SHIFT
6957 #undef DDR_PHY_DTPR3_RESERVED_15_12_MASK
6958 #define DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL 0x02000804
6959 #define DDR_PHY_DTPR3_RESERVED_15_12_SHIFT 12
6960 #define DDR_PHY_DTPR3_RESERVED_15_12_MASK 0x0000F000U
6962 /*Maximum DQS output access time from CK/CK# (LPDDR2/3 only)*/
6963 #undef DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL
6964 #undef DDR_PHY_DTPR3_TDQSCKMAX_SHIFT
6965 #undef DDR_PHY_DTPR3_TDQSCKMAX_MASK
6966 #define DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL 0x02000804
6967 #define DDR_PHY_DTPR3_TDQSCKMAX_SHIFT 8
6968 #define DDR_PHY_DTPR3_TDQSCKMAX_MASK 0x00000F00U
6970 /*Reserved. Return zeroes on reads.*/
6971 #undef DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL
6972 #undef DDR_PHY_DTPR3_RESERVED_7_3_SHIFT
6973 #undef DDR_PHY_DTPR3_RESERVED_7_3_MASK
6974 #define DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL 0x02000804
6975 #define DDR_PHY_DTPR3_RESERVED_7_3_SHIFT 3
6976 #define DDR_PHY_DTPR3_RESERVED_7_3_MASK 0x000000F8U
6978 /*DQS output access time from CK/CK# (LPDDR2/3 only)*/
6979 #undef DDR_PHY_DTPR3_TDQSCK_DEFVAL
6980 #undef DDR_PHY_DTPR3_TDQSCK_SHIFT
6981 #undef DDR_PHY_DTPR3_TDQSCK_MASK
6982 #define DDR_PHY_DTPR3_TDQSCK_DEFVAL 0x02000804
6983 #define DDR_PHY_DTPR3_TDQSCK_SHIFT 0
6984 #define DDR_PHY_DTPR3_TDQSCK_MASK 0x00000007U
6986 /*Reserved. Return zeroes on reads.*/
6987 #undef DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL
6988 #undef DDR_PHY_DTPR4_RESERVED_31_30_SHIFT
6989 #undef DDR_PHY_DTPR4_RESERVED_31_30_MASK
6990 #define DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL 0x01C02B10
6991 #define DDR_PHY_DTPR4_RESERVED_31_30_SHIFT 30
6992 #define DDR_PHY_DTPR4_RESERVED_31_30_MASK 0xC0000000U
6994 /*ODT turn-on/turn-off delays (DDR2 only)*/
6995 #undef DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL
6996 #undef DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT
6997 #undef DDR_PHY_DTPR4_TAOND_TAOFD_MASK
6998 #define DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL 0x01C02B10
6999 #define DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT 28
7000 #define DDR_PHY_DTPR4_TAOND_TAOFD_MASK 0x30000000U
7002 /*Reserved. Return zeroes on reads.*/
7003 #undef DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL
7004 #undef DDR_PHY_DTPR4_RESERVED_27_26_SHIFT
7005 #undef DDR_PHY_DTPR4_RESERVED_27_26_MASK
7006 #define DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL 0x01C02B10
7007 #define DDR_PHY_DTPR4_RESERVED_27_26_SHIFT 26
7008 #define DDR_PHY_DTPR4_RESERVED_27_26_MASK 0x0C000000U
7010 /*Refresh-to-Refresh*/
7011 #undef DDR_PHY_DTPR4_TRFC_DEFVAL
7012 #undef DDR_PHY_DTPR4_TRFC_SHIFT
7013 #undef DDR_PHY_DTPR4_TRFC_MASK
7014 #define DDR_PHY_DTPR4_TRFC_DEFVAL 0x01C02B10
7015 #define DDR_PHY_DTPR4_TRFC_SHIFT 16
7016 #define DDR_PHY_DTPR4_TRFC_MASK 0x03FF0000U
7018 /*Reserved. Return zeroes on reads.*/
7019 #undef DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL
7020 #undef DDR_PHY_DTPR4_RESERVED_15_14_SHIFT
7021 #undef DDR_PHY_DTPR4_RESERVED_15_14_MASK
7022 #define DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL 0x01C02B10
7023 #define DDR_PHY_DTPR4_RESERVED_15_14_SHIFT 14
7024 #define DDR_PHY_DTPR4_RESERVED_15_14_MASK 0x0000C000U
7026 /*Write leveling output delay*/
7027 #undef DDR_PHY_DTPR4_TWLO_DEFVAL
7028 #undef DDR_PHY_DTPR4_TWLO_SHIFT
7029 #undef DDR_PHY_DTPR4_TWLO_MASK
7030 #define DDR_PHY_DTPR4_TWLO_DEFVAL 0x01C02B10
7031 #define DDR_PHY_DTPR4_TWLO_SHIFT 8
7032 #define DDR_PHY_DTPR4_TWLO_MASK 0x00003F00U
7034 /*Reserved. Return zeroes on reads.*/
7035 #undef DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL
7036 #undef DDR_PHY_DTPR4_RESERVED_7_5_SHIFT
7037 #undef DDR_PHY_DTPR4_RESERVED_7_5_MASK
7038 #define DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL 0x01C02B10
7039 #define DDR_PHY_DTPR4_RESERVED_7_5_SHIFT 5
7040 #define DDR_PHY_DTPR4_RESERVED_7_5_MASK 0x000000E0U
7042 /*Power down exit delay*/
7043 #undef DDR_PHY_DTPR4_TXP_DEFVAL
7044 #undef DDR_PHY_DTPR4_TXP_SHIFT
7045 #undef DDR_PHY_DTPR4_TXP_MASK
7046 #define DDR_PHY_DTPR4_TXP_DEFVAL 0x01C02B10
7047 #define DDR_PHY_DTPR4_TXP_SHIFT 0
7048 #define DDR_PHY_DTPR4_TXP_MASK 0x0000001FU
7050 /*Reserved. Return zeroes on reads.*/
7051 #undef DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL
7052 #undef DDR_PHY_DTPR5_RESERVED_31_24_SHIFT
7053 #undef DDR_PHY_DTPR5_RESERVED_31_24_MASK
7054 #define DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL 0x00872716
7055 #define DDR_PHY_DTPR5_RESERVED_31_24_SHIFT 24
7056 #define DDR_PHY_DTPR5_RESERVED_31_24_MASK 0xFF000000U
7058 /*Activate to activate command delay (same bank)*/
7059 #undef DDR_PHY_DTPR5_TRC_DEFVAL
7060 #undef DDR_PHY_DTPR5_TRC_SHIFT
7061 #undef DDR_PHY_DTPR5_TRC_MASK
7062 #define DDR_PHY_DTPR5_TRC_DEFVAL 0x00872716
7063 #define DDR_PHY_DTPR5_TRC_SHIFT 16
7064 #define DDR_PHY_DTPR5_TRC_MASK 0x00FF0000U
7066 /*Reserved. Return zeroes on reads.*/
7067 #undef DDR_PHY_DTPR5_RESERVED_15_DEFVAL
7068 #undef DDR_PHY_DTPR5_RESERVED_15_SHIFT
7069 #undef DDR_PHY_DTPR5_RESERVED_15_MASK
7070 #define DDR_PHY_DTPR5_RESERVED_15_DEFVAL 0x00872716
7071 #define DDR_PHY_DTPR5_RESERVED_15_SHIFT 15
7072 #define DDR_PHY_DTPR5_RESERVED_15_MASK 0x00008000U
7074 /*Activate to read or write delay*/
7075 #undef DDR_PHY_DTPR5_TRCD_DEFVAL
7076 #undef DDR_PHY_DTPR5_TRCD_SHIFT
7077 #undef DDR_PHY_DTPR5_TRCD_MASK
7078 #define DDR_PHY_DTPR5_TRCD_DEFVAL 0x00872716
7079 #define DDR_PHY_DTPR5_TRCD_SHIFT 8
7080 #define DDR_PHY_DTPR5_TRCD_MASK 0x00007F00U
7082 /*Reserved. Return zeroes on reads.*/
7083 #undef DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL
7084 #undef DDR_PHY_DTPR5_RESERVED_7_5_SHIFT
7085 #undef DDR_PHY_DTPR5_RESERVED_7_5_MASK
7086 #define DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL 0x00872716
7087 #define DDR_PHY_DTPR5_RESERVED_7_5_SHIFT 5
7088 #define DDR_PHY_DTPR5_RESERVED_7_5_MASK 0x000000E0U
7090 /*Internal write to read command delay*/
7091 #undef DDR_PHY_DTPR5_TWTR_DEFVAL
7092 #undef DDR_PHY_DTPR5_TWTR_SHIFT
7093 #undef DDR_PHY_DTPR5_TWTR_MASK
7094 #define DDR_PHY_DTPR5_TWTR_DEFVAL 0x00872716
7095 #define DDR_PHY_DTPR5_TWTR_SHIFT 0
7096 #define DDR_PHY_DTPR5_TWTR_MASK 0x0000001FU
7098 /*PUB Write Latency Enable*/
7099 #undef DDR_PHY_DTPR6_PUBWLEN_DEFVAL
7100 #undef DDR_PHY_DTPR6_PUBWLEN_SHIFT
7101 #undef DDR_PHY_DTPR6_PUBWLEN_MASK
7102 #define DDR_PHY_DTPR6_PUBWLEN_DEFVAL 0x00000505
7103 #define DDR_PHY_DTPR6_PUBWLEN_SHIFT 31
7104 #define DDR_PHY_DTPR6_PUBWLEN_MASK 0x80000000U
7106 /*PUB Read Latency Enable*/
7107 #undef DDR_PHY_DTPR6_PUBRLEN_DEFVAL
7108 #undef DDR_PHY_DTPR6_PUBRLEN_SHIFT
7109 #undef DDR_PHY_DTPR6_PUBRLEN_MASK
7110 #define DDR_PHY_DTPR6_PUBRLEN_DEFVAL 0x00000505
7111 #define DDR_PHY_DTPR6_PUBRLEN_SHIFT 30
7112 #define DDR_PHY_DTPR6_PUBRLEN_MASK 0x40000000U
7114 /*Reserved. Return zeroes on reads.*/
7115 #undef DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL
7116 #undef DDR_PHY_DTPR6_RESERVED_29_14_SHIFT
7117 #undef DDR_PHY_DTPR6_RESERVED_29_14_MASK
7118 #define DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL 0x00000505
7119 #define DDR_PHY_DTPR6_RESERVED_29_14_SHIFT 14
7120 #define DDR_PHY_DTPR6_RESERVED_29_14_MASK 0x3FFFC000U
7123 #undef DDR_PHY_DTPR6_PUBWL_DEFVAL
7124 #undef DDR_PHY_DTPR6_PUBWL_SHIFT
7125 #undef DDR_PHY_DTPR6_PUBWL_MASK
7126 #define DDR_PHY_DTPR6_PUBWL_DEFVAL 0x00000505
7127 #define DDR_PHY_DTPR6_PUBWL_SHIFT 8
7128 #define DDR_PHY_DTPR6_PUBWL_MASK 0x00003F00U
7130 /*Reserved. Return zeroes on reads.*/
7131 #undef DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL
7132 #undef DDR_PHY_DTPR6_RESERVED_7_6_SHIFT
7133 #undef DDR_PHY_DTPR6_RESERVED_7_6_MASK
7134 #define DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL 0x00000505
7135 #define DDR_PHY_DTPR6_RESERVED_7_6_SHIFT 6
7136 #define DDR_PHY_DTPR6_RESERVED_7_6_MASK 0x000000C0U
7139 #undef DDR_PHY_DTPR6_PUBRL_DEFVAL
7140 #undef DDR_PHY_DTPR6_PUBRL_SHIFT
7141 #undef DDR_PHY_DTPR6_PUBRL_MASK
7142 #define DDR_PHY_DTPR6_PUBRL_DEFVAL 0x00000505
7143 #define DDR_PHY_DTPR6_PUBRL_SHIFT 0
7144 #define DDR_PHY_DTPR6_PUBRL_MASK 0x0000003FU
7146 /*Reserved. Return zeroes on reads.*/
7147 #undef DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL
7148 #undef DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT
7149 #undef DDR_PHY_RDIMMGCR0_RESERVED_31_MASK
7150 #define DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL 0x08400020
7151 #define DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT 31
7152 #define DDR_PHY_RDIMMGCR0_RESERVED_31_MASK 0x80000000U
7154 /*RDMIMM Quad CS Enable*/
7155 #undef DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL
7156 #undef DDR_PHY_RDIMMGCR0_QCSEN_SHIFT
7157 #undef DDR_PHY_RDIMMGCR0_QCSEN_MASK
7158 #define DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL 0x08400020
7159 #define DDR_PHY_RDIMMGCR0_QCSEN_SHIFT 30
7160 #define DDR_PHY_RDIMMGCR0_QCSEN_MASK 0x40000000U
7162 /*Reserved. Return zeroes on reads.*/
7163 #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL
7164 #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT
7165 #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK
7166 #define DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL 0x08400020
7167 #define DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT 28
7168 #define DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK 0x30000000U
7170 /*RDIMM Outputs I/O Mode*/
7171 #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL
7172 #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT
7173 #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK
7174 #define DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL 0x08400020
7175 #define DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT 27
7176 #define DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK 0x08000000U
7178 /*Reserved. Return zeroes on reads.*/
7179 #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL
7180 #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT
7181 #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK
7182 #define DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL 0x08400020
7183 #define DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT 24
7184 #define DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK 0x07000000U
7186 /*ERROUT# Output Enable*/
7187 #undef DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL
7188 #undef DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT
7189 #undef DDR_PHY_RDIMMGCR0_ERROUTOE_MASK
7190 #define DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL 0x08400020
7191 #define DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT 23
7192 #define DDR_PHY_RDIMMGCR0_ERROUTOE_MASK 0x00800000U
7194 /*ERROUT# I/O Mode*/
7195 #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL
7196 #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT
7197 #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK
7198 #define DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL 0x08400020
7199 #define DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT 22
7200 #define DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK 0x00400000U
7202 /*ERROUT# Power Down Receiver*/
7203 #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL
7204 #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT
7205 #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK
7206 #define DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL 0x08400020
7207 #define DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT 21
7208 #define DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK 0x00200000U
7210 /*Reserved. Return zeroes on reads.*/
7211 #undef DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL
7212 #undef DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT
7213 #undef DDR_PHY_RDIMMGCR0_RESERVED_20_MASK
7214 #define DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL 0x08400020
7215 #define DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT 20
7216 #define DDR_PHY_RDIMMGCR0_RESERVED_20_MASK 0x00100000U
7218 /*ERROUT# On-Die Termination*/
7219 #undef DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL
7220 #undef DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT
7221 #undef DDR_PHY_RDIMMGCR0_ERROUTODT_MASK
7222 #define DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL 0x08400020
7223 #define DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT 19
7224 #define DDR_PHY_RDIMMGCR0_ERROUTODT_MASK 0x00080000U
7226 /*Load Reduced DIMM*/
7227 #undef DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL
7228 #undef DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT
7229 #undef DDR_PHY_RDIMMGCR0_LRDIMM_MASK
7230 #define DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL 0x08400020
7231 #define DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT 18
7232 #define DDR_PHY_RDIMMGCR0_LRDIMM_MASK 0x00040000U
7235 #undef DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL
7236 #undef DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT
7237 #undef DDR_PHY_RDIMMGCR0_PARINIOM_MASK
7238 #define DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL 0x08400020
7239 #define DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT 17
7240 #define DDR_PHY_RDIMMGCR0_PARINIOM_MASK 0x00020000U
7242 /*Reserved. Return zeroes on reads.*/
7243 #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL
7244 #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT
7245 #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK
7246 #define DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL 0x08400020
7247 #define DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT 8
7248 #define DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK 0x0001FF00U
7250 /*Reserved. Return zeroes on reads.*/
7251 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL
7252 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT
7253 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK
7254 #define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL 0x08400020
7255 #define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT 6
7256 #define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK 0x000000C0U
7258 /*Rank Mirror Enable.*/
7259 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL
7260 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT
7261 #undef DDR_PHY_RDIMMGCR0_RNKMRREN_MASK
7262 #define DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL 0x08400020
7263 #define DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT 4
7264 #define DDR_PHY_RDIMMGCR0_RNKMRREN_MASK 0x00000030U
7266 /*Reserved. Return zeroes on reads.*/
7267 #undef DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL
7268 #undef DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT
7269 #undef DDR_PHY_RDIMMGCR0_RESERVED_3_MASK
7270 #define DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL 0x08400020
7271 #define DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT 3
7272 #define DDR_PHY_RDIMMGCR0_RESERVED_3_MASK 0x00000008U
7274 /*Stop on Parity Error*/
7275 #undef DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL
7276 #undef DDR_PHY_RDIMMGCR0_SOPERR_SHIFT
7277 #undef DDR_PHY_RDIMMGCR0_SOPERR_MASK
7278 #define DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL 0x08400020
7279 #define DDR_PHY_RDIMMGCR0_SOPERR_SHIFT 2
7280 #define DDR_PHY_RDIMMGCR0_SOPERR_MASK 0x00000004U
7282 /*Parity Error No Registering*/
7283 #undef DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL
7284 #undef DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT
7285 #undef DDR_PHY_RDIMMGCR0_ERRNOREG_MASK
7286 #define DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL 0x08400020
7287 #define DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT 1
7288 #define DDR_PHY_RDIMMGCR0_ERRNOREG_MASK 0x00000002U
7291 #undef DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL
7292 #undef DDR_PHY_RDIMMGCR0_RDIMM_SHIFT
7293 #undef DDR_PHY_RDIMMGCR0_RDIMM_MASK
7294 #define DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL 0x08400020
7295 #define DDR_PHY_RDIMMGCR0_RDIMM_SHIFT 0
7296 #define DDR_PHY_RDIMMGCR0_RDIMM_MASK 0x00000001U
7298 /*Reserved. Return zeroes on reads.*/
7299 #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL
7300 #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT
7301 #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK
7302 #define DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL 0x00000C80
7303 #define DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT 29
7304 #define DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK 0xE0000000U
7306 /*Address [17] B-side Inversion Disable*/
7307 #undef DDR_PHY_RDIMMGCR1_A17BID_DEFVAL
7308 #undef DDR_PHY_RDIMMGCR1_A17BID_SHIFT
7309 #undef DDR_PHY_RDIMMGCR1_A17BID_MASK
7310 #define DDR_PHY_RDIMMGCR1_A17BID_DEFVAL 0x00000C80
7311 #define DDR_PHY_RDIMMGCR1_A17BID_SHIFT 28
7312 #define DDR_PHY_RDIMMGCR1_A17BID_MASK 0x10000000U
7314 /*Reserved. Return zeroes on reads.*/
7315 #undef DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL
7316 #undef DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT
7317 #undef DDR_PHY_RDIMMGCR1_RESERVED_27_MASK
7318 #define DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL 0x00000C80
7319 #define DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT 27
7320 #define DDR_PHY_RDIMMGCR1_RESERVED_27_MASK 0x08000000U
7322 /*Command word to command word programming delay*/
7323 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL
7324 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT
7325 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK
7326 #define DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL 0x00000C80
7327 #define DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT 24
7328 #define DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK 0x07000000U
7330 /*Reserved. Return zeroes on reads.*/
7331 #undef DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL
7332 #undef DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT
7333 #undef DDR_PHY_RDIMMGCR1_RESERVED_23_MASK
7334 #define DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL 0x00000C80
7335 #define DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT 23
7336 #define DDR_PHY_RDIMMGCR1_RESERVED_23_MASK 0x00800000U
7338 /*Command word to command word programming delay*/
7339 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL
7340 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT
7341 #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK
7342 #define DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL 0x00000C80
7343 #define DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT 20
7344 #define DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK 0x00700000U
7346 /*Reserved. Return zeroes on reads.*/
7347 #undef DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL
7348 #undef DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT
7349 #undef DDR_PHY_RDIMMGCR1_RESERVED_19_MASK
7350 #define DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL 0x00000C80
7351 #define DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT 19
7352 #define DDR_PHY_RDIMMGCR1_RESERVED_19_MASK 0x00080000U
7354 /*Command word to command word programming delay*/
7355 #undef DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL
7356 #undef DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT
7357 #undef DDR_PHY_RDIMMGCR1_TBCMRD_MASK
7358 #define DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL 0x00000C80
7359 #define DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT 16
7360 #define DDR_PHY_RDIMMGCR1_TBCMRD_MASK 0x00070000U
7362 /*Reserved. Return zeroes on reads.*/
7363 #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL
7364 #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT
7365 #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK
7366 #define DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL 0x00000C80
7367 #define DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT 14
7368 #define DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK 0x0000C000U
7370 /*Stabilization time*/
7371 #undef DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL
7372 #undef DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT
7373 #undef DDR_PHY_RDIMMGCR1_TBCSTAB_MASK
7374 #define DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL 0x00000C80
7375 #define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT 0
7376 #define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK 0x00003FFFU
7378 /*DDR4/DDR3 Control Word 7*/
7379 #undef DDR_PHY_RDIMMCR0_RC7_DEFVAL
7380 #undef DDR_PHY_RDIMMCR0_RC7_SHIFT
7381 #undef DDR_PHY_RDIMMCR0_RC7_MASK
7382 #define DDR_PHY_RDIMMCR0_RC7_DEFVAL 0x00000000
7383 #define DDR_PHY_RDIMMCR0_RC7_SHIFT 28
7384 #define DDR_PHY_RDIMMCR0_RC7_MASK 0xF0000000U
7386 /*DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved*/
7387 #undef DDR_PHY_RDIMMCR0_RC6_DEFVAL
7388 #undef DDR_PHY_RDIMMCR0_RC6_SHIFT
7389 #undef DDR_PHY_RDIMMCR0_RC6_MASK
7390 #define DDR_PHY_RDIMMCR0_RC6_DEFVAL 0x00000000
7391 #define DDR_PHY_RDIMMCR0_RC6_SHIFT 24
7392 #define DDR_PHY_RDIMMCR0_RC6_MASK 0x0F000000U
7394 /*DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)*/
7395 #undef DDR_PHY_RDIMMCR0_RC5_DEFVAL
7396 #undef DDR_PHY_RDIMMCR0_RC5_SHIFT
7397 #undef DDR_PHY_RDIMMCR0_RC5_MASK
7398 #define DDR_PHY_RDIMMCR0_RC5_DEFVAL 0x00000000
7399 #define DDR_PHY_RDIMMCR0_RC5_SHIFT 20
7400 #define DDR_PHY_RDIMMCR0_RC5_MASK 0x00F00000U
7402 /*DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 Control Word 4 (Control Signals Driver C
7403 aracteristics Control Word)*/
7404 #undef DDR_PHY_RDIMMCR0_RC4_DEFVAL
7405 #undef DDR_PHY_RDIMMCR0_RC4_SHIFT
7406 #undef DDR_PHY_RDIMMCR0_RC4_MASK
7407 #define DDR_PHY_RDIMMCR0_RC4_DEFVAL 0x00000000
7408 #define DDR_PHY_RDIMMCR0_RC4_SHIFT 16
7409 #define DDR_PHY_RDIMMCR0_RC4_MASK 0x000F0000U
7411 /*DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control Word 3 (Command/Address Signals Dr
7412 ver Characteristrics Control Word)*/
7413 #undef DDR_PHY_RDIMMCR0_RC3_DEFVAL
7414 #undef DDR_PHY_RDIMMCR0_RC3_SHIFT
7415 #undef DDR_PHY_RDIMMCR0_RC3_MASK
7416 #define DDR_PHY_RDIMMCR0_RC3_DEFVAL 0x00000000
7417 #define DDR_PHY_RDIMMCR0_RC3_SHIFT 12
7418 #define DDR_PHY_RDIMMCR0_RC3_MASK 0x0000F000U
7420 /*DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word)*/
7421 #undef DDR_PHY_RDIMMCR0_RC2_DEFVAL
7422 #undef DDR_PHY_RDIMMCR0_RC2_SHIFT
7423 #undef DDR_PHY_RDIMMCR0_RC2_MASK
7424 #define DDR_PHY_RDIMMCR0_RC2_DEFVAL 0x00000000
7425 #define DDR_PHY_RDIMMCR0_RC2_SHIFT 8
7426 #define DDR_PHY_RDIMMCR0_RC2_MASK 0x00000F00U
7428 /*DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)*/
7429 #undef DDR_PHY_RDIMMCR0_RC1_DEFVAL
7430 #undef DDR_PHY_RDIMMCR0_RC1_SHIFT
7431 #undef DDR_PHY_RDIMMCR0_RC1_MASK
7432 #define DDR_PHY_RDIMMCR0_RC1_DEFVAL 0x00000000
7433 #define DDR_PHY_RDIMMCR0_RC1_SHIFT 4
7434 #define DDR_PHY_RDIMMCR0_RC1_MASK 0x000000F0U
7436 /*DDR4/DDR3 Control Word 0 (Global Features Control Word)*/
7437 #undef DDR_PHY_RDIMMCR0_RC0_DEFVAL
7438 #undef DDR_PHY_RDIMMCR0_RC0_SHIFT
7439 #undef DDR_PHY_RDIMMCR0_RC0_MASK
7440 #define DDR_PHY_RDIMMCR0_RC0_DEFVAL 0x00000000
7441 #define DDR_PHY_RDIMMCR0_RC0_SHIFT 0
7442 #define DDR_PHY_RDIMMCR0_RC0_MASK 0x0000000FU
7445 #undef DDR_PHY_RDIMMCR1_RC15_DEFVAL
7446 #undef DDR_PHY_RDIMMCR1_RC15_SHIFT
7447 #undef DDR_PHY_RDIMMCR1_RC15_MASK
7448 #define DDR_PHY_RDIMMCR1_RC15_DEFVAL 0x00000000
7449 #define DDR_PHY_RDIMMCR1_RC15_SHIFT 28
7450 #define DDR_PHY_RDIMMCR1_RC15_MASK 0xF0000000U
7452 /*DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved*/
7453 #undef DDR_PHY_RDIMMCR1_RC14_DEFVAL
7454 #undef DDR_PHY_RDIMMCR1_RC14_SHIFT
7455 #undef DDR_PHY_RDIMMCR1_RC14_MASK
7456 #define DDR_PHY_RDIMMCR1_RC14_DEFVAL 0x00000000
7457 #define DDR_PHY_RDIMMCR1_RC14_SHIFT 24
7458 #define DDR_PHY_RDIMMCR1_RC14_MASK 0x0F000000U
7460 /*DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved*/
7461 #undef DDR_PHY_RDIMMCR1_RC13_DEFVAL
7462 #undef DDR_PHY_RDIMMCR1_RC13_SHIFT
7463 #undef DDR_PHY_RDIMMCR1_RC13_MASK
7464 #define DDR_PHY_RDIMMCR1_RC13_DEFVAL 0x00000000
7465 #define DDR_PHY_RDIMMCR1_RC13_SHIFT 20
7466 #define DDR_PHY_RDIMMCR1_RC13_MASK 0x00F00000U
7468 /*DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved*/
7469 #undef DDR_PHY_RDIMMCR1_RC12_DEFVAL
7470 #undef DDR_PHY_RDIMMCR1_RC12_SHIFT
7471 #undef DDR_PHY_RDIMMCR1_RC12_MASK
7472 #define DDR_PHY_RDIMMCR1_RC12_DEFVAL 0x00000000
7473 #define DDR_PHY_RDIMMCR1_RC12_SHIFT 16
7474 #define DDR_PHY_RDIMMCR1_RC12_MASK 0x000F0000U
7476 /*DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con
7478 #undef DDR_PHY_RDIMMCR1_RC11_DEFVAL
7479 #undef DDR_PHY_RDIMMCR1_RC11_SHIFT
7480 #undef DDR_PHY_RDIMMCR1_RC11_MASK
7481 #define DDR_PHY_RDIMMCR1_RC11_DEFVAL 0x00000000
7482 #define DDR_PHY_RDIMMCR1_RC11_SHIFT 12
7483 #define DDR_PHY_RDIMMCR1_RC11_MASK 0x0000F000U
7485 /*DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)*/
7486 #undef DDR_PHY_RDIMMCR1_RC10_DEFVAL
7487 #undef DDR_PHY_RDIMMCR1_RC10_SHIFT
7488 #undef DDR_PHY_RDIMMCR1_RC10_MASK
7489 #define DDR_PHY_RDIMMCR1_RC10_DEFVAL 0x00000000
7490 #define DDR_PHY_RDIMMCR1_RC10_SHIFT 8
7491 #define DDR_PHY_RDIMMCR1_RC10_MASK 0x00000F00U
7493 /*DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)*/
7494 #undef DDR_PHY_RDIMMCR1_RC9_DEFVAL
7495 #undef DDR_PHY_RDIMMCR1_RC9_SHIFT
7496 #undef DDR_PHY_RDIMMCR1_RC9_MASK
7497 #define DDR_PHY_RDIMMCR1_RC9_DEFVAL 0x00000000
7498 #define DDR_PHY_RDIMMCR1_RC9_SHIFT 4
7499 #define DDR_PHY_RDIMMCR1_RC9_MASK 0x000000F0U
7501 /*DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting
7503 #undef DDR_PHY_RDIMMCR1_RC8_DEFVAL
7504 #undef DDR_PHY_RDIMMCR1_RC8_SHIFT
7505 #undef DDR_PHY_RDIMMCR1_RC8_MASK
7506 #define DDR_PHY_RDIMMCR1_RC8_DEFVAL 0x00000000
7507 #define DDR_PHY_RDIMMCR1_RC8_SHIFT 0
7508 #define DDR_PHY_RDIMMCR1_RC8_MASK 0x0000000FU
7510 /*Reserved. Return zeroes on reads.*/
7511 #undef DDR_PHY_MR0_RESERVED_31_8_DEFVAL
7512 #undef DDR_PHY_MR0_RESERVED_31_8_SHIFT
7513 #undef DDR_PHY_MR0_RESERVED_31_8_MASK
7514 #define DDR_PHY_MR0_RESERVED_31_8_DEFVAL 0x00000052
7515 #define DDR_PHY_MR0_RESERVED_31_8_SHIFT 8
7516 #define DDR_PHY_MR0_RESERVED_31_8_MASK 0xFFFFFF00U
7518 /*CA Terminating Rank*/
7519 #undef DDR_PHY_MR0_CATR_DEFVAL
7520 #undef DDR_PHY_MR0_CATR_SHIFT
7521 #undef DDR_PHY_MR0_CATR_MASK
7522 #define DDR_PHY_MR0_CATR_DEFVAL 0x00000052
7523 #define DDR_PHY_MR0_CATR_SHIFT 7
7524 #define DDR_PHY_MR0_CATR_MASK 0x00000080U
7526 /*Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7527 #undef DDR_PHY_MR0_RSVD_6_5_DEFVAL
7528 #undef DDR_PHY_MR0_RSVD_6_5_SHIFT
7529 #undef DDR_PHY_MR0_RSVD_6_5_MASK
7530 #define DDR_PHY_MR0_RSVD_6_5_DEFVAL 0x00000052
7531 #define DDR_PHY_MR0_RSVD_6_5_SHIFT 5
7532 #define DDR_PHY_MR0_RSVD_6_5_MASK 0x00000060U
7534 /*Built-in Self-Test for RZQ*/
7535 #undef DDR_PHY_MR0_RZQI_DEFVAL
7536 #undef DDR_PHY_MR0_RZQI_SHIFT
7537 #undef DDR_PHY_MR0_RZQI_MASK
7538 #define DDR_PHY_MR0_RZQI_DEFVAL 0x00000052
7539 #define DDR_PHY_MR0_RZQI_SHIFT 3
7540 #define DDR_PHY_MR0_RZQI_MASK 0x00000018U
7542 /*Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7543 #undef DDR_PHY_MR0_RSVD_2_0_DEFVAL
7544 #undef DDR_PHY_MR0_RSVD_2_0_SHIFT
7545 #undef DDR_PHY_MR0_RSVD_2_0_MASK
7546 #define DDR_PHY_MR0_RSVD_2_0_DEFVAL 0x00000052
7547 #define DDR_PHY_MR0_RSVD_2_0_SHIFT 0
7548 #define DDR_PHY_MR0_RSVD_2_0_MASK 0x00000007U
7550 /*Reserved. Return zeroes on reads.*/
7551 #undef DDR_PHY_MR1_RESERVED_31_8_DEFVAL
7552 #undef DDR_PHY_MR1_RESERVED_31_8_SHIFT
7553 #undef DDR_PHY_MR1_RESERVED_31_8_MASK
7554 #define DDR_PHY_MR1_RESERVED_31_8_DEFVAL 0x00000004
7555 #define DDR_PHY_MR1_RESERVED_31_8_SHIFT 8
7556 #define DDR_PHY_MR1_RESERVED_31_8_MASK 0xFFFFFF00U
7558 /*Read Postamble Length*/
7559 #undef DDR_PHY_MR1_RDPST_DEFVAL
7560 #undef DDR_PHY_MR1_RDPST_SHIFT
7561 #undef DDR_PHY_MR1_RDPST_MASK
7562 #define DDR_PHY_MR1_RDPST_DEFVAL 0x00000004
7563 #define DDR_PHY_MR1_RDPST_SHIFT 7
7564 #define DDR_PHY_MR1_RDPST_MASK 0x00000080U
7566 /*Write-recovery for auto-precharge command*/
7567 #undef DDR_PHY_MR1_NWR_DEFVAL
7568 #undef DDR_PHY_MR1_NWR_SHIFT
7569 #undef DDR_PHY_MR1_NWR_MASK
7570 #define DDR_PHY_MR1_NWR_DEFVAL 0x00000004
7571 #define DDR_PHY_MR1_NWR_SHIFT 4
7572 #define DDR_PHY_MR1_NWR_MASK 0x00000070U
7574 /*Read Preamble Length*/
7575 #undef DDR_PHY_MR1_RDPRE_DEFVAL
7576 #undef DDR_PHY_MR1_RDPRE_SHIFT
7577 #undef DDR_PHY_MR1_RDPRE_MASK
7578 #define DDR_PHY_MR1_RDPRE_DEFVAL 0x00000004
7579 #define DDR_PHY_MR1_RDPRE_SHIFT 3
7580 #define DDR_PHY_MR1_RDPRE_MASK 0x00000008U
7582 /*Write Preamble Length*/
7583 #undef DDR_PHY_MR1_WRPRE_DEFVAL
7584 #undef DDR_PHY_MR1_WRPRE_SHIFT
7585 #undef DDR_PHY_MR1_WRPRE_MASK
7586 #define DDR_PHY_MR1_WRPRE_DEFVAL 0x00000004
7587 #define DDR_PHY_MR1_WRPRE_SHIFT 2
7588 #define DDR_PHY_MR1_WRPRE_MASK 0x00000004U
7591 #undef DDR_PHY_MR1_BL_DEFVAL
7592 #undef DDR_PHY_MR1_BL_SHIFT
7593 #undef DDR_PHY_MR1_BL_MASK
7594 #define DDR_PHY_MR1_BL_DEFVAL 0x00000004
7595 #define DDR_PHY_MR1_BL_SHIFT 0
7596 #define DDR_PHY_MR1_BL_MASK 0x00000003U
7598 /*Reserved. Return zeroes on reads.*/
7599 #undef DDR_PHY_MR2_RESERVED_31_8_DEFVAL
7600 #undef DDR_PHY_MR2_RESERVED_31_8_SHIFT
7601 #undef DDR_PHY_MR2_RESERVED_31_8_MASK
7602 #define DDR_PHY_MR2_RESERVED_31_8_DEFVAL 0x00000000
7603 #define DDR_PHY_MR2_RESERVED_31_8_SHIFT 8
7604 #define DDR_PHY_MR2_RESERVED_31_8_MASK 0xFFFFFF00U
7607 #undef DDR_PHY_MR2_WRL_DEFVAL
7608 #undef DDR_PHY_MR2_WRL_SHIFT
7609 #undef DDR_PHY_MR2_WRL_MASK
7610 #define DDR_PHY_MR2_WRL_DEFVAL 0x00000000
7611 #define DDR_PHY_MR2_WRL_SHIFT 7
7612 #define DDR_PHY_MR2_WRL_MASK 0x00000080U
7614 /*Write Latency Set*/
7615 #undef DDR_PHY_MR2_WLS_DEFVAL
7616 #undef DDR_PHY_MR2_WLS_SHIFT
7617 #undef DDR_PHY_MR2_WLS_MASK
7618 #define DDR_PHY_MR2_WLS_DEFVAL 0x00000000
7619 #define DDR_PHY_MR2_WLS_SHIFT 6
7620 #define DDR_PHY_MR2_WLS_MASK 0x00000040U
7623 #undef DDR_PHY_MR2_WL_DEFVAL
7624 #undef DDR_PHY_MR2_WL_SHIFT
7625 #undef DDR_PHY_MR2_WL_MASK
7626 #define DDR_PHY_MR2_WL_DEFVAL 0x00000000
7627 #define DDR_PHY_MR2_WL_SHIFT 3
7628 #define DDR_PHY_MR2_WL_MASK 0x00000038U
7631 #undef DDR_PHY_MR2_RL_DEFVAL
7632 #undef DDR_PHY_MR2_RL_SHIFT
7633 #undef DDR_PHY_MR2_RL_MASK
7634 #define DDR_PHY_MR2_RL_DEFVAL 0x00000000
7635 #define DDR_PHY_MR2_RL_SHIFT 0
7636 #define DDR_PHY_MR2_RL_MASK 0x00000007U
7638 /*Reserved. Return zeroes on reads.*/
7639 #undef DDR_PHY_MR3_RESERVED_31_8_DEFVAL
7640 #undef DDR_PHY_MR3_RESERVED_31_8_SHIFT
7641 #undef DDR_PHY_MR3_RESERVED_31_8_MASK
7642 #define DDR_PHY_MR3_RESERVED_31_8_DEFVAL 0x00000031
7643 #define DDR_PHY_MR3_RESERVED_31_8_SHIFT 8
7644 #define DDR_PHY_MR3_RESERVED_31_8_MASK 0xFFFFFF00U
7646 /*DBI-Write Enable*/
7647 #undef DDR_PHY_MR3_DBIWR_DEFVAL
7648 #undef DDR_PHY_MR3_DBIWR_SHIFT
7649 #undef DDR_PHY_MR3_DBIWR_MASK
7650 #define DDR_PHY_MR3_DBIWR_DEFVAL 0x00000031
7651 #define DDR_PHY_MR3_DBIWR_SHIFT 7
7652 #define DDR_PHY_MR3_DBIWR_MASK 0x00000080U
7655 #undef DDR_PHY_MR3_DBIRD_DEFVAL
7656 #undef DDR_PHY_MR3_DBIRD_SHIFT
7657 #undef DDR_PHY_MR3_DBIRD_MASK
7658 #define DDR_PHY_MR3_DBIRD_DEFVAL 0x00000031
7659 #define DDR_PHY_MR3_DBIRD_SHIFT 6
7660 #define DDR_PHY_MR3_DBIRD_MASK 0x00000040U
7662 /*Pull-down Drive Strength*/
7663 #undef DDR_PHY_MR3_PDDS_DEFVAL
7664 #undef DDR_PHY_MR3_PDDS_SHIFT
7665 #undef DDR_PHY_MR3_PDDS_MASK
7666 #define DDR_PHY_MR3_PDDS_DEFVAL 0x00000031
7667 #define DDR_PHY_MR3_PDDS_SHIFT 3
7668 #define DDR_PHY_MR3_PDDS_MASK 0x00000038U
7670 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7671 #undef DDR_PHY_MR3_RSVD_DEFVAL
7672 #undef DDR_PHY_MR3_RSVD_SHIFT
7673 #undef DDR_PHY_MR3_RSVD_MASK
7674 #define DDR_PHY_MR3_RSVD_DEFVAL 0x00000031
7675 #define DDR_PHY_MR3_RSVD_SHIFT 2
7676 #define DDR_PHY_MR3_RSVD_MASK 0x00000004U
7678 /*Write Postamble Length*/
7679 #undef DDR_PHY_MR3_WRPST_DEFVAL
7680 #undef DDR_PHY_MR3_WRPST_SHIFT
7681 #undef DDR_PHY_MR3_WRPST_MASK
7682 #define DDR_PHY_MR3_WRPST_DEFVAL 0x00000031
7683 #define DDR_PHY_MR3_WRPST_SHIFT 1
7684 #define DDR_PHY_MR3_WRPST_MASK 0x00000002U
7686 /*Pull-up Calibration Point*/
7687 #undef DDR_PHY_MR3_PUCAL_DEFVAL
7688 #undef DDR_PHY_MR3_PUCAL_SHIFT
7689 #undef DDR_PHY_MR3_PUCAL_MASK
7690 #define DDR_PHY_MR3_PUCAL_DEFVAL 0x00000031
7691 #define DDR_PHY_MR3_PUCAL_SHIFT 0
7692 #define DDR_PHY_MR3_PUCAL_MASK 0x00000001U
7694 /*Reserved. Return zeroes on reads.*/
7695 #undef DDR_PHY_MR4_RESERVED_31_16_DEFVAL
7696 #undef DDR_PHY_MR4_RESERVED_31_16_SHIFT
7697 #undef DDR_PHY_MR4_RESERVED_31_16_MASK
7698 #define DDR_PHY_MR4_RESERVED_31_16_DEFVAL 0x00000000
7699 #define DDR_PHY_MR4_RESERVED_31_16_SHIFT 16
7700 #define DDR_PHY_MR4_RESERVED_31_16_MASK 0xFFFF0000U
7702 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7703 #undef DDR_PHY_MR4_RSVD_15_13_DEFVAL
7704 #undef DDR_PHY_MR4_RSVD_15_13_SHIFT
7705 #undef DDR_PHY_MR4_RSVD_15_13_MASK
7706 #define DDR_PHY_MR4_RSVD_15_13_DEFVAL 0x00000000
7707 #define DDR_PHY_MR4_RSVD_15_13_SHIFT 13
7708 #define DDR_PHY_MR4_RSVD_15_13_MASK 0x0000E000U
7711 #undef DDR_PHY_MR4_WRP_DEFVAL
7712 #undef DDR_PHY_MR4_WRP_SHIFT
7713 #undef DDR_PHY_MR4_WRP_MASK
7714 #define DDR_PHY_MR4_WRP_DEFVAL 0x00000000
7715 #define DDR_PHY_MR4_WRP_SHIFT 12
7716 #define DDR_PHY_MR4_WRP_MASK 0x00001000U
7719 #undef DDR_PHY_MR4_RDP_DEFVAL
7720 #undef DDR_PHY_MR4_RDP_SHIFT
7721 #undef DDR_PHY_MR4_RDP_MASK
7722 #define DDR_PHY_MR4_RDP_DEFVAL 0x00000000
7723 #define DDR_PHY_MR4_RDP_SHIFT 11
7724 #define DDR_PHY_MR4_RDP_MASK 0x00000800U
7726 /*Read Preamble Training Mode*/
7727 #undef DDR_PHY_MR4_RPTM_DEFVAL
7728 #undef DDR_PHY_MR4_RPTM_SHIFT
7729 #undef DDR_PHY_MR4_RPTM_MASK
7730 #define DDR_PHY_MR4_RPTM_DEFVAL 0x00000000
7731 #define DDR_PHY_MR4_RPTM_SHIFT 10
7732 #define DDR_PHY_MR4_RPTM_MASK 0x00000400U
7734 /*Self Refresh Abort*/
7735 #undef DDR_PHY_MR4_SRA_DEFVAL
7736 #undef DDR_PHY_MR4_SRA_SHIFT
7737 #undef DDR_PHY_MR4_SRA_MASK
7738 #define DDR_PHY_MR4_SRA_DEFVAL 0x00000000
7739 #define DDR_PHY_MR4_SRA_SHIFT 9
7740 #define DDR_PHY_MR4_SRA_MASK 0x00000200U
7742 /*CS to Command Latency Mode*/
7743 #undef DDR_PHY_MR4_CS2CMDL_DEFVAL
7744 #undef DDR_PHY_MR4_CS2CMDL_SHIFT
7745 #undef DDR_PHY_MR4_CS2CMDL_MASK
7746 #define DDR_PHY_MR4_CS2CMDL_DEFVAL 0x00000000
7747 #define DDR_PHY_MR4_CS2CMDL_SHIFT 6
7748 #define DDR_PHY_MR4_CS2CMDL_MASK 0x000001C0U
7750 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7751 #undef DDR_PHY_MR4_RSVD1_DEFVAL
7752 #undef DDR_PHY_MR4_RSVD1_SHIFT
7753 #undef DDR_PHY_MR4_RSVD1_MASK
7754 #define DDR_PHY_MR4_RSVD1_DEFVAL 0x00000000
7755 #define DDR_PHY_MR4_RSVD1_SHIFT 5
7756 #define DDR_PHY_MR4_RSVD1_MASK 0x00000020U
7758 /*Internal VREF Monitor*/
7759 #undef DDR_PHY_MR4_IVM_DEFVAL
7760 #undef DDR_PHY_MR4_IVM_SHIFT
7761 #undef DDR_PHY_MR4_IVM_MASK
7762 #define DDR_PHY_MR4_IVM_DEFVAL 0x00000000
7763 #define DDR_PHY_MR4_IVM_SHIFT 4
7764 #define DDR_PHY_MR4_IVM_MASK 0x00000010U
7766 /*Temperature Controlled Refresh Mode*/
7767 #undef DDR_PHY_MR4_TCRM_DEFVAL
7768 #undef DDR_PHY_MR4_TCRM_SHIFT
7769 #undef DDR_PHY_MR4_TCRM_MASK
7770 #define DDR_PHY_MR4_TCRM_DEFVAL 0x00000000
7771 #define DDR_PHY_MR4_TCRM_SHIFT 3
7772 #define DDR_PHY_MR4_TCRM_MASK 0x00000008U
7774 /*Temperature Controlled Refresh Range*/
7775 #undef DDR_PHY_MR4_TCRR_DEFVAL
7776 #undef DDR_PHY_MR4_TCRR_SHIFT
7777 #undef DDR_PHY_MR4_TCRR_MASK
7778 #define DDR_PHY_MR4_TCRR_DEFVAL 0x00000000
7779 #define DDR_PHY_MR4_TCRR_SHIFT 2
7780 #define DDR_PHY_MR4_TCRR_MASK 0x00000004U
7782 /*Maximum Power Down Mode*/
7783 #undef DDR_PHY_MR4_MPDM_DEFVAL
7784 #undef DDR_PHY_MR4_MPDM_SHIFT
7785 #undef DDR_PHY_MR4_MPDM_MASK
7786 #define DDR_PHY_MR4_MPDM_DEFVAL 0x00000000
7787 #define DDR_PHY_MR4_MPDM_SHIFT 1
7788 #define DDR_PHY_MR4_MPDM_MASK 0x00000002U
7790 /*This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0.*/
7791 #undef DDR_PHY_MR4_RSVD_0_DEFVAL
7792 #undef DDR_PHY_MR4_RSVD_0_SHIFT
7793 #undef DDR_PHY_MR4_RSVD_0_MASK
7794 #define DDR_PHY_MR4_RSVD_0_DEFVAL 0x00000000
7795 #define DDR_PHY_MR4_RSVD_0_SHIFT 0
7796 #define DDR_PHY_MR4_RSVD_0_MASK 0x00000001U
7798 /*Reserved. Return zeroes on reads.*/
7799 #undef DDR_PHY_MR5_RESERVED_31_16_DEFVAL
7800 #undef DDR_PHY_MR5_RESERVED_31_16_SHIFT
7801 #undef DDR_PHY_MR5_RESERVED_31_16_MASK
7802 #define DDR_PHY_MR5_RESERVED_31_16_DEFVAL 0x00000000
7803 #define DDR_PHY_MR5_RESERVED_31_16_SHIFT 16
7804 #define DDR_PHY_MR5_RESERVED_31_16_MASK 0xFFFF0000U
7806 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7807 #undef DDR_PHY_MR5_RSVD_DEFVAL
7808 #undef DDR_PHY_MR5_RSVD_SHIFT
7809 #undef DDR_PHY_MR5_RSVD_MASK
7810 #define DDR_PHY_MR5_RSVD_DEFVAL 0x00000000
7811 #define DDR_PHY_MR5_RSVD_SHIFT 13
7812 #define DDR_PHY_MR5_RSVD_MASK 0x0000E000U
7815 #undef DDR_PHY_MR5_RDBI_DEFVAL
7816 #undef DDR_PHY_MR5_RDBI_SHIFT
7817 #undef DDR_PHY_MR5_RDBI_MASK
7818 #define DDR_PHY_MR5_RDBI_DEFVAL 0x00000000
7819 #define DDR_PHY_MR5_RDBI_SHIFT 12
7820 #define DDR_PHY_MR5_RDBI_MASK 0x00001000U
7823 #undef DDR_PHY_MR5_WDBI_DEFVAL
7824 #undef DDR_PHY_MR5_WDBI_SHIFT
7825 #undef DDR_PHY_MR5_WDBI_MASK
7826 #define DDR_PHY_MR5_WDBI_DEFVAL 0x00000000
7827 #define DDR_PHY_MR5_WDBI_SHIFT 11
7828 #define DDR_PHY_MR5_WDBI_MASK 0x00000800U
7831 #undef DDR_PHY_MR5_DM_DEFVAL
7832 #undef DDR_PHY_MR5_DM_SHIFT
7833 #undef DDR_PHY_MR5_DM_MASK
7834 #define DDR_PHY_MR5_DM_DEFVAL 0x00000000
7835 #define DDR_PHY_MR5_DM_SHIFT 10
7836 #define DDR_PHY_MR5_DM_MASK 0x00000400U
7838 /*CA Parity Persistent Error*/
7839 #undef DDR_PHY_MR5_CAPPE_DEFVAL
7840 #undef DDR_PHY_MR5_CAPPE_SHIFT
7841 #undef DDR_PHY_MR5_CAPPE_MASK
7842 #define DDR_PHY_MR5_CAPPE_DEFVAL 0x00000000
7843 #define DDR_PHY_MR5_CAPPE_SHIFT 9
7844 #define DDR_PHY_MR5_CAPPE_MASK 0x00000200U
7847 #undef DDR_PHY_MR5_RTTPARK_DEFVAL
7848 #undef DDR_PHY_MR5_RTTPARK_SHIFT
7849 #undef DDR_PHY_MR5_RTTPARK_MASK
7850 #define DDR_PHY_MR5_RTTPARK_DEFVAL 0x00000000
7851 #define DDR_PHY_MR5_RTTPARK_SHIFT 6
7852 #define DDR_PHY_MR5_RTTPARK_MASK 0x000001C0U
7854 /*ODT Input Buffer during Power Down mode*/
7855 #undef DDR_PHY_MR5_ODTIBPD_DEFVAL
7856 #undef DDR_PHY_MR5_ODTIBPD_SHIFT
7857 #undef DDR_PHY_MR5_ODTIBPD_MASK
7858 #define DDR_PHY_MR5_ODTIBPD_DEFVAL 0x00000000
7859 #define DDR_PHY_MR5_ODTIBPD_SHIFT 5
7860 #define DDR_PHY_MR5_ODTIBPD_MASK 0x00000020U
7862 /*C/A Parity Error Status*/
7863 #undef DDR_PHY_MR5_CAPES_DEFVAL
7864 #undef DDR_PHY_MR5_CAPES_SHIFT
7865 #undef DDR_PHY_MR5_CAPES_MASK
7866 #define DDR_PHY_MR5_CAPES_DEFVAL 0x00000000
7867 #define DDR_PHY_MR5_CAPES_SHIFT 4
7868 #define DDR_PHY_MR5_CAPES_MASK 0x00000010U
7871 #undef DDR_PHY_MR5_CRCEC_DEFVAL
7872 #undef DDR_PHY_MR5_CRCEC_SHIFT
7873 #undef DDR_PHY_MR5_CRCEC_MASK
7874 #define DDR_PHY_MR5_CRCEC_DEFVAL 0x00000000
7875 #define DDR_PHY_MR5_CRCEC_SHIFT 3
7876 #define DDR_PHY_MR5_CRCEC_MASK 0x00000008U
7878 /*C/A Parity Latency Mode*/
7879 #undef DDR_PHY_MR5_CAPM_DEFVAL
7880 #undef DDR_PHY_MR5_CAPM_SHIFT
7881 #undef DDR_PHY_MR5_CAPM_MASK
7882 #define DDR_PHY_MR5_CAPM_DEFVAL 0x00000000
7883 #define DDR_PHY_MR5_CAPM_SHIFT 0
7884 #define DDR_PHY_MR5_CAPM_MASK 0x00000007U
7886 /*Reserved. Return zeroes on reads.*/
7887 #undef DDR_PHY_MR6_RESERVED_31_16_DEFVAL
7888 #undef DDR_PHY_MR6_RESERVED_31_16_SHIFT
7889 #undef DDR_PHY_MR6_RESERVED_31_16_MASK
7890 #define DDR_PHY_MR6_RESERVED_31_16_DEFVAL 0x00000000
7891 #define DDR_PHY_MR6_RESERVED_31_16_SHIFT 16
7892 #define DDR_PHY_MR6_RESERVED_31_16_MASK 0xFFFF0000U
7894 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7895 #undef DDR_PHY_MR6_RSVD_15_13_DEFVAL
7896 #undef DDR_PHY_MR6_RSVD_15_13_SHIFT
7897 #undef DDR_PHY_MR6_RSVD_15_13_MASK
7898 #define DDR_PHY_MR6_RSVD_15_13_DEFVAL 0x00000000
7899 #define DDR_PHY_MR6_RSVD_15_13_SHIFT 13
7900 #define DDR_PHY_MR6_RSVD_15_13_MASK 0x0000E000U
7902 /*CAS_n to CAS_n command delay for same bank group (tCCD_L)*/
7903 #undef DDR_PHY_MR6_TCCDL_DEFVAL
7904 #undef DDR_PHY_MR6_TCCDL_SHIFT
7905 #undef DDR_PHY_MR6_TCCDL_MASK
7906 #define DDR_PHY_MR6_TCCDL_DEFVAL 0x00000000
7907 #define DDR_PHY_MR6_TCCDL_SHIFT 10
7908 #define DDR_PHY_MR6_TCCDL_MASK 0x00001C00U
7910 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7911 #undef DDR_PHY_MR6_RSVD_9_8_DEFVAL
7912 #undef DDR_PHY_MR6_RSVD_9_8_SHIFT
7913 #undef DDR_PHY_MR6_RSVD_9_8_MASK
7914 #define DDR_PHY_MR6_RSVD_9_8_DEFVAL 0x00000000
7915 #define DDR_PHY_MR6_RSVD_9_8_SHIFT 8
7916 #define DDR_PHY_MR6_RSVD_9_8_MASK 0x00000300U
7918 /*VrefDQ Training Enable*/
7919 #undef DDR_PHY_MR6_VDDQTEN_DEFVAL
7920 #undef DDR_PHY_MR6_VDDQTEN_SHIFT
7921 #undef DDR_PHY_MR6_VDDQTEN_MASK
7922 #define DDR_PHY_MR6_VDDQTEN_DEFVAL 0x00000000
7923 #define DDR_PHY_MR6_VDDQTEN_SHIFT 7
7924 #define DDR_PHY_MR6_VDDQTEN_MASK 0x00000080U
7926 /*VrefDQ Training Range*/
7927 #undef DDR_PHY_MR6_VDQTRG_DEFVAL
7928 #undef DDR_PHY_MR6_VDQTRG_SHIFT
7929 #undef DDR_PHY_MR6_VDQTRG_MASK
7930 #define DDR_PHY_MR6_VDQTRG_DEFVAL 0x00000000
7931 #define DDR_PHY_MR6_VDQTRG_SHIFT 6
7932 #define DDR_PHY_MR6_VDQTRG_MASK 0x00000040U
7934 /*VrefDQ Training Values*/
7935 #undef DDR_PHY_MR6_VDQTVAL_DEFVAL
7936 #undef DDR_PHY_MR6_VDQTVAL_SHIFT
7937 #undef DDR_PHY_MR6_VDQTVAL_MASK
7938 #define DDR_PHY_MR6_VDQTVAL_DEFVAL 0x00000000
7939 #define DDR_PHY_MR6_VDQTVAL_SHIFT 0
7940 #define DDR_PHY_MR6_VDQTVAL_MASK 0x0000003FU
7942 /*Reserved. Return zeroes on reads.*/
7943 #undef DDR_PHY_MR11_RESERVED_31_8_DEFVAL
7944 #undef DDR_PHY_MR11_RESERVED_31_8_SHIFT
7945 #undef DDR_PHY_MR11_RESERVED_31_8_MASK
7946 #define DDR_PHY_MR11_RESERVED_31_8_DEFVAL 0x00000000
7947 #define DDR_PHY_MR11_RESERVED_31_8_SHIFT 8
7948 #define DDR_PHY_MR11_RESERVED_31_8_MASK 0xFFFFFF00U
7950 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7951 #undef DDR_PHY_MR11_RSVD_DEFVAL
7952 #undef DDR_PHY_MR11_RSVD_SHIFT
7953 #undef DDR_PHY_MR11_RSVD_MASK
7954 #define DDR_PHY_MR11_RSVD_DEFVAL 0x00000000
7955 #define DDR_PHY_MR11_RSVD_SHIFT 3
7956 #define DDR_PHY_MR11_RSVD_MASK 0x000000F8U
7958 /*Power Down Control*/
7959 #undef DDR_PHY_MR11_PDCTL_DEFVAL
7960 #undef DDR_PHY_MR11_PDCTL_SHIFT
7961 #undef DDR_PHY_MR11_PDCTL_MASK
7962 #define DDR_PHY_MR11_PDCTL_DEFVAL 0x00000000
7963 #define DDR_PHY_MR11_PDCTL_SHIFT 2
7964 #define DDR_PHY_MR11_PDCTL_MASK 0x00000004U
7966 /*DQ Bus Receiver On-Die-Termination*/
7967 #undef DDR_PHY_MR11_DQODT_DEFVAL
7968 #undef DDR_PHY_MR11_DQODT_SHIFT
7969 #undef DDR_PHY_MR11_DQODT_MASK
7970 #define DDR_PHY_MR11_DQODT_DEFVAL 0x00000000
7971 #define DDR_PHY_MR11_DQODT_SHIFT 0
7972 #define DDR_PHY_MR11_DQODT_MASK 0x00000003U
7974 /*Reserved. Return zeroes on reads.*/
7975 #undef DDR_PHY_MR12_RESERVED_31_8_DEFVAL
7976 #undef DDR_PHY_MR12_RESERVED_31_8_SHIFT
7977 #undef DDR_PHY_MR12_RESERVED_31_8_MASK
7978 #define DDR_PHY_MR12_RESERVED_31_8_DEFVAL 0x0000004D
7979 #define DDR_PHY_MR12_RESERVED_31_8_SHIFT 8
7980 #define DDR_PHY_MR12_RESERVED_31_8_MASK 0xFFFFFF00U
7982 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
7983 #undef DDR_PHY_MR12_RSVD_DEFVAL
7984 #undef DDR_PHY_MR12_RSVD_SHIFT
7985 #undef DDR_PHY_MR12_RSVD_MASK
7986 #define DDR_PHY_MR12_RSVD_DEFVAL 0x0000004D
7987 #define DDR_PHY_MR12_RSVD_SHIFT 7
7988 #define DDR_PHY_MR12_RSVD_MASK 0x00000080U
7990 /*VREF_CA Range Select.*/
7991 #undef DDR_PHY_MR12_VR_CA_DEFVAL
7992 #undef DDR_PHY_MR12_VR_CA_SHIFT
7993 #undef DDR_PHY_MR12_VR_CA_MASK
7994 #define DDR_PHY_MR12_VR_CA_DEFVAL 0x0000004D
7995 #define DDR_PHY_MR12_VR_CA_SHIFT 6
7996 #define DDR_PHY_MR12_VR_CA_MASK 0x00000040U
7998 /*Controls the VREF(ca) levels for Frequency-Set-Point[1:0].*/
7999 #undef DDR_PHY_MR12_VREF_CA_DEFVAL
8000 #undef DDR_PHY_MR12_VREF_CA_SHIFT
8001 #undef DDR_PHY_MR12_VREF_CA_MASK
8002 #define DDR_PHY_MR12_VREF_CA_DEFVAL 0x0000004D
8003 #define DDR_PHY_MR12_VREF_CA_SHIFT 0
8004 #define DDR_PHY_MR12_VREF_CA_MASK 0x0000003FU
8006 /*Reserved. Return zeroes on reads.*/
8007 #undef DDR_PHY_MR13_RESERVED_31_8_DEFVAL
8008 #undef DDR_PHY_MR13_RESERVED_31_8_SHIFT
8009 #undef DDR_PHY_MR13_RESERVED_31_8_MASK
8010 #define DDR_PHY_MR13_RESERVED_31_8_DEFVAL 0x00000000
8011 #define DDR_PHY_MR13_RESERVED_31_8_SHIFT 8
8012 #define DDR_PHY_MR13_RESERVED_31_8_MASK 0xFFFFFF00U
8014 /*Frequency Set Point Operation Mode*/
8015 #undef DDR_PHY_MR13_FSPOP_DEFVAL
8016 #undef DDR_PHY_MR13_FSPOP_SHIFT
8017 #undef DDR_PHY_MR13_FSPOP_MASK
8018 #define DDR_PHY_MR13_FSPOP_DEFVAL 0x00000000
8019 #define DDR_PHY_MR13_FSPOP_SHIFT 7
8020 #define DDR_PHY_MR13_FSPOP_MASK 0x00000080U
8022 /*Frequency Set Point Write Enable*/
8023 #undef DDR_PHY_MR13_FSPWR_DEFVAL
8024 #undef DDR_PHY_MR13_FSPWR_SHIFT
8025 #undef DDR_PHY_MR13_FSPWR_MASK
8026 #define DDR_PHY_MR13_FSPWR_DEFVAL 0x00000000
8027 #define DDR_PHY_MR13_FSPWR_SHIFT 6
8028 #define DDR_PHY_MR13_FSPWR_MASK 0x00000040U
8030 /*Data Mask Enable*/
8031 #undef DDR_PHY_MR13_DMD_DEFVAL
8032 #undef DDR_PHY_MR13_DMD_SHIFT
8033 #undef DDR_PHY_MR13_DMD_MASK
8034 #define DDR_PHY_MR13_DMD_DEFVAL 0x00000000
8035 #define DDR_PHY_MR13_DMD_SHIFT 5
8036 #define DDR_PHY_MR13_DMD_MASK 0x00000020U
8038 /*Refresh Rate Option*/
8039 #undef DDR_PHY_MR13_RRO_DEFVAL
8040 #undef DDR_PHY_MR13_RRO_SHIFT
8041 #undef DDR_PHY_MR13_RRO_MASK
8042 #define DDR_PHY_MR13_RRO_DEFVAL 0x00000000
8043 #define DDR_PHY_MR13_RRO_SHIFT 4
8044 #define DDR_PHY_MR13_RRO_MASK 0x00000010U
8046 /*VREF Current Generator*/
8047 #undef DDR_PHY_MR13_VRCG_DEFVAL
8048 #undef DDR_PHY_MR13_VRCG_SHIFT
8049 #undef DDR_PHY_MR13_VRCG_MASK
8050 #define DDR_PHY_MR13_VRCG_DEFVAL 0x00000000
8051 #define DDR_PHY_MR13_VRCG_SHIFT 3
8052 #define DDR_PHY_MR13_VRCG_MASK 0x00000008U
8055 #undef DDR_PHY_MR13_VRO_DEFVAL
8056 #undef DDR_PHY_MR13_VRO_SHIFT
8057 #undef DDR_PHY_MR13_VRO_MASK
8058 #define DDR_PHY_MR13_VRO_DEFVAL 0x00000000
8059 #define DDR_PHY_MR13_VRO_SHIFT 2
8060 #define DDR_PHY_MR13_VRO_MASK 0x00000004U
8062 /*Read Preamble Training Mode*/
8063 #undef DDR_PHY_MR13_RPT_DEFVAL
8064 #undef DDR_PHY_MR13_RPT_SHIFT
8065 #undef DDR_PHY_MR13_RPT_MASK
8066 #define DDR_PHY_MR13_RPT_DEFVAL 0x00000000
8067 #define DDR_PHY_MR13_RPT_SHIFT 1
8068 #define DDR_PHY_MR13_RPT_MASK 0x00000002U
8070 /*Command Bus Training*/
8071 #undef DDR_PHY_MR13_CBT_DEFVAL
8072 #undef DDR_PHY_MR13_CBT_SHIFT
8073 #undef DDR_PHY_MR13_CBT_MASK
8074 #define DDR_PHY_MR13_CBT_DEFVAL 0x00000000
8075 #define DDR_PHY_MR13_CBT_SHIFT 0
8076 #define DDR_PHY_MR13_CBT_MASK 0x00000001U
8078 /*Reserved. Return zeroes on reads.*/
8079 #undef DDR_PHY_MR14_RESERVED_31_8_DEFVAL
8080 #undef DDR_PHY_MR14_RESERVED_31_8_SHIFT
8081 #undef DDR_PHY_MR14_RESERVED_31_8_MASK
8082 #define DDR_PHY_MR14_RESERVED_31_8_DEFVAL 0x0000004D
8083 #define DDR_PHY_MR14_RESERVED_31_8_SHIFT 8
8084 #define DDR_PHY_MR14_RESERVED_31_8_MASK 0xFFFFFF00U
8086 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
8087 #undef DDR_PHY_MR14_RSVD_DEFVAL
8088 #undef DDR_PHY_MR14_RSVD_SHIFT
8089 #undef DDR_PHY_MR14_RSVD_MASK
8090 #define DDR_PHY_MR14_RSVD_DEFVAL 0x0000004D
8091 #define DDR_PHY_MR14_RSVD_SHIFT 7
8092 #define DDR_PHY_MR14_RSVD_MASK 0x00000080U
8094 /*VREFDQ Range Selects.*/
8095 #undef DDR_PHY_MR14_VR_DQ_DEFVAL
8096 #undef DDR_PHY_MR14_VR_DQ_SHIFT
8097 #undef DDR_PHY_MR14_VR_DQ_MASK
8098 #define DDR_PHY_MR14_VR_DQ_DEFVAL 0x0000004D
8099 #define DDR_PHY_MR14_VR_DQ_SHIFT 6
8100 #define DDR_PHY_MR14_VR_DQ_MASK 0x00000040U
8102 /*Reserved. Return zeroes on reads.*/
8103 #undef DDR_PHY_MR14_VREF_DQ_DEFVAL
8104 #undef DDR_PHY_MR14_VREF_DQ_SHIFT
8105 #undef DDR_PHY_MR14_VREF_DQ_MASK
8106 #define DDR_PHY_MR14_VREF_DQ_DEFVAL 0x0000004D
8107 #define DDR_PHY_MR14_VREF_DQ_SHIFT 0
8108 #define DDR_PHY_MR14_VREF_DQ_MASK 0x0000003FU
8110 /*Reserved. Return zeroes on reads.*/
8111 #undef DDR_PHY_MR22_RESERVED_31_8_DEFVAL
8112 #undef DDR_PHY_MR22_RESERVED_31_8_SHIFT
8113 #undef DDR_PHY_MR22_RESERVED_31_8_MASK
8114 #define DDR_PHY_MR22_RESERVED_31_8_DEFVAL 0x00000000
8115 #define DDR_PHY_MR22_RESERVED_31_8_SHIFT 8
8116 #define DDR_PHY_MR22_RESERVED_31_8_MASK 0xFFFFFF00U
8118 /*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
8119 #undef DDR_PHY_MR22_RSVD_DEFVAL
8120 #undef DDR_PHY_MR22_RSVD_SHIFT
8121 #undef DDR_PHY_MR22_RSVD_MASK
8122 #define DDR_PHY_MR22_RSVD_DEFVAL 0x00000000
8123 #define DDR_PHY_MR22_RSVD_SHIFT 6
8124 #define DDR_PHY_MR22_RSVD_MASK 0x000000C0U
8126 /*CA ODT termination disable.*/
8127 #undef DDR_PHY_MR22_ODTD_CA_DEFVAL
8128 #undef DDR_PHY_MR22_ODTD_CA_SHIFT
8129 #undef DDR_PHY_MR22_ODTD_CA_MASK
8130 #define DDR_PHY_MR22_ODTD_CA_DEFVAL 0x00000000
8131 #define DDR_PHY_MR22_ODTD_CA_SHIFT 5
8132 #define DDR_PHY_MR22_ODTD_CA_MASK 0x00000020U
8134 /*ODT CS override.*/
8135 #undef DDR_PHY_MR22_ODTE_CS_DEFVAL
8136 #undef DDR_PHY_MR22_ODTE_CS_SHIFT
8137 #undef DDR_PHY_MR22_ODTE_CS_MASK
8138 #define DDR_PHY_MR22_ODTE_CS_DEFVAL 0x00000000
8139 #define DDR_PHY_MR22_ODTE_CS_SHIFT 4
8140 #define DDR_PHY_MR22_ODTE_CS_MASK 0x00000010U
8142 /*ODT CK override.*/
8143 #undef DDR_PHY_MR22_ODTE_CK_DEFVAL
8144 #undef DDR_PHY_MR22_ODTE_CK_SHIFT
8145 #undef DDR_PHY_MR22_ODTE_CK_MASK
8146 #define DDR_PHY_MR22_ODTE_CK_DEFVAL 0x00000000
8147 #define DDR_PHY_MR22_ODTE_CK_SHIFT 3
8148 #define DDR_PHY_MR22_ODTE_CK_MASK 0x00000008U
8150 /*Controller ODT value for VOH calibration.*/
8151 #undef DDR_PHY_MR22_CODT_DEFVAL
8152 #undef DDR_PHY_MR22_CODT_SHIFT
8153 #undef DDR_PHY_MR22_CODT_MASK
8154 #define DDR_PHY_MR22_CODT_DEFVAL 0x00000000
8155 #define DDR_PHY_MR22_CODT_SHIFT 0
8156 #define DDR_PHY_MR22_CODT_MASK 0x00000007U
8158 /*Refresh During Training*/
8159 #undef DDR_PHY_DTCR0_RFSHDT_DEFVAL
8160 #undef DDR_PHY_DTCR0_RFSHDT_SHIFT
8161 #undef DDR_PHY_DTCR0_RFSHDT_MASK
8162 #define DDR_PHY_DTCR0_RFSHDT_DEFVAL 0x800091C7
8163 #define DDR_PHY_DTCR0_RFSHDT_SHIFT 28
8164 #define DDR_PHY_DTCR0_RFSHDT_MASK 0xF0000000U
8166 /*Reserved. Return zeroes on reads.*/
8167 #undef DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL
8168 #undef DDR_PHY_DTCR0_RESERVED_27_26_SHIFT
8169 #undef DDR_PHY_DTCR0_RESERVED_27_26_MASK
8170 #define DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL 0x800091C7
8171 #define DDR_PHY_DTCR0_RESERVED_27_26_SHIFT 26
8172 #define DDR_PHY_DTCR0_RESERVED_27_26_MASK 0x0C000000U
8174 /*Data Training Debug Rank Select*/
8175 #undef DDR_PHY_DTCR0_DTDRS_DEFVAL
8176 #undef DDR_PHY_DTCR0_DTDRS_SHIFT
8177 #undef DDR_PHY_DTCR0_DTDRS_MASK
8178 #define DDR_PHY_DTCR0_DTDRS_DEFVAL 0x800091C7
8179 #define DDR_PHY_DTCR0_DTDRS_SHIFT 24
8180 #define DDR_PHY_DTCR0_DTDRS_MASK 0x03000000U
8182 /*Data Training with Early/Extended Gate*/
8183 #undef DDR_PHY_DTCR0_DTEXG_DEFVAL
8184 #undef DDR_PHY_DTCR0_DTEXG_SHIFT
8185 #undef DDR_PHY_DTCR0_DTEXG_MASK
8186 #define DDR_PHY_DTCR0_DTEXG_DEFVAL 0x800091C7
8187 #define DDR_PHY_DTCR0_DTEXG_SHIFT 23
8188 #define DDR_PHY_DTCR0_DTEXG_MASK 0x00800000U
8190 /*Data Training Extended Write DQS*/
8191 #undef DDR_PHY_DTCR0_DTEXD_DEFVAL
8192 #undef DDR_PHY_DTCR0_DTEXD_SHIFT
8193 #undef DDR_PHY_DTCR0_DTEXD_MASK
8194 #define DDR_PHY_DTCR0_DTEXD_DEFVAL 0x800091C7
8195 #define DDR_PHY_DTCR0_DTEXD_SHIFT 22
8196 #define DDR_PHY_DTCR0_DTEXD_MASK 0x00400000U
8198 /*Data Training Debug Step*/
8199 #undef DDR_PHY_DTCR0_DTDSTP_DEFVAL
8200 #undef DDR_PHY_DTCR0_DTDSTP_SHIFT
8201 #undef DDR_PHY_DTCR0_DTDSTP_MASK
8202 #define DDR_PHY_DTCR0_DTDSTP_DEFVAL 0x800091C7
8203 #define DDR_PHY_DTCR0_DTDSTP_SHIFT 21
8204 #define DDR_PHY_DTCR0_DTDSTP_MASK 0x00200000U
8206 /*Data Training Debug Enable*/
8207 #undef DDR_PHY_DTCR0_DTDEN_DEFVAL
8208 #undef DDR_PHY_DTCR0_DTDEN_SHIFT
8209 #undef DDR_PHY_DTCR0_DTDEN_MASK
8210 #define DDR_PHY_DTCR0_DTDEN_DEFVAL 0x800091C7
8211 #define DDR_PHY_DTCR0_DTDEN_SHIFT 20
8212 #define DDR_PHY_DTCR0_DTDEN_MASK 0x00100000U
8214 /*Data Training Debug Byte Select*/
8215 #undef DDR_PHY_DTCR0_DTDBS_DEFVAL
8216 #undef DDR_PHY_DTCR0_DTDBS_SHIFT
8217 #undef DDR_PHY_DTCR0_DTDBS_MASK
8218 #define DDR_PHY_DTCR0_DTDBS_DEFVAL 0x800091C7
8219 #define DDR_PHY_DTCR0_DTDBS_SHIFT 16
8220 #define DDR_PHY_DTCR0_DTDBS_MASK 0x000F0000U
8222 /*Data Training read DBI deskewing configuration*/
8223 #undef DDR_PHY_DTCR0_DTRDBITR_DEFVAL
8224 #undef DDR_PHY_DTCR0_DTRDBITR_SHIFT
8225 #undef DDR_PHY_DTCR0_DTRDBITR_MASK
8226 #define DDR_PHY_DTCR0_DTRDBITR_DEFVAL 0x800091C7
8227 #define DDR_PHY_DTCR0_DTRDBITR_SHIFT 14
8228 #define DDR_PHY_DTCR0_DTRDBITR_MASK 0x0000C000U
8230 /*Reserved. Return zeroes on reads.*/
8231 #undef DDR_PHY_DTCR0_RESERVED_13_DEFVAL
8232 #undef DDR_PHY_DTCR0_RESERVED_13_SHIFT
8233 #undef DDR_PHY_DTCR0_RESERVED_13_MASK
8234 #define DDR_PHY_DTCR0_RESERVED_13_DEFVAL 0x800091C7
8235 #define DDR_PHY_DTCR0_RESERVED_13_SHIFT 13
8236 #define DDR_PHY_DTCR0_RESERVED_13_MASK 0x00002000U
8238 /*Data Training Write Bit Deskew Data Mask*/
8239 #undef DDR_PHY_DTCR0_DTWBDDM_DEFVAL
8240 #undef DDR_PHY_DTCR0_DTWBDDM_SHIFT
8241 #undef DDR_PHY_DTCR0_DTWBDDM_MASK
8242 #define DDR_PHY_DTCR0_DTWBDDM_DEFVAL 0x800091C7
8243 #define DDR_PHY_DTCR0_DTWBDDM_SHIFT 12
8244 #define DDR_PHY_DTCR0_DTWBDDM_MASK 0x00001000U
8246 /*Refreshes Issued During Entry to Training*/
8247 #undef DDR_PHY_DTCR0_RFSHEN_DEFVAL
8248 #undef DDR_PHY_DTCR0_RFSHEN_SHIFT
8249 #undef DDR_PHY_DTCR0_RFSHEN_MASK
8250 #define DDR_PHY_DTCR0_RFSHEN_DEFVAL 0x800091C7
8251 #define DDR_PHY_DTCR0_RFSHEN_SHIFT 8
8252 #define DDR_PHY_DTCR0_RFSHEN_MASK 0x00000F00U
8254 /*Data Training Compare Data*/
8255 #undef DDR_PHY_DTCR0_DTCMPD_DEFVAL
8256 #undef DDR_PHY_DTCR0_DTCMPD_SHIFT
8257 #undef DDR_PHY_DTCR0_DTCMPD_MASK
8258 #define DDR_PHY_DTCR0_DTCMPD_DEFVAL 0x800091C7
8259 #define DDR_PHY_DTCR0_DTCMPD_SHIFT 7
8260 #define DDR_PHY_DTCR0_DTCMPD_MASK 0x00000080U
8262 /*Data Training Using MPR*/
8263 #undef DDR_PHY_DTCR0_DTMPR_DEFVAL
8264 #undef DDR_PHY_DTCR0_DTMPR_SHIFT
8265 #undef DDR_PHY_DTCR0_DTMPR_MASK
8266 #define DDR_PHY_DTCR0_DTMPR_DEFVAL 0x800091C7
8267 #define DDR_PHY_DTCR0_DTMPR_SHIFT 6
8268 #define DDR_PHY_DTCR0_DTMPR_MASK 0x00000040U
8270 /*Reserved. Return zeroes on reads.*/
8271 #undef DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL
8272 #undef DDR_PHY_DTCR0_RESERVED_5_4_SHIFT
8273 #undef DDR_PHY_DTCR0_RESERVED_5_4_MASK
8274 #define DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL 0x800091C7
8275 #define DDR_PHY_DTCR0_RESERVED_5_4_SHIFT 4
8276 #define DDR_PHY_DTCR0_RESERVED_5_4_MASK 0x00000030U
8278 /*Data Training Repeat Number*/
8279 #undef DDR_PHY_DTCR0_DTRPTN_DEFVAL
8280 #undef DDR_PHY_DTCR0_DTRPTN_SHIFT
8281 #undef DDR_PHY_DTCR0_DTRPTN_MASK
8282 #define DDR_PHY_DTCR0_DTRPTN_DEFVAL 0x800091C7
8283 #define DDR_PHY_DTCR0_DTRPTN_SHIFT 0
8284 #define DDR_PHY_DTCR0_DTRPTN_MASK 0x0000000FU
8287 #undef DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL
8288 #undef DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT
8289 #undef DDR_PHY_DTCR1_RANKEN_RSVD_MASK
8290 #define DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL 0x00030237
8291 #define DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT 18
8292 #define DDR_PHY_DTCR1_RANKEN_RSVD_MASK 0xFFFC0000U
8295 #undef DDR_PHY_DTCR1_RANKEN_DEFVAL
8296 #undef DDR_PHY_DTCR1_RANKEN_SHIFT
8297 #undef DDR_PHY_DTCR1_RANKEN_MASK
8298 #define DDR_PHY_DTCR1_RANKEN_DEFVAL 0x00030237
8299 #define DDR_PHY_DTCR1_RANKEN_SHIFT 16
8300 #define DDR_PHY_DTCR1_RANKEN_MASK 0x00030000U
8302 /*Reserved. Return zeroes on reads.*/
8303 #undef DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL
8304 #undef DDR_PHY_DTCR1_RESERVED_15_14_SHIFT
8305 #undef DDR_PHY_DTCR1_RESERVED_15_14_MASK
8306 #define DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL 0x00030237
8307 #define DDR_PHY_DTCR1_RESERVED_15_14_SHIFT 14
8308 #define DDR_PHY_DTCR1_RESERVED_15_14_MASK 0x0000C000U
8310 /*Data Training Rank*/
8311 #undef DDR_PHY_DTCR1_DTRANK_DEFVAL
8312 #undef DDR_PHY_DTCR1_DTRANK_SHIFT
8313 #undef DDR_PHY_DTCR1_DTRANK_MASK
8314 #define DDR_PHY_DTCR1_DTRANK_DEFVAL 0x00030237
8315 #define DDR_PHY_DTCR1_DTRANK_SHIFT 12
8316 #define DDR_PHY_DTCR1_DTRANK_MASK 0x00003000U
8318 /*Reserved. Return zeroes on reads.*/
8319 #undef DDR_PHY_DTCR1_RESERVED_11_DEFVAL
8320 #undef DDR_PHY_DTCR1_RESERVED_11_SHIFT
8321 #undef DDR_PHY_DTCR1_RESERVED_11_MASK
8322 #define DDR_PHY_DTCR1_RESERVED_11_DEFVAL 0x00030237
8323 #define DDR_PHY_DTCR1_RESERVED_11_SHIFT 11
8324 #define DDR_PHY_DTCR1_RESERVED_11_MASK 0x00000800U
8326 /*Read Leveling Gate Sampling Difference*/
8327 #undef DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL
8328 #undef DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT
8329 #undef DDR_PHY_DTCR1_RDLVLGDIFF_MASK
8330 #define DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL 0x00030237
8331 #define DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT 8
8332 #define DDR_PHY_DTCR1_RDLVLGDIFF_MASK 0x00000700U
8334 /*Reserved. Return zeroes on reads.*/
8335 #undef DDR_PHY_DTCR1_RESERVED_7_DEFVAL
8336 #undef DDR_PHY_DTCR1_RESERVED_7_SHIFT
8337 #undef DDR_PHY_DTCR1_RESERVED_7_MASK
8338 #define DDR_PHY_DTCR1_RESERVED_7_DEFVAL 0x00030237
8339 #define DDR_PHY_DTCR1_RESERVED_7_SHIFT 7
8340 #define DDR_PHY_DTCR1_RESERVED_7_MASK 0x00000080U
8342 /*Read Leveling Gate Shift*/
8343 #undef DDR_PHY_DTCR1_RDLVLGS_DEFVAL
8344 #undef DDR_PHY_DTCR1_RDLVLGS_SHIFT
8345 #undef DDR_PHY_DTCR1_RDLVLGS_MASK
8346 #define DDR_PHY_DTCR1_RDLVLGS_DEFVAL 0x00030237
8347 #define DDR_PHY_DTCR1_RDLVLGS_SHIFT 4
8348 #define DDR_PHY_DTCR1_RDLVLGS_MASK 0x00000070U
8350 /*Reserved. Return zeroes on reads.*/
8351 #undef DDR_PHY_DTCR1_RESERVED_3_DEFVAL
8352 #undef DDR_PHY_DTCR1_RESERVED_3_SHIFT
8353 #undef DDR_PHY_DTCR1_RESERVED_3_MASK
8354 #define DDR_PHY_DTCR1_RESERVED_3_DEFVAL 0x00030237
8355 #define DDR_PHY_DTCR1_RESERVED_3_SHIFT 3
8356 #define DDR_PHY_DTCR1_RESERVED_3_MASK 0x00000008U
8358 /*Read Preamble Training enable*/
8359 #undef DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL
8360 #undef DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT
8361 #undef DDR_PHY_DTCR1_RDPRMVL_TRN_MASK
8362 #define DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL 0x00030237
8363 #define DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT 2
8364 #define DDR_PHY_DTCR1_RDPRMVL_TRN_MASK 0x00000004U
8366 /*Read Leveling Enable*/
8367 #undef DDR_PHY_DTCR1_RDLVLEN_DEFVAL
8368 #undef DDR_PHY_DTCR1_RDLVLEN_SHIFT
8369 #undef DDR_PHY_DTCR1_RDLVLEN_MASK
8370 #define DDR_PHY_DTCR1_RDLVLEN_DEFVAL 0x00030237
8371 #define DDR_PHY_DTCR1_RDLVLEN_SHIFT 1
8372 #define DDR_PHY_DTCR1_RDLVLEN_MASK 0x00000002U
8374 /*Basic Gate Training Enable*/
8375 #undef DDR_PHY_DTCR1_BSTEN_DEFVAL
8376 #undef DDR_PHY_DTCR1_BSTEN_SHIFT
8377 #undef DDR_PHY_DTCR1_BSTEN_MASK
8378 #define DDR_PHY_DTCR1_BSTEN_DEFVAL 0x00030237
8379 #define DDR_PHY_DTCR1_BSTEN_SHIFT 0
8380 #define DDR_PHY_DTCR1_BSTEN_MASK 0x00000001U
8382 /*Reserved. Return zeroes on reads.*/
8383 #undef DDR_PHY_CATR0_RESERVED_31_21_DEFVAL
8384 #undef DDR_PHY_CATR0_RESERVED_31_21_SHIFT
8385 #undef DDR_PHY_CATR0_RESERVED_31_21_MASK
8386 #define DDR_PHY_CATR0_RESERVED_31_21_DEFVAL 0x00141054
8387 #define DDR_PHY_CATR0_RESERVED_31_21_SHIFT 21
8388 #define DDR_PHY_CATR0_RESERVED_31_21_MASK 0xFFE00000U
8390 /*Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command*/
8391 #undef DDR_PHY_CATR0_CACD_DEFVAL
8392 #undef DDR_PHY_CATR0_CACD_SHIFT
8393 #undef DDR_PHY_CATR0_CACD_MASK
8394 #define DDR_PHY_CATR0_CACD_DEFVAL 0x00141054
8395 #define DDR_PHY_CATR0_CACD_SHIFT 16
8396 #define DDR_PHY_CATR0_CACD_MASK 0x001F0000U
8398 /*Reserved. Return zeroes on reads.*/
8399 #undef DDR_PHY_CATR0_RESERVED_15_13_DEFVAL
8400 #undef DDR_PHY_CATR0_RESERVED_15_13_SHIFT
8401 #undef DDR_PHY_CATR0_RESERVED_15_13_MASK
8402 #define DDR_PHY_CATR0_RESERVED_15_13_DEFVAL 0x00141054
8403 #define DDR_PHY_CATR0_RESERVED_15_13_SHIFT 13
8404 #define DDR_PHY_CATR0_RESERVED_15_13_MASK 0x0000E000U
8406 /*Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha
8407 been sent to the memory*/
8408 #undef DDR_PHY_CATR0_CAADR_DEFVAL
8409 #undef DDR_PHY_CATR0_CAADR_SHIFT
8410 #undef DDR_PHY_CATR0_CAADR_MASK
8411 #define DDR_PHY_CATR0_CAADR_DEFVAL 0x00141054
8412 #define DDR_PHY_CATR0_CAADR_SHIFT 8
8413 #define DDR_PHY_CATR0_CAADR_MASK 0x00001F00U
8415 /*CA_1 Response Byte Lane 1*/
8416 #undef DDR_PHY_CATR0_CA1BYTE1_DEFVAL
8417 #undef DDR_PHY_CATR0_CA1BYTE1_SHIFT
8418 #undef DDR_PHY_CATR0_CA1BYTE1_MASK
8419 #define DDR_PHY_CATR0_CA1BYTE1_DEFVAL 0x00141054
8420 #define DDR_PHY_CATR0_CA1BYTE1_SHIFT 4
8421 #define DDR_PHY_CATR0_CA1BYTE1_MASK 0x000000F0U
8423 /*CA_1 Response Byte Lane 0*/
8424 #undef DDR_PHY_CATR0_CA1BYTE0_DEFVAL
8425 #undef DDR_PHY_CATR0_CA1BYTE0_SHIFT
8426 #undef DDR_PHY_CATR0_CA1BYTE0_MASK
8427 #define DDR_PHY_CATR0_CA1BYTE0_DEFVAL 0x00141054
8428 #define DDR_PHY_CATR0_CA1BYTE0_SHIFT 0
8429 #define DDR_PHY_CATR0_CA1BYTE0_MASK 0x0000000FU
8431 /*LFSR seed for pseudo-random BIST patterns*/
8432 #undef DDR_PHY_BISTLSR_SEED_DEFVAL
8433 #undef DDR_PHY_BISTLSR_SEED_SHIFT
8434 #undef DDR_PHY_BISTLSR_SEED_MASK
8435 #define DDR_PHY_BISTLSR_SEED_DEFVAL
8436 #define DDR_PHY_BISTLSR_SEED_SHIFT 0
8437 #define DDR_PHY_BISTLSR_SEED_MASK 0xFFFFFFFFU
8439 /*Reserved. Return zeroes on reads.*/
8440 #undef DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL
8441 #undef DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT
8442 #undef DDR_PHY_RIOCR5_RESERVED_31_16_MASK
8443 #define DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL 0x00000005
8444 #define DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT 16
8445 #define DDR_PHY_RIOCR5_RESERVED_31_16_MASK 0xFFFF0000U
8447 /*Reserved. Return zeros on reads.*/
8448 #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL
8449 #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT
8450 #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK
8451 #define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL 0x00000005
8452 #define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT 4
8453 #define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK 0x0000FFF0U
8455 /*SDRAM On-die Termination Output Enable (OE) Mode Selection.*/
8456 #undef DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL
8457 #undef DDR_PHY_RIOCR5_ODTOEMODE_SHIFT
8458 #undef DDR_PHY_RIOCR5_ODTOEMODE_MASK
8459 #define DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL 0x00000005
8460 #define DDR_PHY_RIOCR5_ODTOEMODE_SHIFT 0
8461 #define DDR_PHY_RIOCR5_ODTOEMODE_MASK 0x0000000FU
8463 /*Address/Command Slew Rate (D3F I/O Only)*/
8464 #undef DDR_PHY_ACIOCR0_ACSR_DEFVAL
8465 #undef DDR_PHY_ACIOCR0_ACSR_SHIFT
8466 #undef DDR_PHY_ACIOCR0_ACSR_MASK
8467 #define DDR_PHY_ACIOCR0_ACSR_DEFVAL 0x30000000
8468 #define DDR_PHY_ACIOCR0_ACSR_SHIFT 30
8469 #define DDR_PHY_ACIOCR0_ACSR_MASK 0xC0000000U
8471 /*SDRAM Reset I/O Mode*/
8472 #undef DDR_PHY_ACIOCR0_RSTIOM_DEFVAL
8473 #undef DDR_PHY_ACIOCR0_RSTIOM_SHIFT
8474 #undef DDR_PHY_ACIOCR0_RSTIOM_MASK
8475 #define DDR_PHY_ACIOCR0_RSTIOM_DEFVAL 0x30000000
8476 #define DDR_PHY_ACIOCR0_RSTIOM_SHIFT 29
8477 #define DDR_PHY_ACIOCR0_RSTIOM_MASK 0x20000000U
8479 /*SDRAM Reset Power Down Receiver*/
8480 #undef DDR_PHY_ACIOCR0_RSTPDR_DEFVAL
8481 #undef DDR_PHY_ACIOCR0_RSTPDR_SHIFT
8482 #undef DDR_PHY_ACIOCR0_RSTPDR_MASK
8483 #define DDR_PHY_ACIOCR0_RSTPDR_DEFVAL 0x30000000
8484 #define DDR_PHY_ACIOCR0_RSTPDR_SHIFT 28
8485 #define DDR_PHY_ACIOCR0_RSTPDR_MASK 0x10000000U
8487 /*Reserved. Return zeroes on reads.*/
8488 #undef DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL
8489 #undef DDR_PHY_ACIOCR0_RESERVED_27_SHIFT
8490 #undef DDR_PHY_ACIOCR0_RESERVED_27_MASK
8491 #define DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL 0x30000000
8492 #define DDR_PHY_ACIOCR0_RESERVED_27_SHIFT 27
8493 #define DDR_PHY_ACIOCR0_RESERVED_27_MASK 0x08000000U
8495 /*SDRAM Reset On-Die Termination*/
8496 #undef DDR_PHY_ACIOCR0_RSTODT_DEFVAL
8497 #undef DDR_PHY_ACIOCR0_RSTODT_SHIFT
8498 #undef DDR_PHY_ACIOCR0_RSTODT_MASK
8499 #define DDR_PHY_ACIOCR0_RSTODT_DEFVAL 0x30000000
8500 #define DDR_PHY_ACIOCR0_RSTODT_SHIFT 26
8501 #define DDR_PHY_ACIOCR0_RSTODT_MASK 0x04000000U
8503 /*Reserved. Return zeroes on reads.*/
8504 #undef DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL
8505 #undef DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT
8506 #undef DDR_PHY_ACIOCR0_RESERVED_25_10_MASK
8507 #define DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL 0x30000000
8508 #define DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT 10
8509 #define DDR_PHY_ACIOCR0_RESERVED_25_10_MASK 0x03FFFC00U
8511 /*CK Duty Cycle Correction*/
8512 #undef DDR_PHY_ACIOCR0_CKDCC_DEFVAL
8513 #undef DDR_PHY_ACIOCR0_CKDCC_SHIFT
8514 #undef DDR_PHY_ACIOCR0_CKDCC_MASK
8515 #define DDR_PHY_ACIOCR0_CKDCC_DEFVAL 0x30000000
8516 #define DDR_PHY_ACIOCR0_CKDCC_SHIFT 6
8517 #define DDR_PHY_ACIOCR0_CKDCC_MASK 0x000003C0U
8519 /*AC Power Down Receiver Mode*/
8520 #undef DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL
8521 #undef DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT
8522 #undef DDR_PHY_ACIOCR0_ACPDRMODE_MASK
8523 #define DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL 0x30000000
8524 #define DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT 4
8525 #define DDR_PHY_ACIOCR0_ACPDRMODE_MASK 0x00000030U
8527 /*AC On-die Termination Mode*/
8528 #undef DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL
8529 #undef DDR_PHY_ACIOCR0_ACODTMODE_SHIFT
8530 #undef DDR_PHY_ACIOCR0_ACODTMODE_MASK
8531 #define DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL 0x30000000
8532 #define DDR_PHY_ACIOCR0_ACODTMODE_SHIFT 2
8533 #define DDR_PHY_ACIOCR0_ACODTMODE_MASK 0x0000000CU
8535 /*Reserved. Return zeroes on reads.*/
8536 #undef DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL
8537 #undef DDR_PHY_ACIOCR0_RESERVED_1_SHIFT
8538 #undef DDR_PHY_ACIOCR0_RESERVED_1_MASK
8539 #define DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL 0x30000000
8540 #define DDR_PHY_ACIOCR0_RESERVED_1_SHIFT 1
8541 #define DDR_PHY_ACIOCR0_RESERVED_1_MASK 0x00000002U
8543 /*Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.*/
8544 #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL
8545 #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT
8546 #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK
8547 #define DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL 0x30000000
8548 #define DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT 0
8549 #define DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK 0x00000001U
8551 /*Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice*/
8552 #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL
8553 #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT
8554 #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK
8555 #define DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL 0x00000000
8556 #define DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT 31
8557 #define DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK 0x80000000U
8559 /*Clock gating for Output Enable D slices [0]*/
8560 #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL
8561 #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT
8562 #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK
8563 #define DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL 0x00000000
8564 #define DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT 30
8565 #define DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK 0x40000000U
8567 /*Clock gating for Power Down Receiver D slices [0]*/
8568 #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL
8569 #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT
8570 #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK
8571 #define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL 0x00000000
8572 #define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT 29
8573 #define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK 0x20000000U
8575 /*Clock gating for Termination Enable D slices [0]*/
8576 #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL
8577 #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT
8578 #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK
8579 #define DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL 0x00000000
8580 #define DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT 28
8581 #define DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK 0x10000000U
8583 /*Clock gating for CK# D slices [1:0]*/
8584 #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL
8585 #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT
8586 #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK
8587 #define DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL 0x00000000
8588 #define DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT 26
8589 #define DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK 0x0C000000U
8591 /*Clock gating for CK D slices [1:0]*/
8592 #undef DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL
8593 #undef DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT
8594 #undef DDR_PHY_ACIOCR2_CKCLKGATE0_MASK
8595 #define DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL 0x00000000
8596 #define DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT 24
8597 #define DDR_PHY_ACIOCR2_CKCLKGATE0_MASK 0x03000000U
8599 /*Clock gating for AC D slices [23:0]*/
8600 #undef DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL
8601 #undef DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT
8602 #undef DDR_PHY_ACIOCR2_ACCLKGATE0_MASK
8603 #define DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL 0x00000000
8604 #define DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT 0
8605 #define DDR_PHY_ACIOCR2_ACCLKGATE0_MASK 0x00FFFFFFU
8607 /*SDRAM Parity Output Enable (OE) Mode Selection*/
8608 #undef DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL
8609 #undef DDR_PHY_ACIOCR3_PAROEMODE_SHIFT
8610 #undef DDR_PHY_ACIOCR3_PAROEMODE_MASK
8611 #define DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL 0x00000005
8612 #define DDR_PHY_ACIOCR3_PAROEMODE_SHIFT 30
8613 #define DDR_PHY_ACIOCR3_PAROEMODE_MASK 0xC0000000U
8615 /*SDRAM Bank Group Output Enable (OE) Mode Selection*/
8616 #undef DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL
8617 #undef DDR_PHY_ACIOCR3_BGOEMODE_SHIFT
8618 #undef DDR_PHY_ACIOCR3_BGOEMODE_MASK
8619 #define DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL 0x00000005
8620 #define DDR_PHY_ACIOCR3_BGOEMODE_SHIFT 26
8621 #define DDR_PHY_ACIOCR3_BGOEMODE_MASK 0x3C000000U
8623 /*SDRAM Bank Address Output Enable (OE) Mode Selection*/
8624 #undef DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL
8625 #undef DDR_PHY_ACIOCR3_BAOEMODE_SHIFT
8626 #undef DDR_PHY_ACIOCR3_BAOEMODE_MASK
8627 #define DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL 0x00000005
8628 #define DDR_PHY_ACIOCR3_BAOEMODE_SHIFT 22
8629 #define DDR_PHY_ACIOCR3_BAOEMODE_MASK 0x03C00000U
8631 /*SDRAM A[17] Output Enable (OE) Mode Selection*/
8632 #undef DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL
8633 #undef DDR_PHY_ACIOCR3_A17OEMODE_SHIFT
8634 #undef DDR_PHY_ACIOCR3_A17OEMODE_MASK
8635 #define DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL 0x00000005
8636 #define DDR_PHY_ACIOCR3_A17OEMODE_SHIFT 20
8637 #define DDR_PHY_ACIOCR3_A17OEMODE_MASK 0x00300000U
8639 /*SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection*/
8640 #undef DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL
8641 #undef DDR_PHY_ACIOCR3_A16OEMODE_SHIFT
8642 #undef DDR_PHY_ACIOCR3_A16OEMODE_MASK
8643 #define DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL 0x00000005
8644 #define DDR_PHY_ACIOCR3_A16OEMODE_SHIFT 18
8645 #define DDR_PHY_ACIOCR3_A16OEMODE_MASK 0x000C0000U
8647 /*SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)*/
8648 #undef DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL
8649 #undef DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT
8650 #undef DDR_PHY_ACIOCR3_ACTOEMODE_MASK
8651 #define DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL 0x00000005
8652 #define DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT 16
8653 #define DDR_PHY_ACIOCR3_ACTOEMODE_MASK 0x00030000U
8655 /*Reserved. Return zeroes on reads.*/
8656 #undef DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL
8657 #undef DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT
8658 #undef DDR_PHY_ACIOCR3_RESERVED_15_8_MASK
8659 #define DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL 0x00000005
8660 #define DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT 8
8661 #define DDR_PHY_ACIOCR3_RESERVED_15_8_MASK 0x0000FF00U
8663 /*Reserved. Return zeros on reads.*/
8664 #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL
8665 #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT
8666 #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK
8667 #define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL 0x00000005
8668 #define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT 4
8669 #define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK 0x000000F0U
8671 /*SDRAM CK Output Enable (OE) Mode Selection.*/
8672 #undef DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL
8673 #undef DDR_PHY_ACIOCR3_CKOEMODE_SHIFT
8674 #undef DDR_PHY_ACIOCR3_CKOEMODE_MASK
8675 #define DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL 0x00000005
8676 #define DDR_PHY_ACIOCR3_CKOEMODE_SHIFT 0
8677 #define DDR_PHY_ACIOCR3_CKOEMODE_MASK 0x0000000FU
8679 /*Clock gating for AC LB slices and loopback read valid slices*/
8680 #undef DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL
8681 #undef DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT
8682 #undef DDR_PHY_ACIOCR4_LBCLKGATE_MASK
8683 #define DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL 0x00000000
8684 #define DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT 31
8685 #define DDR_PHY_ACIOCR4_LBCLKGATE_MASK 0x80000000U
8687 /*Clock gating for Output Enable D slices [1]*/
8688 #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL
8689 #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT
8690 #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK
8691 #define DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL 0x00000000
8692 #define DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT 30
8693 #define DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK 0x40000000U
8695 /*Clock gating for Power Down Receiver D slices [1]*/
8696 #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL
8697 #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT
8698 #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK
8699 #define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL 0x00000000
8700 #define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT 29
8701 #define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK 0x20000000U
8703 /*Clock gating for Termination Enable D slices [1]*/
8704 #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL
8705 #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT
8706 #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK
8707 #define DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL 0x00000000
8708 #define DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT 28
8709 #define DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK 0x10000000U
8711 /*Clock gating for CK# D slices [3:2]*/
8712 #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL
8713 #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT
8714 #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK
8715 #define DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL 0x00000000
8716 #define DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT 26
8717 #define DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK 0x0C000000U
8719 /*Clock gating for CK D slices [3:2]*/
8720 #undef DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL
8721 #undef DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT
8722 #undef DDR_PHY_ACIOCR4_CKCLKGATE1_MASK
8723 #define DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL 0x00000000
8724 #define DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT 24
8725 #define DDR_PHY_ACIOCR4_CKCLKGATE1_MASK 0x03000000U
8727 /*Clock gating for AC D slices [47:24]*/
8728 #undef DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL
8729 #undef DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT
8730 #undef DDR_PHY_ACIOCR4_ACCLKGATE1_MASK
8731 #define DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL 0x00000000
8732 #define DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT 0
8733 #define DDR_PHY_ACIOCR4_ACCLKGATE1_MASK 0x00FFFFFFU
8735 /*Reserved. Return zeroes on reads.*/
8736 #undef DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL
8737 #undef DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT
8738 #undef DDR_PHY_IOVCR0_RESERVED_31_29_MASK
8739 #define DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL 0x0F000000
8740 #define DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT 29
8741 #define DDR_PHY_IOVCR0_RESERVED_31_29_MASK 0xE0000000U
8743 /*Address/command lane VREF Pad Enable*/
8744 #undef DDR_PHY_IOVCR0_ACREFPEN_DEFVAL
8745 #undef DDR_PHY_IOVCR0_ACREFPEN_SHIFT
8746 #undef DDR_PHY_IOVCR0_ACREFPEN_MASK
8747 #define DDR_PHY_IOVCR0_ACREFPEN_DEFVAL 0x0F000000
8748 #define DDR_PHY_IOVCR0_ACREFPEN_SHIFT 28
8749 #define DDR_PHY_IOVCR0_ACREFPEN_MASK 0x10000000U
8751 /*Address/command lane Internal VREF Enable*/
8752 #undef DDR_PHY_IOVCR0_ACREFEEN_DEFVAL
8753 #undef DDR_PHY_IOVCR0_ACREFEEN_SHIFT
8754 #undef DDR_PHY_IOVCR0_ACREFEEN_MASK
8755 #define DDR_PHY_IOVCR0_ACREFEEN_DEFVAL 0x0F000000
8756 #define DDR_PHY_IOVCR0_ACREFEEN_SHIFT 26
8757 #define DDR_PHY_IOVCR0_ACREFEEN_MASK 0x0C000000U
8759 /*Address/command lane Single-End VREF Enable*/
8760 #undef DDR_PHY_IOVCR0_ACREFSEN_DEFVAL
8761 #undef DDR_PHY_IOVCR0_ACREFSEN_SHIFT
8762 #undef DDR_PHY_IOVCR0_ACREFSEN_MASK
8763 #define DDR_PHY_IOVCR0_ACREFSEN_DEFVAL 0x0F000000
8764 #define DDR_PHY_IOVCR0_ACREFSEN_SHIFT 25
8765 #define DDR_PHY_IOVCR0_ACREFSEN_MASK 0x02000000U
8767 /*Address/command lane Internal VREF Enable*/
8768 #undef DDR_PHY_IOVCR0_ACREFIEN_DEFVAL
8769 #undef DDR_PHY_IOVCR0_ACREFIEN_SHIFT
8770 #undef DDR_PHY_IOVCR0_ACREFIEN_MASK
8771 #define DDR_PHY_IOVCR0_ACREFIEN_DEFVAL 0x0F000000
8772 #define DDR_PHY_IOVCR0_ACREFIEN_SHIFT 24
8773 #define DDR_PHY_IOVCR0_ACREFIEN_MASK 0x01000000U
8775 /*External VREF generato REFSEL range select*/
8776 #undef DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL
8777 #undef DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT
8778 #undef DDR_PHY_IOVCR0_ACREFESELRANGE_MASK
8779 #define DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL 0x0F000000
8780 #define DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT 23
8781 #define DDR_PHY_IOVCR0_ACREFESELRANGE_MASK 0x00800000U
8783 /*Address/command lane External VREF Select*/
8784 #undef DDR_PHY_IOVCR0_ACREFESEL_DEFVAL
8785 #undef DDR_PHY_IOVCR0_ACREFESEL_SHIFT
8786 #undef DDR_PHY_IOVCR0_ACREFESEL_MASK
8787 #define DDR_PHY_IOVCR0_ACREFESEL_DEFVAL 0x0F000000
8788 #define DDR_PHY_IOVCR0_ACREFESEL_SHIFT 16
8789 #define DDR_PHY_IOVCR0_ACREFESEL_MASK 0x007F0000U
8791 /*Single ended VREF generator REFSEL range select*/
8792 #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL
8793 #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT
8794 #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK
8795 #define DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL 0x0F000000
8796 #define DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT 15
8797 #define DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK 0x00008000U
8799 /*Address/command lane Single-End VREF Select*/
8800 #undef DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL
8801 #undef DDR_PHY_IOVCR0_ACREFSSEL_SHIFT
8802 #undef DDR_PHY_IOVCR0_ACREFSSEL_MASK
8803 #define DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL 0x0F000000
8804 #define DDR_PHY_IOVCR0_ACREFSSEL_SHIFT 8
8805 #define DDR_PHY_IOVCR0_ACREFSSEL_MASK 0x00007F00U
8807 /*Internal VREF generator REFSEL ragne select*/
8808 #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL
8809 #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT
8810 #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK
8811 #define DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL 0x0F000000
8812 #define DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT 7
8813 #define DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK 0x00000080U
8815 /*REFSEL Control for internal AC IOs*/
8816 #undef DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL
8817 #undef DDR_PHY_IOVCR0_ACVREFISEL_SHIFT
8818 #undef DDR_PHY_IOVCR0_ACVREFISEL_MASK
8819 #define DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL 0x0F000000
8820 #define DDR_PHY_IOVCR0_ACVREFISEL_SHIFT 0
8821 #define DDR_PHY_IOVCR0_ACVREFISEL_MASK 0x0000007FU
8823 /*Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training*/
8824 #undef DDR_PHY_VTCR0_TVREF_DEFVAL
8825 #undef DDR_PHY_VTCR0_TVREF_SHIFT
8826 #undef DDR_PHY_VTCR0_TVREF_MASK
8827 #define DDR_PHY_VTCR0_TVREF_DEFVAL 0x70032019
8828 #define DDR_PHY_VTCR0_TVREF_SHIFT 29
8829 #define DDR_PHY_VTCR0_TVREF_MASK 0xE0000000U
8831 /*DRM DQ VREF training Enable*/
8832 #undef DDR_PHY_VTCR0_DVEN_DEFVAL
8833 #undef DDR_PHY_VTCR0_DVEN_SHIFT
8834 #undef DDR_PHY_VTCR0_DVEN_MASK
8835 #define DDR_PHY_VTCR0_DVEN_DEFVAL 0x70032019
8836 #define DDR_PHY_VTCR0_DVEN_SHIFT 28
8837 #define DDR_PHY_VTCR0_DVEN_MASK 0x10000000U
8839 /*Per Device Addressability Enable*/
8840 #undef DDR_PHY_VTCR0_PDAEN_DEFVAL
8841 #undef DDR_PHY_VTCR0_PDAEN_SHIFT
8842 #undef DDR_PHY_VTCR0_PDAEN_MASK
8843 #define DDR_PHY_VTCR0_PDAEN_DEFVAL 0x70032019
8844 #define DDR_PHY_VTCR0_PDAEN_SHIFT 27
8845 #define DDR_PHY_VTCR0_PDAEN_MASK 0x08000000U
8847 /*Reserved. Returns zeroes on reads.*/
8848 #undef DDR_PHY_VTCR0_RESERVED_26_DEFVAL
8849 #undef DDR_PHY_VTCR0_RESERVED_26_SHIFT
8850 #undef DDR_PHY_VTCR0_RESERVED_26_MASK
8851 #define DDR_PHY_VTCR0_RESERVED_26_DEFVAL 0x70032019
8852 #define DDR_PHY_VTCR0_RESERVED_26_SHIFT 26
8853 #define DDR_PHY_VTCR0_RESERVED_26_MASK 0x04000000U
8856 #undef DDR_PHY_VTCR0_VWCR_DEFVAL
8857 #undef DDR_PHY_VTCR0_VWCR_SHIFT
8858 #undef DDR_PHY_VTCR0_VWCR_MASK
8859 #define DDR_PHY_VTCR0_VWCR_DEFVAL 0x70032019
8860 #define DDR_PHY_VTCR0_VWCR_SHIFT 22
8861 #define DDR_PHY_VTCR0_VWCR_MASK 0x03C00000U
8863 /*DRAM DQ VREF step size used during DRAM VREF training*/
8864 #undef DDR_PHY_VTCR0_DVSS_DEFVAL
8865 #undef DDR_PHY_VTCR0_DVSS_SHIFT
8866 #undef DDR_PHY_VTCR0_DVSS_MASK
8867 #define DDR_PHY_VTCR0_DVSS_DEFVAL 0x70032019
8868 #define DDR_PHY_VTCR0_DVSS_SHIFT 18
8869 #define DDR_PHY_VTCR0_DVSS_MASK 0x003C0000U
8871 /*Maximum VREF limit value used during DRAM VREF training*/
8872 #undef DDR_PHY_VTCR0_DVMAX_DEFVAL
8873 #undef DDR_PHY_VTCR0_DVMAX_SHIFT
8874 #undef DDR_PHY_VTCR0_DVMAX_MASK
8875 #define DDR_PHY_VTCR0_DVMAX_DEFVAL 0x70032019
8876 #define DDR_PHY_VTCR0_DVMAX_SHIFT 12
8877 #define DDR_PHY_VTCR0_DVMAX_MASK 0x0003F000U
8879 /*Minimum VREF limit value used during DRAM VREF training*/
8880 #undef DDR_PHY_VTCR0_DVMIN_DEFVAL
8881 #undef DDR_PHY_VTCR0_DVMIN_SHIFT
8882 #undef DDR_PHY_VTCR0_DVMIN_MASK
8883 #define DDR_PHY_VTCR0_DVMIN_DEFVAL 0x70032019
8884 #define DDR_PHY_VTCR0_DVMIN_SHIFT 6
8885 #define DDR_PHY_VTCR0_DVMIN_MASK 0x00000FC0U
8887 /*Initial DRAM DQ VREF value used during DRAM VREF training*/
8888 #undef DDR_PHY_VTCR0_DVINIT_DEFVAL
8889 #undef DDR_PHY_VTCR0_DVINIT_SHIFT
8890 #undef DDR_PHY_VTCR0_DVINIT_MASK
8891 #define DDR_PHY_VTCR0_DVINIT_DEFVAL 0x70032019
8892 #define DDR_PHY_VTCR0_DVINIT_SHIFT 0
8893 #define DDR_PHY_VTCR0_DVINIT_MASK 0x0000003FU
8895 /*Host VREF step size used during VREF training. The register value of N indicates step size of (N+1)*/
8896 #undef DDR_PHY_VTCR1_HVSS_DEFVAL
8897 #undef DDR_PHY_VTCR1_HVSS_SHIFT
8898 #undef DDR_PHY_VTCR1_HVSS_MASK
8899 #define DDR_PHY_VTCR1_HVSS_DEFVAL 0x07F00072
8900 #define DDR_PHY_VTCR1_HVSS_SHIFT 28
8901 #define DDR_PHY_VTCR1_HVSS_MASK 0xF0000000U
8903 /*Reserved. Returns zeroes on reads.*/
8904 #undef DDR_PHY_VTCR1_RESERVED_27_DEFVAL
8905 #undef DDR_PHY_VTCR1_RESERVED_27_SHIFT
8906 #undef DDR_PHY_VTCR1_RESERVED_27_MASK
8907 #define DDR_PHY_VTCR1_RESERVED_27_DEFVAL 0x07F00072
8908 #define DDR_PHY_VTCR1_RESERVED_27_SHIFT 27
8909 #define DDR_PHY_VTCR1_RESERVED_27_MASK 0x08000000U
8911 /*Maximum VREF limit value used during DRAM VREF training.*/
8912 #undef DDR_PHY_VTCR1_HVMAX_DEFVAL
8913 #undef DDR_PHY_VTCR1_HVMAX_SHIFT
8914 #undef DDR_PHY_VTCR1_HVMAX_MASK
8915 #define DDR_PHY_VTCR1_HVMAX_DEFVAL 0x07F00072
8916 #define DDR_PHY_VTCR1_HVMAX_SHIFT 20
8917 #define DDR_PHY_VTCR1_HVMAX_MASK 0x07F00000U
8919 /*Reserved. Returns zeroes on reads.*/
8920 #undef DDR_PHY_VTCR1_RESERVED_19_DEFVAL
8921 #undef DDR_PHY_VTCR1_RESERVED_19_SHIFT
8922 #undef DDR_PHY_VTCR1_RESERVED_19_MASK
8923 #define DDR_PHY_VTCR1_RESERVED_19_DEFVAL 0x07F00072
8924 #define DDR_PHY_VTCR1_RESERVED_19_SHIFT 19
8925 #define DDR_PHY_VTCR1_RESERVED_19_MASK 0x00080000U
8927 /*Minimum VREF limit value used during DRAM VREF training.*/
8928 #undef DDR_PHY_VTCR1_HVMIN_DEFVAL
8929 #undef DDR_PHY_VTCR1_HVMIN_SHIFT
8930 #undef DDR_PHY_VTCR1_HVMIN_MASK
8931 #define DDR_PHY_VTCR1_HVMIN_DEFVAL 0x07F00072
8932 #define DDR_PHY_VTCR1_HVMIN_SHIFT 12
8933 #define DDR_PHY_VTCR1_HVMIN_MASK 0x0007F000U
8935 /*Reserved. Returns zeroes on reads.*/
8936 #undef DDR_PHY_VTCR1_RESERVED_11_DEFVAL
8937 #undef DDR_PHY_VTCR1_RESERVED_11_SHIFT
8938 #undef DDR_PHY_VTCR1_RESERVED_11_MASK
8939 #define DDR_PHY_VTCR1_RESERVED_11_DEFVAL 0x07F00072
8940 #define DDR_PHY_VTCR1_RESERVED_11_SHIFT 11
8941 #define DDR_PHY_VTCR1_RESERVED_11_MASK 0x00000800U
8943 /*Static Host Vref Rank Value*/
8944 #undef DDR_PHY_VTCR1_SHRNK_DEFVAL
8945 #undef DDR_PHY_VTCR1_SHRNK_SHIFT
8946 #undef DDR_PHY_VTCR1_SHRNK_MASK
8947 #define DDR_PHY_VTCR1_SHRNK_DEFVAL 0x07F00072
8948 #define DDR_PHY_VTCR1_SHRNK_SHIFT 9
8949 #define DDR_PHY_VTCR1_SHRNK_MASK 0x00000600U
8951 /*Static Host Vref Rank Enable*/
8952 #undef DDR_PHY_VTCR1_SHREN_DEFVAL
8953 #undef DDR_PHY_VTCR1_SHREN_SHIFT
8954 #undef DDR_PHY_VTCR1_SHREN_MASK
8955 #define DDR_PHY_VTCR1_SHREN_DEFVAL 0x07F00072
8956 #define DDR_PHY_VTCR1_SHREN_SHIFT 8
8957 #define DDR_PHY_VTCR1_SHREN_MASK 0x00000100U
8959 /*Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training*/
8960 #undef DDR_PHY_VTCR1_TVREFIO_DEFVAL
8961 #undef DDR_PHY_VTCR1_TVREFIO_SHIFT
8962 #undef DDR_PHY_VTCR1_TVREFIO_MASK
8963 #define DDR_PHY_VTCR1_TVREFIO_DEFVAL 0x07F00072
8964 #define DDR_PHY_VTCR1_TVREFIO_SHIFT 5
8965 #define DDR_PHY_VTCR1_TVREFIO_MASK 0x000000E0U
8967 /*Eye LCDL Offset value for VREF training*/
8968 #undef DDR_PHY_VTCR1_EOFF_DEFVAL
8969 #undef DDR_PHY_VTCR1_EOFF_SHIFT
8970 #undef DDR_PHY_VTCR1_EOFF_MASK
8971 #define DDR_PHY_VTCR1_EOFF_DEFVAL 0x07F00072
8972 #define DDR_PHY_VTCR1_EOFF_SHIFT 3
8973 #define DDR_PHY_VTCR1_EOFF_MASK 0x00000018U
8975 /*Number of LCDL Eye points for which VREF training is repeated*/
8976 #undef DDR_PHY_VTCR1_ENUM_DEFVAL
8977 #undef DDR_PHY_VTCR1_ENUM_SHIFT
8978 #undef DDR_PHY_VTCR1_ENUM_MASK
8979 #define DDR_PHY_VTCR1_ENUM_DEFVAL 0x07F00072
8980 #define DDR_PHY_VTCR1_ENUM_SHIFT 2
8981 #define DDR_PHY_VTCR1_ENUM_MASK 0x00000004U
8983 /*HOST (IO) internal VREF training Enable*/
8984 #undef DDR_PHY_VTCR1_HVEN_DEFVAL
8985 #undef DDR_PHY_VTCR1_HVEN_SHIFT
8986 #undef DDR_PHY_VTCR1_HVEN_MASK
8987 #define DDR_PHY_VTCR1_HVEN_DEFVAL 0x07F00072
8988 #define DDR_PHY_VTCR1_HVEN_SHIFT 1
8989 #define DDR_PHY_VTCR1_HVEN_MASK 0x00000002U
8991 /*Host IO Type Control*/
8992 #undef DDR_PHY_VTCR1_HVIO_DEFVAL
8993 #undef DDR_PHY_VTCR1_HVIO_SHIFT
8994 #undef DDR_PHY_VTCR1_HVIO_MASK
8995 #define DDR_PHY_VTCR1_HVIO_DEFVAL 0x07F00072
8996 #define DDR_PHY_VTCR1_HVIO_SHIFT 0
8997 #define DDR_PHY_VTCR1_HVIO_MASK 0x00000001U
8999 /*Reserved. Return zeroes on reads.*/
9000 #undef DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL
9001 #undef DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT
9002 #undef DDR_PHY_ACBDLR1_RESERVED_31_30_MASK
9003 #define DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL 0x00000000
9004 #define DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT 30
9005 #define DDR_PHY_ACBDLR1_RESERVED_31_30_MASK 0xC0000000U
9007 /*Delay select for the BDL on Parity.*/
9008 #undef DDR_PHY_ACBDLR1_PARBD_DEFVAL
9009 #undef DDR_PHY_ACBDLR1_PARBD_SHIFT
9010 #undef DDR_PHY_ACBDLR1_PARBD_MASK
9011 #define DDR_PHY_ACBDLR1_PARBD_DEFVAL 0x00000000
9012 #define DDR_PHY_ACBDLR1_PARBD_SHIFT 24
9013 #define DDR_PHY_ACBDLR1_PARBD_MASK 0x3F000000U
9015 /*Reserved. Return zeroes on reads.*/
9016 #undef DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL
9017 #undef DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT
9018 #undef DDR_PHY_ACBDLR1_RESERVED_23_22_MASK
9019 #define DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL 0x00000000
9020 #define DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT 22
9021 #define DDR_PHY_ACBDLR1_RESERVED_23_22_MASK 0x00C00000U
9023 /*Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE.*/
9024 #undef DDR_PHY_ACBDLR1_A16BD_DEFVAL
9025 #undef DDR_PHY_ACBDLR1_A16BD_SHIFT
9026 #undef DDR_PHY_ACBDLR1_A16BD_MASK
9027 #define DDR_PHY_ACBDLR1_A16BD_DEFVAL 0x00000000
9028 #define DDR_PHY_ACBDLR1_A16BD_SHIFT 16
9029 #define DDR_PHY_ACBDLR1_A16BD_MASK 0x003F0000U
9031 /*Reserved. Return zeroes on reads.*/
9032 #undef DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL
9033 #undef DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT
9034 #undef DDR_PHY_ACBDLR1_RESERVED_15_14_MASK
9035 #define DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL 0x00000000
9036 #define DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT 14
9037 #define DDR_PHY_ACBDLR1_RESERVED_15_14_MASK 0x0000C000U
9039 /*Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS.*/
9040 #undef DDR_PHY_ACBDLR1_A17BD_DEFVAL
9041 #undef DDR_PHY_ACBDLR1_A17BD_SHIFT
9042 #undef DDR_PHY_ACBDLR1_A17BD_MASK
9043 #define DDR_PHY_ACBDLR1_A17BD_DEFVAL 0x00000000
9044 #define DDR_PHY_ACBDLR1_A17BD_SHIFT 8
9045 #define DDR_PHY_ACBDLR1_A17BD_MASK 0x00003F00U
9047 /*Reserved. Return zeroes on reads.*/
9048 #undef DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL
9049 #undef DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT
9050 #undef DDR_PHY_ACBDLR1_RESERVED_7_6_MASK
9051 #define DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL 0x00000000
9052 #define DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT 6
9053 #define DDR_PHY_ACBDLR1_RESERVED_7_6_MASK 0x000000C0U
9055 /*Delay select for the BDL on ACTN.*/
9056 #undef DDR_PHY_ACBDLR1_ACTBD_DEFVAL
9057 #undef DDR_PHY_ACBDLR1_ACTBD_SHIFT
9058 #undef DDR_PHY_ACBDLR1_ACTBD_MASK
9059 #define DDR_PHY_ACBDLR1_ACTBD_DEFVAL 0x00000000
9060 #define DDR_PHY_ACBDLR1_ACTBD_SHIFT 0
9061 #define DDR_PHY_ACBDLR1_ACTBD_MASK 0x0000003FU
9063 /*Reserved. Return zeroes on reads.*/
9064 #undef DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL
9065 #undef DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT
9066 #undef DDR_PHY_ACBDLR2_RESERVED_31_30_MASK
9067 #define DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL 0x00000000
9068 #define DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT 30
9069 #define DDR_PHY_ACBDLR2_RESERVED_31_30_MASK 0xC0000000U
9071 /*Delay select for the BDL on BG[1].*/
9072 #undef DDR_PHY_ACBDLR2_BG1BD_DEFVAL
9073 #undef DDR_PHY_ACBDLR2_BG1BD_SHIFT
9074 #undef DDR_PHY_ACBDLR2_BG1BD_MASK
9075 #define DDR_PHY_ACBDLR2_BG1BD_DEFVAL 0x00000000
9076 #define DDR_PHY_ACBDLR2_BG1BD_SHIFT 24
9077 #define DDR_PHY_ACBDLR2_BG1BD_MASK 0x3F000000U
9079 /*Reserved. Return zeroes on reads.*/
9080 #undef DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL
9081 #undef DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT
9082 #undef DDR_PHY_ACBDLR2_RESERVED_23_22_MASK
9083 #define DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL 0x00000000
9084 #define DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT 22
9085 #define DDR_PHY_ACBDLR2_RESERVED_23_22_MASK 0x00C00000U
9087 /*Delay select for the BDL on BG[0].*/
9088 #undef DDR_PHY_ACBDLR2_BG0BD_DEFVAL
9089 #undef DDR_PHY_ACBDLR2_BG0BD_SHIFT
9090 #undef DDR_PHY_ACBDLR2_BG0BD_MASK
9091 #define DDR_PHY_ACBDLR2_BG0BD_DEFVAL 0x00000000
9092 #define DDR_PHY_ACBDLR2_BG0BD_SHIFT 16
9093 #define DDR_PHY_ACBDLR2_BG0BD_MASK 0x003F0000U
9095 /*Reser.ved Return zeroes on reads.*/
9096 #undef DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL
9097 #undef DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT
9098 #undef DDR_PHY_ACBDLR2_RESERVED_15_14_MASK
9099 #define DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL 0x00000000
9100 #define DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT 14
9101 #define DDR_PHY_ACBDLR2_RESERVED_15_14_MASK 0x0000C000U
9103 /*Delay select for the BDL on BA[1].*/
9104 #undef DDR_PHY_ACBDLR2_BA1BD_DEFVAL
9105 #undef DDR_PHY_ACBDLR2_BA1BD_SHIFT
9106 #undef DDR_PHY_ACBDLR2_BA1BD_MASK
9107 #define DDR_PHY_ACBDLR2_BA1BD_DEFVAL 0x00000000
9108 #define DDR_PHY_ACBDLR2_BA1BD_SHIFT 8
9109 #define DDR_PHY_ACBDLR2_BA1BD_MASK 0x00003F00U
9111 /*Reserved. Return zeroes on reads.*/
9112 #undef DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL
9113 #undef DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT
9114 #undef DDR_PHY_ACBDLR2_RESERVED_7_6_MASK
9115 #define DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL 0x00000000
9116 #define DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT 6
9117 #define DDR_PHY_ACBDLR2_RESERVED_7_6_MASK 0x000000C0U
9119 /*Delay select for the BDL on BA[0].*/
9120 #undef DDR_PHY_ACBDLR2_BA0BD_DEFVAL
9121 #undef DDR_PHY_ACBDLR2_BA0BD_SHIFT
9122 #undef DDR_PHY_ACBDLR2_BA0BD_MASK
9123 #define DDR_PHY_ACBDLR2_BA0BD_DEFVAL 0x00000000
9124 #define DDR_PHY_ACBDLR2_BA0BD_SHIFT 0
9125 #define DDR_PHY_ACBDLR2_BA0BD_MASK 0x0000003FU
9127 /*Reserved. Return zeroes on reads.*/
9128 #undef DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL
9129 #undef DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT
9130 #undef DDR_PHY_ACBDLR6_RESERVED_31_30_MASK
9131 #define DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL 0x00000000
9132 #define DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT 30
9133 #define DDR_PHY_ACBDLR6_RESERVED_31_30_MASK 0xC0000000U
9135 /*Delay select for the BDL on Address A[3].*/
9136 #undef DDR_PHY_ACBDLR6_A03BD_DEFVAL
9137 #undef DDR_PHY_ACBDLR6_A03BD_SHIFT
9138 #undef DDR_PHY_ACBDLR6_A03BD_MASK
9139 #define DDR_PHY_ACBDLR6_A03BD_DEFVAL 0x00000000
9140 #define DDR_PHY_ACBDLR6_A03BD_SHIFT 24
9141 #define DDR_PHY_ACBDLR6_A03BD_MASK 0x3F000000U
9143 /*Reserved. Return zeroes on reads.*/
9144 #undef DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL
9145 #undef DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT
9146 #undef DDR_PHY_ACBDLR6_RESERVED_23_22_MASK
9147 #define DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL 0x00000000
9148 #define DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT 22
9149 #define DDR_PHY_ACBDLR6_RESERVED_23_22_MASK 0x00C00000U
9151 /*Delay select for the BDL on Address A[2].*/
9152 #undef DDR_PHY_ACBDLR6_A02BD_DEFVAL
9153 #undef DDR_PHY_ACBDLR6_A02BD_SHIFT
9154 #undef DDR_PHY_ACBDLR6_A02BD_MASK
9155 #define DDR_PHY_ACBDLR6_A02BD_DEFVAL 0x00000000
9156 #define DDR_PHY_ACBDLR6_A02BD_SHIFT 16
9157 #define DDR_PHY_ACBDLR6_A02BD_MASK 0x003F0000U
9159 /*Reserved. Return zeroes on reads.*/
9160 #undef DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL
9161 #undef DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT
9162 #undef DDR_PHY_ACBDLR6_RESERVED_15_14_MASK
9163 #define DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL 0x00000000
9164 #define DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT 14
9165 #define DDR_PHY_ACBDLR6_RESERVED_15_14_MASK 0x0000C000U
9167 /*Delay select for the BDL on Address A[1].*/
9168 #undef DDR_PHY_ACBDLR6_A01BD_DEFVAL
9169 #undef DDR_PHY_ACBDLR6_A01BD_SHIFT
9170 #undef DDR_PHY_ACBDLR6_A01BD_MASK
9171 #define DDR_PHY_ACBDLR6_A01BD_DEFVAL 0x00000000
9172 #define DDR_PHY_ACBDLR6_A01BD_SHIFT 8
9173 #define DDR_PHY_ACBDLR6_A01BD_MASK 0x00003F00U
9175 /*Reserved. Return zeroes on reads.*/
9176 #undef DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL
9177 #undef DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT
9178 #undef DDR_PHY_ACBDLR6_RESERVED_7_6_MASK
9179 #define DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL 0x00000000
9180 #define DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT 6
9181 #define DDR_PHY_ACBDLR6_RESERVED_7_6_MASK 0x000000C0U
9183 /*Delay select for the BDL on Address A[0].*/
9184 #undef DDR_PHY_ACBDLR6_A00BD_DEFVAL
9185 #undef DDR_PHY_ACBDLR6_A00BD_SHIFT
9186 #undef DDR_PHY_ACBDLR6_A00BD_MASK
9187 #define DDR_PHY_ACBDLR6_A00BD_DEFVAL 0x00000000
9188 #define DDR_PHY_ACBDLR6_A00BD_SHIFT 0
9189 #define DDR_PHY_ACBDLR6_A00BD_MASK 0x0000003FU
9191 /*Reserved. Return zeroes on reads.*/
9192 #undef DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL
9193 #undef DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT
9194 #undef DDR_PHY_ACBDLR7_RESERVED_31_30_MASK
9195 #define DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL 0x00000000
9196 #define DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT 30
9197 #define DDR_PHY_ACBDLR7_RESERVED_31_30_MASK 0xC0000000U
9199 /*Delay select for the BDL on Address A[7].*/
9200 #undef DDR_PHY_ACBDLR7_A07BD_DEFVAL
9201 #undef DDR_PHY_ACBDLR7_A07BD_SHIFT
9202 #undef DDR_PHY_ACBDLR7_A07BD_MASK
9203 #define DDR_PHY_ACBDLR7_A07BD_DEFVAL 0x00000000
9204 #define DDR_PHY_ACBDLR7_A07BD_SHIFT 24
9205 #define DDR_PHY_ACBDLR7_A07BD_MASK 0x3F000000U
9207 /*Reserved. Return zeroes on reads.*/
9208 #undef DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL
9209 #undef DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT
9210 #undef DDR_PHY_ACBDLR7_RESERVED_23_22_MASK
9211 #define DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL 0x00000000
9212 #define DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT 22
9213 #define DDR_PHY_ACBDLR7_RESERVED_23_22_MASK 0x00C00000U
9215 /*Delay select for the BDL on Address A[6].*/
9216 #undef DDR_PHY_ACBDLR7_A06BD_DEFVAL
9217 #undef DDR_PHY_ACBDLR7_A06BD_SHIFT
9218 #undef DDR_PHY_ACBDLR7_A06BD_MASK
9219 #define DDR_PHY_ACBDLR7_A06BD_DEFVAL 0x00000000
9220 #define DDR_PHY_ACBDLR7_A06BD_SHIFT 16
9221 #define DDR_PHY_ACBDLR7_A06BD_MASK 0x003F0000U
9223 /*Reserved. Return zeroes on reads.*/
9224 #undef DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL
9225 #undef DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT
9226 #undef DDR_PHY_ACBDLR7_RESERVED_15_14_MASK
9227 #define DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL 0x00000000
9228 #define DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT 14
9229 #define DDR_PHY_ACBDLR7_RESERVED_15_14_MASK 0x0000C000U
9231 /*Delay select for the BDL on Address A[5].*/
9232 #undef DDR_PHY_ACBDLR7_A05BD_DEFVAL
9233 #undef DDR_PHY_ACBDLR7_A05BD_SHIFT
9234 #undef DDR_PHY_ACBDLR7_A05BD_MASK
9235 #define DDR_PHY_ACBDLR7_A05BD_DEFVAL 0x00000000
9236 #define DDR_PHY_ACBDLR7_A05BD_SHIFT 8
9237 #define DDR_PHY_ACBDLR7_A05BD_MASK 0x00003F00U
9239 /*Reserved. Return zeroes on reads.*/
9240 #undef DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL
9241 #undef DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT
9242 #undef DDR_PHY_ACBDLR7_RESERVED_7_6_MASK
9243 #define DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL 0x00000000
9244 #define DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT 6
9245 #define DDR_PHY_ACBDLR7_RESERVED_7_6_MASK 0x000000C0U
9247 /*Delay select for the BDL on Address A[4].*/
9248 #undef DDR_PHY_ACBDLR7_A04BD_DEFVAL
9249 #undef DDR_PHY_ACBDLR7_A04BD_SHIFT
9250 #undef DDR_PHY_ACBDLR7_A04BD_MASK
9251 #define DDR_PHY_ACBDLR7_A04BD_DEFVAL 0x00000000
9252 #define DDR_PHY_ACBDLR7_A04BD_SHIFT 0
9253 #define DDR_PHY_ACBDLR7_A04BD_MASK 0x0000003FU
9255 /*Reserved. Return zeroes on reads.*/
9256 #undef DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL
9257 #undef DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT
9258 #undef DDR_PHY_ACBDLR8_RESERVED_31_30_MASK
9259 #define DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL 0x00000000
9260 #define DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT 30
9261 #define DDR_PHY_ACBDLR8_RESERVED_31_30_MASK 0xC0000000U
9263 /*Delay select for the BDL on Address A[11].*/
9264 #undef DDR_PHY_ACBDLR8_A11BD_DEFVAL
9265 #undef DDR_PHY_ACBDLR8_A11BD_SHIFT
9266 #undef DDR_PHY_ACBDLR8_A11BD_MASK
9267 #define DDR_PHY_ACBDLR8_A11BD_DEFVAL 0x00000000
9268 #define DDR_PHY_ACBDLR8_A11BD_SHIFT 24
9269 #define DDR_PHY_ACBDLR8_A11BD_MASK 0x3F000000U
9271 /*Reserved. Return zeroes on reads.*/
9272 #undef DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL
9273 #undef DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT
9274 #undef DDR_PHY_ACBDLR8_RESERVED_23_22_MASK
9275 #define DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL 0x00000000
9276 #define DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT 22
9277 #define DDR_PHY_ACBDLR8_RESERVED_23_22_MASK 0x00C00000U
9279 /*Delay select for the BDL on Address A[10].*/
9280 #undef DDR_PHY_ACBDLR8_A10BD_DEFVAL
9281 #undef DDR_PHY_ACBDLR8_A10BD_SHIFT
9282 #undef DDR_PHY_ACBDLR8_A10BD_MASK
9283 #define DDR_PHY_ACBDLR8_A10BD_DEFVAL 0x00000000
9284 #define DDR_PHY_ACBDLR8_A10BD_SHIFT 16
9285 #define DDR_PHY_ACBDLR8_A10BD_MASK 0x003F0000U
9287 /*Reserved. Return zeroes on reads.*/
9288 #undef DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL
9289 #undef DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT
9290 #undef DDR_PHY_ACBDLR8_RESERVED_15_14_MASK
9291 #define DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL 0x00000000
9292 #define DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT 14
9293 #define DDR_PHY_ACBDLR8_RESERVED_15_14_MASK 0x0000C000U
9295 /*Delay select for the BDL on Address A[9].*/
9296 #undef DDR_PHY_ACBDLR8_A09BD_DEFVAL
9297 #undef DDR_PHY_ACBDLR8_A09BD_SHIFT
9298 #undef DDR_PHY_ACBDLR8_A09BD_MASK
9299 #define DDR_PHY_ACBDLR8_A09BD_DEFVAL 0x00000000
9300 #define DDR_PHY_ACBDLR8_A09BD_SHIFT 8
9301 #define DDR_PHY_ACBDLR8_A09BD_MASK 0x00003F00U
9303 /*Reserved. Return zeroes on reads.*/
9304 #undef DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL
9305 #undef DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT
9306 #undef DDR_PHY_ACBDLR8_RESERVED_7_6_MASK
9307 #define DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL 0x00000000
9308 #define DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT 6
9309 #define DDR_PHY_ACBDLR8_RESERVED_7_6_MASK 0x000000C0U
9311 /*Delay select for the BDL on Address A[8].*/
9312 #undef DDR_PHY_ACBDLR8_A08BD_DEFVAL
9313 #undef DDR_PHY_ACBDLR8_A08BD_SHIFT
9314 #undef DDR_PHY_ACBDLR8_A08BD_MASK
9315 #define DDR_PHY_ACBDLR8_A08BD_DEFVAL 0x00000000
9316 #define DDR_PHY_ACBDLR8_A08BD_SHIFT 0
9317 #define DDR_PHY_ACBDLR8_A08BD_MASK 0x0000003FU
9319 /*Reserved. Return zeroes on reads.*/
9320 #undef DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL
9321 #undef DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT
9322 #undef DDR_PHY_ACBDLR9_RESERVED_31_30_MASK
9323 #define DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL 0x00000000
9324 #define DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT 30
9325 #define DDR_PHY_ACBDLR9_RESERVED_31_30_MASK 0xC0000000U
9327 /*Delay select for the BDL on Address A[15].*/
9328 #undef DDR_PHY_ACBDLR9_A15BD_DEFVAL
9329 #undef DDR_PHY_ACBDLR9_A15BD_SHIFT
9330 #undef DDR_PHY_ACBDLR9_A15BD_MASK
9331 #define DDR_PHY_ACBDLR9_A15BD_DEFVAL 0x00000000
9332 #define DDR_PHY_ACBDLR9_A15BD_SHIFT 24
9333 #define DDR_PHY_ACBDLR9_A15BD_MASK 0x3F000000U
9335 /*Reserved. Return zeroes on reads.*/
9336 #undef DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL
9337 #undef DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT
9338 #undef DDR_PHY_ACBDLR9_RESERVED_23_22_MASK
9339 #define DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL 0x00000000
9340 #define DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT 22
9341 #define DDR_PHY_ACBDLR9_RESERVED_23_22_MASK 0x00C00000U
9343 /*Delay select for the BDL on Address A[14].*/
9344 #undef DDR_PHY_ACBDLR9_A14BD_DEFVAL
9345 #undef DDR_PHY_ACBDLR9_A14BD_SHIFT
9346 #undef DDR_PHY_ACBDLR9_A14BD_MASK
9347 #define DDR_PHY_ACBDLR9_A14BD_DEFVAL 0x00000000
9348 #define DDR_PHY_ACBDLR9_A14BD_SHIFT 16
9349 #define DDR_PHY_ACBDLR9_A14BD_MASK 0x003F0000U
9351 /*Reserved. Return zeroes on reads.*/
9352 #undef DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL
9353 #undef DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT
9354 #undef DDR_PHY_ACBDLR9_RESERVED_15_14_MASK
9355 #define DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL 0x00000000
9356 #define DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT 14
9357 #define DDR_PHY_ACBDLR9_RESERVED_15_14_MASK 0x0000C000U
9359 /*Delay select for the BDL on Address A[13].*/
9360 #undef DDR_PHY_ACBDLR9_A13BD_DEFVAL
9361 #undef DDR_PHY_ACBDLR9_A13BD_SHIFT
9362 #undef DDR_PHY_ACBDLR9_A13BD_MASK
9363 #define DDR_PHY_ACBDLR9_A13BD_DEFVAL 0x00000000
9364 #define DDR_PHY_ACBDLR9_A13BD_SHIFT 8
9365 #define DDR_PHY_ACBDLR9_A13BD_MASK 0x00003F00U
9367 /*Reserved. Return zeroes on reads.*/
9368 #undef DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL
9369 #undef DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT
9370 #undef DDR_PHY_ACBDLR9_RESERVED_7_6_MASK
9371 #define DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL 0x00000000
9372 #define DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT 6
9373 #define DDR_PHY_ACBDLR9_RESERVED_7_6_MASK 0x000000C0U
9375 /*Delay select for the BDL on Address A[12].*/
9376 #undef DDR_PHY_ACBDLR9_A12BD_DEFVAL
9377 #undef DDR_PHY_ACBDLR9_A12BD_SHIFT
9378 #undef DDR_PHY_ACBDLR9_A12BD_MASK
9379 #define DDR_PHY_ACBDLR9_A12BD_DEFVAL 0x00000000
9380 #define DDR_PHY_ACBDLR9_A12BD_SHIFT 0
9381 #define DDR_PHY_ACBDLR9_A12BD_MASK 0x0000003FU
9383 /*Reserved. Return zeroes on reads.*/
9384 #undef DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL
9385 #undef DDR_PHY_ZQCR_RESERVED_31_26_SHIFT
9386 #undef DDR_PHY_ZQCR_RESERVED_31_26_MASK
9387 #define DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL 0x008A2858
9388 #define DDR_PHY_ZQCR_RESERVED_31_26_SHIFT 26
9389 #define DDR_PHY_ZQCR_RESERVED_31_26_MASK 0xFC000000U
9392 #undef DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL
9393 #undef DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT
9394 #undef DDR_PHY_ZQCR_ZQREFISELRANGE_MASK
9395 #define DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL 0x008A2858
9396 #define DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT 25
9397 #define DDR_PHY_ZQCR_ZQREFISELRANGE_MASK 0x02000000U
9399 /*Programmable Wait for Frequency B*/
9400 #undef DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL
9401 #undef DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT
9402 #undef DDR_PHY_ZQCR_PGWAIT_FRQB_MASK
9403 #define DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL 0x008A2858
9404 #define DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT 19
9405 #define DDR_PHY_ZQCR_PGWAIT_FRQB_MASK 0x01F80000U
9407 /*Programmable Wait for Frequency A*/
9408 #undef DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL
9409 #undef DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT
9410 #undef DDR_PHY_ZQCR_PGWAIT_FRQA_MASK
9411 #define DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL 0x008A2858
9412 #define DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT 13
9413 #define DDR_PHY_ZQCR_PGWAIT_FRQA_MASK 0x0007E000U
9415 /*ZQ VREF Pad Enable*/
9416 #undef DDR_PHY_ZQCR_ZQREFPEN_DEFVAL
9417 #undef DDR_PHY_ZQCR_ZQREFPEN_SHIFT
9418 #undef DDR_PHY_ZQCR_ZQREFPEN_MASK
9419 #define DDR_PHY_ZQCR_ZQREFPEN_DEFVAL 0x008A2858
9420 #define DDR_PHY_ZQCR_ZQREFPEN_SHIFT 12
9421 #define DDR_PHY_ZQCR_ZQREFPEN_MASK 0x00001000U
9423 /*ZQ Internal VREF Enable*/
9424 #undef DDR_PHY_ZQCR_ZQREFIEN_DEFVAL
9425 #undef DDR_PHY_ZQCR_ZQREFIEN_SHIFT
9426 #undef DDR_PHY_ZQCR_ZQREFIEN_MASK
9427 #define DDR_PHY_ZQCR_ZQREFIEN_DEFVAL 0x008A2858
9428 #define DDR_PHY_ZQCR_ZQREFIEN_SHIFT 11
9429 #define DDR_PHY_ZQCR_ZQREFIEN_MASK 0x00000800U
9431 /*Choice of termination mode*/
9432 #undef DDR_PHY_ZQCR_ODT_MODE_DEFVAL
9433 #undef DDR_PHY_ZQCR_ODT_MODE_SHIFT
9434 #undef DDR_PHY_ZQCR_ODT_MODE_MASK
9435 #define DDR_PHY_ZQCR_ODT_MODE_DEFVAL 0x008A2858
9436 #define DDR_PHY_ZQCR_ODT_MODE_SHIFT 9
9437 #define DDR_PHY_ZQCR_ODT_MODE_MASK 0x00000600U
9439 /*Force ZCAL VT update*/
9440 #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL
9441 #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT
9442 #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK
9443 #define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL 0x008A2858
9444 #define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT 8
9445 #define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK 0x00000100U
9447 /*IO VT Drift Limit*/
9448 #undef DDR_PHY_ZQCR_IODLMT_DEFVAL
9449 #undef DDR_PHY_ZQCR_IODLMT_SHIFT
9450 #undef DDR_PHY_ZQCR_IODLMT_MASK
9451 #define DDR_PHY_ZQCR_IODLMT_DEFVAL 0x008A2858
9452 #define DDR_PHY_ZQCR_IODLMT_SHIFT 5
9453 #define DDR_PHY_ZQCR_IODLMT_MASK 0x000000E0U
9455 /*Averaging algorithm enable, if set, enables averaging algorithm*/
9456 #undef DDR_PHY_ZQCR_AVGEN_DEFVAL
9457 #undef DDR_PHY_ZQCR_AVGEN_SHIFT
9458 #undef DDR_PHY_ZQCR_AVGEN_MASK
9459 #define DDR_PHY_ZQCR_AVGEN_DEFVAL 0x008A2858
9460 #define DDR_PHY_ZQCR_AVGEN_SHIFT 4
9461 #define DDR_PHY_ZQCR_AVGEN_MASK 0x00000010U
9463 /*Maximum number of averaging rounds to be used by averaging algorithm*/
9464 #undef DDR_PHY_ZQCR_AVGMAX_DEFVAL
9465 #undef DDR_PHY_ZQCR_AVGMAX_SHIFT
9466 #undef DDR_PHY_ZQCR_AVGMAX_MASK
9467 #define DDR_PHY_ZQCR_AVGMAX_DEFVAL 0x008A2858
9468 #define DDR_PHY_ZQCR_AVGMAX_SHIFT 2
9469 #define DDR_PHY_ZQCR_AVGMAX_MASK 0x0000000CU
9471 /*ZQ Calibration Type*/
9472 #undef DDR_PHY_ZQCR_ZCALT_DEFVAL
9473 #undef DDR_PHY_ZQCR_ZCALT_SHIFT
9474 #undef DDR_PHY_ZQCR_ZCALT_MASK
9475 #define DDR_PHY_ZQCR_ZCALT_DEFVAL 0x008A2858
9476 #define DDR_PHY_ZQCR_ZCALT_SHIFT 1
9477 #define DDR_PHY_ZQCR_ZCALT_MASK 0x00000002U
9480 #undef DDR_PHY_ZQCR_ZQPD_DEFVAL
9481 #undef DDR_PHY_ZQCR_ZQPD_SHIFT
9482 #undef DDR_PHY_ZQCR_ZQPD_MASK
9483 #define DDR_PHY_ZQCR_ZQPD_DEFVAL 0x008A2858
9484 #define DDR_PHY_ZQCR_ZQPD_SHIFT 0
9485 #define DDR_PHY_ZQCR_ZQPD_MASK 0x00000001U
9487 /*Pull-down drive strength ZCTRL over-ride enable*/
9488 #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL
9489 #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT
9490 #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK
9491 #define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB
9492 #define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT 31
9493 #define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK 0x80000000U
9495 /*Pull-up drive strength ZCTRL over-ride enable*/
9496 #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL
9497 #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT
9498 #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK
9499 #define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB
9500 #define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT 30
9501 #define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK 0x40000000U
9503 /*Pull-down termination ZCTRL over-ride enable*/
9504 #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL
9505 #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT
9506 #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK
9507 #define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB
9508 #define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT 29
9509 #define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK 0x20000000U
9511 /*Pull-up termination ZCTRL over-ride enable*/
9512 #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL
9513 #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT
9514 #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK
9515 #define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB
9516 #define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT 28
9517 #define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK 0x10000000U
9519 /*Calibration segment bypass*/
9520 #undef DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL
9521 #undef DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT
9522 #undef DDR_PHY_ZQ0PR0_ZSEGBYP_MASK
9523 #define DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL 0x000077BB
9524 #define DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT 27
9525 #define DDR_PHY_ZQ0PR0_ZSEGBYP_MASK 0x08000000U
9527 /*VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB*/
9528 #undef DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL
9529 #undef DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT
9530 #undef DDR_PHY_ZQ0PR0_ZLE_MODE_MASK
9531 #define DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL 0x000077BB
9532 #define DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT 25
9533 #define DDR_PHY_ZQ0PR0_ZLE_MODE_MASK 0x06000000U
9535 /*Termination adjustment*/
9536 #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL
9537 #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT
9538 #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK
9539 #define DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL 0x000077BB
9540 #define DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT 22
9541 #define DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK 0x01C00000U
9543 /*Pulldown drive strength adjustment*/
9544 #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL
9545 #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT
9546 #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK
9547 #define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB
9548 #define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT 19
9549 #define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK 0x00380000U
9551 /*Pullup drive strength adjustment*/
9552 #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL
9553 #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT
9554 #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK
9555 #define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB
9556 #define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT 16
9557 #define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK 0x00070000U
9559 /*DRAM Impedance Divide Ratio*/
9560 #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL
9561 #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT
9562 #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK
9563 #define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB
9564 #define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT 12
9565 #define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U
9567 /*HOST Impedance Divide Ratio*/
9568 #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL
9569 #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT
9570 #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK
9571 #define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB
9572 #define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT 8
9573 #define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK 0x00000F00U
9575 /*Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)*/
9576 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL
9577 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT
9578 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK
9579 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB
9580 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT 4
9581 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U
9583 /*Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)*/
9584 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL
9585 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT
9586 #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK
9587 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB
9588 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT 0
9589 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU
9591 /*Reserved. Return zeros on reads.*/
9592 #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL
9593 #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT
9594 #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK
9595 #define DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL 0x00000000
9596 #define DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT 26
9597 #define DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK 0xFC000000U
9599 /*Override value for the pull-up output impedance*/
9600 #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL
9601 #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT
9602 #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK
9603 #define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL 0x00000000
9604 #define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT 16
9605 #define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK 0x03FF0000U
9607 /*Reserved. Return zeros on reads.*/
9608 #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL
9609 #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT
9610 #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK
9611 #define DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL 0x00000000
9612 #define DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT 10
9613 #define DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK 0x0000FC00U
9615 /*Override value for the pull-down output impedance*/
9616 #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL
9617 #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT
9618 #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK
9619 #define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL 0x00000000
9620 #define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT 0
9621 #define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK 0x000003FFU
9623 /*Reserved. Return zeros on reads.*/
9624 #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL
9625 #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT
9626 #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK
9627 #define DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL 0x00000000
9628 #define DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT 26
9629 #define DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK 0xFC000000U
9631 /*Override value for the pull-up termination*/
9632 #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL
9633 #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT
9634 #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK
9635 #define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL 0x00000000
9636 #define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT 16
9637 #define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK 0x03FF0000U
9639 /*Reserved. Return zeros on reads.*/
9640 #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL
9641 #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT
9642 #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK
9643 #define DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL 0x00000000
9644 #define DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT 10
9645 #define DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK 0x0000FC00U
9647 /*Override value for the pull-down termination*/
9648 #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL
9649 #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT
9650 #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK
9651 #define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL 0x00000000
9652 #define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT 0
9653 #define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK 0x000003FFU
9655 /*Pull-down drive strength ZCTRL over-ride enable*/
9656 #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL
9657 #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT
9658 #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK
9659 #define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB
9660 #define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT 31
9661 #define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK 0x80000000U
9663 /*Pull-up drive strength ZCTRL over-ride enable*/
9664 #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL
9665 #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT
9666 #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK
9667 #define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB
9668 #define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT 30
9669 #define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK 0x40000000U
9671 /*Pull-down termination ZCTRL over-ride enable*/
9672 #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL
9673 #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT
9674 #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK
9675 #define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB
9676 #define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT 29
9677 #define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK 0x20000000U
9679 /*Pull-up termination ZCTRL over-ride enable*/
9680 #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL
9681 #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT
9682 #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK
9683 #define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB
9684 #define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT 28
9685 #define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK 0x10000000U
9687 /*Calibration segment bypass*/
9688 #undef DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL
9689 #undef DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT
9690 #undef DDR_PHY_ZQ1PR0_ZSEGBYP_MASK
9691 #define DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL 0x000077BB
9692 #define DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT 27
9693 #define DDR_PHY_ZQ1PR0_ZSEGBYP_MASK 0x08000000U
9695 /*VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB*/
9696 #undef DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL
9697 #undef DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT
9698 #undef DDR_PHY_ZQ1PR0_ZLE_MODE_MASK
9699 #define DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL 0x000077BB
9700 #define DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT 25
9701 #define DDR_PHY_ZQ1PR0_ZLE_MODE_MASK 0x06000000U
9703 /*Termination adjustment*/
9704 #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL
9705 #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT
9706 #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK
9707 #define DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL 0x000077BB
9708 #define DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT 22
9709 #define DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK 0x01C00000U
9711 /*Pulldown drive strength adjustment*/
9712 #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL
9713 #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT
9714 #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK
9715 #define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB
9716 #define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT 19
9717 #define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK 0x00380000U
9719 /*Pullup drive strength adjustment*/
9720 #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL
9721 #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT
9722 #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK
9723 #define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB
9724 #define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT 16
9725 #define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK 0x00070000U
9727 /*DRAM Impedance Divide Ratio*/
9728 #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL
9729 #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT
9730 #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK
9731 #define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB
9732 #define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT 12
9733 #define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U
9735 /*HOST Impedance Divide Ratio*/
9736 #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL
9737 #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT
9738 #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK
9739 #define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB
9740 #define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT 8
9741 #define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK 0x00000F00U
9743 /*Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)*/
9744 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL
9745 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT
9746 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK
9747 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB
9748 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT 4
9749 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U
9751 /*Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)*/
9752 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL
9753 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT
9754 #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK
9755 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB
9756 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT 0
9757 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU
9759 /*Calibration Bypass*/
9760 #undef DDR_PHY_DX0GCR0_CALBYP_DEFVAL
9761 #undef DDR_PHY_DX0GCR0_CALBYP_SHIFT
9762 #undef DDR_PHY_DX0GCR0_CALBYP_MASK
9763 #define DDR_PHY_DX0GCR0_CALBYP_DEFVAL 0x40200204
9764 #define DDR_PHY_DX0GCR0_CALBYP_SHIFT 31
9765 #define DDR_PHY_DX0GCR0_CALBYP_MASK 0x80000000U
9767 /*Master Delay Line Enable*/
9768 #undef DDR_PHY_DX0GCR0_MDLEN_DEFVAL
9769 #undef DDR_PHY_DX0GCR0_MDLEN_SHIFT
9770 #undef DDR_PHY_DX0GCR0_MDLEN_MASK
9771 #define DDR_PHY_DX0GCR0_MDLEN_DEFVAL 0x40200204
9772 #define DDR_PHY_DX0GCR0_MDLEN_SHIFT 30
9773 #define DDR_PHY_DX0GCR0_MDLEN_MASK 0x40000000U
9775 /*Configurable ODT(TE) Phase Shift*/
9776 #undef DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL
9777 #undef DDR_PHY_DX0GCR0_CODTSHFT_SHIFT
9778 #undef DDR_PHY_DX0GCR0_CODTSHFT_MASK
9779 #define DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL 0x40200204
9780 #define DDR_PHY_DX0GCR0_CODTSHFT_SHIFT 28
9781 #define DDR_PHY_DX0GCR0_CODTSHFT_MASK 0x30000000U
9783 /*DQS Duty Cycle Correction*/
9784 #undef DDR_PHY_DX0GCR0_DQSDCC_DEFVAL
9785 #undef DDR_PHY_DX0GCR0_DQSDCC_SHIFT
9786 #undef DDR_PHY_DX0GCR0_DQSDCC_MASK
9787 #define DDR_PHY_DX0GCR0_DQSDCC_DEFVAL 0x40200204
9788 #define DDR_PHY_DX0GCR0_DQSDCC_SHIFT 24
9789 #define DDR_PHY_DX0GCR0_DQSDCC_MASK 0x0F000000U
9791 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
9792 #undef DDR_PHY_DX0GCR0_RDDLY_DEFVAL
9793 #undef DDR_PHY_DX0GCR0_RDDLY_SHIFT
9794 #undef DDR_PHY_DX0GCR0_RDDLY_MASK
9795 #define DDR_PHY_DX0GCR0_RDDLY_DEFVAL 0x40200204
9796 #define DDR_PHY_DX0GCR0_RDDLY_SHIFT 20
9797 #define DDR_PHY_DX0GCR0_RDDLY_MASK 0x00F00000U
9799 /*Reserved. Return zeroes on reads.*/
9800 #undef DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL
9801 #undef DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT
9802 #undef DDR_PHY_DX0GCR0_RESERVED_19_14_MASK
9803 #define DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL 0x40200204
9804 #define DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT 14
9805 #define DDR_PHY_DX0GCR0_RESERVED_19_14_MASK 0x000FC000U
9807 /*DQSNSE Power Down Receiver*/
9808 #undef DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL
9809 #undef DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT
9810 #undef DDR_PHY_DX0GCR0_DQSNSEPDR_MASK
9811 #define DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL 0x40200204
9812 #define DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT 13
9813 #define DDR_PHY_DX0GCR0_DQSNSEPDR_MASK 0x00002000U
9815 /*DQSSE Power Down Receiver*/
9816 #undef DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL
9817 #undef DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT
9818 #undef DDR_PHY_DX0GCR0_DQSSEPDR_MASK
9819 #define DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL 0x40200204
9820 #define DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT 12
9821 #define DDR_PHY_DX0GCR0_DQSSEPDR_MASK 0x00001000U
9823 /*RTT On Additive Latency*/
9824 #undef DDR_PHY_DX0GCR0_RTTOAL_DEFVAL
9825 #undef DDR_PHY_DX0GCR0_RTTOAL_SHIFT
9826 #undef DDR_PHY_DX0GCR0_RTTOAL_MASK
9827 #define DDR_PHY_DX0GCR0_RTTOAL_DEFVAL 0x40200204
9828 #define DDR_PHY_DX0GCR0_RTTOAL_SHIFT 11
9829 #define DDR_PHY_DX0GCR0_RTTOAL_MASK 0x00000800U
9832 #undef DDR_PHY_DX0GCR0_RTTOH_DEFVAL
9833 #undef DDR_PHY_DX0GCR0_RTTOH_SHIFT
9834 #undef DDR_PHY_DX0GCR0_RTTOH_MASK
9835 #define DDR_PHY_DX0GCR0_RTTOH_DEFVAL 0x40200204
9836 #define DDR_PHY_DX0GCR0_RTTOH_SHIFT 9
9837 #define DDR_PHY_DX0GCR0_RTTOH_MASK 0x00000600U
9839 /*Configurable PDR Phase Shift*/
9840 #undef DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL
9841 #undef DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT
9842 #undef DDR_PHY_DX0GCR0_CPDRSHFT_MASK
9843 #define DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL 0x40200204
9844 #define DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT 7
9845 #define DDR_PHY_DX0GCR0_CPDRSHFT_MASK 0x00000180U
9848 #undef DDR_PHY_DX0GCR0_DQSRPD_DEFVAL
9849 #undef DDR_PHY_DX0GCR0_DQSRPD_SHIFT
9850 #undef DDR_PHY_DX0GCR0_DQSRPD_MASK
9851 #define DDR_PHY_DX0GCR0_DQSRPD_DEFVAL 0x40200204
9852 #define DDR_PHY_DX0GCR0_DQSRPD_SHIFT 6
9853 #define DDR_PHY_DX0GCR0_DQSRPD_MASK 0x00000040U
9855 /*DQSG Power Down Receiver*/
9856 #undef DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL
9857 #undef DDR_PHY_DX0GCR0_DQSGPDR_SHIFT
9858 #undef DDR_PHY_DX0GCR0_DQSGPDR_MASK
9859 #define DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL 0x40200204
9860 #define DDR_PHY_DX0GCR0_DQSGPDR_SHIFT 5
9861 #define DDR_PHY_DX0GCR0_DQSGPDR_MASK 0x00000020U
9863 /*Reserved. Return zeroes on reads.*/
9864 #undef DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL
9865 #undef DDR_PHY_DX0GCR0_RESERVED_4_SHIFT
9866 #undef DDR_PHY_DX0GCR0_RESERVED_4_MASK
9867 #define DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL 0x40200204
9868 #define DDR_PHY_DX0GCR0_RESERVED_4_SHIFT 4
9869 #define DDR_PHY_DX0GCR0_RESERVED_4_MASK 0x00000010U
9871 /*DQSG On-Die Termination*/
9872 #undef DDR_PHY_DX0GCR0_DQSGODT_DEFVAL
9873 #undef DDR_PHY_DX0GCR0_DQSGODT_SHIFT
9874 #undef DDR_PHY_DX0GCR0_DQSGODT_MASK
9875 #define DDR_PHY_DX0GCR0_DQSGODT_DEFVAL 0x40200204
9876 #define DDR_PHY_DX0GCR0_DQSGODT_SHIFT 3
9877 #define DDR_PHY_DX0GCR0_DQSGODT_MASK 0x00000008U
9879 /*DQSG Output Enable*/
9880 #undef DDR_PHY_DX0GCR0_DQSGOE_DEFVAL
9881 #undef DDR_PHY_DX0GCR0_DQSGOE_SHIFT
9882 #undef DDR_PHY_DX0GCR0_DQSGOE_MASK
9883 #define DDR_PHY_DX0GCR0_DQSGOE_DEFVAL 0x40200204
9884 #define DDR_PHY_DX0GCR0_DQSGOE_SHIFT 2
9885 #define DDR_PHY_DX0GCR0_DQSGOE_MASK 0x00000004U
9887 /*Reserved. Return zeroes on reads.*/
9888 #undef DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL
9889 #undef DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT
9890 #undef DDR_PHY_DX0GCR0_RESERVED_1_0_MASK
9891 #define DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL 0x40200204
9892 #define DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT 0
9893 #define DDR_PHY_DX0GCR0_RESERVED_1_0_MASK 0x00000003U
9895 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
9896 #undef DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL
9897 #undef DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT
9898 #undef DDR_PHY_DX0GCR4_RESERVED_31_29_MASK
9899 #define DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL 0x0E00003C
9900 #define DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT 29
9901 #define DDR_PHY_DX0GCR4_RESERVED_31_29_MASK 0xE0000000U
9903 /*Byte Lane VREF Pad Enable*/
9904 #undef DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL
9905 #undef DDR_PHY_DX0GCR4_DXREFPEN_SHIFT
9906 #undef DDR_PHY_DX0GCR4_DXREFPEN_MASK
9907 #define DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL 0x0E00003C
9908 #define DDR_PHY_DX0GCR4_DXREFPEN_SHIFT 28
9909 #define DDR_PHY_DX0GCR4_DXREFPEN_MASK 0x10000000U
9911 /*Byte Lane Internal VREF Enable*/
9912 #undef DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL
9913 #undef DDR_PHY_DX0GCR4_DXREFEEN_SHIFT
9914 #undef DDR_PHY_DX0GCR4_DXREFEEN_MASK
9915 #define DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL 0x0E00003C
9916 #define DDR_PHY_DX0GCR4_DXREFEEN_SHIFT 26
9917 #define DDR_PHY_DX0GCR4_DXREFEEN_MASK 0x0C000000U
9919 /*Byte Lane Single-End VREF Enable*/
9920 #undef DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL
9921 #undef DDR_PHY_DX0GCR4_DXREFSEN_SHIFT
9922 #undef DDR_PHY_DX0GCR4_DXREFSEN_MASK
9923 #define DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL 0x0E00003C
9924 #define DDR_PHY_DX0GCR4_DXREFSEN_SHIFT 25
9925 #define DDR_PHY_DX0GCR4_DXREFSEN_MASK 0x02000000U
9927 /*Reserved. Returns zeros on reads.*/
9928 #undef DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL
9929 #undef DDR_PHY_DX0GCR4_RESERVED_24_SHIFT
9930 #undef DDR_PHY_DX0GCR4_RESERVED_24_MASK
9931 #define DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL 0x0E00003C
9932 #define DDR_PHY_DX0GCR4_RESERVED_24_SHIFT 24
9933 #define DDR_PHY_DX0GCR4_RESERVED_24_MASK 0x01000000U
9935 /*External VREF generator REFSEL range select*/
9936 #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL
9937 #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT
9938 #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK
9939 #define DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C
9940 #define DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT 23
9941 #define DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK 0x00800000U
9943 /*Byte Lane External VREF Select*/
9944 #undef DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL
9945 #undef DDR_PHY_DX0GCR4_DXREFESEL_SHIFT
9946 #undef DDR_PHY_DX0GCR4_DXREFESEL_MASK
9947 #define DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL 0x0E00003C
9948 #define DDR_PHY_DX0GCR4_DXREFESEL_SHIFT 16
9949 #define DDR_PHY_DX0GCR4_DXREFESEL_MASK 0x007F0000U
9951 /*Single ended VREF generator REFSEL range select*/
9952 #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL
9953 #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT
9954 #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK
9955 #define DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C
9956 #define DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT 15
9957 #define DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK 0x00008000U
9959 /*Byte Lane Single-End VREF Select*/
9960 #undef DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL
9961 #undef DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT
9962 #undef DDR_PHY_DX0GCR4_DXREFSSEL_MASK
9963 #define DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL 0x0E00003C
9964 #define DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT 8
9965 #define DDR_PHY_DX0GCR4_DXREFSSEL_MASK 0x00007F00U
9967 /*Reserved. Returns zeros on reads.*/
9968 #undef DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL
9969 #undef DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT
9970 #undef DDR_PHY_DX0GCR4_RESERVED_7_6_MASK
9971 #define DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL 0x0E00003C
9972 #define DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT 6
9973 #define DDR_PHY_DX0GCR4_RESERVED_7_6_MASK 0x000000C0U
9975 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
9976 #undef DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL
9977 #undef DDR_PHY_DX0GCR4_DXREFIEN_SHIFT
9978 #undef DDR_PHY_DX0GCR4_DXREFIEN_MASK
9979 #define DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL 0x0E00003C
9980 #define DDR_PHY_DX0GCR4_DXREFIEN_SHIFT 2
9981 #define DDR_PHY_DX0GCR4_DXREFIEN_MASK 0x0000003CU
9983 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
9984 #undef DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL
9985 #undef DDR_PHY_DX0GCR4_DXREFIMON_SHIFT
9986 #undef DDR_PHY_DX0GCR4_DXREFIMON_MASK
9987 #define DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL 0x0E00003C
9988 #define DDR_PHY_DX0GCR4_DXREFIMON_SHIFT 0
9989 #define DDR_PHY_DX0GCR4_DXREFIMON_MASK 0x00000003U
9991 /*Reserved. Returns zeros on reads.*/
9992 #undef DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL
9993 #undef DDR_PHY_DX0GCR5_RESERVED_31_SHIFT
9994 #undef DDR_PHY_DX0GCR5_RESERVED_31_MASK
9995 #define DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL 0x09090909
9996 #define DDR_PHY_DX0GCR5_RESERVED_31_SHIFT 31
9997 #define DDR_PHY_DX0GCR5_RESERVED_31_MASK 0x80000000U
9999 /*Byte Lane internal VREF Select for Rank 3*/
10000 #undef DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL
10001 #undef DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT
10002 #undef DDR_PHY_DX0GCR5_DXREFISELR3_MASK
10003 #define DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL 0x09090909
10004 #define DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT 24
10005 #define DDR_PHY_DX0GCR5_DXREFISELR3_MASK 0x7F000000U
10007 /*Reserved. Returns zeros on reads.*/
10008 #undef DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL
10009 #undef DDR_PHY_DX0GCR5_RESERVED_23_SHIFT
10010 #undef DDR_PHY_DX0GCR5_RESERVED_23_MASK
10011 #define DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL 0x09090909
10012 #define DDR_PHY_DX0GCR5_RESERVED_23_SHIFT 23
10013 #define DDR_PHY_DX0GCR5_RESERVED_23_MASK 0x00800000U
10015 /*Byte Lane internal VREF Select for Rank 2*/
10016 #undef DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL
10017 #undef DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT
10018 #undef DDR_PHY_DX0GCR5_DXREFISELR2_MASK
10019 #define DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL 0x09090909
10020 #define DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT 16
10021 #define DDR_PHY_DX0GCR5_DXREFISELR2_MASK 0x007F0000U
10023 /*Reserved. Returns zeros on reads.*/
10024 #undef DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL
10025 #undef DDR_PHY_DX0GCR5_RESERVED_15_SHIFT
10026 #undef DDR_PHY_DX0GCR5_RESERVED_15_MASK
10027 #define DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL 0x09090909
10028 #define DDR_PHY_DX0GCR5_RESERVED_15_SHIFT 15
10029 #define DDR_PHY_DX0GCR5_RESERVED_15_MASK 0x00008000U
10031 /*Byte Lane internal VREF Select for Rank 1*/
10032 #undef DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL
10033 #undef DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT
10034 #undef DDR_PHY_DX0GCR5_DXREFISELR1_MASK
10035 #define DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL 0x09090909
10036 #define DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT 8
10037 #define DDR_PHY_DX0GCR5_DXREFISELR1_MASK 0x00007F00U
10039 /*Reserved. Returns zeros on reads.*/
10040 #undef DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL
10041 #undef DDR_PHY_DX0GCR5_RESERVED_7_SHIFT
10042 #undef DDR_PHY_DX0GCR5_RESERVED_7_MASK
10043 #define DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL 0x09090909
10044 #define DDR_PHY_DX0GCR5_RESERVED_7_SHIFT 7
10045 #define DDR_PHY_DX0GCR5_RESERVED_7_MASK 0x00000080U
10047 /*Byte Lane internal VREF Select for Rank 0*/
10048 #undef DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL
10049 #undef DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT
10050 #undef DDR_PHY_DX0GCR5_DXREFISELR0_MASK
10051 #define DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL 0x09090909
10052 #define DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT 0
10053 #define DDR_PHY_DX0GCR5_DXREFISELR0_MASK 0x0000007FU
10055 /*Reserved. Returns zeros on reads.*/
10056 #undef DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL
10057 #undef DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT
10058 #undef DDR_PHY_DX0GCR6_RESERVED_31_30_MASK
10059 #define DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL 0x09090909
10060 #define DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT 30
10061 #define DDR_PHY_DX0GCR6_RESERVED_31_30_MASK 0xC0000000U
10063 /*DRAM DQ VREF Select for Rank3*/
10064 #undef DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL
10065 #undef DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT
10066 #undef DDR_PHY_DX0GCR6_DXDQVREFR3_MASK
10067 #define DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL 0x09090909
10068 #define DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT 24
10069 #define DDR_PHY_DX0GCR6_DXDQVREFR3_MASK 0x3F000000U
10071 /*Reserved. Returns zeros on reads.*/
10072 #undef DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL
10073 #undef DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT
10074 #undef DDR_PHY_DX0GCR6_RESERVED_23_22_MASK
10075 #define DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL 0x09090909
10076 #define DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT 22
10077 #define DDR_PHY_DX0GCR6_RESERVED_23_22_MASK 0x00C00000U
10079 /*DRAM DQ VREF Select for Rank2*/
10080 #undef DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL
10081 #undef DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT
10082 #undef DDR_PHY_DX0GCR6_DXDQVREFR2_MASK
10083 #define DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL 0x09090909
10084 #define DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT 16
10085 #define DDR_PHY_DX0GCR6_DXDQVREFR2_MASK 0x003F0000U
10087 /*Reserved. Returns zeros on reads.*/
10088 #undef DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL
10089 #undef DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT
10090 #undef DDR_PHY_DX0GCR6_RESERVED_15_14_MASK
10091 #define DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL 0x09090909
10092 #define DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT 14
10093 #define DDR_PHY_DX0GCR6_RESERVED_15_14_MASK 0x0000C000U
10095 /*DRAM DQ VREF Select for Rank1*/
10096 #undef DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL
10097 #undef DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT
10098 #undef DDR_PHY_DX0GCR6_DXDQVREFR1_MASK
10099 #define DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL 0x09090909
10100 #define DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT 8
10101 #define DDR_PHY_DX0GCR6_DXDQVREFR1_MASK 0x00003F00U
10103 /*Reserved. Returns zeros on reads.*/
10104 #undef DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL
10105 #undef DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT
10106 #undef DDR_PHY_DX0GCR6_RESERVED_7_6_MASK
10107 #define DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL 0x09090909
10108 #define DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT 6
10109 #define DDR_PHY_DX0GCR6_RESERVED_7_6_MASK 0x000000C0U
10111 /*DRAM DQ VREF Select for Rank0*/
10112 #undef DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL
10113 #undef DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT
10114 #undef DDR_PHY_DX0GCR6_DXDQVREFR0_MASK
10115 #define DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL 0x09090909
10116 #define DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT 0
10117 #define DDR_PHY_DX0GCR6_DXDQVREFR0_MASK 0x0000003FU
10119 /*Reserved. Return zeroes on reads.*/
10120 #undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_DEFVAL
10121 #undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT
10122 #undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK
10123 #define DDR_PHY_DX0LCDLR2_RESERVED_31_25_DEFVAL 0x00000000
10124 #define DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT 25
10125 #define DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK 0xFE000000U
10127 /*Reserved. Caution, do not write to this register field.*/
10128 #undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_DEFVAL
10129 #undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT
10130 #undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK
10131 #define DDR_PHY_DX0LCDLR2_RESERVED_24_16_DEFVAL 0x00000000
10132 #define DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT 16
10133 #define DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK 0x01FF0000U
10135 /*Reserved. Return zeroes on reads.*/
10136 #undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_DEFVAL
10137 #undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT
10138 #undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK
10139 #define DDR_PHY_DX0LCDLR2_RESERVED_15_9_DEFVAL 0x00000000
10140 #define DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT 9
10141 #define DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK 0x0000FE00U
10143 /*Read DQS Gating Delay*/
10144 #undef DDR_PHY_DX0LCDLR2_DQSGD_DEFVAL
10145 #undef DDR_PHY_DX0LCDLR2_DQSGD_SHIFT
10146 #undef DDR_PHY_DX0LCDLR2_DQSGD_MASK
10147 #define DDR_PHY_DX0LCDLR2_DQSGD_DEFVAL 0x00000000
10148 #define DDR_PHY_DX0LCDLR2_DQSGD_SHIFT 0
10149 #define DDR_PHY_DX0LCDLR2_DQSGD_MASK 0x000001FFU
10151 /*Reserved. Return zeroes on reads.*/
10152 #undef DDR_PHY_DX0GTR0_RESERVED_31_24_DEFVAL
10153 #undef DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT
10154 #undef DDR_PHY_DX0GTR0_RESERVED_31_24_MASK
10155 #define DDR_PHY_DX0GTR0_RESERVED_31_24_DEFVAL 0x00020000
10156 #define DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT 27
10157 #define DDR_PHY_DX0GTR0_RESERVED_31_24_MASK 0xF8000000U
10159 /*DQ Write Path Latency Pipeline*/
10160 #undef DDR_PHY_DX0GTR0_WDQSL_DEFVAL
10161 #undef DDR_PHY_DX0GTR0_WDQSL_SHIFT
10162 #undef DDR_PHY_DX0GTR0_WDQSL_MASK
10163 #define DDR_PHY_DX0GTR0_WDQSL_DEFVAL 0x00020000
10164 #define DDR_PHY_DX0GTR0_WDQSL_SHIFT 24
10165 #define DDR_PHY_DX0GTR0_WDQSL_MASK 0x07000000U
10167 /*Reserved. Caution, do not write to this register field.*/
10168 #undef DDR_PHY_DX0GTR0_RESERVED_23_20_DEFVAL
10169 #undef DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT
10170 #undef DDR_PHY_DX0GTR0_RESERVED_23_20_MASK
10171 #define DDR_PHY_DX0GTR0_RESERVED_23_20_DEFVAL 0x00020000
10172 #define DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT 20
10173 #define DDR_PHY_DX0GTR0_RESERVED_23_20_MASK 0x00F00000U
10175 /*Write Leveling System Latency*/
10176 #undef DDR_PHY_DX0GTR0_WLSL_DEFVAL
10177 #undef DDR_PHY_DX0GTR0_WLSL_SHIFT
10178 #undef DDR_PHY_DX0GTR0_WLSL_MASK
10179 #define DDR_PHY_DX0GTR0_WLSL_DEFVAL 0x00020000
10180 #define DDR_PHY_DX0GTR0_WLSL_SHIFT 16
10181 #define DDR_PHY_DX0GTR0_WLSL_MASK 0x000F0000U
10183 /*Reserved. Return zeroes on reads.*/
10184 #undef DDR_PHY_DX0GTR0_RESERVED_15_13_DEFVAL
10185 #undef DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT
10186 #undef DDR_PHY_DX0GTR0_RESERVED_15_13_MASK
10187 #define DDR_PHY_DX0GTR0_RESERVED_15_13_DEFVAL 0x00020000
10188 #define DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT 13
10189 #define DDR_PHY_DX0GTR0_RESERVED_15_13_MASK 0x0000E000U
10191 /*Reserved. Caution, do not write to this register field.*/
10192 #undef DDR_PHY_DX0GTR0_RESERVED_12_8_DEFVAL
10193 #undef DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT
10194 #undef DDR_PHY_DX0GTR0_RESERVED_12_8_MASK
10195 #define DDR_PHY_DX0GTR0_RESERVED_12_8_DEFVAL 0x00020000
10196 #define DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT 8
10197 #define DDR_PHY_DX0GTR0_RESERVED_12_8_MASK 0x00001F00U
10199 /*Reserved. Return zeroes on reads.*/
10200 #undef DDR_PHY_DX0GTR0_RESERVED_7_5_DEFVAL
10201 #undef DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT
10202 #undef DDR_PHY_DX0GTR0_RESERVED_7_5_MASK
10203 #define DDR_PHY_DX0GTR0_RESERVED_7_5_DEFVAL 0x00020000
10204 #define DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT 5
10205 #define DDR_PHY_DX0GTR0_RESERVED_7_5_MASK 0x000000E0U
10207 /*DQS Gating System Latency*/
10208 #undef DDR_PHY_DX0GTR0_DGSL_DEFVAL
10209 #undef DDR_PHY_DX0GTR0_DGSL_SHIFT
10210 #undef DDR_PHY_DX0GTR0_DGSL_MASK
10211 #define DDR_PHY_DX0GTR0_DGSL_DEFVAL 0x00020000
10212 #define DDR_PHY_DX0GTR0_DGSL_SHIFT 0
10213 #define DDR_PHY_DX0GTR0_DGSL_MASK 0x0000001FU
10215 /*Calibration Bypass*/
10216 #undef DDR_PHY_DX1GCR0_CALBYP_DEFVAL
10217 #undef DDR_PHY_DX1GCR0_CALBYP_SHIFT
10218 #undef DDR_PHY_DX1GCR0_CALBYP_MASK
10219 #define DDR_PHY_DX1GCR0_CALBYP_DEFVAL 0x40200204
10220 #define DDR_PHY_DX1GCR0_CALBYP_SHIFT 31
10221 #define DDR_PHY_DX1GCR0_CALBYP_MASK 0x80000000U
10223 /*Master Delay Line Enable*/
10224 #undef DDR_PHY_DX1GCR0_MDLEN_DEFVAL
10225 #undef DDR_PHY_DX1GCR0_MDLEN_SHIFT
10226 #undef DDR_PHY_DX1GCR0_MDLEN_MASK
10227 #define DDR_PHY_DX1GCR0_MDLEN_DEFVAL 0x40200204
10228 #define DDR_PHY_DX1GCR0_MDLEN_SHIFT 30
10229 #define DDR_PHY_DX1GCR0_MDLEN_MASK 0x40000000U
10231 /*Configurable ODT(TE) Phase Shift*/
10232 #undef DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL
10233 #undef DDR_PHY_DX1GCR0_CODTSHFT_SHIFT
10234 #undef DDR_PHY_DX1GCR0_CODTSHFT_MASK
10235 #define DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL 0x40200204
10236 #define DDR_PHY_DX1GCR0_CODTSHFT_SHIFT 28
10237 #define DDR_PHY_DX1GCR0_CODTSHFT_MASK 0x30000000U
10239 /*DQS Duty Cycle Correction*/
10240 #undef DDR_PHY_DX1GCR0_DQSDCC_DEFVAL
10241 #undef DDR_PHY_DX1GCR0_DQSDCC_SHIFT
10242 #undef DDR_PHY_DX1GCR0_DQSDCC_MASK
10243 #define DDR_PHY_DX1GCR0_DQSDCC_DEFVAL 0x40200204
10244 #define DDR_PHY_DX1GCR0_DQSDCC_SHIFT 24
10245 #define DDR_PHY_DX1GCR0_DQSDCC_MASK 0x0F000000U
10247 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
10248 #undef DDR_PHY_DX1GCR0_RDDLY_DEFVAL
10249 #undef DDR_PHY_DX1GCR0_RDDLY_SHIFT
10250 #undef DDR_PHY_DX1GCR0_RDDLY_MASK
10251 #define DDR_PHY_DX1GCR0_RDDLY_DEFVAL 0x40200204
10252 #define DDR_PHY_DX1GCR0_RDDLY_SHIFT 20
10253 #define DDR_PHY_DX1GCR0_RDDLY_MASK 0x00F00000U
10255 /*Reserved. Return zeroes on reads.*/
10256 #undef DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL
10257 #undef DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT
10258 #undef DDR_PHY_DX1GCR0_RESERVED_19_14_MASK
10259 #define DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL 0x40200204
10260 #define DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT 14
10261 #define DDR_PHY_DX1GCR0_RESERVED_19_14_MASK 0x000FC000U
10263 /*DQSNSE Power Down Receiver*/
10264 #undef DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL
10265 #undef DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT
10266 #undef DDR_PHY_DX1GCR0_DQSNSEPDR_MASK
10267 #define DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL 0x40200204
10268 #define DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT 13
10269 #define DDR_PHY_DX1GCR0_DQSNSEPDR_MASK 0x00002000U
10271 /*DQSSE Power Down Receiver*/
10272 #undef DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL
10273 #undef DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT
10274 #undef DDR_PHY_DX1GCR0_DQSSEPDR_MASK
10275 #define DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL 0x40200204
10276 #define DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT 12
10277 #define DDR_PHY_DX1GCR0_DQSSEPDR_MASK 0x00001000U
10279 /*RTT On Additive Latency*/
10280 #undef DDR_PHY_DX1GCR0_RTTOAL_DEFVAL
10281 #undef DDR_PHY_DX1GCR0_RTTOAL_SHIFT
10282 #undef DDR_PHY_DX1GCR0_RTTOAL_MASK
10283 #define DDR_PHY_DX1GCR0_RTTOAL_DEFVAL 0x40200204
10284 #define DDR_PHY_DX1GCR0_RTTOAL_SHIFT 11
10285 #define DDR_PHY_DX1GCR0_RTTOAL_MASK 0x00000800U
10287 /*RTT Output Hold*/
10288 #undef DDR_PHY_DX1GCR0_RTTOH_DEFVAL
10289 #undef DDR_PHY_DX1GCR0_RTTOH_SHIFT
10290 #undef DDR_PHY_DX1GCR0_RTTOH_MASK
10291 #define DDR_PHY_DX1GCR0_RTTOH_DEFVAL 0x40200204
10292 #define DDR_PHY_DX1GCR0_RTTOH_SHIFT 9
10293 #define DDR_PHY_DX1GCR0_RTTOH_MASK 0x00000600U
10295 /*Configurable PDR Phase Shift*/
10296 #undef DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL
10297 #undef DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT
10298 #undef DDR_PHY_DX1GCR0_CPDRSHFT_MASK
10299 #define DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL 0x40200204
10300 #define DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT 7
10301 #define DDR_PHY_DX1GCR0_CPDRSHFT_MASK 0x00000180U
10303 /*DQSR Power Down*/
10304 #undef DDR_PHY_DX1GCR0_DQSRPD_DEFVAL
10305 #undef DDR_PHY_DX1GCR0_DQSRPD_SHIFT
10306 #undef DDR_PHY_DX1GCR0_DQSRPD_MASK
10307 #define DDR_PHY_DX1GCR0_DQSRPD_DEFVAL 0x40200204
10308 #define DDR_PHY_DX1GCR0_DQSRPD_SHIFT 6
10309 #define DDR_PHY_DX1GCR0_DQSRPD_MASK 0x00000040U
10311 /*DQSG Power Down Receiver*/
10312 #undef DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL
10313 #undef DDR_PHY_DX1GCR0_DQSGPDR_SHIFT
10314 #undef DDR_PHY_DX1GCR0_DQSGPDR_MASK
10315 #define DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL 0x40200204
10316 #define DDR_PHY_DX1GCR0_DQSGPDR_SHIFT 5
10317 #define DDR_PHY_DX1GCR0_DQSGPDR_MASK 0x00000020U
10319 /*Reserved. Return zeroes on reads.*/
10320 #undef DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL
10321 #undef DDR_PHY_DX1GCR0_RESERVED_4_SHIFT
10322 #undef DDR_PHY_DX1GCR0_RESERVED_4_MASK
10323 #define DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL 0x40200204
10324 #define DDR_PHY_DX1GCR0_RESERVED_4_SHIFT 4
10325 #define DDR_PHY_DX1GCR0_RESERVED_4_MASK 0x00000010U
10327 /*DQSG On-Die Termination*/
10328 #undef DDR_PHY_DX1GCR0_DQSGODT_DEFVAL
10329 #undef DDR_PHY_DX1GCR0_DQSGODT_SHIFT
10330 #undef DDR_PHY_DX1GCR0_DQSGODT_MASK
10331 #define DDR_PHY_DX1GCR0_DQSGODT_DEFVAL 0x40200204
10332 #define DDR_PHY_DX1GCR0_DQSGODT_SHIFT 3
10333 #define DDR_PHY_DX1GCR0_DQSGODT_MASK 0x00000008U
10335 /*DQSG Output Enable*/
10336 #undef DDR_PHY_DX1GCR0_DQSGOE_DEFVAL
10337 #undef DDR_PHY_DX1GCR0_DQSGOE_SHIFT
10338 #undef DDR_PHY_DX1GCR0_DQSGOE_MASK
10339 #define DDR_PHY_DX1GCR0_DQSGOE_DEFVAL 0x40200204
10340 #define DDR_PHY_DX1GCR0_DQSGOE_SHIFT 2
10341 #define DDR_PHY_DX1GCR0_DQSGOE_MASK 0x00000004U
10343 /*Reserved. Return zeroes on reads.*/
10344 #undef DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL
10345 #undef DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT
10346 #undef DDR_PHY_DX1GCR0_RESERVED_1_0_MASK
10347 #define DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL 0x40200204
10348 #define DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT 0
10349 #define DDR_PHY_DX1GCR0_RESERVED_1_0_MASK 0x00000003U
10351 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
10352 #undef DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL
10353 #undef DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT
10354 #undef DDR_PHY_DX1GCR4_RESERVED_31_29_MASK
10355 #define DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL 0x0E00003C
10356 #define DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT 29
10357 #define DDR_PHY_DX1GCR4_RESERVED_31_29_MASK 0xE0000000U
10359 /*Byte Lane VREF Pad Enable*/
10360 #undef DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL
10361 #undef DDR_PHY_DX1GCR4_DXREFPEN_SHIFT
10362 #undef DDR_PHY_DX1GCR4_DXREFPEN_MASK
10363 #define DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL 0x0E00003C
10364 #define DDR_PHY_DX1GCR4_DXREFPEN_SHIFT 28
10365 #define DDR_PHY_DX1GCR4_DXREFPEN_MASK 0x10000000U
10367 /*Byte Lane Internal VREF Enable*/
10368 #undef DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL
10369 #undef DDR_PHY_DX1GCR4_DXREFEEN_SHIFT
10370 #undef DDR_PHY_DX1GCR4_DXREFEEN_MASK
10371 #define DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL 0x0E00003C
10372 #define DDR_PHY_DX1GCR4_DXREFEEN_SHIFT 26
10373 #define DDR_PHY_DX1GCR4_DXREFEEN_MASK 0x0C000000U
10375 /*Byte Lane Single-End VREF Enable*/
10376 #undef DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL
10377 #undef DDR_PHY_DX1GCR4_DXREFSEN_SHIFT
10378 #undef DDR_PHY_DX1GCR4_DXREFSEN_MASK
10379 #define DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL 0x0E00003C
10380 #define DDR_PHY_DX1GCR4_DXREFSEN_SHIFT 25
10381 #define DDR_PHY_DX1GCR4_DXREFSEN_MASK 0x02000000U
10383 /*Reserved. Returns zeros on reads.*/
10384 #undef DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL
10385 #undef DDR_PHY_DX1GCR4_RESERVED_24_SHIFT
10386 #undef DDR_PHY_DX1GCR4_RESERVED_24_MASK
10387 #define DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL 0x0E00003C
10388 #define DDR_PHY_DX1GCR4_RESERVED_24_SHIFT 24
10389 #define DDR_PHY_DX1GCR4_RESERVED_24_MASK 0x01000000U
10391 /*External VREF generator REFSEL range select*/
10392 #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL
10393 #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT
10394 #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK
10395 #define DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C
10396 #define DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT 23
10397 #define DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK 0x00800000U
10399 /*Byte Lane External VREF Select*/
10400 #undef DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL
10401 #undef DDR_PHY_DX1GCR4_DXREFESEL_SHIFT
10402 #undef DDR_PHY_DX1GCR4_DXREFESEL_MASK
10403 #define DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL 0x0E00003C
10404 #define DDR_PHY_DX1GCR4_DXREFESEL_SHIFT 16
10405 #define DDR_PHY_DX1GCR4_DXREFESEL_MASK 0x007F0000U
10407 /*Single ended VREF generator REFSEL range select*/
10408 #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL
10409 #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT
10410 #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK
10411 #define DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C
10412 #define DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT 15
10413 #define DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK 0x00008000U
10415 /*Byte Lane Single-End VREF Select*/
10416 #undef DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL
10417 #undef DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT
10418 #undef DDR_PHY_DX1GCR4_DXREFSSEL_MASK
10419 #define DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL 0x0E00003C
10420 #define DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT 8
10421 #define DDR_PHY_DX1GCR4_DXREFSSEL_MASK 0x00007F00U
10423 /*Reserved. Returns zeros on reads.*/
10424 #undef DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL
10425 #undef DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT
10426 #undef DDR_PHY_DX1GCR4_RESERVED_7_6_MASK
10427 #define DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL 0x0E00003C
10428 #define DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT 6
10429 #define DDR_PHY_DX1GCR4_RESERVED_7_6_MASK 0x000000C0U
10431 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
10432 #undef DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL
10433 #undef DDR_PHY_DX1GCR4_DXREFIEN_SHIFT
10434 #undef DDR_PHY_DX1GCR4_DXREFIEN_MASK
10435 #define DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL 0x0E00003C
10436 #define DDR_PHY_DX1GCR4_DXREFIEN_SHIFT 2
10437 #define DDR_PHY_DX1GCR4_DXREFIEN_MASK 0x0000003CU
10439 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
10440 #undef DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL
10441 #undef DDR_PHY_DX1GCR4_DXREFIMON_SHIFT
10442 #undef DDR_PHY_DX1GCR4_DXREFIMON_MASK
10443 #define DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL 0x0E00003C
10444 #define DDR_PHY_DX1GCR4_DXREFIMON_SHIFT 0
10445 #define DDR_PHY_DX1GCR4_DXREFIMON_MASK 0x00000003U
10447 /*Reserved. Returns zeros on reads.*/
10448 #undef DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL
10449 #undef DDR_PHY_DX1GCR5_RESERVED_31_SHIFT
10450 #undef DDR_PHY_DX1GCR5_RESERVED_31_MASK
10451 #define DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL 0x09090909
10452 #define DDR_PHY_DX1GCR5_RESERVED_31_SHIFT 31
10453 #define DDR_PHY_DX1GCR5_RESERVED_31_MASK 0x80000000U
10455 /*Byte Lane internal VREF Select for Rank 3*/
10456 #undef DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL
10457 #undef DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT
10458 #undef DDR_PHY_DX1GCR5_DXREFISELR3_MASK
10459 #define DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL 0x09090909
10460 #define DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT 24
10461 #define DDR_PHY_DX1GCR5_DXREFISELR3_MASK 0x7F000000U
10463 /*Reserved. Returns zeros on reads.*/
10464 #undef DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL
10465 #undef DDR_PHY_DX1GCR5_RESERVED_23_SHIFT
10466 #undef DDR_PHY_DX1GCR5_RESERVED_23_MASK
10467 #define DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL 0x09090909
10468 #define DDR_PHY_DX1GCR5_RESERVED_23_SHIFT 23
10469 #define DDR_PHY_DX1GCR5_RESERVED_23_MASK 0x00800000U
10471 /*Byte Lane internal VREF Select for Rank 2*/
10472 #undef DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL
10473 #undef DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT
10474 #undef DDR_PHY_DX1GCR5_DXREFISELR2_MASK
10475 #define DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL 0x09090909
10476 #define DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT 16
10477 #define DDR_PHY_DX1GCR5_DXREFISELR2_MASK 0x007F0000U
10479 /*Reserved. Returns zeros on reads.*/
10480 #undef DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL
10481 #undef DDR_PHY_DX1GCR5_RESERVED_15_SHIFT
10482 #undef DDR_PHY_DX1GCR5_RESERVED_15_MASK
10483 #define DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL 0x09090909
10484 #define DDR_PHY_DX1GCR5_RESERVED_15_SHIFT 15
10485 #define DDR_PHY_DX1GCR5_RESERVED_15_MASK 0x00008000U
10487 /*Byte Lane internal VREF Select for Rank 1*/
10488 #undef DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL
10489 #undef DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT
10490 #undef DDR_PHY_DX1GCR5_DXREFISELR1_MASK
10491 #define DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL 0x09090909
10492 #define DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT 8
10493 #define DDR_PHY_DX1GCR5_DXREFISELR1_MASK 0x00007F00U
10495 /*Reserved. Returns zeros on reads.*/
10496 #undef DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL
10497 #undef DDR_PHY_DX1GCR5_RESERVED_7_SHIFT
10498 #undef DDR_PHY_DX1GCR5_RESERVED_7_MASK
10499 #define DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL 0x09090909
10500 #define DDR_PHY_DX1GCR5_RESERVED_7_SHIFT 7
10501 #define DDR_PHY_DX1GCR5_RESERVED_7_MASK 0x00000080U
10503 /*Byte Lane internal VREF Select for Rank 0*/
10504 #undef DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL
10505 #undef DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT
10506 #undef DDR_PHY_DX1GCR5_DXREFISELR0_MASK
10507 #define DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL 0x09090909
10508 #define DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT 0
10509 #define DDR_PHY_DX1GCR5_DXREFISELR0_MASK 0x0000007FU
10511 /*Reserved. Returns zeros on reads.*/
10512 #undef DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL
10513 #undef DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT
10514 #undef DDR_PHY_DX1GCR6_RESERVED_31_30_MASK
10515 #define DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL 0x09090909
10516 #define DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT 30
10517 #define DDR_PHY_DX1GCR6_RESERVED_31_30_MASK 0xC0000000U
10519 /*DRAM DQ VREF Select for Rank3*/
10520 #undef DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL
10521 #undef DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT
10522 #undef DDR_PHY_DX1GCR6_DXDQVREFR3_MASK
10523 #define DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL 0x09090909
10524 #define DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT 24
10525 #define DDR_PHY_DX1GCR6_DXDQVREFR3_MASK 0x3F000000U
10527 /*Reserved. Returns zeros on reads.*/
10528 #undef DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL
10529 #undef DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT
10530 #undef DDR_PHY_DX1GCR6_RESERVED_23_22_MASK
10531 #define DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL 0x09090909
10532 #define DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT 22
10533 #define DDR_PHY_DX1GCR6_RESERVED_23_22_MASK 0x00C00000U
10535 /*DRAM DQ VREF Select for Rank2*/
10536 #undef DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL
10537 #undef DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT
10538 #undef DDR_PHY_DX1GCR6_DXDQVREFR2_MASK
10539 #define DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL 0x09090909
10540 #define DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT 16
10541 #define DDR_PHY_DX1GCR6_DXDQVREFR2_MASK 0x003F0000U
10543 /*Reserved. Returns zeros on reads.*/
10544 #undef DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL
10545 #undef DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT
10546 #undef DDR_PHY_DX1GCR6_RESERVED_15_14_MASK
10547 #define DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL 0x09090909
10548 #define DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT 14
10549 #define DDR_PHY_DX1GCR6_RESERVED_15_14_MASK 0x0000C000U
10551 /*DRAM DQ VREF Select for Rank1*/
10552 #undef DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL
10553 #undef DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT
10554 #undef DDR_PHY_DX1GCR6_DXDQVREFR1_MASK
10555 #define DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL 0x09090909
10556 #define DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT 8
10557 #define DDR_PHY_DX1GCR6_DXDQVREFR1_MASK 0x00003F00U
10559 /*Reserved. Returns zeros on reads.*/
10560 #undef DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL
10561 #undef DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT
10562 #undef DDR_PHY_DX1GCR6_RESERVED_7_6_MASK
10563 #define DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL 0x09090909
10564 #define DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT 6
10565 #define DDR_PHY_DX1GCR6_RESERVED_7_6_MASK 0x000000C0U
10567 /*DRAM DQ VREF Select for Rank0*/
10568 #undef DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL
10569 #undef DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT
10570 #undef DDR_PHY_DX1GCR6_DXDQVREFR0_MASK
10571 #define DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL 0x09090909
10572 #define DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT 0
10573 #define DDR_PHY_DX1GCR6_DXDQVREFR0_MASK 0x0000003FU
10575 /*Reserved. Return zeroes on reads.*/
10576 #undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_DEFVAL
10577 #undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT
10578 #undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK
10579 #define DDR_PHY_DX1LCDLR2_RESERVED_31_25_DEFVAL 0x00000000
10580 #define DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT 25
10581 #define DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK 0xFE000000U
10583 /*Reserved. Caution, do not write to this register field.*/
10584 #undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_DEFVAL
10585 #undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT
10586 #undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK
10587 #define DDR_PHY_DX1LCDLR2_RESERVED_24_16_DEFVAL 0x00000000
10588 #define DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT 16
10589 #define DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK 0x01FF0000U
10591 /*Reserved. Return zeroes on reads.*/
10592 #undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_DEFVAL
10593 #undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT
10594 #undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK
10595 #define DDR_PHY_DX1LCDLR2_RESERVED_15_9_DEFVAL 0x00000000
10596 #define DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT 9
10597 #define DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK 0x0000FE00U
10599 /*Read DQS Gating Delay*/
10600 #undef DDR_PHY_DX1LCDLR2_DQSGD_DEFVAL
10601 #undef DDR_PHY_DX1LCDLR2_DQSGD_SHIFT
10602 #undef DDR_PHY_DX1LCDLR2_DQSGD_MASK
10603 #define DDR_PHY_DX1LCDLR2_DQSGD_DEFVAL 0x00000000
10604 #define DDR_PHY_DX1LCDLR2_DQSGD_SHIFT 0
10605 #define DDR_PHY_DX1LCDLR2_DQSGD_MASK 0x000001FFU
10607 /*Reserved. Return zeroes on reads.*/
10608 #undef DDR_PHY_DX1GTR0_RESERVED_31_24_DEFVAL
10609 #undef DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT
10610 #undef DDR_PHY_DX1GTR0_RESERVED_31_24_MASK
10611 #define DDR_PHY_DX1GTR0_RESERVED_31_24_DEFVAL 0x00020000
10612 #define DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT 27
10613 #define DDR_PHY_DX1GTR0_RESERVED_31_24_MASK 0xF8000000U
10615 /*DQ Write Path Latency Pipeline*/
10616 #undef DDR_PHY_DX1GTR0_WDQSL_DEFVAL
10617 #undef DDR_PHY_DX1GTR0_WDQSL_SHIFT
10618 #undef DDR_PHY_DX1GTR0_WDQSL_MASK
10619 #define DDR_PHY_DX1GTR0_WDQSL_DEFVAL 0x00020000
10620 #define DDR_PHY_DX1GTR0_WDQSL_SHIFT 24
10621 #define DDR_PHY_DX1GTR0_WDQSL_MASK 0x07000000U
10623 /*Reserved. Caution, do not write to this register field.*/
10624 #undef DDR_PHY_DX1GTR0_RESERVED_23_20_DEFVAL
10625 #undef DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT
10626 #undef DDR_PHY_DX1GTR0_RESERVED_23_20_MASK
10627 #define DDR_PHY_DX1GTR0_RESERVED_23_20_DEFVAL 0x00020000
10628 #define DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT 20
10629 #define DDR_PHY_DX1GTR0_RESERVED_23_20_MASK 0x00F00000U
10631 /*Write Leveling System Latency*/
10632 #undef DDR_PHY_DX1GTR0_WLSL_DEFVAL
10633 #undef DDR_PHY_DX1GTR0_WLSL_SHIFT
10634 #undef DDR_PHY_DX1GTR0_WLSL_MASK
10635 #define DDR_PHY_DX1GTR0_WLSL_DEFVAL 0x00020000
10636 #define DDR_PHY_DX1GTR0_WLSL_SHIFT 16
10637 #define DDR_PHY_DX1GTR0_WLSL_MASK 0x000F0000U
10639 /*Reserved. Return zeroes on reads.*/
10640 #undef DDR_PHY_DX1GTR0_RESERVED_15_13_DEFVAL
10641 #undef DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT
10642 #undef DDR_PHY_DX1GTR0_RESERVED_15_13_MASK
10643 #define DDR_PHY_DX1GTR0_RESERVED_15_13_DEFVAL 0x00020000
10644 #define DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT 13
10645 #define DDR_PHY_DX1GTR0_RESERVED_15_13_MASK 0x0000E000U
10647 /*Reserved. Caution, do not write to this register field.*/
10648 #undef DDR_PHY_DX1GTR0_RESERVED_12_8_DEFVAL
10649 #undef DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT
10650 #undef DDR_PHY_DX1GTR0_RESERVED_12_8_MASK
10651 #define DDR_PHY_DX1GTR0_RESERVED_12_8_DEFVAL 0x00020000
10652 #define DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT 8
10653 #define DDR_PHY_DX1GTR0_RESERVED_12_8_MASK 0x00001F00U
10655 /*Reserved. Return zeroes on reads.*/
10656 #undef DDR_PHY_DX1GTR0_RESERVED_7_5_DEFVAL
10657 #undef DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT
10658 #undef DDR_PHY_DX1GTR0_RESERVED_7_5_MASK
10659 #define DDR_PHY_DX1GTR0_RESERVED_7_5_DEFVAL 0x00020000
10660 #define DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT 5
10661 #define DDR_PHY_DX1GTR0_RESERVED_7_5_MASK 0x000000E0U
10663 /*DQS Gating System Latency*/
10664 #undef DDR_PHY_DX1GTR0_DGSL_DEFVAL
10665 #undef DDR_PHY_DX1GTR0_DGSL_SHIFT
10666 #undef DDR_PHY_DX1GTR0_DGSL_MASK
10667 #define DDR_PHY_DX1GTR0_DGSL_DEFVAL 0x00020000
10668 #define DDR_PHY_DX1GTR0_DGSL_SHIFT 0
10669 #define DDR_PHY_DX1GTR0_DGSL_MASK 0x0000001FU
10671 /*Calibration Bypass*/
10672 #undef DDR_PHY_DX2GCR0_CALBYP_DEFVAL
10673 #undef DDR_PHY_DX2GCR0_CALBYP_SHIFT
10674 #undef DDR_PHY_DX2GCR0_CALBYP_MASK
10675 #define DDR_PHY_DX2GCR0_CALBYP_DEFVAL 0x40200204
10676 #define DDR_PHY_DX2GCR0_CALBYP_SHIFT 31
10677 #define DDR_PHY_DX2GCR0_CALBYP_MASK 0x80000000U
10679 /*Master Delay Line Enable*/
10680 #undef DDR_PHY_DX2GCR0_MDLEN_DEFVAL
10681 #undef DDR_PHY_DX2GCR0_MDLEN_SHIFT
10682 #undef DDR_PHY_DX2GCR0_MDLEN_MASK
10683 #define DDR_PHY_DX2GCR0_MDLEN_DEFVAL 0x40200204
10684 #define DDR_PHY_DX2GCR0_MDLEN_SHIFT 30
10685 #define DDR_PHY_DX2GCR0_MDLEN_MASK 0x40000000U
10687 /*Configurable ODT(TE) Phase Shift*/
10688 #undef DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL
10689 #undef DDR_PHY_DX2GCR0_CODTSHFT_SHIFT
10690 #undef DDR_PHY_DX2GCR0_CODTSHFT_MASK
10691 #define DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL 0x40200204
10692 #define DDR_PHY_DX2GCR0_CODTSHFT_SHIFT 28
10693 #define DDR_PHY_DX2GCR0_CODTSHFT_MASK 0x30000000U
10695 /*DQS Duty Cycle Correction*/
10696 #undef DDR_PHY_DX2GCR0_DQSDCC_DEFVAL
10697 #undef DDR_PHY_DX2GCR0_DQSDCC_SHIFT
10698 #undef DDR_PHY_DX2GCR0_DQSDCC_MASK
10699 #define DDR_PHY_DX2GCR0_DQSDCC_DEFVAL 0x40200204
10700 #define DDR_PHY_DX2GCR0_DQSDCC_SHIFT 24
10701 #define DDR_PHY_DX2GCR0_DQSDCC_MASK 0x0F000000U
10703 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
10704 #undef DDR_PHY_DX2GCR0_RDDLY_DEFVAL
10705 #undef DDR_PHY_DX2GCR0_RDDLY_SHIFT
10706 #undef DDR_PHY_DX2GCR0_RDDLY_MASK
10707 #define DDR_PHY_DX2GCR0_RDDLY_DEFVAL 0x40200204
10708 #define DDR_PHY_DX2GCR0_RDDLY_SHIFT 20
10709 #define DDR_PHY_DX2GCR0_RDDLY_MASK 0x00F00000U
10711 /*Reserved. Return zeroes on reads.*/
10712 #undef DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL
10713 #undef DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT
10714 #undef DDR_PHY_DX2GCR0_RESERVED_19_14_MASK
10715 #define DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL 0x40200204
10716 #define DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT 14
10717 #define DDR_PHY_DX2GCR0_RESERVED_19_14_MASK 0x000FC000U
10719 /*DQSNSE Power Down Receiver*/
10720 #undef DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL
10721 #undef DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT
10722 #undef DDR_PHY_DX2GCR0_DQSNSEPDR_MASK
10723 #define DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL 0x40200204
10724 #define DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT 13
10725 #define DDR_PHY_DX2GCR0_DQSNSEPDR_MASK 0x00002000U
10727 /*DQSSE Power Down Receiver*/
10728 #undef DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL
10729 #undef DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT
10730 #undef DDR_PHY_DX2GCR0_DQSSEPDR_MASK
10731 #define DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL 0x40200204
10732 #define DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT 12
10733 #define DDR_PHY_DX2GCR0_DQSSEPDR_MASK 0x00001000U
10735 /*RTT On Additive Latency*/
10736 #undef DDR_PHY_DX2GCR0_RTTOAL_DEFVAL
10737 #undef DDR_PHY_DX2GCR0_RTTOAL_SHIFT
10738 #undef DDR_PHY_DX2GCR0_RTTOAL_MASK
10739 #define DDR_PHY_DX2GCR0_RTTOAL_DEFVAL 0x40200204
10740 #define DDR_PHY_DX2GCR0_RTTOAL_SHIFT 11
10741 #define DDR_PHY_DX2GCR0_RTTOAL_MASK 0x00000800U
10743 /*RTT Output Hold*/
10744 #undef DDR_PHY_DX2GCR0_RTTOH_DEFVAL
10745 #undef DDR_PHY_DX2GCR0_RTTOH_SHIFT
10746 #undef DDR_PHY_DX2GCR0_RTTOH_MASK
10747 #define DDR_PHY_DX2GCR0_RTTOH_DEFVAL 0x40200204
10748 #define DDR_PHY_DX2GCR0_RTTOH_SHIFT 9
10749 #define DDR_PHY_DX2GCR0_RTTOH_MASK 0x00000600U
10751 /*Configurable PDR Phase Shift*/
10752 #undef DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL
10753 #undef DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT
10754 #undef DDR_PHY_DX2GCR0_CPDRSHFT_MASK
10755 #define DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL 0x40200204
10756 #define DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT 7
10757 #define DDR_PHY_DX2GCR0_CPDRSHFT_MASK 0x00000180U
10759 /*DQSR Power Down*/
10760 #undef DDR_PHY_DX2GCR0_DQSRPD_DEFVAL
10761 #undef DDR_PHY_DX2GCR0_DQSRPD_SHIFT
10762 #undef DDR_PHY_DX2GCR0_DQSRPD_MASK
10763 #define DDR_PHY_DX2GCR0_DQSRPD_DEFVAL 0x40200204
10764 #define DDR_PHY_DX2GCR0_DQSRPD_SHIFT 6
10765 #define DDR_PHY_DX2GCR0_DQSRPD_MASK 0x00000040U
10767 /*DQSG Power Down Receiver*/
10768 #undef DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL
10769 #undef DDR_PHY_DX2GCR0_DQSGPDR_SHIFT
10770 #undef DDR_PHY_DX2GCR0_DQSGPDR_MASK
10771 #define DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL 0x40200204
10772 #define DDR_PHY_DX2GCR0_DQSGPDR_SHIFT 5
10773 #define DDR_PHY_DX2GCR0_DQSGPDR_MASK 0x00000020U
10775 /*Reserved. Return zeroes on reads.*/
10776 #undef DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL
10777 #undef DDR_PHY_DX2GCR0_RESERVED_4_SHIFT
10778 #undef DDR_PHY_DX2GCR0_RESERVED_4_MASK
10779 #define DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL 0x40200204
10780 #define DDR_PHY_DX2GCR0_RESERVED_4_SHIFT 4
10781 #define DDR_PHY_DX2GCR0_RESERVED_4_MASK 0x00000010U
10783 /*DQSG On-Die Termination*/
10784 #undef DDR_PHY_DX2GCR0_DQSGODT_DEFVAL
10785 #undef DDR_PHY_DX2GCR0_DQSGODT_SHIFT
10786 #undef DDR_PHY_DX2GCR0_DQSGODT_MASK
10787 #define DDR_PHY_DX2GCR0_DQSGODT_DEFVAL 0x40200204
10788 #define DDR_PHY_DX2GCR0_DQSGODT_SHIFT 3
10789 #define DDR_PHY_DX2GCR0_DQSGODT_MASK 0x00000008U
10791 /*DQSG Output Enable*/
10792 #undef DDR_PHY_DX2GCR0_DQSGOE_DEFVAL
10793 #undef DDR_PHY_DX2GCR0_DQSGOE_SHIFT
10794 #undef DDR_PHY_DX2GCR0_DQSGOE_MASK
10795 #define DDR_PHY_DX2GCR0_DQSGOE_DEFVAL 0x40200204
10796 #define DDR_PHY_DX2GCR0_DQSGOE_SHIFT 2
10797 #define DDR_PHY_DX2GCR0_DQSGOE_MASK 0x00000004U
10799 /*Reserved. Return zeroes on reads.*/
10800 #undef DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL
10801 #undef DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT
10802 #undef DDR_PHY_DX2GCR0_RESERVED_1_0_MASK
10803 #define DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL 0x40200204
10804 #define DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT 0
10805 #define DDR_PHY_DX2GCR0_RESERVED_1_0_MASK 0x00000003U
10807 /*Enables the PDR mode for DQ[7:0]*/
10808 #undef DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL
10809 #undef DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT
10810 #undef DDR_PHY_DX2GCR1_DXPDRMODE_MASK
10811 #define DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL 0x00007FFF
10812 #define DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT 16
10813 #define DDR_PHY_DX2GCR1_DXPDRMODE_MASK 0xFFFF0000U
10815 /*Reserved. Returns zeroes on reads.*/
10816 #undef DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL
10817 #undef DDR_PHY_DX2GCR1_RESERVED_15_SHIFT
10818 #undef DDR_PHY_DX2GCR1_RESERVED_15_MASK
10819 #define DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL 0x00007FFF
10820 #define DDR_PHY_DX2GCR1_RESERVED_15_SHIFT 15
10821 #define DDR_PHY_DX2GCR1_RESERVED_15_MASK 0x00008000U
10823 /*Select the delayed or non-delayed read data strobe #*/
10824 #undef DDR_PHY_DX2GCR1_QSNSEL_DEFVAL
10825 #undef DDR_PHY_DX2GCR1_QSNSEL_SHIFT
10826 #undef DDR_PHY_DX2GCR1_QSNSEL_MASK
10827 #define DDR_PHY_DX2GCR1_QSNSEL_DEFVAL 0x00007FFF
10828 #define DDR_PHY_DX2GCR1_QSNSEL_SHIFT 14
10829 #define DDR_PHY_DX2GCR1_QSNSEL_MASK 0x00004000U
10831 /*Select the delayed or non-delayed read data strobe*/
10832 #undef DDR_PHY_DX2GCR1_QSSEL_DEFVAL
10833 #undef DDR_PHY_DX2GCR1_QSSEL_SHIFT
10834 #undef DDR_PHY_DX2GCR1_QSSEL_MASK
10835 #define DDR_PHY_DX2GCR1_QSSEL_DEFVAL 0x00007FFF
10836 #define DDR_PHY_DX2GCR1_QSSEL_SHIFT 13
10837 #define DDR_PHY_DX2GCR1_QSSEL_MASK 0x00002000U
10839 /*Enables Read Data Strobe in a byte lane*/
10840 #undef DDR_PHY_DX2GCR1_OEEN_DEFVAL
10841 #undef DDR_PHY_DX2GCR1_OEEN_SHIFT
10842 #undef DDR_PHY_DX2GCR1_OEEN_MASK
10843 #define DDR_PHY_DX2GCR1_OEEN_DEFVAL 0x00007FFF
10844 #define DDR_PHY_DX2GCR1_OEEN_SHIFT 12
10845 #define DDR_PHY_DX2GCR1_OEEN_MASK 0x00001000U
10847 /*Enables PDR in a byte lane*/
10848 #undef DDR_PHY_DX2GCR1_PDREN_DEFVAL
10849 #undef DDR_PHY_DX2GCR1_PDREN_SHIFT
10850 #undef DDR_PHY_DX2GCR1_PDREN_MASK
10851 #define DDR_PHY_DX2GCR1_PDREN_DEFVAL 0x00007FFF
10852 #define DDR_PHY_DX2GCR1_PDREN_SHIFT 11
10853 #define DDR_PHY_DX2GCR1_PDREN_MASK 0x00000800U
10855 /*Enables ODT/TE in a byte lane*/
10856 #undef DDR_PHY_DX2GCR1_TEEN_DEFVAL
10857 #undef DDR_PHY_DX2GCR1_TEEN_SHIFT
10858 #undef DDR_PHY_DX2GCR1_TEEN_MASK
10859 #define DDR_PHY_DX2GCR1_TEEN_DEFVAL 0x00007FFF
10860 #define DDR_PHY_DX2GCR1_TEEN_SHIFT 10
10861 #define DDR_PHY_DX2GCR1_TEEN_MASK 0x00000400U
10863 /*Enables Write Data strobe in a byte lane*/
10864 #undef DDR_PHY_DX2GCR1_DSEN_DEFVAL
10865 #undef DDR_PHY_DX2GCR1_DSEN_SHIFT
10866 #undef DDR_PHY_DX2GCR1_DSEN_MASK
10867 #define DDR_PHY_DX2GCR1_DSEN_DEFVAL 0x00007FFF
10868 #define DDR_PHY_DX2GCR1_DSEN_SHIFT 9
10869 #define DDR_PHY_DX2GCR1_DSEN_MASK 0x00000200U
10871 /*Enables DM pin in a byte lane*/
10872 #undef DDR_PHY_DX2GCR1_DMEN_DEFVAL
10873 #undef DDR_PHY_DX2GCR1_DMEN_SHIFT
10874 #undef DDR_PHY_DX2GCR1_DMEN_MASK
10875 #define DDR_PHY_DX2GCR1_DMEN_DEFVAL 0x00007FFF
10876 #define DDR_PHY_DX2GCR1_DMEN_SHIFT 8
10877 #define DDR_PHY_DX2GCR1_DMEN_MASK 0x00000100U
10879 /*Enables DQ corresponding to each bit in a byte*/
10880 #undef DDR_PHY_DX2GCR1_DQEN_DEFVAL
10881 #undef DDR_PHY_DX2GCR1_DQEN_SHIFT
10882 #undef DDR_PHY_DX2GCR1_DQEN_MASK
10883 #define DDR_PHY_DX2GCR1_DQEN_DEFVAL 0x00007FFF
10884 #define DDR_PHY_DX2GCR1_DQEN_SHIFT 0
10885 #define DDR_PHY_DX2GCR1_DQEN_MASK 0x000000FFU
10887 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
10888 #undef DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL
10889 #undef DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT
10890 #undef DDR_PHY_DX2GCR4_RESERVED_31_29_MASK
10891 #define DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL 0x0E00003C
10892 #define DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT 29
10893 #define DDR_PHY_DX2GCR4_RESERVED_31_29_MASK 0xE0000000U
10895 /*Byte Lane VREF Pad Enable*/
10896 #undef DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL
10897 #undef DDR_PHY_DX2GCR4_DXREFPEN_SHIFT
10898 #undef DDR_PHY_DX2GCR4_DXREFPEN_MASK
10899 #define DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL 0x0E00003C
10900 #define DDR_PHY_DX2GCR4_DXREFPEN_SHIFT 28
10901 #define DDR_PHY_DX2GCR4_DXREFPEN_MASK 0x10000000U
10903 /*Byte Lane Internal VREF Enable*/
10904 #undef DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL
10905 #undef DDR_PHY_DX2GCR4_DXREFEEN_SHIFT
10906 #undef DDR_PHY_DX2GCR4_DXREFEEN_MASK
10907 #define DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL 0x0E00003C
10908 #define DDR_PHY_DX2GCR4_DXREFEEN_SHIFT 26
10909 #define DDR_PHY_DX2GCR4_DXREFEEN_MASK 0x0C000000U
10911 /*Byte Lane Single-End VREF Enable*/
10912 #undef DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL
10913 #undef DDR_PHY_DX2GCR4_DXREFSEN_SHIFT
10914 #undef DDR_PHY_DX2GCR4_DXREFSEN_MASK
10915 #define DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL 0x0E00003C
10916 #define DDR_PHY_DX2GCR4_DXREFSEN_SHIFT 25
10917 #define DDR_PHY_DX2GCR4_DXREFSEN_MASK 0x02000000U
10919 /*Reserved. Returns zeros on reads.*/
10920 #undef DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL
10921 #undef DDR_PHY_DX2GCR4_RESERVED_24_SHIFT
10922 #undef DDR_PHY_DX2GCR4_RESERVED_24_MASK
10923 #define DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL 0x0E00003C
10924 #define DDR_PHY_DX2GCR4_RESERVED_24_SHIFT 24
10925 #define DDR_PHY_DX2GCR4_RESERVED_24_MASK 0x01000000U
10927 /*External VREF generator REFSEL range select*/
10928 #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL
10929 #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT
10930 #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK
10931 #define DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C
10932 #define DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT 23
10933 #define DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK 0x00800000U
10935 /*Byte Lane External VREF Select*/
10936 #undef DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL
10937 #undef DDR_PHY_DX2GCR4_DXREFESEL_SHIFT
10938 #undef DDR_PHY_DX2GCR4_DXREFESEL_MASK
10939 #define DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL 0x0E00003C
10940 #define DDR_PHY_DX2GCR4_DXREFESEL_SHIFT 16
10941 #define DDR_PHY_DX2GCR4_DXREFESEL_MASK 0x007F0000U
10943 /*Single ended VREF generator REFSEL range select*/
10944 #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL
10945 #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT
10946 #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK
10947 #define DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C
10948 #define DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT 15
10949 #define DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK 0x00008000U
10951 /*Byte Lane Single-End VREF Select*/
10952 #undef DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL
10953 #undef DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT
10954 #undef DDR_PHY_DX2GCR4_DXREFSSEL_MASK
10955 #define DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL 0x0E00003C
10956 #define DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT 8
10957 #define DDR_PHY_DX2GCR4_DXREFSSEL_MASK 0x00007F00U
10959 /*Reserved. Returns zeros on reads.*/
10960 #undef DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL
10961 #undef DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT
10962 #undef DDR_PHY_DX2GCR4_RESERVED_7_6_MASK
10963 #define DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL 0x0E00003C
10964 #define DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT 6
10965 #define DDR_PHY_DX2GCR4_RESERVED_7_6_MASK 0x000000C0U
10967 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
10968 #undef DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL
10969 #undef DDR_PHY_DX2GCR4_DXREFIEN_SHIFT
10970 #undef DDR_PHY_DX2GCR4_DXREFIEN_MASK
10971 #define DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL 0x0E00003C
10972 #define DDR_PHY_DX2GCR4_DXREFIEN_SHIFT 2
10973 #define DDR_PHY_DX2GCR4_DXREFIEN_MASK 0x0000003CU
10975 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
10976 #undef DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL
10977 #undef DDR_PHY_DX2GCR4_DXREFIMON_SHIFT
10978 #undef DDR_PHY_DX2GCR4_DXREFIMON_MASK
10979 #define DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL 0x0E00003C
10980 #define DDR_PHY_DX2GCR4_DXREFIMON_SHIFT 0
10981 #define DDR_PHY_DX2GCR4_DXREFIMON_MASK 0x00000003U
10983 /*Reserved. Returns zeros on reads.*/
10984 #undef DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL
10985 #undef DDR_PHY_DX2GCR5_RESERVED_31_SHIFT
10986 #undef DDR_PHY_DX2GCR5_RESERVED_31_MASK
10987 #define DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL 0x09090909
10988 #define DDR_PHY_DX2GCR5_RESERVED_31_SHIFT 31
10989 #define DDR_PHY_DX2GCR5_RESERVED_31_MASK 0x80000000U
10991 /*Byte Lane internal VREF Select for Rank 3*/
10992 #undef DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL
10993 #undef DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT
10994 #undef DDR_PHY_DX2GCR5_DXREFISELR3_MASK
10995 #define DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL 0x09090909
10996 #define DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT 24
10997 #define DDR_PHY_DX2GCR5_DXREFISELR3_MASK 0x7F000000U
10999 /*Reserved. Returns zeros on reads.*/
11000 #undef DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL
11001 #undef DDR_PHY_DX2GCR5_RESERVED_23_SHIFT
11002 #undef DDR_PHY_DX2GCR5_RESERVED_23_MASK
11003 #define DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL 0x09090909
11004 #define DDR_PHY_DX2GCR5_RESERVED_23_SHIFT 23
11005 #define DDR_PHY_DX2GCR5_RESERVED_23_MASK 0x00800000U
11007 /*Byte Lane internal VREF Select for Rank 2*/
11008 #undef DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL
11009 #undef DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT
11010 #undef DDR_PHY_DX2GCR5_DXREFISELR2_MASK
11011 #define DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL 0x09090909
11012 #define DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT 16
11013 #define DDR_PHY_DX2GCR5_DXREFISELR2_MASK 0x007F0000U
11015 /*Reserved. Returns zeros on reads.*/
11016 #undef DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL
11017 #undef DDR_PHY_DX2GCR5_RESERVED_15_SHIFT
11018 #undef DDR_PHY_DX2GCR5_RESERVED_15_MASK
11019 #define DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL 0x09090909
11020 #define DDR_PHY_DX2GCR5_RESERVED_15_SHIFT 15
11021 #define DDR_PHY_DX2GCR5_RESERVED_15_MASK 0x00008000U
11023 /*Byte Lane internal VREF Select for Rank 1*/
11024 #undef DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL
11025 #undef DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT
11026 #undef DDR_PHY_DX2GCR5_DXREFISELR1_MASK
11027 #define DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL 0x09090909
11028 #define DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT 8
11029 #define DDR_PHY_DX2GCR5_DXREFISELR1_MASK 0x00007F00U
11031 /*Reserved. Returns zeros on reads.*/
11032 #undef DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL
11033 #undef DDR_PHY_DX2GCR5_RESERVED_7_SHIFT
11034 #undef DDR_PHY_DX2GCR5_RESERVED_7_MASK
11035 #define DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL 0x09090909
11036 #define DDR_PHY_DX2GCR5_RESERVED_7_SHIFT 7
11037 #define DDR_PHY_DX2GCR5_RESERVED_7_MASK 0x00000080U
11039 /*Byte Lane internal VREF Select for Rank 0*/
11040 #undef DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL
11041 #undef DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT
11042 #undef DDR_PHY_DX2GCR5_DXREFISELR0_MASK
11043 #define DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL 0x09090909
11044 #define DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT 0
11045 #define DDR_PHY_DX2GCR5_DXREFISELR0_MASK 0x0000007FU
11047 /*Reserved. Returns zeros on reads.*/
11048 #undef DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL
11049 #undef DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT
11050 #undef DDR_PHY_DX2GCR6_RESERVED_31_30_MASK
11051 #define DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL 0x09090909
11052 #define DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT 30
11053 #define DDR_PHY_DX2GCR6_RESERVED_31_30_MASK 0xC0000000U
11055 /*DRAM DQ VREF Select for Rank3*/
11056 #undef DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL
11057 #undef DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT
11058 #undef DDR_PHY_DX2GCR6_DXDQVREFR3_MASK
11059 #define DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL 0x09090909
11060 #define DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT 24
11061 #define DDR_PHY_DX2GCR6_DXDQVREFR3_MASK 0x3F000000U
11063 /*Reserved. Returns zeros on reads.*/
11064 #undef DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL
11065 #undef DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT
11066 #undef DDR_PHY_DX2GCR6_RESERVED_23_22_MASK
11067 #define DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL 0x09090909
11068 #define DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT 22
11069 #define DDR_PHY_DX2GCR6_RESERVED_23_22_MASK 0x00C00000U
11071 /*DRAM DQ VREF Select for Rank2*/
11072 #undef DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL
11073 #undef DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT
11074 #undef DDR_PHY_DX2GCR6_DXDQVREFR2_MASK
11075 #define DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL 0x09090909
11076 #define DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT 16
11077 #define DDR_PHY_DX2GCR6_DXDQVREFR2_MASK 0x003F0000U
11079 /*Reserved. Returns zeros on reads.*/
11080 #undef DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL
11081 #undef DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT
11082 #undef DDR_PHY_DX2GCR6_RESERVED_15_14_MASK
11083 #define DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL 0x09090909
11084 #define DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT 14
11085 #define DDR_PHY_DX2GCR6_RESERVED_15_14_MASK 0x0000C000U
11087 /*DRAM DQ VREF Select for Rank1*/
11088 #undef DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL
11089 #undef DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT
11090 #undef DDR_PHY_DX2GCR6_DXDQVREFR1_MASK
11091 #define DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL 0x09090909
11092 #define DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT 8
11093 #define DDR_PHY_DX2GCR6_DXDQVREFR1_MASK 0x00003F00U
11095 /*Reserved. Returns zeros on reads.*/
11096 #undef DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL
11097 #undef DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT
11098 #undef DDR_PHY_DX2GCR6_RESERVED_7_6_MASK
11099 #define DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL 0x09090909
11100 #define DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT 6
11101 #define DDR_PHY_DX2GCR6_RESERVED_7_6_MASK 0x000000C0U
11103 /*DRAM DQ VREF Select for Rank0*/
11104 #undef DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL
11105 #undef DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT
11106 #undef DDR_PHY_DX2GCR6_DXDQVREFR0_MASK
11107 #define DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL 0x09090909
11108 #define DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT 0
11109 #define DDR_PHY_DX2GCR6_DXDQVREFR0_MASK 0x0000003FU
11111 /*Reserved. Return zeroes on reads.*/
11112 #undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_DEFVAL
11113 #undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT
11114 #undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK
11115 #define DDR_PHY_DX2LCDLR2_RESERVED_31_25_DEFVAL 0x00000000
11116 #define DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT 25
11117 #define DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK 0xFE000000U
11119 /*Reserved. Caution, do not write to this register field.*/
11120 #undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_DEFVAL
11121 #undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT
11122 #undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK
11123 #define DDR_PHY_DX2LCDLR2_RESERVED_24_16_DEFVAL 0x00000000
11124 #define DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT 16
11125 #define DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK 0x01FF0000U
11127 /*Reserved. Return zeroes on reads.*/
11128 #undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_DEFVAL
11129 #undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT
11130 #undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK
11131 #define DDR_PHY_DX2LCDLR2_RESERVED_15_9_DEFVAL 0x00000000
11132 #define DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT 9
11133 #define DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK 0x0000FE00U
11135 /*Read DQS Gating Delay*/
11136 #undef DDR_PHY_DX2LCDLR2_DQSGD_DEFVAL
11137 #undef DDR_PHY_DX2LCDLR2_DQSGD_SHIFT
11138 #undef DDR_PHY_DX2LCDLR2_DQSGD_MASK
11139 #define DDR_PHY_DX2LCDLR2_DQSGD_DEFVAL 0x00000000
11140 #define DDR_PHY_DX2LCDLR2_DQSGD_SHIFT 0
11141 #define DDR_PHY_DX2LCDLR2_DQSGD_MASK 0x000001FFU
11143 /*Reserved. Return zeroes on reads.*/
11144 #undef DDR_PHY_DX2GTR0_RESERVED_31_24_DEFVAL
11145 #undef DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT
11146 #undef DDR_PHY_DX2GTR0_RESERVED_31_24_MASK
11147 #define DDR_PHY_DX2GTR0_RESERVED_31_24_DEFVAL 0x00020000
11148 #define DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT 27
11149 #define DDR_PHY_DX2GTR0_RESERVED_31_24_MASK 0xF8000000U
11151 /*DQ Write Path Latency Pipeline*/
11152 #undef DDR_PHY_DX2GTR0_WDQSL_DEFVAL
11153 #undef DDR_PHY_DX2GTR0_WDQSL_SHIFT
11154 #undef DDR_PHY_DX2GTR0_WDQSL_MASK
11155 #define DDR_PHY_DX2GTR0_WDQSL_DEFVAL 0x00020000
11156 #define DDR_PHY_DX2GTR0_WDQSL_SHIFT 24
11157 #define DDR_PHY_DX2GTR0_WDQSL_MASK 0x07000000U
11159 /*Reserved. Caution, do not write to this register field.*/
11160 #undef DDR_PHY_DX2GTR0_RESERVED_23_20_DEFVAL
11161 #undef DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT
11162 #undef DDR_PHY_DX2GTR0_RESERVED_23_20_MASK
11163 #define DDR_PHY_DX2GTR0_RESERVED_23_20_DEFVAL 0x00020000
11164 #define DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT 20
11165 #define DDR_PHY_DX2GTR0_RESERVED_23_20_MASK 0x00F00000U
11167 /*Write Leveling System Latency*/
11168 #undef DDR_PHY_DX2GTR0_WLSL_DEFVAL
11169 #undef DDR_PHY_DX2GTR0_WLSL_SHIFT
11170 #undef DDR_PHY_DX2GTR0_WLSL_MASK
11171 #define DDR_PHY_DX2GTR0_WLSL_DEFVAL 0x00020000
11172 #define DDR_PHY_DX2GTR0_WLSL_SHIFT 16
11173 #define DDR_PHY_DX2GTR0_WLSL_MASK 0x000F0000U
11175 /*Reserved. Return zeroes on reads.*/
11176 #undef DDR_PHY_DX2GTR0_RESERVED_15_13_DEFVAL
11177 #undef DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT
11178 #undef DDR_PHY_DX2GTR0_RESERVED_15_13_MASK
11179 #define DDR_PHY_DX2GTR0_RESERVED_15_13_DEFVAL 0x00020000
11180 #define DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT 13
11181 #define DDR_PHY_DX2GTR0_RESERVED_15_13_MASK 0x0000E000U
11183 /*Reserved. Caution, do not write to this register field.*/
11184 #undef DDR_PHY_DX2GTR0_RESERVED_12_8_DEFVAL
11185 #undef DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT
11186 #undef DDR_PHY_DX2GTR0_RESERVED_12_8_MASK
11187 #define DDR_PHY_DX2GTR0_RESERVED_12_8_DEFVAL 0x00020000
11188 #define DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT 8
11189 #define DDR_PHY_DX2GTR0_RESERVED_12_8_MASK 0x00001F00U
11191 /*Reserved. Return zeroes on reads.*/
11192 #undef DDR_PHY_DX2GTR0_RESERVED_7_5_DEFVAL
11193 #undef DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT
11194 #undef DDR_PHY_DX2GTR0_RESERVED_7_5_MASK
11195 #define DDR_PHY_DX2GTR0_RESERVED_7_5_DEFVAL 0x00020000
11196 #define DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT 5
11197 #define DDR_PHY_DX2GTR0_RESERVED_7_5_MASK 0x000000E0U
11199 /*DQS Gating System Latency*/
11200 #undef DDR_PHY_DX2GTR0_DGSL_DEFVAL
11201 #undef DDR_PHY_DX2GTR0_DGSL_SHIFT
11202 #undef DDR_PHY_DX2GTR0_DGSL_MASK
11203 #define DDR_PHY_DX2GTR0_DGSL_DEFVAL 0x00020000
11204 #define DDR_PHY_DX2GTR0_DGSL_SHIFT 0
11205 #define DDR_PHY_DX2GTR0_DGSL_MASK 0x0000001FU
11207 /*Calibration Bypass*/
11208 #undef DDR_PHY_DX3GCR0_CALBYP_DEFVAL
11209 #undef DDR_PHY_DX3GCR0_CALBYP_SHIFT
11210 #undef DDR_PHY_DX3GCR0_CALBYP_MASK
11211 #define DDR_PHY_DX3GCR0_CALBYP_DEFVAL 0x40200204
11212 #define DDR_PHY_DX3GCR0_CALBYP_SHIFT 31
11213 #define DDR_PHY_DX3GCR0_CALBYP_MASK 0x80000000U
11215 /*Master Delay Line Enable*/
11216 #undef DDR_PHY_DX3GCR0_MDLEN_DEFVAL
11217 #undef DDR_PHY_DX3GCR0_MDLEN_SHIFT
11218 #undef DDR_PHY_DX3GCR0_MDLEN_MASK
11219 #define DDR_PHY_DX3GCR0_MDLEN_DEFVAL 0x40200204
11220 #define DDR_PHY_DX3GCR0_MDLEN_SHIFT 30
11221 #define DDR_PHY_DX3GCR0_MDLEN_MASK 0x40000000U
11223 /*Configurable ODT(TE) Phase Shift*/
11224 #undef DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL
11225 #undef DDR_PHY_DX3GCR0_CODTSHFT_SHIFT
11226 #undef DDR_PHY_DX3GCR0_CODTSHFT_MASK
11227 #define DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL 0x40200204
11228 #define DDR_PHY_DX3GCR0_CODTSHFT_SHIFT 28
11229 #define DDR_PHY_DX3GCR0_CODTSHFT_MASK 0x30000000U
11231 /*DQS Duty Cycle Correction*/
11232 #undef DDR_PHY_DX3GCR0_DQSDCC_DEFVAL
11233 #undef DDR_PHY_DX3GCR0_DQSDCC_SHIFT
11234 #undef DDR_PHY_DX3GCR0_DQSDCC_MASK
11235 #define DDR_PHY_DX3GCR0_DQSDCC_DEFVAL 0x40200204
11236 #define DDR_PHY_DX3GCR0_DQSDCC_SHIFT 24
11237 #define DDR_PHY_DX3GCR0_DQSDCC_MASK 0x0F000000U
11239 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
11240 #undef DDR_PHY_DX3GCR0_RDDLY_DEFVAL
11241 #undef DDR_PHY_DX3GCR0_RDDLY_SHIFT
11242 #undef DDR_PHY_DX3GCR0_RDDLY_MASK
11243 #define DDR_PHY_DX3GCR0_RDDLY_DEFVAL 0x40200204
11244 #define DDR_PHY_DX3GCR0_RDDLY_SHIFT 20
11245 #define DDR_PHY_DX3GCR0_RDDLY_MASK 0x00F00000U
11247 /*Reserved. Return zeroes on reads.*/
11248 #undef DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL
11249 #undef DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT
11250 #undef DDR_PHY_DX3GCR0_RESERVED_19_14_MASK
11251 #define DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL 0x40200204
11252 #define DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT 14
11253 #define DDR_PHY_DX3GCR0_RESERVED_19_14_MASK 0x000FC000U
11255 /*DQSNSE Power Down Receiver*/
11256 #undef DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL
11257 #undef DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT
11258 #undef DDR_PHY_DX3GCR0_DQSNSEPDR_MASK
11259 #define DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL 0x40200204
11260 #define DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT 13
11261 #define DDR_PHY_DX3GCR0_DQSNSEPDR_MASK 0x00002000U
11263 /*DQSSE Power Down Receiver*/
11264 #undef DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL
11265 #undef DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT
11266 #undef DDR_PHY_DX3GCR0_DQSSEPDR_MASK
11267 #define DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL 0x40200204
11268 #define DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT 12
11269 #define DDR_PHY_DX3GCR0_DQSSEPDR_MASK 0x00001000U
11271 /*RTT On Additive Latency*/
11272 #undef DDR_PHY_DX3GCR0_RTTOAL_DEFVAL
11273 #undef DDR_PHY_DX3GCR0_RTTOAL_SHIFT
11274 #undef DDR_PHY_DX3GCR0_RTTOAL_MASK
11275 #define DDR_PHY_DX3GCR0_RTTOAL_DEFVAL 0x40200204
11276 #define DDR_PHY_DX3GCR0_RTTOAL_SHIFT 11
11277 #define DDR_PHY_DX3GCR0_RTTOAL_MASK 0x00000800U
11279 /*RTT Output Hold*/
11280 #undef DDR_PHY_DX3GCR0_RTTOH_DEFVAL
11281 #undef DDR_PHY_DX3GCR0_RTTOH_SHIFT
11282 #undef DDR_PHY_DX3GCR0_RTTOH_MASK
11283 #define DDR_PHY_DX3GCR0_RTTOH_DEFVAL 0x40200204
11284 #define DDR_PHY_DX3GCR0_RTTOH_SHIFT 9
11285 #define DDR_PHY_DX3GCR0_RTTOH_MASK 0x00000600U
11287 /*Configurable PDR Phase Shift*/
11288 #undef DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL
11289 #undef DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT
11290 #undef DDR_PHY_DX3GCR0_CPDRSHFT_MASK
11291 #define DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL 0x40200204
11292 #define DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT 7
11293 #define DDR_PHY_DX3GCR0_CPDRSHFT_MASK 0x00000180U
11295 /*DQSR Power Down*/
11296 #undef DDR_PHY_DX3GCR0_DQSRPD_DEFVAL
11297 #undef DDR_PHY_DX3GCR0_DQSRPD_SHIFT
11298 #undef DDR_PHY_DX3GCR0_DQSRPD_MASK
11299 #define DDR_PHY_DX3GCR0_DQSRPD_DEFVAL 0x40200204
11300 #define DDR_PHY_DX3GCR0_DQSRPD_SHIFT 6
11301 #define DDR_PHY_DX3GCR0_DQSRPD_MASK 0x00000040U
11303 /*DQSG Power Down Receiver*/
11304 #undef DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL
11305 #undef DDR_PHY_DX3GCR0_DQSGPDR_SHIFT
11306 #undef DDR_PHY_DX3GCR0_DQSGPDR_MASK
11307 #define DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL 0x40200204
11308 #define DDR_PHY_DX3GCR0_DQSGPDR_SHIFT 5
11309 #define DDR_PHY_DX3GCR0_DQSGPDR_MASK 0x00000020U
11311 /*Reserved. Return zeroes on reads.*/
11312 #undef DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL
11313 #undef DDR_PHY_DX3GCR0_RESERVED_4_SHIFT
11314 #undef DDR_PHY_DX3GCR0_RESERVED_4_MASK
11315 #define DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL 0x40200204
11316 #define DDR_PHY_DX3GCR0_RESERVED_4_SHIFT 4
11317 #define DDR_PHY_DX3GCR0_RESERVED_4_MASK 0x00000010U
11319 /*DQSG On-Die Termination*/
11320 #undef DDR_PHY_DX3GCR0_DQSGODT_DEFVAL
11321 #undef DDR_PHY_DX3GCR0_DQSGODT_SHIFT
11322 #undef DDR_PHY_DX3GCR0_DQSGODT_MASK
11323 #define DDR_PHY_DX3GCR0_DQSGODT_DEFVAL 0x40200204
11324 #define DDR_PHY_DX3GCR0_DQSGODT_SHIFT 3
11325 #define DDR_PHY_DX3GCR0_DQSGODT_MASK 0x00000008U
11327 /*DQSG Output Enable*/
11328 #undef DDR_PHY_DX3GCR0_DQSGOE_DEFVAL
11329 #undef DDR_PHY_DX3GCR0_DQSGOE_SHIFT
11330 #undef DDR_PHY_DX3GCR0_DQSGOE_MASK
11331 #define DDR_PHY_DX3GCR0_DQSGOE_DEFVAL 0x40200204
11332 #define DDR_PHY_DX3GCR0_DQSGOE_SHIFT 2
11333 #define DDR_PHY_DX3GCR0_DQSGOE_MASK 0x00000004U
11335 /*Reserved. Return zeroes on reads.*/
11336 #undef DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL
11337 #undef DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT
11338 #undef DDR_PHY_DX3GCR0_RESERVED_1_0_MASK
11339 #define DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL 0x40200204
11340 #define DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT 0
11341 #define DDR_PHY_DX3GCR0_RESERVED_1_0_MASK 0x00000003U
11343 /*Enables the PDR mode for DQ[7:0]*/
11344 #undef DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL
11345 #undef DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT
11346 #undef DDR_PHY_DX3GCR1_DXPDRMODE_MASK
11347 #define DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL 0x00007FFF
11348 #define DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT 16
11349 #define DDR_PHY_DX3GCR1_DXPDRMODE_MASK 0xFFFF0000U
11351 /*Reserved. Returns zeroes on reads.*/
11352 #undef DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL
11353 #undef DDR_PHY_DX3GCR1_RESERVED_15_SHIFT
11354 #undef DDR_PHY_DX3GCR1_RESERVED_15_MASK
11355 #define DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL 0x00007FFF
11356 #define DDR_PHY_DX3GCR1_RESERVED_15_SHIFT 15
11357 #define DDR_PHY_DX3GCR1_RESERVED_15_MASK 0x00008000U
11359 /*Select the delayed or non-delayed read data strobe #*/
11360 #undef DDR_PHY_DX3GCR1_QSNSEL_DEFVAL
11361 #undef DDR_PHY_DX3GCR1_QSNSEL_SHIFT
11362 #undef DDR_PHY_DX3GCR1_QSNSEL_MASK
11363 #define DDR_PHY_DX3GCR1_QSNSEL_DEFVAL 0x00007FFF
11364 #define DDR_PHY_DX3GCR1_QSNSEL_SHIFT 14
11365 #define DDR_PHY_DX3GCR1_QSNSEL_MASK 0x00004000U
11367 /*Select the delayed or non-delayed read data strobe*/
11368 #undef DDR_PHY_DX3GCR1_QSSEL_DEFVAL
11369 #undef DDR_PHY_DX3GCR1_QSSEL_SHIFT
11370 #undef DDR_PHY_DX3GCR1_QSSEL_MASK
11371 #define DDR_PHY_DX3GCR1_QSSEL_DEFVAL 0x00007FFF
11372 #define DDR_PHY_DX3GCR1_QSSEL_SHIFT 13
11373 #define DDR_PHY_DX3GCR1_QSSEL_MASK 0x00002000U
11375 /*Enables Read Data Strobe in a byte lane*/
11376 #undef DDR_PHY_DX3GCR1_OEEN_DEFVAL
11377 #undef DDR_PHY_DX3GCR1_OEEN_SHIFT
11378 #undef DDR_PHY_DX3GCR1_OEEN_MASK
11379 #define DDR_PHY_DX3GCR1_OEEN_DEFVAL 0x00007FFF
11380 #define DDR_PHY_DX3GCR1_OEEN_SHIFT 12
11381 #define DDR_PHY_DX3GCR1_OEEN_MASK 0x00001000U
11383 /*Enables PDR in a byte lane*/
11384 #undef DDR_PHY_DX3GCR1_PDREN_DEFVAL
11385 #undef DDR_PHY_DX3GCR1_PDREN_SHIFT
11386 #undef DDR_PHY_DX3GCR1_PDREN_MASK
11387 #define DDR_PHY_DX3GCR1_PDREN_DEFVAL 0x00007FFF
11388 #define DDR_PHY_DX3GCR1_PDREN_SHIFT 11
11389 #define DDR_PHY_DX3GCR1_PDREN_MASK 0x00000800U
11391 /*Enables ODT/TE in a byte lane*/
11392 #undef DDR_PHY_DX3GCR1_TEEN_DEFVAL
11393 #undef DDR_PHY_DX3GCR1_TEEN_SHIFT
11394 #undef DDR_PHY_DX3GCR1_TEEN_MASK
11395 #define DDR_PHY_DX3GCR1_TEEN_DEFVAL 0x00007FFF
11396 #define DDR_PHY_DX3GCR1_TEEN_SHIFT 10
11397 #define DDR_PHY_DX3GCR1_TEEN_MASK 0x00000400U
11399 /*Enables Write Data strobe in a byte lane*/
11400 #undef DDR_PHY_DX3GCR1_DSEN_DEFVAL
11401 #undef DDR_PHY_DX3GCR1_DSEN_SHIFT
11402 #undef DDR_PHY_DX3GCR1_DSEN_MASK
11403 #define DDR_PHY_DX3GCR1_DSEN_DEFVAL 0x00007FFF
11404 #define DDR_PHY_DX3GCR1_DSEN_SHIFT 9
11405 #define DDR_PHY_DX3GCR1_DSEN_MASK 0x00000200U
11407 /*Enables DM pin in a byte lane*/
11408 #undef DDR_PHY_DX3GCR1_DMEN_DEFVAL
11409 #undef DDR_PHY_DX3GCR1_DMEN_SHIFT
11410 #undef DDR_PHY_DX3GCR1_DMEN_MASK
11411 #define DDR_PHY_DX3GCR1_DMEN_DEFVAL 0x00007FFF
11412 #define DDR_PHY_DX3GCR1_DMEN_SHIFT 8
11413 #define DDR_PHY_DX3GCR1_DMEN_MASK 0x00000100U
11415 /*Enables DQ corresponding to each bit in a byte*/
11416 #undef DDR_PHY_DX3GCR1_DQEN_DEFVAL
11417 #undef DDR_PHY_DX3GCR1_DQEN_SHIFT
11418 #undef DDR_PHY_DX3GCR1_DQEN_MASK
11419 #define DDR_PHY_DX3GCR1_DQEN_DEFVAL 0x00007FFF
11420 #define DDR_PHY_DX3GCR1_DQEN_SHIFT 0
11421 #define DDR_PHY_DX3GCR1_DQEN_MASK 0x000000FFU
11423 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
11424 #undef DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL
11425 #undef DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT
11426 #undef DDR_PHY_DX3GCR4_RESERVED_31_29_MASK
11427 #define DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL 0x0E00003C
11428 #define DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT 29
11429 #define DDR_PHY_DX3GCR4_RESERVED_31_29_MASK 0xE0000000U
11431 /*Byte Lane VREF Pad Enable*/
11432 #undef DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL
11433 #undef DDR_PHY_DX3GCR4_DXREFPEN_SHIFT
11434 #undef DDR_PHY_DX3GCR4_DXREFPEN_MASK
11435 #define DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL 0x0E00003C
11436 #define DDR_PHY_DX3GCR4_DXREFPEN_SHIFT 28
11437 #define DDR_PHY_DX3GCR4_DXREFPEN_MASK 0x10000000U
11439 /*Byte Lane Internal VREF Enable*/
11440 #undef DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL
11441 #undef DDR_PHY_DX3GCR4_DXREFEEN_SHIFT
11442 #undef DDR_PHY_DX3GCR4_DXREFEEN_MASK
11443 #define DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL 0x0E00003C
11444 #define DDR_PHY_DX3GCR4_DXREFEEN_SHIFT 26
11445 #define DDR_PHY_DX3GCR4_DXREFEEN_MASK 0x0C000000U
11447 /*Byte Lane Single-End VREF Enable*/
11448 #undef DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL
11449 #undef DDR_PHY_DX3GCR4_DXREFSEN_SHIFT
11450 #undef DDR_PHY_DX3GCR4_DXREFSEN_MASK
11451 #define DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL 0x0E00003C
11452 #define DDR_PHY_DX3GCR4_DXREFSEN_SHIFT 25
11453 #define DDR_PHY_DX3GCR4_DXREFSEN_MASK 0x02000000U
11455 /*Reserved. Returns zeros on reads.*/
11456 #undef DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL
11457 #undef DDR_PHY_DX3GCR4_RESERVED_24_SHIFT
11458 #undef DDR_PHY_DX3GCR4_RESERVED_24_MASK
11459 #define DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL 0x0E00003C
11460 #define DDR_PHY_DX3GCR4_RESERVED_24_SHIFT 24
11461 #define DDR_PHY_DX3GCR4_RESERVED_24_MASK 0x01000000U
11463 /*External VREF generator REFSEL range select*/
11464 #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL
11465 #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT
11466 #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK
11467 #define DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C
11468 #define DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT 23
11469 #define DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK 0x00800000U
11471 /*Byte Lane External VREF Select*/
11472 #undef DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL
11473 #undef DDR_PHY_DX3GCR4_DXREFESEL_SHIFT
11474 #undef DDR_PHY_DX3GCR4_DXREFESEL_MASK
11475 #define DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL 0x0E00003C
11476 #define DDR_PHY_DX3GCR4_DXREFESEL_SHIFT 16
11477 #define DDR_PHY_DX3GCR4_DXREFESEL_MASK 0x007F0000U
11479 /*Single ended VREF generator REFSEL range select*/
11480 #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL
11481 #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT
11482 #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK
11483 #define DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C
11484 #define DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT 15
11485 #define DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK 0x00008000U
11487 /*Byte Lane Single-End VREF Select*/
11488 #undef DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL
11489 #undef DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT
11490 #undef DDR_PHY_DX3GCR4_DXREFSSEL_MASK
11491 #define DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL 0x0E00003C
11492 #define DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT 8
11493 #define DDR_PHY_DX3GCR4_DXREFSSEL_MASK 0x00007F00U
11495 /*Reserved. Returns zeros on reads.*/
11496 #undef DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL
11497 #undef DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT
11498 #undef DDR_PHY_DX3GCR4_RESERVED_7_6_MASK
11499 #define DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL 0x0E00003C
11500 #define DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT 6
11501 #define DDR_PHY_DX3GCR4_RESERVED_7_6_MASK 0x000000C0U
11503 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
11504 #undef DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL
11505 #undef DDR_PHY_DX3GCR4_DXREFIEN_SHIFT
11506 #undef DDR_PHY_DX3GCR4_DXREFIEN_MASK
11507 #define DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL 0x0E00003C
11508 #define DDR_PHY_DX3GCR4_DXREFIEN_SHIFT 2
11509 #define DDR_PHY_DX3GCR4_DXREFIEN_MASK 0x0000003CU
11511 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
11512 #undef DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL
11513 #undef DDR_PHY_DX3GCR4_DXREFIMON_SHIFT
11514 #undef DDR_PHY_DX3GCR4_DXREFIMON_MASK
11515 #define DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL 0x0E00003C
11516 #define DDR_PHY_DX3GCR4_DXREFIMON_SHIFT 0
11517 #define DDR_PHY_DX3GCR4_DXREFIMON_MASK 0x00000003U
11519 /*Reserved. Returns zeros on reads.*/
11520 #undef DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL
11521 #undef DDR_PHY_DX3GCR5_RESERVED_31_SHIFT
11522 #undef DDR_PHY_DX3GCR5_RESERVED_31_MASK
11523 #define DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL 0x09090909
11524 #define DDR_PHY_DX3GCR5_RESERVED_31_SHIFT 31
11525 #define DDR_PHY_DX3GCR5_RESERVED_31_MASK 0x80000000U
11527 /*Byte Lane internal VREF Select for Rank 3*/
11528 #undef DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL
11529 #undef DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT
11530 #undef DDR_PHY_DX3GCR5_DXREFISELR3_MASK
11531 #define DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL 0x09090909
11532 #define DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT 24
11533 #define DDR_PHY_DX3GCR5_DXREFISELR3_MASK 0x7F000000U
11535 /*Reserved. Returns zeros on reads.*/
11536 #undef DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL
11537 #undef DDR_PHY_DX3GCR5_RESERVED_23_SHIFT
11538 #undef DDR_PHY_DX3GCR5_RESERVED_23_MASK
11539 #define DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL 0x09090909
11540 #define DDR_PHY_DX3GCR5_RESERVED_23_SHIFT 23
11541 #define DDR_PHY_DX3GCR5_RESERVED_23_MASK 0x00800000U
11543 /*Byte Lane internal VREF Select for Rank 2*/
11544 #undef DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL
11545 #undef DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT
11546 #undef DDR_PHY_DX3GCR5_DXREFISELR2_MASK
11547 #define DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL 0x09090909
11548 #define DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT 16
11549 #define DDR_PHY_DX3GCR5_DXREFISELR2_MASK 0x007F0000U
11551 /*Reserved. Returns zeros on reads.*/
11552 #undef DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL
11553 #undef DDR_PHY_DX3GCR5_RESERVED_15_SHIFT
11554 #undef DDR_PHY_DX3GCR5_RESERVED_15_MASK
11555 #define DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL 0x09090909
11556 #define DDR_PHY_DX3GCR5_RESERVED_15_SHIFT 15
11557 #define DDR_PHY_DX3GCR5_RESERVED_15_MASK 0x00008000U
11559 /*Byte Lane internal VREF Select for Rank 1*/
11560 #undef DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL
11561 #undef DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT
11562 #undef DDR_PHY_DX3GCR5_DXREFISELR1_MASK
11563 #define DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL 0x09090909
11564 #define DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT 8
11565 #define DDR_PHY_DX3GCR5_DXREFISELR1_MASK 0x00007F00U
11567 /*Reserved. Returns zeros on reads.*/
11568 #undef DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL
11569 #undef DDR_PHY_DX3GCR5_RESERVED_7_SHIFT
11570 #undef DDR_PHY_DX3GCR5_RESERVED_7_MASK
11571 #define DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL 0x09090909
11572 #define DDR_PHY_DX3GCR5_RESERVED_7_SHIFT 7
11573 #define DDR_PHY_DX3GCR5_RESERVED_7_MASK 0x00000080U
11575 /*Byte Lane internal VREF Select for Rank 0*/
11576 #undef DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL
11577 #undef DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT
11578 #undef DDR_PHY_DX3GCR5_DXREFISELR0_MASK
11579 #define DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL 0x09090909
11580 #define DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT 0
11581 #define DDR_PHY_DX3GCR5_DXREFISELR0_MASK 0x0000007FU
11583 /*Reserved. Returns zeros on reads.*/
11584 #undef DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL
11585 #undef DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT
11586 #undef DDR_PHY_DX3GCR6_RESERVED_31_30_MASK
11587 #define DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL 0x09090909
11588 #define DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT 30
11589 #define DDR_PHY_DX3GCR6_RESERVED_31_30_MASK 0xC0000000U
11591 /*DRAM DQ VREF Select for Rank3*/
11592 #undef DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL
11593 #undef DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT
11594 #undef DDR_PHY_DX3GCR6_DXDQVREFR3_MASK
11595 #define DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL 0x09090909
11596 #define DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT 24
11597 #define DDR_PHY_DX3GCR6_DXDQVREFR3_MASK 0x3F000000U
11599 /*Reserved. Returns zeros on reads.*/
11600 #undef DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL
11601 #undef DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT
11602 #undef DDR_PHY_DX3GCR6_RESERVED_23_22_MASK
11603 #define DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL 0x09090909
11604 #define DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT 22
11605 #define DDR_PHY_DX3GCR6_RESERVED_23_22_MASK 0x00C00000U
11607 /*DRAM DQ VREF Select for Rank2*/
11608 #undef DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL
11609 #undef DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT
11610 #undef DDR_PHY_DX3GCR6_DXDQVREFR2_MASK
11611 #define DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL 0x09090909
11612 #define DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT 16
11613 #define DDR_PHY_DX3GCR6_DXDQVREFR2_MASK 0x003F0000U
11615 /*Reserved. Returns zeros on reads.*/
11616 #undef DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL
11617 #undef DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT
11618 #undef DDR_PHY_DX3GCR6_RESERVED_15_14_MASK
11619 #define DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL 0x09090909
11620 #define DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT 14
11621 #define DDR_PHY_DX3GCR6_RESERVED_15_14_MASK 0x0000C000U
11623 /*DRAM DQ VREF Select for Rank1*/
11624 #undef DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL
11625 #undef DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT
11626 #undef DDR_PHY_DX3GCR6_DXDQVREFR1_MASK
11627 #define DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL 0x09090909
11628 #define DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT 8
11629 #define DDR_PHY_DX3GCR6_DXDQVREFR1_MASK 0x00003F00U
11631 /*Reserved. Returns zeros on reads.*/
11632 #undef DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL
11633 #undef DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT
11634 #undef DDR_PHY_DX3GCR6_RESERVED_7_6_MASK
11635 #define DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL 0x09090909
11636 #define DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT 6
11637 #define DDR_PHY_DX3GCR6_RESERVED_7_6_MASK 0x000000C0U
11639 /*DRAM DQ VREF Select for Rank0*/
11640 #undef DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL
11641 #undef DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT
11642 #undef DDR_PHY_DX3GCR6_DXDQVREFR0_MASK
11643 #define DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL 0x09090909
11644 #define DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT 0
11645 #define DDR_PHY_DX3GCR6_DXDQVREFR0_MASK 0x0000003FU
11647 /*Reserved. Return zeroes on reads.*/
11648 #undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_DEFVAL
11649 #undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT
11650 #undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK
11651 #define DDR_PHY_DX3LCDLR2_RESERVED_31_25_DEFVAL 0x00000000
11652 #define DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT 25
11653 #define DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK 0xFE000000U
11655 /*Reserved. Caution, do not write to this register field.*/
11656 #undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_DEFVAL
11657 #undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT
11658 #undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK
11659 #define DDR_PHY_DX3LCDLR2_RESERVED_24_16_DEFVAL 0x00000000
11660 #define DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT 16
11661 #define DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK 0x01FF0000U
11663 /*Reserved. Return zeroes on reads.*/
11664 #undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_DEFVAL
11665 #undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT
11666 #undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK
11667 #define DDR_PHY_DX3LCDLR2_RESERVED_15_9_DEFVAL 0x00000000
11668 #define DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT 9
11669 #define DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK 0x0000FE00U
11671 /*Read DQS Gating Delay*/
11672 #undef DDR_PHY_DX3LCDLR2_DQSGD_DEFVAL
11673 #undef DDR_PHY_DX3LCDLR2_DQSGD_SHIFT
11674 #undef DDR_PHY_DX3LCDLR2_DQSGD_MASK
11675 #define DDR_PHY_DX3LCDLR2_DQSGD_DEFVAL 0x00000000
11676 #define DDR_PHY_DX3LCDLR2_DQSGD_SHIFT 0
11677 #define DDR_PHY_DX3LCDLR2_DQSGD_MASK 0x000001FFU
11679 /*Reserved. Return zeroes on reads.*/
11680 #undef DDR_PHY_DX3GTR0_RESERVED_31_24_DEFVAL
11681 #undef DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT
11682 #undef DDR_PHY_DX3GTR0_RESERVED_31_24_MASK
11683 #define DDR_PHY_DX3GTR0_RESERVED_31_24_DEFVAL 0x00020000
11684 #define DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT 27
11685 #define DDR_PHY_DX3GTR0_RESERVED_31_24_MASK 0xF8000000U
11687 /*DQ Write Path Latency Pipeline*/
11688 #undef DDR_PHY_DX3GTR0_WDQSL_DEFVAL
11689 #undef DDR_PHY_DX3GTR0_WDQSL_SHIFT
11690 #undef DDR_PHY_DX3GTR0_WDQSL_MASK
11691 #define DDR_PHY_DX3GTR0_WDQSL_DEFVAL 0x00020000
11692 #define DDR_PHY_DX3GTR0_WDQSL_SHIFT 24
11693 #define DDR_PHY_DX3GTR0_WDQSL_MASK 0x07000000U
11695 /*Reserved. Caution, do not write to this register field.*/
11696 #undef DDR_PHY_DX3GTR0_RESERVED_23_20_DEFVAL
11697 #undef DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT
11698 #undef DDR_PHY_DX3GTR0_RESERVED_23_20_MASK
11699 #define DDR_PHY_DX3GTR0_RESERVED_23_20_DEFVAL 0x00020000
11700 #define DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT 20
11701 #define DDR_PHY_DX3GTR0_RESERVED_23_20_MASK 0x00F00000U
11703 /*Write Leveling System Latency*/
11704 #undef DDR_PHY_DX3GTR0_WLSL_DEFVAL
11705 #undef DDR_PHY_DX3GTR0_WLSL_SHIFT
11706 #undef DDR_PHY_DX3GTR0_WLSL_MASK
11707 #define DDR_PHY_DX3GTR0_WLSL_DEFVAL 0x00020000
11708 #define DDR_PHY_DX3GTR0_WLSL_SHIFT 16
11709 #define DDR_PHY_DX3GTR0_WLSL_MASK 0x000F0000U
11711 /*Reserved. Return zeroes on reads.*/
11712 #undef DDR_PHY_DX3GTR0_RESERVED_15_13_DEFVAL
11713 #undef DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT
11714 #undef DDR_PHY_DX3GTR0_RESERVED_15_13_MASK
11715 #define DDR_PHY_DX3GTR0_RESERVED_15_13_DEFVAL 0x00020000
11716 #define DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT 13
11717 #define DDR_PHY_DX3GTR0_RESERVED_15_13_MASK 0x0000E000U
11719 /*Reserved. Caution, do not write to this register field.*/
11720 #undef DDR_PHY_DX3GTR0_RESERVED_12_8_DEFVAL
11721 #undef DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT
11722 #undef DDR_PHY_DX3GTR0_RESERVED_12_8_MASK
11723 #define DDR_PHY_DX3GTR0_RESERVED_12_8_DEFVAL 0x00020000
11724 #define DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT 8
11725 #define DDR_PHY_DX3GTR0_RESERVED_12_8_MASK 0x00001F00U
11727 /*Reserved. Return zeroes on reads.*/
11728 #undef DDR_PHY_DX3GTR0_RESERVED_7_5_DEFVAL
11729 #undef DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT
11730 #undef DDR_PHY_DX3GTR0_RESERVED_7_5_MASK
11731 #define DDR_PHY_DX3GTR0_RESERVED_7_5_DEFVAL 0x00020000
11732 #define DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT 5
11733 #define DDR_PHY_DX3GTR0_RESERVED_7_5_MASK 0x000000E0U
11735 /*DQS Gating System Latency*/
11736 #undef DDR_PHY_DX3GTR0_DGSL_DEFVAL
11737 #undef DDR_PHY_DX3GTR0_DGSL_SHIFT
11738 #undef DDR_PHY_DX3GTR0_DGSL_MASK
11739 #define DDR_PHY_DX3GTR0_DGSL_DEFVAL 0x00020000
11740 #define DDR_PHY_DX3GTR0_DGSL_SHIFT 0
11741 #define DDR_PHY_DX3GTR0_DGSL_MASK 0x0000001FU
11743 /*Calibration Bypass*/
11744 #undef DDR_PHY_DX4GCR0_CALBYP_DEFVAL
11745 #undef DDR_PHY_DX4GCR0_CALBYP_SHIFT
11746 #undef DDR_PHY_DX4GCR0_CALBYP_MASK
11747 #define DDR_PHY_DX4GCR0_CALBYP_DEFVAL 0x40200204
11748 #define DDR_PHY_DX4GCR0_CALBYP_SHIFT 31
11749 #define DDR_PHY_DX4GCR0_CALBYP_MASK 0x80000000U
11751 /*Master Delay Line Enable*/
11752 #undef DDR_PHY_DX4GCR0_MDLEN_DEFVAL
11753 #undef DDR_PHY_DX4GCR0_MDLEN_SHIFT
11754 #undef DDR_PHY_DX4GCR0_MDLEN_MASK
11755 #define DDR_PHY_DX4GCR0_MDLEN_DEFVAL 0x40200204
11756 #define DDR_PHY_DX4GCR0_MDLEN_SHIFT 30
11757 #define DDR_PHY_DX4GCR0_MDLEN_MASK 0x40000000U
11759 /*Configurable ODT(TE) Phase Shift*/
11760 #undef DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL
11761 #undef DDR_PHY_DX4GCR0_CODTSHFT_SHIFT
11762 #undef DDR_PHY_DX4GCR0_CODTSHFT_MASK
11763 #define DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL 0x40200204
11764 #define DDR_PHY_DX4GCR0_CODTSHFT_SHIFT 28
11765 #define DDR_PHY_DX4GCR0_CODTSHFT_MASK 0x30000000U
11767 /*DQS Duty Cycle Correction*/
11768 #undef DDR_PHY_DX4GCR0_DQSDCC_DEFVAL
11769 #undef DDR_PHY_DX4GCR0_DQSDCC_SHIFT
11770 #undef DDR_PHY_DX4GCR0_DQSDCC_MASK
11771 #define DDR_PHY_DX4GCR0_DQSDCC_DEFVAL 0x40200204
11772 #define DDR_PHY_DX4GCR0_DQSDCC_SHIFT 24
11773 #define DDR_PHY_DX4GCR0_DQSDCC_MASK 0x0F000000U
11775 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
11776 #undef DDR_PHY_DX4GCR0_RDDLY_DEFVAL
11777 #undef DDR_PHY_DX4GCR0_RDDLY_SHIFT
11778 #undef DDR_PHY_DX4GCR0_RDDLY_MASK
11779 #define DDR_PHY_DX4GCR0_RDDLY_DEFVAL 0x40200204
11780 #define DDR_PHY_DX4GCR0_RDDLY_SHIFT 20
11781 #define DDR_PHY_DX4GCR0_RDDLY_MASK 0x00F00000U
11783 /*Reserved. Return zeroes on reads.*/
11784 #undef DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL
11785 #undef DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT
11786 #undef DDR_PHY_DX4GCR0_RESERVED_19_14_MASK
11787 #define DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL 0x40200204
11788 #define DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT 14
11789 #define DDR_PHY_DX4GCR0_RESERVED_19_14_MASK 0x000FC000U
11791 /*DQSNSE Power Down Receiver*/
11792 #undef DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL
11793 #undef DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT
11794 #undef DDR_PHY_DX4GCR0_DQSNSEPDR_MASK
11795 #define DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL 0x40200204
11796 #define DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT 13
11797 #define DDR_PHY_DX4GCR0_DQSNSEPDR_MASK 0x00002000U
11799 /*DQSSE Power Down Receiver*/
11800 #undef DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL
11801 #undef DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT
11802 #undef DDR_PHY_DX4GCR0_DQSSEPDR_MASK
11803 #define DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL 0x40200204
11804 #define DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT 12
11805 #define DDR_PHY_DX4GCR0_DQSSEPDR_MASK 0x00001000U
11807 /*RTT On Additive Latency*/
11808 #undef DDR_PHY_DX4GCR0_RTTOAL_DEFVAL
11809 #undef DDR_PHY_DX4GCR0_RTTOAL_SHIFT
11810 #undef DDR_PHY_DX4GCR0_RTTOAL_MASK
11811 #define DDR_PHY_DX4GCR0_RTTOAL_DEFVAL 0x40200204
11812 #define DDR_PHY_DX4GCR0_RTTOAL_SHIFT 11
11813 #define DDR_PHY_DX4GCR0_RTTOAL_MASK 0x00000800U
11815 /*RTT Output Hold*/
11816 #undef DDR_PHY_DX4GCR0_RTTOH_DEFVAL
11817 #undef DDR_PHY_DX4GCR0_RTTOH_SHIFT
11818 #undef DDR_PHY_DX4GCR0_RTTOH_MASK
11819 #define DDR_PHY_DX4GCR0_RTTOH_DEFVAL 0x40200204
11820 #define DDR_PHY_DX4GCR0_RTTOH_SHIFT 9
11821 #define DDR_PHY_DX4GCR0_RTTOH_MASK 0x00000600U
11823 /*Configurable PDR Phase Shift*/
11824 #undef DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL
11825 #undef DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT
11826 #undef DDR_PHY_DX4GCR0_CPDRSHFT_MASK
11827 #define DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL 0x40200204
11828 #define DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT 7
11829 #define DDR_PHY_DX4GCR0_CPDRSHFT_MASK 0x00000180U
11831 /*DQSR Power Down*/
11832 #undef DDR_PHY_DX4GCR0_DQSRPD_DEFVAL
11833 #undef DDR_PHY_DX4GCR0_DQSRPD_SHIFT
11834 #undef DDR_PHY_DX4GCR0_DQSRPD_MASK
11835 #define DDR_PHY_DX4GCR0_DQSRPD_DEFVAL 0x40200204
11836 #define DDR_PHY_DX4GCR0_DQSRPD_SHIFT 6
11837 #define DDR_PHY_DX4GCR0_DQSRPD_MASK 0x00000040U
11839 /*DQSG Power Down Receiver*/
11840 #undef DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL
11841 #undef DDR_PHY_DX4GCR0_DQSGPDR_SHIFT
11842 #undef DDR_PHY_DX4GCR0_DQSGPDR_MASK
11843 #define DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL 0x40200204
11844 #define DDR_PHY_DX4GCR0_DQSGPDR_SHIFT 5
11845 #define DDR_PHY_DX4GCR0_DQSGPDR_MASK 0x00000020U
11847 /*Reserved. Return zeroes on reads.*/
11848 #undef DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL
11849 #undef DDR_PHY_DX4GCR0_RESERVED_4_SHIFT
11850 #undef DDR_PHY_DX4GCR0_RESERVED_4_MASK
11851 #define DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL 0x40200204
11852 #define DDR_PHY_DX4GCR0_RESERVED_4_SHIFT 4
11853 #define DDR_PHY_DX4GCR0_RESERVED_4_MASK 0x00000010U
11855 /*DQSG On-Die Termination*/
11856 #undef DDR_PHY_DX4GCR0_DQSGODT_DEFVAL
11857 #undef DDR_PHY_DX4GCR0_DQSGODT_SHIFT
11858 #undef DDR_PHY_DX4GCR0_DQSGODT_MASK
11859 #define DDR_PHY_DX4GCR0_DQSGODT_DEFVAL 0x40200204
11860 #define DDR_PHY_DX4GCR0_DQSGODT_SHIFT 3
11861 #define DDR_PHY_DX4GCR0_DQSGODT_MASK 0x00000008U
11863 /*DQSG Output Enable*/
11864 #undef DDR_PHY_DX4GCR0_DQSGOE_DEFVAL
11865 #undef DDR_PHY_DX4GCR0_DQSGOE_SHIFT
11866 #undef DDR_PHY_DX4GCR0_DQSGOE_MASK
11867 #define DDR_PHY_DX4GCR0_DQSGOE_DEFVAL 0x40200204
11868 #define DDR_PHY_DX4GCR0_DQSGOE_SHIFT 2
11869 #define DDR_PHY_DX4GCR0_DQSGOE_MASK 0x00000004U
11871 /*Reserved. Return zeroes on reads.*/
11872 #undef DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL
11873 #undef DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT
11874 #undef DDR_PHY_DX4GCR0_RESERVED_1_0_MASK
11875 #define DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL 0x40200204
11876 #define DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT 0
11877 #define DDR_PHY_DX4GCR0_RESERVED_1_0_MASK 0x00000003U
11879 /*Enables the PDR mode for DQ[7:0]*/
11880 #undef DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL
11881 #undef DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT
11882 #undef DDR_PHY_DX4GCR1_DXPDRMODE_MASK
11883 #define DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL 0x00007FFF
11884 #define DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT 16
11885 #define DDR_PHY_DX4GCR1_DXPDRMODE_MASK 0xFFFF0000U
11887 /*Reserved. Returns zeroes on reads.*/
11888 #undef DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL
11889 #undef DDR_PHY_DX4GCR1_RESERVED_15_SHIFT
11890 #undef DDR_PHY_DX4GCR1_RESERVED_15_MASK
11891 #define DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL 0x00007FFF
11892 #define DDR_PHY_DX4GCR1_RESERVED_15_SHIFT 15
11893 #define DDR_PHY_DX4GCR1_RESERVED_15_MASK 0x00008000U
11895 /*Select the delayed or non-delayed read data strobe #*/
11896 #undef DDR_PHY_DX4GCR1_QSNSEL_DEFVAL
11897 #undef DDR_PHY_DX4GCR1_QSNSEL_SHIFT
11898 #undef DDR_PHY_DX4GCR1_QSNSEL_MASK
11899 #define DDR_PHY_DX4GCR1_QSNSEL_DEFVAL 0x00007FFF
11900 #define DDR_PHY_DX4GCR1_QSNSEL_SHIFT 14
11901 #define DDR_PHY_DX4GCR1_QSNSEL_MASK 0x00004000U
11903 /*Select the delayed or non-delayed read data strobe*/
11904 #undef DDR_PHY_DX4GCR1_QSSEL_DEFVAL
11905 #undef DDR_PHY_DX4GCR1_QSSEL_SHIFT
11906 #undef DDR_PHY_DX4GCR1_QSSEL_MASK
11907 #define DDR_PHY_DX4GCR1_QSSEL_DEFVAL 0x00007FFF
11908 #define DDR_PHY_DX4GCR1_QSSEL_SHIFT 13
11909 #define DDR_PHY_DX4GCR1_QSSEL_MASK 0x00002000U
11911 /*Enables Read Data Strobe in a byte lane*/
11912 #undef DDR_PHY_DX4GCR1_OEEN_DEFVAL
11913 #undef DDR_PHY_DX4GCR1_OEEN_SHIFT
11914 #undef DDR_PHY_DX4GCR1_OEEN_MASK
11915 #define DDR_PHY_DX4GCR1_OEEN_DEFVAL 0x00007FFF
11916 #define DDR_PHY_DX4GCR1_OEEN_SHIFT 12
11917 #define DDR_PHY_DX4GCR1_OEEN_MASK 0x00001000U
11919 /*Enables PDR in a byte lane*/
11920 #undef DDR_PHY_DX4GCR1_PDREN_DEFVAL
11921 #undef DDR_PHY_DX4GCR1_PDREN_SHIFT
11922 #undef DDR_PHY_DX4GCR1_PDREN_MASK
11923 #define DDR_PHY_DX4GCR1_PDREN_DEFVAL 0x00007FFF
11924 #define DDR_PHY_DX4GCR1_PDREN_SHIFT 11
11925 #define DDR_PHY_DX4GCR1_PDREN_MASK 0x00000800U
11927 /*Enables ODT/TE in a byte lane*/
11928 #undef DDR_PHY_DX4GCR1_TEEN_DEFVAL
11929 #undef DDR_PHY_DX4GCR1_TEEN_SHIFT
11930 #undef DDR_PHY_DX4GCR1_TEEN_MASK
11931 #define DDR_PHY_DX4GCR1_TEEN_DEFVAL 0x00007FFF
11932 #define DDR_PHY_DX4GCR1_TEEN_SHIFT 10
11933 #define DDR_PHY_DX4GCR1_TEEN_MASK 0x00000400U
11935 /*Enables Write Data strobe in a byte lane*/
11936 #undef DDR_PHY_DX4GCR1_DSEN_DEFVAL
11937 #undef DDR_PHY_DX4GCR1_DSEN_SHIFT
11938 #undef DDR_PHY_DX4GCR1_DSEN_MASK
11939 #define DDR_PHY_DX4GCR1_DSEN_DEFVAL 0x00007FFF
11940 #define DDR_PHY_DX4GCR1_DSEN_SHIFT 9
11941 #define DDR_PHY_DX4GCR1_DSEN_MASK 0x00000200U
11943 /*Enables DM pin in a byte lane*/
11944 #undef DDR_PHY_DX4GCR1_DMEN_DEFVAL
11945 #undef DDR_PHY_DX4GCR1_DMEN_SHIFT
11946 #undef DDR_PHY_DX4GCR1_DMEN_MASK
11947 #define DDR_PHY_DX4GCR1_DMEN_DEFVAL 0x00007FFF
11948 #define DDR_PHY_DX4GCR1_DMEN_SHIFT 8
11949 #define DDR_PHY_DX4GCR1_DMEN_MASK 0x00000100U
11951 /*Enables DQ corresponding to each bit in a byte*/
11952 #undef DDR_PHY_DX4GCR1_DQEN_DEFVAL
11953 #undef DDR_PHY_DX4GCR1_DQEN_SHIFT
11954 #undef DDR_PHY_DX4GCR1_DQEN_MASK
11955 #define DDR_PHY_DX4GCR1_DQEN_DEFVAL 0x00007FFF
11956 #define DDR_PHY_DX4GCR1_DQEN_SHIFT 0
11957 #define DDR_PHY_DX4GCR1_DQEN_MASK 0x000000FFU
11959 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
11960 #undef DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL
11961 #undef DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT
11962 #undef DDR_PHY_DX4GCR4_RESERVED_31_29_MASK
11963 #define DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL 0x0E00003C
11964 #define DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT 29
11965 #define DDR_PHY_DX4GCR4_RESERVED_31_29_MASK 0xE0000000U
11967 /*Byte Lane VREF Pad Enable*/
11968 #undef DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL
11969 #undef DDR_PHY_DX4GCR4_DXREFPEN_SHIFT
11970 #undef DDR_PHY_DX4GCR4_DXREFPEN_MASK
11971 #define DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL 0x0E00003C
11972 #define DDR_PHY_DX4GCR4_DXREFPEN_SHIFT 28
11973 #define DDR_PHY_DX4GCR4_DXREFPEN_MASK 0x10000000U
11975 /*Byte Lane Internal VREF Enable*/
11976 #undef DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL
11977 #undef DDR_PHY_DX4GCR4_DXREFEEN_SHIFT
11978 #undef DDR_PHY_DX4GCR4_DXREFEEN_MASK
11979 #define DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL 0x0E00003C
11980 #define DDR_PHY_DX4GCR4_DXREFEEN_SHIFT 26
11981 #define DDR_PHY_DX4GCR4_DXREFEEN_MASK 0x0C000000U
11983 /*Byte Lane Single-End VREF Enable*/
11984 #undef DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL
11985 #undef DDR_PHY_DX4GCR4_DXREFSEN_SHIFT
11986 #undef DDR_PHY_DX4GCR4_DXREFSEN_MASK
11987 #define DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL 0x0E00003C
11988 #define DDR_PHY_DX4GCR4_DXREFSEN_SHIFT 25
11989 #define DDR_PHY_DX4GCR4_DXREFSEN_MASK 0x02000000U
11991 /*Reserved. Returns zeros on reads.*/
11992 #undef DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL
11993 #undef DDR_PHY_DX4GCR4_RESERVED_24_SHIFT
11994 #undef DDR_PHY_DX4GCR4_RESERVED_24_MASK
11995 #define DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL 0x0E00003C
11996 #define DDR_PHY_DX4GCR4_RESERVED_24_SHIFT 24
11997 #define DDR_PHY_DX4GCR4_RESERVED_24_MASK 0x01000000U
11999 /*External VREF generator REFSEL range select*/
12000 #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL
12001 #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT
12002 #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK
12003 #define DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C
12004 #define DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT 23
12005 #define DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK 0x00800000U
12007 /*Byte Lane External VREF Select*/
12008 #undef DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL
12009 #undef DDR_PHY_DX4GCR4_DXREFESEL_SHIFT
12010 #undef DDR_PHY_DX4GCR4_DXREFESEL_MASK
12011 #define DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL 0x0E00003C
12012 #define DDR_PHY_DX4GCR4_DXREFESEL_SHIFT 16
12013 #define DDR_PHY_DX4GCR4_DXREFESEL_MASK 0x007F0000U
12015 /*Single ended VREF generator REFSEL range select*/
12016 #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL
12017 #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT
12018 #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK
12019 #define DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C
12020 #define DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT 15
12021 #define DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK 0x00008000U
12023 /*Byte Lane Single-End VREF Select*/
12024 #undef DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL
12025 #undef DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT
12026 #undef DDR_PHY_DX4GCR4_DXREFSSEL_MASK
12027 #define DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL 0x0E00003C
12028 #define DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT 8
12029 #define DDR_PHY_DX4GCR4_DXREFSSEL_MASK 0x00007F00U
12031 /*Reserved. Returns zeros on reads.*/
12032 #undef DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL
12033 #undef DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT
12034 #undef DDR_PHY_DX4GCR4_RESERVED_7_6_MASK
12035 #define DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL 0x0E00003C
12036 #define DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT 6
12037 #define DDR_PHY_DX4GCR4_RESERVED_7_6_MASK 0x000000C0U
12039 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
12040 #undef DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL
12041 #undef DDR_PHY_DX4GCR4_DXREFIEN_SHIFT
12042 #undef DDR_PHY_DX4GCR4_DXREFIEN_MASK
12043 #define DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL 0x0E00003C
12044 #define DDR_PHY_DX4GCR4_DXREFIEN_SHIFT 2
12045 #define DDR_PHY_DX4GCR4_DXREFIEN_MASK 0x0000003CU
12047 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
12048 #undef DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL
12049 #undef DDR_PHY_DX4GCR4_DXREFIMON_SHIFT
12050 #undef DDR_PHY_DX4GCR4_DXREFIMON_MASK
12051 #define DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL 0x0E00003C
12052 #define DDR_PHY_DX4GCR4_DXREFIMON_SHIFT 0
12053 #define DDR_PHY_DX4GCR4_DXREFIMON_MASK 0x00000003U
12055 /*Reserved. Returns zeros on reads.*/
12056 #undef DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL
12057 #undef DDR_PHY_DX4GCR5_RESERVED_31_SHIFT
12058 #undef DDR_PHY_DX4GCR5_RESERVED_31_MASK
12059 #define DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL 0x09090909
12060 #define DDR_PHY_DX4GCR5_RESERVED_31_SHIFT 31
12061 #define DDR_PHY_DX4GCR5_RESERVED_31_MASK 0x80000000U
12063 /*Byte Lane internal VREF Select for Rank 3*/
12064 #undef DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL
12065 #undef DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT
12066 #undef DDR_PHY_DX4GCR5_DXREFISELR3_MASK
12067 #define DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL 0x09090909
12068 #define DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT 24
12069 #define DDR_PHY_DX4GCR5_DXREFISELR3_MASK 0x7F000000U
12071 /*Reserved. Returns zeros on reads.*/
12072 #undef DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL
12073 #undef DDR_PHY_DX4GCR5_RESERVED_23_SHIFT
12074 #undef DDR_PHY_DX4GCR5_RESERVED_23_MASK
12075 #define DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL 0x09090909
12076 #define DDR_PHY_DX4GCR5_RESERVED_23_SHIFT 23
12077 #define DDR_PHY_DX4GCR5_RESERVED_23_MASK 0x00800000U
12079 /*Byte Lane internal VREF Select for Rank 2*/
12080 #undef DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL
12081 #undef DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT
12082 #undef DDR_PHY_DX4GCR5_DXREFISELR2_MASK
12083 #define DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL 0x09090909
12084 #define DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT 16
12085 #define DDR_PHY_DX4GCR5_DXREFISELR2_MASK 0x007F0000U
12087 /*Reserved. Returns zeros on reads.*/
12088 #undef DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL
12089 #undef DDR_PHY_DX4GCR5_RESERVED_15_SHIFT
12090 #undef DDR_PHY_DX4GCR5_RESERVED_15_MASK
12091 #define DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL 0x09090909
12092 #define DDR_PHY_DX4GCR5_RESERVED_15_SHIFT 15
12093 #define DDR_PHY_DX4GCR5_RESERVED_15_MASK 0x00008000U
12095 /*Byte Lane internal VREF Select for Rank 1*/
12096 #undef DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL
12097 #undef DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT
12098 #undef DDR_PHY_DX4GCR5_DXREFISELR1_MASK
12099 #define DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL 0x09090909
12100 #define DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT 8
12101 #define DDR_PHY_DX4GCR5_DXREFISELR1_MASK 0x00007F00U
12103 /*Reserved. Returns zeros on reads.*/
12104 #undef DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL
12105 #undef DDR_PHY_DX4GCR5_RESERVED_7_SHIFT
12106 #undef DDR_PHY_DX4GCR5_RESERVED_7_MASK
12107 #define DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL 0x09090909
12108 #define DDR_PHY_DX4GCR5_RESERVED_7_SHIFT 7
12109 #define DDR_PHY_DX4GCR5_RESERVED_7_MASK 0x00000080U
12111 /*Byte Lane internal VREF Select for Rank 0*/
12112 #undef DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL
12113 #undef DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT
12114 #undef DDR_PHY_DX4GCR5_DXREFISELR0_MASK
12115 #define DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL 0x09090909
12116 #define DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT 0
12117 #define DDR_PHY_DX4GCR5_DXREFISELR0_MASK 0x0000007FU
12119 /*Reserved. Returns zeros on reads.*/
12120 #undef DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL
12121 #undef DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT
12122 #undef DDR_PHY_DX4GCR6_RESERVED_31_30_MASK
12123 #define DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL 0x09090909
12124 #define DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT 30
12125 #define DDR_PHY_DX4GCR6_RESERVED_31_30_MASK 0xC0000000U
12127 /*DRAM DQ VREF Select for Rank3*/
12128 #undef DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL
12129 #undef DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT
12130 #undef DDR_PHY_DX4GCR6_DXDQVREFR3_MASK
12131 #define DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL 0x09090909
12132 #define DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT 24
12133 #define DDR_PHY_DX4GCR6_DXDQVREFR3_MASK 0x3F000000U
12135 /*Reserved. Returns zeros on reads.*/
12136 #undef DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL
12137 #undef DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT
12138 #undef DDR_PHY_DX4GCR6_RESERVED_23_22_MASK
12139 #define DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL 0x09090909
12140 #define DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT 22
12141 #define DDR_PHY_DX4GCR6_RESERVED_23_22_MASK 0x00C00000U
12143 /*DRAM DQ VREF Select for Rank2*/
12144 #undef DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL
12145 #undef DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT
12146 #undef DDR_PHY_DX4GCR6_DXDQVREFR2_MASK
12147 #define DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL 0x09090909
12148 #define DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT 16
12149 #define DDR_PHY_DX4GCR6_DXDQVREFR2_MASK 0x003F0000U
12151 /*Reserved. Returns zeros on reads.*/
12152 #undef DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL
12153 #undef DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT
12154 #undef DDR_PHY_DX4GCR6_RESERVED_15_14_MASK
12155 #define DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL 0x09090909
12156 #define DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT 14
12157 #define DDR_PHY_DX4GCR6_RESERVED_15_14_MASK 0x0000C000U
12159 /*DRAM DQ VREF Select for Rank1*/
12160 #undef DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL
12161 #undef DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT
12162 #undef DDR_PHY_DX4GCR6_DXDQVREFR1_MASK
12163 #define DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL 0x09090909
12164 #define DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT 8
12165 #define DDR_PHY_DX4GCR6_DXDQVREFR1_MASK 0x00003F00U
12167 /*Reserved. Returns zeros on reads.*/
12168 #undef DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL
12169 #undef DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT
12170 #undef DDR_PHY_DX4GCR6_RESERVED_7_6_MASK
12171 #define DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL 0x09090909
12172 #define DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT 6
12173 #define DDR_PHY_DX4GCR6_RESERVED_7_6_MASK 0x000000C0U
12175 /*DRAM DQ VREF Select for Rank0*/
12176 #undef DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL
12177 #undef DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT
12178 #undef DDR_PHY_DX4GCR6_DXDQVREFR0_MASK
12179 #define DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL 0x09090909
12180 #define DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT 0
12181 #define DDR_PHY_DX4GCR6_DXDQVREFR0_MASK 0x0000003FU
12183 /*Reserved. Return zeroes on reads.*/
12184 #undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_DEFVAL
12185 #undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT
12186 #undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK
12187 #define DDR_PHY_DX4LCDLR2_RESERVED_31_25_DEFVAL 0x00000000
12188 #define DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT 25
12189 #define DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK 0xFE000000U
12191 /*Reserved. Caution, do not write to this register field.*/
12192 #undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_DEFVAL
12193 #undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT
12194 #undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK
12195 #define DDR_PHY_DX4LCDLR2_RESERVED_24_16_DEFVAL 0x00000000
12196 #define DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT 16
12197 #define DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK 0x01FF0000U
12199 /*Reserved. Return zeroes on reads.*/
12200 #undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_DEFVAL
12201 #undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT
12202 #undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK
12203 #define DDR_PHY_DX4LCDLR2_RESERVED_15_9_DEFVAL 0x00000000
12204 #define DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT 9
12205 #define DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK 0x0000FE00U
12207 /*Read DQS Gating Delay*/
12208 #undef DDR_PHY_DX4LCDLR2_DQSGD_DEFVAL
12209 #undef DDR_PHY_DX4LCDLR2_DQSGD_SHIFT
12210 #undef DDR_PHY_DX4LCDLR2_DQSGD_MASK
12211 #define DDR_PHY_DX4LCDLR2_DQSGD_DEFVAL 0x00000000
12212 #define DDR_PHY_DX4LCDLR2_DQSGD_SHIFT 0
12213 #define DDR_PHY_DX4LCDLR2_DQSGD_MASK 0x000001FFU
12215 /*Reserved. Return zeroes on reads.*/
12216 #undef DDR_PHY_DX4GTR0_RESERVED_31_24_DEFVAL
12217 #undef DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT
12218 #undef DDR_PHY_DX4GTR0_RESERVED_31_24_MASK
12219 #define DDR_PHY_DX4GTR0_RESERVED_31_24_DEFVAL 0x00020000
12220 #define DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT 27
12221 #define DDR_PHY_DX4GTR0_RESERVED_31_24_MASK 0xF8000000U
12223 /*DQ Write Path Latency Pipeline*/
12224 #undef DDR_PHY_DX4GTR0_WDQSL_DEFVAL
12225 #undef DDR_PHY_DX4GTR0_WDQSL_SHIFT
12226 #undef DDR_PHY_DX4GTR0_WDQSL_MASK
12227 #define DDR_PHY_DX4GTR0_WDQSL_DEFVAL 0x00020000
12228 #define DDR_PHY_DX4GTR0_WDQSL_SHIFT 24
12229 #define DDR_PHY_DX4GTR0_WDQSL_MASK 0x07000000U
12231 /*Reserved. Caution, do not write to this register field.*/
12232 #undef DDR_PHY_DX4GTR0_RESERVED_23_20_DEFVAL
12233 #undef DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT
12234 #undef DDR_PHY_DX4GTR0_RESERVED_23_20_MASK
12235 #define DDR_PHY_DX4GTR0_RESERVED_23_20_DEFVAL 0x00020000
12236 #define DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT 20
12237 #define DDR_PHY_DX4GTR0_RESERVED_23_20_MASK 0x00F00000U
12239 /*Write Leveling System Latency*/
12240 #undef DDR_PHY_DX4GTR0_WLSL_DEFVAL
12241 #undef DDR_PHY_DX4GTR0_WLSL_SHIFT
12242 #undef DDR_PHY_DX4GTR0_WLSL_MASK
12243 #define DDR_PHY_DX4GTR0_WLSL_DEFVAL 0x00020000
12244 #define DDR_PHY_DX4GTR0_WLSL_SHIFT 16
12245 #define DDR_PHY_DX4GTR0_WLSL_MASK 0x000F0000U
12247 /*Reserved. Return zeroes on reads.*/
12248 #undef DDR_PHY_DX4GTR0_RESERVED_15_13_DEFVAL
12249 #undef DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT
12250 #undef DDR_PHY_DX4GTR0_RESERVED_15_13_MASK
12251 #define DDR_PHY_DX4GTR0_RESERVED_15_13_DEFVAL 0x00020000
12252 #define DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT 13
12253 #define DDR_PHY_DX4GTR0_RESERVED_15_13_MASK 0x0000E000U
12255 /*Reserved. Caution, do not write to this register field.*/
12256 #undef DDR_PHY_DX4GTR0_RESERVED_12_8_DEFVAL
12257 #undef DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT
12258 #undef DDR_PHY_DX4GTR0_RESERVED_12_8_MASK
12259 #define DDR_PHY_DX4GTR0_RESERVED_12_8_DEFVAL 0x00020000
12260 #define DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT 8
12261 #define DDR_PHY_DX4GTR0_RESERVED_12_8_MASK 0x00001F00U
12263 /*Reserved. Return zeroes on reads.*/
12264 #undef DDR_PHY_DX4GTR0_RESERVED_7_5_DEFVAL
12265 #undef DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT
12266 #undef DDR_PHY_DX4GTR0_RESERVED_7_5_MASK
12267 #define DDR_PHY_DX4GTR0_RESERVED_7_5_DEFVAL 0x00020000
12268 #define DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT 5
12269 #define DDR_PHY_DX4GTR0_RESERVED_7_5_MASK 0x000000E0U
12271 /*DQS Gating System Latency*/
12272 #undef DDR_PHY_DX4GTR0_DGSL_DEFVAL
12273 #undef DDR_PHY_DX4GTR0_DGSL_SHIFT
12274 #undef DDR_PHY_DX4GTR0_DGSL_MASK
12275 #define DDR_PHY_DX4GTR0_DGSL_DEFVAL 0x00020000
12276 #define DDR_PHY_DX4GTR0_DGSL_SHIFT 0
12277 #define DDR_PHY_DX4GTR0_DGSL_MASK 0x0000001FU
12279 /*Calibration Bypass*/
12280 #undef DDR_PHY_DX5GCR0_CALBYP_DEFVAL
12281 #undef DDR_PHY_DX5GCR0_CALBYP_SHIFT
12282 #undef DDR_PHY_DX5GCR0_CALBYP_MASK
12283 #define DDR_PHY_DX5GCR0_CALBYP_DEFVAL 0x40200204
12284 #define DDR_PHY_DX5GCR0_CALBYP_SHIFT 31
12285 #define DDR_PHY_DX5GCR0_CALBYP_MASK 0x80000000U
12287 /*Master Delay Line Enable*/
12288 #undef DDR_PHY_DX5GCR0_MDLEN_DEFVAL
12289 #undef DDR_PHY_DX5GCR0_MDLEN_SHIFT
12290 #undef DDR_PHY_DX5GCR0_MDLEN_MASK
12291 #define DDR_PHY_DX5GCR0_MDLEN_DEFVAL 0x40200204
12292 #define DDR_PHY_DX5GCR0_MDLEN_SHIFT 30
12293 #define DDR_PHY_DX5GCR0_MDLEN_MASK 0x40000000U
12295 /*Configurable ODT(TE) Phase Shift*/
12296 #undef DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL
12297 #undef DDR_PHY_DX5GCR0_CODTSHFT_SHIFT
12298 #undef DDR_PHY_DX5GCR0_CODTSHFT_MASK
12299 #define DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL 0x40200204
12300 #define DDR_PHY_DX5GCR0_CODTSHFT_SHIFT 28
12301 #define DDR_PHY_DX5GCR0_CODTSHFT_MASK 0x30000000U
12303 /*DQS Duty Cycle Correction*/
12304 #undef DDR_PHY_DX5GCR0_DQSDCC_DEFVAL
12305 #undef DDR_PHY_DX5GCR0_DQSDCC_SHIFT
12306 #undef DDR_PHY_DX5GCR0_DQSDCC_MASK
12307 #define DDR_PHY_DX5GCR0_DQSDCC_DEFVAL 0x40200204
12308 #define DDR_PHY_DX5GCR0_DQSDCC_SHIFT 24
12309 #define DDR_PHY_DX5GCR0_DQSDCC_MASK 0x0F000000U
12311 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
12312 #undef DDR_PHY_DX5GCR0_RDDLY_DEFVAL
12313 #undef DDR_PHY_DX5GCR0_RDDLY_SHIFT
12314 #undef DDR_PHY_DX5GCR0_RDDLY_MASK
12315 #define DDR_PHY_DX5GCR0_RDDLY_DEFVAL 0x40200204
12316 #define DDR_PHY_DX5GCR0_RDDLY_SHIFT 20
12317 #define DDR_PHY_DX5GCR0_RDDLY_MASK 0x00F00000U
12319 /*Reserved. Return zeroes on reads.*/
12320 #undef DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL
12321 #undef DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT
12322 #undef DDR_PHY_DX5GCR0_RESERVED_19_14_MASK
12323 #define DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL 0x40200204
12324 #define DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT 14
12325 #define DDR_PHY_DX5GCR0_RESERVED_19_14_MASK 0x000FC000U
12327 /*DQSNSE Power Down Receiver*/
12328 #undef DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL
12329 #undef DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT
12330 #undef DDR_PHY_DX5GCR0_DQSNSEPDR_MASK
12331 #define DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL 0x40200204
12332 #define DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT 13
12333 #define DDR_PHY_DX5GCR0_DQSNSEPDR_MASK 0x00002000U
12335 /*DQSSE Power Down Receiver*/
12336 #undef DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL
12337 #undef DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT
12338 #undef DDR_PHY_DX5GCR0_DQSSEPDR_MASK
12339 #define DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL 0x40200204
12340 #define DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT 12
12341 #define DDR_PHY_DX5GCR0_DQSSEPDR_MASK 0x00001000U
12343 /*RTT On Additive Latency*/
12344 #undef DDR_PHY_DX5GCR0_RTTOAL_DEFVAL
12345 #undef DDR_PHY_DX5GCR0_RTTOAL_SHIFT
12346 #undef DDR_PHY_DX5GCR0_RTTOAL_MASK
12347 #define DDR_PHY_DX5GCR0_RTTOAL_DEFVAL 0x40200204
12348 #define DDR_PHY_DX5GCR0_RTTOAL_SHIFT 11
12349 #define DDR_PHY_DX5GCR0_RTTOAL_MASK 0x00000800U
12351 /*RTT Output Hold*/
12352 #undef DDR_PHY_DX5GCR0_RTTOH_DEFVAL
12353 #undef DDR_PHY_DX5GCR0_RTTOH_SHIFT
12354 #undef DDR_PHY_DX5GCR0_RTTOH_MASK
12355 #define DDR_PHY_DX5GCR0_RTTOH_DEFVAL 0x40200204
12356 #define DDR_PHY_DX5GCR0_RTTOH_SHIFT 9
12357 #define DDR_PHY_DX5GCR0_RTTOH_MASK 0x00000600U
12359 /*Configurable PDR Phase Shift*/
12360 #undef DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL
12361 #undef DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT
12362 #undef DDR_PHY_DX5GCR0_CPDRSHFT_MASK
12363 #define DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL 0x40200204
12364 #define DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT 7
12365 #define DDR_PHY_DX5GCR0_CPDRSHFT_MASK 0x00000180U
12367 /*DQSR Power Down*/
12368 #undef DDR_PHY_DX5GCR0_DQSRPD_DEFVAL
12369 #undef DDR_PHY_DX5GCR0_DQSRPD_SHIFT
12370 #undef DDR_PHY_DX5GCR0_DQSRPD_MASK
12371 #define DDR_PHY_DX5GCR0_DQSRPD_DEFVAL 0x40200204
12372 #define DDR_PHY_DX5GCR0_DQSRPD_SHIFT 6
12373 #define DDR_PHY_DX5GCR0_DQSRPD_MASK 0x00000040U
12375 /*DQSG Power Down Receiver*/
12376 #undef DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL
12377 #undef DDR_PHY_DX5GCR0_DQSGPDR_SHIFT
12378 #undef DDR_PHY_DX5GCR0_DQSGPDR_MASK
12379 #define DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL 0x40200204
12380 #define DDR_PHY_DX5GCR0_DQSGPDR_SHIFT 5
12381 #define DDR_PHY_DX5GCR0_DQSGPDR_MASK 0x00000020U
12383 /*Reserved. Return zeroes on reads.*/
12384 #undef DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL
12385 #undef DDR_PHY_DX5GCR0_RESERVED_4_SHIFT
12386 #undef DDR_PHY_DX5GCR0_RESERVED_4_MASK
12387 #define DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL 0x40200204
12388 #define DDR_PHY_DX5GCR0_RESERVED_4_SHIFT 4
12389 #define DDR_PHY_DX5GCR0_RESERVED_4_MASK 0x00000010U
12391 /*DQSG On-Die Termination*/
12392 #undef DDR_PHY_DX5GCR0_DQSGODT_DEFVAL
12393 #undef DDR_PHY_DX5GCR0_DQSGODT_SHIFT
12394 #undef DDR_PHY_DX5GCR0_DQSGODT_MASK
12395 #define DDR_PHY_DX5GCR0_DQSGODT_DEFVAL 0x40200204
12396 #define DDR_PHY_DX5GCR0_DQSGODT_SHIFT 3
12397 #define DDR_PHY_DX5GCR0_DQSGODT_MASK 0x00000008U
12399 /*DQSG Output Enable*/
12400 #undef DDR_PHY_DX5GCR0_DQSGOE_DEFVAL
12401 #undef DDR_PHY_DX5GCR0_DQSGOE_SHIFT
12402 #undef DDR_PHY_DX5GCR0_DQSGOE_MASK
12403 #define DDR_PHY_DX5GCR0_DQSGOE_DEFVAL 0x40200204
12404 #define DDR_PHY_DX5GCR0_DQSGOE_SHIFT 2
12405 #define DDR_PHY_DX5GCR0_DQSGOE_MASK 0x00000004U
12407 /*Reserved. Return zeroes on reads.*/
12408 #undef DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL
12409 #undef DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT
12410 #undef DDR_PHY_DX5GCR0_RESERVED_1_0_MASK
12411 #define DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL 0x40200204
12412 #define DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT 0
12413 #define DDR_PHY_DX5GCR0_RESERVED_1_0_MASK 0x00000003U
12415 /*Enables the PDR mode for DQ[7:0]*/
12416 #undef DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL
12417 #undef DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT
12418 #undef DDR_PHY_DX5GCR1_DXPDRMODE_MASK
12419 #define DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL 0x00007FFF
12420 #define DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT 16
12421 #define DDR_PHY_DX5GCR1_DXPDRMODE_MASK 0xFFFF0000U
12423 /*Reserved. Returns zeroes on reads.*/
12424 #undef DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL
12425 #undef DDR_PHY_DX5GCR1_RESERVED_15_SHIFT
12426 #undef DDR_PHY_DX5GCR1_RESERVED_15_MASK
12427 #define DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL 0x00007FFF
12428 #define DDR_PHY_DX5GCR1_RESERVED_15_SHIFT 15
12429 #define DDR_PHY_DX5GCR1_RESERVED_15_MASK 0x00008000U
12431 /*Select the delayed or non-delayed read data strobe #*/
12432 #undef DDR_PHY_DX5GCR1_QSNSEL_DEFVAL
12433 #undef DDR_PHY_DX5GCR1_QSNSEL_SHIFT
12434 #undef DDR_PHY_DX5GCR1_QSNSEL_MASK
12435 #define DDR_PHY_DX5GCR1_QSNSEL_DEFVAL 0x00007FFF
12436 #define DDR_PHY_DX5GCR1_QSNSEL_SHIFT 14
12437 #define DDR_PHY_DX5GCR1_QSNSEL_MASK 0x00004000U
12439 /*Select the delayed or non-delayed read data strobe*/
12440 #undef DDR_PHY_DX5GCR1_QSSEL_DEFVAL
12441 #undef DDR_PHY_DX5GCR1_QSSEL_SHIFT
12442 #undef DDR_PHY_DX5GCR1_QSSEL_MASK
12443 #define DDR_PHY_DX5GCR1_QSSEL_DEFVAL 0x00007FFF
12444 #define DDR_PHY_DX5GCR1_QSSEL_SHIFT 13
12445 #define DDR_PHY_DX5GCR1_QSSEL_MASK 0x00002000U
12447 /*Enables Read Data Strobe in a byte lane*/
12448 #undef DDR_PHY_DX5GCR1_OEEN_DEFVAL
12449 #undef DDR_PHY_DX5GCR1_OEEN_SHIFT
12450 #undef DDR_PHY_DX5GCR1_OEEN_MASK
12451 #define DDR_PHY_DX5GCR1_OEEN_DEFVAL 0x00007FFF
12452 #define DDR_PHY_DX5GCR1_OEEN_SHIFT 12
12453 #define DDR_PHY_DX5GCR1_OEEN_MASK 0x00001000U
12455 /*Enables PDR in a byte lane*/
12456 #undef DDR_PHY_DX5GCR1_PDREN_DEFVAL
12457 #undef DDR_PHY_DX5GCR1_PDREN_SHIFT
12458 #undef DDR_PHY_DX5GCR1_PDREN_MASK
12459 #define DDR_PHY_DX5GCR1_PDREN_DEFVAL 0x00007FFF
12460 #define DDR_PHY_DX5GCR1_PDREN_SHIFT 11
12461 #define DDR_PHY_DX5GCR1_PDREN_MASK 0x00000800U
12463 /*Enables ODT/TE in a byte lane*/
12464 #undef DDR_PHY_DX5GCR1_TEEN_DEFVAL
12465 #undef DDR_PHY_DX5GCR1_TEEN_SHIFT
12466 #undef DDR_PHY_DX5GCR1_TEEN_MASK
12467 #define DDR_PHY_DX5GCR1_TEEN_DEFVAL 0x00007FFF
12468 #define DDR_PHY_DX5GCR1_TEEN_SHIFT 10
12469 #define DDR_PHY_DX5GCR1_TEEN_MASK 0x00000400U
12471 /*Enables Write Data strobe in a byte lane*/
12472 #undef DDR_PHY_DX5GCR1_DSEN_DEFVAL
12473 #undef DDR_PHY_DX5GCR1_DSEN_SHIFT
12474 #undef DDR_PHY_DX5GCR1_DSEN_MASK
12475 #define DDR_PHY_DX5GCR1_DSEN_DEFVAL 0x00007FFF
12476 #define DDR_PHY_DX5GCR1_DSEN_SHIFT 9
12477 #define DDR_PHY_DX5GCR1_DSEN_MASK 0x00000200U
12479 /*Enables DM pin in a byte lane*/
12480 #undef DDR_PHY_DX5GCR1_DMEN_DEFVAL
12481 #undef DDR_PHY_DX5GCR1_DMEN_SHIFT
12482 #undef DDR_PHY_DX5GCR1_DMEN_MASK
12483 #define DDR_PHY_DX5GCR1_DMEN_DEFVAL 0x00007FFF
12484 #define DDR_PHY_DX5GCR1_DMEN_SHIFT 8
12485 #define DDR_PHY_DX5GCR1_DMEN_MASK 0x00000100U
12487 /*Enables DQ corresponding to each bit in a byte*/
12488 #undef DDR_PHY_DX5GCR1_DQEN_DEFVAL
12489 #undef DDR_PHY_DX5GCR1_DQEN_SHIFT
12490 #undef DDR_PHY_DX5GCR1_DQEN_MASK
12491 #define DDR_PHY_DX5GCR1_DQEN_DEFVAL 0x00007FFF
12492 #define DDR_PHY_DX5GCR1_DQEN_SHIFT 0
12493 #define DDR_PHY_DX5GCR1_DQEN_MASK 0x000000FFU
12495 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
12496 #undef DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL
12497 #undef DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT
12498 #undef DDR_PHY_DX5GCR4_RESERVED_31_29_MASK
12499 #define DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL 0x0E00003C
12500 #define DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT 29
12501 #define DDR_PHY_DX5GCR4_RESERVED_31_29_MASK 0xE0000000U
12503 /*Byte Lane VREF Pad Enable*/
12504 #undef DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL
12505 #undef DDR_PHY_DX5GCR4_DXREFPEN_SHIFT
12506 #undef DDR_PHY_DX5GCR4_DXREFPEN_MASK
12507 #define DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL 0x0E00003C
12508 #define DDR_PHY_DX5GCR4_DXREFPEN_SHIFT 28
12509 #define DDR_PHY_DX5GCR4_DXREFPEN_MASK 0x10000000U
12511 /*Byte Lane Internal VREF Enable*/
12512 #undef DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL
12513 #undef DDR_PHY_DX5GCR4_DXREFEEN_SHIFT
12514 #undef DDR_PHY_DX5GCR4_DXREFEEN_MASK
12515 #define DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL 0x0E00003C
12516 #define DDR_PHY_DX5GCR4_DXREFEEN_SHIFT 26
12517 #define DDR_PHY_DX5GCR4_DXREFEEN_MASK 0x0C000000U
12519 /*Byte Lane Single-End VREF Enable*/
12520 #undef DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL
12521 #undef DDR_PHY_DX5GCR4_DXREFSEN_SHIFT
12522 #undef DDR_PHY_DX5GCR4_DXREFSEN_MASK
12523 #define DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL 0x0E00003C
12524 #define DDR_PHY_DX5GCR4_DXREFSEN_SHIFT 25
12525 #define DDR_PHY_DX5GCR4_DXREFSEN_MASK 0x02000000U
12527 /*Reserved. Returns zeros on reads.*/
12528 #undef DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL
12529 #undef DDR_PHY_DX5GCR4_RESERVED_24_SHIFT
12530 #undef DDR_PHY_DX5GCR4_RESERVED_24_MASK
12531 #define DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL 0x0E00003C
12532 #define DDR_PHY_DX5GCR4_RESERVED_24_SHIFT 24
12533 #define DDR_PHY_DX5GCR4_RESERVED_24_MASK 0x01000000U
12535 /*External VREF generator REFSEL range select*/
12536 #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL
12537 #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT
12538 #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK
12539 #define DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C
12540 #define DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT 23
12541 #define DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK 0x00800000U
12543 /*Byte Lane External VREF Select*/
12544 #undef DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL
12545 #undef DDR_PHY_DX5GCR4_DXREFESEL_SHIFT
12546 #undef DDR_PHY_DX5GCR4_DXREFESEL_MASK
12547 #define DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL 0x0E00003C
12548 #define DDR_PHY_DX5GCR4_DXREFESEL_SHIFT 16
12549 #define DDR_PHY_DX5GCR4_DXREFESEL_MASK 0x007F0000U
12551 /*Single ended VREF generator REFSEL range select*/
12552 #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL
12553 #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT
12554 #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK
12555 #define DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C
12556 #define DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT 15
12557 #define DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK 0x00008000U
12559 /*Byte Lane Single-End VREF Select*/
12560 #undef DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL
12561 #undef DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT
12562 #undef DDR_PHY_DX5GCR4_DXREFSSEL_MASK
12563 #define DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL 0x0E00003C
12564 #define DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT 8
12565 #define DDR_PHY_DX5GCR4_DXREFSSEL_MASK 0x00007F00U
12567 /*Reserved. Returns zeros on reads.*/
12568 #undef DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL
12569 #undef DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT
12570 #undef DDR_PHY_DX5GCR4_RESERVED_7_6_MASK
12571 #define DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL 0x0E00003C
12572 #define DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT 6
12573 #define DDR_PHY_DX5GCR4_RESERVED_7_6_MASK 0x000000C0U
12575 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
12576 #undef DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL
12577 #undef DDR_PHY_DX5GCR4_DXREFIEN_SHIFT
12578 #undef DDR_PHY_DX5GCR4_DXREFIEN_MASK
12579 #define DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL 0x0E00003C
12580 #define DDR_PHY_DX5GCR4_DXREFIEN_SHIFT 2
12581 #define DDR_PHY_DX5GCR4_DXREFIEN_MASK 0x0000003CU
12583 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
12584 #undef DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL
12585 #undef DDR_PHY_DX5GCR4_DXREFIMON_SHIFT
12586 #undef DDR_PHY_DX5GCR4_DXREFIMON_MASK
12587 #define DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL 0x0E00003C
12588 #define DDR_PHY_DX5GCR4_DXREFIMON_SHIFT 0
12589 #define DDR_PHY_DX5GCR4_DXREFIMON_MASK 0x00000003U
12591 /*Reserved. Returns zeros on reads.*/
12592 #undef DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL
12593 #undef DDR_PHY_DX5GCR5_RESERVED_31_SHIFT
12594 #undef DDR_PHY_DX5GCR5_RESERVED_31_MASK
12595 #define DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL 0x09090909
12596 #define DDR_PHY_DX5GCR5_RESERVED_31_SHIFT 31
12597 #define DDR_PHY_DX5GCR5_RESERVED_31_MASK 0x80000000U
12599 /*Byte Lane internal VREF Select for Rank 3*/
12600 #undef DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL
12601 #undef DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT
12602 #undef DDR_PHY_DX5GCR5_DXREFISELR3_MASK
12603 #define DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL 0x09090909
12604 #define DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT 24
12605 #define DDR_PHY_DX5GCR5_DXREFISELR3_MASK 0x7F000000U
12607 /*Reserved. Returns zeros on reads.*/
12608 #undef DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL
12609 #undef DDR_PHY_DX5GCR5_RESERVED_23_SHIFT
12610 #undef DDR_PHY_DX5GCR5_RESERVED_23_MASK
12611 #define DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL 0x09090909
12612 #define DDR_PHY_DX5GCR5_RESERVED_23_SHIFT 23
12613 #define DDR_PHY_DX5GCR5_RESERVED_23_MASK 0x00800000U
12615 /*Byte Lane internal VREF Select for Rank 2*/
12616 #undef DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL
12617 #undef DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT
12618 #undef DDR_PHY_DX5GCR5_DXREFISELR2_MASK
12619 #define DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL 0x09090909
12620 #define DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT 16
12621 #define DDR_PHY_DX5GCR5_DXREFISELR2_MASK 0x007F0000U
12623 /*Reserved. Returns zeros on reads.*/
12624 #undef DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL
12625 #undef DDR_PHY_DX5GCR5_RESERVED_15_SHIFT
12626 #undef DDR_PHY_DX5GCR5_RESERVED_15_MASK
12627 #define DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL 0x09090909
12628 #define DDR_PHY_DX5GCR5_RESERVED_15_SHIFT 15
12629 #define DDR_PHY_DX5GCR5_RESERVED_15_MASK 0x00008000U
12631 /*Byte Lane internal VREF Select for Rank 1*/
12632 #undef DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL
12633 #undef DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT
12634 #undef DDR_PHY_DX5GCR5_DXREFISELR1_MASK
12635 #define DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL 0x09090909
12636 #define DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT 8
12637 #define DDR_PHY_DX5GCR5_DXREFISELR1_MASK 0x00007F00U
12639 /*Reserved. Returns zeros on reads.*/
12640 #undef DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL
12641 #undef DDR_PHY_DX5GCR5_RESERVED_7_SHIFT
12642 #undef DDR_PHY_DX5GCR5_RESERVED_7_MASK
12643 #define DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL 0x09090909
12644 #define DDR_PHY_DX5GCR5_RESERVED_7_SHIFT 7
12645 #define DDR_PHY_DX5GCR5_RESERVED_7_MASK 0x00000080U
12647 /*Byte Lane internal VREF Select for Rank 0*/
12648 #undef DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL
12649 #undef DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT
12650 #undef DDR_PHY_DX5GCR5_DXREFISELR0_MASK
12651 #define DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL 0x09090909
12652 #define DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT 0
12653 #define DDR_PHY_DX5GCR5_DXREFISELR0_MASK 0x0000007FU
12655 /*Reserved. Returns zeros on reads.*/
12656 #undef DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL
12657 #undef DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT
12658 #undef DDR_PHY_DX5GCR6_RESERVED_31_30_MASK
12659 #define DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL 0x09090909
12660 #define DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT 30
12661 #define DDR_PHY_DX5GCR6_RESERVED_31_30_MASK 0xC0000000U
12663 /*DRAM DQ VREF Select for Rank3*/
12664 #undef DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL
12665 #undef DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT
12666 #undef DDR_PHY_DX5GCR6_DXDQVREFR3_MASK
12667 #define DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL 0x09090909
12668 #define DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT 24
12669 #define DDR_PHY_DX5GCR6_DXDQVREFR3_MASK 0x3F000000U
12671 /*Reserved. Returns zeros on reads.*/
12672 #undef DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL
12673 #undef DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT
12674 #undef DDR_PHY_DX5GCR6_RESERVED_23_22_MASK
12675 #define DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL 0x09090909
12676 #define DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT 22
12677 #define DDR_PHY_DX5GCR6_RESERVED_23_22_MASK 0x00C00000U
12679 /*DRAM DQ VREF Select for Rank2*/
12680 #undef DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL
12681 #undef DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT
12682 #undef DDR_PHY_DX5GCR6_DXDQVREFR2_MASK
12683 #define DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL 0x09090909
12684 #define DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT 16
12685 #define DDR_PHY_DX5GCR6_DXDQVREFR2_MASK 0x003F0000U
12687 /*Reserved. Returns zeros on reads.*/
12688 #undef DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL
12689 #undef DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT
12690 #undef DDR_PHY_DX5GCR6_RESERVED_15_14_MASK
12691 #define DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL 0x09090909
12692 #define DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT 14
12693 #define DDR_PHY_DX5GCR6_RESERVED_15_14_MASK 0x0000C000U
12695 /*DRAM DQ VREF Select for Rank1*/
12696 #undef DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL
12697 #undef DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT
12698 #undef DDR_PHY_DX5GCR6_DXDQVREFR1_MASK
12699 #define DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL 0x09090909
12700 #define DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT 8
12701 #define DDR_PHY_DX5GCR6_DXDQVREFR1_MASK 0x00003F00U
12703 /*Reserved. Returns zeros on reads.*/
12704 #undef DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL
12705 #undef DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT
12706 #undef DDR_PHY_DX5GCR6_RESERVED_7_6_MASK
12707 #define DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL 0x09090909
12708 #define DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT 6
12709 #define DDR_PHY_DX5GCR6_RESERVED_7_6_MASK 0x000000C0U
12711 /*DRAM DQ VREF Select for Rank0*/
12712 #undef DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL
12713 #undef DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT
12714 #undef DDR_PHY_DX5GCR6_DXDQVREFR0_MASK
12715 #define DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL 0x09090909
12716 #define DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT 0
12717 #define DDR_PHY_DX5GCR6_DXDQVREFR0_MASK 0x0000003FU
12719 /*Reserved. Return zeroes on reads.*/
12720 #undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_DEFVAL
12721 #undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT
12722 #undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK
12723 #define DDR_PHY_DX5LCDLR2_RESERVED_31_25_DEFVAL 0x00000000
12724 #define DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT 25
12725 #define DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK 0xFE000000U
12727 /*Reserved. Caution, do not write to this register field.*/
12728 #undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_DEFVAL
12729 #undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT
12730 #undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK
12731 #define DDR_PHY_DX5LCDLR2_RESERVED_24_16_DEFVAL 0x00000000
12732 #define DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT 16
12733 #define DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK 0x01FF0000U
12735 /*Reserved. Return zeroes on reads.*/
12736 #undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_DEFVAL
12737 #undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT
12738 #undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK
12739 #define DDR_PHY_DX5LCDLR2_RESERVED_15_9_DEFVAL 0x00000000
12740 #define DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT 9
12741 #define DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK 0x0000FE00U
12743 /*Read DQS Gating Delay*/
12744 #undef DDR_PHY_DX5LCDLR2_DQSGD_DEFVAL
12745 #undef DDR_PHY_DX5LCDLR2_DQSGD_SHIFT
12746 #undef DDR_PHY_DX5LCDLR2_DQSGD_MASK
12747 #define DDR_PHY_DX5LCDLR2_DQSGD_DEFVAL 0x00000000
12748 #define DDR_PHY_DX5LCDLR2_DQSGD_SHIFT 0
12749 #define DDR_PHY_DX5LCDLR2_DQSGD_MASK 0x000001FFU
12751 /*Reserved. Return zeroes on reads.*/
12752 #undef DDR_PHY_DX5GTR0_RESERVED_31_24_DEFVAL
12753 #undef DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT
12754 #undef DDR_PHY_DX5GTR0_RESERVED_31_24_MASK
12755 #define DDR_PHY_DX5GTR0_RESERVED_31_24_DEFVAL 0x00020000
12756 #define DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT 27
12757 #define DDR_PHY_DX5GTR0_RESERVED_31_24_MASK 0xF8000000U
12759 /*DQ Write Path Latency Pipeline*/
12760 #undef DDR_PHY_DX5GTR0_WDQSL_DEFVAL
12761 #undef DDR_PHY_DX5GTR0_WDQSL_SHIFT
12762 #undef DDR_PHY_DX5GTR0_WDQSL_MASK
12763 #define DDR_PHY_DX5GTR0_WDQSL_DEFVAL 0x00020000
12764 #define DDR_PHY_DX5GTR0_WDQSL_SHIFT 24
12765 #define DDR_PHY_DX5GTR0_WDQSL_MASK 0x07000000U
12767 /*Reserved. Caution, do not write to this register field.*/
12768 #undef DDR_PHY_DX5GTR0_RESERVED_23_20_DEFVAL
12769 #undef DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT
12770 #undef DDR_PHY_DX5GTR0_RESERVED_23_20_MASK
12771 #define DDR_PHY_DX5GTR0_RESERVED_23_20_DEFVAL 0x00020000
12772 #define DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT 20
12773 #define DDR_PHY_DX5GTR0_RESERVED_23_20_MASK 0x00F00000U
12775 /*Write Leveling System Latency*/
12776 #undef DDR_PHY_DX5GTR0_WLSL_DEFVAL
12777 #undef DDR_PHY_DX5GTR0_WLSL_SHIFT
12778 #undef DDR_PHY_DX5GTR0_WLSL_MASK
12779 #define DDR_PHY_DX5GTR0_WLSL_DEFVAL 0x00020000
12780 #define DDR_PHY_DX5GTR0_WLSL_SHIFT 16
12781 #define DDR_PHY_DX5GTR0_WLSL_MASK 0x000F0000U
12783 /*Reserved. Return zeroes on reads.*/
12784 #undef DDR_PHY_DX5GTR0_RESERVED_15_13_DEFVAL
12785 #undef DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT
12786 #undef DDR_PHY_DX5GTR0_RESERVED_15_13_MASK
12787 #define DDR_PHY_DX5GTR0_RESERVED_15_13_DEFVAL 0x00020000
12788 #define DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT 13
12789 #define DDR_PHY_DX5GTR0_RESERVED_15_13_MASK 0x0000E000U
12791 /*Reserved. Caution, do not write to this register field.*/
12792 #undef DDR_PHY_DX5GTR0_RESERVED_12_8_DEFVAL
12793 #undef DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT
12794 #undef DDR_PHY_DX5GTR0_RESERVED_12_8_MASK
12795 #define DDR_PHY_DX5GTR0_RESERVED_12_8_DEFVAL 0x00020000
12796 #define DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT 8
12797 #define DDR_PHY_DX5GTR0_RESERVED_12_8_MASK 0x00001F00U
12799 /*Reserved. Return zeroes on reads.*/
12800 #undef DDR_PHY_DX5GTR0_RESERVED_7_5_DEFVAL
12801 #undef DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT
12802 #undef DDR_PHY_DX5GTR0_RESERVED_7_5_MASK
12803 #define DDR_PHY_DX5GTR0_RESERVED_7_5_DEFVAL 0x00020000
12804 #define DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT 5
12805 #define DDR_PHY_DX5GTR0_RESERVED_7_5_MASK 0x000000E0U
12807 /*DQS Gating System Latency*/
12808 #undef DDR_PHY_DX5GTR0_DGSL_DEFVAL
12809 #undef DDR_PHY_DX5GTR0_DGSL_SHIFT
12810 #undef DDR_PHY_DX5GTR0_DGSL_MASK
12811 #define DDR_PHY_DX5GTR0_DGSL_DEFVAL 0x00020000
12812 #define DDR_PHY_DX5GTR0_DGSL_SHIFT 0
12813 #define DDR_PHY_DX5GTR0_DGSL_MASK 0x0000001FU
12815 /*Calibration Bypass*/
12816 #undef DDR_PHY_DX6GCR0_CALBYP_DEFVAL
12817 #undef DDR_PHY_DX6GCR0_CALBYP_SHIFT
12818 #undef DDR_PHY_DX6GCR0_CALBYP_MASK
12819 #define DDR_PHY_DX6GCR0_CALBYP_DEFVAL 0x40200204
12820 #define DDR_PHY_DX6GCR0_CALBYP_SHIFT 31
12821 #define DDR_PHY_DX6GCR0_CALBYP_MASK 0x80000000U
12823 /*Master Delay Line Enable*/
12824 #undef DDR_PHY_DX6GCR0_MDLEN_DEFVAL
12825 #undef DDR_PHY_DX6GCR0_MDLEN_SHIFT
12826 #undef DDR_PHY_DX6GCR0_MDLEN_MASK
12827 #define DDR_PHY_DX6GCR0_MDLEN_DEFVAL 0x40200204
12828 #define DDR_PHY_DX6GCR0_MDLEN_SHIFT 30
12829 #define DDR_PHY_DX6GCR0_MDLEN_MASK 0x40000000U
12831 /*Configurable ODT(TE) Phase Shift*/
12832 #undef DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL
12833 #undef DDR_PHY_DX6GCR0_CODTSHFT_SHIFT
12834 #undef DDR_PHY_DX6GCR0_CODTSHFT_MASK
12835 #define DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL 0x40200204
12836 #define DDR_PHY_DX6GCR0_CODTSHFT_SHIFT 28
12837 #define DDR_PHY_DX6GCR0_CODTSHFT_MASK 0x30000000U
12839 /*DQS Duty Cycle Correction*/
12840 #undef DDR_PHY_DX6GCR0_DQSDCC_DEFVAL
12841 #undef DDR_PHY_DX6GCR0_DQSDCC_SHIFT
12842 #undef DDR_PHY_DX6GCR0_DQSDCC_MASK
12843 #define DDR_PHY_DX6GCR0_DQSDCC_DEFVAL 0x40200204
12844 #define DDR_PHY_DX6GCR0_DQSDCC_SHIFT 24
12845 #define DDR_PHY_DX6GCR0_DQSDCC_MASK 0x0F000000U
12847 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
12848 #undef DDR_PHY_DX6GCR0_RDDLY_DEFVAL
12849 #undef DDR_PHY_DX6GCR0_RDDLY_SHIFT
12850 #undef DDR_PHY_DX6GCR0_RDDLY_MASK
12851 #define DDR_PHY_DX6GCR0_RDDLY_DEFVAL 0x40200204
12852 #define DDR_PHY_DX6GCR0_RDDLY_SHIFT 20
12853 #define DDR_PHY_DX6GCR0_RDDLY_MASK 0x00F00000U
12855 /*Reserved. Return zeroes on reads.*/
12856 #undef DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL
12857 #undef DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT
12858 #undef DDR_PHY_DX6GCR0_RESERVED_19_14_MASK
12859 #define DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL 0x40200204
12860 #define DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT 14
12861 #define DDR_PHY_DX6GCR0_RESERVED_19_14_MASK 0x000FC000U
12863 /*DQSNSE Power Down Receiver*/
12864 #undef DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL
12865 #undef DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT
12866 #undef DDR_PHY_DX6GCR0_DQSNSEPDR_MASK
12867 #define DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL 0x40200204
12868 #define DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT 13
12869 #define DDR_PHY_DX6GCR0_DQSNSEPDR_MASK 0x00002000U
12871 /*DQSSE Power Down Receiver*/
12872 #undef DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL
12873 #undef DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT
12874 #undef DDR_PHY_DX6GCR0_DQSSEPDR_MASK
12875 #define DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL 0x40200204
12876 #define DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT 12
12877 #define DDR_PHY_DX6GCR0_DQSSEPDR_MASK 0x00001000U
12879 /*RTT On Additive Latency*/
12880 #undef DDR_PHY_DX6GCR0_RTTOAL_DEFVAL
12881 #undef DDR_PHY_DX6GCR0_RTTOAL_SHIFT
12882 #undef DDR_PHY_DX6GCR0_RTTOAL_MASK
12883 #define DDR_PHY_DX6GCR0_RTTOAL_DEFVAL 0x40200204
12884 #define DDR_PHY_DX6GCR0_RTTOAL_SHIFT 11
12885 #define DDR_PHY_DX6GCR0_RTTOAL_MASK 0x00000800U
12887 /*RTT Output Hold*/
12888 #undef DDR_PHY_DX6GCR0_RTTOH_DEFVAL
12889 #undef DDR_PHY_DX6GCR0_RTTOH_SHIFT
12890 #undef DDR_PHY_DX6GCR0_RTTOH_MASK
12891 #define DDR_PHY_DX6GCR0_RTTOH_DEFVAL 0x40200204
12892 #define DDR_PHY_DX6GCR0_RTTOH_SHIFT 9
12893 #define DDR_PHY_DX6GCR0_RTTOH_MASK 0x00000600U
12895 /*Configurable PDR Phase Shift*/
12896 #undef DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL
12897 #undef DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT
12898 #undef DDR_PHY_DX6GCR0_CPDRSHFT_MASK
12899 #define DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL 0x40200204
12900 #define DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT 7
12901 #define DDR_PHY_DX6GCR0_CPDRSHFT_MASK 0x00000180U
12903 /*DQSR Power Down*/
12904 #undef DDR_PHY_DX6GCR0_DQSRPD_DEFVAL
12905 #undef DDR_PHY_DX6GCR0_DQSRPD_SHIFT
12906 #undef DDR_PHY_DX6GCR0_DQSRPD_MASK
12907 #define DDR_PHY_DX6GCR0_DQSRPD_DEFVAL 0x40200204
12908 #define DDR_PHY_DX6GCR0_DQSRPD_SHIFT 6
12909 #define DDR_PHY_DX6GCR0_DQSRPD_MASK 0x00000040U
12911 /*DQSG Power Down Receiver*/
12912 #undef DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL
12913 #undef DDR_PHY_DX6GCR0_DQSGPDR_SHIFT
12914 #undef DDR_PHY_DX6GCR0_DQSGPDR_MASK
12915 #define DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL 0x40200204
12916 #define DDR_PHY_DX6GCR0_DQSGPDR_SHIFT 5
12917 #define DDR_PHY_DX6GCR0_DQSGPDR_MASK 0x00000020U
12919 /*Reserved. Return zeroes on reads.*/
12920 #undef DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL
12921 #undef DDR_PHY_DX6GCR0_RESERVED_4_SHIFT
12922 #undef DDR_PHY_DX6GCR0_RESERVED_4_MASK
12923 #define DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL 0x40200204
12924 #define DDR_PHY_DX6GCR0_RESERVED_4_SHIFT 4
12925 #define DDR_PHY_DX6GCR0_RESERVED_4_MASK 0x00000010U
12927 /*DQSG On-Die Termination*/
12928 #undef DDR_PHY_DX6GCR0_DQSGODT_DEFVAL
12929 #undef DDR_PHY_DX6GCR0_DQSGODT_SHIFT
12930 #undef DDR_PHY_DX6GCR0_DQSGODT_MASK
12931 #define DDR_PHY_DX6GCR0_DQSGODT_DEFVAL 0x40200204
12932 #define DDR_PHY_DX6GCR0_DQSGODT_SHIFT 3
12933 #define DDR_PHY_DX6GCR0_DQSGODT_MASK 0x00000008U
12935 /*DQSG Output Enable*/
12936 #undef DDR_PHY_DX6GCR0_DQSGOE_DEFVAL
12937 #undef DDR_PHY_DX6GCR0_DQSGOE_SHIFT
12938 #undef DDR_PHY_DX6GCR0_DQSGOE_MASK
12939 #define DDR_PHY_DX6GCR0_DQSGOE_DEFVAL 0x40200204
12940 #define DDR_PHY_DX6GCR0_DQSGOE_SHIFT 2
12941 #define DDR_PHY_DX6GCR0_DQSGOE_MASK 0x00000004U
12943 /*Reserved. Return zeroes on reads.*/
12944 #undef DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL
12945 #undef DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT
12946 #undef DDR_PHY_DX6GCR0_RESERVED_1_0_MASK
12947 #define DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL 0x40200204
12948 #define DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT 0
12949 #define DDR_PHY_DX6GCR0_RESERVED_1_0_MASK 0x00000003U
12951 /*Enables the PDR mode for DQ[7:0]*/
12952 #undef DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL
12953 #undef DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT
12954 #undef DDR_PHY_DX6GCR1_DXPDRMODE_MASK
12955 #define DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL 0x00007FFF
12956 #define DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT 16
12957 #define DDR_PHY_DX6GCR1_DXPDRMODE_MASK 0xFFFF0000U
12959 /*Reserved. Returns zeroes on reads.*/
12960 #undef DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL
12961 #undef DDR_PHY_DX6GCR1_RESERVED_15_SHIFT
12962 #undef DDR_PHY_DX6GCR1_RESERVED_15_MASK
12963 #define DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL 0x00007FFF
12964 #define DDR_PHY_DX6GCR1_RESERVED_15_SHIFT 15
12965 #define DDR_PHY_DX6GCR1_RESERVED_15_MASK 0x00008000U
12967 /*Select the delayed or non-delayed read data strobe #*/
12968 #undef DDR_PHY_DX6GCR1_QSNSEL_DEFVAL
12969 #undef DDR_PHY_DX6GCR1_QSNSEL_SHIFT
12970 #undef DDR_PHY_DX6GCR1_QSNSEL_MASK
12971 #define DDR_PHY_DX6GCR1_QSNSEL_DEFVAL 0x00007FFF
12972 #define DDR_PHY_DX6GCR1_QSNSEL_SHIFT 14
12973 #define DDR_PHY_DX6GCR1_QSNSEL_MASK 0x00004000U
12975 /*Select the delayed or non-delayed read data strobe*/
12976 #undef DDR_PHY_DX6GCR1_QSSEL_DEFVAL
12977 #undef DDR_PHY_DX6GCR1_QSSEL_SHIFT
12978 #undef DDR_PHY_DX6GCR1_QSSEL_MASK
12979 #define DDR_PHY_DX6GCR1_QSSEL_DEFVAL 0x00007FFF
12980 #define DDR_PHY_DX6GCR1_QSSEL_SHIFT 13
12981 #define DDR_PHY_DX6GCR1_QSSEL_MASK 0x00002000U
12983 /*Enables Read Data Strobe in a byte lane*/
12984 #undef DDR_PHY_DX6GCR1_OEEN_DEFVAL
12985 #undef DDR_PHY_DX6GCR1_OEEN_SHIFT
12986 #undef DDR_PHY_DX6GCR1_OEEN_MASK
12987 #define DDR_PHY_DX6GCR1_OEEN_DEFVAL 0x00007FFF
12988 #define DDR_PHY_DX6GCR1_OEEN_SHIFT 12
12989 #define DDR_PHY_DX6GCR1_OEEN_MASK 0x00001000U
12991 /*Enables PDR in a byte lane*/
12992 #undef DDR_PHY_DX6GCR1_PDREN_DEFVAL
12993 #undef DDR_PHY_DX6GCR1_PDREN_SHIFT
12994 #undef DDR_PHY_DX6GCR1_PDREN_MASK
12995 #define DDR_PHY_DX6GCR1_PDREN_DEFVAL 0x00007FFF
12996 #define DDR_PHY_DX6GCR1_PDREN_SHIFT 11
12997 #define DDR_PHY_DX6GCR1_PDREN_MASK 0x00000800U
12999 /*Enables ODT/TE in a byte lane*/
13000 #undef DDR_PHY_DX6GCR1_TEEN_DEFVAL
13001 #undef DDR_PHY_DX6GCR1_TEEN_SHIFT
13002 #undef DDR_PHY_DX6GCR1_TEEN_MASK
13003 #define DDR_PHY_DX6GCR1_TEEN_DEFVAL 0x00007FFF
13004 #define DDR_PHY_DX6GCR1_TEEN_SHIFT 10
13005 #define DDR_PHY_DX6GCR1_TEEN_MASK 0x00000400U
13007 /*Enables Write Data strobe in a byte lane*/
13008 #undef DDR_PHY_DX6GCR1_DSEN_DEFVAL
13009 #undef DDR_PHY_DX6GCR1_DSEN_SHIFT
13010 #undef DDR_PHY_DX6GCR1_DSEN_MASK
13011 #define DDR_PHY_DX6GCR1_DSEN_DEFVAL 0x00007FFF
13012 #define DDR_PHY_DX6GCR1_DSEN_SHIFT 9
13013 #define DDR_PHY_DX6GCR1_DSEN_MASK 0x00000200U
13015 /*Enables DM pin in a byte lane*/
13016 #undef DDR_PHY_DX6GCR1_DMEN_DEFVAL
13017 #undef DDR_PHY_DX6GCR1_DMEN_SHIFT
13018 #undef DDR_PHY_DX6GCR1_DMEN_MASK
13019 #define DDR_PHY_DX6GCR1_DMEN_DEFVAL 0x00007FFF
13020 #define DDR_PHY_DX6GCR1_DMEN_SHIFT 8
13021 #define DDR_PHY_DX6GCR1_DMEN_MASK 0x00000100U
13023 /*Enables DQ corresponding to each bit in a byte*/
13024 #undef DDR_PHY_DX6GCR1_DQEN_DEFVAL
13025 #undef DDR_PHY_DX6GCR1_DQEN_SHIFT
13026 #undef DDR_PHY_DX6GCR1_DQEN_MASK
13027 #define DDR_PHY_DX6GCR1_DQEN_DEFVAL 0x00007FFF
13028 #define DDR_PHY_DX6GCR1_DQEN_SHIFT 0
13029 #define DDR_PHY_DX6GCR1_DQEN_MASK 0x000000FFU
13031 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
13032 #undef DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL
13033 #undef DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT
13034 #undef DDR_PHY_DX6GCR4_RESERVED_31_29_MASK
13035 #define DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL 0x0E00003C
13036 #define DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT 29
13037 #define DDR_PHY_DX6GCR4_RESERVED_31_29_MASK 0xE0000000U
13039 /*Byte Lane VREF Pad Enable*/
13040 #undef DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL
13041 #undef DDR_PHY_DX6GCR4_DXREFPEN_SHIFT
13042 #undef DDR_PHY_DX6GCR4_DXREFPEN_MASK
13043 #define DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL 0x0E00003C
13044 #define DDR_PHY_DX6GCR4_DXREFPEN_SHIFT 28
13045 #define DDR_PHY_DX6GCR4_DXREFPEN_MASK 0x10000000U
13047 /*Byte Lane Internal VREF Enable*/
13048 #undef DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL
13049 #undef DDR_PHY_DX6GCR4_DXREFEEN_SHIFT
13050 #undef DDR_PHY_DX6GCR4_DXREFEEN_MASK
13051 #define DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL 0x0E00003C
13052 #define DDR_PHY_DX6GCR4_DXREFEEN_SHIFT 26
13053 #define DDR_PHY_DX6GCR4_DXREFEEN_MASK 0x0C000000U
13055 /*Byte Lane Single-End VREF Enable*/
13056 #undef DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL
13057 #undef DDR_PHY_DX6GCR4_DXREFSEN_SHIFT
13058 #undef DDR_PHY_DX6GCR4_DXREFSEN_MASK
13059 #define DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL 0x0E00003C
13060 #define DDR_PHY_DX6GCR4_DXREFSEN_SHIFT 25
13061 #define DDR_PHY_DX6GCR4_DXREFSEN_MASK 0x02000000U
13063 /*Reserved. Returns zeros on reads.*/
13064 #undef DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL
13065 #undef DDR_PHY_DX6GCR4_RESERVED_24_SHIFT
13066 #undef DDR_PHY_DX6GCR4_RESERVED_24_MASK
13067 #define DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL 0x0E00003C
13068 #define DDR_PHY_DX6GCR4_RESERVED_24_SHIFT 24
13069 #define DDR_PHY_DX6GCR4_RESERVED_24_MASK 0x01000000U
13071 /*External VREF generator REFSEL range select*/
13072 #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL
13073 #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT
13074 #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK
13075 #define DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C
13076 #define DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT 23
13077 #define DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK 0x00800000U
13079 /*Byte Lane External VREF Select*/
13080 #undef DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL
13081 #undef DDR_PHY_DX6GCR4_DXREFESEL_SHIFT
13082 #undef DDR_PHY_DX6GCR4_DXREFESEL_MASK
13083 #define DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL 0x0E00003C
13084 #define DDR_PHY_DX6GCR4_DXREFESEL_SHIFT 16
13085 #define DDR_PHY_DX6GCR4_DXREFESEL_MASK 0x007F0000U
13087 /*Single ended VREF generator REFSEL range select*/
13088 #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL
13089 #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT
13090 #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK
13091 #define DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C
13092 #define DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT 15
13093 #define DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK 0x00008000U
13095 /*Byte Lane Single-End VREF Select*/
13096 #undef DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL
13097 #undef DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT
13098 #undef DDR_PHY_DX6GCR4_DXREFSSEL_MASK
13099 #define DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL 0x0E00003C
13100 #define DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT 8
13101 #define DDR_PHY_DX6GCR4_DXREFSSEL_MASK 0x00007F00U
13103 /*Reserved. Returns zeros on reads.*/
13104 #undef DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL
13105 #undef DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT
13106 #undef DDR_PHY_DX6GCR4_RESERVED_7_6_MASK
13107 #define DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL 0x0E00003C
13108 #define DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT 6
13109 #define DDR_PHY_DX6GCR4_RESERVED_7_6_MASK 0x000000C0U
13111 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
13112 #undef DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL
13113 #undef DDR_PHY_DX6GCR4_DXREFIEN_SHIFT
13114 #undef DDR_PHY_DX6GCR4_DXREFIEN_MASK
13115 #define DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL 0x0E00003C
13116 #define DDR_PHY_DX6GCR4_DXREFIEN_SHIFT 2
13117 #define DDR_PHY_DX6GCR4_DXREFIEN_MASK 0x0000003CU
13119 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
13120 #undef DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL
13121 #undef DDR_PHY_DX6GCR4_DXREFIMON_SHIFT
13122 #undef DDR_PHY_DX6GCR4_DXREFIMON_MASK
13123 #define DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL 0x0E00003C
13124 #define DDR_PHY_DX6GCR4_DXREFIMON_SHIFT 0
13125 #define DDR_PHY_DX6GCR4_DXREFIMON_MASK 0x00000003U
13127 /*Reserved. Returns zeros on reads.*/
13128 #undef DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL
13129 #undef DDR_PHY_DX6GCR5_RESERVED_31_SHIFT
13130 #undef DDR_PHY_DX6GCR5_RESERVED_31_MASK
13131 #define DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL 0x09090909
13132 #define DDR_PHY_DX6GCR5_RESERVED_31_SHIFT 31
13133 #define DDR_PHY_DX6GCR5_RESERVED_31_MASK 0x80000000U
13135 /*Byte Lane internal VREF Select for Rank 3*/
13136 #undef DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL
13137 #undef DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT
13138 #undef DDR_PHY_DX6GCR5_DXREFISELR3_MASK
13139 #define DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL 0x09090909
13140 #define DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT 24
13141 #define DDR_PHY_DX6GCR5_DXREFISELR3_MASK 0x7F000000U
13143 /*Reserved. Returns zeros on reads.*/
13144 #undef DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL
13145 #undef DDR_PHY_DX6GCR5_RESERVED_23_SHIFT
13146 #undef DDR_PHY_DX6GCR5_RESERVED_23_MASK
13147 #define DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL 0x09090909
13148 #define DDR_PHY_DX6GCR5_RESERVED_23_SHIFT 23
13149 #define DDR_PHY_DX6GCR5_RESERVED_23_MASK 0x00800000U
13151 /*Byte Lane internal VREF Select for Rank 2*/
13152 #undef DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL
13153 #undef DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT
13154 #undef DDR_PHY_DX6GCR5_DXREFISELR2_MASK
13155 #define DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL 0x09090909
13156 #define DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT 16
13157 #define DDR_PHY_DX6GCR5_DXREFISELR2_MASK 0x007F0000U
13159 /*Reserved. Returns zeros on reads.*/
13160 #undef DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL
13161 #undef DDR_PHY_DX6GCR5_RESERVED_15_SHIFT
13162 #undef DDR_PHY_DX6GCR5_RESERVED_15_MASK
13163 #define DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL 0x09090909
13164 #define DDR_PHY_DX6GCR5_RESERVED_15_SHIFT 15
13165 #define DDR_PHY_DX6GCR5_RESERVED_15_MASK 0x00008000U
13167 /*Byte Lane internal VREF Select for Rank 1*/
13168 #undef DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL
13169 #undef DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT
13170 #undef DDR_PHY_DX6GCR5_DXREFISELR1_MASK
13171 #define DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL 0x09090909
13172 #define DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT 8
13173 #define DDR_PHY_DX6GCR5_DXREFISELR1_MASK 0x00007F00U
13175 /*Reserved. Returns zeros on reads.*/
13176 #undef DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL
13177 #undef DDR_PHY_DX6GCR5_RESERVED_7_SHIFT
13178 #undef DDR_PHY_DX6GCR5_RESERVED_7_MASK
13179 #define DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL 0x09090909
13180 #define DDR_PHY_DX6GCR5_RESERVED_7_SHIFT 7
13181 #define DDR_PHY_DX6GCR5_RESERVED_7_MASK 0x00000080U
13183 /*Byte Lane internal VREF Select for Rank 0*/
13184 #undef DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL
13185 #undef DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT
13186 #undef DDR_PHY_DX6GCR5_DXREFISELR0_MASK
13187 #define DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL 0x09090909
13188 #define DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT 0
13189 #define DDR_PHY_DX6GCR5_DXREFISELR0_MASK 0x0000007FU
13191 /*Reserved. Returns zeros on reads.*/
13192 #undef DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL
13193 #undef DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT
13194 #undef DDR_PHY_DX6GCR6_RESERVED_31_30_MASK
13195 #define DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL 0x09090909
13196 #define DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT 30
13197 #define DDR_PHY_DX6GCR6_RESERVED_31_30_MASK 0xC0000000U
13199 /*DRAM DQ VREF Select for Rank3*/
13200 #undef DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL
13201 #undef DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT
13202 #undef DDR_PHY_DX6GCR6_DXDQVREFR3_MASK
13203 #define DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL 0x09090909
13204 #define DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT 24
13205 #define DDR_PHY_DX6GCR6_DXDQVREFR3_MASK 0x3F000000U
13207 /*Reserved. Returns zeros on reads.*/
13208 #undef DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL
13209 #undef DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT
13210 #undef DDR_PHY_DX6GCR6_RESERVED_23_22_MASK
13211 #define DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL 0x09090909
13212 #define DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT 22
13213 #define DDR_PHY_DX6GCR6_RESERVED_23_22_MASK 0x00C00000U
13215 /*DRAM DQ VREF Select for Rank2*/
13216 #undef DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL
13217 #undef DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT
13218 #undef DDR_PHY_DX6GCR6_DXDQVREFR2_MASK
13219 #define DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL 0x09090909
13220 #define DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT 16
13221 #define DDR_PHY_DX6GCR6_DXDQVREFR2_MASK 0x003F0000U
13223 /*Reserved. Returns zeros on reads.*/
13224 #undef DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL
13225 #undef DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT
13226 #undef DDR_PHY_DX6GCR6_RESERVED_15_14_MASK
13227 #define DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL 0x09090909
13228 #define DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT 14
13229 #define DDR_PHY_DX6GCR6_RESERVED_15_14_MASK 0x0000C000U
13231 /*DRAM DQ VREF Select for Rank1*/
13232 #undef DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL
13233 #undef DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT
13234 #undef DDR_PHY_DX6GCR6_DXDQVREFR1_MASK
13235 #define DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL 0x09090909
13236 #define DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT 8
13237 #define DDR_PHY_DX6GCR6_DXDQVREFR1_MASK 0x00003F00U
13239 /*Reserved. Returns zeros on reads.*/
13240 #undef DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL
13241 #undef DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT
13242 #undef DDR_PHY_DX6GCR6_RESERVED_7_6_MASK
13243 #define DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL 0x09090909
13244 #define DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT 6
13245 #define DDR_PHY_DX6GCR6_RESERVED_7_6_MASK 0x000000C0U
13247 /*DRAM DQ VREF Select for Rank0*/
13248 #undef DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL
13249 #undef DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT
13250 #undef DDR_PHY_DX6GCR6_DXDQVREFR0_MASK
13251 #define DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL 0x09090909
13252 #define DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT 0
13253 #define DDR_PHY_DX6GCR6_DXDQVREFR0_MASK 0x0000003FU
13255 /*Reserved. Return zeroes on reads.*/
13256 #undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_DEFVAL
13257 #undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT
13258 #undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK
13259 #define DDR_PHY_DX6LCDLR2_RESERVED_31_25_DEFVAL 0x00000000
13260 #define DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT 25
13261 #define DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK 0xFE000000U
13263 /*Reserved. Caution, do not write to this register field.*/
13264 #undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_DEFVAL
13265 #undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT
13266 #undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK
13267 #define DDR_PHY_DX6LCDLR2_RESERVED_24_16_DEFVAL 0x00000000
13268 #define DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT 16
13269 #define DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK 0x01FF0000U
13271 /*Reserved. Return zeroes on reads.*/
13272 #undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_DEFVAL
13273 #undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT
13274 #undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK
13275 #define DDR_PHY_DX6LCDLR2_RESERVED_15_9_DEFVAL 0x00000000
13276 #define DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT 9
13277 #define DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK 0x0000FE00U
13279 /*Read DQS Gating Delay*/
13280 #undef DDR_PHY_DX6LCDLR2_DQSGD_DEFVAL
13281 #undef DDR_PHY_DX6LCDLR2_DQSGD_SHIFT
13282 #undef DDR_PHY_DX6LCDLR2_DQSGD_MASK
13283 #define DDR_PHY_DX6LCDLR2_DQSGD_DEFVAL 0x00000000
13284 #define DDR_PHY_DX6LCDLR2_DQSGD_SHIFT 0
13285 #define DDR_PHY_DX6LCDLR2_DQSGD_MASK 0x000001FFU
13287 /*Reserved. Return zeroes on reads.*/
13288 #undef DDR_PHY_DX6GTR0_RESERVED_31_24_DEFVAL
13289 #undef DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT
13290 #undef DDR_PHY_DX6GTR0_RESERVED_31_24_MASK
13291 #define DDR_PHY_DX6GTR0_RESERVED_31_24_DEFVAL 0x00020000
13292 #define DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT 27
13293 #define DDR_PHY_DX6GTR0_RESERVED_31_24_MASK 0xF8000000U
13295 /*DQ Write Path Latency Pipeline*/
13296 #undef DDR_PHY_DX6GTR0_WDQSL_DEFVAL
13297 #undef DDR_PHY_DX6GTR0_WDQSL_SHIFT
13298 #undef DDR_PHY_DX6GTR0_WDQSL_MASK
13299 #define DDR_PHY_DX6GTR0_WDQSL_DEFVAL 0x00020000
13300 #define DDR_PHY_DX6GTR0_WDQSL_SHIFT 24
13301 #define DDR_PHY_DX6GTR0_WDQSL_MASK 0x07000000U
13303 /*Reserved. Caution, do not write to this register field.*/
13304 #undef DDR_PHY_DX6GTR0_RESERVED_23_20_DEFVAL
13305 #undef DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT
13306 #undef DDR_PHY_DX6GTR0_RESERVED_23_20_MASK
13307 #define DDR_PHY_DX6GTR0_RESERVED_23_20_DEFVAL 0x00020000
13308 #define DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT 20
13309 #define DDR_PHY_DX6GTR0_RESERVED_23_20_MASK 0x00F00000U
13311 /*Write Leveling System Latency*/
13312 #undef DDR_PHY_DX6GTR0_WLSL_DEFVAL
13313 #undef DDR_PHY_DX6GTR0_WLSL_SHIFT
13314 #undef DDR_PHY_DX6GTR0_WLSL_MASK
13315 #define DDR_PHY_DX6GTR0_WLSL_DEFVAL 0x00020000
13316 #define DDR_PHY_DX6GTR0_WLSL_SHIFT 16
13317 #define DDR_PHY_DX6GTR0_WLSL_MASK 0x000F0000U
13319 /*Reserved. Return zeroes on reads.*/
13320 #undef DDR_PHY_DX6GTR0_RESERVED_15_13_DEFVAL
13321 #undef DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT
13322 #undef DDR_PHY_DX6GTR0_RESERVED_15_13_MASK
13323 #define DDR_PHY_DX6GTR0_RESERVED_15_13_DEFVAL 0x00020000
13324 #define DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT 13
13325 #define DDR_PHY_DX6GTR0_RESERVED_15_13_MASK 0x0000E000U
13327 /*Reserved. Caution, do not write to this register field.*/
13328 #undef DDR_PHY_DX6GTR0_RESERVED_12_8_DEFVAL
13329 #undef DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT
13330 #undef DDR_PHY_DX6GTR0_RESERVED_12_8_MASK
13331 #define DDR_PHY_DX6GTR0_RESERVED_12_8_DEFVAL 0x00020000
13332 #define DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT 8
13333 #define DDR_PHY_DX6GTR0_RESERVED_12_8_MASK 0x00001F00U
13335 /*Reserved. Return zeroes on reads.*/
13336 #undef DDR_PHY_DX6GTR0_RESERVED_7_5_DEFVAL
13337 #undef DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT
13338 #undef DDR_PHY_DX6GTR0_RESERVED_7_5_MASK
13339 #define DDR_PHY_DX6GTR0_RESERVED_7_5_DEFVAL 0x00020000
13340 #define DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT 5
13341 #define DDR_PHY_DX6GTR0_RESERVED_7_5_MASK 0x000000E0U
13343 /*DQS Gating System Latency*/
13344 #undef DDR_PHY_DX6GTR0_DGSL_DEFVAL
13345 #undef DDR_PHY_DX6GTR0_DGSL_SHIFT
13346 #undef DDR_PHY_DX6GTR0_DGSL_MASK
13347 #define DDR_PHY_DX6GTR0_DGSL_DEFVAL 0x00020000
13348 #define DDR_PHY_DX6GTR0_DGSL_SHIFT 0
13349 #define DDR_PHY_DX6GTR0_DGSL_MASK 0x0000001FU
13351 /*Calibration Bypass*/
13352 #undef DDR_PHY_DX7GCR0_CALBYP_DEFVAL
13353 #undef DDR_PHY_DX7GCR0_CALBYP_SHIFT
13354 #undef DDR_PHY_DX7GCR0_CALBYP_MASK
13355 #define DDR_PHY_DX7GCR0_CALBYP_DEFVAL 0x40200204
13356 #define DDR_PHY_DX7GCR0_CALBYP_SHIFT 31
13357 #define DDR_PHY_DX7GCR0_CALBYP_MASK 0x80000000U
13359 /*Master Delay Line Enable*/
13360 #undef DDR_PHY_DX7GCR0_MDLEN_DEFVAL
13361 #undef DDR_PHY_DX7GCR0_MDLEN_SHIFT
13362 #undef DDR_PHY_DX7GCR0_MDLEN_MASK
13363 #define DDR_PHY_DX7GCR0_MDLEN_DEFVAL 0x40200204
13364 #define DDR_PHY_DX7GCR0_MDLEN_SHIFT 30
13365 #define DDR_PHY_DX7GCR0_MDLEN_MASK 0x40000000U
13367 /*Configurable ODT(TE) Phase Shift*/
13368 #undef DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL
13369 #undef DDR_PHY_DX7GCR0_CODTSHFT_SHIFT
13370 #undef DDR_PHY_DX7GCR0_CODTSHFT_MASK
13371 #define DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL 0x40200204
13372 #define DDR_PHY_DX7GCR0_CODTSHFT_SHIFT 28
13373 #define DDR_PHY_DX7GCR0_CODTSHFT_MASK 0x30000000U
13375 /*DQS Duty Cycle Correction*/
13376 #undef DDR_PHY_DX7GCR0_DQSDCC_DEFVAL
13377 #undef DDR_PHY_DX7GCR0_DQSDCC_SHIFT
13378 #undef DDR_PHY_DX7GCR0_DQSDCC_MASK
13379 #define DDR_PHY_DX7GCR0_DQSDCC_DEFVAL 0x40200204
13380 #define DDR_PHY_DX7GCR0_DQSDCC_SHIFT 24
13381 #define DDR_PHY_DX7GCR0_DQSDCC_MASK 0x0F000000U
13383 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
13384 #undef DDR_PHY_DX7GCR0_RDDLY_DEFVAL
13385 #undef DDR_PHY_DX7GCR0_RDDLY_SHIFT
13386 #undef DDR_PHY_DX7GCR0_RDDLY_MASK
13387 #define DDR_PHY_DX7GCR0_RDDLY_DEFVAL 0x40200204
13388 #define DDR_PHY_DX7GCR0_RDDLY_SHIFT 20
13389 #define DDR_PHY_DX7GCR0_RDDLY_MASK 0x00F00000U
13391 /*Reserved. Return zeroes on reads.*/
13392 #undef DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL
13393 #undef DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT
13394 #undef DDR_PHY_DX7GCR0_RESERVED_19_14_MASK
13395 #define DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL 0x40200204
13396 #define DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT 14
13397 #define DDR_PHY_DX7GCR0_RESERVED_19_14_MASK 0x000FC000U
13399 /*DQSNSE Power Down Receiver*/
13400 #undef DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL
13401 #undef DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT
13402 #undef DDR_PHY_DX7GCR0_DQSNSEPDR_MASK
13403 #define DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL 0x40200204
13404 #define DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT 13
13405 #define DDR_PHY_DX7GCR0_DQSNSEPDR_MASK 0x00002000U
13407 /*DQSSE Power Down Receiver*/
13408 #undef DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL
13409 #undef DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT
13410 #undef DDR_PHY_DX7GCR0_DQSSEPDR_MASK
13411 #define DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL 0x40200204
13412 #define DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT 12
13413 #define DDR_PHY_DX7GCR0_DQSSEPDR_MASK 0x00001000U
13415 /*RTT On Additive Latency*/
13416 #undef DDR_PHY_DX7GCR0_RTTOAL_DEFVAL
13417 #undef DDR_PHY_DX7GCR0_RTTOAL_SHIFT
13418 #undef DDR_PHY_DX7GCR0_RTTOAL_MASK
13419 #define DDR_PHY_DX7GCR0_RTTOAL_DEFVAL 0x40200204
13420 #define DDR_PHY_DX7GCR0_RTTOAL_SHIFT 11
13421 #define DDR_PHY_DX7GCR0_RTTOAL_MASK 0x00000800U
13423 /*RTT Output Hold*/
13424 #undef DDR_PHY_DX7GCR0_RTTOH_DEFVAL
13425 #undef DDR_PHY_DX7GCR0_RTTOH_SHIFT
13426 #undef DDR_PHY_DX7GCR0_RTTOH_MASK
13427 #define DDR_PHY_DX7GCR0_RTTOH_DEFVAL 0x40200204
13428 #define DDR_PHY_DX7GCR0_RTTOH_SHIFT 9
13429 #define DDR_PHY_DX7GCR0_RTTOH_MASK 0x00000600U
13431 /*Configurable PDR Phase Shift*/
13432 #undef DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL
13433 #undef DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT
13434 #undef DDR_PHY_DX7GCR0_CPDRSHFT_MASK
13435 #define DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL 0x40200204
13436 #define DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT 7
13437 #define DDR_PHY_DX7GCR0_CPDRSHFT_MASK 0x00000180U
13439 /*DQSR Power Down*/
13440 #undef DDR_PHY_DX7GCR0_DQSRPD_DEFVAL
13441 #undef DDR_PHY_DX7GCR0_DQSRPD_SHIFT
13442 #undef DDR_PHY_DX7GCR0_DQSRPD_MASK
13443 #define DDR_PHY_DX7GCR0_DQSRPD_DEFVAL 0x40200204
13444 #define DDR_PHY_DX7GCR0_DQSRPD_SHIFT 6
13445 #define DDR_PHY_DX7GCR0_DQSRPD_MASK 0x00000040U
13447 /*DQSG Power Down Receiver*/
13448 #undef DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL
13449 #undef DDR_PHY_DX7GCR0_DQSGPDR_SHIFT
13450 #undef DDR_PHY_DX7GCR0_DQSGPDR_MASK
13451 #define DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL 0x40200204
13452 #define DDR_PHY_DX7GCR0_DQSGPDR_SHIFT 5
13453 #define DDR_PHY_DX7GCR0_DQSGPDR_MASK 0x00000020U
13455 /*Reserved. Return zeroes on reads.*/
13456 #undef DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL
13457 #undef DDR_PHY_DX7GCR0_RESERVED_4_SHIFT
13458 #undef DDR_PHY_DX7GCR0_RESERVED_4_MASK
13459 #define DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL 0x40200204
13460 #define DDR_PHY_DX7GCR0_RESERVED_4_SHIFT 4
13461 #define DDR_PHY_DX7GCR0_RESERVED_4_MASK 0x00000010U
13463 /*DQSG On-Die Termination*/
13464 #undef DDR_PHY_DX7GCR0_DQSGODT_DEFVAL
13465 #undef DDR_PHY_DX7GCR0_DQSGODT_SHIFT
13466 #undef DDR_PHY_DX7GCR0_DQSGODT_MASK
13467 #define DDR_PHY_DX7GCR0_DQSGODT_DEFVAL 0x40200204
13468 #define DDR_PHY_DX7GCR0_DQSGODT_SHIFT 3
13469 #define DDR_PHY_DX7GCR0_DQSGODT_MASK 0x00000008U
13471 /*DQSG Output Enable*/
13472 #undef DDR_PHY_DX7GCR0_DQSGOE_DEFVAL
13473 #undef DDR_PHY_DX7GCR0_DQSGOE_SHIFT
13474 #undef DDR_PHY_DX7GCR0_DQSGOE_MASK
13475 #define DDR_PHY_DX7GCR0_DQSGOE_DEFVAL 0x40200204
13476 #define DDR_PHY_DX7GCR0_DQSGOE_SHIFT 2
13477 #define DDR_PHY_DX7GCR0_DQSGOE_MASK 0x00000004U
13479 /*Reserved. Return zeroes on reads.*/
13480 #undef DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL
13481 #undef DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT
13482 #undef DDR_PHY_DX7GCR0_RESERVED_1_0_MASK
13483 #define DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL 0x40200204
13484 #define DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT 0
13485 #define DDR_PHY_DX7GCR0_RESERVED_1_0_MASK 0x00000003U
13487 /*Enables the PDR mode for DQ[7:0]*/
13488 #undef DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL
13489 #undef DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT
13490 #undef DDR_PHY_DX7GCR1_DXPDRMODE_MASK
13491 #define DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL 0x00007FFF
13492 #define DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT 16
13493 #define DDR_PHY_DX7GCR1_DXPDRMODE_MASK 0xFFFF0000U
13495 /*Reserved. Returns zeroes on reads.*/
13496 #undef DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL
13497 #undef DDR_PHY_DX7GCR1_RESERVED_15_SHIFT
13498 #undef DDR_PHY_DX7GCR1_RESERVED_15_MASK
13499 #define DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL 0x00007FFF
13500 #define DDR_PHY_DX7GCR1_RESERVED_15_SHIFT 15
13501 #define DDR_PHY_DX7GCR1_RESERVED_15_MASK 0x00008000U
13503 /*Select the delayed or non-delayed read data strobe #*/
13504 #undef DDR_PHY_DX7GCR1_QSNSEL_DEFVAL
13505 #undef DDR_PHY_DX7GCR1_QSNSEL_SHIFT
13506 #undef DDR_PHY_DX7GCR1_QSNSEL_MASK
13507 #define DDR_PHY_DX7GCR1_QSNSEL_DEFVAL 0x00007FFF
13508 #define DDR_PHY_DX7GCR1_QSNSEL_SHIFT 14
13509 #define DDR_PHY_DX7GCR1_QSNSEL_MASK 0x00004000U
13511 /*Select the delayed or non-delayed read data strobe*/
13512 #undef DDR_PHY_DX7GCR1_QSSEL_DEFVAL
13513 #undef DDR_PHY_DX7GCR1_QSSEL_SHIFT
13514 #undef DDR_PHY_DX7GCR1_QSSEL_MASK
13515 #define DDR_PHY_DX7GCR1_QSSEL_DEFVAL 0x00007FFF
13516 #define DDR_PHY_DX7GCR1_QSSEL_SHIFT 13
13517 #define DDR_PHY_DX7GCR1_QSSEL_MASK 0x00002000U
13519 /*Enables Read Data Strobe in a byte lane*/
13520 #undef DDR_PHY_DX7GCR1_OEEN_DEFVAL
13521 #undef DDR_PHY_DX7GCR1_OEEN_SHIFT
13522 #undef DDR_PHY_DX7GCR1_OEEN_MASK
13523 #define DDR_PHY_DX7GCR1_OEEN_DEFVAL 0x00007FFF
13524 #define DDR_PHY_DX7GCR1_OEEN_SHIFT 12
13525 #define DDR_PHY_DX7GCR1_OEEN_MASK 0x00001000U
13527 /*Enables PDR in a byte lane*/
13528 #undef DDR_PHY_DX7GCR1_PDREN_DEFVAL
13529 #undef DDR_PHY_DX7GCR1_PDREN_SHIFT
13530 #undef DDR_PHY_DX7GCR1_PDREN_MASK
13531 #define DDR_PHY_DX7GCR1_PDREN_DEFVAL 0x00007FFF
13532 #define DDR_PHY_DX7GCR1_PDREN_SHIFT 11
13533 #define DDR_PHY_DX7GCR1_PDREN_MASK 0x00000800U
13535 /*Enables ODT/TE in a byte lane*/
13536 #undef DDR_PHY_DX7GCR1_TEEN_DEFVAL
13537 #undef DDR_PHY_DX7GCR1_TEEN_SHIFT
13538 #undef DDR_PHY_DX7GCR1_TEEN_MASK
13539 #define DDR_PHY_DX7GCR1_TEEN_DEFVAL 0x00007FFF
13540 #define DDR_PHY_DX7GCR1_TEEN_SHIFT 10
13541 #define DDR_PHY_DX7GCR1_TEEN_MASK 0x00000400U
13543 /*Enables Write Data strobe in a byte lane*/
13544 #undef DDR_PHY_DX7GCR1_DSEN_DEFVAL
13545 #undef DDR_PHY_DX7GCR1_DSEN_SHIFT
13546 #undef DDR_PHY_DX7GCR1_DSEN_MASK
13547 #define DDR_PHY_DX7GCR1_DSEN_DEFVAL 0x00007FFF
13548 #define DDR_PHY_DX7GCR1_DSEN_SHIFT 9
13549 #define DDR_PHY_DX7GCR1_DSEN_MASK 0x00000200U
13551 /*Enables DM pin in a byte lane*/
13552 #undef DDR_PHY_DX7GCR1_DMEN_DEFVAL
13553 #undef DDR_PHY_DX7GCR1_DMEN_SHIFT
13554 #undef DDR_PHY_DX7GCR1_DMEN_MASK
13555 #define DDR_PHY_DX7GCR1_DMEN_DEFVAL 0x00007FFF
13556 #define DDR_PHY_DX7GCR1_DMEN_SHIFT 8
13557 #define DDR_PHY_DX7GCR1_DMEN_MASK 0x00000100U
13559 /*Enables DQ corresponding to each bit in a byte*/
13560 #undef DDR_PHY_DX7GCR1_DQEN_DEFVAL
13561 #undef DDR_PHY_DX7GCR1_DQEN_SHIFT
13562 #undef DDR_PHY_DX7GCR1_DQEN_MASK
13563 #define DDR_PHY_DX7GCR1_DQEN_DEFVAL 0x00007FFF
13564 #define DDR_PHY_DX7GCR1_DQEN_SHIFT 0
13565 #define DDR_PHY_DX7GCR1_DQEN_MASK 0x000000FFU
13567 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
13568 #undef DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL
13569 #undef DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT
13570 #undef DDR_PHY_DX7GCR4_RESERVED_31_29_MASK
13571 #define DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL 0x0E00003C
13572 #define DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT 29
13573 #define DDR_PHY_DX7GCR4_RESERVED_31_29_MASK 0xE0000000U
13575 /*Byte Lane VREF Pad Enable*/
13576 #undef DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL
13577 #undef DDR_PHY_DX7GCR4_DXREFPEN_SHIFT
13578 #undef DDR_PHY_DX7GCR4_DXREFPEN_MASK
13579 #define DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL 0x0E00003C
13580 #define DDR_PHY_DX7GCR4_DXREFPEN_SHIFT 28
13581 #define DDR_PHY_DX7GCR4_DXREFPEN_MASK 0x10000000U
13583 /*Byte Lane Internal VREF Enable*/
13584 #undef DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL
13585 #undef DDR_PHY_DX7GCR4_DXREFEEN_SHIFT
13586 #undef DDR_PHY_DX7GCR4_DXREFEEN_MASK
13587 #define DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL 0x0E00003C
13588 #define DDR_PHY_DX7GCR4_DXREFEEN_SHIFT 26
13589 #define DDR_PHY_DX7GCR4_DXREFEEN_MASK 0x0C000000U
13591 /*Byte Lane Single-End VREF Enable*/
13592 #undef DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL
13593 #undef DDR_PHY_DX7GCR4_DXREFSEN_SHIFT
13594 #undef DDR_PHY_DX7GCR4_DXREFSEN_MASK
13595 #define DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL 0x0E00003C
13596 #define DDR_PHY_DX7GCR4_DXREFSEN_SHIFT 25
13597 #define DDR_PHY_DX7GCR4_DXREFSEN_MASK 0x02000000U
13599 /*Reserved. Returns zeros on reads.*/
13600 #undef DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL
13601 #undef DDR_PHY_DX7GCR4_RESERVED_24_SHIFT
13602 #undef DDR_PHY_DX7GCR4_RESERVED_24_MASK
13603 #define DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL 0x0E00003C
13604 #define DDR_PHY_DX7GCR4_RESERVED_24_SHIFT 24
13605 #define DDR_PHY_DX7GCR4_RESERVED_24_MASK 0x01000000U
13607 /*External VREF generator REFSEL range select*/
13608 #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL
13609 #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT
13610 #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK
13611 #define DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C
13612 #define DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT 23
13613 #define DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK 0x00800000U
13615 /*Byte Lane External VREF Select*/
13616 #undef DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL
13617 #undef DDR_PHY_DX7GCR4_DXREFESEL_SHIFT
13618 #undef DDR_PHY_DX7GCR4_DXREFESEL_MASK
13619 #define DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL 0x0E00003C
13620 #define DDR_PHY_DX7GCR4_DXREFESEL_SHIFT 16
13621 #define DDR_PHY_DX7GCR4_DXREFESEL_MASK 0x007F0000U
13623 /*Single ended VREF generator REFSEL range select*/
13624 #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL
13625 #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT
13626 #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK
13627 #define DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C
13628 #define DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT 15
13629 #define DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK 0x00008000U
13631 /*Byte Lane Single-End VREF Select*/
13632 #undef DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL
13633 #undef DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT
13634 #undef DDR_PHY_DX7GCR4_DXREFSSEL_MASK
13635 #define DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL 0x0E00003C
13636 #define DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT 8
13637 #define DDR_PHY_DX7GCR4_DXREFSSEL_MASK 0x00007F00U
13639 /*Reserved. Returns zeros on reads.*/
13640 #undef DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL
13641 #undef DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT
13642 #undef DDR_PHY_DX7GCR4_RESERVED_7_6_MASK
13643 #define DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL 0x0E00003C
13644 #define DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT 6
13645 #define DDR_PHY_DX7GCR4_RESERVED_7_6_MASK 0x000000C0U
13647 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
13648 #undef DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL
13649 #undef DDR_PHY_DX7GCR4_DXREFIEN_SHIFT
13650 #undef DDR_PHY_DX7GCR4_DXREFIEN_MASK
13651 #define DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL 0x0E00003C
13652 #define DDR_PHY_DX7GCR4_DXREFIEN_SHIFT 2
13653 #define DDR_PHY_DX7GCR4_DXREFIEN_MASK 0x0000003CU
13655 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
13656 #undef DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL
13657 #undef DDR_PHY_DX7GCR4_DXREFIMON_SHIFT
13658 #undef DDR_PHY_DX7GCR4_DXREFIMON_MASK
13659 #define DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL 0x0E00003C
13660 #define DDR_PHY_DX7GCR4_DXREFIMON_SHIFT 0
13661 #define DDR_PHY_DX7GCR4_DXREFIMON_MASK 0x00000003U
13663 /*Reserved. Returns zeros on reads.*/
13664 #undef DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL
13665 #undef DDR_PHY_DX7GCR5_RESERVED_31_SHIFT
13666 #undef DDR_PHY_DX7GCR5_RESERVED_31_MASK
13667 #define DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL 0x09090909
13668 #define DDR_PHY_DX7GCR5_RESERVED_31_SHIFT 31
13669 #define DDR_PHY_DX7GCR5_RESERVED_31_MASK 0x80000000U
13671 /*Byte Lane internal VREF Select for Rank 3*/
13672 #undef DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL
13673 #undef DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT
13674 #undef DDR_PHY_DX7GCR5_DXREFISELR3_MASK
13675 #define DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL 0x09090909
13676 #define DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT 24
13677 #define DDR_PHY_DX7GCR5_DXREFISELR3_MASK 0x7F000000U
13679 /*Reserved. Returns zeros on reads.*/
13680 #undef DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL
13681 #undef DDR_PHY_DX7GCR5_RESERVED_23_SHIFT
13682 #undef DDR_PHY_DX7GCR5_RESERVED_23_MASK
13683 #define DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL 0x09090909
13684 #define DDR_PHY_DX7GCR5_RESERVED_23_SHIFT 23
13685 #define DDR_PHY_DX7GCR5_RESERVED_23_MASK 0x00800000U
13687 /*Byte Lane internal VREF Select for Rank 2*/
13688 #undef DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL
13689 #undef DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT
13690 #undef DDR_PHY_DX7GCR5_DXREFISELR2_MASK
13691 #define DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL 0x09090909
13692 #define DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT 16
13693 #define DDR_PHY_DX7GCR5_DXREFISELR2_MASK 0x007F0000U
13695 /*Reserved. Returns zeros on reads.*/
13696 #undef DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL
13697 #undef DDR_PHY_DX7GCR5_RESERVED_15_SHIFT
13698 #undef DDR_PHY_DX7GCR5_RESERVED_15_MASK
13699 #define DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL 0x09090909
13700 #define DDR_PHY_DX7GCR5_RESERVED_15_SHIFT 15
13701 #define DDR_PHY_DX7GCR5_RESERVED_15_MASK 0x00008000U
13703 /*Byte Lane internal VREF Select for Rank 1*/
13704 #undef DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL
13705 #undef DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT
13706 #undef DDR_PHY_DX7GCR5_DXREFISELR1_MASK
13707 #define DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL 0x09090909
13708 #define DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT 8
13709 #define DDR_PHY_DX7GCR5_DXREFISELR1_MASK 0x00007F00U
13711 /*Reserved. Returns zeros on reads.*/
13712 #undef DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL
13713 #undef DDR_PHY_DX7GCR5_RESERVED_7_SHIFT
13714 #undef DDR_PHY_DX7GCR5_RESERVED_7_MASK
13715 #define DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL 0x09090909
13716 #define DDR_PHY_DX7GCR5_RESERVED_7_SHIFT 7
13717 #define DDR_PHY_DX7GCR5_RESERVED_7_MASK 0x00000080U
13719 /*Byte Lane internal VREF Select for Rank 0*/
13720 #undef DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL
13721 #undef DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT
13722 #undef DDR_PHY_DX7GCR5_DXREFISELR0_MASK
13723 #define DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL 0x09090909
13724 #define DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT 0
13725 #define DDR_PHY_DX7GCR5_DXREFISELR0_MASK 0x0000007FU
13727 /*Reserved. Returns zeros on reads.*/
13728 #undef DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL
13729 #undef DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT
13730 #undef DDR_PHY_DX7GCR6_RESERVED_31_30_MASK
13731 #define DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL 0x09090909
13732 #define DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT 30
13733 #define DDR_PHY_DX7GCR6_RESERVED_31_30_MASK 0xC0000000U
13735 /*DRAM DQ VREF Select for Rank3*/
13736 #undef DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL
13737 #undef DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT
13738 #undef DDR_PHY_DX7GCR6_DXDQVREFR3_MASK
13739 #define DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL 0x09090909
13740 #define DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT 24
13741 #define DDR_PHY_DX7GCR6_DXDQVREFR3_MASK 0x3F000000U
13743 /*Reserved. Returns zeros on reads.*/
13744 #undef DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL
13745 #undef DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT
13746 #undef DDR_PHY_DX7GCR6_RESERVED_23_22_MASK
13747 #define DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL 0x09090909
13748 #define DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT 22
13749 #define DDR_PHY_DX7GCR6_RESERVED_23_22_MASK 0x00C00000U
13751 /*DRAM DQ VREF Select for Rank2*/
13752 #undef DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL
13753 #undef DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT
13754 #undef DDR_PHY_DX7GCR6_DXDQVREFR2_MASK
13755 #define DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL 0x09090909
13756 #define DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT 16
13757 #define DDR_PHY_DX7GCR6_DXDQVREFR2_MASK 0x003F0000U
13759 /*Reserved. Returns zeros on reads.*/
13760 #undef DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL
13761 #undef DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT
13762 #undef DDR_PHY_DX7GCR6_RESERVED_15_14_MASK
13763 #define DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL 0x09090909
13764 #define DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT 14
13765 #define DDR_PHY_DX7GCR6_RESERVED_15_14_MASK 0x0000C000U
13767 /*DRAM DQ VREF Select for Rank1*/
13768 #undef DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL
13769 #undef DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT
13770 #undef DDR_PHY_DX7GCR6_DXDQVREFR1_MASK
13771 #define DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL 0x09090909
13772 #define DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT 8
13773 #define DDR_PHY_DX7GCR6_DXDQVREFR1_MASK 0x00003F00U
13775 /*Reserved. Returns zeros on reads.*/
13776 #undef DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL
13777 #undef DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT
13778 #undef DDR_PHY_DX7GCR6_RESERVED_7_6_MASK
13779 #define DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL 0x09090909
13780 #define DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT 6
13781 #define DDR_PHY_DX7GCR6_RESERVED_7_6_MASK 0x000000C0U
13783 /*DRAM DQ VREF Select for Rank0*/
13784 #undef DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL
13785 #undef DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT
13786 #undef DDR_PHY_DX7GCR6_DXDQVREFR0_MASK
13787 #define DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL 0x09090909
13788 #define DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT 0
13789 #define DDR_PHY_DX7GCR6_DXDQVREFR0_MASK 0x0000003FU
13791 /*Reserved. Return zeroes on reads.*/
13792 #undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_DEFVAL
13793 #undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT
13794 #undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK
13795 #define DDR_PHY_DX7LCDLR2_RESERVED_31_25_DEFVAL 0x00000000
13796 #define DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT 25
13797 #define DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK 0xFE000000U
13799 /*Reserved. Caution, do not write to this register field.*/
13800 #undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_DEFVAL
13801 #undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT
13802 #undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK
13803 #define DDR_PHY_DX7LCDLR2_RESERVED_24_16_DEFVAL 0x00000000
13804 #define DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT 16
13805 #define DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK 0x01FF0000U
13807 /*Reserved. Return zeroes on reads.*/
13808 #undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_DEFVAL
13809 #undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT
13810 #undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK
13811 #define DDR_PHY_DX7LCDLR2_RESERVED_15_9_DEFVAL 0x00000000
13812 #define DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT 9
13813 #define DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK 0x0000FE00U
13815 /*Read DQS Gating Delay*/
13816 #undef DDR_PHY_DX7LCDLR2_DQSGD_DEFVAL
13817 #undef DDR_PHY_DX7LCDLR2_DQSGD_SHIFT
13818 #undef DDR_PHY_DX7LCDLR2_DQSGD_MASK
13819 #define DDR_PHY_DX7LCDLR2_DQSGD_DEFVAL 0x00000000
13820 #define DDR_PHY_DX7LCDLR2_DQSGD_SHIFT 0
13821 #define DDR_PHY_DX7LCDLR2_DQSGD_MASK 0x000001FFU
13823 /*Reserved. Return zeroes on reads.*/
13824 #undef DDR_PHY_DX7GTR0_RESERVED_31_24_DEFVAL
13825 #undef DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT
13826 #undef DDR_PHY_DX7GTR0_RESERVED_31_24_MASK
13827 #define DDR_PHY_DX7GTR0_RESERVED_31_24_DEFVAL 0x00020000
13828 #define DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT 27
13829 #define DDR_PHY_DX7GTR0_RESERVED_31_24_MASK 0xF8000000U
13831 /*DQ Write Path Latency Pipeline*/
13832 #undef DDR_PHY_DX7GTR0_WDQSL_DEFVAL
13833 #undef DDR_PHY_DX7GTR0_WDQSL_SHIFT
13834 #undef DDR_PHY_DX7GTR0_WDQSL_MASK
13835 #define DDR_PHY_DX7GTR0_WDQSL_DEFVAL 0x00020000
13836 #define DDR_PHY_DX7GTR0_WDQSL_SHIFT 24
13837 #define DDR_PHY_DX7GTR0_WDQSL_MASK 0x07000000U
13839 /*Reserved. Caution, do not write to this register field.*/
13840 #undef DDR_PHY_DX7GTR0_RESERVED_23_20_DEFVAL
13841 #undef DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT
13842 #undef DDR_PHY_DX7GTR0_RESERVED_23_20_MASK
13843 #define DDR_PHY_DX7GTR0_RESERVED_23_20_DEFVAL 0x00020000
13844 #define DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT 20
13845 #define DDR_PHY_DX7GTR0_RESERVED_23_20_MASK 0x00F00000U
13847 /*Write Leveling System Latency*/
13848 #undef DDR_PHY_DX7GTR0_WLSL_DEFVAL
13849 #undef DDR_PHY_DX7GTR0_WLSL_SHIFT
13850 #undef DDR_PHY_DX7GTR0_WLSL_MASK
13851 #define DDR_PHY_DX7GTR0_WLSL_DEFVAL 0x00020000
13852 #define DDR_PHY_DX7GTR0_WLSL_SHIFT 16
13853 #define DDR_PHY_DX7GTR0_WLSL_MASK 0x000F0000U
13855 /*Reserved. Return zeroes on reads.*/
13856 #undef DDR_PHY_DX7GTR0_RESERVED_15_13_DEFVAL
13857 #undef DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT
13858 #undef DDR_PHY_DX7GTR0_RESERVED_15_13_MASK
13859 #define DDR_PHY_DX7GTR0_RESERVED_15_13_DEFVAL 0x00020000
13860 #define DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT 13
13861 #define DDR_PHY_DX7GTR0_RESERVED_15_13_MASK 0x0000E000U
13863 /*Reserved. Caution, do not write to this register field.*/
13864 #undef DDR_PHY_DX7GTR0_RESERVED_12_8_DEFVAL
13865 #undef DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT
13866 #undef DDR_PHY_DX7GTR0_RESERVED_12_8_MASK
13867 #define DDR_PHY_DX7GTR0_RESERVED_12_8_DEFVAL 0x00020000
13868 #define DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT 8
13869 #define DDR_PHY_DX7GTR0_RESERVED_12_8_MASK 0x00001F00U
13871 /*Reserved. Return zeroes on reads.*/
13872 #undef DDR_PHY_DX7GTR0_RESERVED_7_5_DEFVAL
13873 #undef DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT
13874 #undef DDR_PHY_DX7GTR0_RESERVED_7_5_MASK
13875 #define DDR_PHY_DX7GTR0_RESERVED_7_5_DEFVAL 0x00020000
13876 #define DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT 5
13877 #define DDR_PHY_DX7GTR0_RESERVED_7_5_MASK 0x000000E0U
13879 /*DQS Gating System Latency*/
13880 #undef DDR_PHY_DX7GTR0_DGSL_DEFVAL
13881 #undef DDR_PHY_DX7GTR0_DGSL_SHIFT
13882 #undef DDR_PHY_DX7GTR0_DGSL_MASK
13883 #define DDR_PHY_DX7GTR0_DGSL_DEFVAL 0x00020000
13884 #define DDR_PHY_DX7GTR0_DGSL_SHIFT 0
13885 #define DDR_PHY_DX7GTR0_DGSL_MASK 0x0000001FU
13887 /*Calibration Bypass*/
13888 #undef DDR_PHY_DX8GCR0_CALBYP_DEFVAL
13889 #undef DDR_PHY_DX8GCR0_CALBYP_SHIFT
13890 #undef DDR_PHY_DX8GCR0_CALBYP_MASK
13891 #define DDR_PHY_DX8GCR0_CALBYP_DEFVAL 0x40200204
13892 #define DDR_PHY_DX8GCR0_CALBYP_SHIFT 31
13893 #define DDR_PHY_DX8GCR0_CALBYP_MASK 0x80000000U
13895 /*Master Delay Line Enable*/
13896 #undef DDR_PHY_DX8GCR0_MDLEN_DEFVAL
13897 #undef DDR_PHY_DX8GCR0_MDLEN_SHIFT
13898 #undef DDR_PHY_DX8GCR0_MDLEN_MASK
13899 #define DDR_PHY_DX8GCR0_MDLEN_DEFVAL 0x40200204
13900 #define DDR_PHY_DX8GCR0_MDLEN_SHIFT 30
13901 #define DDR_PHY_DX8GCR0_MDLEN_MASK 0x40000000U
13903 /*Configurable ODT(TE) Phase Shift*/
13904 #undef DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL
13905 #undef DDR_PHY_DX8GCR0_CODTSHFT_SHIFT
13906 #undef DDR_PHY_DX8GCR0_CODTSHFT_MASK
13907 #define DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL 0x40200204
13908 #define DDR_PHY_DX8GCR0_CODTSHFT_SHIFT 28
13909 #define DDR_PHY_DX8GCR0_CODTSHFT_MASK 0x30000000U
13911 /*DQS Duty Cycle Correction*/
13912 #undef DDR_PHY_DX8GCR0_DQSDCC_DEFVAL
13913 #undef DDR_PHY_DX8GCR0_DQSDCC_SHIFT
13914 #undef DDR_PHY_DX8GCR0_DQSDCC_MASK
13915 #define DDR_PHY_DX8GCR0_DQSDCC_DEFVAL 0x40200204
13916 #define DDR_PHY_DX8GCR0_DQSDCC_SHIFT 24
13917 #define DDR_PHY_DX8GCR0_DQSDCC_MASK 0x0F000000U
13919 /*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
13920 #undef DDR_PHY_DX8GCR0_RDDLY_DEFVAL
13921 #undef DDR_PHY_DX8GCR0_RDDLY_SHIFT
13922 #undef DDR_PHY_DX8GCR0_RDDLY_MASK
13923 #define DDR_PHY_DX8GCR0_RDDLY_DEFVAL 0x40200204
13924 #define DDR_PHY_DX8GCR0_RDDLY_SHIFT 20
13925 #define DDR_PHY_DX8GCR0_RDDLY_MASK 0x00F00000U
13927 /*Reserved. Return zeroes on reads.*/
13928 #undef DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL
13929 #undef DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT
13930 #undef DDR_PHY_DX8GCR0_RESERVED_19_14_MASK
13931 #define DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL 0x40200204
13932 #define DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT 14
13933 #define DDR_PHY_DX8GCR0_RESERVED_19_14_MASK 0x000FC000U
13935 /*DQSNSE Power Down Receiver*/
13936 #undef DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL
13937 #undef DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT
13938 #undef DDR_PHY_DX8GCR0_DQSNSEPDR_MASK
13939 #define DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL 0x40200204
13940 #define DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT 13
13941 #define DDR_PHY_DX8GCR0_DQSNSEPDR_MASK 0x00002000U
13943 /*DQSSE Power Down Receiver*/
13944 #undef DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL
13945 #undef DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT
13946 #undef DDR_PHY_DX8GCR0_DQSSEPDR_MASK
13947 #define DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL 0x40200204
13948 #define DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT 12
13949 #define DDR_PHY_DX8GCR0_DQSSEPDR_MASK 0x00001000U
13951 /*RTT On Additive Latency*/
13952 #undef DDR_PHY_DX8GCR0_RTTOAL_DEFVAL
13953 #undef DDR_PHY_DX8GCR0_RTTOAL_SHIFT
13954 #undef DDR_PHY_DX8GCR0_RTTOAL_MASK
13955 #define DDR_PHY_DX8GCR0_RTTOAL_DEFVAL 0x40200204
13956 #define DDR_PHY_DX8GCR0_RTTOAL_SHIFT 11
13957 #define DDR_PHY_DX8GCR0_RTTOAL_MASK 0x00000800U
13959 /*RTT Output Hold*/
13960 #undef DDR_PHY_DX8GCR0_RTTOH_DEFVAL
13961 #undef DDR_PHY_DX8GCR0_RTTOH_SHIFT
13962 #undef DDR_PHY_DX8GCR0_RTTOH_MASK
13963 #define DDR_PHY_DX8GCR0_RTTOH_DEFVAL 0x40200204
13964 #define DDR_PHY_DX8GCR0_RTTOH_SHIFT 9
13965 #define DDR_PHY_DX8GCR0_RTTOH_MASK 0x00000600U
13967 /*Configurable PDR Phase Shift*/
13968 #undef DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL
13969 #undef DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT
13970 #undef DDR_PHY_DX8GCR0_CPDRSHFT_MASK
13971 #define DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL 0x40200204
13972 #define DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT 7
13973 #define DDR_PHY_DX8GCR0_CPDRSHFT_MASK 0x00000180U
13975 /*DQSR Power Down*/
13976 #undef DDR_PHY_DX8GCR0_DQSRPD_DEFVAL
13977 #undef DDR_PHY_DX8GCR0_DQSRPD_SHIFT
13978 #undef DDR_PHY_DX8GCR0_DQSRPD_MASK
13979 #define DDR_PHY_DX8GCR0_DQSRPD_DEFVAL 0x40200204
13980 #define DDR_PHY_DX8GCR0_DQSRPD_SHIFT 6
13981 #define DDR_PHY_DX8GCR0_DQSRPD_MASK 0x00000040U
13983 /*DQSG Power Down Receiver*/
13984 #undef DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL
13985 #undef DDR_PHY_DX8GCR0_DQSGPDR_SHIFT
13986 #undef DDR_PHY_DX8GCR0_DQSGPDR_MASK
13987 #define DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL 0x40200204
13988 #define DDR_PHY_DX8GCR0_DQSGPDR_SHIFT 5
13989 #define DDR_PHY_DX8GCR0_DQSGPDR_MASK 0x00000020U
13991 /*Reserved. Return zeroes on reads.*/
13992 #undef DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL
13993 #undef DDR_PHY_DX8GCR0_RESERVED_4_SHIFT
13994 #undef DDR_PHY_DX8GCR0_RESERVED_4_MASK
13995 #define DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL 0x40200204
13996 #define DDR_PHY_DX8GCR0_RESERVED_4_SHIFT 4
13997 #define DDR_PHY_DX8GCR0_RESERVED_4_MASK 0x00000010U
13999 /*DQSG On-Die Termination*/
14000 #undef DDR_PHY_DX8GCR0_DQSGODT_DEFVAL
14001 #undef DDR_PHY_DX8GCR0_DQSGODT_SHIFT
14002 #undef DDR_PHY_DX8GCR0_DQSGODT_MASK
14003 #define DDR_PHY_DX8GCR0_DQSGODT_DEFVAL 0x40200204
14004 #define DDR_PHY_DX8GCR0_DQSGODT_SHIFT 3
14005 #define DDR_PHY_DX8GCR0_DQSGODT_MASK 0x00000008U
14007 /*DQSG Output Enable*/
14008 #undef DDR_PHY_DX8GCR0_DQSGOE_DEFVAL
14009 #undef DDR_PHY_DX8GCR0_DQSGOE_SHIFT
14010 #undef DDR_PHY_DX8GCR0_DQSGOE_MASK
14011 #define DDR_PHY_DX8GCR0_DQSGOE_DEFVAL 0x40200204
14012 #define DDR_PHY_DX8GCR0_DQSGOE_SHIFT 2
14013 #define DDR_PHY_DX8GCR0_DQSGOE_MASK 0x00000004U
14015 /*Reserved. Return zeroes on reads.*/
14016 #undef DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL
14017 #undef DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT
14018 #undef DDR_PHY_DX8GCR0_RESERVED_1_0_MASK
14019 #define DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL 0x40200204
14020 #define DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT 0
14021 #define DDR_PHY_DX8GCR0_RESERVED_1_0_MASK 0x00000003U
14023 /*Enables the PDR mode for DQ[7:0]*/
14024 #undef DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL
14025 #undef DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT
14026 #undef DDR_PHY_DX8GCR1_DXPDRMODE_MASK
14027 #define DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL 0x00007FFF
14028 #define DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT 16
14029 #define DDR_PHY_DX8GCR1_DXPDRMODE_MASK 0xFFFF0000U
14031 /*Reserved. Returns zeroes on reads.*/
14032 #undef DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL
14033 #undef DDR_PHY_DX8GCR1_RESERVED_15_SHIFT
14034 #undef DDR_PHY_DX8GCR1_RESERVED_15_MASK
14035 #define DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL 0x00007FFF
14036 #define DDR_PHY_DX8GCR1_RESERVED_15_SHIFT 15
14037 #define DDR_PHY_DX8GCR1_RESERVED_15_MASK 0x00008000U
14039 /*Select the delayed or non-delayed read data strobe #*/
14040 #undef DDR_PHY_DX8GCR1_QSNSEL_DEFVAL
14041 #undef DDR_PHY_DX8GCR1_QSNSEL_SHIFT
14042 #undef DDR_PHY_DX8GCR1_QSNSEL_MASK
14043 #define DDR_PHY_DX8GCR1_QSNSEL_DEFVAL 0x00007FFF
14044 #define DDR_PHY_DX8GCR1_QSNSEL_SHIFT 14
14045 #define DDR_PHY_DX8GCR1_QSNSEL_MASK 0x00004000U
14047 /*Select the delayed or non-delayed read data strobe*/
14048 #undef DDR_PHY_DX8GCR1_QSSEL_DEFVAL
14049 #undef DDR_PHY_DX8GCR1_QSSEL_SHIFT
14050 #undef DDR_PHY_DX8GCR1_QSSEL_MASK
14051 #define DDR_PHY_DX8GCR1_QSSEL_DEFVAL 0x00007FFF
14052 #define DDR_PHY_DX8GCR1_QSSEL_SHIFT 13
14053 #define DDR_PHY_DX8GCR1_QSSEL_MASK 0x00002000U
14055 /*Enables Read Data Strobe in a byte lane*/
14056 #undef DDR_PHY_DX8GCR1_OEEN_DEFVAL
14057 #undef DDR_PHY_DX8GCR1_OEEN_SHIFT
14058 #undef DDR_PHY_DX8GCR1_OEEN_MASK
14059 #define DDR_PHY_DX8GCR1_OEEN_DEFVAL 0x00007FFF
14060 #define DDR_PHY_DX8GCR1_OEEN_SHIFT 12
14061 #define DDR_PHY_DX8GCR1_OEEN_MASK 0x00001000U
14063 /*Enables PDR in a byte lane*/
14064 #undef DDR_PHY_DX8GCR1_PDREN_DEFVAL
14065 #undef DDR_PHY_DX8GCR1_PDREN_SHIFT
14066 #undef DDR_PHY_DX8GCR1_PDREN_MASK
14067 #define DDR_PHY_DX8GCR1_PDREN_DEFVAL 0x00007FFF
14068 #define DDR_PHY_DX8GCR1_PDREN_SHIFT 11
14069 #define DDR_PHY_DX8GCR1_PDREN_MASK 0x00000800U
14071 /*Enables ODT/TE in a byte lane*/
14072 #undef DDR_PHY_DX8GCR1_TEEN_DEFVAL
14073 #undef DDR_PHY_DX8GCR1_TEEN_SHIFT
14074 #undef DDR_PHY_DX8GCR1_TEEN_MASK
14075 #define DDR_PHY_DX8GCR1_TEEN_DEFVAL 0x00007FFF
14076 #define DDR_PHY_DX8GCR1_TEEN_SHIFT 10
14077 #define DDR_PHY_DX8GCR1_TEEN_MASK 0x00000400U
14079 /*Enables Write Data strobe in a byte lane*/
14080 #undef DDR_PHY_DX8GCR1_DSEN_DEFVAL
14081 #undef DDR_PHY_DX8GCR1_DSEN_SHIFT
14082 #undef DDR_PHY_DX8GCR1_DSEN_MASK
14083 #define DDR_PHY_DX8GCR1_DSEN_DEFVAL 0x00007FFF
14084 #define DDR_PHY_DX8GCR1_DSEN_SHIFT 9
14085 #define DDR_PHY_DX8GCR1_DSEN_MASK 0x00000200U
14087 /*Enables DM pin in a byte lane*/
14088 #undef DDR_PHY_DX8GCR1_DMEN_DEFVAL
14089 #undef DDR_PHY_DX8GCR1_DMEN_SHIFT
14090 #undef DDR_PHY_DX8GCR1_DMEN_MASK
14091 #define DDR_PHY_DX8GCR1_DMEN_DEFVAL 0x00007FFF
14092 #define DDR_PHY_DX8GCR1_DMEN_SHIFT 8
14093 #define DDR_PHY_DX8GCR1_DMEN_MASK 0x00000100U
14095 /*Enables DQ corresponding to each bit in a byte*/
14096 #undef DDR_PHY_DX8GCR1_DQEN_DEFVAL
14097 #undef DDR_PHY_DX8GCR1_DQEN_SHIFT
14098 #undef DDR_PHY_DX8GCR1_DQEN_MASK
14099 #define DDR_PHY_DX8GCR1_DQEN_DEFVAL 0x00007FFF
14100 #define DDR_PHY_DX8GCR1_DQEN_SHIFT 0
14101 #define DDR_PHY_DX8GCR1_DQEN_MASK 0x000000FFU
14103 /*Byte lane VREF IOM (Used only by D4MU IOs)*/
14104 #undef DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL
14105 #undef DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT
14106 #undef DDR_PHY_DX8GCR4_RESERVED_31_29_MASK
14107 #define DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL 0x0E00003C
14108 #define DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT 29
14109 #define DDR_PHY_DX8GCR4_RESERVED_31_29_MASK 0xE0000000U
14111 /*Byte Lane VREF Pad Enable*/
14112 #undef DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL
14113 #undef DDR_PHY_DX8GCR4_DXREFPEN_SHIFT
14114 #undef DDR_PHY_DX8GCR4_DXREFPEN_MASK
14115 #define DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL 0x0E00003C
14116 #define DDR_PHY_DX8GCR4_DXREFPEN_SHIFT 28
14117 #define DDR_PHY_DX8GCR4_DXREFPEN_MASK 0x10000000U
14119 /*Byte Lane Internal VREF Enable*/
14120 #undef DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL
14121 #undef DDR_PHY_DX8GCR4_DXREFEEN_SHIFT
14122 #undef DDR_PHY_DX8GCR4_DXREFEEN_MASK
14123 #define DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL 0x0E00003C
14124 #define DDR_PHY_DX8GCR4_DXREFEEN_SHIFT 26
14125 #define DDR_PHY_DX8GCR4_DXREFEEN_MASK 0x0C000000U
14127 /*Byte Lane Single-End VREF Enable*/
14128 #undef DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL
14129 #undef DDR_PHY_DX8GCR4_DXREFSEN_SHIFT
14130 #undef DDR_PHY_DX8GCR4_DXREFSEN_MASK
14131 #define DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL 0x0E00003C
14132 #define DDR_PHY_DX8GCR4_DXREFSEN_SHIFT 25
14133 #define DDR_PHY_DX8GCR4_DXREFSEN_MASK 0x02000000U
14135 /*Reserved. Returns zeros on reads.*/
14136 #undef DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL
14137 #undef DDR_PHY_DX8GCR4_RESERVED_24_SHIFT
14138 #undef DDR_PHY_DX8GCR4_RESERVED_24_MASK
14139 #define DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL 0x0E00003C
14140 #define DDR_PHY_DX8GCR4_RESERVED_24_SHIFT 24
14141 #define DDR_PHY_DX8GCR4_RESERVED_24_MASK 0x01000000U
14143 /*External VREF generator REFSEL range select*/
14144 #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL
14145 #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT
14146 #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK
14147 #define DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C
14148 #define DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT 23
14149 #define DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK 0x00800000U
14151 /*Byte Lane External VREF Select*/
14152 #undef DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL
14153 #undef DDR_PHY_DX8GCR4_DXREFESEL_SHIFT
14154 #undef DDR_PHY_DX8GCR4_DXREFESEL_MASK
14155 #define DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL 0x0E00003C
14156 #define DDR_PHY_DX8GCR4_DXREFESEL_SHIFT 16
14157 #define DDR_PHY_DX8GCR4_DXREFESEL_MASK 0x007F0000U
14159 /*Single ended VREF generator REFSEL range select*/
14160 #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL
14161 #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT
14162 #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK
14163 #define DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C
14164 #define DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT 15
14165 #define DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK 0x00008000U
14167 /*Byte Lane Single-End VREF Select*/
14168 #undef DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL
14169 #undef DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT
14170 #undef DDR_PHY_DX8GCR4_DXREFSSEL_MASK
14171 #define DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL 0x0E00003C
14172 #define DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT 8
14173 #define DDR_PHY_DX8GCR4_DXREFSSEL_MASK 0x00007F00U
14175 /*Reserved. Returns zeros on reads.*/
14176 #undef DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL
14177 #undef DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT
14178 #undef DDR_PHY_DX8GCR4_RESERVED_7_6_MASK
14179 #define DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL 0x0E00003C
14180 #define DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT 6
14181 #define DDR_PHY_DX8GCR4_RESERVED_7_6_MASK 0x000000C0U
14183 /*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
14184 #undef DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL
14185 #undef DDR_PHY_DX8GCR4_DXREFIEN_SHIFT
14186 #undef DDR_PHY_DX8GCR4_DXREFIEN_MASK
14187 #define DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL 0x0E00003C
14188 #define DDR_PHY_DX8GCR4_DXREFIEN_SHIFT 2
14189 #define DDR_PHY_DX8GCR4_DXREFIEN_MASK 0x0000003CU
14191 /*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
14192 #undef DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL
14193 #undef DDR_PHY_DX8GCR4_DXREFIMON_SHIFT
14194 #undef DDR_PHY_DX8GCR4_DXREFIMON_MASK
14195 #define DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL 0x0E00003C
14196 #define DDR_PHY_DX8GCR4_DXREFIMON_SHIFT 0
14197 #define DDR_PHY_DX8GCR4_DXREFIMON_MASK 0x00000003U
14199 /*Reserved. Returns zeros on reads.*/
14200 #undef DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL
14201 #undef DDR_PHY_DX8GCR5_RESERVED_31_SHIFT
14202 #undef DDR_PHY_DX8GCR5_RESERVED_31_MASK
14203 #define DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL 0x09090909
14204 #define DDR_PHY_DX8GCR5_RESERVED_31_SHIFT 31
14205 #define DDR_PHY_DX8GCR5_RESERVED_31_MASK 0x80000000U
14207 /*Byte Lane internal VREF Select for Rank 3*/
14208 #undef DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL
14209 #undef DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT
14210 #undef DDR_PHY_DX8GCR5_DXREFISELR3_MASK
14211 #define DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL 0x09090909
14212 #define DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT 24
14213 #define DDR_PHY_DX8GCR5_DXREFISELR3_MASK 0x7F000000U
14215 /*Reserved. Returns zeros on reads.*/
14216 #undef DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL
14217 #undef DDR_PHY_DX8GCR5_RESERVED_23_SHIFT
14218 #undef DDR_PHY_DX8GCR5_RESERVED_23_MASK
14219 #define DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL 0x09090909
14220 #define DDR_PHY_DX8GCR5_RESERVED_23_SHIFT 23
14221 #define DDR_PHY_DX8GCR5_RESERVED_23_MASK 0x00800000U
14223 /*Byte Lane internal VREF Select for Rank 2*/
14224 #undef DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL
14225 #undef DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT
14226 #undef DDR_PHY_DX8GCR5_DXREFISELR2_MASK
14227 #define DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL 0x09090909
14228 #define DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT 16
14229 #define DDR_PHY_DX8GCR5_DXREFISELR2_MASK 0x007F0000U
14231 /*Reserved. Returns zeros on reads.*/
14232 #undef DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL
14233 #undef DDR_PHY_DX8GCR5_RESERVED_15_SHIFT
14234 #undef DDR_PHY_DX8GCR5_RESERVED_15_MASK
14235 #define DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL 0x09090909
14236 #define DDR_PHY_DX8GCR5_RESERVED_15_SHIFT 15
14237 #define DDR_PHY_DX8GCR5_RESERVED_15_MASK 0x00008000U
14239 /*Byte Lane internal VREF Select for Rank 1*/
14240 #undef DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL
14241 #undef DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT
14242 #undef DDR_PHY_DX8GCR5_DXREFISELR1_MASK
14243 #define DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL 0x09090909
14244 #define DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT 8
14245 #define DDR_PHY_DX8GCR5_DXREFISELR1_MASK 0x00007F00U
14247 /*Reserved. Returns zeros on reads.*/
14248 #undef DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL
14249 #undef DDR_PHY_DX8GCR5_RESERVED_7_SHIFT
14250 #undef DDR_PHY_DX8GCR5_RESERVED_7_MASK
14251 #define DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL 0x09090909
14252 #define DDR_PHY_DX8GCR5_RESERVED_7_SHIFT 7
14253 #define DDR_PHY_DX8GCR5_RESERVED_7_MASK 0x00000080U
14255 /*Byte Lane internal VREF Select for Rank 0*/
14256 #undef DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL
14257 #undef DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT
14258 #undef DDR_PHY_DX8GCR5_DXREFISELR0_MASK
14259 #define DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL 0x09090909
14260 #define DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT 0
14261 #define DDR_PHY_DX8GCR5_DXREFISELR0_MASK 0x0000007FU
14263 /*Reserved. Returns zeros on reads.*/
14264 #undef DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL
14265 #undef DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT
14266 #undef DDR_PHY_DX8GCR6_RESERVED_31_30_MASK
14267 #define DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL 0x09090909
14268 #define DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT 30
14269 #define DDR_PHY_DX8GCR6_RESERVED_31_30_MASK 0xC0000000U
14271 /*DRAM DQ VREF Select for Rank3*/
14272 #undef DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL
14273 #undef DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT
14274 #undef DDR_PHY_DX8GCR6_DXDQVREFR3_MASK
14275 #define DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL 0x09090909
14276 #define DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT 24
14277 #define DDR_PHY_DX8GCR6_DXDQVREFR3_MASK 0x3F000000U
14279 /*Reserved. Returns zeros on reads.*/
14280 #undef DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL
14281 #undef DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT
14282 #undef DDR_PHY_DX8GCR6_RESERVED_23_22_MASK
14283 #define DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL 0x09090909
14284 #define DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT 22
14285 #define DDR_PHY_DX8GCR6_RESERVED_23_22_MASK 0x00C00000U
14287 /*DRAM DQ VREF Select for Rank2*/
14288 #undef DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL
14289 #undef DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT
14290 #undef DDR_PHY_DX8GCR6_DXDQVREFR2_MASK
14291 #define DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL 0x09090909
14292 #define DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT 16
14293 #define DDR_PHY_DX8GCR6_DXDQVREFR2_MASK 0x003F0000U
14295 /*Reserved. Returns zeros on reads.*/
14296 #undef DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL
14297 #undef DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT
14298 #undef DDR_PHY_DX8GCR6_RESERVED_15_14_MASK
14299 #define DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL 0x09090909
14300 #define DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT 14
14301 #define DDR_PHY_DX8GCR6_RESERVED_15_14_MASK 0x0000C000U
14303 /*DRAM DQ VREF Select for Rank1*/
14304 #undef DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL
14305 #undef DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT
14306 #undef DDR_PHY_DX8GCR6_DXDQVREFR1_MASK
14307 #define DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL 0x09090909
14308 #define DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT 8
14309 #define DDR_PHY_DX8GCR6_DXDQVREFR1_MASK 0x00003F00U
14311 /*Reserved. Returns zeros on reads.*/
14312 #undef DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL
14313 #undef DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT
14314 #undef DDR_PHY_DX8GCR6_RESERVED_7_6_MASK
14315 #define DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL 0x09090909
14316 #define DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT 6
14317 #define DDR_PHY_DX8GCR6_RESERVED_7_6_MASK 0x000000C0U
14319 /*DRAM DQ VREF Select for Rank0*/
14320 #undef DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL
14321 #undef DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT
14322 #undef DDR_PHY_DX8GCR6_DXDQVREFR0_MASK
14323 #define DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL 0x09090909
14324 #define DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT 0
14325 #define DDR_PHY_DX8GCR6_DXDQVREFR0_MASK 0x0000003FU
14327 /*Reserved. Return zeroes on reads.*/
14328 #undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_DEFVAL
14329 #undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT
14330 #undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK
14331 #define DDR_PHY_DX8LCDLR2_RESERVED_31_25_DEFVAL 0x00000000
14332 #define DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT 25
14333 #define DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK 0xFE000000U
14335 /*Reserved. Caution, do not write to this register field.*/
14336 #undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_DEFVAL
14337 #undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT
14338 #undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK
14339 #define DDR_PHY_DX8LCDLR2_RESERVED_24_16_DEFVAL 0x00000000
14340 #define DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT 16
14341 #define DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK 0x01FF0000U
14343 /*Reserved. Return zeroes on reads.*/
14344 #undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_DEFVAL
14345 #undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT
14346 #undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK
14347 #define DDR_PHY_DX8LCDLR2_RESERVED_15_9_DEFVAL 0x00000000
14348 #define DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT 9
14349 #define DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK 0x0000FE00U
14351 /*Read DQS Gating Delay*/
14352 #undef DDR_PHY_DX8LCDLR2_DQSGD_DEFVAL
14353 #undef DDR_PHY_DX8LCDLR2_DQSGD_SHIFT
14354 #undef DDR_PHY_DX8LCDLR2_DQSGD_MASK
14355 #define DDR_PHY_DX8LCDLR2_DQSGD_DEFVAL 0x00000000
14356 #define DDR_PHY_DX8LCDLR2_DQSGD_SHIFT 0
14357 #define DDR_PHY_DX8LCDLR2_DQSGD_MASK 0x000001FFU
14359 /*Reserved. Return zeroes on reads.*/
14360 #undef DDR_PHY_DX8GTR0_RESERVED_31_24_DEFVAL
14361 #undef DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT
14362 #undef DDR_PHY_DX8GTR0_RESERVED_31_24_MASK
14363 #define DDR_PHY_DX8GTR0_RESERVED_31_24_DEFVAL 0x00020000
14364 #define DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT 27
14365 #define DDR_PHY_DX8GTR0_RESERVED_31_24_MASK 0xF8000000U
14367 /*DQ Write Path Latency Pipeline*/
14368 #undef DDR_PHY_DX8GTR0_WDQSL_DEFVAL
14369 #undef DDR_PHY_DX8GTR0_WDQSL_SHIFT
14370 #undef DDR_PHY_DX8GTR0_WDQSL_MASK
14371 #define DDR_PHY_DX8GTR0_WDQSL_DEFVAL 0x00020000
14372 #define DDR_PHY_DX8GTR0_WDQSL_SHIFT 24
14373 #define DDR_PHY_DX8GTR0_WDQSL_MASK 0x07000000U
14375 /*Reserved. Caution, do not write to this register field.*/
14376 #undef DDR_PHY_DX8GTR0_RESERVED_23_20_DEFVAL
14377 #undef DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT
14378 #undef DDR_PHY_DX8GTR0_RESERVED_23_20_MASK
14379 #define DDR_PHY_DX8GTR0_RESERVED_23_20_DEFVAL 0x00020000
14380 #define DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT 20
14381 #define DDR_PHY_DX8GTR0_RESERVED_23_20_MASK 0x00F00000U
14383 /*Write Leveling System Latency*/
14384 #undef DDR_PHY_DX8GTR0_WLSL_DEFVAL
14385 #undef DDR_PHY_DX8GTR0_WLSL_SHIFT
14386 #undef DDR_PHY_DX8GTR0_WLSL_MASK
14387 #define DDR_PHY_DX8GTR0_WLSL_DEFVAL 0x00020000
14388 #define DDR_PHY_DX8GTR0_WLSL_SHIFT 16
14389 #define DDR_PHY_DX8GTR0_WLSL_MASK 0x000F0000U
14391 /*Reserved. Return zeroes on reads.*/
14392 #undef DDR_PHY_DX8GTR0_RESERVED_15_13_DEFVAL
14393 #undef DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT
14394 #undef DDR_PHY_DX8GTR0_RESERVED_15_13_MASK
14395 #define DDR_PHY_DX8GTR0_RESERVED_15_13_DEFVAL 0x00020000
14396 #define DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT 13
14397 #define DDR_PHY_DX8GTR0_RESERVED_15_13_MASK 0x0000E000U
14399 /*Reserved. Caution, do not write to this register field.*/
14400 #undef DDR_PHY_DX8GTR0_RESERVED_12_8_DEFVAL
14401 #undef DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT
14402 #undef DDR_PHY_DX8GTR0_RESERVED_12_8_MASK
14403 #define DDR_PHY_DX8GTR0_RESERVED_12_8_DEFVAL 0x00020000
14404 #define DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT 8
14405 #define DDR_PHY_DX8GTR0_RESERVED_12_8_MASK 0x00001F00U
14407 /*Reserved. Return zeroes on reads.*/
14408 #undef DDR_PHY_DX8GTR0_RESERVED_7_5_DEFVAL
14409 #undef DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT
14410 #undef DDR_PHY_DX8GTR0_RESERVED_7_5_MASK
14411 #define DDR_PHY_DX8GTR0_RESERVED_7_5_DEFVAL 0x00020000
14412 #define DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT 5
14413 #define DDR_PHY_DX8GTR0_RESERVED_7_5_MASK 0x000000E0U
14415 /*DQS Gating System Latency*/
14416 #undef DDR_PHY_DX8GTR0_DGSL_DEFVAL
14417 #undef DDR_PHY_DX8GTR0_DGSL_SHIFT
14418 #undef DDR_PHY_DX8GTR0_DGSL_MASK
14419 #define DDR_PHY_DX8GTR0_DGSL_DEFVAL 0x00020000
14420 #define DDR_PHY_DX8GTR0_DGSL_SHIFT 0
14421 #define DDR_PHY_DX8GTR0_DGSL_MASK 0x0000001FU
14423 /*Reserved. Return zeroes on reads.*/
14424 #undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL
14425 #undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT
14426 #undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK
14427 #define DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL 0x00019FFE
14428 #define DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT 30
14429 #define DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK 0xC0000000U
14431 /*Enable Clock Gating for DX ddr_clk*/
14432 #undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL
14433 #undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT
14434 #undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK
14435 #define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL 0x00019FFE
14436 #define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT 28
14437 #define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK 0x30000000U
14439 /*Enable Clock Gating for DX ctl_rd_clk*/
14440 #undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL
14441 #undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT
14442 #undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK
14443 #define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE
14444 #define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT 26
14445 #define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK 0x0C000000U
14447 /*Enable Clock Gating for DX ctl_clk*/
14448 #undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL
14449 #undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT
14450 #undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK
14451 #define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE
14452 #define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT 24
14453 #define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK 0x03000000U
14455 /*Selects the level to which clocks will be stalled when clock gating is enabled.*/
14456 #undef DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL
14457 #undef DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT
14458 #undef DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK
14459 #define DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL 0x00019FFE
14460 #define DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT 22
14461 #define DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK 0x00C00000U
14464 #undef DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL
14465 #undef DDR_PHY_DX8SL0OSC_LBMODE_SHIFT
14466 #undef DDR_PHY_DX8SL0OSC_LBMODE_MASK
14467 #define DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL 0x00019FFE
14468 #define DDR_PHY_DX8SL0OSC_LBMODE_SHIFT 21
14469 #define DDR_PHY_DX8SL0OSC_LBMODE_MASK 0x00200000U
14471 /*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/
14472 #undef DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL
14473 #undef DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT
14474 #undef DDR_PHY_DX8SL0OSC_LBGSDQS_MASK
14475 #define DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL 0x00019FFE
14476 #define DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT 20
14477 #define DDR_PHY_DX8SL0OSC_LBGSDQS_MASK 0x00100000U
14479 /*Loopback DQS Gating*/
14480 #undef DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL
14481 #undef DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT
14482 #undef DDR_PHY_DX8SL0OSC_LBGDQS_MASK
14483 #define DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL 0x00019FFE
14484 #define DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT 18
14485 #define DDR_PHY_DX8SL0OSC_LBGDQS_MASK 0x000C0000U
14487 /*Loopback DQS Shift*/
14488 #undef DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL
14489 #undef DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT
14490 #undef DDR_PHY_DX8SL0OSC_LBDQSS_MASK
14491 #define DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL 0x00019FFE
14492 #define DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT 17
14493 #define DDR_PHY_DX8SL0OSC_LBDQSS_MASK 0x00020000U
14495 /*PHY High-Speed Reset*/
14496 #undef DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL
14497 #undef DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT
14498 #undef DDR_PHY_DX8SL0OSC_PHYHRST_MASK
14499 #define DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL 0x00019FFE
14500 #define DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT 16
14501 #define DDR_PHY_DX8SL0OSC_PHYHRST_MASK 0x00010000U
14504 #undef DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL
14505 #undef DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT
14506 #undef DDR_PHY_DX8SL0OSC_PHYFRST_MASK
14507 #define DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL 0x00019FFE
14508 #define DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT 15
14509 #define DDR_PHY_DX8SL0OSC_PHYFRST_MASK 0x00008000U
14511 /*Delay Line Test Start*/
14512 #undef DDR_PHY_DX8SL0OSC_DLTST_DEFVAL
14513 #undef DDR_PHY_DX8SL0OSC_DLTST_SHIFT
14514 #undef DDR_PHY_DX8SL0OSC_DLTST_MASK
14515 #define DDR_PHY_DX8SL0OSC_DLTST_DEFVAL 0x00019FFE
14516 #define DDR_PHY_DX8SL0OSC_DLTST_SHIFT 14
14517 #define DDR_PHY_DX8SL0OSC_DLTST_MASK 0x00004000U
14519 /*Delay Line Test Mode*/
14520 #undef DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL
14521 #undef DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT
14522 #undef DDR_PHY_DX8SL0OSC_DLTMODE_MASK
14523 #define DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL 0x00019FFE
14524 #define DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT 13
14525 #define DDR_PHY_DX8SL0OSC_DLTMODE_MASK 0x00002000U
14527 /*Reserved. Caution, do not write to this register field.*/
14528 #undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL
14529 #undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT
14530 #undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK
14531 #define DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL 0x00019FFE
14532 #define DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT 11
14533 #define DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK 0x00001800U
14535 /*Oscillator Mode Write-Data Delay Line Select*/
14536 #undef DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL
14537 #undef DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT
14538 #undef DDR_PHY_DX8SL0OSC_OSCWDDL_MASK
14539 #define DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL 0x00019FFE
14540 #define DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT 9
14541 #define DDR_PHY_DX8SL0OSC_OSCWDDL_MASK 0x00000600U
14543 /*Reserved. Caution, do not write to this register field.*/
14544 #undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL
14545 #undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT
14546 #undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK
14547 #define DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL 0x00019FFE
14548 #define DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT 7
14549 #define DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK 0x00000180U
14551 /*Oscillator Mode Write-Leveling Delay Line Select*/
14552 #undef DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL
14553 #undef DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT
14554 #undef DDR_PHY_DX8SL0OSC_OSCWDL_MASK
14555 #define DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL 0x00019FFE
14556 #define DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT 5
14557 #define DDR_PHY_DX8SL0OSC_OSCWDL_MASK 0x00000060U
14559 /*Oscillator Mode Division*/
14560 #undef DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL
14561 #undef DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT
14562 #undef DDR_PHY_DX8SL0OSC_OSCDIV_MASK
14563 #define DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL 0x00019FFE
14564 #define DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT 1
14565 #define DDR_PHY_DX8SL0OSC_OSCDIV_MASK 0x0000001EU
14567 /*Oscillator Enable*/
14568 #undef DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL
14569 #undef DDR_PHY_DX8SL0OSC_OSCEN_SHIFT
14570 #undef DDR_PHY_DX8SL0OSC_OSCEN_MASK
14571 #define DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL 0x00019FFE
14572 #define DDR_PHY_DX8SL0OSC_OSCEN_SHIFT 0
14573 #define DDR_PHY_DX8SL0OSC_OSCEN_MASK 0x00000001U
14575 /*Reserved. Return zeroes on reads.*/
14576 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL
14577 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT
14578 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK
14579 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL 0x01264000
14580 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT 25
14581 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK 0xFE000000U
14583 /*Read Path Rise-to-Rise Mode*/
14584 #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL
14585 #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT
14586 #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK
14587 #define DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL 0x01264000
14588 #define DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT 24
14589 #define DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK 0x01000000U
14591 /*Reserved. Return zeroes on reads.*/
14592 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL
14593 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT
14594 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK
14595 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL 0x01264000
14596 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT 22
14597 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK 0x00C00000U
14599 /*Write Path Rise-to-Rise Mode*/
14600 #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL
14601 #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT
14602 #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK
14603 #define DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL 0x01264000
14604 #define DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT 21
14605 #define DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK 0x00200000U
14607 /*DQS Gate Extension*/
14608 #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL
14609 #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT
14610 #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK
14611 #define DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL 0x01264000
14612 #define DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT 19
14613 #define DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK 0x00180000U
14615 /*Low Power PLL Power Down*/
14616 #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL
14617 #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT
14618 #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK
14619 #define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL 0x01264000
14620 #define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT 18
14621 #define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK 0x00040000U
14623 /*Low Power I/O Power Down*/
14624 #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL
14625 #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT
14626 #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK
14627 #define DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL 0x01264000
14628 #define DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT 17
14629 #define DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK 0x00020000U
14631 /*Reserved. Return zeroes on reads.*/
14632 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL
14633 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT
14634 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK
14635 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL 0x01264000
14636 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT 15
14637 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK 0x00018000U
14639 /*QS Counter Enable*/
14640 #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL
14641 #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT
14642 #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK
14643 #define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL 0x01264000
14644 #define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT 14
14645 #define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK 0x00004000U
14647 /*Unused DQ I/O Mode*/
14648 #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL
14649 #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT
14650 #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK
14651 #define DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL 0x01264000
14652 #define DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT 13
14653 #define DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK 0x00002000U
14655 /*Reserved. Return zeroes on reads.*/
14656 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL
14657 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT
14658 #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK
14659 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL 0x01264000
14660 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT 10
14661 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK 0x00001C00U
14664 #undef DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL
14665 #undef DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT
14666 #undef DDR_PHY_DX8SL0DQSCTL_DXSR_MASK
14667 #define DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL 0x01264000
14668 #define DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT 8
14669 #define DDR_PHY_DX8SL0DQSCTL_DXSR_MASK 0x00000300U
14672 #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL
14673 #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT
14674 #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK
14675 #define DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL 0x01264000
14676 #define DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT 4
14677 #define DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK 0x000000F0U
14680 #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL
14681 #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT
14682 #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK
14683 #define DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL 0x01264000
14684 #define DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT 0
14685 #define DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK 0x0000000FU
14687 /*Reserved. Return zeroes on reads.*/
14688 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL
14689 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT
14690 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK
14691 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL 0x00141800
14692 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT 24
14693 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK 0xFF000000U
14695 /*Configurable Read Data Enable*/
14696 #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL
14697 #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT
14698 #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK
14699 #define DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL 0x00141800
14700 #define DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT 23
14701 #define DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK 0x00800000U
14703 /*OX Extension during Post-amble*/
14704 #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL
14705 #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT
14706 #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK
14707 #define DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL 0x00141800
14708 #define DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT 20
14709 #define DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK 0x00700000U
14711 /*OE Extension during Pre-amble*/
14712 #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL
14713 #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT
14714 #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK
14715 #define DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL 0x00141800
14716 #define DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT 18
14717 #define DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK 0x000C0000U
14719 /*Reserved. Return zeroes on reads.*/
14720 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL
14721 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT
14722 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK
14723 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL 0x00141800
14724 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT 17
14725 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK 0x00020000U
14727 /*I/O Assisted Gate Select*/
14728 #undef DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL
14729 #undef DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT
14730 #undef DDR_PHY_DX8SL0DXCTL2_IOAG_MASK
14731 #define DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL 0x00141800
14732 #define DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT 16
14733 #define DDR_PHY_DX8SL0DXCTL2_IOAG_MASK 0x00010000U
14735 /*I/O Loopback Select*/
14736 #undef DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL
14737 #undef DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT
14738 #undef DDR_PHY_DX8SL0DXCTL2_IOLB_MASK
14739 #define DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL 0x00141800
14740 #define DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT 15
14741 #define DDR_PHY_DX8SL0DXCTL2_IOLB_MASK 0x00008000U
14743 /*Reserved. Return zeroes on reads.*/
14744 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL
14745 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT
14746 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK
14747 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL 0x00141800
14748 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT 13
14749 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK 0x00006000U
14751 /*Low Power Wakeup Threshold*/
14752 #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL
14753 #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT
14754 #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK
14755 #define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800
14756 #define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT 9
14757 #define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U
14759 /*Read Data Bus Inversion Enable*/
14760 #undef DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL
14761 #undef DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT
14762 #undef DDR_PHY_DX8SL0DXCTL2_RDBI_MASK
14763 #define DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL 0x00141800
14764 #define DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT 8
14765 #define DDR_PHY_DX8SL0DXCTL2_RDBI_MASK 0x00000100U
14767 /*Write Data Bus Inversion Enable*/
14768 #undef DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL
14769 #undef DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT
14770 #undef DDR_PHY_DX8SL0DXCTL2_WDBI_MASK
14771 #define DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL 0x00141800
14772 #define DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT 7
14773 #define DDR_PHY_DX8SL0DXCTL2_WDBI_MASK 0x00000080U
14775 /*PUB Read FIFO Bypass*/
14776 #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL
14777 #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT
14778 #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK
14779 #define DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL 0x00141800
14780 #define DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT 6
14781 #define DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK 0x00000040U
14783 /*DATX8 Receive FIFO Read Mode*/
14784 #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL
14785 #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT
14786 #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK
14787 #define DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL 0x00141800
14788 #define DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT 4
14789 #define DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK 0x00000030U
14791 /*Disables the Read FIFO Reset*/
14792 #undef DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL
14793 #undef DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT
14794 #undef DDR_PHY_DX8SL0DXCTL2_DISRST_MASK
14795 #define DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL 0x00141800
14796 #define DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT 3
14797 #define DDR_PHY_DX8SL0DXCTL2_DISRST_MASK 0x00000008U
14799 /*Read DQS Gate I/O Loopback*/
14800 #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL
14801 #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT
14802 #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK
14803 #define DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL 0x00141800
14804 #define DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT 1
14805 #define DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK 0x00000006U
14807 /*Reserved. Return zeroes on reads.*/
14808 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL
14809 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT
14810 #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK
14811 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL 0x00141800
14812 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT 0
14813 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK 0x00000001U
14815 /*Reserved. Return zeroes on reads.*/
14816 #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL
14817 #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT
14818 #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK
14819 #define DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL 0x00000000
14820 #define DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT 31
14821 #define DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK 0x80000000U
14823 /*PVREF_DAC REFSEL range select*/
14824 #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL
14825 #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT
14826 #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK
14827 #define DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL 0x00000000
14828 #define DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT 28
14829 #define DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK 0x70000000U
14831 /*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
14832 #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL
14833 #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT
14834 #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK
14835 #define DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL 0x00000000
14836 #define DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT 25
14837 #define DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK 0x0E000000U
14840 #undef DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL
14841 #undef DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT
14842 #undef DDR_PHY_DX8SL0IOCR_DXIOM_MASK
14843 #define DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL 0x00000000
14844 #define DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT 22
14845 #define DDR_PHY_DX8SL0IOCR_DXIOM_MASK 0x01C00000U
14847 /*DX IO Transmitter Mode*/
14848 #undef DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL
14849 #undef DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT
14850 #undef DDR_PHY_DX8SL0IOCR_DXTXM_MASK
14851 #define DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL 0x00000000
14852 #define DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT 11
14853 #define DDR_PHY_DX8SL0IOCR_DXTXM_MASK 0x003FF800U
14855 /*DX IO Receiver Mode*/
14856 #undef DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL
14857 #undef DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT
14858 #undef DDR_PHY_DX8SL0IOCR_DXRXM_MASK
14859 #define DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL 0x00000000
14860 #define DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT 0
14861 #define DDR_PHY_DX8SL0IOCR_DXRXM_MASK 0x000007FFU
14863 /*Reserved. Return zeroes on reads.*/
14864 #undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL
14865 #undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT
14866 #undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK
14867 #define DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL 0x00019FFE
14868 #define DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT 30
14869 #define DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK 0xC0000000U
14871 /*Enable Clock Gating for DX ddr_clk*/
14872 #undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL
14873 #undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT
14874 #undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK
14875 #define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL 0x00019FFE
14876 #define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT 28
14877 #define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK 0x30000000U
14879 /*Enable Clock Gating for DX ctl_rd_clk*/
14880 #undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL
14881 #undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT
14882 #undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK
14883 #define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE
14884 #define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT 26
14885 #define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK 0x0C000000U
14887 /*Enable Clock Gating for DX ctl_clk*/
14888 #undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL
14889 #undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT
14890 #undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK
14891 #define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE
14892 #define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT 24
14893 #define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK 0x03000000U
14895 /*Selects the level to which clocks will be stalled when clock gating is enabled.*/
14896 #undef DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL
14897 #undef DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT
14898 #undef DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK
14899 #define DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL 0x00019FFE
14900 #define DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT 22
14901 #define DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK 0x00C00000U
14904 #undef DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL
14905 #undef DDR_PHY_DX8SL1OSC_LBMODE_SHIFT
14906 #undef DDR_PHY_DX8SL1OSC_LBMODE_MASK
14907 #define DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL 0x00019FFE
14908 #define DDR_PHY_DX8SL1OSC_LBMODE_SHIFT 21
14909 #define DDR_PHY_DX8SL1OSC_LBMODE_MASK 0x00200000U
14911 /*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/
14912 #undef DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL
14913 #undef DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT
14914 #undef DDR_PHY_DX8SL1OSC_LBGSDQS_MASK
14915 #define DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL 0x00019FFE
14916 #define DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT 20
14917 #define DDR_PHY_DX8SL1OSC_LBGSDQS_MASK 0x00100000U
14919 /*Loopback DQS Gating*/
14920 #undef DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL
14921 #undef DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT
14922 #undef DDR_PHY_DX8SL1OSC_LBGDQS_MASK
14923 #define DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL 0x00019FFE
14924 #define DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT 18
14925 #define DDR_PHY_DX8SL1OSC_LBGDQS_MASK 0x000C0000U
14927 /*Loopback DQS Shift*/
14928 #undef DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL
14929 #undef DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT
14930 #undef DDR_PHY_DX8SL1OSC_LBDQSS_MASK
14931 #define DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL 0x00019FFE
14932 #define DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT 17
14933 #define DDR_PHY_DX8SL1OSC_LBDQSS_MASK 0x00020000U
14935 /*PHY High-Speed Reset*/
14936 #undef DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL
14937 #undef DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT
14938 #undef DDR_PHY_DX8SL1OSC_PHYHRST_MASK
14939 #define DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL 0x00019FFE
14940 #define DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT 16
14941 #define DDR_PHY_DX8SL1OSC_PHYHRST_MASK 0x00010000U
14944 #undef DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL
14945 #undef DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT
14946 #undef DDR_PHY_DX8SL1OSC_PHYFRST_MASK
14947 #define DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL 0x00019FFE
14948 #define DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT 15
14949 #define DDR_PHY_DX8SL1OSC_PHYFRST_MASK 0x00008000U
14951 /*Delay Line Test Start*/
14952 #undef DDR_PHY_DX8SL1OSC_DLTST_DEFVAL
14953 #undef DDR_PHY_DX8SL1OSC_DLTST_SHIFT
14954 #undef DDR_PHY_DX8SL1OSC_DLTST_MASK
14955 #define DDR_PHY_DX8SL1OSC_DLTST_DEFVAL 0x00019FFE
14956 #define DDR_PHY_DX8SL1OSC_DLTST_SHIFT 14
14957 #define DDR_PHY_DX8SL1OSC_DLTST_MASK 0x00004000U
14959 /*Delay Line Test Mode*/
14960 #undef DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL
14961 #undef DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT
14962 #undef DDR_PHY_DX8SL1OSC_DLTMODE_MASK
14963 #define DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL 0x00019FFE
14964 #define DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT 13
14965 #define DDR_PHY_DX8SL1OSC_DLTMODE_MASK 0x00002000U
14967 /*Reserved. Caution, do not write to this register field.*/
14968 #undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL
14969 #undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT
14970 #undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK
14971 #define DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL 0x00019FFE
14972 #define DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT 11
14973 #define DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK 0x00001800U
14975 /*Oscillator Mode Write-Data Delay Line Select*/
14976 #undef DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL
14977 #undef DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT
14978 #undef DDR_PHY_DX8SL1OSC_OSCWDDL_MASK
14979 #define DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL 0x00019FFE
14980 #define DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT 9
14981 #define DDR_PHY_DX8SL1OSC_OSCWDDL_MASK 0x00000600U
14983 /*Reserved. Caution, do not write to this register field.*/
14984 #undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL
14985 #undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT
14986 #undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK
14987 #define DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL 0x00019FFE
14988 #define DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT 7
14989 #define DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK 0x00000180U
14991 /*Oscillator Mode Write-Leveling Delay Line Select*/
14992 #undef DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL
14993 #undef DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT
14994 #undef DDR_PHY_DX8SL1OSC_OSCWDL_MASK
14995 #define DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL 0x00019FFE
14996 #define DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT 5
14997 #define DDR_PHY_DX8SL1OSC_OSCWDL_MASK 0x00000060U
14999 /*Oscillator Mode Division*/
15000 #undef DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL
15001 #undef DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT
15002 #undef DDR_PHY_DX8SL1OSC_OSCDIV_MASK
15003 #define DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL 0x00019FFE
15004 #define DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT 1
15005 #define DDR_PHY_DX8SL1OSC_OSCDIV_MASK 0x0000001EU
15007 /*Oscillator Enable*/
15008 #undef DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL
15009 #undef DDR_PHY_DX8SL1OSC_OSCEN_SHIFT
15010 #undef DDR_PHY_DX8SL1OSC_OSCEN_MASK
15011 #define DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL 0x00019FFE
15012 #define DDR_PHY_DX8SL1OSC_OSCEN_SHIFT 0
15013 #define DDR_PHY_DX8SL1OSC_OSCEN_MASK 0x00000001U
15015 /*Reserved. Return zeroes on reads.*/
15016 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL
15017 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT
15018 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK
15019 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL 0x01264000
15020 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT 25
15021 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK 0xFE000000U
15023 /*Read Path Rise-to-Rise Mode*/
15024 #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL
15025 #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT
15026 #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK
15027 #define DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL 0x01264000
15028 #define DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT 24
15029 #define DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK 0x01000000U
15031 /*Reserved. Return zeroes on reads.*/
15032 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL
15033 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT
15034 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK
15035 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL 0x01264000
15036 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT 22
15037 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK 0x00C00000U
15039 /*Write Path Rise-to-Rise Mode*/
15040 #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL
15041 #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT
15042 #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK
15043 #define DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL 0x01264000
15044 #define DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT 21
15045 #define DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK 0x00200000U
15047 /*DQS Gate Extension*/
15048 #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL
15049 #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT
15050 #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK
15051 #define DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL 0x01264000
15052 #define DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT 19
15053 #define DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK 0x00180000U
15055 /*Low Power PLL Power Down*/
15056 #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL
15057 #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT
15058 #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK
15059 #define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL 0x01264000
15060 #define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT 18
15061 #define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK 0x00040000U
15063 /*Low Power I/O Power Down*/
15064 #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL
15065 #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT
15066 #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK
15067 #define DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL 0x01264000
15068 #define DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT 17
15069 #define DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK 0x00020000U
15071 /*Reserved. Return zeroes on reads.*/
15072 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL
15073 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT
15074 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK
15075 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL 0x01264000
15076 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT 15
15077 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK 0x00018000U
15079 /*QS Counter Enable*/
15080 #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL
15081 #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT
15082 #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK
15083 #define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL 0x01264000
15084 #define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT 14
15085 #define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK 0x00004000U
15087 /*Unused DQ I/O Mode*/
15088 #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL
15089 #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT
15090 #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK
15091 #define DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL 0x01264000
15092 #define DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT 13
15093 #define DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK 0x00002000U
15095 /*Reserved. Return zeroes on reads.*/
15096 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL
15097 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT
15098 #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK
15099 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL 0x01264000
15100 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT 10
15101 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK 0x00001C00U
15104 #undef DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL
15105 #undef DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT
15106 #undef DDR_PHY_DX8SL1DQSCTL_DXSR_MASK
15107 #define DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL 0x01264000
15108 #define DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT 8
15109 #define DDR_PHY_DX8SL1DQSCTL_DXSR_MASK 0x00000300U
15112 #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL
15113 #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT
15114 #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK
15115 #define DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL 0x01264000
15116 #define DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT 4
15117 #define DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK 0x000000F0U
15120 #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL
15121 #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT
15122 #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK
15123 #define DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL 0x01264000
15124 #define DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT 0
15125 #define DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK 0x0000000FU
15127 /*Reserved. Return zeroes on reads.*/
15128 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL
15129 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT
15130 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK
15131 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL 0x00141800
15132 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT 24
15133 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK 0xFF000000U
15135 /*Configurable Read Data Enable*/
15136 #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL
15137 #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT
15138 #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK
15139 #define DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL 0x00141800
15140 #define DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT 23
15141 #define DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK 0x00800000U
15143 /*OX Extension during Post-amble*/
15144 #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL
15145 #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT
15146 #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK
15147 #define DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL 0x00141800
15148 #define DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT 20
15149 #define DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK 0x00700000U
15151 /*OE Extension during Pre-amble*/
15152 #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL
15153 #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT
15154 #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK
15155 #define DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL 0x00141800
15156 #define DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT 18
15157 #define DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK 0x000C0000U
15159 /*Reserved. Return zeroes on reads.*/
15160 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL
15161 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT
15162 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK
15163 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL 0x00141800
15164 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT 17
15165 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK 0x00020000U
15167 /*I/O Assisted Gate Select*/
15168 #undef DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL
15169 #undef DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT
15170 #undef DDR_PHY_DX8SL1DXCTL2_IOAG_MASK
15171 #define DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL 0x00141800
15172 #define DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT 16
15173 #define DDR_PHY_DX8SL1DXCTL2_IOAG_MASK 0x00010000U
15175 /*I/O Loopback Select*/
15176 #undef DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL
15177 #undef DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT
15178 #undef DDR_PHY_DX8SL1DXCTL2_IOLB_MASK
15179 #define DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL 0x00141800
15180 #define DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT 15
15181 #define DDR_PHY_DX8SL1DXCTL2_IOLB_MASK 0x00008000U
15183 /*Reserved. Return zeroes on reads.*/
15184 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL
15185 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT
15186 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK
15187 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL 0x00141800
15188 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT 13
15189 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK 0x00006000U
15191 /*Low Power Wakeup Threshold*/
15192 #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL
15193 #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT
15194 #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK
15195 #define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800
15196 #define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT 9
15197 #define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U
15199 /*Read Data Bus Inversion Enable*/
15200 #undef DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL
15201 #undef DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT
15202 #undef DDR_PHY_DX8SL1DXCTL2_RDBI_MASK
15203 #define DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL 0x00141800
15204 #define DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT 8
15205 #define DDR_PHY_DX8SL1DXCTL2_RDBI_MASK 0x00000100U
15207 /*Write Data Bus Inversion Enable*/
15208 #undef DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL
15209 #undef DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT
15210 #undef DDR_PHY_DX8SL1DXCTL2_WDBI_MASK
15211 #define DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL 0x00141800
15212 #define DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT 7
15213 #define DDR_PHY_DX8SL1DXCTL2_WDBI_MASK 0x00000080U
15215 /*PUB Read FIFO Bypass*/
15216 #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL
15217 #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT
15218 #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK
15219 #define DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL 0x00141800
15220 #define DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT 6
15221 #define DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK 0x00000040U
15223 /*DATX8 Receive FIFO Read Mode*/
15224 #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL
15225 #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT
15226 #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK
15227 #define DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL 0x00141800
15228 #define DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT 4
15229 #define DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK 0x00000030U
15231 /*Disables the Read FIFO Reset*/
15232 #undef DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL
15233 #undef DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT
15234 #undef DDR_PHY_DX8SL1DXCTL2_DISRST_MASK
15235 #define DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL 0x00141800
15236 #define DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT 3
15237 #define DDR_PHY_DX8SL1DXCTL2_DISRST_MASK 0x00000008U
15239 /*Read DQS Gate I/O Loopback*/
15240 #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL
15241 #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT
15242 #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK
15243 #define DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL 0x00141800
15244 #define DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT 1
15245 #define DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK 0x00000006U
15247 /*Reserved. Return zeroes on reads.*/
15248 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL
15249 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT
15250 #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK
15251 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL 0x00141800
15252 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT 0
15253 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK 0x00000001U
15255 /*Reserved. Return zeroes on reads.*/
15256 #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL
15257 #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT
15258 #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK
15259 #define DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL 0x00000000
15260 #define DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT 31
15261 #define DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK 0x80000000U
15263 /*PVREF_DAC REFSEL range select*/
15264 #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL
15265 #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT
15266 #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK
15267 #define DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL 0x00000000
15268 #define DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT 28
15269 #define DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK 0x70000000U
15271 /*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
15272 #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL
15273 #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT
15274 #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK
15275 #define DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL 0x00000000
15276 #define DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT 25
15277 #define DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK 0x0E000000U
15280 #undef DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL
15281 #undef DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT
15282 #undef DDR_PHY_DX8SL1IOCR_DXIOM_MASK
15283 #define DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL 0x00000000
15284 #define DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT 22
15285 #define DDR_PHY_DX8SL1IOCR_DXIOM_MASK 0x01C00000U
15287 /*DX IO Transmitter Mode*/
15288 #undef DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL
15289 #undef DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT
15290 #undef DDR_PHY_DX8SL1IOCR_DXTXM_MASK
15291 #define DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL 0x00000000
15292 #define DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT 11
15293 #define DDR_PHY_DX8SL1IOCR_DXTXM_MASK 0x003FF800U
15295 /*DX IO Receiver Mode*/
15296 #undef DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL
15297 #undef DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT
15298 #undef DDR_PHY_DX8SL1IOCR_DXRXM_MASK
15299 #define DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL 0x00000000
15300 #define DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT 0
15301 #define DDR_PHY_DX8SL1IOCR_DXRXM_MASK 0x000007FFU
15303 /*Reserved. Return zeroes on reads.*/
15304 #undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL
15305 #undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT
15306 #undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK
15307 #define DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL 0x00019FFE
15308 #define DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT 30
15309 #define DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK 0xC0000000U
15311 /*Enable Clock Gating for DX ddr_clk*/
15312 #undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL
15313 #undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT
15314 #undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK
15315 #define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL 0x00019FFE
15316 #define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT 28
15317 #define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK 0x30000000U
15319 /*Enable Clock Gating for DX ctl_rd_clk*/
15320 #undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL
15321 #undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT
15322 #undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK
15323 #define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE
15324 #define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT 26
15325 #define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK 0x0C000000U
15327 /*Enable Clock Gating for DX ctl_clk*/
15328 #undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL
15329 #undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT
15330 #undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK
15331 #define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE
15332 #define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT 24
15333 #define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK 0x03000000U
15335 /*Selects the level to which clocks will be stalled when clock gating is enabled.*/
15336 #undef DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL
15337 #undef DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT
15338 #undef DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK
15339 #define DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL 0x00019FFE
15340 #define DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT 22
15341 #define DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK 0x00C00000U
15344 #undef DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL
15345 #undef DDR_PHY_DX8SL2OSC_LBMODE_SHIFT
15346 #undef DDR_PHY_DX8SL2OSC_LBMODE_MASK
15347 #define DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL 0x00019FFE
15348 #define DDR_PHY_DX8SL2OSC_LBMODE_SHIFT 21
15349 #define DDR_PHY_DX8SL2OSC_LBMODE_MASK 0x00200000U
15351 /*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/
15352 #undef DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL
15353 #undef DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT
15354 #undef DDR_PHY_DX8SL2OSC_LBGSDQS_MASK
15355 #define DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL 0x00019FFE
15356 #define DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT 20
15357 #define DDR_PHY_DX8SL2OSC_LBGSDQS_MASK 0x00100000U
15359 /*Loopback DQS Gating*/
15360 #undef DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL
15361 #undef DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT
15362 #undef DDR_PHY_DX8SL2OSC_LBGDQS_MASK
15363 #define DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL 0x00019FFE
15364 #define DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT 18
15365 #define DDR_PHY_DX8SL2OSC_LBGDQS_MASK 0x000C0000U
15367 /*Loopback DQS Shift*/
15368 #undef DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL
15369 #undef DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT
15370 #undef DDR_PHY_DX8SL2OSC_LBDQSS_MASK
15371 #define DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL 0x00019FFE
15372 #define DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT 17
15373 #define DDR_PHY_DX8SL2OSC_LBDQSS_MASK 0x00020000U
15375 /*PHY High-Speed Reset*/
15376 #undef DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL
15377 #undef DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT
15378 #undef DDR_PHY_DX8SL2OSC_PHYHRST_MASK
15379 #define DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL 0x00019FFE
15380 #define DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT 16
15381 #define DDR_PHY_DX8SL2OSC_PHYHRST_MASK 0x00010000U
15384 #undef DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL
15385 #undef DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT
15386 #undef DDR_PHY_DX8SL2OSC_PHYFRST_MASK
15387 #define DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL 0x00019FFE
15388 #define DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT 15
15389 #define DDR_PHY_DX8SL2OSC_PHYFRST_MASK 0x00008000U
15391 /*Delay Line Test Start*/
15392 #undef DDR_PHY_DX8SL2OSC_DLTST_DEFVAL
15393 #undef DDR_PHY_DX8SL2OSC_DLTST_SHIFT
15394 #undef DDR_PHY_DX8SL2OSC_DLTST_MASK
15395 #define DDR_PHY_DX8SL2OSC_DLTST_DEFVAL 0x00019FFE
15396 #define DDR_PHY_DX8SL2OSC_DLTST_SHIFT 14
15397 #define DDR_PHY_DX8SL2OSC_DLTST_MASK 0x00004000U
15399 /*Delay Line Test Mode*/
15400 #undef DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL
15401 #undef DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT
15402 #undef DDR_PHY_DX8SL2OSC_DLTMODE_MASK
15403 #define DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL 0x00019FFE
15404 #define DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT 13
15405 #define DDR_PHY_DX8SL2OSC_DLTMODE_MASK 0x00002000U
15407 /*Reserved. Caution, do not write to this register field.*/
15408 #undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL
15409 #undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT
15410 #undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK
15411 #define DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL 0x00019FFE
15412 #define DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT 11
15413 #define DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK 0x00001800U
15415 /*Oscillator Mode Write-Data Delay Line Select*/
15416 #undef DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL
15417 #undef DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT
15418 #undef DDR_PHY_DX8SL2OSC_OSCWDDL_MASK
15419 #define DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL 0x00019FFE
15420 #define DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT 9
15421 #define DDR_PHY_DX8SL2OSC_OSCWDDL_MASK 0x00000600U
15423 /*Reserved. Caution, do not write to this register field.*/
15424 #undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL
15425 #undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT
15426 #undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK
15427 #define DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL 0x00019FFE
15428 #define DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT 7
15429 #define DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK 0x00000180U
15431 /*Oscillator Mode Write-Leveling Delay Line Select*/
15432 #undef DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL
15433 #undef DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT
15434 #undef DDR_PHY_DX8SL2OSC_OSCWDL_MASK
15435 #define DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL 0x00019FFE
15436 #define DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT 5
15437 #define DDR_PHY_DX8SL2OSC_OSCWDL_MASK 0x00000060U
15439 /*Oscillator Mode Division*/
15440 #undef DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL
15441 #undef DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT
15442 #undef DDR_PHY_DX8SL2OSC_OSCDIV_MASK
15443 #define DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL 0x00019FFE
15444 #define DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT 1
15445 #define DDR_PHY_DX8SL2OSC_OSCDIV_MASK 0x0000001EU
15447 /*Oscillator Enable*/
15448 #undef DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL
15449 #undef DDR_PHY_DX8SL2OSC_OSCEN_SHIFT
15450 #undef DDR_PHY_DX8SL2OSC_OSCEN_MASK
15451 #define DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL 0x00019FFE
15452 #define DDR_PHY_DX8SL2OSC_OSCEN_SHIFT 0
15453 #define DDR_PHY_DX8SL2OSC_OSCEN_MASK 0x00000001U
15455 /*Reserved. Return zeroes on reads.*/
15456 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL
15457 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT
15458 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK
15459 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL 0x01264000
15460 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT 25
15461 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK 0xFE000000U
15463 /*Read Path Rise-to-Rise Mode*/
15464 #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL
15465 #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT
15466 #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK
15467 #define DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL 0x01264000
15468 #define DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT 24
15469 #define DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK 0x01000000U
15471 /*Reserved. Return zeroes on reads.*/
15472 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL
15473 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT
15474 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK
15475 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL 0x01264000
15476 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT 22
15477 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK 0x00C00000U
15479 /*Write Path Rise-to-Rise Mode*/
15480 #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL
15481 #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT
15482 #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK
15483 #define DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL 0x01264000
15484 #define DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT 21
15485 #define DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK 0x00200000U
15487 /*DQS Gate Extension*/
15488 #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL
15489 #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT
15490 #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK
15491 #define DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL 0x01264000
15492 #define DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT 19
15493 #define DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK 0x00180000U
15495 /*Low Power PLL Power Down*/
15496 #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL
15497 #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT
15498 #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK
15499 #define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL 0x01264000
15500 #define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT 18
15501 #define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK 0x00040000U
15503 /*Low Power I/O Power Down*/
15504 #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL
15505 #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT
15506 #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK
15507 #define DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL 0x01264000
15508 #define DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT 17
15509 #define DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK 0x00020000U
15511 /*Reserved. Return zeroes on reads.*/
15512 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL
15513 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT
15514 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK
15515 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL 0x01264000
15516 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT 15
15517 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK 0x00018000U
15519 /*QS Counter Enable*/
15520 #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL
15521 #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT
15522 #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK
15523 #define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL 0x01264000
15524 #define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT 14
15525 #define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK 0x00004000U
15527 /*Unused DQ I/O Mode*/
15528 #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL
15529 #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT
15530 #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK
15531 #define DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL 0x01264000
15532 #define DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT 13
15533 #define DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK 0x00002000U
15535 /*Reserved. Return zeroes on reads.*/
15536 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL
15537 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT
15538 #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK
15539 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL 0x01264000
15540 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT 10
15541 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK 0x00001C00U
15544 #undef DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL
15545 #undef DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT
15546 #undef DDR_PHY_DX8SL2DQSCTL_DXSR_MASK
15547 #define DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL 0x01264000
15548 #define DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT 8
15549 #define DDR_PHY_DX8SL2DQSCTL_DXSR_MASK 0x00000300U
15552 #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL
15553 #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT
15554 #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK
15555 #define DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL 0x01264000
15556 #define DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT 4
15557 #define DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK 0x000000F0U
15560 #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL
15561 #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT
15562 #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK
15563 #define DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL 0x01264000
15564 #define DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT 0
15565 #define DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK 0x0000000FU
15567 /*Reserved. Return zeroes on reads.*/
15568 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL
15569 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT
15570 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK
15571 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL 0x00141800
15572 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT 24
15573 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK 0xFF000000U
15575 /*Configurable Read Data Enable*/
15576 #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL
15577 #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT
15578 #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK
15579 #define DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL 0x00141800
15580 #define DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT 23
15581 #define DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK 0x00800000U
15583 /*OX Extension during Post-amble*/
15584 #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL
15585 #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT
15586 #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK
15587 #define DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL 0x00141800
15588 #define DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT 20
15589 #define DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK 0x00700000U
15591 /*OE Extension during Pre-amble*/
15592 #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL
15593 #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT
15594 #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK
15595 #define DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL 0x00141800
15596 #define DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT 18
15597 #define DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK 0x000C0000U
15599 /*Reserved. Return zeroes on reads.*/
15600 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL
15601 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT
15602 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK
15603 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL 0x00141800
15604 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT 17
15605 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK 0x00020000U
15607 /*I/O Assisted Gate Select*/
15608 #undef DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL
15609 #undef DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT
15610 #undef DDR_PHY_DX8SL2DXCTL2_IOAG_MASK
15611 #define DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL 0x00141800
15612 #define DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT 16
15613 #define DDR_PHY_DX8SL2DXCTL2_IOAG_MASK 0x00010000U
15615 /*I/O Loopback Select*/
15616 #undef DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL
15617 #undef DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT
15618 #undef DDR_PHY_DX8SL2DXCTL2_IOLB_MASK
15619 #define DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL 0x00141800
15620 #define DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT 15
15621 #define DDR_PHY_DX8SL2DXCTL2_IOLB_MASK 0x00008000U
15623 /*Reserved. Return zeroes on reads.*/
15624 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL
15625 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT
15626 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK
15627 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL 0x00141800
15628 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT 13
15629 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK 0x00006000U
15631 /*Low Power Wakeup Threshold*/
15632 #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL
15633 #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT
15634 #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK
15635 #define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800
15636 #define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT 9
15637 #define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U
15639 /*Read Data Bus Inversion Enable*/
15640 #undef DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL
15641 #undef DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT
15642 #undef DDR_PHY_DX8SL2DXCTL2_RDBI_MASK
15643 #define DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL 0x00141800
15644 #define DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT 8
15645 #define DDR_PHY_DX8SL2DXCTL2_RDBI_MASK 0x00000100U
15647 /*Write Data Bus Inversion Enable*/
15648 #undef DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL
15649 #undef DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT
15650 #undef DDR_PHY_DX8SL2DXCTL2_WDBI_MASK
15651 #define DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL 0x00141800
15652 #define DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT 7
15653 #define DDR_PHY_DX8SL2DXCTL2_WDBI_MASK 0x00000080U
15655 /*PUB Read FIFO Bypass*/
15656 #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL
15657 #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT
15658 #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK
15659 #define DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL 0x00141800
15660 #define DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT 6
15661 #define DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK 0x00000040U
15663 /*DATX8 Receive FIFO Read Mode*/
15664 #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL
15665 #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT
15666 #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK
15667 #define DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL 0x00141800
15668 #define DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT 4
15669 #define DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK 0x00000030U
15671 /*Disables the Read FIFO Reset*/
15672 #undef DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL
15673 #undef DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT
15674 #undef DDR_PHY_DX8SL2DXCTL2_DISRST_MASK
15675 #define DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL 0x00141800
15676 #define DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT 3
15677 #define DDR_PHY_DX8SL2DXCTL2_DISRST_MASK 0x00000008U
15679 /*Read DQS Gate I/O Loopback*/
15680 #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL
15681 #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT
15682 #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK
15683 #define DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL 0x00141800
15684 #define DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT 1
15685 #define DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK 0x00000006U
15687 /*Reserved. Return zeroes on reads.*/
15688 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL
15689 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT
15690 #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK
15691 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL 0x00141800
15692 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT 0
15693 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK 0x00000001U
15695 /*Reserved. Return zeroes on reads.*/
15696 #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL
15697 #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT
15698 #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK
15699 #define DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL 0x00000000
15700 #define DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT 31
15701 #define DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK 0x80000000U
15703 /*PVREF_DAC REFSEL range select*/
15704 #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL
15705 #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT
15706 #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK
15707 #define DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL 0x00000000
15708 #define DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT 28
15709 #define DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK 0x70000000U
15711 /*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
15712 #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL
15713 #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT
15714 #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK
15715 #define DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL 0x00000000
15716 #define DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT 25
15717 #define DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK 0x0E000000U
15720 #undef DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL
15721 #undef DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT
15722 #undef DDR_PHY_DX8SL2IOCR_DXIOM_MASK
15723 #define DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL 0x00000000
15724 #define DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT 22
15725 #define DDR_PHY_DX8SL2IOCR_DXIOM_MASK 0x01C00000U
15727 /*DX IO Transmitter Mode*/
15728 #undef DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL
15729 #undef DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT
15730 #undef DDR_PHY_DX8SL2IOCR_DXTXM_MASK
15731 #define DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL 0x00000000
15732 #define DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT 11
15733 #define DDR_PHY_DX8SL2IOCR_DXTXM_MASK 0x003FF800U
15735 /*DX IO Receiver Mode*/
15736 #undef DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL
15737 #undef DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT
15738 #undef DDR_PHY_DX8SL2IOCR_DXRXM_MASK
15739 #define DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL 0x00000000
15740 #define DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT 0
15741 #define DDR_PHY_DX8SL2IOCR_DXRXM_MASK 0x000007FFU
15743 /*Reserved. Return zeroes on reads.*/
15744 #undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL
15745 #undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT
15746 #undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK
15747 #define DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL 0x00019FFE
15748 #define DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT 30
15749 #define DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK 0xC0000000U
15751 /*Enable Clock Gating for DX ddr_clk*/
15752 #undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL
15753 #undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT
15754 #undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK
15755 #define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL 0x00019FFE
15756 #define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT 28
15757 #define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK 0x30000000U
15759 /*Enable Clock Gating for DX ctl_rd_clk*/
15760 #undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL
15761 #undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT
15762 #undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK
15763 #define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE
15764 #define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT 26
15765 #define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK 0x0C000000U
15767 /*Enable Clock Gating for DX ctl_clk*/
15768 #undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL
15769 #undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT
15770 #undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK
15771 #define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE
15772 #define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT 24
15773 #define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK 0x03000000U
15775 /*Selects the level to which clocks will be stalled when clock gating is enabled.*/
15776 #undef DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL
15777 #undef DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT
15778 #undef DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK
15779 #define DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL 0x00019FFE
15780 #define DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT 22
15781 #define DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK 0x00C00000U
15784 #undef DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL
15785 #undef DDR_PHY_DX8SL3OSC_LBMODE_SHIFT
15786 #undef DDR_PHY_DX8SL3OSC_LBMODE_MASK
15787 #define DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL 0x00019FFE
15788 #define DDR_PHY_DX8SL3OSC_LBMODE_SHIFT 21
15789 #define DDR_PHY_DX8SL3OSC_LBMODE_MASK 0x00200000U
15791 /*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/
15792 #undef DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL
15793 #undef DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT
15794 #undef DDR_PHY_DX8SL3OSC_LBGSDQS_MASK
15795 #define DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL 0x00019FFE
15796 #define DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT 20
15797 #define DDR_PHY_DX8SL3OSC_LBGSDQS_MASK 0x00100000U
15799 /*Loopback DQS Gating*/
15800 #undef DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL
15801 #undef DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT
15802 #undef DDR_PHY_DX8SL3OSC_LBGDQS_MASK
15803 #define DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL 0x00019FFE
15804 #define DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT 18
15805 #define DDR_PHY_DX8SL3OSC_LBGDQS_MASK 0x000C0000U
15807 /*Loopback DQS Shift*/
15808 #undef DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL
15809 #undef DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT
15810 #undef DDR_PHY_DX8SL3OSC_LBDQSS_MASK
15811 #define DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL 0x00019FFE
15812 #define DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT 17
15813 #define DDR_PHY_DX8SL3OSC_LBDQSS_MASK 0x00020000U
15815 /*PHY High-Speed Reset*/
15816 #undef DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL
15817 #undef DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT
15818 #undef DDR_PHY_DX8SL3OSC_PHYHRST_MASK
15819 #define DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL 0x00019FFE
15820 #define DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT 16
15821 #define DDR_PHY_DX8SL3OSC_PHYHRST_MASK 0x00010000U
15824 #undef DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL
15825 #undef DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT
15826 #undef DDR_PHY_DX8SL3OSC_PHYFRST_MASK
15827 #define DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL 0x00019FFE
15828 #define DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT 15
15829 #define DDR_PHY_DX8SL3OSC_PHYFRST_MASK 0x00008000U
15831 /*Delay Line Test Start*/
15832 #undef DDR_PHY_DX8SL3OSC_DLTST_DEFVAL
15833 #undef DDR_PHY_DX8SL3OSC_DLTST_SHIFT
15834 #undef DDR_PHY_DX8SL3OSC_DLTST_MASK
15835 #define DDR_PHY_DX8SL3OSC_DLTST_DEFVAL 0x00019FFE
15836 #define DDR_PHY_DX8SL3OSC_DLTST_SHIFT 14
15837 #define DDR_PHY_DX8SL3OSC_DLTST_MASK 0x00004000U
15839 /*Delay Line Test Mode*/
15840 #undef DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL
15841 #undef DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT
15842 #undef DDR_PHY_DX8SL3OSC_DLTMODE_MASK
15843 #define DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL 0x00019FFE
15844 #define DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT 13
15845 #define DDR_PHY_DX8SL3OSC_DLTMODE_MASK 0x00002000U
15847 /*Reserved. Caution, do not write to this register field.*/
15848 #undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL
15849 #undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT
15850 #undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK
15851 #define DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL 0x00019FFE
15852 #define DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT 11
15853 #define DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK 0x00001800U
15855 /*Oscillator Mode Write-Data Delay Line Select*/
15856 #undef DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL
15857 #undef DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT
15858 #undef DDR_PHY_DX8SL3OSC_OSCWDDL_MASK
15859 #define DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL 0x00019FFE
15860 #define DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT 9
15861 #define DDR_PHY_DX8SL3OSC_OSCWDDL_MASK 0x00000600U
15863 /*Reserved. Caution, do not write to this register field.*/
15864 #undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL
15865 #undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT
15866 #undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK
15867 #define DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL 0x00019FFE
15868 #define DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT 7
15869 #define DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK 0x00000180U
15871 /*Oscillator Mode Write-Leveling Delay Line Select*/
15872 #undef DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL
15873 #undef DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT
15874 #undef DDR_PHY_DX8SL3OSC_OSCWDL_MASK
15875 #define DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL 0x00019FFE
15876 #define DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT 5
15877 #define DDR_PHY_DX8SL3OSC_OSCWDL_MASK 0x00000060U
15879 /*Oscillator Mode Division*/
15880 #undef DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL
15881 #undef DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT
15882 #undef DDR_PHY_DX8SL3OSC_OSCDIV_MASK
15883 #define DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL 0x00019FFE
15884 #define DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT 1
15885 #define DDR_PHY_DX8SL3OSC_OSCDIV_MASK 0x0000001EU
15887 /*Oscillator Enable*/
15888 #undef DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL
15889 #undef DDR_PHY_DX8SL3OSC_OSCEN_SHIFT
15890 #undef DDR_PHY_DX8SL3OSC_OSCEN_MASK
15891 #define DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL 0x00019FFE
15892 #define DDR_PHY_DX8SL3OSC_OSCEN_SHIFT 0
15893 #define DDR_PHY_DX8SL3OSC_OSCEN_MASK 0x00000001U
15895 /*Reserved. Return zeroes on reads.*/
15896 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL
15897 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT
15898 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK
15899 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL 0x01264000
15900 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT 25
15901 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK 0xFE000000U
15903 /*Read Path Rise-to-Rise Mode*/
15904 #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL
15905 #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT
15906 #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK
15907 #define DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL 0x01264000
15908 #define DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT 24
15909 #define DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK 0x01000000U
15911 /*Reserved. Return zeroes on reads.*/
15912 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL
15913 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT
15914 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK
15915 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL 0x01264000
15916 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT 22
15917 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK 0x00C00000U
15919 /*Write Path Rise-to-Rise Mode*/
15920 #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL
15921 #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT
15922 #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK
15923 #define DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL 0x01264000
15924 #define DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT 21
15925 #define DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK 0x00200000U
15927 /*DQS Gate Extension*/
15928 #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL
15929 #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT
15930 #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK
15931 #define DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL 0x01264000
15932 #define DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT 19
15933 #define DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK 0x00180000U
15935 /*Low Power PLL Power Down*/
15936 #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL
15937 #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT
15938 #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK
15939 #define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL 0x01264000
15940 #define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT 18
15941 #define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK 0x00040000U
15943 /*Low Power I/O Power Down*/
15944 #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL
15945 #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT
15946 #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK
15947 #define DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL 0x01264000
15948 #define DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT 17
15949 #define DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK 0x00020000U
15951 /*Reserved. Return zeroes on reads.*/
15952 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL
15953 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT
15954 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK
15955 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL 0x01264000
15956 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT 15
15957 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK 0x00018000U
15959 /*QS Counter Enable*/
15960 #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL
15961 #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT
15962 #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK
15963 #define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL 0x01264000
15964 #define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT 14
15965 #define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK 0x00004000U
15967 /*Unused DQ I/O Mode*/
15968 #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL
15969 #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT
15970 #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK
15971 #define DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL 0x01264000
15972 #define DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT 13
15973 #define DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK 0x00002000U
15975 /*Reserved. Return zeroes on reads.*/
15976 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL
15977 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT
15978 #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK
15979 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL 0x01264000
15980 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT 10
15981 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK 0x00001C00U
15984 #undef DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL
15985 #undef DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT
15986 #undef DDR_PHY_DX8SL3DQSCTL_DXSR_MASK
15987 #define DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL 0x01264000
15988 #define DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT 8
15989 #define DDR_PHY_DX8SL3DQSCTL_DXSR_MASK 0x00000300U
15992 #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL
15993 #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT
15994 #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK
15995 #define DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL 0x01264000
15996 #define DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT 4
15997 #define DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK 0x000000F0U
16000 #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL
16001 #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT
16002 #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK
16003 #define DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL 0x01264000
16004 #define DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT 0
16005 #define DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK 0x0000000FU
16007 /*Reserved. Return zeroes on reads.*/
16008 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL
16009 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT
16010 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK
16011 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL 0x00141800
16012 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT 24
16013 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK 0xFF000000U
16015 /*Configurable Read Data Enable*/
16016 #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL
16017 #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT
16018 #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK
16019 #define DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL 0x00141800
16020 #define DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT 23
16021 #define DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK 0x00800000U
16023 /*OX Extension during Post-amble*/
16024 #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL
16025 #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT
16026 #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK
16027 #define DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL 0x00141800
16028 #define DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT 20
16029 #define DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK 0x00700000U
16031 /*OE Extension during Pre-amble*/
16032 #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL
16033 #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT
16034 #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK
16035 #define DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL 0x00141800
16036 #define DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT 18
16037 #define DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK 0x000C0000U
16039 /*Reserved. Return zeroes on reads.*/
16040 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL
16041 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT
16042 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK
16043 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL 0x00141800
16044 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT 17
16045 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK 0x00020000U
16047 /*I/O Assisted Gate Select*/
16048 #undef DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL
16049 #undef DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT
16050 #undef DDR_PHY_DX8SL3DXCTL2_IOAG_MASK
16051 #define DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL 0x00141800
16052 #define DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT 16
16053 #define DDR_PHY_DX8SL3DXCTL2_IOAG_MASK 0x00010000U
16055 /*I/O Loopback Select*/
16056 #undef DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL
16057 #undef DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT
16058 #undef DDR_PHY_DX8SL3DXCTL2_IOLB_MASK
16059 #define DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL 0x00141800
16060 #define DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT 15
16061 #define DDR_PHY_DX8SL3DXCTL2_IOLB_MASK 0x00008000U
16063 /*Reserved. Return zeroes on reads.*/
16064 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL
16065 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT
16066 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK
16067 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL 0x00141800
16068 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT 13
16069 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK 0x00006000U
16071 /*Low Power Wakeup Threshold*/
16072 #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL
16073 #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT
16074 #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK
16075 #define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800
16076 #define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT 9
16077 #define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U
16079 /*Read Data Bus Inversion Enable*/
16080 #undef DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL
16081 #undef DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT
16082 #undef DDR_PHY_DX8SL3DXCTL2_RDBI_MASK
16083 #define DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL 0x00141800
16084 #define DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT 8
16085 #define DDR_PHY_DX8SL3DXCTL2_RDBI_MASK 0x00000100U
16087 /*Write Data Bus Inversion Enable*/
16088 #undef DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL
16089 #undef DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT
16090 #undef DDR_PHY_DX8SL3DXCTL2_WDBI_MASK
16091 #define DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL 0x00141800
16092 #define DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT 7
16093 #define DDR_PHY_DX8SL3DXCTL2_WDBI_MASK 0x00000080U
16095 /*PUB Read FIFO Bypass*/
16096 #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL
16097 #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT
16098 #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK
16099 #define DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL 0x00141800
16100 #define DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT 6
16101 #define DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK 0x00000040U
16103 /*DATX8 Receive FIFO Read Mode*/
16104 #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL
16105 #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT
16106 #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK
16107 #define DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL 0x00141800
16108 #define DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT 4
16109 #define DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK 0x00000030U
16111 /*Disables the Read FIFO Reset*/
16112 #undef DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL
16113 #undef DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT
16114 #undef DDR_PHY_DX8SL3DXCTL2_DISRST_MASK
16115 #define DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL 0x00141800
16116 #define DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT 3
16117 #define DDR_PHY_DX8SL3DXCTL2_DISRST_MASK 0x00000008U
16119 /*Read DQS Gate I/O Loopback*/
16120 #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL
16121 #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT
16122 #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK
16123 #define DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL 0x00141800
16124 #define DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT 1
16125 #define DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK 0x00000006U
16127 /*Reserved. Return zeroes on reads.*/
16128 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL
16129 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT
16130 #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK
16131 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL 0x00141800
16132 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT 0
16133 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK 0x00000001U
16135 /*Reserved. Return zeroes on reads.*/
16136 #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL
16137 #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT
16138 #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK
16139 #define DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL 0x00000000
16140 #define DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT 31
16141 #define DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK 0x80000000U
16143 /*PVREF_DAC REFSEL range select*/
16144 #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL
16145 #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT
16146 #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK
16147 #define DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL 0x00000000
16148 #define DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT 28
16149 #define DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK 0x70000000U
16151 /*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
16152 #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL
16153 #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT
16154 #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK
16155 #define DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL 0x00000000
16156 #define DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT 25
16157 #define DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK 0x0E000000U
16160 #undef DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL
16161 #undef DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT
16162 #undef DDR_PHY_DX8SL3IOCR_DXIOM_MASK
16163 #define DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL 0x00000000
16164 #define DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT 22
16165 #define DDR_PHY_DX8SL3IOCR_DXIOM_MASK 0x01C00000U
16167 /*DX IO Transmitter Mode*/
16168 #undef DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL
16169 #undef DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT
16170 #undef DDR_PHY_DX8SL3IOCR_DXTXM_MASK
16171 #define DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL 0x00000000
16172 #define DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT 11
16173 #define DDR_PHY_DX8SL3IOCR_DXTXM_MASK 0x003FF800U
16175 /*DX IO Receiver Mode*/
16176 #undef DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL
16177 #undef DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT
16178 #undef DDR_PHY_DX8SL3IOCR_DXRXM_MASK
16179 #define DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL 0x00000000
16180 #define DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT 0
16181 #define DDR_PHY_DX8SL3IOCR_DXRXM_MASK 0x000007FFU
16183 /*Reserved. Return zeroes on reads.*/
16184 #undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL
16185 #undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT
16186 #undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK
16187 #define DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL 0x00019FFE
16188 #define DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT 30
16189 #define DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK 0xC0000000U
16191 /*Enable Clock Gating for DX ddr_clk*/
16192 #undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL
16193 #undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT
16194 #undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK
16195 #define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL 0x00019FFE
16196 #define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT 28
16197 #define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK 0x30000000U
16199 /*Enable Clock Gating for DX ctl_rd_clk*/
16200 #undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL
16201 #undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT
16202 #undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK
16203 #define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE
16204 #define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT 26
16205 #define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK 0x0C000000U
16207 /*Enable Clock Gating for DX ctl_clk*/
16208 #undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL
16209 #undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT
16210 #undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK
16211 #define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE
16212 #define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT 24
16213 #define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK 0x03000000U
16215 /*Selects the level to which clocks will be stalled when clock gating is enabled.*/
16216 #undef DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL
16217 #undef DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT
16218 #undef DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK
16219 #define DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL 0x00019FFE
16220 #define DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT 22
16221 #define DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK 0x00C00000U
16224 #undef DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL
16225 #undef DDR_PHY_DX8SL4OSC_LBMODE_SHIFT
16226 #undef DDR_PHY_DX8SL4OSC_LBMODE_MASK
16227 #define DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL 0x00019FFE
16228 #define DDR_PHY_DX8SL4OSC_LBMODE_SHIFT 21
16229 #define DDR_PHY_DX8SL4OSC_LBMODE_MASK 0x00200000U
16231 /*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/
16232 #undef DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL
16233 #undef DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT
16234 #undef DDR_PHY_DX8SL4OSC_LBGSDQS_MASK
16235 #define DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL 0x00019FFE
16236 #define DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT 20
16237 #define DDR_PHY_DX8SL4OSC_LBGSDQS_MASK 0x00100000U
16239 /*Loopback DQS Gating*/
16240 #undef DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL
16241 #undef DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT
16242 #undef DDR_PHY_DX8SL4OSC_LBGDQS_MASK
16243 #define DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL 0x00019FFE
16244 #define DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT 18
16245 #define DDR_PHY_DX8SL4OSC_LBGDQS_MASK 0x000C0000U
16247 /*Loopback DQS Shift*/
16248 #undef DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL
16249 #undef DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT
16250 #undef DDR_PHY_DX8SL4OSC_LBDQSS_MASK
16251 #define DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL 0x00019FFE
16252 #define DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT 17
16253 #define DDR_PHY_DX8SL4OSC_LBDQSS_MASK 0x00020000U
16255 /*PHY High-Speed Reset*/
16256 #undef DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL
16257 #undef DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT
16258 #undef DDR_PHY_DX8SL4OSC_PHYHRST_MASK
16259 #define DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL 0x00019FFE
16260 #define DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT 16
16261 #define DDR_PHY_DX8SL4OSC_PHYHRST_MASK 0x00010000U
16264 #undef DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL
16265 #undef DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT
16266 #undef DDR_PHY_DX8SL4OSC_PHYFRST_MASK
16267 #define DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL 0x00019FFE
16268 #define DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT 15
16269 #define DDR_PHY_DX8SL4OSC_PHYFRST_MASK 0x00008000U
16271 /*Delay Line Test Start*/
16272 #undef DDR_PHY_DX8SL4OSC_DLTST_DEFVAL
16273 #undef DDR_PHY_DX8SL4OSC_DLTST_SHIFT
16274 #undef DDR_PHY_DX8SL4OSC_DLTST_MASK
16275 #define DDR_PHY_DX8SL4OSC_DLTST_DEFVAL 0x00019FFE
16276 #define DDR_PHY_DX8SL4OSC_DLTST_SHIFT 14
16277 #define DDR_PHY_DX8SL4OSC_DLTST_MASK 0x00004000U
16279 /*Delay Line Test Mode*/
16280 #undef DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL
16281 #undef DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT
16282 #undef DDR_PHY_DX8SL4OSC_DLTMODE_MASK
16283 #define DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL 0x00019FFE
16284 #define DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT 13
16285 #define DDR_PHY_DX8SL4OSC_DLTMODE_MASK 0x00002000U
16287 /*Reserved. Caution, do not write to this register field.*/
16288 #undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL
16289 #undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT
16290 #undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK
16291 #define DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL 0x00019FFE
16292 #define DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT 11
16293 #define DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK 0x00001800U
16295 /*Oscillator Mode Write-Data Delay Line Select*/
16296 #undef DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL
16297 #undef DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT
16298 #undef DDR_PHY_DX8SL4OSC_OSCWDDL_MASK
16299 #define DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL 0x00019FFE
16300 #define DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT 9
16301 #define DDR_PHY_DX8SL4OSC_OSCWDDL_MASK 0x00000600U
16303 /*Reserved. Caution, do not write to this register field.*/
16304 #undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL
16305 #undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT
16306 #undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK
16307 #define DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL 0x00019FFE
16308 #define DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT 7
16309 #define DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK 0x00000180U
16311 /*Oscillator Mode Write-Leveling Delay Line Select*/
16312 #undef DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL
16313 #undef DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT
16314 #undef DDR_PHY_DX8SL4OSC_OSCWDL_MASK
16315 #define DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL 0x00019FFE
16316 #define DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT 5
16317 #define DDR_PHY_DX8SL4OSC_OSCWDL_MASK 0x00000060U
16319 /*Oscillator Mode Division*/
16320 #undef DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL
16321 #undef DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT
16322 #undef DDR_PHY_DX8SL4OSC_OSCDIV_MASK
16323 #define DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL 0x00019FFE
16324 #define DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT 1
16325 #define DDR_PHY_DX8SL4OSC_OSCDIV_MASK 0x0000001EU
16327 /*Oscillator Enable*/
16328 #undef DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL
16329 #undef DDR_PHY_DX8SL4OSC_OSCEN_SHIFT
16330 #undef DDR_PHY_DX8SL4OSC_OSCEN_MASK
16331 #define DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL 0x00019FFE
16332 #define DDR_PHY_DX8SL4OSC_OSCEN_SHIFT 0
16333 #define DDR_PHY_DX8SL4OSC_OSCEN_MASK 0x00000001U
16335 /*Reserved. Return zeroes on reads.*/
16336 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL
16337 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT
16338 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK
16339 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL 0x01264000
16340 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT 25
16341 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK 0xFE000000U
16343 /*Read Path Rise-to-Rise Mode*/
16344 #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL
16345 #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT
16346 #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK
16347 #define DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL 0x01264000
16348 #define DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT 24
16349 #define DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK 0x01000000U
16351 /*Reserved. Return zeroes on reads.*/
16352 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL
16353 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT
16354 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK
16355 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL 0x01264000
16356 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT 22
16357 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK 0x00C00000U
16359 /*Write Path Rise-to-Rise Mode*/
16360 #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL
16361 #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT
16362 #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK
16363 #define DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL 0x01264000
16364 #define DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT 21
16365 #define DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK 0x00200000U
16367 /*DQS Gate Extension*/
16368 #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL
16369 #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT
16370 #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK
16371 #define DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL 0x01264000
16372 #define DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT 19
16373 #define DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK 0x00180000U
16375 /*Low Power PLL Power Down*/
16376 #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL
16377 #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT
16378 #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK
16379 #define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL 0x01264000
16380 #define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT 18
16381 #define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK 0x00040000U
16383 /*Low Power I/O Power Down*/
16384 #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL
16385 #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT
16386 #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK
16387 #define DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL 0x01264000
16388 #define DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT 17
16389 #define DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK 0x00020000U
16391 /*Reserved. Return zeroes on reads.*/
16392 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL
16393 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT
16394 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK
16395 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL 0x01264000
16396 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT 15
16397 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK 0x00018000U
16399 /*QS Counter Enable*/
16400 #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL
16401 #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT
16402 #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK
16403 #define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL 0x01264000
16404 #define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT 14
16405 #define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK 0x00004000U
16407 /*Unused DQ I/O Mode*/
16408 #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL
16409 #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT
16410 #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK
16411 #define DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL 0x01264000
16412 #define DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT 13
16413 #define DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK 0x00002000U
16415 /*Reserved. Return zeroes on reads.*/
16416 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL
16417 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT
16418 #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK
16419 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL 0x01264000
16420 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT 10
16421 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK 0x00001C00U
16424 #undef DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL
16425 #undef DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT
16426 #undef DDR_PHY_DX8SL4DQSCTL_DXSR_MASK
16427 #define DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL 0x01264000
16428 #define DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT 8
16429 #define DDR_PHY_DX8SL4DQSCTL_DXSR_MASK 0x00000300U
16432 #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL
16433 #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT
16434 #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK
16435 #define DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL 0x01264000
16436 #define DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT 4
16437 #define DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK 0x000000F0U
16440 #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL
16441 #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT
16442 #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK
16443 #define DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL 0x01264000
16444 #define DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT 0
16445 #define DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK 0x0000000FU
16447 /*Reserved. Return zeroes on reads.*/
16448 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL
16449 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT
16450 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK
16451 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL 0x00141800
16452 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT 24
16453 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK 0xFF000000U
16455 /*Configurable Read Data Enable*/
16456 #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL
16457 #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT
16458 #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK
16459 #define DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL 0x00141800
16460 #define DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT 23
16461 #define DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK 0x00800000U
16463 /*OX Extension during Post-amble*/
16464 #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL
16465 #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT
16466 #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK
16467 #define DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL 0x00141800
16468 #define DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT 20
16469 #define DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK 0x00700000U
16471 /*OE Extension during Pre-amble*/
16472 #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL
16473 #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT
16474 #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK
16475 #define DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL 0x00141800
16476 #define DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT 18
16477 #define DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK 0x000C0000U
16479 /*Reserved. Return zeroes on reads.*/
16480 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL
16481 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT
16482 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK
16483 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL 0x00141800
16484 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT 17
16485 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK 0x00020000U
16487 /*I/O Assisted Gate Select*/
16488 #undef DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL
16489 #undef DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT
16490 #undef DDR_PHY_DX8SL4DXCTL2_IOAG_MASK
16491 #define DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL 0x00141800
16492 #define DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT 16
16493 #define DDR_PHY_DX8SL4DXCTL2_IOAG_MASK 0x00010000U
16495 /*I/O Loopback Select*/
16496 #undef DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL
16497 #undef DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT
16498 #undef DDR_PHY_DX8SL4DXCTL2_IOLB_MASK
16499 #define DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL 0x00141800
16500 #define DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT 15
16501 #define DDR_PHY_DX8SL4DXCTL2_IOLB_MASK 0x00008000U
16503 /*Reserved. Return zeroes on reads.*/
16504 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL
16505 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT
16506 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK
16507 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL 0x00141800
16508 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT 13
16509 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK 0x00006000U
16511 /*Low Power Wakeup Threshold*/
16512 #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL
16513 #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT
16514 #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK
16515 #define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800
16516 #define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT 9
16517 #define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U
16519 /*Read Data Bus Inversion Enable*/
16520 #undef DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL
16521 #undef DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT
16522 #undef DDR_PHY_DX8SL4DXCTL2_RDBI_MASK
16523 #define DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL 0x00141800
16524 #define DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT 8
16525 #define DDR_PHY_DX8SL4DXCTL2_RDBI_MASK 0x00000100U
16527 /*Write Data Bus Inversion Enable*/
16528 #undef DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL
16529 #undef DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT
16530 #undef DDR_PHY_DX8SL4DXCTL2_WDBI_MASK
16531 #define DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL 0x00141800
16532 #define DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT 7
16533 #define DDR_PHY_DX8SL4DXCTL2_WDBI_MASK 0x00000080U
16535 /*PUB Read FIFO Bypass*/
16536 #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL
16537 #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT
16538 #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK
16539 #define DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL 0x00141800
16540 #define DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT 6
16541 #define DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK 0x00000040U
16543 /*DATX8 Receive FIFO Read Mode*/
16544 #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL
16545 #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT
16546 #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK
16547 #define DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL 0x00141800
16548 #define DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT 4
16549 #define DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK 0x00000030U
16551 /*Disables the Read FIFO Reset*/
16552 #undef DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL
16553 #undef DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT
16554 #undef DDR_PHY_DX8SL4DXCTL2_DISRST_MASK
16555 #define DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL 0x00141800
16556 #define DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT 3
16557 #define DDR_PHY_DX8SL4DXCTL2_DISRST_MASK 0x00000008U
16559 /*Read DQS Gate I/O Loopback*/
16560 #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL
16561 #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT
16562 #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK
16563 #define DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL 0x00141800
16564 #define DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT 1
16565 #define DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK 0x00000006U
16567 /*Reserved. Return zeroes on reads.*/
16568 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL
16569 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT
16570 #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK
16571 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL 0x00141800
16572 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT 0
16573 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK 0x00000001U
16575 /*Reserved. Return zeroes on reads.*/
16576 #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL
16577 #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT
16578 #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK
16579 #define DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL 0x00000000
16580 #define DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT 31
16581 #define DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK 0x80000000U
16583 /*PVREF_DAC REFSEL range select*/
16584 #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL
16585 #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT
16586 #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK
16587 #define DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL 0x00000000
16588 #define DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT 28
16589 #define DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK 0x70000000U
16591 /*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
16592 #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL
16593 #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT
16594 #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK
16595 #define DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL 0x00000000
16596 #define DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT 25
16597 #define DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK 0x0E000000U
16600 #undef DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL
16601 #undef DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT
16602 #undef DDR_PHY_DX8SL4IOCR_DXIOM_MASK
16603 #define DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL 0x00000000
16604 #define DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT 22
16605 #define DDR_PHY_DX8SL4IOCR_DXIOM_MASK 0x01C00000U
16607 /*DX IO Transmitter Mode*/
16608 #undef DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL
16609 #undef DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT
16610 #undef DDR_PHY_DX8SL4IOCR_DXTXM_MASK
16611 #define DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL 0x00000000
16612 #define DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT 11
16613 #define DDR_PHY_DX8SL4IOCR_DXTXM_MASK 0x003FF800U
16615 /*DX IO Receiver Mode*/
16616 #undef DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL
16617 #undef DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT
16618 #undef DDR_PHY_DX8SL4IOCR_DXRXM_MASK
16619 #define DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL 0x00000000
16620 #define DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT 0
16621 #define DDR_PHY_DX8SL4IOCR_DXRXM_MASK 0x000007FFU
16623 /*Reserved. Return zeroes on reads.*/
16624 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL
16625 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT
16626 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK
16627 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL 0x00000000
16628 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT 25
16629 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK 0xFE000000U
16631 /*Read Path Rise-to-Rise Mode*/
16632 #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL
16633 #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT
16634 #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK
16635 #define DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL 0x00000000
16636 #define DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT 24
16637 #define DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK 0x01000000U
16639 /*Reserved. Return zeroes on reads.*/
16640 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL
16641 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT
16642 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK
16643 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL 0x00000000
16644 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT 22
16645 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK 0x00C00000U
16647 /*Write Path Rise-to-Rise Mode*/
16648 #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL
16649 #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT
16650 #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK
16651 #define DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL 0x00000000
16652 #define DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT 21
16653 #define DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK 0x00200000U
16655 /*DQS Gate Extension*/
16656 #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL
16657 #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT
16658 #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK
16659 #define DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL 0x00000000
16660 #define DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT 19
16661 #define DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK 0x00180000U
16663 /*Low Power PLL Power Down*/
16664 #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL
16665 #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT
16666 #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK
16667 #define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL 0x00000000
16668 #define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT 18
16669 #define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK 0x00040000U
16671 /*Low Power I/O Power Down*/
16672 #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL
16673 #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT
16674 #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK
16675 #define DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL 0x00000000
16676 #define DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT 17
16677 #define DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK 0x00020000U
16679 /*Reserved. Return zeroes on reads.*/
16680 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL
16681 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT
16682 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK
16683 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL 0x00000000
16684 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT 15
16685 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK 0x00018000U
16687 /*QS Counter Enable*/
16688 #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL
16689 #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT
16690 #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK
16691 #define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL 0x00000000
16692 #define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT 14
16693 #define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK 0x00004000U
16695 /*Unused DQ I/O Mode*/
16696 #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL
16697 #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT
16698 #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK
16699 #define DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL 0x00000000
16700 #define DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT 13
16701 #define DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK 0x00002000U
16703 /*Reserved. Return zeroes on reads.*/
16704 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL
16705 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT
16706 #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK
16707 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL 0x00000000
16708 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT 10
16709 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK 0x00001C00U
16712 #undef DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL
16713 #undef DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT
16714 #undef DDR_PHY_DX8SLBDQSCTL_DXSR_MASK
16715 #define DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL 0x00000000
16716 #define DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT 8
16717 #define DDR_PHY_DX8SLBDQSCTL_DXSR_MASK 0x00000300U
16720 #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL
16721 #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT
16722 #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK
16723 #define DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL 0x00000000
16724 #define DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT 4
16725 #define DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK 0x000000F0U
16728 #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL
16729 #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT
16730 #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK
16731 #define DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL 0x00000000
16732 #define DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT 0
16733 #define DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK 0x0000000FU
16735 /*Reserved. Return zeroes on reads.*/
16736 #undef DDR_PHY_PIR_RESERVED_31_DEFVAL
16737 #undef DDR_PHY_PIR_RESERVED_31_SHIFT
16738 #undef DDR_PHY_PIR_RESERVED_31_MASK
16739 #define DDR_PHY_PIR_RESERVED_31_DEFVAL 0x00000000
16740 #define DDR_PHY_PIR_RESERVED_31_SHIFT 31
16741 #define DDR_PHY_PIR_RESERVED_31_MASK 0x80000000U
16743 /*Impedance Calibration Bypass*/
16744 #undef DDR_PHY_PIR_ZCALBYP_DEFVAL
16745 #undef DDR_PHY_PIR_ZCALBYP_SHIFT
16746 #undef DDR_PHY_PIR_ZCALBYP_MASK
16747 #define DDR_PHY_PIR_ZCALBYP_DEFVAL 0x00000000
16748 #define DDR_PHY_PIR_ZCALBYP_SHIFT 30
16749 #define DDR_PHY_PIR_ZCALBYP_MASK 0x40000000U
16751 /*Digital Delay Line (DDL) Calibration Pause*/
16752 #undef DDR_PHY_PIR_DCALPSE_DEFVAL
16753 #undef DDR_PHY_PIR_DCALPSE_SHIFT
16754 #undef DDR_PHY_PIR_DCALPSE_MASK
16755 #define DDR_PHY_PIR_DCALPSE_DEFVAL 0x00000000
16756 #define DDR_PHY_PIR_DCALPSE_SHIFT 29
16757 #define DDR_PHY_PIR_DCALPSE_MASK 0x20000000U
16759 /*Reserved. Return zeroes on reads.*/
16760 #undef DDR_PHY_PIR_RESERVED_28_21_DEFVAL
16761 #undef DDR_PHY_PIR_RESERVED_28_21_SHIFT
16762 #undef DDR_PHY_PIR_RESERVED_28_21_MASK
16763 #define DDR_PHY_PIR_RESERVED_28_21_DEFVAL 0x00000000
16764 #define DDR_PHY_PIR_RESERVED_28_21_SHIFT 21
16765 #define DDR_PHY_PIR_RESERVED_28_21_MASK 0x1FE00000U
16767 /*Write DQS2DQ Training*/
16768 #undef DDR_PHY_PIR_DQS2DQ_DEFVAL
16769 #undef DDR_PHY_PIR_DQS2DQ_SHIFT
16770 #undef DDR_PHY_PIR_DQS2DQ_MASK
16771 #define DDR_PHY_PIR_DQS2DQ_DEFVAL 0x00000000
16772 #define DDR_PHY_PIR_DQS2DQ_SHIFT 20
16773 #define DDR_PHY_PIR_DQS2DQ_MASK 0x00100000U
16775 /*RDIMM Initialization*/
16776 #undef DDR_PHY_PIR_RDIMMINIT_DEFVAL
16777 #undef DDR_PHY_PIR_RDIMMINIT_SHIFT
16778 #undef DDR_PHY_PIR_RDIMMINIT_MASK
16779 #define DDR_PHY_PIR_RDIMMINIT_DEFVAL 0x00000000
16780 #define DDR_PHY_PIR_RDIMMINIT_SHIFT 19
16781 #define DDR_PHY_PIR_RDIMMINIT_MASK 0x00080000U
16783 /*Controller DRAM Initialization*/
16784 #undef DDR_PHY_PIR_CTLDINIT_DEFVAL
16785 #undef DDR_PHY_PIR_CTLDINIT_SHIFT
16786 #undef DDR_PHY_PIR_CTLDINIT_MASK
16787 #define DDR_PHY_PIR_CTLDINIT_DEFVAL 0x00000000
16788 #define DDR_PHY_PIR_CTLDINIT_SHIFT 18
16789 #define DDR_PHY_PIR_CTLDINIT_MASK 0x00040000U
16792 #undef DDR_PHY_PIR_VREF_DEFVAL
16793 #undef DDR_PHY_PIR_VREF_SHIFT
16794 #undef DDR_PHY_PIR_VREF_MASK
16795 #define DDR_PHY_PIR_VREF_DEFVAL 0x00000000
16796 #define DDR_PHY_PIR_VREF_SHIFT 17
16797 #define DDR_PHY_PIR_VREF_MASK 0x00020000U
16799 /*Static Read Training*/
16800 #undef DDR_PHY_PIR_SRD_DEFVAL
16801 #undef DDR_PHY_PIR_SRD_SHIFT
16802 #undef DDR_PHY_PIR_SRD_MASK
16803 #define DDR_PHY_PIR_SRD_DEFVAL 0x00000000
16804 #define DDR_PHY_PIR_SRD_SHIFT 16
16805 #define DDR_PHY_PIR_SRD_MASK 0x00010000U
16807 /*Write Data Eye Training*/
16808 #undef DDR_PHY_PIR_WREYE_DEFVAL
16809 #undef DDR_PHY_PIR_WREYE_SHIFT
16810 #undef DDR_PHY_PIR_WREYE_MASK
16811 #define DDR_PHY_PIR_WREYE_DEFVAL 0x00000000
16812 #define DDR_PHY_PIR_WREYE_SHIFT 15
16813 #define DDR_PHY_PIR_WREYE_MASK 0x00008000U
16815 /*Read Data Eye Training*/
16816 #undef DDR_PHY_PIR_RDEYE_DEFVAL
16817 #undef DDR_PHY_PIR_RDEYE_SHIFT
16818 #undef DDR_PHY_PIR_RDEYE_MASK
16819 #define DDR_PHY_PIR_RDEYE_DEFVAL 0x00000000
16820 #define DDR_PHY_PIR_RDEYE_SHIFT 14
16821 #define DDR_PHY_PIR_RDEYE_MASK 0x00004000U
16823 /*Write Data Bit Deskew*/
16824 #undef DDR_PHY_PIR_WRDSKW_DEFVAL
16825 #undef DDR_PHY_PIR_WRDSKW_SHIFT
16826 #undef DDR_PHY_PIR_WRDSKW_MASK
16827 #define DDR_PHY_PIR_WRDSKW_DEFVAL 0x00000000
16828 #define DDR_PHY_PIR_WRDSKW_SHIFT 13
16829 #define DDR_PHY_PIR_WRDSKW_MASK 0x00002000U
16831 /*Read Data Bit Deskew*/
16832 #undef DDR_PHY_PIR_RDDSKW_DEFVAL
16833 #undef DDR_PHY_PIR_RDDSKW_SHIFT
16834 #undef DDR_PHY_PIR_RDDSKW_MASK
16835 #define DDR_PHY_PIR_RDDSKW_DEFVAL 0x00000000
16836 #define DDR_PHY_PIR_RDDSKW_SHIFT 12
16837 #define DDR_PHY_PIR_RDDSKW_MASK 0x00001000U
16839 /*Write Leveling Adjust*/
16840 #undef DDR_PHY_PIR_WLADJ_DEFVAL
16841 #undef DDR_PHY_PIR_WLADJ_SHIFT
16842 #undef DDR_PHY_PIR_WLADJ_MASK
16843 #define DDR_PHY_PIR_WLADJ_DEFVAL 0x00000000
16844 #define DDR_PHY_PIR_WLADJ_SHIFT 11
16845 #define DDR_PHY_PIR_WLADJ_MASK 0x00000800U
16847 /*Read DQS Gate Training*/
16848 #undef DDR_PHY_PIR_QSGATE_DEFVAL
16849 #undef DDR_PHY_PIR_QSGATE_SHIFT
16850 #undef DDR_PHY_PIR_QSGATE_MASK
16851 #define DDR_PHY_PIR_QSGATE_DEFVAL 0x00000000
16852 #define DDR_PHY_PIR_QSGATE_SHIFT 10
16853 #define DDR_PHY_PIR_QSGATE_MASK 0x00000400U
16856 #undef DDR_PHY_PIR_WL_DEFVAL
16857 #undef DDR_PHY_PIR_WL_SHIFT
16858 #undef DDR_PHY_PIR_WL_MASK
16859 #define DDR_PHY_PIR_WL_DEFVAL 0x00000000
16860 #define DDR_PHY_PIR_WL_SHIFT 9
16861 #define DDR_PHY_PIR_WL_MASK 0x00000200U
16863 /*DRAM Initialization*/
16864 #undef DDR_PHY_PIR_DRAMINIT_DEFVAL
16865 #undef DDR_PHY_PIR_DRAMINIT_SHIFT
16866 #undef DDR_PHY_PIR_DRAMINIT_MASK
16867 #define DDR_PHY_PIR_DRAMINIT_DEFVAL 0x00000000
16868 #define DDR_PHY_PIR_DRAMINIT_SHIFT 8
16869 #define DDR_PHY_PIR_DRAMINIT_MASK 0x00000100U
16871 /*DRAM Reset (DDR3/DDR4/LPDDR4 Only)*/
16872 #undef DDR_PHY_PIR_DRAMRST_DEFVAL
16873 #undef DDR_PHY_PIR_DRAMRST_SHIFT
16874 #undef DDR_PHY_PIR_DRAMRST_MASK
16875 #define DDR_PHY_PIR_DRAMRST_DEFVAL 0x00000000
16876 #define DDR_PHY_PIR_DRAMRST_SHIFT 7
16877 #define DDR_PHY_PIR_DRAMRST_MASK 0x00000080U
16880 #undef DDR_PHY_PIR_PHYRST_DEFVAL
16881 #undef DDR_PHY_PIR_PHYRST_SHIFT
16882 #undef DDR_PHY_PIR_PHYRST_MASK
16883 #define DDR_PHY_PIR_PHYRST_DEFVAL 0x00000000
16884 #define DDR_PHY_PIR_PHYRST_SHIFT 6
16885 #define DDR_PHY_PIR_PHYRST_MASK 0x00000040U
16887 /*Digital Delay Line (DDL) Calibration*/
16888 #undef DDR_PHY_PIR_DCAL_DEFVAL
16889 #undef DDR_PHY_PIR_DCAL_SHIFT
16890 #undef DDR_PHY_PIR_DCAL_MASK
16891 #define DDR_PHY_PIR_DCAL_DEFVAL 0x00000000
16892 #define DDR_PHY_PIR_DCAL_SHIFT 5
16893 #define DDR_PHY_PIR_DCAL_MASK 0x00000020U
16895 /*PLL Initialiazation*/
16896 #undef DDR_PHY_PIR_PLLINIT_DEFVAL
16897 #undef DDR_PHY_PIR_PLLINIT_SHIFT
16898 #undef DDR_PHY_PIR_PLLINIT_MASK
16899 #define DDR_PHY_PIR_PLLINIT_DEFVAL 0x00000000
16900 #define DDR_PHY_PIR_PLLINIT_SHIFT 4
16901 #define DDR_PHY_PIR_PLLINIT_MASK 0x00000010U
16903 /*Reserved. Return zeroes on reads.*/
16904 #undef DDR_PHY_PIR_RESERVED_3_DEFVAL
16905 #undef DDR_PHY_PIR_RESERVED_3_SHIFT
16906 #undef DDR_PHY_PIR_RESERVED_3_MASK
16907 #define DDR_PHY_PIR_RESERVED_3_DEFVAL 0x00000000
16908 #define DDR_PHY_PIR_RESERVED_3_SHIFT 3
16909 #define DDR_PHY_PIR_RESERVED_3_MASK 0x00000008U
16912 #undef DDR_PHY_PIR_CA_DEFVAL
16913 #undef DDR_PHY_PIR_CA_SHIFT
16914 #undef DDR_PHY_PIR_CA_MASK
16915 #define DDR_PHY_PIR_CA_DEFVAL 0x00000000
16916 #define DDR_PHY_PIR_CA_SHIFT 2
16917 #define DDR_PHY_PIR_CA_MASK 0x00000004U
16919 /*Impedance Calibration*/
16920 #undef DDR_PHY_PIR_ZCAL_DEFVAL
16921 #undef DDR_PHY_PIR_ZCAL_SHIFT
16922 #undef DDR_PHY_PIR_ZCAL_MASK
16923 #define DDR_PHY_PIR_ZCAL_DEFVAL 0x00000000
16924 #define DDR_PHY_PIR_ZCAL_SHIFT 1
16925 #define DDR_PHY_PIR_ZCAL_MASK 0x00000002U
16927 /*Initialization Trigger*/
16928 #undef DDR_PHY_PIR_INIT_DEFVAL
16929 #undef DDR_PHY_PIR_INIT_SHIFT
16930 #undef DDR_PHY_PIR_INIT_MASK
16931 #define DDR_PHY_PIR_INIT_DEFVAL 0x00000000
16932 #define DDR_PHY_PIR_INIT_SHIFT 0
16933 #define DDR_PHY_PIR_INIT_MASK 0x00000001U
16934 #undef IOU_SLCR_MIO_PIN_0_OFFSET
16935 #define IOU_SLCR_MIO_PIN_0_OFFSET 0XFF180000
16936 #undef IOU_SLCR_MIO_PIN_1_OFFSET
16937 #define IOU_SLCR_MIO_PIN_1_OFFSET 0XFF180004
16938 #undef IOU_SLCR_MIO_PIN_2_OFFSET
16939 #define IOU_SLCR_MIO_PIN_2_OFFSET 0XFF180008
16940 #undef IOU_SLCR_MIO_PIN_3_OFFSET
16941 #define IOU_SLCR_MIO_PIN_3_OFFSET 0XFF18000C
16942 #undef IOU_SLCR_MIO_PIN_4_OFFSET
16943 #define IOU_SLCR_MIO_PIN_4_OFFSET 0XFF180010
16944 #undef IOU_SLCR_MIO_PIN_5_OFFSET
16945 #define IOU_SLCR_MIO_PIN_5_OFFSET 0XFF180014
16946 #undef IOU_SLCR_MIO_PIN_6_OFFSET
16947 #define IOU_SLCR_MIO_PIN_6_OFFSET 0XFF180018
16948 #undef IOU_SLCR_MIO_PIN_7_OFFSET
16949 #define IOU_SLCR_MIO_PIN_7_OFFSET 0XFF18001C
16950 #undef IOU_SLCR_MIO_PIN_8_OFFSET
16951 #define IOU_SLCR_MIO_PIN_8_OFFSET 0XFF180020
16952 #undef IOU_SLCR_MIO_PIN_9_OFFSET
16953 #define IOU_SLCR_MIO_PIN_9_OFFSET 0XFF180024
16954 #undef IOU_SLCR_MIO_PIN_10_OFFSET
16955 #define IOU_SLCR_MIO_PIN_10_OFFSET 0XFF180028
16956 #undef IOU_SLCR_MIO_PIN_11_OFFSET
16957 #define IOU_SLCR_MIO_PIN_11_OFFSET 0XFF18002C
16958 #undef IOU_SLCR_MIO_PIN_12_OFFSET
16959 #define IOU_SLCR_MIO_PIN_12_OFFSET 0XFF180030
16960 #undef IOU_SLCR_MIO_PIN_13_OFFSET
16961 #define IOU_SLCR_MIO_PIN_13_OFFSET 0XFF180034
16962 #undef IOU_SLCR_MIO_PIN_14_OFFSET
16963 #define IOU_SLCR_MIO_PIN_14_OFFSET 0XFF180038
16964 #undef IOU_SLCR_MIO_PIN_15_OFFSET
16965 #define IOU_SLCR_MIO_PIN_15_OFFSET 0XFF18003C
16966 #undef IOU_SLCR_MIO_PIN_16_OFFSET
16967 #define IOU_SLCR_MIO_PIN_16_OFFSET 0XFF180040
16968 #undef IOU_SLCR_MIO_PIN_17_OFFSET
16969 #define IOU_SLCR_MIO_PIN_17_OFFSET 0XFF180044
16970 #undef IOU_SLCR_MIO_PIN_18_OFFSET
16971 #define IOU_SLCR_MIO_PIN_18_OFFSET 0XFF180048
16972 #undef IOU_SLCR_MIO_PIN_19_OFFSET
16973 #define IOU_SLCR_MIO_PIN_19_OFFSET 0XFF18004C
16974 #undef IOU_SLCR_MIO_PIN_20_OFFSET
16975 #define IOU_SLCR_MIO_PIN_20_OFFSET 0XFF180050
16976 #undef IOU_SLCR_MIO_PIN_21_OFFSET
16977 #define IOU_SLCR_MIO_PIN_21_OFFSET 0XFF180054
16978 #undef IOU_SLCR_MIO_PIN_22_OFFSET
16979 #define IOU_SLCR_MIO_PIN_22_OFFSET 0XFF180058
16980 #undef IOU_SLCR_MIO_PIN_23_OFFSET
16981 #define IOU_SLCR_MIO_PIN_23_OFFSET 0XFF18005C
16982 #undef IOU_SLCR_MIO_PIN_24_OFFSET
16983 #define IOU_SLCR_MIO_PIN_24_OFFSET 0XFF180060
16984 #undef IOU_SLCR_MIO_PIN_25_OFFSET
16985 #define IOU_SLCR_MIO_PIN_25_OFFSET 0XFF180064
16986 #undef IOU_SLCR_MIO_PIN_26_OFFSET
16987 #define IOU_SLCR_MIO_PIN_26_OFFSET 0XFF180068
16988 #undef IOU_SLCR_MIO_PIN_27_OFFSET
16989 #define IOU_SLCR_MIO_PIN_27_OFFSET 0XFF18006C
16990 #undef IOU_SLCR_MIO_PIN_28_OFFSET
16991 #define IOU_SLCR_MIO_PIN_28_OFFSET 0XFF180070
16992 #undef IOU_SLCR_MIO_PIN_29_OFFSET
16993 #define IOU_SLCR_MIO_PIN_29_OFFSET 0XFF180074
16994 #undef IOU_SLCR_MIO_PIN_30_OFFSET
16995 #define IOU_SLCR_MIO_PIN_30_OFFSET 0XFF180078
16996 #undef IOU_SLCR_MIO_PIN_31_OFFSET
16997 #define IOU_SLCR_MIO_PIN_31_OFFSET 0XFF18007C
16998 #undef IOU_SLCR_MIO_PIN_32_OFFSET
16999 #define IOU_SLCR_MIO_PIN_32_OFFSET 0XFF180080
17000 #undef IOU_SLCR_MIO_PIN_33_OFFSET
17001 #define IOU_SLCR_MIO_PIN_33_OFFSET 0XFF180084
17002 #undef IOU_SLCR_MIO_PIN_34_OFFSET
17003 #define IOU_SLCR_MIO_PIN_34_OFFSET 0XFF180088
17004 #undef IOU_SLCR_MIO_PIN_35_OFFSET
17005 #define IOU_SLCR_MIO_PIN_35_OFFSET 0XFF18008C
17006 #undef IOU_SLCR_MIO_PIN_36_OFFSET
17007 #define IOU_SLCR_MIO_PIN_36_OFFSET 0XFF180090
17008 #undef IOU_SLCR_MIO_PIN_37_OFFSET
17009 #define IOU_SLCR_MIO_PIN_37_OFFSET 0XFF180094
17010 #undef IOU_SLCR_MIO_PIN_38_OFFSET
17011 #define IOU_SLCR_MIO_PIN_38_OFFSET 0XFF180098
17012 #undef IOU_SLCR_MIO_PIN_39_OFFSET
17013 #define IOU_SLCR_MIO_PIN_39_OFFSET 0XFF18009C
17014 #undef IOU_SLCR_MIO_PIN_40_OFFSET
17015 #define IOU_SLCR_MIO_PIN_40_OFFSET 0XFF1800A0
17016 #undef IOU_SLCR_MIO_PIN_41_OFFSET
17017 #define IOU_SLCR_MIO_PIN_41_OFFSET 0XFF1800A4
17018 #undef IOU_SLCR_MIO_PIN_42_OFFSET
17019 #define IOU_SLCR_MIO_PIN_42_OFFSET 0XFF1800A8
17020 #undef IOU_SLCR_MIO_PIN_43_OFFSET
17021 #define IOU_SLCR_MIO_PIN_43_OFFSET 0XFF1800AC
17022 #undef IOU_SLCR_MIO_PIN_44_OFFSET
17023 #define IOU_SLCR_MIO_PIN_44_OFFSET 0XFF1800B0
17024 #undef IOU_SLCR_MIO_PIN_45_OFFSET
17025 #define IOU_SLCR_MIO_PIN_45_OFFSET 0XFF1800B4
17026 #undef IOU_SLCR_MIO_PIN_46_OFFSET
17027 #define IOU_SLCR_MIO_PIN_46_OFFSET 0XFF1800B8
17028 #undef IOU_SLCR_MIO_PIN_47_OFFSET
17029 #define IOU_SLCR_MIO_PIN_47_OFFSET 0XFF1800BC
17030 #undef IOU_SLCR_MIO_PIN_48_OFFSET
17031 #define IOU_SLCR_MIO_PIN_48_OFFSET 0XFF1800C0
17032 #undef IOU_SLCR_MIO_PIN_49_OFFSET
17033 #define IOU_SLCR_MIO_PIN_49_OFFSET 0XFF1800C4
17034 #undef IOU_SLCR_MIO_PIN_50_OFFSET
17035 #define IOU_SLCR_MIO_PIN_50_OFFSET 0XFF1800C8
17036 #undef IOU_SLCR_MIO_PIN_51_OFFSET
17037 #define IOU_SLCR_MIO_PIN_51_OFFSET 0XFF1800CC
17038 #undef IOU_SLCR_MIO_PIN_52_OFFSET
17039 #define IOU_SLCR_MIO_PIN_52_OFFSET 0XFF1800D0
17040 #undef IOU_SLCR_MIO_PIN_53_OFFSET
17041 #define IOU_SLCR_MIO_PIN_53_OFFSET 0XFF1800D4
17042 #undef IOU_SLCR_MIO_PIN_54_OFFSET
17043 #define IOU_SLCR_MIO_PIN_54_OFFSET 0XFF1800D8
17044 #undef IOU_SLCR_MIO_PIN_55_OFFSET
17045 #define IOU_SLCR_MIO_PIN_55_OFFSET 0XFF1800DC
17046 #undef IOU_SLCR_MIO_PIN_56_OFFSET
17047 #define IOU_SLCR_MIO_PIN_56_OFFSET 0XFF1800E0
17048 #undef IOU_SLCR_MIO_PIN_57_OFFSET
17049 #define IOU_SLCR_MIO_PIN_57_OFFSET 0XFF1800E4
17050 #undef IOU_SLCR_MIO_PIN_58_OFFSET
17051 #define IOU_SLCR_MIO_PIN_58_OFFSET 0XFF1800E8
17052 #undef IOU_SLCR_MIO_PIN_59_OFFSET
17053 #define IOU_SLCR_MIO_PIN_59_OFFSET 0XFF1800EC
17054 #undef IOU_SLCR_MIO_PIN_60_OFFSET
17055 #define IOU_SLCR_MIO_PIN_60_OFFSET 0XFF1800F0
17056 #undef IOU_SLCR_MIO_PIN_61_OFFSET
17057 #define IOU_SLCR_MIO_PIN_61_OFFSET 0XFF1800F4
17058 #undef IOU_SLCR_MIO_PIN_62_OFFSET
17059 #define IOU_SLCR_MIO_PIN_62_OFFSET 0XFF1800F8
17060 #undef IOU_SLCR_MIO_PIN_63_OFFSET
17061 #define IOU_SLCR_MIO_PIN_63_OFFSET 0XFF1800FC
17062 #undef IOU_SLCR_MIO_PIN_64_OFFSET
17063 #define IOU_SLCR_MIO_PIN_64_OFFSET 0XFF180100
17064 #undef IOU_SLCR_MIO_PIN_65_OFFSET
17065 #define IOU_SLCR_MIO_PIN_65_OFFSET 0XFF180104
17066 #undef IOU_SLCR_MIO_PIN_66_OFFSET
17067 #define IOU_SLCR_MIO_PIN_66_OFFSET 0XFF180108
17068 #undef IOU_SLCR_MIO_PIN_67_OFFSET
17069 #define IOU_SLCR_MIO_PIN_67_OFFSET 0XFF18010C
17070 #undef IOU_SLCR_MIO_PIN_68_OFFSET
17071 #define IOU_SLCR_MIO_PIN_68_OFFSET 0XFF180110
17072 #undef IOU_SLCR_MIO_PIN_69_OFFSET
17073 #define IOU_SLCR_MIO_PIN_69_OFFSET 0XFF180114
17074 #undef IOU_SLCR_MIO_PIN_70_OFFSET
17075 #define IOU_SLCR_MIO_PIN_70_OFFSET 0XFF180118
17076 #undef IOU_SLCR_MIO_PIN_71_OFFSET
17077 #define IOU_SLCR_MIO_PIN_71_OFFSET 0XFF18011C
17078 #undef IOU_SLCR_MIO_PIN_72_OFFSET
17079 #define IOU_SLCR_MIO_PIN_72_OFFSET 0XFF180120
17080 #undef IOU_SLCR_MIO_PIN_73_OFFSET
17081 #define IOU_SLCR_MIO_PIN_73_OFFSET 0XFF180124
17082 #undef IOU_SLCR_MIO_PIN_74_OFFSET
17083 #define IOU_SLCR_MIO_PIN_74_OFFSET 0XFF180128
17084 #undef IOU_SLCR_MIO_PIN_75_OFFSET
17085 #define IOU_SLCR_MIO_PIN_75_OFFSET 0XFF18012C
17086 #undef IOU_SLCR_MIO_PIN_76_OFFSET
17087 #define IOU_SLCR_MIO_PIN_76_OFFSET 0XFF180130
17088 #undef IOU_SLCR_MIO_PIN_77_OFFSET
17089 #define IOU_SLCR_MIO_PIN_77_OFFSET 0XFF180134
17090 #undef IOU_SLCR_MIO_MST_TRI0_OFFSET
17091 #define IOU_SLCR_MIO_MST_TRI0_OFFSET 0XFF180204
17092 #undef IOU_SLCR_MIO_MST_TRI1_OFFSET
17093 #define IOU_SLCR_MIO_MST_TRI1_OFFSET 0XFF180208
17094 #undef IOU_SLCR_MIO_MST_TRI2_OFFSET
17095 #define IOU_SLCR_MIO_MST_TRI2_OFFSET 0XFF18020C
17096 #undef IOU_SLCR_BANK0_CTRL0_OFFSET
17097 #define IOU_SLCR_BANK0_CTRL0_OFFSET 0XFF180138
17098 #undef IOU_SLCR_BANK0_CTRL1_OFFSET
17099 #define IOU_SLCR_BANK0_CTRL1_OFFSET 0XFF18013C
17100 #undef IOU_SLCR_BANK0_CTRL3_OFFSET
17101 #define IOU_SLCR_BANK0_CTRL3_OFFSET 0XFF180140
17102 #undef IOU_SLCR_BANK0_CTRL4_OFFSET
17103 #define IOU_SLCR_BANK0_CTRL4_OFFSET 0XFF180144
17104 #undef IOU_SLCR_BANK0_CTRL5_OFFSET
17105 #define IOU_SLCR_BANK0_CTRL5_OFFSET 0XFF180148
17106 #undef IOU_SLCR_BANK0_CTRL6_OFFSET
17107 #define IOU_SLCR_BANK0_CTRL6_OFFSET 0XFF18014C
17108 #undef IOU_SLCR_BANK1_CTRL0_OFFSET
17109 #define IOU_SLCR_BANK1_CTRL0_OFFSET 0XFF180154
17110 #undef IOU_SLCR_BANK1_CTRL1_OFFSET
17111 #define IOU_SLCR_BANK1_CTRL1_OFFSET 0XFF180158
17112 #undef IOU_SLCR_BANK1_CTRL3_OFFSET
17113 #define IOU_SLCR_BANK1_CTRL3_OFFSET 0XFF18015C
17114 #undef IOU_SLCR_BANK1_CTRL4_OFFSET
17115 #define IOU_SLCR_BANK1_CTRL4_OFFSET 0XFF180160
17116 #undef IOU_SLCR_BANK1_CTRL5_OFFSET
17117 #define IOU_SLCR_BANK1_CTRL5_OFFSET 0XFF180164
17118 #undef IOU_SLCR_BANK1_CTRL6_OFFSET
17119 #define IOU_SLCR_BANK1_CTRL6_OFFSET 0XFF180168
17120 #undef IOU_SLCR_BANK2_CTRL0_OFFSET
17121 #define IOU_SLCR_BANK2_CTRL0_OFFSET 0XFF180170
17122 #undef IOU_SLCR_BANK2_CTRL1_OFFSET
17123 #define IOU_SLCR_BANK2_CTRL1_OFFSET 0XFF180174
17124 #undef IOU_SLCR_BANK2_CTRL3_OFFSET
17125 #define IOU_SLCR_BANK2_CTRL3_OFFSET 0XFF180178
17126 #undef IOU_SLCR_BANK2_CTRL4_OFFSET
17127 #define IOU_SLCR_BANK2_CTRL4_OFFSET 0XFF18017C
17128 #undef IOU_SLCR_BANK2_CTRL5_OFFSET
17129 #define IOU_SLCR_BANK2_CTRL5_OFFSET 0XFF180180
17130 #undef IOU_SLCR_BANK2_CTRL6_OFFSET
17131 #define IOU_SLCR_BANK2_CTRL6_OFFSET 0XFF180184
17132 #undef IOU_SLCR_MIO_LOOPBACK_OFFSET
17133 #define IOU_SLCR_MIO_LOOPBACK_OFFSET 0XFF180200
17135 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)*/
17136 #undef IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL
17137 #undef IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT
17138 #undef IOU_SLCR_MIO_PIN_0_L0_SEL_MASK
17139 #define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 0x00000000
17140 #define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 1
17141 #define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK 0x00000002U
17143 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17144 #undef IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL
17145 #undef IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT
17146 #undef IOU_SLCR_MIO_PIN_0_L1_SEL_MASK
17147 #define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 0x00000000
17148 #define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 2
17149 #define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK 0x00000004U
17151 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp
17152 t, test_scan_out[0]- (Test Scan Port) 3= Not Used*/
17153 #undef IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL
17154 #undef IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT
17155 #undef IOU_SLCR_MIO_PIN_0_L2_SEL_MASK
17156 #define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 0x00000000
17157 #define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 3
17158 #define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK 0x00000018U
17160 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can
17161 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
17162 ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
17163 ) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
17164 lk- (Trace Port Clock)*/
17165 #undef IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL
17166 #undef IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT
17167 #undef IOU_SLCR_MIO_PIN_0_L3_SEL_MASK
17168 #define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 0x00000000
17169 #define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 5
17170 #define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK 0x000000E0U
17172 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data
17174 #undef IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL
17175 #undef IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT
17176 #undef IOU_SLCR_MIO_PIN_1_L0_SEL_MASK
17177 #define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 0x00000000
17178 #define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 1
17179 #define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK 0x00000002U
17181 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17182 #undef IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL
17183 #undef IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT
17184 #undef IOU_SLCR_MIO_PIN_1_L1_SEL_MASK
17185 #define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 0x00000000
17186 #define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 2
17187 #define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK 0x00000004U
17189 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp
17190 t, test_scan_out[1]- (Test Scan Port) 3= Not Used*/
17191 #undef IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL
17192 #undef IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT
17193 #undef IOU_SLCR_MIO_PIN_1_L2_SEL_MASK
17194 #define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 0x00000000
17195 #define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 3
17196 #define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK 0x00000018U
17198 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can
17199 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
17200 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o
17201 t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
17203 #undef IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL
17204 #undef IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT
17205 #undef IOU_SLCR_MIO_PIN_1_L3_SEL_MASK
17206 #define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 0x00000000
17207 #define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 5
17208 #define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK 0x000000E0U
17210 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)*/
17211 #undef IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL
17212 #undef IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT
17213 #undef IOU_SLCR_MIO_PIN_2_L0_SEL_MASK
17214 #define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 0x00000000
17215 #define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 1
17216 #define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK 0x00000002U
17218 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17219 #undef IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL
17220 #undef IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT
17221 #undef IOU_SLCR_MIO_PIN_2_L1_SEL_MASK
17222 #define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 0x00000000
17223 #define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 2
17224 #define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK 0x00000004U
17226 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp
17227 t, test_scan_out[2]- (Test Scan Port) 3= Not Used*/
17228 #undef IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL
17229 #undef IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT
17230 #undef IOU_SLCR_MIO_PIN_2_L2_SEL_MASK
17231 #define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 0x00000000
17232 #define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 3
17233 #define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK 0x00000018U
17235 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can
17236 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
17237 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in
17238 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
17239 #undef IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL
17240 #undef IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT
17241 #undef IOU_SLCR_MIO_PIN_2_L3_SEL_MASK
17242 #define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 0x00000000
17243 #define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 5
17244 #define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK 0x000000E0U
17246 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)*/
17247 #undef IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL
17248 #undef IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT
17249 #undef IOU_SLCR_MIO_PIN_3_L0_SEL_MASK
17250 #define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 0x00000000
17251 #define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 1
17252 #define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK 0x00000002U
17254 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17255 #undef IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL
17256 #undef IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT
17257 #undef IOU_SLCR_MIO_PIN_3_L1_SEL_MASK
17258 #define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 0x00000000
17259 #define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 2
17260 #define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK 0x00000004U
17262 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp
17263 t, test_scan_out[3]- (Test Scan Port) 3= Not Used*/
17264 #undef IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL
17265 #undef IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT
17266 #undef IOU_SLCR_MIO_PIN_3_L2_SEL_MASK
17267 #define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 0x00000000
17268 #define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 3
17269 #define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK 0x00000018U
17271 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can
17272 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
17273 ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
17274 - (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
17275 output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
17276 #undef IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL
17277 #undef IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT
17278 #undef IOU_SLCR_MIO_PIN_3_L3_SEL_MASK
17279 #define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 0x00000000
17280 #define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 5
17281 #define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK 0x000000E0U
17283 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data
17285 #undef IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL
17286 #undef IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT
17287 #undef IOU_SLCR_MIO_PIN_4_L0_SEL_MASK
17288 #define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 0x00000000
17289 #define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 1
17290 #define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK 0x00000002U
17292 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17293 #undef IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL
17294 #undef IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT
17295 #undef IOU_SLCR_MIO_PIN_4_L1_SEL_MASK
17296 #define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 0x00000000
17297 #define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 2
17298 #define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK 0x00000004U
17300 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp
17301 t, test_scan_out[4]- (Test Scan Port) 3= Not Used*/
17302 #undef IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL
17303 #undef IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT
17304 #undef IOU_SLCR_MIO_PIN_4_L2_SEL_MASK
17305 #define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 0x00000000
17306 #define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 3
17307 #define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK 0x00000018U
17309 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can
17310 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
17311 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
17312 - (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
17313 utput, tracedq[2]- (Trace Port Databus)*/
17314 #undef IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL
17315 #undef IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT
17316 #undef IOU_SLCR_MIO_PIN_4_L3_SEL_MASK
17317 #define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 0x00000000
17318 #define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 5
17319 #define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK 0x000000E0U
17321 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)*/
17322 #undef IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL
17323 #undef IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT
17324 #undef IOU_SLCR_MIO_PIN_5_L0_SEL_MASK
17325 #define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 0x00000000
17326 #define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 1
17327 #define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK 0x00000002U
17329 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17330 #undef IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL
17331 #undef IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT
17332 #undef IOU_SLCR_MIO_PIN_5_L1_SEL_MASK
17333 #define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 0x00000000
17334 #define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 2
17335 #define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK 0x00000004U
17337 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp
17338 t, test_scan_out[5]- (Test Scan Port) 3= Not Used*/
17339 #undef IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL
17340 #undef IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT
17341 #undef IOU_SLCR_MIO_PIN_5_L2_SEL_MASK
17342 #define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 0x00000000
17343 #define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 3
17344 #define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK 0x00000018U
17346 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can
17347 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
17348 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
17349 si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
17350 trace, Output, tracedq[3]- (Trace Port Databus)*/
17351 #undef IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL
17352 #undef IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT
17353 #undef IOU_SLCR_MIO_PIN_5_L3_SEL_MASK
17354 #define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 0x00000000
17355 #define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 5
17356 #define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK 0x000000E0U
17358 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)*/
17359 #undef IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL
17360 #undef IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT
17361 #undef IOU_SLCR_MIO_PIN_6_L0_SEL_MASK
17362 #define IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 0x00000000
17363 #define IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 1
17364 #define IOU_SLCR_MIO_PIN_6_L0_SEL_MASK 0x00000002U
17366 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17367 #undef IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL
17368 #undef IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT
17369 #undef IOU_SLCR_MIO_PIN_6_L1_SEL_MASK
17370 #define IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 0x00000000
17371 #define IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 2
17372 #define IOU_SLCR_MIO_PIN_6_L1_SEL_MASK 0x00000004U
17374 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp
17375 t, test_scan_out[6]- (Test Scan Port) 3= Not Used*/
17376 #undef IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL
17377 #undef IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT
17378 #undef IOU_SLCR_MIO_PIN_6_L2_SEL_MASK
17379 #define IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 0x00000000
17380 #define IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 3
17381 #define IOU_SLCR_MIO_PIN_6_L2_SEL_MASK 0x00000018U
17383 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can
17384 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
17385 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1
17386 sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
17387 Output, tracedq[4]- (Trace Port Databus)*/
17388 #undef IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL
17389 #undef IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT
17390 #undef IOU_SLCR_MIO_PIN_6_L3_SEL_MASK
17391 #define IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 0x00000000
17392 #define IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 5
17393 #define IOU_SLCR_MIO_PIN_6_L3_SEL_MASK 0x000000E0U
17395 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)*/
17396 #undef IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL
17397 #undef IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT
17398 #undef IOU_SLCR_MIO_PIN_7_L0_SEL_MASK
17399 #define IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 0x00000000
17400 #define IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 1
17401 #define IOU_SLCR_MIO_PIN_7_L0_SEL_MASK 0x00000002U
17403 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17404 #undef IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL
17405 #undef IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT
17406 #undef IOU_SLCR_MIO_PIN_7_L1_SEL_MASK
17407 #define IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 0x00000000
17408 #define IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 2
17409 #define IOU_SLCR_MIO_PIN_7_L1_SEL_MASK 0x00000004U
17411 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp
17412 t, test_scan_out[7]- (Test Scan Port) 3= Not Used*/
17413 #undef IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL
17414 #undef IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT
17415 #undef IOU_SLCR_MIO_PIN_7_L2_SEL_MASK
17416 #define IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 0x00000000
17417 #define IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 3
17418 #define IOU_SLCR_MIO_PIN_7_L2_SEL_MASK 0x00000018U
17420 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can
17421 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
17422 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
17423 tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output,
17424 racedq[5]- (Trace Port Databus)*/
17425 #undef IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL
17426 #undef IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT
17427 #undef IOU_SLCR_MIO_PIN_7_L3_SEL_MASK
17428 #define IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 0x00000000
17429 #define IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 5
17430 #define IOU_SLCR_MIO_PIN_7_L3_SEL_MASK 0x000000E0U
17432 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
17433 [0]- (QSPI Upper Databus)*/
17434 #undef IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL
17435 #undef IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT
17436 #undef IOU_SLCR_MIO_PIN_8_L0_SEL_MASK
17437 #define IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 0x00000000
17438 #define IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 1
17439 #define IOU_SLCR_MIO_PIN_8_L0_SEL_MASK 0x00000002U
17441 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
17442 #undef IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL
17443 #undef IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT
17444 #undef IOU_SLCR_MIO_PIN_8_L1_SEL_MASK
17445 #define IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 0x00000000
17446 #define IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 2
17447 #define IOU_SLCR_MIO_PIN_8_L1_SEL_MASK 0x00000004U
17449 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp
17450 t, test_scan_out[8]- (Test Scan Port) 3= Not Used*/
17451 #undef IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL
17452 #undef IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT
17453 #undef IOU_SLCR_MIO_PIN_8_L2_SEL_MASK
17454 #define IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 0x00000000
17455 #define IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 3
17456 #define IOU_SLCR_MIO_PIN_8_L2_SEL_MASK 0x00000018U
17458 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can
17459 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
17460 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc
17461 , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr
17463 #undef IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL
17464 #undef IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT
17465 #undef IOU_SLCR_MIO_PIN_8_L3_SEL_MASK
17466 #define IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 0x00000000
17467 #define IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 5
17468 #define IOU_SLCR_MIO_PIN_8_L3_SEL_MASK 0x000000E0U
17470 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
17471 [1]- (QSPI Upper Databus)*/
17472 #undef IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL
17473 #undef IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT
17474 #undef IOU_SLCR_MIO_PIN_9_L0_SEL_MASK
17475 #define IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 0x00000000
17476 #define IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 1
17477 #define IOU_SLCR_MIO_PIN_9_L0_SEL_MASK 0x00000002U
17479 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/
17480 #undef IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL
17481 #undef IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT
17482 #undef IOU_SLCR_MIO_PIN_9_L1_SEL_MASK
17483 #define IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 0x00000000
17484 #define IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 2
17485 #define IOU_SLCR_MIO_PIN_9_L1_SEL_MASK 0x00000004U
17487 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp
17488 t, test_scan_out[9]- (Test Scan Port) 3= Not Used*/
17489 #undef IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL
17490 #undef IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT
17491 #undef IOU_SLCR_MIO_PIN_9_L2_SEL_MASK
17492 #define IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 0x00000000
17493 #define IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 3
17494 #define IOU_SLCR_MIO_PIN_9_L2_SEL_MASK 0x00000018U
17496 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can
17497 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
17498 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
17499 utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U
17500 RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
17501 #undef IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL
17502 #undef IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT
17503 #undef IOU_SLCR_MIO_PIN_9_L3_SEL_MASK
17504 #define IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 0x00000000
17505 #define IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 5
17506 #define IOU_SLCR_MIO_PIN_9_L3_SEL_MASK 0x000000E0U
17508 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
17509 [2]- (QSPI Upper Databus)*/
17510 #undef IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL
17511 #undef IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT
17512 #undef IOU_SLCR_MIO_PIN_10_L0_SEL_MASK
17513 #define IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 0x00000000
17514 #define IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 1
17515 #define IOU_SLCR_MIO_PIN_10_L0_SEL_MASK 0x00000002U
17517 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/
17518 #undef IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL
17519 #undef IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT
17520 #undef IOU_SLCR_MIO_PIN_10_L1_SEL_MASK
17521 #define IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 0x00000000
17522 #define IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 2
17523 #define IOU_SLCR_MIO_PIN_10_L1_SEL_MASK 0x00000004U
17525 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out
17526 ut, test_scan_out[10]- (Test Scan Port) 3= Not Used*/
17527 #undef IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL
17528 #undef IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT
17529 #undef IOU_SLCR_MIO_PIN_10_L2_SEL_MASK
17530 #define IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 0x00000000
17531 #define IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 3
17532 #define IOU_SLCR_MIO_PIN_10_L2_SEL_MASK 0x00000018U
17534 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c
17535 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
17536 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
17537 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
17538 t, tracedq[8]- (Trace Port Databus)*/
17539 #undef IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL
17540 #undef IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT
17541 #undef IOU_SLCR_MIO_PIN_10_L3_SEL_MASK
17542 #define IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 0x00000000
17543 #define IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 5
17544 #define IOU_SLCR_MIO_PIN_10_L3_SEL_MASK 0x000000E0U
17546 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
17547 [3]- (QSPI Upper Databus)*/
17548 #undef IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL
17549 #undef IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT
17550 #undef IOU_SLCR_MIO_PIN_11_L0_SEL_MASK
17551 #define IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 0x00000000
17552 #define IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 1
17553 #define IOU_SLCR_MIO_PIN_11_L0_SEL_MASK 0x00000002U
17555 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/
17556 #undef IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL
17557 #undef IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT
17558 #undef IOU_SLCR_MIO_PIN_11_L1_SEL_MASK
17559 #define IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 0x00000000
17560 #define IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 2
17561 #define IOU_SLCR_MIO_PIN_11_L1_SEL_MASK 0x00000004U
17563 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out
17564 ut, test_scan_out[11]- (Test Scan Port) 3= Not Used*/
17565 #undef IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL
17566 #undef IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT
17567 #undef IOU_SLCR_MIO_PIN_11_L2_SEL_MASK
17568 #define IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 0x00000000
17569 #define IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 3
17570 #define IOU_SLCR_MIO_PIN_11_L2_SEL_MASK 0x00000018U
17572 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c
17573 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
17574 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
17575 i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
17576 tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
17577 #undef IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL
17578 #undef IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT
17579 #undef IOU_SLCR_MIO_PIN_11_L3_SEL_MASK
17580 #define IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 0x00000000
17581 #define IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 5
17582 #define IOU_SLCR_MIO_PIN_11_L3_SEL_MASK 0x000000E0U
17584 /*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)*/
17585 #undef IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL
17586 #undef IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT
17587 #undef IOU_SLCR_MIO_PIN_12_L0_SEL_MASK
17588 #define IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 0x00000000
17589 #define IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 1
17590 #define IOU_SLCR_MIO_PIN_12_L0_SEL_MASK 0x00000002U
17592 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
17594 #undef IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL
17595 #undef IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT
17596 #undef IOU_SLCR_MIO_PIN_12_L1_SEL_MASK
17597 #define IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 0x00000000
17598 #define IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 2
17599 #define IOU_SLCR_MIO_PIN_12_L1_SEL_MASK 0x00000004U
17601 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out
17602 ut, test_scan_out[12]- (Test Scan Port) 3= Not Used*/
17603 #undef IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL
17604 #undef IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT
17605 #undef IOU_SLCR_MIO_PIN_12_L2_SEL_MASK
17606 #define IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 0x00000000
17607 #define IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 3
17608 #define IOU_SLCR_MIO_PIN_12_L2_SEL_MASK 0x00000018U
17610 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c
17611 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
17612 al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl
17613 ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac
17614 dq[10]- (Trace Port Databus)*/
17615 #undef IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL
17616 #undef IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT
17617 #undef IOU_SLCR_MIO_PIN_12_L3_SEL_MASK
17618 #define IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 0x00000000
17619 #define IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 5
17620 #define IOU_SLCR_MIO_PIN_12_L3_SEL_MASK 0x000000E0U
17622 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17623 #undef IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL
17624 #undef IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT
17625 #undef IOU_SLCR_MIO_PIN_13_L0_SEL_MASK
17626 #define IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 0x00000000
17627 #define IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 1
17628 #define IOU_SLCR_MIO_PIN_13_L0_SEL_MASK 0x00000002U
17630 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)*/
17631 #undef IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL
17632 #undef IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT
17633 #undef IOU_SLCR_MIO_PIN_13_L1_SEL_MASK
17634 #define IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 0x00000000
17635 #define IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 2
17636 #define IOU_SLCR_MIO_PIN_13_L1_SEL_MASK 0x00000004U
17638 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
17639 bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port
17641 #undef IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL
17642 #undef IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT
17643 #undef IOU_SLCR_MIO_PIN_13_L2_SEL_MASK
17644 #define IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 0x00000000
17645 #define IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 3
17646 #define IOU_SLCR_MIO_PIN_13_L2_SEL_MASK 0x00000018U
17648 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c
17649 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
17650 l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave
17651 out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat
17653 #undef IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL
17654 #undef IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT
17655 #undef IOU_SLCR_MIO_PIN_13_L3_SEL_MASK
17656 #define IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 0x00000000
17657 #define IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 5
17658 #define IOU_SLCR_MIO_PIN_13_L3_SEL_MASK 0x000000E0U
17660 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17661 #undef IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL
17662 #undef IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT
17663 #undef IOU_SLCR_MIO_PIN_14_L0_SEL_MASK
17664 #define IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 0x00000000
17665 #define IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 1
17666 #define IOU_SLCR_MIO_PIN_14_L0_SEL_MASK 0x00000002U
17668 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)*/
17669 #undef IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL
17670 #undef IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT
17671 #undef IOU_SLCR_MIO_PIN_14_L1_SEL_MASK
17672 #define IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 0x00000000
17673 #define IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 2
17674 #define IOU_SLCR_MIO_PIN_14_L1_SEL_MASK 0x00000004U
17676 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
17677 bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port
17679 #undef IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL
17680 #undef IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT
17681 #undef IOU_SLCR_MIO_PIN_14_L2_SEL_MASK
17682 #define IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 0x00000000
17683 #define IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 3
17684 #define IOU_SLCR_MIO_PIN_14_L2_SEL_MASK 0x00000018U
17686 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c
17687 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
17688 l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_
17689 n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)*/
17690 #undef IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL
17691 #undef IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT
17692 #undef IOU_SLCR_MIO_PIN_14_L3_SEL_MASK
17693 #define IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 0x00000000
17694 #define IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 5
17695 #define IOU_SLCR_MIO_PIN_14_L3_SEL_MASK 0x000000E0U
17697 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17698 #undef IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL
17699 #undef IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT
17700 #undef IOU_SLCR_MIO_PIN_15_L0_SEL_MASK
17701 #define IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 0x00000000
17702 #define IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 1
17703 #define IOU_SLCR_MIO_PIN_15_L0_SEL_MASK 0x00000002U
17705 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)*/
17706 #undef IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL
17707 #undef IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT
17708 #undef IOU_SLCR_MIO_PIN_15_L1_SEL_MASK
17709 #define IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 0x00000000
17710 #define IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 2
17711 #define IOU_SLCR_MIO_PIN_15_L1_SEL_MASK 0x00000004U
17713 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
17714 bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port
17716 #undef IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL
17717 #undef IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT
17718 #undef IOU_SLCR_MIO_PIN_15_L2_SEL_MASK
17719 #define IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 0x00000000
17720 #define IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 3
17721 #define IOU_SLCR_MIO_PIN_15_L2_SEL_MASK 0x00000018U
17723 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c
17724 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
17725 al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out
17726 0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri
17727 l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
17728 #undef IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL
17729 #undef IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT
17730 #undef IOU_SLCR_MIO_PIN_15_L3_SEL_MASK
17731 #define IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 0x00000000
17732 #define IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 5
17733 #define IOU_SLCR_MIO_PIN_15_L3_SEL_MASK 0x000000E0U
17735 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17736 #undef IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL
17737 #undef IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT
17738 #undef IOU_SLCR_MIO_PIN_16_L0_SEL_MASK
17739 #define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 0x00000000
17740 #define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 1
17741 #define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK 0x00000002U
17743 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND
17745 #undef IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL
17746 #undef IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT
17747 #undef IOU_SLCR_MIO_PIN_16_L1_SEL_MASK
17748 #define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 0x00000000
17749 #define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 2
17750 #define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK 0x00000004U
17752 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
17753 bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port
17755 #undef IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL
17756 #undef IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT
17757 #undef IOU_SLCR_MIO_PIN_16_L2_SEL_MASK
17758 #define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 0x00000000
17759 #define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 3
17760 #define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK 0x00000018U
17762 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c
17763 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
17764 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
17765 so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
17766 Output, tracedq[14]- (Trace Port Databus)*/
17767 #undef IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL
17768 #undef IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT
17769 #undef IOU_SLCR_MIO_PIN_16_L3_SEL_MASK
17770 #define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 0x00000000
17771 #define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 5
17772 #define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK 0x000000E0U
17774 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17775 #undef IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL
17776 #undef IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT
17777 #undef IOU_SLCR_MIO_PIN_17_L0_SEL_MASK
17778 #define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 0x00000000
17779 #define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 1
17780 #define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK 0x00000002U
17782 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND
17784 #undef IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL
17785 #undef IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT
17786 #undef IOU_SLCR_MIO_PIN_17_L1_SEL_MASK
17787 #define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 0x00000000
17788 #define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 2
17789 #define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK 0x00000004U
17791 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
17792 bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port
17794 #undef IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL
17795 #undef IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT
17796 #undef IOU_SLCR_MIO_PIN_17_L2_SEL_MASK
17797 #define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 0x00000000
17798 #define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 3
17799 #define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK 0x00000018U
17801 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c
17802 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
17803 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
17804 0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
17805 7= trace, Output, tracedq[15]- (Trace Port Databus)*/
17806 #undef IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL
17807 #undef IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT
17808 #undef IOU_SLCR_MIO_PIN_17_L3_SEL_MASK
17809 #define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 0x00000000
17810 #define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 5
17811 #define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK 0x000000E0U
17813 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17814 #undef IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL
17815 #undef IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT
17816 #undef IOU_SLCR_MIO_PIN_18_L0_SEL_MASK
17817 #define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 0x00000000
17818 #define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 1
17819 #define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK 0x00000002U
17821 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND
17823 #undef IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL
17824 #undef IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT
17825 #undef IOU_SLCR_MIO_PIN_18_L1_SEL_MASK
17826 #define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 0x00000000
17827 #define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 2
17828 #define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK 0x00000004U
17830 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
17831 bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port
17832 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
17833 #undef IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL
17834 #undef IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT
17835 #undef IOU_SLCR_MIO_PIN_18_L2_SEL_MASK
17836 #define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 0x00000000
17837 #define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 3
17838 #define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK 0x00000018U
17840 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c
17841 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
17842 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
17843 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
17844 #undef IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL
17845 #undef IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT
17846 #undef IOU_SLCR_MIO_PIN_18_L3_SEL_MASK
17847 #define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 0x00000000
17848 #define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 5
17849 #define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK 0x000000E0U
17851 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17852 #undef IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL
17853 #undef IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT
17854 #undef IOU_SLCR_MIO_PIN_19_L0_SEL_MASK
17855 #define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 0x00000000
17856 #define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 1
17857 #define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK 0x00000002U
17859 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND
17861 #undef IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL
17862 #undef IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT
17863 #undef IOU_SLCR_MIO_PIN_19_L1_SEL_MASK
17864 #define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 0x00000000
17865 #define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 2
17866 #define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK 0x00000004U
17868 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
17869 bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port
17870 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
17871 #undef IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL
17872 #undef IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT
17873 #undef IOU_SLCR_MIO_PIN_19_L2_SEL_MASK
17874 #define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 0x00000000
17875 #define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 3
17876 #define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK 0x00000018U
17878 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c
17879 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
17880 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
17881 ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
17882 #undef IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL
17883 #undef IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT
17884 #undef IOU_SLCR_MIO_PIN_19_L3_SEL_MASK
17885 #define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 0x00000000
17886 #define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 5
17887 #define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK 0x000000E0U
17889 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17890 #undef IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL
17891 #undef IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT
17892 #undef IOU_SLCR_MIO_PIN_20_L0_SEL_MASK
17893 #define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 0x00000000
17894 #define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 1
17895 #define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK 0x00000002U
17897 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND
17899 #undef IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL
17900 #undef IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT
17901 #undef IOU_SLCR_MIO_PIN_20_L1_SEL_MASK
17902 #define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 0x00000000
17903 #define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 2
17904 #define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK 0x00000004U
17906 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
17907 bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port
17908 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
17909 #undef IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL
17910 #undef IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT
17911 #undef IOU_SLCR_MIO_PIN_20_L2_SEL_MASK
17912 #define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 0x00000000
17913 #define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 3
17914 #define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK 0x00000018U
17916 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c
17917 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
17918 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t
17919 c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
17920 #undef IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL
17921 #undef IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT
17922 #undef IOU_SLCR_MIO_PIN_20_L3_SEL_MASK
17923 #define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 0x00000000
17924 #define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 5
17925 #define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK 0x000000E0U
17927 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17928 #undef IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL
17929 #undef IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT
17930 #undef IOU_SLCR_MIO_PIN_21_L0_SEL_MASK
17931 #define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 0x00000000
17932 #define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 1
17933 #define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK 0x00000002U
17935 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND
17937 #undef IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL
17938 #undef IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT
17939 #undef IOU_SLCR_MIO_PIN_21_L1_SEL_MASK
17940 #define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 0x00000000
17941 #define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 2
17942 #define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK 0x00000004U
17944 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
17945 Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port)
17946 = csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
17947 #undef IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL
17948 #undef IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT
17949 #undef IOU_SLCR_MIO_PIN_21_L2_SEL_MASK
17950 #define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 0x00000000
17951 #define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 3
17952 #define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK 0x00000018U
17954 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c
17955 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
17956 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
17957 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd-
17958 UART receiver serial input) 7= Not Used*/
17959 #undef IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL
17960 #undef IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT
17961 #undef IOU_SLCR_MIO_PIN_21_L3_SEL_MASK
17962 #define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 0x00000000
17963 #define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 5
17964 #define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK 0x000000E0U
17966 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
17967 #undef IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL
17968 #undef IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT
17969 #undef IOU_SLCR_MIO_PIN_22_L0_SEL_MASK
17970 #define IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 0x00000000
17971 #define IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 1
17972 #define IOU_SLCR_MIO_PIN_22_L0_SEL_MASK 0x00000002U
17974 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)*/
17975 #undef IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL
17976 #undef IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT
17977 #undef IOU_SLCR_MIO_PIN_22_L1_SEL_MASK
17978 #define IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 0x00000000
17979 #define IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 2
17980 #define IOU_SLCR_MIO_PIN_22_L1_SEL_MASK 0x00000004U
17982 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]-
17983 (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
17984 #undef IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL
17985 #undef IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT
17986 #undef IOU_SLCR_MIO_PIN_22_L2_SEL_MASK
17987 #define IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 0x00000000
17988 #define IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 3
17989 #define IOU_SLCR_MIO_PIN_22_L2_SEL_MASK 0x00000018U
17991 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c
17992 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
17993 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
17994 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not
17996 #undef IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL
17997 #undef IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT
17998 #undef IOU_SLCR_MIO_PIN_22_L3_SEL_MASK
17999 #define IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 0x00000000
18000 #define IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 5
18001 #define IOU_SLCR_MIO_PIN_22_L3_SEL_MASK 0x000000E0U
18003 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
18004 #undef IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL
18005 #undef IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT
18006 #undef IOU_SLCR_MIO_PIN_23_L0_SEL_MASK
18007 #define IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 0x00000000
18008 #define IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 1
18009 #define IOU_SLCR_MIO_PIN_23_L0_SEL_MASK 0x00000002U
18011 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND
18013 #undef IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL
18014 #undef IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT
18015 #undef IOU_SLCR_MIO_PIN_23_L1_SEL_MASK
18016 #define IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 0x00000000
18017 #define IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 2
18018 #define IOU_SLCR_MIO_PIN_23_L1_SEL_MASK 0x00000004U
18020 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in
18021 23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper
18023 #undef IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL
18024 #undef IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT
18025 #undef IOU_SLCR_MIO_PIN_23_L2_SEL_MASK
18026 #define IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 0x00000000
18027 #define IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 3
18028 #define IOU_SLCR_MIO_PIN_23_L2_SEL_MASK 0x00000018U
18030 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c
18031 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
18032 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
18033 i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
18034 tput) 7= Not Used*/
18035 #undef IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL
18036 #undef IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT
18037 #undef IOU_SLCR_MIO_PIN_23_L3_SEL_MASK
18038 #define IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 0x00000000
18039 #define IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 5
18040 #define IOU_SLCR_MIO_PIN_23_L3_SEL_MASK 0x000000E0U
18042 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
18043 #undef IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL
18044 #undef IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT
18045 #undef IOU_SLCR_MIO_PIN_24_L0_SEL_MASK
18046 #define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 0x00000000
18047 #define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 1
18048 #define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK 0x00000002U
18050 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND
18052 #undef IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL
18053 #undef IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT
18054 #undef IOU_SLCR_MIO_PIN_24_L1_SEL_MASK
18055 #define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 0x00000000
18056 #define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 2
18057 #define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK 0x00000004U
18059 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test
18060 scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex
18062 #undef IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL
18063 #undef IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT
18064 #undef IOU_SLCR_MIO_PIN_24_L2_SEL_MASK
18065 #define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 0x00000000
18066 #define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 3
18067 #define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK 0x00000018U
18069 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c
18070 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
18071 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1,
18072 Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
18073 #undef IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL
18074 #undef IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT
18075 #undef IOU_SLCR_MIO_PIN_24_L3_SEL_MASK
18076 #define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 0x00000000
18077 #define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 5
18078 #define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK 0x000000E0U
18080 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
18081 #undef IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL
18082 #undef IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT
18083 #undef IOU_SLCR_MIO_PIN_25_L0_SEL_MASK
18084 #define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 0x00000000
18085 #define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 1
18086 #define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK 0x00000002U
18088 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)*/
18089 #undef IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL
18090 #undef IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT
18091 #undef IOU_SLCR_MIO_PIN_25_L1_SEL_MASK
18092 #define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 0x00000000
18093 #define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 2
18094 #define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK 0x00000004U
18096 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input,
18097 test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C
18099 #undef IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL
18100 #undef IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT
18101 #undef IOU_SLCR_MIO_PIN_25_L2_SEL_MASK
18102 #define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 0x00000000
18103 #define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 3
18104 #define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK 0x00000018U
18106 /*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c
18107 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
18108 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform
18109 lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
18110 #undef IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL
18111 #undef IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT
18112 #undef IOU_SLCR_MIO_PIN_25_L3_SEL_MASK
18113 #define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 0x00000000
18114 #define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 5
18115 #define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK 0x000000E0U
18117 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)*/
18118 #undef IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL
18119 #undef IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT
18120 #undef IOU_SLCR_MIO_PIN_26_L0_SEL_MASK
18121 #define IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 0x00000000
18122 #define IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 1
18123 #define IOU_SLCR_MIO_PIN_26_L0_SEL_MASK 0x00000002U
18125 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/
18126 #undef IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL
18127 #undef IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT
18128 #undef IOU_SLCR_MIO_PIN_26_L1_SEL_MASK
18129 #define IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 0x00000000
18130 #define IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 2
18131 #define IOU_SLCR_MIO_PIN_26_L1_SEL_MASK 0x00000004U
18133 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc
18134 n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
18135 #undef IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL
18136 #undef IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT
18137 #undef IOU_SLCR_MIO_PIN_26_L2_SEL_MASK
18138 #define IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 0x00000000
18139 #define IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 3
18140 #define IOU_SLCR_MIO_PIN_26_L2_SEL_MASK 0x00000018U
18142 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can
18143 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
18144 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock
18145 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]-
18146 Trace Port Databus)*/
18147 #undef IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL
18148 #undef IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT
18149 #undef IOU_SLCR_MIO_PIN_26_L3_SEL_MASK
18150 #define IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 0x00000000
18151 #define IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 5
18152 #define IOU_SLCR_MIO_PIN_26_L3_SEL_MASK 0x000000E0U
18154 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)*/
18155 #undef IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL
18156 #undef IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT
18157 #undef IOU_SLCR_MIO_PIN_27_L0_SEL_MASK
18158 #define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 0x00000000
18159 #define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 1
18160 #define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK 0x00000002U
18162 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/
18163 #undef IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL
18164 #undef IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT
18165 #undef IOU_SLCR_MIO_PIN_27_L1_SEL_MASK
18166 #define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 0x00000000
18167 #define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 2
18168 #define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK 0x00000004U
18170 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc
18171 n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
18172 t, dp_aux_data_out- (Dp Aux Data)*/
18173 #undef IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL
18174 #undef IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT
18175 #undef IOU_SLCR_MIO_PIN_27_L2_SEL_MASK
18176 #define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 0x00000000
18177 #define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 3
18178 #define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK 0x00000018U
18180 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can
18181 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
18182 ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
18183 ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port
18185 #undef IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL
18186 #undef IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT
18187 #undef IOU_SLCR_MIO_PIN_27_L3_SEL_MASK
18188 #define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 0x00000000
18189 #define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 5
18190 #define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK 0x000000E0U
18192 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)*/
18193 #undef IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL
18194 #undef IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT
18195 #undef IOU_SLCR_MIO_PIN_28_L0_SEL_MASK
18196 #define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 0x00000000
18197 #define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 1
18198 #define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK 0x00000002U
18200 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/
18201 #undef IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL
18202 #undef IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT
18203 #undef IOU_SLCR_MIO_PIN_28_L1_SEL_MASK
18204 #define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 0x00000000
18205 #define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 2
18206 #define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK 0x00000004U
18208 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc
18209 n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
18210 #undef IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL
18211 #undef IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT
18212 #undef IOU_SLCR_MIO_PIN_28_L2_SEL_MASK
18213 #define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 0x00000000
18214 #define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 3
18215 #define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK 0x00000018U
18217 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can
18218 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
18219 ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
18220 - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/
18221 #undef IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL
18222 #undef IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT
18223 #undef IOU_SLCR_MIO_PIN_28_L3_SEL_MASK
18224 #define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 0x00000000
18225 #define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 5
18226 #define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK 0x000000E0U
18228 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)*/
18229 #undef IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL
18230 #undef IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT
18231 #undef IOU_SLCR_MIO_PIN_29_L0_SEL_MASK
18232 #define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 0x00000000
18233 #define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 1
18234 #define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK 0x00000002U
18236 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
18237 #undef IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL
18238 #undef IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT
18239 #undef IOU_SLCR_MIO_PIN_29_L1_SEL_MASK
18240 #define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 0x00000000
18241 #define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 2
18242 #define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK 0x00000004U
18244 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc
18245 n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
18246 t, dp_aux_data_out- (Dp Aux Data)*/
18247 #undef IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL
18248 #undef IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT
18249 #undef IOU_SLCR_MIO_PIN_29_L2_SEL_MASK
18250 #define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 0x00000000
18251 #define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 3
18252 #define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK 0x00000018U
18254 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can
18255 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
18256 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]
18257 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
18258 ) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
18259 #undef IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL
18260 #undef IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT
18261 #undef IOU_SLCR_MIO_PIN_29_L3_SEL_MASK
18262 #define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 0x00000000
18263 #define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 5
18264 #define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK 0x000000E0U
18266 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)*/
18267 #undef IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL
18268 #undef IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT
18269 #undef IOU_SLCR_MIO_PIN_30_L0_SEL_MASK
18270 #define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 0x00000000
18271 #define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 1
18272 #define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK 0x00000002U
18274 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
18275 #undef IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL
18276 #undef IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT
18277 #undef IOU_SLCR_MIO_PIN_30_L1_SEL_MASK
18278 #define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 0x00000000
18279 #define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 2
18280 #define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK 0x00000004U
18282 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc
18283 n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
18284 #undef IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL
18285 #undef IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT
18286 #undef IOU_SLCR_MIO_PIN_30_L2_SEL_MASK
18287 #define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 0x00000000
18288 #define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 3
18289 #define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK 0x00000018U
18291 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can
18292 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
18293 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so
18294 (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output
18295 tracedq[8]- (Trace Port Databus)*/
18296 #undef IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL
18297 #undef IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT
18298 #undef IOU_SLCR_MIO_PIN_30_L3_SEL_MASK
18299 #define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 0x00000000
18300 #define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 5
18301 #define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK 0x000000E0U
18303 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)*/
18304 #undef IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL
18305 #undef IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT
18306 #undef IOU_SLCR_MIO_PIN_31_L0_SEL_MASK
18307 #define IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 0x00000000
18308 #define IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 1
18309 #define IOU_SLCR_MIO_PIN_31_L0_SEL_MASK 0x00000002U
18311 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
18312 #undef IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL
18313 #undef IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT
18314 #undef IOU_SLCR_MIO_PIN_31_L1_SEL_MASK
18315 #define IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 0x00000000
18316 #define IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 2
18317 #define IOU_SLCR_MIO_PIN_31_L1_SEL_MASK 0x00000004U
18319 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc
18320 n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
18321 #undef IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL
18322 #undef IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT
18323 #undef IOU_SLCR_MIO_PIN_31_L2_SEL_MASK
18324 #define IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 0x00000000
18325 #define IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 3
18326 #define IOU_SLCR_MIO_PIN_31_L2_SEL_MASK 0x00000018U
18328 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can
18329 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
18330 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi
18331 _si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out
18332 ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
18333 #undef IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL
18334 #undef IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT
18335 #undef IOU_SLCR_MIO_PIN_31_L3_SEL_MASK
18336 #define IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 0x00000000
18337 #define IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 5
18338 #define IOU_SLCR_MIO_PIN_31_L3_SEL_MASK 0x000000E0U
18340 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)*/
18341 #undef IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL
18342 #undef IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT
18343 #undef IOU_SLCR_MIO_PIN_32_L0_SEL_MASK
18344 #define IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 0x00000000
18345 #define IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 1
18346 #define IOU_SLCR_MIO_PIN_32_L0_SEL_MASK 0x00000002U
18348 /*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
18350 #undef IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL
18351 #undef IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT
18352 #undef IOU_SLCR_MIO_PIN_32_L1_SEL_MASK
18353 #define IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 0x00000000
18354 #define IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 2
18355 #define IOU_SLCR_MIO_PIN_32_L1_SEL_MASK 0x00000004U
18357 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S
18358 an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
18359 #undef IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL
18360 #undef IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT
18361 #undef IOU_SLCR_MIO_PIN_32_L2_SEL_MASK
18362 #define IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 0x00000000
18363 #define IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 3
18364 #define IOU_SLCR_MIO_PIN_32_L2_SEL_MASK 0x00000018U
18366 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can
18367 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
18368 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi
18369 _sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7=
18370 race, Output, tracedq[10]- (Trace Port Databus)*/
18371 #undef IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL
18372 #undef IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT
18373 #undef IOU_SLCR_MIO_PIN_32_L3_SEL_MASK
18374 #define IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 0x00000000
18375 #define IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 5
18376 #define IOU_SLCR_MIO_PIN_32_L3_SEL_MASK 0x000000E0U
18378 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)*/
18379 #undef IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL
18380 #undef IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT
18381 #undef IOU_SLCR_MIO_PIN_33_L0_SEL_MASK
18382 #define IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 0x00000000
18383 #define IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 1
18384 #define IOU_SLCR_MIO_PIN_33_L0_SEL_MASK 0x00000002U
18386 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
18387 #undef IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL
18388 #undef IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT
18389 #undef IOU_SLCR_MIO_PIN_33_L1_SEL_MASK
18390 #define IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 0x00000000
18391 #define IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 2
18392 #define IOU_SLCR_MIO_PIN_33_L1_SEL_MASK 0x00000004U
18394 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S
18395 an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
18396 #undef IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL
18397 #undef IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT
18398 #undef IOU_SLCR_MIO_PIN_33_L2_SEL_MASK
18399 #define IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 0x00000000
18400 #define IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 3
18401 #define IOU_SLCR_MIO_PIN_33_L2_SEL_MASK 0x00000018U
18403 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can
18404 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
18405 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t
18406 c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced
18407 [11]- (Trace Port Databus)*/
18408 #undef IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL
18409 #undef IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT
18410 #undef IOU_SLCR_MIO_PIN_33_L3_SEL_MASK
18411 #define IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 0x00000000
18412 #define IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 5
18413 #define IOU_SLCR_MIO_PIN_33_L3_SEL_MASK 0x000000E0U
18415 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)*/
18416 #undef IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL
18417 #undef IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT
18418 #undef IOU_SLCR_MIO_PIN_34_L0_SEL_MASK
18419 #define IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 0x00000000
18420 #define IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 1
18421 #define IOU_SLCR_MIO_PIN_34_L0_SEL_MASK 0x00000002U
18423 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
18424 #undef IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL
18425 #undef IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT
18426 #undef IOU_SLCR_MIO_PIN_34_L1_SEL_MASK
18427 #define IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 0x00000000
18428 #define IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 2
18429 #define IOU_SLCR_MIO_PIN_34_L1_SEL_MASK 0x00000004U
18431 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S
18432 an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
18433 ut, dp_aux_data_out- (Dp Aux Data)*/
18434 #undef IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL
18435 #undef IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT
18436 #undef IOU_SLCR_MIO_PIN_34_L2_SEL_MASK
18437 #define IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 0x00000000
18438 #define IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 3
18439 #define IOU_SLCR_MIO_PIN_34_L2_SEL_MASK 0x00000018U
18441 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can
18442 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
18443 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2
18444 Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P
18446 #undef IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL
18447 #undef IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT
18448 #undef IOU_SLCR_MIO_PIN_34_L3_SEL_MASK
18449 #define IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 0x00000000
18450 #define IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 5
18451 #define IOU_SLCR_MIO_PIN_34_L3_SEL_MASK 0x000000E0U
18453 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)*/
18454 #undef IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL
18455 #undef IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT
18456 #undef IOU_SLCR_MIO_PIN_35_L0_SEL_MASK
18457 #define IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 0x00000000
18458 #define IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 1
18459 #define IOU_SLCR_MIO_PIN_35_L0_SEL_MASK 0x00000002U
18461 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
18462 #undef IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL
18463 #undef IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT
18464 #undef IOU_SLCR_MIO_PIN_35_L1_SEL_MASK
18465 #define IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 0x00000000
18466 #define IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 2
18467 #define IOU_SLCR_MIO_PIN_35_L1_SEL_MASK 0x00000004U
18469 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S
18470 an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
18471 #undef IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL
18472 #undef IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT
18473 #undef IOU_SLCR_MIO_PIN_35_L2_SEL_MASK
18474 #define IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 0x00000000
18475 #define IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 3
18476 #define IOU_SLCR_MIO_PIN_35_L2_SEL_MASK 0x00000018U
18478 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can
18479 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
18480 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
18481 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd-
18482 UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
18483 #undef IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL
18484 #undef IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT
18485 #undef IOU_SLCR_MIO_PIN_35_L3_SEL_MASK
18486 #define IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 0x00000000
18487 #define IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 5
18488 #define IOU_SLCR_MIO_PIN_35_L3_SEL_MASK 0x000000E0U
18490 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)*/
18491 #undef IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL
18492 #undef IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT
18493 #undef IOU_SLCR_MIO_PIN_36_L0_SEL_MASK
18494 #define IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 0x00000000
18495 #define IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 1
18496 #define IOU_SLCR_MIO_PIN_36_L0_SEL_MASK 0x00000002U
18498 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
18499 #undef IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL
18500 #undef IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT
18501 #undef IOU_SLCR_MIO_PIN_36_L1_SEL_MASK
18502 #define IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 0x00000000
18503 #define IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 2
18504 #define IOU_SLCR_MIO_PIN_36_L1_SEL_MASK 0x00000004U
18506 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S
18507 an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
18508 ut, dp_aux_data_out- (Dp Aux Data)*/
18509 #undef IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL
18510 #undef IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT
18511 #undef IOU_SLCR_MIO_PIN_36_L2_SEL_MASK
18512 #define IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 0x00000000
18513 #define IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 3
18514 #define IOU_SLCR_MIO_PIN_36_L2_SEL_MASK 0x00000018U
18516 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c
18517 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
18518 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
18519 so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
18520 Output, tracedq[14]- (Trace Port Databus)*/
18521 #undef IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL
18522 #undef IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT
18523 #undef IOU_SLCR_MIO_PIN_36_L3_SEL_MASK
18524 #define IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 0x00000000
18525 #define IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 5
18526 #define IOU_SLCR_MIO_PIN_36_L3_SEL_MASK 0x000000E0U
18528 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )*/
18529 #undef IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL
18530 #undef IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT
18531 #undef IOU_SLCR_MIO_PIN_37_L0_SEL_MASK
18532 #define IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 0x00000000
18533 #define IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 1
18534 #define IOU_SLCR_MIO_PIN_37_L0_SEL_MASK 0x00000002U
18536 /*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
18537 #undef IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL
18538 #undef IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT
18539 #undef IOU_SLCR_MIO_PIN_37_L1_SEL_MASK
18540 #define IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 0x00000000
18541 #define IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 2
18542 #define IOU_SLCR_MIO_PIN_37_L1_SEL_MASK 0x00000004U
18544 /*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S
18545 an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
18546 #undef IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL
18547 #undef IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT
18548 #undef IOU_SLCR_MIO_PIN_37_L2_SEL_MASK
18549 #define IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 0x00000000
18550 #define IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 3
18551 #define IOU_SLCR_MIO_PIN_37_L2_SEL_MASK 0x00000018U
18553 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c
18554 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
18555 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
18556 1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
18557 7= trace, Output, tracedq[15]- (Trace Port Databus)*/
18558 #undef IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL
18559 #undef IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT
18560 #undef IOU_SLCR_MIO_PIN_37_L3_SEL_MASK
18561 #define IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 0x00000000
18562 #define IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 5
18563 #define IOU_SLCR_MIO_PIN_37_L3_SEL_MASK 0x000000E0U
18565 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)*/
18566 #undef IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL
18567 #undef IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT
18568 #undef IOU_SLCR_MIO_PIN_38_L0_SEL_MASK
18569 #define IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 0x00000000
18570 #define IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 1
18571 #define IOU_SLCR_MIO_PIN_38_L0_SEL_MASK 0x00000002U
18573 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18574 #undef IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL
18575 #undef IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT
18576 #undef IOU_SLCR_MIO_PIN_38_L1_SEL_MASK
18577 #define IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 0x00000000
18578 #define IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 2
18579 #define IOU_SLCR_MIO_PIN_38_L1_SEL_MASK 0x00000004U
18581 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/
18582 #undef IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL
18583 #undef IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT
18584 #undef IOU_SLCR_MIO_PIN_38_L2_SEL_MASK
18585 #define IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 0x00000000
18586 #define IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 3
18587 #define IOU_SLCR_MIO_PIN_38_L2_SEL_MASK 0x00000018U
18589 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c
18590 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
18591 l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo
18592 k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
18593 (Trace Port Clock)*/
18594 #undef IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL
18595 #undef IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT
18596 #undef IOU_SLCR_MIO_PIN_38_L3_SEL_MASK
18597 #define IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 0x00000000
18598 #define IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 5
18599 #define IOU_SLCR_MIO_PIN_38_L3_SEL_MASK 0x000000E0U
18601 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)*/
18602 #undef IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL
18603 #undef IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT
18604 #undef IOU_SLCR_MIO_PIN_39_L0_SEL_MASK
18605 #define IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 0x00000000
18606 #define IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 1
18607 #define IOU_SLCR_MIO_PIN_39_L0_SEL_MASK 0x00000002U
18609 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18610 #undef IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL
18611 #undef IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT
18612 #undef IOU_SLCR_MIO_PIN_39_L1_SEL_MASK
18613 #define IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 0x00000000
18614 #define IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 2
18615 #define IOU_SLCR_MIO_PIN_39_L1_SEL_MASK 0x00000004U
18617 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i
18618 [4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used*/
18619 #undef IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL
18620 #undef IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT
18621 #undef IOU_SLCR_MIO_PIN_39_L2_SEL_MASK
18622 #define IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 0x00000000
18623 #define IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 3
18624 #define IOU_SLCR_MIO_PIN_39_L2_SEL_MASK 0x00000018U
18626 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c
18627 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
18628 al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav
18629 _out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
18631 #undef IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL
18632 #undef IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT
18633 #undef IOU_SLCR_MIO_PIN_39_L3_SEL_MASK
18634 #define IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 0x00000000
18635 #define IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 5
18636 #define IOU_SLCR_MIO_PIN_39_L3_SEL_MASK 0x000000E0U
18638 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)*/
18639 #undef IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL
18640 #undef IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT
18641 #undef IOU_SLCR_MIO_PIN_40_L0_SEL_MASK
18642 #define IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 0x00000000
18643 #define IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 1
18644 #define IOU_SLCR_MIO_PIN_40_L0_SEL_MASK 0x00000002U
18646 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18647 #undef IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL
18648 #undef IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT
18649 #undef IOU_SLCR_MIO_PIN_40_L1_SEL_MASK
18650 #define IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 0x00000000
18651 #define IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 2
18652 #define IOU_SLCR_MIO_PIN_40_L1_SEL_MASK 0x00000004U
18654 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
18655 Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used*/
18656 #undef IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL
18657 #undef IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT
18658 #undef IOU_SLCR_MIO_PIN_40_L2_SEL_MASK
18659 #define IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 0x00000000
18660 #define IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 3
18661 #define IOU_SLCR_MIO_PIN_40_L2_SEL_MASK 0x00000018U
18663 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c
18664 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
18665 al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk
18666 in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
18667 #undef IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL
18668 #undef IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT
18669 #undef IOU_SLCR_MIO_PIN_40_L3_SEL_MASK
18670 #define IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 0x00000000
18671 #define IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 5
18672 #define IOU_SLCR_MIO_PIN_40_L3_SEL_MASK 0x000000E0U
18674 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)*/
18675 #undef IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL
18676 #undef IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT
18677 #undef IOU_SLCR_MIO_PIN_41_L0_SEL_MASK
18678 #define IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 0x00000000
18679 #define IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 1
18680 #define IOU_SLCR_MIO_PIN_41_L0_SEL_MASK 0x00000002U
18682 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18683 #undef IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL
18684 #undef IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT
18685 #undef IOU_SLCR_MIO_PIN_41_L1_SEL_MASK
18686 #define IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 0x00000000
18687 #define IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 2
18688 #define IOU_SLCR_MIO_PIN_41_L1_SEL_MASK 0x00000004U
18690 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
18691 bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used*/
18692 #undef IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL
18693 #undef IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT
18694 #undef IOU_SLCR_MIO_PIN_41_L2_SEL_MASK
18695 #define IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 0x00000000
18696 #define IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 3
18697 #define IOU_SLCR_MIO_PIN_41_L2_SEL_MASK 0x00000018U
18699 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c
18700 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
18701 l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[
18702 ]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
18703 ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
18704 #undef IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL
18705 #undef IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT
18706 #undef IOU_SLCR_MIO_PIN_41_L3_SEL_MASK
18707 #define IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 0x00000000
18708 #define IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 5
18709 #define IOU_SLCR_MIO_PIN_41_L3_SEL_MASK 0x000000E0U
18711 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)*/
18712 #undef IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL
18713 #undef IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT
18714 #undef IOU_SLCR_MIO_PIN_42_L0_SEL_MASK
18715 #define IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 0x00000000
18716 #define IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 1
18717 #define IOU_SLCR_MIO_PIN_42_L0_SEL_MASK 0x00000002U
18719 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18720 #undef IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL
18721 #undef IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT
18722 #undef IOU_SLCR_MIO_PIN_42_L1_SEL_MASK
18723 #define IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 0x00000000
18724 #define IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 2
18725 #define IOU_SLCR_MIO_PIN_42_L1_SEL_MASK 0x00000004U
18727 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
18728 bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used*/
18729 #undef IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL
18730 #undef IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT
18731 #undef IOU_SLCR_MIO_PIN_42_L2_SEL_MASK
18732 #define IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 0x00000000
18733 #define IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 3
18734 #define IOU_SLCR_MIO_PIN_42_L2_SEL_MASK 0x00000018U
18736 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c
18737 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
18738 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_
18739 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
18740 t, tracedq[2]- (Trace Port Databus)*/
18741 #undef IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL
18742 #undef IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT
18743 #undef IOU_SLCR_MIO_PIN_42_L3_SEL_MASK
18744 #define IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 0x00000000
18745 #define IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 5
18746 #define IOU_SLCR_MIO_PIN_42_L3_SEL_MASK 0x000000E0U
18748 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)*/
18749 #undef IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL
18750 #undef IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT
18751 #undef IOU_SLCR_MIO_PIN_43_L0_SEL_MASK
18752 #define IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 0x00000000
18753 #define IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 1
18754 #define IOU_SLCR_MIO_PIN_43_L0_SEL_MASK 0x00000002U
18756 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18757 #undef IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL
18758 #undef IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT
18759 #undef IOU_SLCR_MIO_PIN_43_L1_SEL_MASK
18760 #define IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 0x00000000
18761 #define IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 2
18762 #define IOU_SLCR_MIO_PIN_43_L1_SEL_MASK 0x00000004U
18764 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
18765 bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/
18766 #undef IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL
18767 #undef IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT
18768 #undef IOU_SLCR_MIO_PIN_43_L2_SEL_MASK
18769 #define IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 0x00000000
18770 #define IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 3
18771 #define IOU_SLCR_MIO_PIN_43_L2_SEL_MASK 0x00000018U
18773 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c
18774 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
18775 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s
18776 i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
18777 tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)*/
18778 #undef IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL
18779 #undef IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT
18780 #undef IOU_SLCR_MIO_PIN_43_L3_SEL_MASK
18781 #define IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 0x00000000
18782 #define IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 5
18783 #define IOU_SLCR_MIO_PIN_43_L3_SEL_MASK 0x000000E0U
18785 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)*/
18786 #undef IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL
18787 #undef IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT
18788 #undef IOU_SLCR_MIO_PIN_44_L0_SEL_MASK
18789 #define IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 0x00000000
18790 #define IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 1
18791 #define IOU_SLCR_MIO_PIN_44_L0_SEL_MASK 0x00000002U
18793 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18794 #undef IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL
18795 #undef IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT
18796 #undef IOU_SLCR_MIO_PIN_44_L1_SEL_MASK
18797 #define IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 0x00000000
18798 #define IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 2
18799 #define IOU_SLCR_MIO_PIN_44_L1_SEL_MASK 0x00000004U
18801 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
18802 bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/
18803 #undef IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL
18804 #undef IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT
18805 #undef IOU_SLCR_MIO_PIN_44_L2_SEL_MASK
18806 #define IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 0x00000000
18807 #define IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 3
18808 #define IOU_SLCR_MIO_PIN_44_L2_SEL_MASK 0x00000018U
18810 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c
18811 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
18812 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s
18813 i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
18815 #undef IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL
18816 #undef IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT
18817 #undef IOU_SLCR_MIO_PIN_44_L3_SEL_MASK
18818 #define IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 0x00000000
18819 #define IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 5
18820 #define IOU_SLCR_MIO_PIN_44_L3_SEL_MASK 0x000000E0U
18822 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)*/
18823 #undef IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL
18824 #undef IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT
18825 #undef IOU_SLCR_MIO_PIN_45_L0_SEL_MASK
18826 #define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 0x00000000
18827 #define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 1
18828 #define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK 0x00000002U
18830 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18831 #undef IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL
18832 #undef IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT
18833 #undef IOU_SLCR_MIO_PIN_45_L1_SEL_MASK
18834 #define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 0x00000000
18835 #define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 2
18836 #define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK 0x00000004U
18838 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
18839 bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/
18840 #undef IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL
18841 #undef IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT
18842 #undef IOU_SLCR_MIO_PIN_45_L2_SEL_MASK
18843 #define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 0x00000000
18844 #define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 3
18845 #define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK 0x00000018U
18847 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c
18848 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
18849 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
18850 ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
18851 #undef IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL
18852 #undef IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT
18853 #undef IOU_SLCR_MIO_PIN_45_L3_SEL_MASK
18854 #define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 0x00000000
18855 #define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 5
18856 #define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK 0x000000E0U
18858 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)*/
18859 #undef IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL
18860 #undef IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT
18861 #undef IOU_SLCR_MIO_PIN_46_L0_SEL_MASK
18862 #define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 0x00000000
18863 #define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 1
18864 #define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK 0x00000002U
18866 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18867 #undef IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL
18868 #undef IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT
18869 #undef IOU_SLCR_MIO_PIN_46_L1_SEL_MASK
18870 #define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 0x00000000
18871 #define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 2
18872 #define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK 0x00000004U
18874 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
18875 bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/
18876 #undef IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL
18877 #undef IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT
18878 #undef IOU_SLCR_MIO_PIN_46_L2_SEL_MASK
18879 #define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 0x00000000
18880 #define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 3
18881 #define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK 0x00000018U
18883 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c
18884 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
18885 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt
18886 0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
18887 #undef IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL
18888 #undef IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT
18889 #undef IOU_SLCR_MIO_PIN_46_L3_SEL_MASK
18890 #define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 0x00000000
18891 #define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 5
18892 #define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK 0x000000E0U
18894 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)*/
18895 #undef IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL
18896 #undef IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT
18897 #undef IOU_SLCR_MIO_PIN_47_L0_SEL_MASK
18898 #define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 0x00000000
18899 #define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 1
18900 #define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK 0x00000002U
18902 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18903 #undef IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL
18904 #undef IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT
18905 #undef IOU_SLCR_MIO_PIN_47_L1_SEL_MASK
18906 #define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 0x00000000
18907 #define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 2
18908 #define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK 0x00000004U
18910 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
18911 bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/
18912 #undef IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL
18913 #undef IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT
18914 #undef IOU_SLCR_MIO_PIN_47_L2_SEL_MASK
18915 #define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 0x00000000
18916 #define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 3
18917 #define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK 0x00000018U
18919 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c
18920 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
18921 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi
18922 , Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
18923 (UART transmitter serial output) 7= Not Used*/
18924 #undef IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL
18925 #undef IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT
18926 #undef IOU_SLCR_MIO_PIN_47_L3_SEL_MASK
18927 #define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 0x00000000
18928 #define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 5
18929 #define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK 0x000000E0U
18931 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)*/
18932 #undef IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL
18933 #undef IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT
18934 #undef IOU_SLCR_MIO_PIN_48_L0_SEL_MASK
18935 #define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 0x00000000
18936 #define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 1
18937 #define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK 0x00000002U
18939 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18940 #undef IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL
18941 #undef IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT
18942 #undef IOU_SLCR_MIO_PIN_48_L1_SEL_MASK
18943 #define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 0x00000000
18944 #define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 2
18945 #define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK 0x00000004U
18947 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
18948 bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/
18949 #undef IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL
18950 #undef IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT
18951 #undef IOU_SLCR_MIO_PIN_48_L2_SEL_MASK
18952 #define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 0x00000000
18953 #define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 3
18954 #define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK 0x00000018U
18956 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c
18957 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
18958 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
18959 so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U
18961 #undef IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL
18962 #undef IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT
18963 #undef IOU_SLCR_MIO_PIN_48_L3_SEL_MASK
18964 #define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 0x00000000
18965 #define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 5
18966 #define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK 0x000000E0U
18968 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )*/
18969 #undef IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL
18970 #undef IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT
18971 #undef IOU_SLCR_MIO_PIN_49_L0_SEL_MASK
18972 #define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 0x00000000
18973 #define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 1
18974 #define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK 0x00000002U
18976 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
18977 #undef IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL
18978 #undef IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT
18979 #undef IOU_SLCR_MIO_PIN_49_L1_SEL_MASK
18980 #define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 0x00000000
18981 #define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 2
18982 #define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK 0x00000004U
18984 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8
18985 bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/
18986 #undef IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL
18987 #undef IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT
18988 #undef IOU_SLCR_MIO_PIN_49_L2_SEL_MASK
18989 #define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 0x00000000
18990 #define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 3
18991 #define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK 0x00000018U
18993 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c
18994 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
18995 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
18996 1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
18998 #undef IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL
18999 #undef IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT
19000 #undef IOU_SLCR_MIO_PIN_49_L3_SEL_MASK
19001 #define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 0x00000000
19002 #define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 5
19003 #define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK 0x000000E0U
19005 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/
19006 #undef IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL
19007 #undef IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT
19008 #undef IOU_SLCR_MIO_PIN_50_L0_SEL_MASK
19009 #define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 0x00000000
19010 #define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 1
19011 #define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK 0x00000002U
19013 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
19014 #undef IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL
19015 #undef IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT
19016 #undef IOU_SLCR_MIO_PIN_50_L1_SEL_MASK
19017 #define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 0x00000000
19018 #define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 2
19019 #define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK 0x00000004U
19021 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c
19022 d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/
19023 #undef IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL
19024 #undef IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT
19025 #undef IOU_SLCR_MIO_PIN_50_L2_SEL_MASK
19026 #define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 0x00000000
19027 #define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 3
19028 #define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK 0x00000018U
19030 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c
19031 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
19032 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2
19033 clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
19034 #undef IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL
19035 #undef IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT
19036 #undef IOU_SLCR_MIO_PIN_50_L3_SEL_MASK
19037 #define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 0x00000000
19038 #define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 5
19039 #define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK 0x000000E0U
19041 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/
19042 #undef IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL
19043 #undef IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT
19044 #undef IOU_SLCR_MIO_PIN_51_L0_SEL_MASK
19045 #define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 0x00000000
19046 #define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 1
19047 #define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK 0x00000002U
19049 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
19050 #undef IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL
19051 #undef IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT
19052 #undef IOU_SLCR_MIO_PIN_51_L1_SEL_MASK
19053 #define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 0x00000000
19054 #define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 2
19055 #define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK 0x00000004U
19057 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used*/
19058 #undef IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL
19059 #undef IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT
19060 #undef IOU_SLCR_MIO_PIN_51_L2_SEL_MASK
19061 #define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 0x00000000
19062 #define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 3
19063 #define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK 0x00000018U
19065 /*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c
19066 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
19067 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp
19068 t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
19069 serial output) 7= Not Used*/
19070 #undef IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL
19071 #undef IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT
19072 #undef IOU_SLCR_MIO_PIN_51_L3_SEL_MASK
19073 #define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 0x00000000
19074 #define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 5
19075 #define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 0x000000E0U
19077 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)*/
19078 #undef IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL
19079 #undef IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT
19080 #undef IOU_SLCR_MIO_PIN_52_L0_SEL_MASK
19081 #define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 0x00000000
19082 #define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 1
19083 #define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 0x00000002U
19085 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)*/
19086 #undef IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL
19087 #undef IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT
19088 #undef IOU_SLCR_MIO_PIN_52_L1_SEL_MASK
19089 #define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 0x00000000
19090 #define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 2
19091 #define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 0x00000004U
19093 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19094 #undef IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL
19095 #undef IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT
19096 #undef IOU_SLCR_MIO_PIN_52_L2_SEL_MASK
19097 #define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 0x00000000
19098 #define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 3
19099 #define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 0x00000018U
19101 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can
19102 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
19103 ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
19104 ) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
19105 lk- (Trace Port Clock)*/
19106 #undef IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL
19107 #undef IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT
19108 #undef IOU_SLCR_MIO_PIN_52_L3_SEL_MASK
19109 #define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 0x00000000
19110 #define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 5
19111 #define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 0x000000E0U
19113 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)*/
19114 #undef IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL
19115 #undef IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT
19116 #undef IOU_SLCR_MIO_PIN_53_L0_SEL_MASK
19117 #define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 0x00000000
19118 #define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 1
19119 #define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 0x00000002U
19121 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)*/
19122 #undef IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL
19123 #undef IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT
19124 #undef IOU_SLCR_MIO_PIN_53_L1_SEL_MASK
19125 #define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 0x00000000
19126 #define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 2
19127 #define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 0x00000004U
19129 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19130 #undef IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL
19131 #undef IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT
19132 #undef IOU_SLCR_MIO_PIN_53_L2_SEL_MASK
19133 #define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 0x00000000
19134 #define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 3
19135 #define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 0x00000018U
19137 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can
19138 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
19139 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o
19140 t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
19142 #undef IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL
19143 #undef IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT
19144 #undef IOU_SLCR_MIO_PIN_53_L3_SEL_MASK
19145 #define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 0x00000000
19146 #define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 5
19147 #define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 0x000000E0U
19149 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)*/
19150 #undef IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL
19151 #undef IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT
19152 #undef IOU_SLCR_MIO_PIN_54_L0_SEL_MASK
19153 #define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 0x00000000
19154 #define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 1
19155 #define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 0x00000002U
19157 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
19158 ata[2]- (ULPI data bus)*/
19159 #undef IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL
19160 #undef IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT
19161 #undef IOU_SLCR_MIO_PIN_54_L1_SEL_MASK
19162 #define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 0x00000000
19163 #define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 2
19164 #define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 0x00000004U
19166 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19167 #undef IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL
19168 #undef IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT
19169 #undef IOU_SLCR_MIO_PIN_54_L2_SEL_MASK
19170 #define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 0x00000000
19171 #define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 3
19172 #define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 0x00000018U
19174 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can
19175 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
19176 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in
19177 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
19178 #undef IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL
19179 #undef IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT
19180 #undef IOU_SLCR_MIO_PIN_54_L3_SEL_MASK
19181 #define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 0x00000000
19182 #define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 5
19183 #define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 0x000000E0U
19185 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)*/
19186 #undef IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL
19187 #undef IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT
19188 #undef IOU_SLCR_MIO_PIN_55_L0_SEL_MASK
19189 #define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 0x00000000
19190 #define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 1
19191 #define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 0x00000002U
19193 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)*/
19194 #undef IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL
19195 #undef IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT
19196 #undef IOU_SLCR_MIO_PIN_55_L1_SEL_MASK
19197 #define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 0x00000000
19198 #define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 2
19199 #define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 0x00000004U
19201 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19202 #undef IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL
19203 #undef IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT
19204 #undef IOU_SLCR_MIO_PIN_55_L2_SEL_MASK
19205 #define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 0x00000000
19206 #define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 3
19207 #define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 0x00000018U
19209 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can
19210 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
19211 ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
19212 - (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
19213 output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
19214 #undef IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL
19215 #undef IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT
19216 #undef IOU_SLCR_MIO_PIN_55_L3_SEL_MASK
19217 #define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 0x00000000
19218 #define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 5
19219 #define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 0x000000E0U
19221 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)*/
19222 #undef IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL
19223 #undef IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT
19224 #undef IOU_SLCR_MIO_PIN_56_L0_SEL_MASK
19225 #define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 0x00000000
19226 #define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 1
19227 #define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 0x00000002U
19229 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
19230 ata[0]- (ULPI data bus)*/
19231 #undef IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL
19232 #undef IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT
19233 #undef IOU_SLCR_MIO_PIN_56_L1_SEL_MASK
19234 #define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 0x00000000
19235 #define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 2
19236 #define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK 0x00000004U
19238 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19239 #undef IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL
19240 #undef IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT
19241 #undef IOU_SLCR_MIO_PIN_56_L2_SEL_MASK
19242 #define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 0x00000000
19243 #define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 3
19244 #define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK 0x00000018U
19246 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can
19247 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
19248 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
19249 - (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
19250 utput, tracedq[2]- (Trace Port Databus)*/
19251 #undef IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL
19252 #undef IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT
19253 #undef IOU_SLCR_MIO_PIN_56_L3_SEL_MASK
19254 #define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 0x00000000
19255 #define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 5
19256 #define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK 0x000000E0U
19258 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)*/
19259 #undef IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL
19260 #undef IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT
19261 #undef IOU_SLCR_MIO_PIN_57_L0_SEL_MASK
19262 #define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 0x00000000
19263 #define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 1
19264 #define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK 0x00000002U
19266 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
19267 ata[1]- (ULPI data bus)*/
19268 #undef IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL
19269 #undef IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT
19270 #undef IOU_SLCR_MIO_PIN_57_L1_SEL_MASK
19271 #define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 0x00000000
19272 #define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 2
19273 #define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK 0x00000004U
19275 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19276 #undef IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL
19277 #undef IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT
19278 #undef IOU_SLCR_MIO_PIN_57_L2_SEL_MASK
19279 #define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 0x00000000
19280 #define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 3
19281 #define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK 0x00000018U
19283 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can
19284 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
19285 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
19286 si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
19287 trace, Output, tracedq[3]- (Trace Port Databus)*/
19288 #undef IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL
19289 #undef IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT
19290 #undef IOU_SLCR_MIO_PIN_57_L3_SEL_MASK
19291 #define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 0x00000000
19292 #define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 5
19293 #define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 0x000000E0U
19295 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)*/
19296 #undef IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL
19297 #undef IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT
19298 #undef IOU_SLCR_MIO_PIN_58_L0_SEL_MASK
19299 #define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 0x00000000
19300 #define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 1
19301 #define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 0x00000002U
19303 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)*/
19304 #undef IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL
19305 #undef IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT
19306 #undef IOU_SLCR_MIO_PIN_58_L1_SEL_MASK
19307 #define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 0x00000000
19308 #define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 2
19309 #define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 0x00000004U
19311 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19312 #undef IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL
19313 #undef IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT
19314 #undef IOU_SLCR_MIO_PIN_58_L2_SEL_MASK
19315 #define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 0x00000000
19316 #define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 3
19317 #define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 0x00000018U
19319 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can
19320 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
19321 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock
19322 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]-
19323 Trace Port Databus)*/
19324 #undef IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL
19325 #undef IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT
19326 #undef IOU_SLCR_MIO_PIN_58_L3_SEL_MASK
19327 #define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 0x00000000
19328 #define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 5
19329 #define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 0x000000E0U
19331 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)*/
19332 #undef IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL
19333 #undef IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT
19334 #undef IOU_SLCR_MIO_PIN_59_L0_SEL_MASK
19335 #define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 0x00000000
19336 #define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 1
19337 #define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 0x00000002U
19339 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
19340 ata[3]- (ULPI data bus)*/
19341 #undef IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL
19342 #undef IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT
19343 #undef IOU_SLCR_MIO_PIN_59_L1_SEL_MASK
19344 #define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 0x00000000
19345 #define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 2
19346 #define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 0x00000004U
19348 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19349 #undef IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL
19350 #undef IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT
19351 #undef IOU_SLCR_MIO_PIN_59_L2_SEL_MASK
19352 #define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 0x00000000
19353 #define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 3
19354 #define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 0x00000018U
19356 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can
19357 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
19358 ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
19359 ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port
19361 #undef IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL
19362 #undef IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT
19363 #undef IOU_SLCR_MIO_PIN_59_L3_SEL_MASK
19364 #define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 0x00000000
19365 #define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 5
19366 #define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 0x000000E0U
19368 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)*/
19369 #undef IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL
19370 #undef IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT
19371 #undef IOU_SLCR_MIO_PIN_60_L0_SEL_MASK
19372 #define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 0x00000000
19373 #define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 1
19374 #define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 0x00000002U
19376 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
19377 ata[4]- (ULPI data bus)*/
19378 #undef IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL
19379 #undef IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT
19380 #undef IOU_SLCR_MIO_PIN_60_L1_SEL_MASK
19381 #define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 0x00000000
19382 #define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 2
19383 #define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 0x00000004U
19385 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19386 #undef IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL
19387 #undef IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT
19388 #undef IOU_SLCR_MIO_PIN_60_L2_SEL_MASK
19389 #define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 0x00000000
19390 #define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 3
19391 #define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 0x00000018U
19393 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can
19394 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
19395 ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
19396 - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/
19397 #undef IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL
19398 #undef IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT
19399 #undef IOU_SLCR_MIO_PIN_60_L3_SEL_MASK
19400 #define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 0x00000000
19401 #define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 5
19402 #define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 0x000000E0U
19404 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)*/
19405 #undef IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL
19406 #undef IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT
19407 #undef IOU_SLCR_MIO_PIN_61_L0_SEL_MASK
19408 #define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 0x00000000
19409 #define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 1
19410 #define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 0x00000002U
19412 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
19413 ata[5]- (ULPI data bus)*/
19414 #undef IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL
19415 #undef IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT
19416 #undef IOU_SLCR_MIO_PIN_61_L1_SEL_MASK
19417 #define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 0x00000000
19418 #define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 2
19419 #define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK 0x00000004U
19421 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19422 #undef IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL
19423 #undef IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT
19424 #undef IOU_SLCR_MIO_PIN_61_L2_SEL_MASK
19425 #define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 0x00000000
19426 #define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 3
19427 #define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK 0x00000018U
19429 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can
19430 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
19431 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]
19432 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
19433 ) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
19434 #undef IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL
19435 #undef IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT
19436 #undef IOU_SLCR_MIO_PIN_61_L3_SEL_MASK
19437 #define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 0x00000000
19438 #define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 5
19439 #define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK 0x000000E0U
19441 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)*/
19442 #undef IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL
19443 #undef IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT
19444 #undef IOU_SLCR_MIO_PIN_62_L0_SEL_MASK
19445 #define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 0x00000000
19446 #define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 1
19447 #define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK 0x00000002U
19449 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
19450 ata[6]- (ULPI data bus)*/
19451 #undef IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL
19452 #undef IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT
19453 #undef IOU_SLCR_MIO_PIN_62_L1_SEL_MASK
19454 #define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 0x00000000
19455 #define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 2
19456 #define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK 0x00000004U
19458 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19459 #undef IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL
19460 #undef IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT
19461 #undef IOU_SLCR_MIO_PIN_62_L2_SEL_MASK
19462 #define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 0x00000000
19463 #define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 3
19464 #define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK 0x00000018U
19466 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c
19467 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
19468 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
19469 o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
19470 t, tracedq[8]- (Trace Port Databus)*/
19471 #undef IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL
19472 #undef IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT
19473 #undef IOU_SLCR_MIO_PIN_62_L3_SEL_MASK
19474 #define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 0x00000000
19475 #define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 5
19476 #define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK 0x000000E0U
19478 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )*/
19479 #undef IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL
19480 #undef IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT
19481 #undef IOU_SLCR_MIO_PIN_63_L0_SEL_MASK
19482 #define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 0x00000000
19483 #define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 1
19484 #define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK 0x00000002U
19486 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
19487 ata[7]- (ULPI data bus)*/
19488 #undef IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL
19489 #undef IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT
19490 #undef IOU_SLCR_MIO_PIN_63_L1_SEL_MASK
19491 #define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 0x00000000
19492 #define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 2
19493 #define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK 0x00000004U
19495 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
19496 #undef IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL
19497 #undef IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT
19498 #undef IOU_SLCR_MIO_PIN_63_L2_SEL_MASK
19499 #define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 0x00000000
19500 #define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 3
19501 #define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK 0x00000018U
19503 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c
19504 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
19505 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
19506 i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
19507 tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
19508 #undef IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL
19509 #undef IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT
19510 #undef IOU_SLCR_MIO_PIN_63_L3_SEL_MASK
19511 #define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 0x00000000
19512 #define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 5
19513 #define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK 0x000000E0U
19515 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)*/
19516 #undef IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL
19517 #undef IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT
19518 #undef IOU_SLCR_MIO_PIN_64_L0_SEL_MASK
19519 #define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 0x00000000
19520 #define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 1
19521 #define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK 0x00000002U
19523 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)*/
19524 #undef IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL
19525 #undef IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT
19526 #undef IOU_SLCR_MIO_PIN_64_L1_SEL_MASK
19527 #define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 0x00000000
19528 #define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 2
19529 #define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK 0x00000004U
19531 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/
19532 #undef IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL
19533 #undef IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT
19534 #undef IOU_SLCR_MIO_PIN_64_L2_SEL_MASK
19535 #define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 0x00000000
19536 #define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 3
19537 #define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK 0x00000018U
19539 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c
19540 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
19541 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s
19542 i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
19543 trace, Output, tracedq[10]- (Trace Port Databus)*/
19544 #undef IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL
19545 #undef IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT
19546 #undef IOU_SLCR_MIO_PIN_64_L3_SEL_MASK
19547 #define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 0x00000000
19548 #define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 5
19549 #define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK 0x000000E0U
19551 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)*/
19552 #undef IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL
19553 #undef IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT
19554 #undef IOU_SLCR_MIO_PIN_65_L0_SEL_MASK
19555 #define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 0x00000000
19556 #define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 1
19557 #define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK 0x00000002U
19559 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)*/
19560 #undef IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL
19561 #undef IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT
19562 #undef IOU_SLCR_MIO_PIN_65_L1_SEL_MASK
19563 #define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 0x00000000
19564 #define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 2
19565 #define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK 0x00000004U
19567 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used*/
19568 #undef IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL
19569 #undef IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT
19570 #undef IOU_SLCR_MIO_PIN_65_L2_SEL_MASK
19571 #define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 0x00000000
19572 #define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 3
19573 #define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK 0x00000018U
19575 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c
19576 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
19577 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5=
19578 ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac
19579 dq[11]- (Trace Port Databus)*/
19580 #undef IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL
19581 #undef IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT
19582 #undef IOU_SLCR_MIO_PIN_65_L3_SEL_MASK
19583 #define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 0x00000000
19584 #define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 5
19585 #define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK 0x000000E0U
19587 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)*/
19588 #undef IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL
19589 #undef IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT
19590 #undef IOU_SLCR_MIO_PIN_66_L0_SEL_MASK
19591 #define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 0x00000000
19592 #define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 1
19593 #define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK 0x00000002U
19595 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
19596 ata[2]- (ULPI data bus)*/
19597 #undef IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL
19598 #undef IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT
19599 #undef IOU_SLCR_MIO_PIN_66_L1_SEL_MASK
19600 #define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 0x00000000
19601 #define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 2
19602 #define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK 0x00000004U
19604 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
19605 Indicator) 2= Not Used 3= Not Used*/
19606 #undef IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL
19607 #undef IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT
19608 #undef IOU_SLCR_MIO_PIN_66_L2_SEL_MASK
19609 #define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 0x00000000
19610 #define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 3
19611 #define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK 0x00000018U
19613 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c
19614 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
19615 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt
19616 2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
19618 #undef IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL
19619 #undef IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT
19620 #undef IOU_SLCR_MIO_PIN_66_L3_SEL_MASK
19621 #define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 0x00000000
19622 #define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 5
19623 #define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK 0x000000E0U
19625 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)*/
19626 #undef IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL
19627 #undef IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT
19628 #undef IOU_SLCR_MIO_PIN_67_L0_SEL_MASK
19629 #define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 0x00000000
19630 #define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 1
19631 #define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK 0x00000002U
19633 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)*/
19634 #undef IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL
19635 #undef IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT
19636 #undef IOU_SLCR_MIO_PIN_67_L1_SEL_MASK
19637 #define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 0x00000000
19638 #define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 2
19639 #define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK 0x00000004U
19641 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
19642 bit Data bus) 2= Not Used 3= Not Used*/
19643 #undef IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL
19644 #undef IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT
19645 #undef IOU_SLCR_MIO_PIN_67_L2_SEL_MASK
19646 #define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 0x00000000
19647 #define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 3
19648 #define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK 0x00000018U
19650 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c
19651 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
19652 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi
19653 , Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
19654 (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
19655 #undef IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL
19656 #undef IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT
19657 #undef IOU_SLCR_MIO_PIN_67_L3_SEL_MASK
19658 #define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 0x00000000
19659 #define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 5
19660 #define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK 0x000000E0U
19662 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)*/
19663 #undef IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL
19664 #undef IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT
19665 #undef IOU_SLCR_MIO_PIN_68_L0_SEL_MASK
19666 #define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 0x00000000
19667 #define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 1
19668 #define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK 0x00000002U
19670 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
19671 ata[0]- (ULPI data bus)*/
19672 #undef IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL
19673 #undef IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT
19674 #undef IOU_SLCR_MIO_PIN_68_L1_SEL_MASK
19675 #define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 0x00000000
19676 #define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 2
19677 #define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK 0x00000004U
19679 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
19680 bit Data bus) 2= Not Used 3= Not Used*/
19681 #undef IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL
19682 #undef IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT
19683 #undef IOU_SLCR_MIO_PIN_68_L2_SEL_MASK
19684 #define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 0x00000000
19685 #define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 3
19686 #define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK 0x00000018U
19688 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c
19689 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
19690 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
19691 so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
19692 Output, tracedq[14]- (Trace Port Databus)*/
19693 #undef IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL
19694 #undef IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT
19695 #undef IOU_SLCR_MIO_PIN_68_L3_SEL_MASK
19696 #define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 0x00000000
19697 #define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 5
19698 #define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK 0x000000E0U
19700 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)*/
19701 #undef IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL
19702 #undef IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT
19703 #undef IOU_SLCR_MIO_PIN_69_L0_SEL_MASK
19704 #define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 0x00000000
19705 #define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 1
19706 #define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK 0x00000002U
19708 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
19709 ata[1]- (ULPI data bus)*/
19710 #undef IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL
19711 #undef IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT
19712 #undef IOU_SLCR_MIO_PIN_69_L1_SEL_MASK
19713 #define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 0x00000000
19714 #define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 2
19715 #define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK 0x00000004U
19717 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
19718 bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/
19719 #undef IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL
19720 #undef IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT
19721 #undef IOU_SLCR_MIO_PIN_69_L2_SEL_MASK
19722 #define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 0x00000000
19723 #define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 3
19724 #define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK 0x00000018U
19726 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c
19727 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
19728 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
19729 0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
19730 7= trace, Output, tracedq[15]- (Trace Port Databus)*/
19731 #undef IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL
19732 #undef IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT
19733 #undef IOU_SLCR_MIO_PIN_69_L3_SEL_MASK
19734 #define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 0x00000000
19735 #define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 5
19736 #define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK 0x000000E0U
19738 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)*/
19739 #undef IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL
19740 #undef IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT
19741 #undef IOU_SLCR_MIO_PIN_70_L0_SEL_MASK
19742 #define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 0x00000000
19743 #define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 1
19744 #define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK 0x00000002U
19746 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)*/
19747 #undef IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL
19748 #undef IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT
19749 #undef IOU_SLCR_MIO_PIN_70_L1_SEL_MASK
19750 #define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 0x00000000
19751 #define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 2
19752 #define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK 0x00000004U
19754 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
19755 bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/
19756 #undef IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL
19757 #undef IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT
19758 #undef IOU_SLCR_MIO_PIN_70_L2_SEL_MASK
19759 #define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 0x00000000
19760 #define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 3
19761 #define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK 0x00000018U
19763 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c
19764 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
19765 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
19766 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not
19768 #undef IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL
19769 #undef IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT
19770 #undef IOU_SLCR_MIO_PIN_70_L3_SEL_MASK
19771 #define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 0x00000000
19772 #define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 5
19773 #define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK 0x000000E0U
19775 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)*/
19776 #undef IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL
19777 #undef IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT
19778 #undef IOU_SLCR_MIO_PIN_71_L0_SEL_MASK
19779 #define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 0x00000000
19780 #define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 1
19781 #define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK 0x00000002U
19783 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
19784 ata[3]- (ULPI data bus)*/
19785 #undef IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL
19786 #undef IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT
19787 #undef IOU_SLCR_MIO_PIN_71_L1_SEL_MASK
19788 #define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 0x00000000
19789 #define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 2
19790 #define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK 0x00000004U
19792 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
19793 bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/
19794 #undef IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL
19795 #undef IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT
19796 #undef IOU_SLCR_MIO_PIN_71_L2_SEL_MASK
19797 #define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 0x00000000
19798 #define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 3
19799 #define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK 0x00000018U
19801 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c
19802 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
19803 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
19804 ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
19805 #undef IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL
19806 #undef IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT
19807 #undef IOU_SLCR_MIO_PIN_71_L3_SEL_MASK
19808 #define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 0x00000000
19809 #define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 5
19810 #define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK 0x000000E0U
19812 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)*/
19813 #undef IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL
19814 #undef IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT
19815 #undef IOU_SLCR_MIO_PIN_72_L0_SEL_MASK
19816 #define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 0x00000000
19817 #define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 1
19818 #define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK 0x00000002U
19820 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
19821 ata[4]- (ULPI data bus)*/
19822 #undef IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL
19823 #undef IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT
19824 #undef IOU_SLCR_MIO_PIN_72_L1_SEL_MASK
19825 #define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 0x00000000
19826 #define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 2
19827 #define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK 0x00000004U
19829 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
19830 bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/
19831 #undef IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL
19832 #undef IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT
19833 #undef IOU_SLCR_MIO_PIN_72_L2_SEL_MASK
19834 #define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 0x00000000
19835 #define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 3
19836 #define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK 0x00000018U
19838 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c
19839 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
19840 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N
19841 t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
19842 #undef IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL
19843 #undef IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT
19844 #undef IOU_SLCR_MIO_PIN_72_L3_SEL_MASK
19845 #define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 0x00000000
19846 #define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 5
19847 #define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK 0x000000E0U
19849 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)*/
19850 #undef IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL
19851 #undef IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT
19852 #undef IOU_SLCR_MIO_PIN_73_L0_SEL_MASK
19853 #define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 0x00000000
19854 #define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 1
19855 #define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK 0x00000002U
19857 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
19858 ata[5]- (ULPI data bus)*/
19859 #undef IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL
19860 #undef IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT
19861 #undef IOU_SLCR_MIO_PIN_73_L1_SEL_MASK
19862 #define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 0x00000000
19863 #define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 2
19864 #define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK 0x00000004U
19866 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
19867 bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/
19868 #undef IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL
19869 #undef IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT
19870 #undef IOU_SLCR_MIO_PIN_73_L2_SEL_MASK
19871 #define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 0x00000000
19872 #define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 3
19873 #define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK 0x00000018U
19875 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c
19876 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
19877 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
19878 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
19879 #undef IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL
19880 #undef IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT
19881 #undef IOU_SLCR_MIO_PIN_73_L3_SEL_MASK
19882 #define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 0x00000000
19883 #define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 5
19884 #define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK 0x000000E0U
19886 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)*/
19887 #undef IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL
19888 #undef IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT
19889 #undef IOU_SLCR_MIO_PIN_74_L0_SEL_MASK
19890 #define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 0x00000000
19891 #define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 1
19892 #define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK 0x00000002U
19894 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
19895 ata[6]- (ULPI data bus)*/
19896 #undef IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL
19897 #undef IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT
19898 #undef IOU_SLCR_MIO_PIN_74_L1_SEL_MASK
19899 #define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 0x00000000
19900 #define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 2
19901 #define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK 0x00000004U
19903 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
19904 bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/
19905 #undef IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL
19906 #undef IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT
19907 #undef IOU_SLCR_MIO_PIN_74_L2_SEL_MASK
19908 #define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 0x00000000
19909 #define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 3
19910 #define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK 0x00000018U
19912 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c
19913 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
19914 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
19915 o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
19916 #undef IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL
19917 #undef IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT
19918 #undef IOU_SLCR_MIO_PIN_74_L3_SEL_MASK
19919 #define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 0x00000000
19920 #define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 5
19921 #define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK 0x000000E0U
19923 /*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )*/
19924 #undef IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL
19925 #undef IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT
19926 #undef IOU_SLCR_MIO_PIN_75_L0_SEL_MASK
19927 #define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 0x00000000
19928 #define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 1
19929 #define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK 0x00000002U
19931 /*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
19932 ata[7]- (ULPI data bus)*/
19933 #undef IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL
19934 #undef IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT
19935 #undef IOU_SLCR_MIO_PIN_75_L1_SEL_MASK
19936 #define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 0x00000000
19937 #define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 2
19938 #define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK 0x00000004U
19940 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma
19941 d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/
19942 #undef IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL
19943 #undef IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT
19944 #undef IOU_SLCR_MIO_PIN_75_L2_SEL_MASK
19945 #define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 0x00000000
19946 #define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 3
19947 #define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK 0x00000018U
19949 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c
19950 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
19951 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
19952 i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
19953 #undef IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL
19954 #undef IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT
19955 #undef IOU_SLCR_MIO_PIN_75_L3_SEL_MASK
19956 #define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 0x00000000
19957 #define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 5
19958 #define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK 0x000000E0U
19960 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
19961 #undef IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL
19962 #undef IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT
19963 #undef IOU_SLCR_MIO_PIN_76_L0_SEL_MASK
19964 #define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 0x00000000
19965 #define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 1
19966 #define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK 0x00000002U
19968 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
19969 #undef IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL
19970 #undef IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT
19971 #undef IOU_SLCR_MIO_PIN_76_L1_SEL_MASK
19972 #define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 0x00000000
19973 #define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 2
19974 #define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK 0x00000004U
19976 /*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio
19977 _clk_out- (SDSDIO clock) 3= Not Used*/
19978 #undef IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL
19979 #undef IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT
19980 #undef IOU_SLCR_MIO_PIN_76_L2_SEL_MASK
19981 #define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 0x00000000
19982 #define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 3
19983 #define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK 0x00000018U
19985 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c
19986 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
19987 al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock
19988 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used*/
19989 #undef IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL
19990 #undef IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT
19991 #undef IOU_SLCR_MIO_PIN_76_L3_SEL_MASK
19992 #define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 0x00000000
19993 #define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 5
19994 #define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK 0x000000E0U
19996 /*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
19997 #undef IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL
19998 #undef IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT
19999 #undef IOU_SLCR_MIO_PIN_77_L0_SEL_MASK
20000 #define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 0x00000000
20001 #define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 1
20002 #define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK 0x00000002U
20004 /*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
20005 #undef IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL
20006 #undef IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT
20007 #undef IOU_SLCR_MIO_PIN_77_L1_SEL_MASK
20008 #define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 0x00000000
20009 #define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 2
20010 #define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK 0x00000004U
20012 /*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/
20013 #undef IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL
20014 #undef IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT
20015 #undef IOU_SLCR_MIO_PIN_77_L2_SEL_MASK
20016 #define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 0x00000000
20017 #define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 3
20018 #define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK 0x00000018U
20020 /*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c
20021 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
20022 l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD
20023 O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o
20024 t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used*/
20025 #undef IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL
20026 #undef IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT
20027 #undef IOU_SLCR_MIO_PIN_77_L3_SEL_MASK
20028 #define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 0x00000000
20029 #define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 5
20030 #define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK 0x000000E0U
20032 /*Master Tri-state Enable for pin 0, active high*/
20033 #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL
20034 #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT
20035 #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK
20036 #define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 0xFFFFFFFF
20037 #define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 0
20038 #define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 0x00000001U
20040 /*Master Tri-state Enable for pin 1, active high*/
20041 #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL
20042 #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT
20043 #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK
20044 #define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 0xFFFFFFFF
20045 #define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 1
20046 #define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 0x00000002U
20048 /*Master Tri-state Enable for pin 2, active high*/
20049 #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL
20050 #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT
20051 #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK
20052 #define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 0xFFFFFFFF
20053 #define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 2
20054 #define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 0x00000004U
20056 /*Master Tri-state Enable for pin 3, active high*/
20057 #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL
20058 #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT
20059 #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK
20060 #define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 0xFFFFFFFF
20061 #define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 3
20062 #define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 0x00000008U
20064 /*Master Tri-state Enable for pin 4, active high*/
20065 #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL
20066 #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT
20067 #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK
20068 #define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 0xFFFFFFFF
20069 #define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 4
20070 #define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 0x00000010U
20072 /*Master Tri-state Enable for pin 5, active high*/
20073 #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL
20074 #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT
20075 #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK
20076 #define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 0xFFFFFFFF
20077 #define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 5
20078 #define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 0x00000020U
20080 /*Master Tri-state Enable for pin 6, active high*/
20081 #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL
20082 #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT
20083 #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK
20084 #define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 0xFFFFFFFF
20085 #define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 6
20086 #define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 0x00000040U
20088 /*Master Tri-state Enable for pin 7, active high*/
20089 #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL
20090 #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT
20091 #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK
20092 #define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 0xFFFFFFFF
20093 #define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 7
20094 #define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 0x00000080U
20096 /*Master Tri-state Enable for pin 8, active high*/
20097 #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL
20098 #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT
20099 #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK
20100 #define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 0xFFFFFFFF
20101 #define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 8
20102 #define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 0x00000100U
20104 /*Master Tri-state Enable for pin 9, active high*/
20105 #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL
20106 #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT
20107 #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK
20108 #define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 0xFFFFFFFF
20109 #define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 9
20110 #define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 0x00000200U
20112 /*Master Tri-state Enable for pin 10, active high*/
20113 #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL
20114 #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT
20115 #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK
20116 #define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 0xFFFFFFFF
20117 #define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 10
20118 #define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 0x00000400U
20120 /*Master Tri-state Enable for pin 11, active high*/
20121 #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL
20122 #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT
20123 #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK
20124 #define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 0xFFFFFFFF
20125 #define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 11
20126 #define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 0x00000800U
20128 /*Master Tri-state Enable for pin 12, active high*/
20129 #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL
20130 #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT
20131 #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK
20132 #define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 0xFFFFFFFF
20133 #define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 12
20134 #define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 0x00001000U
20136 /*Master Tri-state Enable for pin 13, active high*/
20137 #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL
20138 #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT
20139 #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK
20140 #define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 0xFFFFFFFF
20141 #define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 13
20142 #define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 0x00002000U
20144 /*Master Tri-state Enable for pin 14, active high*/
20145 #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL
20146 #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT
20147 #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK
20148 #define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 0xFFFFFFFF
20149 #define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 14
20150 #define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 0x00004000U
20152 /*Master Tri-state Enable for pin 15, active high*/
20153 #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL
20154 #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT
20155 #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK
20156 #define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 0xFFFFFFFF
20157 #define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 15
20158 #define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 0x00008000U
20160 /*Master Tri-state Enable for pin 16, active high*/
20161 #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL
20162 #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT
20163 #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK
20164 #define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 0xFFFFFFFF
20165 #define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 16
20166 #define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 0x00010000U
20168 /*Master Tri-state Enable for pin 17, active high*/
20169 #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL
20170 #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT
20171 #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK
20172 #define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 0xFFFFFFFF
20173 #define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 17
20174 #define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 0x00020000U
20176 /*Master Tri-state Enable for pin 18, active high*/
20177 #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL
20178 #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT
20179 #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK
20180 #define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 0xFFFFFFFF
20181 #define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 18
20182 #define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 0x00040000U
20184 /*Master Tri-state Enable for pin 19, active high*/
20185 #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL
20186 #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT
20187 #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK
20188 #define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 0xFFFFFFFF
20189 #define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 19
20190 #define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 0x00080000U
20192 /*Master Tri-state Enable for pin 20, active high*/
20193 #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL
20194 #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT
20195 #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK
20196 #define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 0xFFFFFFFF
20197 #define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 20
20198 #define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 0x00100000U
20200 /*Master Tri-state Enable for pin 21, active high*/
20201 #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL
20202 #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT
20203 #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK
20204 #define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 0xFFFFFFFF
20205 #define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 21
20206 #define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 0x00200000U
20208 /*Master Tri-state Enable for pin 22, active high*/
20209 #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL
20210 #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT
20211 #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK
20212 #define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 0xFFFFFFFF
20213 #define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 22
20214 #define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 0x00400000U
20216 /*Master Tri-state Enable for pin 23, active high*/
20217 #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL
20218 #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT
20219 #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK
20220 #define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 0xFFFFFFFF
20221 #define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 23
20222 #define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 0x00800000U
20224 /*Master Tri-state Enable for pin 24, active high*/
20225 #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL
20226 #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT
20227 #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK
20228 #define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 0xFFFFFFFF
20229 #define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 24
20230 #define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 0x01000000U
20232 /*Master Tri-state Enable for pin 25, active high*/
20233 #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL
20234 #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT
20235 #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK
20236 #define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 0xFFFFFFFF
20237 #define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 25
20238 #define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 0x02000000U
20240 /*Master Tri-state Enable for pin 26, active high*/
20241 #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL
20242 #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT
20243 #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK
20244 #define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 0xFFFFFFFF
20245 #define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 26
20246 #define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 0x04000000U
20248 /*Master Tri-state Enable for pin 27, active high*/
20249 #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL
20250 #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT
20251 #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK
20252 #define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 0xFFFFFFFF
20253 #define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 27
20254 #define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 0x08000000U
20256 /*Master Tri-state Enable for pin 28, active high*/
20257 #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL
20258 #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT
20259 #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK
20260 #define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 0xFFFFFFFF
20261 #define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 28
20262 #define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 0x10000000U
20264 /*Master Tri-state Enable for pin 29, active high*/
20265 #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL
20266 #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT
20267 #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK
20268 #define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 0xFFFFFFFF
20269 #define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 29
20270 #define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 0x20000000U
20272 /*Master Tri-state Enable for pin 30, active high*/
20273 #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL
20274 #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT
20275 #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK
20276 #define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 0xFFFFFFFF
20277 #define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 30
20278 #define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 0x40000000U
20280 /*Master Tri-state Enable for pin 31, active high*/
20281 #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL
20282 #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT
20283 #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK
20284 #define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 0xFFFFFFFF
20285 #define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 31
20286 #define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 0x80000000U
20288 /*Master Tri-state Enable for pin 32, active high*/
20289 #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL
20290 #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT
20291 #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK
20292 #define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 0xFFFFFFFF
20293 #define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 0
20294 #define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 0x00000001U
20296 /*Master Tri-state Enable for pin 33, active high*/
20297 #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL
20298 #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT
20299 #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK
20300 #define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 0xFFFFFFFF
20301 #define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 1
20302 #define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 0x00000002U
20304 /*Master Tri-state Enable for pin 34, active high*/
20305 #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL
20306 #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT
20307 #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK
20308 #define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 0xFFFFFFFF
20309 #define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 2
20310 #define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 0x00000004U
20312 /*Master Tri-state Enable for pin 35, active high*/
20313 #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL
20314 #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT
20315 #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK
20316 #define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 0xFFFFFFFF
20317 #define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 3
20318 #define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 0x00000008U
20320 /*Master Tri-state Enable for pin 36, active high*/
20321 #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL
20322 #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT
20323 #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK
20324 #define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 0xFFFFFFFF
20325 #define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 4
20326 #define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 0x00000010U
20328 /*Master Tri-state Enable for pin 37, active high*/
20329 #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL
20330 #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT
20331 #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK
20332 #define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 0xFFFFFFFF
20333 #define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 5
20334 #define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 0x00000020U
20336 /*Master Tri-state Enable for pin 38, active high*/
20337 #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL
20338 #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT
20339 #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK
20340 #define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 0xFFFFFFFF
20341 #define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 6
20342 #define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 0x00000040U
20344 /*Master Tri-state Enable for pin 39, active high*/
20345 #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL
20346 #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT
20347 #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK
20348 #define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 0xFFFFFFFF
20349 #define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 7
20350 #define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 0x00000080U
20352 /*Master Tri-state Enable for pin 40, active high*/
20353 #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL
20354 #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT
20355 #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK
20356 #define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 0xFFFFFFFF
20357 #define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 8
20358 #define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 0x00000100U
20360 /*Master Tri-state Enable for pin 41, active high*/
20361 #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL
20362 #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT
20363 #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK
20364 #define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 0xFFFFFFFF
20365 #define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 9
20366 #define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 0x00000200U
20368 /*Master Tri-state Enable for pin 42, active high*/
20369 #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL
20370 #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT
20371 #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK
20372 #define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 0xFFFFFFFF
20373 #define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 10
20374 #define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 0x00000400U
20376 /*Master Tri-state Enable for pin 43, active high*/
20377 #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL
20378 #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT
20379 #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK
20380 #define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 0xFFFFFFFF
20381 #define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 11
20382 #define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 0x00000800U
20384 /*Master Tri-state Enable for pin 44, active high*/
20385 #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL
20386 #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT
20387 #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK
20388 #define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 0xFFFFFFFF
20389 #define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 12
20390 #define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 0x00001000U
20392 /*Master Tri-state Enable for pin 45, active high*/
20393 #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL
20394 #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT
20395 #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK
20396 #define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 0xFFFFFFFF
20397 #define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 13
20398 #define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 0x00002000U
20400 /*Master Tri-state Enable for pin 46, active high*/
20401 #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL
20402 #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT
20403 #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK
20404 #define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 0xFFFFFFFF
20405 #define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 14
20406 #define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 0x00004000U
20408 /*Master Tri-state Enable for pin 47, active high*/
20409 #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL
20410 #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT
20411 #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK
20412 #define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 0xFFFFFFFF
20413 #define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 15
20414 #define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 0x00008000U
20416 /*Master Tri-state Enable for pin 48, active high*/
20417 #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL
20418 #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT
20419 #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK
20420 #define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 0xFFFFFFFF
20421 #define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 16
20422 #define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 0x00010000U
20424 /*Master Tri-state Enable for pin 49, active high*/
20425 #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL
20426 #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT
20427 #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK
20428 #define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 0xFFFFFFFF
20429 #define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 17
20430 #define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 0x00020000U
20432 /*Master Tri-state Enable for pin 50, active high*/
20433 #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL
20434 #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT
20435 #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK
20436 #define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 0xFFFFFFFF
20437 #define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 18
20438 #define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 0x00040000U
20440 /*Master Tri-state Enable for pin 51, active high*/
20441 #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL
20442 #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT
20443 #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK
20444 #define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 0xFFFFFFFF
20445 #define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 19
20446 #define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 0x00080000U
20448 /*Master Tri-state Enable for pin 52, active high*/
20449 #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL
20450 #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT
20451 #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK
20452 #define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 0xFFFFFFFF
20453 #define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 20
20454 #define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 0x00100000U
20456 /*Master Tri-state Enable for pin 53, active high*/
20457 #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL
20458 #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT
20459 #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK
20460 #define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 0xFFFFFFFF
20461 #define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 21
20462 #define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 0x00200000U
20464 /*Master Tri-state Enable for pin 54, active high*/
20465 #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL
20466 #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT
20467 #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK
20468 #define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 0xFFFFFFFF
20469 #define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 22
20470 #define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 0x00400000U
20472 /*Master Tri-state Enable for pin 55, active high*/
20473 #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL
20474 #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT
20475 #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK
20476 #define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 0xFFFFFFFF
20477 #define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 23
20478 #define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 0x00800000U
20480 /*Master Tri-state Enable for pin 56, active high*/
20481 #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL
20482 #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT
20483 #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK
20484 #define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 0xFFFFFFFF
20485 #define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 24
20486 #define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 0x01000000U
20488 /*Master Tri-state Enable for pin 57, active high*/
20489 #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL
20490 #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT
20491 #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK
20492 #define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 0xFFFFFFFF
20493 #define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 25
20494 #define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 0x02000000U
20496 /*Master Tri-state Enable for pin 58, active high*/
20497 #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL
20498 #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT
20499 #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK
20500 #define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 0xFFFFFFFF
20501 #define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 26
20502 #define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 0x04000000U
20504 /*Master Tri-state Enable for pin 59, active high*/
20505 #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL
20506 #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT
20507 #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK
20508 #define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 0xFFFFFFFF
20509 #define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 27
20510 #define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 0x08000000U
20512 /*Master Tri-state Enable for pin 60, active high*/
20513 #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL
20514 #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT
20515 #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK
20516 #define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 0xFFFFFFFF
20517 #define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 28
20518 #define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 0x10000000U
20520 /*Master Tri-state Enable for pin 61, active high*/
20521 #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL
20522 #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT
20523 #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK
20524 #define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 0xFFFFFFFF
20525 #define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 29
20526 #define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 0x20000000U
20528 /*Master Tri-state Enable for pin 62, active high*/
20529 #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL
20530 #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT
20531 #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK
20532 #define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 0xFFFFFFFF
20533 #define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 30
20534 #define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 0x40000000U
20536 /*Master Tri-state Enable for pin 63, active high*/
20537 #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL
20538 #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT
20539 #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK
20540 #define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 0xFFFFFFFF
20541 #define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 31
20542 #define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 0x80000000U
20544 /*Master Tri-state Enable for pin 64, active high*/
20545 #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL
20546 #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT
20547 #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK
20548 #define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 0x00003FFF
20549 #define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 0
20550 #define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 0x00000001U
20552 /*Master Tri-state Enable for pin 65, active high*/
20553 #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL
20554 #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT
20555 #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK
20556 #define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 0x00003FFF
20557 #define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 1
20558 #define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 0x00000002U
20560 /*Master Tri-state Enable for pin 66, active high*/
20561 #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL
20562 #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT
20563 #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK
20564 #define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 0x00003FFF
20565 #define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 2
20566 #define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 0x00000004U
20568 /*Master Tri-state Enable for pin 67, active high*/
20569 #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL
20570 #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT
20571 #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK
20572 #define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 0x00003FFF
20573 #define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 3
20574 #define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 0x00000008U
20576 /*Master Tri-state Enable for pin 68, active high*/
20577 #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL
20578 #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT
20579 #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK
20580 #define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 0x00003FFF
20581 #define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 4
20582 #define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 0x00000010U
20584 /*Master Tri-state Enable for pin 69, active high*/
20585 #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL
20586 #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT
20587 #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK
20588 #define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 0x00003FFF
20589 #define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 5
20590 #define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 0x00000020U
20592 /*Master Tri-state Enable for pin 70, active high*/
20593 #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL
20594 #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT
20595 #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK
20596 #define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 0x00003FFF
20597 #define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 6
20598 #define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 0x00000040U
20600 /*Master Tri-state Enable for pin 71, active high*/
20601 #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL
20602 #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT
20603 #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK
20604 #define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 0x00003FFF
20605 #define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 7
20606 #define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 0x00000080U
20608 /*Master Tri-state Enable for pin 72, active high*/
20609 #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL
20610 #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT
20611 #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK
20612 #define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 0x00003FFF
20613 #define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 8
20614 #define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 0x00000100U
20616 /*Master Tri-state Enable for pin 73, active high*/
20617 #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL
20618 #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT
20619 #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK
20620 #define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 0x00003FFF
20621 #define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 9
20622 #define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 0x00000200U
20624 /*Master Tri-state Enable for pin 74, active high*/
20625 #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL
20626 #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT
20627 #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK
20628 #define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 0x00003FFF
20629 #define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 10
20630 #define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 0x00000400U
20632 /*Master Tri-state Enable for pin 75, active high*/
20633 #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL
20634 #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT
20635 #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK
20636 #define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 0x00003FFF
20637 #define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 11
20638 #define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 0x00000800U
20640 /*Master Tri-state Enable for pin 76, active high*/
20641 #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL
20642 #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT
20643 #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK
20644 #define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 0x00003FFF
20645 #define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 12
20646 #define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 0x00001000U
20648 /*Master Tri-state Enable for pin 77, active high*/
20649 #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL
20650 #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT
20651 #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK
20652 #define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 0x00003FFF
20653 #define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 13
20654 #define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 0x00002000U
20656 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20657 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL
20658 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT
20659 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK
20660 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL
20661 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT 0
20662 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U
20664 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20665 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL
20666 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT
20667 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK
20668 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL
20669 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT 1
20670 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U
20672 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20673 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL
20674 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT
20675 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK
20676 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL
20677 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT 2
20678 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U
20680 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20681 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL
20682 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT
20683 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK
20684 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL
20685 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT 3
20686 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U
20688 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20689 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL
20690 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT
20691 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK
20692 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL
20693 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT 4
20694 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U
20696 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20697 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL
20698 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT
20699 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK
20700 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL
20701 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT 5
20702 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U
20704 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20705 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL
20706 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT
20707 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK
20708 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL
20709 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT 6
20710 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U
20712 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20713 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL
20714 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT
20715 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK
20716 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL
20717 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT 7
20718 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U
20720 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20721 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL
20722 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT
20723 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK
20724 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL
20725 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT 8
20726 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U
20728 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20729 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL
20730 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT
20731 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK
20732 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL
20733 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT 9
20734 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U
20736 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20737 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL
20738 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT
20739 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK
20740 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL
20741 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT 10
20742 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U
20744 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20745 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL
20746 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT
20747 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK
20748 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL
20749 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT 11
20750 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U
20752 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20753 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL
20754 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT
20755 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK
20756 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL
20757 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT 12
20758 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U
20760 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20761 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL
20762 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT
20763 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK
20764 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL
20765 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT 13
20766 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U
20768 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20769 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL
20770 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT
20771 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK
20772 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL
20773 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT 14
20774 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U
20776 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20777 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL
20778 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT
20779 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK
20780 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL
20781 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT 15
20782 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U
20784 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20785 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL
20786 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT
20787 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK
20788 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL
20789 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT 16
20790 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U
20792 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20793 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL
20794 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT
20795 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK
20796 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL
20797 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT 17
20798 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U
20800 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20801 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL
20802 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT
20803 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK
20804 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL
20805 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT 18
20806 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U
20808 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20809 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL
20810 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT
20811 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK
20812 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL
20813 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT 19
20814 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U
20816 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20817 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL
20818 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT
20819 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK
20820 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL
20821 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT 20
20822 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U
20824 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20825 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL
20826 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT
20827 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK
20828 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL
20829 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT 21
20830 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U
20832 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20833 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL
20834 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT
20835 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK
20836 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL
20837 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT 22
20838 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U
20840 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20841 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL
20842 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT
20843 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK
20844 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL
20845 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT 23
20846 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U
20848 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20849 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL
20850 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT
20851 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK
20852 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL
20853 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT 24
20854 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U
20856 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20857 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL
20858 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT
20859 #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK
20860 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL
20861 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT 25
20862 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U
20864 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20865 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL
20866 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT
20867 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK
20868 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL
20869 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT 0
20870 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U
20872 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20873 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL
20874 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT
20875 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK
20876 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL
20877 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT 1
20878 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U
20880 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20881 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL
20882 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT
20883 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK
20884 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL
20885 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT 2
20886 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U
20888 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20889 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL
20890 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT
20891 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK
20892 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL
20893 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT 3
20894 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U
20896 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20897 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL
20898 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT
20899 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK
20900 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL
20901 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT 4
20902 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U
20904 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20905 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL
20906 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT
20907 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK
20908 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL
20909 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT 5
20910 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U
20912 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20913 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL
20914 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT
20915 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK
20916 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL
20917 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT 6
20918 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U
20920 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20921 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL
20922 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT
20923 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK
20924 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL
20925 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT 7
20926 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U
20928 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20929 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL
20930 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT
20931 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK
20932 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL
20933 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT 8
20934 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U
20936 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20937 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL
20938 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT
20939 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK
20940 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL
20941 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT 9
20942 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U
20944 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20945 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL
20946 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT
20947 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK
20948 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL
20949 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT 10
20950 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U
20952 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20953 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL
20954 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT
20955 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK
20956 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL
20957 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT 11
20958 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U
20960 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20961 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL
20962 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT
20963 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK
20964 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL
20965 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT 12
20966 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U
20968 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20969 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL
20970 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT
20971 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK
20972 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL
20973 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT 13
20974 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U
20976 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20977 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL
20978 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT
20979 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK
20980 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL
20981 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT 14
20982 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U
20984 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20985 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL
20986 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT
20987 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK
20988 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL
20989 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT 15
20990 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U
20992 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
20993 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL
20994 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT
20995 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK
20996 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL
20997 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT 16
20998 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U
21000 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21001 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL
21002 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT
21003 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK
21004 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL
21005 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT 17
21006 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U
21008 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21009 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL
21010 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT
21011 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK
21012 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL
21013 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT 18
21014 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U
21016 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21017 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL
21018 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT
21019 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK
21020 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL
21021 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT 19
21022 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U
21024 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21025 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL
21026 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT
21027 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK
21028 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL
21029 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT 20
21030 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U
21032 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21033 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL
21034 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT
21035 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK
21036 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL
21037 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT 21
21038 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U
21040 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21041 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL
21042 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT
21043 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK
21044 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL
21045 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT 22
21046 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U
21048 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21049 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL
21050 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT
21051 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK
21052 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL
21053 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT 23
21054 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U
21056 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21057 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL
21058 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT
21059 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK
21060 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL
21061 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT 24
21062 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U
21064 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21065 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL
21066 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT
21067 #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK
21068 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL
21069 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT 25
21070 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U
21072 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21073 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
21074 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
21075 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK
21076 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
21077 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0
21078 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U
21080 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21081 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
21082 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
21083 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK
21084 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
21085 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1
21086 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U
21088 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21089 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
21090 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
21091 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK
21092 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
21093 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2
21094 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U
21096 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21097 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
21098 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
21099 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK
21100 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
21101 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3
21102 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U
21104 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21105 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
21106 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
21107 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK
21108 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
21109 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4
21110 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U
21112 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21113 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
21114 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
21115 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK
21116 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
21117 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5
21118 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U
21120 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21121 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
21122 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
21123 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK
21124 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
21125 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6
21126 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U
21128 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21129 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
21130 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
21131 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK
21132 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
21133 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7
21134 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U
21136 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21137 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
21138 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
21139 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK
21140 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
21141 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8
21142 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U
21144 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21145 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
21146 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
21147 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK
21148 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
21149 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9
21150 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U
21152 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21153 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
21154 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
21155 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK
21156 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
21157 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10
21158 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U
21160 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21161 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
21162 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
21163 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK
21164 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
21165 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11
21166 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U
21168 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21169 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
21170 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
21171 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK
21172 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
21173 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12
21174 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U
21176 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21177 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
21178 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
21179 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK
21180 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
21181 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13
21182 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U
21184 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21185 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
21186 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
21187 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK
21188 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
21189 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14
21190 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U
21192 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21193 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
21194 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
21195 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK
21196 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
21197 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15
21198 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U
21200 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21201 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
21202 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
21203 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK
21204 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
21205 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16
21206 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U
21208 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21209 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
21210 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
21211 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK
21212 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
21213 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17
21214 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U
21216 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21217 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
21218 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
21219 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK
21220 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
21221 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18
21222 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U
21224 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21225 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
21226 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
21227 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK
21228 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
21229 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19
21230 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U
21232 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21233 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
21234 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
21235 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK
21236 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
21237 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20
21238 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U
21240 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21241 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
21242 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
21243 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK
21244 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
21245 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21
21246 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U
21248 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21249 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
21250 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
21251 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK
21252 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
21253 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22
21254 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U
21256 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21257 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
21258 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
21259 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK
21260 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
21261 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23
21262 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U
21264 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21265 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
21266 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
21267 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK
21268 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
21269 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24
21270 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U
21272 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21273 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
21274 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
21275 #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK
21276 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
21277 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25
21278 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U
21280 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21281 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
21282 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
21283 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK
21284 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
21285 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0
21286 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U
21288 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21289 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
21290 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
21291 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK
21292 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
21293 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1
21294 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U
21296 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21297 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
21298 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
21299 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK
21300 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
21301 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2
21302 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U
21304 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21305 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
21306 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
21307 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK
21308 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
21309 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3
21310 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U
21312 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21313 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
21314 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
21315 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK
21316 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
21317 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4
21318 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U
21320 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21321 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
21322 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
21323 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK
21324 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
21325 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5
21326 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U
21328 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21329 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
21330 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
21331 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK
21332 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
21333 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6
21334 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U
21336 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21337 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
21338 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
21339 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK
21340 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
21341 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7
21342 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U
21344 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21345 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
21346 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
21347 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK
21348 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
21349 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8
21350 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U
21352 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21353 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
21354 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
21355 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK
21356 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
21357 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9
21358 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U
21360 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21361 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
21362 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
21363 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK
21364 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
21365 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10
21366 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U
21368 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21369 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
21370 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
21371 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK
21372 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
21373 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11
21374 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U
21376 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21377 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
21378 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
21379 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK
21380 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
21381 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12
21382 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U
21384 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21385 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
21386 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
21387 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK
21388 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
21389 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13
21390 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U
21392 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21393 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
21394 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
21395 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK
21396 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
21397 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14
21398 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U
21400 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21401 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
21402 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
21403 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK
21404 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
21405 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15
21406 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U
21408 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21409 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
21410 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
21411 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK
21412 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
21413 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16
21414 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U
21416 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21417 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
21418 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
21419 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK
21420 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
21421 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17
21422 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U
21424 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21425 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
21426 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
21427 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK
21428 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
21429 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18
21430 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U
21432 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21433 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
21434 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
21435 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK
21436 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
21437 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19
21438 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U
21440 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21441 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
21442 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
21443 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK
21444 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
21445 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20
21446 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U
21448 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21449 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
21450 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
21451 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK
21452 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
21453 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21
21454 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U
21456 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21457 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
21458 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
21459 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK
21460 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
21461 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22
21462 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U
21464 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21465 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
21466 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
21467 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK
21468 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
21469 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23
21470 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U
21472 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21473 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
21474 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
21475 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK
21476 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
21477 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24
21478 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U
21480 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21481 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
21482 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
21483 #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK
21484 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
21485 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25
21486 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U
21488 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21489 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
21490 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT
21491 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK
21492 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
21493 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0
21494 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U
21496 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21497 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
21498 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT
21499 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK
21500 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
21501 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1
21502 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U
21504 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21505 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
21506 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT
21507 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK
21508 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
21509 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2
21510 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U
21512 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21513 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
21514 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT
21515 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK
21516 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
21517 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3
21518 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U
21520 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21521 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
21522 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT
21523 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK
21524 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
21525 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4
21526 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U
21528 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21529 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
21530 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT
21531 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK
21532 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
21533 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5
21534 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U
21536 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21537 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
21538 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT
21539 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK
21540 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
21541 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6
21542 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U
21544 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21545 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
21546 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT
21547 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK
21548 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
21549 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7
21550 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U
21552 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21553 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
21554 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT
21555 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK
21556 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
21557 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8
21558 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U
21560 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21561 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
21562 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT
21563 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK
21564 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
21565 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9
21566 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U
21568 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21569 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
21570 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT
21571 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK
21572 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
21573 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10
21574 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U
21576 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21577 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
21578 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT
21579 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK
21580 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
21581 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11
21582 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U
21584 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21585 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
21586 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT
21587 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK
21588 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
21589 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12
21590 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U
21592 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21593 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
21594 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT
21595 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK
21596 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
21597 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13
21598 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U
21600 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21601 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
21602 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT
21603 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK
21604 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
21605 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14
21606 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U
21608 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21609 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
21610 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT
21611 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK
21612 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
21613 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15
21614 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U
21616 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21617 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
21618 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT
21619 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK
21620 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
21621 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16
21622 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U
21624 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21625 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
21626 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT
21627 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK
21628 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
21629 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17
21630 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U
21632 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21633 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
21634 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT
21635 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK
21636 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
21637 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18
21638 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U
21640 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21641 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
21642 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT
21643 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK
21644 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
21645 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19
21646 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U
21648 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21649 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
21650 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT
21651 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK
21652 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
21653 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20
21654 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U
21656 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21657 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
21658 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT
21659 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK
21660 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
21661 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21
21662 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U
21664 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21665 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
21666 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT
21667 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK
21668 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
21669 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22
21670 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U
21672 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21673 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
21674 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT
21675 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK
21676 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
21677 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23
21678 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U
21680 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21681 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
21682 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT
21683 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK
21684 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
21685 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24
21686 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U
21688 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21689 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
21690 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT
21691 #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK
21692 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
21693 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25
21694 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U
21696 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21697 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
21698 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
21699 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK
21700 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
21701 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0
21702 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U
21704 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21705 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
21706 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
21707 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK
21708 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
21709 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1
21710 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U
21712 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21713 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
21714 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
21715 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK
21716 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
21717 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2
21718 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U
21720 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21721 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
21722 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
21723 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK
21724 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
21725 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3
21726 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U
21728 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21729 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
21730 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
21731 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK
21732 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
21733 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4
21734 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U
21736 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21737 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
21738 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
21739 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK
21740 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
21741 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5
21742 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U
21744 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21745 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
21746 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
21747 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK
21748 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
21749 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6
21750 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U
21752 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21753 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
21754 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
21755 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK
21756 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
21757 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7
21758 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U
21760 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21761 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
21762 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
21763 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK
21764 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
21765 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8
21766 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U
21768 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21769 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
21770 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
21771 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK
21772 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
21773 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9
21774 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U
21776 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21777 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
21778 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
21779 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK
21780 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
21781 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10
21782 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U
21784 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21785 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
21786 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
21787 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK
21788 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
21789 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11
21790 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U
21792 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21793 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
21794 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
21795 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK
21796 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
21797 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12
21798 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U
21800 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21801 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
21802 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
21803 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK
21804 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
21805 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13
21806 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U
21808 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21809 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
21810 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
21811 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK
21812 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
21813 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14
21814 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U
21816 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21817 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
21818 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
21819 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK
21820 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
21821 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15
21822 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U
21824 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21825 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
21826 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
21827 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK
21828 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
21829 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16
21830 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U
21832 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21833 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
21834 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
21835 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK
21836 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
21837 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17
21838 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U
21840 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21841 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
21842 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
21843 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK
21844 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
21845 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18
21846 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U
21848 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21849 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
21850 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
21851 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK
21852 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
21853 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19
21854 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U
21856 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21857 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
21858 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
21859 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK
21860 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
21861 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20
21862 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U
21864 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21865 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
21866 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
21867 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK
21868 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
21869 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21
21870 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U
21872 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21873 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
21874 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
21875 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK
21876 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
21877 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22
21878 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U
21880 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21881 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
21882 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
21883 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK
21884 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
21885 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23
21886 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U
21888 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21889 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
21890 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
21891 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK
21892 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
21893 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24
21894 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U
21896 /*Each bit applies to a single IO. Bit 0 for MIO[0].*/
21897 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
21898 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
21899 #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK
21900 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
21901 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25
21902 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U
21904 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21905 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL
21906 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT
21907 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK
21908 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL
21909 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT 0
21910 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U
21912 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21913 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL
21914 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT
21915 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK
21916 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL
21917 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT 1
21918 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U
21920 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21921 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL
21922 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT
21923 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK
21924 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL
21925 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT 2
21926 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U
21928 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21929 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL
21930 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT
21931 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK
21932 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL
21933 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT 3
21934 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U
21936 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21937 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL
21938 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT
21939 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK
21940 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL
21941 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT 4
21942 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U
21944 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21945 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL
21946 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT
21947 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK
21948 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL
21949 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT 5
21950 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U
21952 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21953 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL
21954 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT
21955 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK
21956 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL
21957 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT 6
21958 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U
21960 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21961 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL
21962 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT
21963 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK
21964 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL
21965 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT 7
21966 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U
21968 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21969 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL
21970 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT
21971 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK
21972 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL
21973 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT 8
21974 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U
21976 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21977 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL
21978 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT
21979 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK
21980 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL
21981 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT 9
21982 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U
21984 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21985 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL
21986 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT
21987 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK
21988 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL
21989 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT 10
21990 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U
21992 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
21993 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL
21994 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT
21995 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK
21996 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL
21997 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT 11
21998 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U
22000 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22001 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL
22002 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT
22003 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK
22004 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL
22005 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT 12
22006 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U
22008 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22009 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL
22010 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT
22011 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK
22012 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL
22013 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT 13
22014 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U
22016 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22017 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL
22018 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT
22019 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK
22020 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL
22021 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT 14
22022 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U
22024 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22025 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL
22026 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT
22027 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK
22028 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL
22029 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT 15
22030 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U
22032 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22033 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL
22034 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT
22035 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK
22036 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL
22037 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT 16
22038 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U
22040 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22041 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL
22042 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT
22043 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK
22044 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL
22045 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT 17
22046 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U
22048 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22049 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL
22050 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT
22051 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK
22052 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL
22053 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT 18
22054 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U
22056 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22057 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL
22058 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT
22059 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK
22060 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL
22061 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT 19
22062 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U
22064 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22065 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL
22066 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT
22067 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK
22068 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL
22069 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT 20
22070 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U
22072 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22073 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL
22074 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT
22075 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK
22076 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL
22077 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT 21
22078 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U
22080 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22081 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL
22082 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT
22083 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK
22084 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL
22085 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT 22
22086 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U
22088 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22089 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL
22090 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT
22091 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK
22092 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL
22093 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT 23
22094 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U
22096 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22097 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL
22098 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT
22099 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK
22100 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL
22101 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT 24
22102 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U
22104 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22105 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL
22106 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT
22107 #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK
22108 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL
22109 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT 25
22110 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U
22112 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22113 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL
22114 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT
22115 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK
22116 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL
22117 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT 0
22118 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U
22120 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22121 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL
22122 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT
22123 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK
22124 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL
22125 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT 1
22126 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U
22128 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22129 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL
22130 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT
22131 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK
22132 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL
22133 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT 2
22134 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U
22136 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22137 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL
22138 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT
22139 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK
22140 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL
22141 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT 3
22142 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U
22144 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22145 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL
22146 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT
22147 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK
22148 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL
22149 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT 4
22150 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U
22152 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22153 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL
22154 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT
22155 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK
22156 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL
22157 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT 5
22158 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U
22160 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22161 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL
22162 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT
22163 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK
22164 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL
22165 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT 6
22166 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U
22168 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22169 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL
22170 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT
22171 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK
22172 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL
22173 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT 7
22174 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U
22176 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22177 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL
22178 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT
22179 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK
22180 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL
22181 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT 8
22182 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U
22184 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22185 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL
22186 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT
22187 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK
22188 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL
22189 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT 9
22190 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U
22192 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22193 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL
22194 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT
22195 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK
22196 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL
22197 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT 10
22198 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U
22200 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22201 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL
22202 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT
22203 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK
22204 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL
22205 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT 11
22206 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U
22208 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22209 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL
22210 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT
22211 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK
22212 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL
22213 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT 12
22214 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U
22216 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22217 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL
22218 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT
22219 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK
22220 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL
22221 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT 13
22222 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U
22224 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22225 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL
22226 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT
22227 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK
22228 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL
22229 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT 14
22230 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U
22232 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22233 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL
22234 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT
22235 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK
22236 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL
22237 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT 15
22238 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U
22240 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22241 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL
22242 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT
22243 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK
22244 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL
22245 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT 16
22246 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U
22248 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22249 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL
22250 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT
22251 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK
22252 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL
22253 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT 17
22254 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U
22256 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22257 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL
22258 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT
22259 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK
22260 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL
22261 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT 18
22262 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U
22264 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22265 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL
22266 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT
22267 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK
22268 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL
22269 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT 19
22270 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U
22272 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22273 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL
22274 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT
22275 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK
22276 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL
22277 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT 20
22278 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U
22280 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22281 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL
22282 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT
22283 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK
22284 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL
22285 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT 21
22286 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U
22288 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22289 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL
22290 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT
22291 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK
22292 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL
22293 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT 22
22294 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U
22296 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22297 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL
22298 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT
22299 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK
22300 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL
22301 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT 23
22302 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U
22304 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22305 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL
22306 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT
22307 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK
22308 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL
22309 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT 24
22310 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U
22312 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22313 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL
22314 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT
22315 #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK
22316 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL
22317 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT 25
22318 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U
22320 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22321 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
22322 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
22323 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK
22324 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
22325 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0
22326 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U
22328 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22329 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
22330 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
22331 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK
22332 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
22333 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1
22334 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U
22336 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22337 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
22338 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
22339 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK
22340 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
22341 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2
22342 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U
22344 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22345 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
22346 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
22347 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK
22348 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
22349 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3
22350 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U
22352 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22353 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
22354 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
22355 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK
22356 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
22357 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4
22358 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U
22360 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22361 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
22362 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
22363 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK
22364 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
22365 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5
22366 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U
22368 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22369 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
22370 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
22371 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK
22372 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
22373 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6
22374 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U
22376 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22377 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
22378 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
22379 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK
22380 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
22381 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7
22382 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U
22384 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22385 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
22386 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
22387 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK
22388 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
22389 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8
22390 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U
22392 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22393 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
22394 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
22395 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK
22396 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
22397 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9
22398 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U
22400 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22401 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
22402 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
22403 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK
22404 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
22405 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10
22406 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U
22408 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22409 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
22410 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
22411 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK
22412 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
22413 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11
22414 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U
22416 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22417 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
22418 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
22419 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK
22420 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
22421 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12
22422 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U
22424 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22425 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
22426 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
22427 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK
22428 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
22429 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13
22430 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U
22432 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22433 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
22434 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
22435 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK
22436 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
22437 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14
22438 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U
22440 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22441 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
22442 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
22443 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK
22444 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
22445 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15
22446 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U
22448 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22449 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
22450 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
22451 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK
22452 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
22453 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16
22454 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U
22456 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22457 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
22458 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
22459 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK
22460 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
22461 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17
22462 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U
22464 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22465 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
22466 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
22467 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK
22468 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
22469 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18
22470 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U
22472 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22473 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
22474 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
22475 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK
22476 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
22477 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19
22478 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U
22480 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22481 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
22482 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
22483 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK
22484 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
22485 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20
22486 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U
22488 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22489 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
22490 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
22491 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK
22492 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
22493 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21
22494 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U
22496 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22497 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
22498 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
22499 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK
22500 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
22501 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22
22502 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U
22504 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22505 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
22506 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
22507 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK
22508 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
22509 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23
22510 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U
22512 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22513 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
22514 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
22515 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK
22516 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
22517 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24
22518 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U
22520 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22521 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
22522 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
22523 #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK
22524 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
22525 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25
22526 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U
22528 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22529 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
22530 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
22531 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK
22532 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
22533 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0
22534 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U
22536 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22537 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
22538 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
22539 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK
22540 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
22541 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1
22542 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U
22544 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22545 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
22546 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
22547 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK
22548 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
22549 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2
22550 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U
22552 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22553 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
22554 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
22555 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK
22556 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
22557 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3
22558 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U
22560 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22561 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
22562 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
22563 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK
22564 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
22565 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4
22566 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U
22568 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22569 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
22570 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
22571 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK
22572 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
22573 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5
22574 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U
22576 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22577 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
22578 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
22579 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK
22580 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
22581 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6
22582 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U
22584 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22585 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
22586 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
22587 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK
22588 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
22589 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7
22590 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U
22592 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22593 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
22594 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
22595 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK
22596 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
22597 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8
22598 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U
22600 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22601 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
22602 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
22603 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK
22604 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
22605 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9
22606 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U
22608 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22609 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
22610 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
22611 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK
22612 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
22613 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10
22614 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U
22616 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22617 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
22618 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
22619 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK
22620 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
22621 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11
22622 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U
22624 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22625 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
22626 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
22627 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK
22628 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
22629 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12
22630 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U
22632 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22633 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
22634 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
22635 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK
22636 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
22637 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13
22638 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U
22640 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22641 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
22642 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
22643 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK
22644 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
22645 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14
22646 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U
22648 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22649 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
22650 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
22651 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK
22652 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
22653 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15
22654 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U
22656 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22657 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
22658 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
22659 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK
22660 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
22661 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16
22662 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U
22664 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22665 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
22666 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
22667 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK
22668 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
22669 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17
22670 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U
22672 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22673 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
22674 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
22675 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK
22676 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
22677 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18
22678 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U
22680 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22681 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
22682 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
22683 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK
22684 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
22685 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19
22686 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U
22688 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22689 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
22690 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
22691 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK
22692 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
22693 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20
22694 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U
22696 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22697 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
22698 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
22699 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK
22700 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
22701 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21
22702 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U
22704 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22705 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
22706 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
22707 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK
22708 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
22709 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22
22710 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U
22712 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22713 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
22714 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
22715 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK
22716 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
22717 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23
22718 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U
22720 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22721 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
22722 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
22723 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK
22724 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
22725 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24
22726 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U
22728 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22729 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
22730 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
22731 #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK
22732 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
22733 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25
22734 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U
22736 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22737 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
22738 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT
22739 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK
22740 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
22741 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 12
22742 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00001000U
22744 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22745 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
22746 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT
22747 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK
22748 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
22749 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 13
22750 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00002000U
22752 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22753 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
22754 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT
22755 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK
22756 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
22757 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 14
22758 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00004000U
22760 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22761 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
22762 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT
22763 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK
22764 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
22765 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 15
22766 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00008000U
22768 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22769 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
22770 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT
22771 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK
22772 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
22773 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 16
22774 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00010000U
22776 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22777 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
22778 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT
22779 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK
22780 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
22781 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 17
22782 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00020000U
22784 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22785 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
22786 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT
22787 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK
22788 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
22789 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 18
22790 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00040000U
22792 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22793 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
22794 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT
22795 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK
22796 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
22797 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 19
22798 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00080000U
22800 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22801 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
22802 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT
22803 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK
22804 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
22805 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 20
22806 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00100000U
22808 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22809 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
22810 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT
22811 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK
22812 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
22813 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 21
22814 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00200000U
22816 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22817 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
22818 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT
22819 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK
22820 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
22821 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 22
22822 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00400000U
22824 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22825 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
22826 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT
22827 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK
22828 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
22829 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 23
22830 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00800000U
22832 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22833 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
22834 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT
22835 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK
22836 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
22837 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 24
22838 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 0x01000000U
22840 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22841 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
22842 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT
22843 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK
22844 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
22845 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 25
22846 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 0x02000000U
22848 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22849 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
22850 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT
22851 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK
22852 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
22853 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 0
22854 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00000001U
22856 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22857 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
22858 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT
22859 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK
22860 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
22861 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 1
22862 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00000002U
22864 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22865 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
22866 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT
22867 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK
22868 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
22869 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 2
22870 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00000004U
22872 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22873 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
22874 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT
22875 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK
22876 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
22877 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 3
22878 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00000008U
22880 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22881 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
22882 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT
22883 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK
22884 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
22885 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 4
22886 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00000010U
22888 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22889 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
22890 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT
22891 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK
22892 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
22893 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 5
22894 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00000020U
22896 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22897 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
22898 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT
22899 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK
22900 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
22901 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 6
22902 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00000040U
22904 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22905 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
22906 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT
22907 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK
22908 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
22909 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 7
22910 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00000080U
22912 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22913 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
22914 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT
22915 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK
22916 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
22917 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 8
22918 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00000100U
22920 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22921 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
22922 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT
22923 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK
22924 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
22925 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 9
22926 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00000200U
22928 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22929 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
22930 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT
22931 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK
22932 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
22933 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 10
22934 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 0x00000400U
22936 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22937 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
22938 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT
22939 #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK
22940 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
22941 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 11
22942 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 0x00000800U
22944 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22945 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
22946 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
22947 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK
22948 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
22949 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0
22950 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U
22952 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22953 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
22954 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
22955 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK
22956 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
22957 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1
22958 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U
22960 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22961 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
22962 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
22963 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK
22964 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
22965 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2
22966 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U
22968 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22969 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
22970 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
22971 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK
22972 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
22973 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3
22974 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U
22976 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22977 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
22978 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
22979 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK
22980 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
22981 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4
22982 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U
22984 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22985 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
22986 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
22987 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK
22988 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
22989 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5
22990 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U
22992 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
22993 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
22994 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
22995 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK
22996 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
22997 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6
22998 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U
23000 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23001 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
23002 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
23003 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK
23004 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
23005 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7
23006 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U
23008 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23009 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
23010 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
23011 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK
23012 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
23013 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8
23014 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U
23016 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23017 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
23018 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
23019 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK
23020 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
23021 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9
23022 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U
23024 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23025 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
23026 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
23027 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK
23028 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
23029 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10
23030 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U
23032 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23033 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
23034 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
23035 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK
23036 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
23037 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11
23038 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U
23040 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23041 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
23042 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
23043 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK
23044 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
23045 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12
23046 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U
23048 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23049 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
23050 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
23051 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK
23052 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
23053 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13
23054 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U
23056 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23057 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
23058 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
23059 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK
23060 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
23061 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14
23062 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U
23064 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23065 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
23066 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
23067 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK
23068 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
23069 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15
23070 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U
23072 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23073 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
23074 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
23075 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK
23076 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
23077 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16
23078 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U
23080 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23081 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
23082 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
23083 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK
23084 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
23085 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17
23086 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U
23088 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23089 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
23090 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
23091 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK
23092 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
23093 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18
23094 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U
23096 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23097 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
23098 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
23099 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK
23100 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
23101 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19
23102 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U
23104 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23105 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
23106 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
23107 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK
23108 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
23109 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20
23110 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U
23112 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23113 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
23114 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
23115 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK
23116 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
23117 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21
23118 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U
23120 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23121 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
23122 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
23123 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK
23124 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
23125 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22
23126 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U
23128 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23129 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
23130 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
23131 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK
23132 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
23133 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23
23134 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U
23136 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23137 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
23138 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
23139 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK
23140 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
23141 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24
23142 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U
23144 /*Each bit applies to a single IO. Bit 0 for MIO[26].*/
23145 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
23146 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
23147 #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK
23148 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
23149 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25
23150 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U
23152 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23153 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL
23154 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT
23155 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK
23156 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL
23157 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT 0
23158 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U
23160 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23161 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL
23162 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT
23163 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK
23164 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL
23165 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT 1
23166 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U
23168 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23169 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL
23170 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT
23171 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK
23172 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL
23173 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT 2
23174 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U
23176 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23177 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL
23178 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT
23179 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK
23180 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL
23181 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT 3
23182 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U
23184 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23185 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL
23186 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT
23187 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK
23188 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL
23189 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT 4
23190 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U
23192 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23193 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL
23194 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT
23195 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK
23196 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL
23197 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT 5
23198 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U
23200 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23201 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL
23202 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT
23203 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK
23204 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL
23205 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT 6
23206 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U
23208 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23209 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL
23210 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT
23211 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK
23212 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL
23213 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT 7
23214 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U
23216 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23217 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL
23218 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT
23219 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK
23220 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL
23221 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT 8
23222 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U
23224 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23225 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL
23226 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT
23227 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK
23228 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL
23229 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT 9
23230 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U
23232 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23233 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL
23234 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT
23235 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK
23236 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL
23237 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT 10
23238 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U
23240 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23241 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL
23242 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT
23243 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK
23244 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL
23245 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT 11
23246 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U
23248 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23249 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL
23250 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT
23251 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK
23252 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL
23253 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT 12
23254 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U
23256 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23257 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL
23258 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT
23259 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK
23260 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL
23261 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT 13
23262 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U
23264 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23265 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL
23266 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT
23267 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK
23268 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL
23269 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT 14
23270 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U
23272 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23273 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL
23274 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT
23275 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK
23276 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL
23277 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT 15
23278 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U
23280 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23281 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL
23282 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT
23283 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK
23284 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL
23285 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT 16
23286 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U
23288 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23289 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL
23290 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT
23291 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK
23292 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL
23293 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT 17
23294 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U
23296 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23297 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL
23298 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT
23299 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK
23300 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL
23301 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT 18
23302 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U
23304 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23305 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL
23306 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT
23307 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK
23308 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL
23309 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT 19
23310 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U
23312 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23313 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL
23314 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT
23315 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK
23316 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL
23317 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT 20
23318 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U
23320 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23321 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL
23322 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT
23323 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK
23324 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL
23325 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT 21
23326 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U
23328 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23329 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL
23330 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT
23331 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK
23332 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL
23333 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT 22
23334 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U
23336 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23337 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL
23338 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT
23339 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK
23340 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL
23341 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT 23
23342 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U
23344 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23345 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL
23346 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT
23347 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK
23348 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL
23349 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT 24
23350 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U
23352 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23353 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL
23354 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT
23355 #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK
23356 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL
23357 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT 25
23358 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U
23360 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23361 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL
23362 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT
23363 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK
23364 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL
23365 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT 0
23366 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U
23368 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23369 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL
23370 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT
23371 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK
23372 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL
23373 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT 1
23374 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U
23376 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23377 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL
23378 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT
23379 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK
23380 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL
23381 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT 2
23382 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U
23384 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23385 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL
23386 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT
23387 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK
23388 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL
23389 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT 3
23390 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U
23392 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23393 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL
23394 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT
23395 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK
23396 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL
23397 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT 4
23398 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U
23400 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23401 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL
23402 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT
23403 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK
23404 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL
23405 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT 5
23406 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U
23408 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23409 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL
23410 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT
23411 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK
23412 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL
23413 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT 6
23414 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U
23416 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23417 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL
23418 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT
23419 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK
23420 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL
23421 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT 7
23422 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U
23424 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23425 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL
23426 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT
23427 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK
23428 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL
23429 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT 8
23430 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U
23432 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23433 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL
23434 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT
23435 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK
23436 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL
23437 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT 9
23438 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U
23440 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23441 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL
23442 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT
23443 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK
23444 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL
23445 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT 10
23446 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U
23448 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23449 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL
23450 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT
23451 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK
23452 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL
23453 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT 11
23454 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U
23456 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23457 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL
23458 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT
23459 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK
23460 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL
23461 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT 12
23462 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U
23464 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23465 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL
23466 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT
23467 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK
23468 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL
23469 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT 13
23470 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U
23472 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23473 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL
23474 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT
23475 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK
23476 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL
23477 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT 14
23478 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U
23480 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23481 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL
23482 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT
23483 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK
23484 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL
23485 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT 15
23486 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U
23488 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23489 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL
23490 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT
23491 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK
23492 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL
23493 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT 16
23494 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U
23496 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23497 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL
23498 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT
23499 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK
23500 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL
23501 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT 17
23502 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U
23504 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23505 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL
23506 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT
23507 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK
23508 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL
23509 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT 18
23510 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U
23512 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23513 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL
23514 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT
23515 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK
23516 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL
23517 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT 19
23518 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U
23520 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23521 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL
23522 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT
23523 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK
23524 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL
23525 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT 20
23526 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U
23528 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23529 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL
23530 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT
23531 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK
23532 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL
23533 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT 21
23534 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U
23536 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23537 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL
23538 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT
23539 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK
23540 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL
23541 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT 22
23542 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U
23544 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23545 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL
23546 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT
23547 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK
23548 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL
23549 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT 23
23550 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U
23552 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23553 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL
23554 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT
23555 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK
23556 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL
23557 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT 24
23558 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U
23560 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23561 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL
23562 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT
23563 #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK
23564 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL
23565 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT 25
23566 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U
23568 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23569 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
23570 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
23571 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK
23572 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
23573 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0
23574 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U
23576 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23577 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
23578 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
23579 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK
23580 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
23581 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1
23582 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U
23584 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23585 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
23586 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
23587 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK
23588 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
23589 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2
23590 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U
23592 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23593 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
23594 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
23595 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK
23596 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
23597 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3
23598 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U
23600 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23601 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
23602 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
23603 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK
23604 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
23605 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4
23606 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U
23608 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23609 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
23610 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
23611 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK
23612 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
23613 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5
23614 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U
23616 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23617 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
23618 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
23619 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK
23620 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
23621 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6
23622 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U
23624 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23625 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
23626 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
23627 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK
23628 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
23629 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7
23630 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U
23632 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23633 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
23634 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
23635 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK
23636 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
23637 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8
23638 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U
23640 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23641 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
23642 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
23643 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK
23644 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
23645 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9
23646 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U
23648 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23649 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
23650 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
23651 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK
23652 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
23653 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10
23654 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U
23656 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23657 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
23658 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
23659 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK
23660 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
23661 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11
23662 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U
23664 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23665 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
23666 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
23667 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK
23668 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
23669 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12
23670 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U
23672 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23673 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
23674 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
23675 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK
23676 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
23677 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13
23678 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U
23680 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23681 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
23682 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
23683 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK
23684 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
23685 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14
23686 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U
23688 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23689 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
23690 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
23691 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK
23692 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
23693 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15
23694 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U
23696 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23697 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
23698 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
23699 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK
23700 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
23701 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16
23702 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U
23704 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23705 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
23706 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
23707 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK
23708 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
23709 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17
23710 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U
23712 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23713 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
23714 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
23715 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK
23716 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
23717 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18
23718 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U
23720 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23721 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
23722 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
23723 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK
23724 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
23725 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19
23726 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U
23728 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23729 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
23730 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
23731 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK
23732 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
23733 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20
23734 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U
23736 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23737 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
23738 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
23739 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK
23740 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
23741 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21
23742 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U
23744 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23745 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
23746 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
23747 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK
23748 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
23749 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22
23750 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U
23752 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23753 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
23754 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
23755 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK
23756 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
23757 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23
23758 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U
23760 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23761 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
23762 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
23763 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK
23764 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
23765 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24
23766 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U
23768 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23769 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
23770 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
23771 #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK
23772 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
23773 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25
23774 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U
23776 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23777 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
23778 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
23779 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK
23780 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
23781 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0
23782 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U
23784 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23785 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
23786 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
23787 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK
23788 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
23789 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1
23790 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U
23792 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23793 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
23794 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
23795 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK
23796 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
23797 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2
23798 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U
23800 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23801 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
23802 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
23803 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK
23804 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
23805 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3
23806 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U
23808 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23809 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
23810 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
23811 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK
23812 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
23813 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4
23814 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U
23816 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23817 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
23818 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
23819 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK
23820 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
23821 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5
23822 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U
23824 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23825 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
23826 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
23827 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK
23828 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
23829 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6
23830 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U
23832 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23833 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
23834 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
23835 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK
23836 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
23837 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7
23838 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U
23840 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23841 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
23842 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
23843 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK
23844 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
23845 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8
23846 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U
23848 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23849 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
23850 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
23851 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK
23852 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
23853 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9
23854 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U
23856 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23857 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
23858 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
23859 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK
23860 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
23861 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10
23862 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U
23864 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23865 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
23866 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
23867 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK
23868 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
23869 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11
23870 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U
23872 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23873 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
23874 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
23875 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK
23876 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
23877 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12
23878 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U
23880 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23881 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
23882 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
23883 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK
23884 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
23885 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13
23886 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U
23888 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23889 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
23890 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
23891 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK
23892 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
23893 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14
23894 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U
23896 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23897 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
23898 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
23899 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK
23900 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
23901 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15
23902 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U
23904 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23905 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
23906 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
23907 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK
23908 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
23909 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16
23910 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U
23912 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23913 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
23914 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
23915 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK
23916 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
23917 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17
23918 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U
23920 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23921 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
23922 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
23923 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK
23924 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
23925 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18
23926 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U
23928 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23929 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
23930 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
23931 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK
23932 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
23933 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19
23934 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U
23936 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23937 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
23938 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
23939 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK
23940 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
23941 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20
23942 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U
23944 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23945 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
23946 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
23947 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK
23948 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
23949 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21
23950 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U
23952 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23953 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
23954 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
23955 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK
23956 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
23957 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22
23958 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U
23960 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23961 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
23962 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
23963 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK
23964 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
23965 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23
23966 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U
23968 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23969 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
23970 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
23971 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK
23972 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
23973 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24
23974 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U
23976 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23977 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
23978 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
23979 #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK
23980 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
23981 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25
23982 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U
23984 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23985 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
23986 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT
23987 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK
23988 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
23989 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0
23990 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U
23992 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
23993 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
23994 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT
23995 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK
23996 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
23997 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1
23998 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U
24000 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24001 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
24002 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT
24003 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK
24004 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
24005 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2
24006 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U
24008 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24009 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
24010 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT
24011 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK
24012 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
24013 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3
24014 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U
24016 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24017 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
24018 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT
24019 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK
24020 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
24021 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4
24022 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U
24024 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24025 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
24026 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT
24027 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK
24028 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
24029 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5
24030 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U
24032 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24033 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
24034 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT
24035 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK
24036 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
24037 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6
24038 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U
24040 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24041 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
24042 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT
24043 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK
24044 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
24045 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7
24046 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U
24048 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24049 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
24050 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT
24051 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK
24052 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
24053 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8
24054 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U
24056 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24057 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
24058 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT
24059 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK
24060 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
24061 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9
24062 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U
24064 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24065 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
24066 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT
24067 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK
24068 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
24069 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10
24070 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U
24072 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24073 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
24074 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT
24075 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK
24076 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
24077 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11
24078 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U
24080 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24081 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
24082 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT
24083 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK
24084 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
24085 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12
24086 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U
24088 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24089 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
24090 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT
24091 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK
24092 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
24093 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13
24094 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U
24096 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24097 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
24098 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT
24099 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK
24100 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
24101 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14
24102 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U
24104 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24105 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
24106 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT
24107 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK
24108 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
24109 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15
24110 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U
24112 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24113 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
24114 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT
24115 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK
24116 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
24117 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16
24118 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U
24120 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24121 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
24122 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT
24123 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK
24124 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
24125 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17
24126 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U
24128 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24129 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
24130 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT
24131 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK
24132 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
24133 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18
24134 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U
24136 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24137 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
24138 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT
24139 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK
24140 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
24141 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19
24142 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U
24144 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24145 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
24146 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT
24147 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK
24148 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
24149 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20
24150 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U
24152 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24153 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
24154 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT
24155 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK
24156 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
24157 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21
24158 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U
24160 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24161 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
24162 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT
24163 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK
24164 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
24165 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22
24166 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U
24168 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24169 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
24170 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT
24171 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK
24172 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
24173 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23
24174 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U
24176 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24177 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
24178 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT
24179 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK
24180 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
24181 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24
24182 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U
24184 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24185 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
24186 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT
24187 #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK
24188 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
24189 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25
24190 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U
24192 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24193 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
24194 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
24195 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK
24196 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
24197 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0
24198 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U
24200 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24201 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
24202 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
24203 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK
24204 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
24205 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1
24206 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U
24208 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24209 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
24210 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
24211 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK
24212 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
24213 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2
24214 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U
24216 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24217 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
24218 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
24219 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK
24220 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
24221 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3
24222 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U
24224 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24225 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
24226 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
24227 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK
24228 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
24229 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4
24230 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U
24232 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24233 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
24234 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
24235 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK
24236 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
24237 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5
24238 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U
24240 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24241 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
24242 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
24243 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK
24244 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
24245 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6
24246 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U
24248 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24249 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
24250 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
24251 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK
24252 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
24253 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7
24254 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U
24256 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24257 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
24258 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
24259 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK
24260 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
24261 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8
24262 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U
24264 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24265 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
24266 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
24267 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK
24268 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
24269 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9
24270 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U
24272 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24273 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
24274 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
24275 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK
24276 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
24277 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10
24278 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U
24280 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24281 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
24282 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
24283 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK
24284 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
24285 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11
24286 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U
24288 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24289 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
24290 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
24291 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK
24292 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
24293 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12
24294 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U
24296 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24297 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
24298 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
24299 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK
24300 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
24301 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13
24302 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U
24304 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24305 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
24306 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
24307 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK
24308 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
24309 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14
24310 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U
24312 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24313 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
24314 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
24315 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK
24316 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
24317 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15
24318 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U
24320 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24321 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
24322 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
24323 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK
24324 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
24325 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16
24326 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U
24328 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24329 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
24330 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
24331 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK
24332 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
24333 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17
24334 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U
24336 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24337 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
24338 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
24339 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK
24340 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
24341 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18
24342 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U
24344 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24345 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
24346 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
24347 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK
24348 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
24349 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19
24350 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U
24352 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24353 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
24354 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
24355 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK
24356 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
24357 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20
24358 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U
24360 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24361 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
24362 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
24363 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK
24364 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
24365 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21
24366 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U
24368 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24369 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
24370 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
24371 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK
24372 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
24373 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22
24374 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U
24376 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24377 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
24378 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
24379 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK
24380 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
24381 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23
24382 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U
24384 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24385 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
24386 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
24387 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK
24388 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
24389 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24
24390 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U
24392 /*Each bit applies to a single IO. Bit 0 for MIO[52].*/
24393 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
24394 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
24395 #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK
24396 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
24397 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25
24398 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U
24400 /*I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp
24401 ts to I2C 0 inputs.*/
24402 #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL
24403 #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT
24404 #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK
24405 #define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL 0x00000000
24406 #define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT 3
24407 #define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK 0x00000008U
24409 /*CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R
24411 #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL
24412 #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT
24413 #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK
24414 #define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL 0x00000000
24415 #define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT 2
24416 #define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK 0x00000004U
24418 /*UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1
24419 outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.*/
24420 #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL
24421 #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT
24422 #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK
24423 #define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL 0x00000000
24424 #define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT 1
24425 #define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK 0x00000002U
24427 /*SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp
24428 ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.*/
24429 #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL
24430 #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT
24431 #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK
24432 #define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 0x00000000
24433 #define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 0
24434 #define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 0x00000001U
24435 #undef CRL_APB_RST_LPD_IOU2_OFFSET
24436 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
24437 #undef CRL_APB_RST_LPD_IOU0_OFFSET
24438 #define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230
24439 #undef CRL_APB_RST_LPD_IOU2_OFFSET
24440 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
24441 #undef IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET
24442 #define IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET 0XFF180390
24443 #undef CRL_APB_RST_LPD_TOP_OFFSET
24444 #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
24445 #undef CRF_APB_RST_FPD_TOP_OFFSET
24446 #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
24447 #undef CRL_APB_RST_LPD_IOU2_OFFSET
24448 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
24449 #undef IOU_SLCR_CTRL_REG_SD_OFFSET
24450 #define IOU_SLCR_CTRL_REG_SD_OFFSET 0XFF180310
24451 #undef IOU_SLCR_SD_CONFIG_REG2_OFFSET
24452 #define IOU_SLCR_SD_CONFIG_REG2_OFFSET 0XFF180320
24453 #undef IOU_SLCR_SD_CONFIG_REG1_OFFSET
24454 #define IOU_SLCR_SD_CONFIG_REG1_OFFSET 0XFF18031C
24455 #undef IOU_SLCR_SD_CONFIG_REG3_OFFSET
24456 #define IOU_SLCR_SD_CONFIG_REG3_OFFSET 0XFF180324
24457 #undef CRL_APB_RST_LPD_IOU2_OFFSET
24458 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
24459 #undef CRL_APB_RST_LPD_IOU2_OFFSET
24460 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
24461 #undef CRL_APB_RST_LPD_IOU2_OFFSET
24462 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
24463 #undef CRL_APB_RST_LPD_IOU2_OFFSET
24464 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
24465 #undef CRL_APB_RST_LPD_IOU2_OFFSET
24466 #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
24467 #undef UART0_BAUD_RATE_DIVIDER_REG0_OFFSET
24468 #define UART0_BAUD_RATE_DIVIDER_REG0_OFFSET 0XFF000034
24469 #undef UART0_BAUD_RATE_GEN_REG0_OFFSET
24470 #define UART0_BAUD_RATE_GEN_REG0_OFFSET 0XFF000018
24471 #undef UART0_CONTROL_REG0_OFFSET
24472 #define UART0_CONTROL_REG0_OFFSET 0XFF000000
24473 #undef UART0_MODE_REG0_OFFSET
24474 #define UART0_MODE_REG0_OFFSET 0XFF000004
24475 #undef UART1_BAUD_RATE_DIVIDER_REG0_OFFSET
24476 #define UART1_BAUD_RATE_DIVIDER_REG0_OFFSET 0XFF010034
24477 #undef UART1_BAUD_RATE_GEN_REG0_OFFSET
24478 #define UART1_BAUD_RATE_GEN_REG0_OFFSET 0XFF010018
24479 #undef UART1_CONTROL_REG0_OFFSET
24480 #define UART1_CONTROL_REG0_OFFSET 0XFF010000
24481 #undef UART1_MODE_REG0_OFFSET
24482 #define UART1_MODE_REG0_OFFSET 0XFF010004
24483 #undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET
24484 #define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 0XFF4B0024
24485 #undef CSU_TAMPER_STATUS_OFFSET
24486 #define CSU_TAMPER_STATUS_OFFSET 0XFFCA5000
24487 #undef APU_ACE_CTRL_OFFSET
24488 #define APU_ACE_CTRL_OFFSET 0XFD5C0060
24489 #undef RTC_CONTROL_OFFSET
24490 #define RTC_CONTROL_OFFSET 0XFFA60040
24491 #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET
24492 #define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET 0XFF260020
24493 #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET
24494 #define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET 0XFF260000
24496 /*Block level reset*/
24497 #undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL
24498 #undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT
24499 #undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK
24500 #define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL 0x0017FFFF
24501 #define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT 20
24502 #define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK 0x00100000U
24505 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL
24506 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
24507 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK
24508 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F
24509 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3
24510 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U
24512 /*Block level reset*/
24513 #undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL
24514 #undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT
24515 #undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK
24516 #define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL 0x0017FFFF
24517 #define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 0
24518 #define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 0x00000001U
24520 /*0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypass the Tap delay on the Rx clock signal of LQSPI*/
24521 #undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL
24522 #undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT
24523 #undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK
24524 #define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL 0x00000007
24525 #define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 2
24526 #define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U
24528 /*USB 0 reset for control registers*/
24529 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL
24530 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
24531 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK
24532 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF
24533 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10
24534 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U
24536 /*USB 0 sleep circuit reset*/
24537 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL
24538 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
24539 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK
24540 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF
24541 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8
24542 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U
24545 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL
24546 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
24547 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK
24548 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF
24549 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6
24550 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U
24552 /*PCIE config reset*/
24553 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL
24554 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
24555 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK
24556 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE
24557 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19
24558 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U
24560 /*PCIE control block level reset*/
24561 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL
24562 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
24563 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK
24564 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE
24565 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17
24566 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U
24568 /*PCIE bridge block level reset (AXI interface)*/
24569 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL
24570 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
24571 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK
24572 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE
24573 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18
24574 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U
24576 /*Display Port block level reset (includes DPDMA)*/
24577 #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL
24578 #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
24579 #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK
24580 #define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE
24581 #define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16
24582 #define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U
24585 #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL
24586 #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT
24587 #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK
24588 #define CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL 0x000F9FFE
24589 #define CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT 15
24590 #define CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK 0x00008000U
24592 /*GDMA block level reset*/
24593 #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL
24594 #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT
24595 #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK
24596 #define CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL 0x000F9FFE
24597 #define CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT 6
24598 #define CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK 0x00000040U
24600 /*Pixel Processor (submodule of GPU) block level reset*/
24601 #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL
24602 #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT
24603 #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK
24604 #define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL 0x000F9FFE
24605 #define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT 4
24606 #define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK 0x00000010U
24608 /*Pixel Processor (submodule of GPU) block level reset*/
24609 #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL
24610 #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT
24611 #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK
24612 #define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL 0x000F9FFE
24613 #define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT 5
24614 #define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK 0x00000020U
24616 /*GPU block level reset*/
24617 #undef CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL
24618 #undef CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT
24619 #undef CRF_APB_RST_FPD_TOP_GPU_RESET_MASK
24620 #define CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL 0x000F9FFE
24621 #define CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT 3
24622 #define CRF_APB_RST_FPD_TOP_GPU_RESET_MASK 0x00000008U
24624 /*GT block level reset*/
24625 #undef CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL
24626 #undef CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT
24627 #undef CRF_APB_RST_FPD_TOP_GT_RESET_MASK
24628 #define CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL 0x000F9FFE
24629 #define CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT 2
24630 #define CRF_APB_RST_FPD_TOP_GT_RESET_MASK 0x00000004U
24632 /*Sata block level reset*/
24633 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL
24634 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
24635 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK
24636 #define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE
24637 #define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1
24638 #define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U
24640 /*Block level reset*/
24641 #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL
24642 #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT
24643 #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK
24644 #define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL 0x0017FFFF
24645 #define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT 6
24646 #define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK 0x00000040U
24648 /*SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled*/
24649 #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL
24650 #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT
24651 #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK
24652 #define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL 0x00000000
24653 #define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT 15
24654 #define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK 0x00008000U
24656 /*Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
24658 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL
24659 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT
24660 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK
24661 #define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL 0x0FFC0FFC
24662 #define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT 28
24663 #define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK 0x30000000U
24665 /*1.8V Support 1: 1.8V supported 0: 1.8V not supported support*/
24666 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL
24667 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT
24668 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK
24669 #define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL 0x0FFC0FFC
24670 #define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT 25
24671 #define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK 0x02000000U
24673 /*3.0V Support 1: 3.0V supported 0: 3.0V not supported support*/
24674 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL
24675 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT
24676 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK
24677 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL 0x0FFC0FFC
24678 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT 24
24679 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK 0x01000000U
24681 /*3.3V Support 1: 3.3V supported 0: 3.3V not supported support*/
24682 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL
24683 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT
24684 #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK
24685 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL 0x0FFC0FFC
24686 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT 23
24687 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK 0x00800000U
24689 /*Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.*/
24690 #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL
24691 #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT
24692 #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK
24693 #define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL 0x32403240
24694 #define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT 23
24695 #define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK 0x7F800000U
24697 /*This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. 0h - Get inf
24698 rmation via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 secon
24699 s Fh - Ch = Reserved*/
24700 #undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL
24701 #undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT
24702 #undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK
24703 #define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL 0x06070607
24704 #define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT 22
24705 #define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK 0x03C00000U
24707 /*Block level reset*/
24708 #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL
24709 #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT
24710 #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK
24711 #define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL 0x0017FFFF
24712 #define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 8
24713 #define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK 0x00000100U
24715 /*Block level reset*/
24716 #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL
24717 #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT
24718 #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK
24719 #define CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL 0x0017FFFF
24720 #define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 9
24721 #define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK 0x00000200U
24723 /*Block level reset*/
24724 #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL
24725 #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT
24726 #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK
24727 #define CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL 0x0017FFFF
24728 #define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT 10
24729 #define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK 0x00000400U
24731 /*Block level reset*/
24732 #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL
24733 #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT
24734 #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK
24735 #define CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL 0x0017FFFF
24736 #define CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT 15
24737 #define CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK 0x00008000U
24739 /*Block level reset*/
24740 #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL
24741 #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT
24742 #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK
24743 #define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL 0x0017FFFF
24744 #define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 11
24745 #define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK 0x00000800U
24747 /*Block level reset*/
24748 #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL
24749 #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT
24750 #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK
24751 #define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL 0x0017FFFF
24752 #define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 12
24753 #define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK 0x00001000U
24755 /*Block level reset*/
24756 #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL
24757 #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT
24758 #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK
24759 #define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL 0x0017FFFF
24760 #define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 13
24761 #define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK 0x00002000U
24763 /*Block level reset*/
24764 #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL
24765 #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT
24766 #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK
24767 #define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL 0x0017FFFF
24768 #define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 14
24769 #define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK 0x00004000U
24771 /*Block level reset*/
24772 #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL
24773 #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT
24774 #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK
24775 #define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL 0x0017FFFF
24776 #define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 1
24777 #define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK 0x00000002U
24779 /*Block level reset*/
24780 #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL
24781 #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT
24782 #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK
24783 #define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL 0x0017FFFF
24784 #define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 2
24785 #define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 0x00000004U
24787 /*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/
24788 #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL
24789 #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
24790 #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK
24791 #define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F
24792 #define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0
24793 #define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU
24795 /*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/
24796 #undef UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL
24797 #undef UART0_BAUD_RATE_GEN_REG0_CD_SHIFT
24798 #undef UART0_BAUD_RATE_GEN_REG0_CD_MASK
24799 #define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B
24800 #define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 0
24801 #define UART0_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU
24803 /*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
24804 high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/
24805 #undef UART0_CONTROL_REG0_STPBRK_DEFVAL
24806 #undef UART0_CONTROL_REG0_STPBRK_SHIFT
24807 #undef UART0_CONTROL_REG0_STPBRK_MASK
24808 #define UART0_CONTROL_REG0_STPBRK_DEFVAL 0x00000128
24809 #define UART0_CONTROL_REG0_STPBRK_SHIFT 8
24810 #define UART0_CONTROL_REG0_STPBRK_MASK 0x00000100U
24812 /*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
24813 transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/
24814 #undef UART0_CONTROL_REG0_STTBRK_DEFVAL
24815 #undef UART0_CONTROL_REG0_STTBRK_SHIFT
24816 #undef UART0_CONTROL_REG0_STTBRK_MASK
24817 #define UART0_CONTROL_REG0_STTBRK_DEFVAL 0x00000128
24818 #define UART0_CONTROL_REG0_STTBRK_SHIFT 7
24819 #define UART0_CONTROL_REG0_STTBRK_MASK 0x00000080U
24821 /*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
24823 #undef UART0_CONTROL_REG0_RSTTO_DEFVAL
24824 #undef UART0_CONTROL_REG0_RSTTO_SHIFT
24825 #undef UART0_CONTROL_REG0_RSTTO_MASK
24826 #define UART0_CONTROL_REG0_RSTTO_DEFVAL 0x00000128
24827 #define UART0_CONTROL_REG0_RSTTO_SHIFT 6
24828 #define UART0_CONTROL_REG0_RSTTO_MASK 0x00000040U
24830 /*Transmit disable: 0: enable transmitter 1: disable transmitter*/
24831 #undef UART0_CONTROL_REG0_TXDIS_DEFVAL
24832 #undef UART0_CONTROL_REG0_TXDIS_SHIFT
24833 #undef UART0_CONTROL_REG0_TXDIS_MASK
24834 #define UART0_CONTROL_REG0_TXDIS_DEFVAL 0x00000128
24835 #define UART0_CONTROL_REG0_TXDIS_SHIFT 5
24836 #define UART0_CONTROL_REG0_TXDIS_MASK 0x00000020U
24838 /*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/
24839 #undef UART0_CONTROL_REG0_TXEN_DEFVAL
24840 #undef UART0_CONTROL_REG0_TXEN_SHIFT
24841 #undef UART0_CONTROL_REG0_TXEN_MASK
24842 #define UART0_CONTROL_REG0_TXEN_DEFVAL 0x00000128
24843 #define UART0_CONTROL_REG0_TXEN_SHIFT 4
24844 #define UART0_CONTROL_REG0_TXEN_MASK 0x00000010U
24846 /*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/
24847 #undef UART0_CONTROL_REG0_RXDIS_DEFVAL
24848 #undef UART0_CONTROL_REG0_RXDIS_SHIFT
24849 #undef UART0_CONTROL_REG0_RXDIS_MASK
24850 #define UART0_CONTROL_REG0_RXDIS_DEFVAL 0x00000128
24851 #define UART0_CONTROL_REG0_RXDIS_SHIFT 3
24852 #define UART0_CONTROL_REG0_RXDIS_MASK 0x00000008U
24854 /*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/
24855 #undef UART0_CONTROL_REG0_RXEN_DEFVAL
24856 #undef UART0_CONTROL_REG0_RXEN_SHIFT
24857 #undef UART0_CONTROL_REG0_RXEN_MASK
24858 #define UART0_CONTROL_REG0_RXEN_DEFVAL 0x00000128
24859 #define UART0_CONTROL_REG0_RXEN_SHIFT 2
24860 #define UART0_CONTROL_REG0_RXEN_MASK 0x00000004U
24862 /*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
24863 bit is self clearing once the reset has completed.*/
24864 #undef UART0_CONTROL_REG0_TXRES_DEFVAL
24865 #undef UART0_CONTROL_REG0_TXRES_SHIFT
24866 #undef UART0_CONTROL_REG0_TXRES_MASK
24867 #define UART0_CONTROL_REG0_TXRES_DEFVAL 0x00000128
24868 #define UART0_CONTROL_REG0_TXRES_SHIFT 1
24869 #define UART0_CONTROL_REG0_TXRES_MASK 0x00000002U
24871 /*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
24872 is self clearing once the reset has completed.*/
24873 #undef UART0_CONTROL_REG0_RXRES_DEFVAL
24874 #undef UART0_CONTROL_REG0_RXRES_SHIFT
24875 #undef UART0_CONTROL_REG0_RXRES_MASK
24876 #define UART0_CONTROL_REG0_RXRES_DEFVAL 0x00000128
24877 #define UART0_CONTROL_REG0_RXRES_SHIFT 0
24878 #define UART0_CONTROL_REG0_RXRES_MASK 0x00000001U
24880 /*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/
24881 #undef UART0_MODE_REG0_CHMODE_DEFVAL
24882 #undef UART0_MODE_REG0_CHMODE_SHIFT
24883 #undef UART0_MODE_REG0_CHMODE_MASK
24884 #define UART0_MODE_REG0_CHMODE_DEFVAL 0x00000000
24885 #define UART0_MODE_REG0_CHMODE_SHIFT 8
24886 #define UART0_MODE_REG0_CHMODE_MASK 0x00000300U
24888 /*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
24889 stop bits 10: 2 stop bits 11: reserved*/
24890 #undef UART0_MODE_REG0_NBSTOP_DEFVAL
24891 #undef UART0_MODE_REG0_NBSTOP_SHIFT
24892 #undef UART0_MODE_REG0_NBSTOP_MASK
24893 #define UART0_MODE_REG0_NBSTOP_DEFVAL 0x00000000
24894 #define UART0_MODE_REG0_NBSTOP_SHIFT 6
24895 #define UART0_MODE_REG0_NBSTOP_MASK 0x000000C0U
24897 /*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity
24898 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/
24899 #undef UART0_MODE_REG0_PAR_DEFVAL
24900 #undef UART0_MODE_REG0_PAR_SHIFT
24901 #undef UART0_MODE_REG0_PAR_MASK
24902 #define UART0_MODE_REG0_PAR_DEFVAL 0x00000000
24903 #define UART0_MODE_REG0_PAR_SHIFT 3
24904 #define UART0_MODE_REG0_PAR_MASK 0x00000038U
24906 /*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/
24907 #undef UART0_MODE_REG0_CHRL_DEFVAL
24908 #undef UART0_MODE_REG0_CHRL_SHIFT
24909 #undef UART0_MODE_REG0_CHRL_MASK
24910 #define UART0_MODE_REG0_CHRL_DEFVAL 0x00000000
24911 #define UART0_MODE_REG0_CHRL_SHIFT 1
24912 #define UART0_MODE_REG0_CHRL_MASK 0x00000006U
24914 /*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
24915 source is uart_ref_clk 1: clock source is uart_ref_clk/8*/
24916 #undef UART0_MODE_REG0_CLKS_DEFVAL
24917 #undef UART0_MODE_REG0_CLKS_SHIFT
24918 #undef UART0_MODE_REG0_CLKS_MASK
24919 #define UART0_MODE_REG0_CLKS_DEFVAL 0x00000000
24920 #define UART0_MODE_REG0_CLKS_SHIFT 0
24921 #define UART0_MODE_REG0_CLKS_MASK 0x00000001U
24923 /*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/
24924 #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL
24925 #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
24926 #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK
24927 #define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F
24928 #define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0
24929 #define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU
24931 /*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/
24932 #undef UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL
24933 #undef UART1_BAUD_RATE_GEN_REG0_CD_SHIFT
24934 #undef UART1_BAUD_RATE_GEN_REG0_CD_MASK
24935 #define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B
24936 #define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 0
24937 #define UART1_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU
24939 /*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
24940 high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/
24941 #undef UART1_CONTROL_REG0_STPBRK_DEFVAL
24942 #undef UART1_CONTROL_REG0_STPBRK_SHIFT
24943 #undef UART1_CONTROL_REG0_STPBRK_MASK
24944 #define UART1_CONTROL_REG0_STPBRK_DEFVAL 0x00000128
24945 #define UART1_CONTROL_REG0_STPBRK_SHIFT 8
24946 #define UART1_CONTROL_REG0_STPBRK_MASK 0x00000100U
24948 /*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
24949 transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/
24950 #undef UART1_CONTROL_REG0_STTBRK_DEFVAL
24951 #undef UART1_CONTROL_REG0_STTBRK_SHIFT
24952 #undef UART1_CONTROL_REG0_STTBRK_MASK
24953 #define UART1_CONTROL_REG0_STTBRK_DEFVAL 0x00000128
24954 #define UART1_CONTROL_REG0_STTBRK_SHIFT 7
24955 #define UART1_CONTROL_REG0_STTBRK_MASK 0x00000080U
24957 /*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
24959 #undef UART1_CONTROL_REG0_RSTTO_DEFVAL
24960 #undef UART1_CONTROL_REG0_RSTTO_SHIFT
24961 #undef UART1_CONTROL_REG0_RSTTO_MASK
24962 #define UART1_CONTROL_REG0_RSTTO_DEFVAL 0x00000128
24963 #define UART1_CONTROL_REG0_RSTTO_SHIFT 6
24964 #define UART1_CONTROL_REG0_RSTTO_MASK 0x00000040U
24966 /*Transmit disable: 0: enable transmitter 1: disable transmitter*/
24967 #undef UART1_CONTROL_REG0_TXDIS_DEFVAL
24968 #undef UART1_CONTROL_REG0_TXDIS_SHIFT
24969 #undef UART1_CONTROL_REG0_TXDIS_MASK
24970 #define UART1_CONTROL_REG0_TXDIS_DEFVAL 0x00000128
24971 #define UART1_CONTROL_REG0_TXDIS_SHIFT 5
24972 #define UART1_CONTROL_REG0_TXDIS_MASK 0x00000020U
24974 /*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/
24975 #undef UART1_CONTROL_REG0_TXEN_DEFVAL
24976 #undef UART1_CONTROL_REG0_TXEN_SHIFT
24977 #undef UART1_CONTROL_REG0_TXEN_MASK
24978 #define UART1_CONTROL_REG0_TXEN_DEFVAL 0x00000128
24979 #define UART1_CONTROL_REG0_TXEN_SHIFT 4
24980 #define UART1_CONTROL_REG0_TXEN_MASK 0x00000010U
24982 /*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/
24983 #undef UART1_CONTROL_REG0_RXDIS_DEFVAL
24984 #undef UART1_CONTROL_REG0_RXDIS_SHIFT
24985 #undef UART1_CONTROL_REG0_RXDIS_MASK
24986 #define UART1_CONTROL_REG0_RXDIS_DEFVAL 0x00000128
24987 #define UART1_CONTROL_REG0_RXDIS_SHIFT 3
24988 #define UART1_CONTROL_REG0_RXDIS_MASK 0x00000008U
24990 /*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/
24991 #undef UART1_CONTROL_REG0_RXEN_DEFVAL
24992 #undef UART1_CONTROL_REG0_RXEN_SHIFT
24993 #undef UART1_CONTROL_REG0_RXEN_MASK
24994 #define UART1_CONTROL_REG0_RXEN_DEFVAL 0x00000128
24995 #define UART1_CONTROL_REG0_RXEN_SHIFT 2
24996 #define UART1_CONTROL_REG0_RXEN_MASK 0x00000004U
24998 /*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
24999 bit is self clearing once the reset has completed.*/
25000 #undef UART1_CONTROL_REG0_TXRES_DEFVAL
25001 #undef UART1_CONTROL_REG0_TXRES_SHIFT
25002 #undef UART1_CONTROL_REG0_TXRES_MASK
25003 #define UART1_CONTROL_REG0_TXRES_DEFVAL 0x00000128
25004 #define UART1_CONTROL_REG0_TXRES_SHIFT 1
25005 #define UART1_CONTROL_REG0_TXRES_MASK 0x00000002U
25007 /*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
25008 is self clearing once the reset has completed.*/
25009 #undef UART1_CONTROL_REG0_RXRES_DEFVAL
25010 #undef UART1_CONTROL_REG0_RXRES_SHIFT
25011 #undef UART1_CONTROL_REG0_RXRES_MASK
25012 #define UART1_CONTROL_REG0_RXRES_DEFVAL 0x00000128
25013 #define UART1_CONTROL_REG0_RXRES_SHIFT 0
25014 #define UART1_CONTROL_REG0_RXRES_MASK 0x00000001U
25016 /*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/
25017 #undef UART1_MODE_REG0_CHMODE_DEFVAL
25018 #undef UART1_MODE_REG0_CHMODE_SHIFT
25019 #undef UART1_MODE_REG0_CHMODE_MASK
25020 #define UART1_MODE_REG0_CHMODE_DEFVAL 0x00000000
25021 #define UART1_MODE_REG0_CHMODE_SHIFT 8
25022 #define UART1_MODE_REG0_CHMODE_MASK 0x00000300U
25024 /*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
25025 stop bits 10: 2 stop bits 11: reserved*/
25026 #undef UART1_MODE_REG0_NBSTOP_DEFVAL
25027 #undef UART1_MODE_REG0_NBSTOP_SHIFT
25028 #undef UART1_MODE_REG0_NBSTOP_MASK
25029 #define UART1_MODE_REG0_NBSTOP_DEFVAL 0x00000000
25030 #define UART1_MODE_REG0_NBSTOP_SHIFT 6
25031 #define UART1_MODE_REG0_NBSTOP_MASK 0x000000C0U
25033 /*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity
25034 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/
25035 #undef UART1_MODE_REG0_PAR_DEFVAL
25036 #undef UART1_MODE_REG0_PAR_SHIFT
25037 #undef UART1_MODE_REG0_PAR_MASK
25038 #define UART1_MODE_REG0_PAR_DEFVAL 0x00000000
25039 #define UART1_MODE_REG0_PAR_SHIFT 3
25040 #define UART1_MODE_REG0_PAR_MASK 0x00000038U
25042 /*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/
25043 #undef UART1_MODE_REG0_CHRL_DEFVAL
25044 #undef UART1_MODE_REG0_CHRL_SHIFT
25045 #undef UART1_MODE_REG0_CHRL_MASK
25046 #define UART1_MODE_REG0_CHRL_DEFVAL 0x00000000
25047 #define UART1_MODE_REG0_CHRL_SHIFT 1
25048 #define UART1_MODE_REG0_CHRL_MASK 0x00000006U
25050 /*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
25051 source is uart_ref_clk 1: clock source is uart_ref_clk/8*/
25052 #undef UART1_MODE_REG0_CLKS_DEFVAL
25053 #undef UART1_MODE_REG0_CLKS_SHIFT
25054 #undef UART1_MODE_REG0_CLKS_MASK
25055 #define UART1_MODE_REG0_CLKS_DEFVAL 0x00000000
25056 #define UART1_MODE_REG0_CLKS_SHIFT 0
25057 #define UART1_MODE_REG0_CLKS_MASK 0x00000001U
25059 /*TrustZone Classification for ADMA*/
25060 #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL
25061 #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT
25062 #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK
25063 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL
25064 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 0
25065 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 0x000000FFU
25068 #undef CSU_TAMPER_STATUS_TAMPER_0_DEFVAL
25069 #undef CSU_TAMPER_STATUS_TAMPER_0_SHIFT
25070 #undef CSU_TAMPER_STATUS_TAMPER_0_MASK
25071 #define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL 0x00000000
25072 #define CSU_TAMPER_STATUS_TAMPER_0_SHIFT 0
25073 #define CSU_TAMPER_STATUS_TAMPER_0_MASK 0x00000001U
25076 #undef CSU_TAMPER_STATUS_TAMPER_1_DEFVAL
25077 #undef CSU_TAMPER_STATUS_TAMPER_1_SHIFT
25078 #undef CSU_TAMPER_STATUS_TAMPER_1_MASK
25079 #define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL 0x00000000
25080 #define CSU_TAMPER_STATUS_TAMPER_1_SHIFT 1
25081 #define CSU_TAMPER_STATUS_TAMPER_1_MASK 0x00000002U
25083 /*JTAG toggle detect*/
25084 #undef CSU_TAMPER_STATUS_TAMPER_2_DEFVAL
25085 #undef CSU_TAMPER_STATUS_TAMPER_2_SHIFT
25086 #undef CSU_TAMPER_STATUS_TAMPER_2_MASK
25087 #define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL 0x00000000
25088 #define CSU_TAMPER_STATUS_TAMPER_2_SHIFT 2
25089 #define CSU_TAMPER_STATUS_TAMPER_2_MASK 0x00000004U
25092 #undef CSU_TAMPER_STATUS_TAMPER_3_DEFVAL
25093 #undef CSU_TAMPER_STATUS_TAMPER_3_SHIFT
25094 #undef CSU_TAMPER_STATUS_TAMPER_3_MASK
25095 #define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL 0x00000000
25096 #define CSU_TAMPER_STATUS_TAMPER_3_SHIFT 3
25097 #define CSU_TAMPER_STATUS_TAMPER_3_MASK 0x00000008U
25099 /*AMS over temperature alarm for LPD*/
25100 #undef CSU_TAMPER_STATUS_TAMPER_4_DEFVAL
25101 #undef CSU_TAMPER_STATUS_TAMPER_4_SHIFT
25102 #undef CSU_TAMPER_STATUS_TAMPER_4_MASK
25103 #define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL 0x00000000
25104 #define CSU_TAMPER_STATUS_TAMPER_4_SHIFT 4
25105 #define CSU_TAMPER_STATUS_TAMPER_4_MASK 0x00000010U
25107 /*AMS over temperature alarm for APU*/
25108 #undef CSU_TAMPER_STATUS_TAMPER_5_DEFVAL
25109 #undef CSU_TAMPER_STATUS_TAMPER_5_SHIFT
25110 #undef CSU_TAMPER_STATUS_TAMPER_5_MASK
25111 #define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL 0x00000000
25112 #define CSU_TAMPER_STATUS_TAMPER_5_SHIFT 5
25113 #define CSU_TAMPER_STATUS_TAMPER_5_MASK 0x00000020U
25115 /*AMS voltage alarm for VCCPINT_FPD*/
25116 #undef CSU_TAMPER_STATUS_TAMPER_6_DEFVAL
25117 #undef CSU_TAMPER_STATUS_TAMPER_6_SHIFT
25118 #undef CSU_TAMPER_STATUS_TAMPER_6_MASK
25119 #define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL 0x00000000
25120 #define CSU_TAMPER_STATUS_TAMPER_6_SHIFT 6
25121 #define CSU_TAMPER_STATUS_TAMPER_6_MASK 0x00000040U
25123 /*AMS voltage alarm for VCCPINT_LPD*/
25124 #undef CSU_TAMPER_STATUS_TAMPER_7_DEFVAL
25125 #undef CSU_TAMPER_STATUS_TAMPER_7_SHIFT
25126 #undef CSU_TAMPER_STATUS_TAMPER_7_MASK
25127 #define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL 0x00000000
25128 #define CSU_TAMPER_STATUS_TAMPER_7_SHIFT 7
25129 #define CSU_TAMPER_STATUS_TAMPER_7_MASK 0x00000080U
25131 /*AMS voltage alarm for VCCPAUX*/
25132 #undef CSU_TAMPER_STATUS_TAMPER_8_DEFVAL
25133 #undef CSU_TAMPER_STATUS_TAMPER_8_SHIFT
25134 #undef CSU_TAMPER_STATUS_TAMPER_8_MASK
25135 #define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL 0x00000000
25136 #define CSU_TAMPER_STATUS_TAMPER_8_SHIFT 8
25137 #define CSU_TAMPER_STATUS_TAMPER_8_MASK 0x00000100U
25139 /*AMS voltage alarm for DDRPHY*/
25140 #undef CSU_TAMPER_STATUS_TAMPER_9_DEFVAL
25141 #undef CSU_TAMPER_STATUS_TAMPER_9_SHIFT
25142 #undef CSU_TAMPER_STATUS_TAMPER_9_MASK
25143 #define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL 0x00000000
25144 #define CSU_TAMPER_STATUS_TAMPER_9_SHIFT 9
25145 #define CSU_TAMPER_STATUS_TAMPER_9_MASK 0x00000200U
25147 /*AMS voltage alarm for PSIO bank 0/1/2*/
25148 #undef CSU_TAMPER_STATUS_TAMPER_10_DEFVAL
25149 #undef CSU_TAMPER_STATUS_TAMPER_10_SHIFT
25150 #undef CSU_TAMPER_STATUS_TAMPER_10_MASK
25151 #define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL 0x00000000
25152 #define CSU_TAMPER_STATUS_TAMPER_10_SHIFT 10
25153 #define CSU_TAMPER_STATUS_TAMPER_10_MASK 0x00000400U
25155 /*AMS voltage alarm for PSIO bank 3 (dedicated pins)*/
25156 #undef CSU_TAMPER_STATUS_TAMPER_11_DEFVAL
25157 #undef CSU_TAMPER_STATUS_TAMPER_11_SHIFT
25158 #undef CSU_TAMPER_STATUS_TAMPER_11_MASK
25159 #define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL 0x00000000
25160 #define CSU_TAMPER_STATUS_TAMPER_11_SHIFT 11
25161 #define CSU_TAMPER_STATUS_TAMPER_11_MASK 0x00000800U
25163 /*AMS voltaage alarm for GT*/
25164 #undef CSU_TAMPER_STATUS_TAMPER_12_DEFVAL
25165 #undef CSU_TAMPER_STATUS_TAMPER_12_SHIFT
25166 #undef CSU_TAMPER_STATUS_TAMPER_12_MASK
25167 #define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL 0x00000000
25168 #define CSU_TAMPER_STATUS_TAMPER_12_SHIFT 12
25169 #define CSU_TAMPER_STATUS_TAMPER_12_MASK 0x00001000U
25171 /*Set ACE outgoing AWQOS value*/
25172 #undef APU_ACE_CTRL_AWQOS_DEFVAL
25173 #undef APU_ACE_CTRL_AWQOS_SHIFT
25174 #undef APU_ACE_CTRL_AWQOS_MASK
25175 #define APU_ACE_CTRL_AWQOS_DEFVAL 0x000F000F
25176 #define APU_ACE_CTRL_AWQOS_SHIFT 16
25177 #define APU_ACE_CTRL_AWQOS_MASK 0x000F0000U
25179 /*Set ACE outgoing ARQOS value*/
25180 #undef APU_ACE_CTRL_ARQOS_DEFVAL
25181 #undef APU_ACE_CTRL_ARQOS_SHIFT
25182 #undef APU_ACE_CTRL_ARQOS_MASK
25183 #define APU_ACE_CTRL_ARQOS_DEFVAL 0x000F000F
25184 #define APU_ACE_CTRL_ARQOS_SHIFT 0
25185 #define APU_ACE_CTRL_ARQOS_MASK 0x0000000FU
25187 /*Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from
25188 he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e
25189 pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi
25190 g a 0 to this bit.*/
25191 #undef RTC_CONTROL_BATTERY_DISABLE_DEFVAL
25192 #undef RTC_CONTROL_BATTERY_DISABLE_SHIFT
25193 #undef RTC_CONTROL_BATTERY_DISABLE_MASK
25194 #define RTC_CONTROL_BATTERY_DISABLE_DEFVAL 0x01000000
25195 #define RTC_CONTROL_BATTERY_DISABLE_SHIFT 31
25196 #define RTC_CONTROL_BATTERY_DISABLE_MASK 0x80000000U
25198 /*Frequency in number of ticks per second. Valid range from 10 MHz to 100 MHz.*/
25199 #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL
25200 #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT
25201 #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK
25202 #define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL
25203 #define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT 0
25204 #define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK 0xFFFFFFFFU
25206 /*Enable 0: The counter is disabled and not incrementing. 1: The counter is enabled and is incrementing.*/
25207 #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL
25208 #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT
25209 #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK
25210 #define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL 0x00000000
25211 #define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT 0
25212 #define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK 0x00000001U
25213 #undef LPD_XPPU_CFG_IEN_OFFSET
25214 #define LPD_XPPU_CFG_IEN_OFFSET 0XFF980018
25216 /*See Interuppt Status Register for details*/
25217 #undef LPD_XPPU_CFG_IEN_APER_PARITY_DEFVAL
25218 #undef LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT
25219 #undef LPD_XPPU_CFG_IEN_APER_PARITY_MASK
25220 #define LPD_XPPU_CFG_IEN_APER_PARITY_DEFVAL 0x00000000
25221 #define LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT 7
25222 #define LPD_XPPU_CFG_IEN_APER_PARITY_MASK 0x00000080U
25224 /*See Interuppt Status Register for details*/
25225 #undef LPD_XPPU_CFG_IEN_APER_TZ_DEFVAL
25226 #undef LPD_XPPU_CFG_IEN_APER_TZ_SHIFT
25227 #undef LPD_XPPU_CFG_IEN_APER_TZ_MASK
25228 #define LPD_XPPU_CFG_IEN_APER_TZ_DEFVAL 0x00000000
25229 #define LPD_XPPU_CFG_IEN_APER_TZ_SHIFT 6
25230 #define LPD_XPPU_CFG_IEN_APER_TZ_MASK 0x00000040U
25232 /*See Interuppt Status Register for details*/
25233 #undef LPD_XPPU_CFG_IEN_APER_PERM_DEFVAL
25234 #undef LPD_XPPU_CFG_IEN_APER_PERM_SHIFT
25235 #undef LPD_XPPU_CFG_IEN_APER_PERM_MASK
25236 #define LPD_XPPU_CFG_IEN_APER_PERM_DEFVAL 0x00000000
25237 #define LPD_XPPU_CFG_IEN_APER_PERM_SHIFT 5
25238 #define LPD_XPPU_CFG_IEN_APER_PERM_MASK 0x00000020U
25240 /*See Interuppt Status Register for details*/
25241 #undef LPD_XPPU_CFG_IEN_MID_PARITY_DEFVAL
25242 #undef LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT
25243 #undef LPD_XPPU_CFG_IEN_MID_PARITY_MASK
25244 #define LPD_XPPU_CFG_IEN_MID_PARITY_DEFVAL 0x00000000
25245 #define LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT 3
25246 #define LPD_XPPU_CFG_IEN_MID_PARITY_MASK 0x00000008U
25248 /*See Interuppt Status Register for details*/
25249 #undef LPD_XPPU_CFG_IEN_MID_RO_DEFVAL
25250 #undef LPD_XPPU_CFG_IEN_MID_RO_SHIFT
25251 #undef LPD_XPPU_CFG_IEN_MID_RO_MASK
25252 #define LPD_XPPU_CFG_IEN_MID_RO_DEFVAL 0x00000000
25253 #define LPD_XPPU_CFG_IEN_MID_RO_SHIFT 2
25254 #define LPD_XPPU_CFG_IEN_MID_RO_MASK 0x00000004U
25256 /*See Interuppt Status Register for details*/
25257 #undef LPD_XPPU_CFG_IEN_MID_MISS_DEFVAL
25258 #undef LPD_XPPU_CFG_IEN_MID_MISS_SHIFT
25259 #undef LPD_XPPU_CFG_IEN_MID_MISS_MASK
25260 #define LPD_XPPU_CFG_IEN_MID_MISS_DEFVAL 0x00000000
25261 #define LPD_XPPU_CFG_IEN_MID_MISS_SHIFT 1
25262 #define LPD_XPPU_CFG_IEN_MID_MISS_MASK 0x00000002U
25264 /*See Interuppt Status Register for details*/
25265 #undef LPD_XPPU_CFG_IEN_INV_APB_DEFVAL
25266 #undef LPD_XPPU_CFG_IEN_INV_APB_SHIFT
25267 #undef LPD_XPPU_CFG_IEN_INV_APB_MASK
25268 #define LPD_XPPU_CFG_IEN_INV_APB_DEFVAL 0x00000000
25269 #define LPD_XPPU_CFG_IEN_INV_APB_SHIFT 0
25270 #define LPD_XPPU_CFG_IEN_INV_APB_MASK 0x00000001U
25271 #undef SERDES_PLL_REF_SEL0_OFFSET
25272 #define SERDES_PLL_REF_SEL0_OFFSET 0XFD410000
25273 #undef SERDES_PLL_REF_SEL1_OFFSET
25274 #define SERDES_PLL_REF_SEL1_OFFSET 0XFD410004
25275 #undef SERDES_PLL_REF_SEL2_OFFSET
25276 #define SERDES_PLL_REF_SEL2_OFFSET 0XFD410008
25277 #undef SERDES_PLL_REF_SEL3_OFFSET
25278 #define SERDES_PLL_REF_SEL3_OFFSET 0XFD41000C
25279 #undef SERDES_L0_L0_REF_CLK_SEL_OFFSET
25280 #define SERDES_L0_L0_REF_CLK_SEL_OFFSET 0XFD402860
25281 #undef SERDES_L0_L1_REF_CLK_SEL_OFFSET
25282 #define SERDES_L0_L1_REF_CLK_SEL_OFFSET 0XFD402864
25283 #undef SERDES_L0_L2_REF_CLK_SEL_OFFSET
25284 #define SERDES_L0_L2_REF_CLK_SEL_OFFSET 0XFD402868
25285 #undef SERDES_L0_L3_REF_CLK_SEL_OFFSET
25286 #define SERDES_L0_L3_REF_CLK_SEL_OFFSET 0XFD40286C
25287 #undef SERDES_L2_TM_PLL_DIG_37_OFFSET
25288 #define SERDES_L2_TM_PLL_DIG_37_OFFSET 0XFD40A094
25289 #undef SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET
25290 #define SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET 0XFD40A368
25291 #undef SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET
25292 #define SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET 0XFD40A36C
25293 #undef SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET
25294 #define SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET 0XFD40E368
25295 #undef SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET
25296 #define SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET 0XFD40E36C
25297 #undef SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET
25298 #define SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET 0XFD406368
25299 #undef SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET
25300 #define SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET 0XFD40636C
25301 #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET
25302 #define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET 0XFD406370
25303 #undef SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET
25304 #define SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET 0XFD406374
25305 #undef SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET
25306 #define SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET 0XFD406378
25307 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET
25308 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET 0XFD40637C
25309 #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET
25310 #define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET 0XFD40A370
25311 #undef SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET
25312 #define SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET 0XFD40A374
25313 #undef SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET
25314 #define SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET 0XFD40A378
25315 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET
25316 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET 0XFD40A37C
25317 #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET
25318 #define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET 0XFD40E370
25319 #undef SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET
25320 #define SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET 0XFD40E374
25321 #undef SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET
25322 #define SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET 0XFD40E378
25323 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET
25324 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET 0XFD40E37C
25325 #undef SERDES_L2_TM_DIG_6_OFFSET
25326 #define SERDES_L2_TM_DIG_6_OFFSET 0XFD40906C
25327 #undef SERDES_L2_TX_DIG_TM_61_OFFSET
25328 #define SERDES_L2_TX_DIG_TM_61_OFFSET 0XFD4080F4
25329 #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET
25330 #define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET 0XFD40E360
25331 #undef SERDES_L3_TM_DIG_6_OFFSET
25332 #define SERDES_L3_TM_DIG_6_OFFSET 0XFD40D06C
25333 #undef SERDES_L3_TX_DIG_TM_61_OFFSET
25334 #define SERDES_L3_TX_DIG_TM_61_OFFSET 0XFD40C0F4
25335 #undef SERDES_L3_TXPMA_ST_0_OFFSET
25336 #define SERDES_L3_TXPMA_ST_0_OFFSET 0XFD40CB00
25337 #undef SERDES_L0_TM_AUX_0_OFFSET
25338 #define SERDES_L0_TM_AUX_0_OFFSET 0XFD4010CC
25339 #undef SERDES_L2_TM_AUX_0_OFFSET
25340 #define SERDES_L2_TM_AUX_0_OFFSET 0XFD4090CC
25341 #undef SERDES_L0_TM_DIG_8_OFFSET
25342 #define SERDES_L0_TM_DIG_8_OFFSET 0XFD401074
25343 #undef SERDES_L1_TM_DIG_8_OFFSET
25344 #define SERDES_L1_TM_DIG_8_OFFSET 0XFD405074
25345 #undef SERDES_L2_TM_DIG_8_OFFSET
25346 #define SERDES_L2_TM_DIG_8_OFFSET 0XFD409074
25347 #undef SERDES_L3_TM_DIG_8_OFFSET
25348 #define SERDES_L3_TM_DIG_8_OFFSET 0XFD40D074
25349 #undef SERDES_L0_TM_MISC2_OFFSET
25350 #define SERDES_L0_TM_MISC2_OFFSET 0XFD40189C
25351 #undef SERDES_L0_TM_IQ_ILL1_OFFSET
25352 #define SERDES_L0_TM_IQ_ILL1_OFFSET 0XFD4018F8
25353 #undef SERDES_L0_TM_IQ_ILL2_OFFSET
25354 #define SERDES_L0_TM_IQ_ILL2_OFFSET 0XFD4018FC
25355 #undef SERDES_L0_TM_ILL12_OFFSET
25356 #define SERDES_L0_TM_ILL12_OFFSET 0XFD401990
25357 #undef SERDES_L0_TM_E_ILL1_OFFSET
25358 #define SERDES_L0_TM_E_ILL1_OFFSET 0XFD401924
25359 #undef SERDES_L0_TM_E_ILL2_OFFSET
25360 #define SERDES_L0_TM_E_ILL2_OFFSET 0XFD401928
25361 #undef SERDES_L0_TM_IQ_ILL3_OFFSET
25362 #define SERDES_L0_TM_IQ_ILL3_OFFSET 0XFD401900
25363 #undef SERDES_L0_TM_E_ILL3_OFFSET
25364 #define SERDES_L0_TM_E_ILL3_OFFSET 0XFD40192C
25365 #undef SERDES_L0_TM_ILL8_OFFSET
25366 #define SERDES_L0_TM_ILL8_OFFSET 0XFD401980
25367 #undef SERDES_L0_TM_IQ_ILL8_OFFSET
25368 #define SERDES_L0_TM_IQ_ILL8_OFFSET 0XFD401914
25369 #undef SERDES_L0_TM_IQ_ILL9_OFFSET
25370 #define SERDES_L0_TM_IQ_ILL9_OFFSET 0XFD401918
25371 #undef SERDES_L0_TM_E_ILL8_OFFSET
25372 #define SERDES_L0_TM_E_ILL8_OFFSET 0XFD401940
25373 #undef SERDES_L0_TM_E_ILL9_OFFSET
25374 #define SERDES_L0_TM_E_ILL9_OFFSET 0XFD401944
25375 #undef SERDES_L2_TM_MISC2_OFFSET
25376 #define SERDES_L2_TM_MISC2_OFFSET 0XFD40989C
25377 #undef SERDES_L2_TM_IQ_ILL1_OFFSET
25378 #define SERDES_L2_TM_IQ_ILL1_OFFSET 0XFD4098F8
25379 #undef SERDES_L2_TM_IQ_ILL2_OFFSET
25380 #define SERDES_L2_TM_IQ_ILL2_OFFSET 0XFD4098FC
25381 #undef SERDES_L2_TM_ILL12_OFFSET
25382 #define SERDES_L2_TM_ILL12_OFFSET 0XFD409990
25383 #undef SERDES_L2_TM_E_ILL1_OFFSET
25384 #define SERDES_L2_TM_E_ILL1_OFFSET 0XFD409924
25385 #undef SERDES_L2_TM_E_ILL2_OFFSET
25386 #define SERDES_L2_TM_E_ILL2_OFFSET 0XFD409928
25387 #undef SERDES_L2_TM_IQ_ILL3_OFFSET
25388 #define SERDES_L2_TM_IQ_ILL3_OFFSET 0XFD409900
25389 #undef SERDES_L2_TM_E_ILL3_OFFSET
25390 #define SERDES_L2_TM_E_ILL3_OFFSET 0XFD40992C
25391 #undef SERDES_L2_TM_ILL8_OFFSET
25392 #define SERDES_L2_TM_ILL8_OFFSET 0XFD409980
25393 #undef SERDES_L2_TM_IQ_ILL8_OFFSET
25394 #define SERDES_L2_TM_IQ_ILL8_OFFSET 0XFD409914
25395 #undef SERDES_L2_TM_IQ_ILL9_OFFSET
25396 #define SERDES_L2_TM_IQ_ILL9_OFFSET 0XFD409918
25397 #undef SERDES_L2_TM_E_ILL8_OFFSET
25398 #define SERDES_L2_TM_E_ILL8_OFFSET 0XFD409940
25399 #undef SERDES_L2_TM_E_ILL9_OFFSET
25400 #define SERDES_L2_TM_E_ILL9_OFFSET 0XFD409944
25401 #undef SERDES_L3_TM_MISC2_OFFSET
25402 #define SERDES_L3_TM_MISC2_OFFSET 0XFD40D89C
25403 #undef SERDES_L3_TM_IQ_ILL1_OFFSET
25404 #define SERDES_L3_TM_IQ_ILL1_OFFSET 0XFD40D8F8
25405 #undef SERDES_L3_TM_IQ_ILL2_OFFSET
25406 #define SERDES_L3_TM_IQ_ILL2_OFFSET 0XFD40D8FC
25407 #undef SERDES_L3_TM_ILL12_OFFSET
25408 #define SERDES_L3_TM_ILL12_OFFSET 0XFD40D990
25409 #undef SERDES_L3_TM_E_ILL1_OFFSET
25410 #define SERDES_L3_TM_E_ILL1_OFFSET 0XFD40D924
25411 #undef SERDES_L3_TM_E_ILL2_OFFSET
25412 #define SERDES_L3_TM_E_ILL2_OFFSET 0XFD40D928
25413 #undef SERDES_L3_TM_ILL11_OFFSET
25414 #define SERDES_L3_TM_ILL11_OFFSET 0XFD40D98C
25415 #undef SERDES_L3_TM_IQ_ILL3_OFFSET
25416 #define SERDES_L3_TM_IQ_ILL3_OFFSET 0XFD40D900
25417 #undef SERDES_L3_TM_E_ILL3_OFFSET
25418 #define SERDES_L3_TM_E_ILL3_OFFSET 0XFD40D92C
25419 #undef SERDES_L3_TM_ILL8_OFFSET
25420 #define SERDES_L3_TM_ILL8_OFFSET 0XFD40D980
25421 #undef SERDES_L3_TM_IQ_ILL8_OFFSET
25422 #define SERDES_L3_TM_IQ_ILL8_OFFSET 0XFD40D914
25423 #undef SERDES_L3_TM_IQ_ILL9_OFFSET
25424 #define SERDES_L3_TM_IQ_ILL9_OFFSET 0XFD40D918
25425 #undef SERDES_L3_TM_E_ILL8_OFFSET
25426 #define SERDES_L3_TM_E_ILL8_OFFSET 0XFD40D940
25427 #undef SERDES_L3_TM_E_ILL9_OFFSET
25428 #define SERDES_L3_TM_E_ILL9_OFFSET 0XFD40D944
25429 #undef SERDES_L0_TM_DIG_21_OFFSET
25430 #define SERDES_L0_TM_DIG_21_OFFSET 0XFD4010A8
25431 #undef SERDES_L0_TM_DIG_10_OFFSET
25432 #define SERDES_L0_TM_DIG_10_OFFSET 0XFD40107C
25433 #undef SERDES_L0_TM_RST_DLY_OFFSET
25434 #define SERDES_L0_TM_RST_DLY_OFFSET 0XFD4019A4
25435 #undef SERDES_L0_TM_ANA_BYP_15_OFFSET
25436 #define SERDES_L0_TM_ANA_BYP_15_OFFSET 0XFD401038
25437 #undef SERDES_L0_TM_ANA_BYP_12_OFFSET
25438 #define SERDES_L0_TM_ANA_BYP_12_OFFSET 0XFD40102C
25439 #undef SERDES_L1_TM_RST_DLY_OFFSET
25440 #define SERDES_L1_TM_RST_DLY_OFFSET 0XFD4059A4
25441 #undef SERDES_L1_TM_ANA_BYP_15_OFFSET
25442 #define SERDES_L1_TM_ANA_BYP_15_OFFSET 0XFD405038
25443 #undef SERDES_L1_TM_ANA_BYP_12_OFFSET
25444 #define SERDES_L1_TM_ANA_BYP_12_OFFSET 0XFD40502C
25445 #undef SERDES_L2_TM_RST_DLY_OFFSET
25446 #define SERDES_L2_TM_RST_DLY_OFFSET 0XFD4099A4
25447 #undef SERDES_L2_TM_ANA_BYP_15_OFFSET
25448 #define SERDES_L2_TM_ANA_BYP_15_OFFSET 0XFD409038
25449 #undef SERDES_L2_TM_ANA_BYP_12_OFFSET
25450 #define SERDES_L2_TM_ANA_BYP_12_OFFSET 0XFD40902C
25451 #undef SERDES_L3_TM_RST_DLY_OFFSET
25452 #define SERDES_L3_TM_RST_DLY_OFFSET 0XFD40D9A4
25453 #undef SERDES_L3_TM_ANA_BYP_15_OFFSET
25454 #define SERDES_L3_TM_ANA_BYP_15_OFFSET 0XFD40D038
25455 #undef SERDES_L3_TM_ANA_BYP_12_OFFSET
25456 #define SERDES_L3_TM_ANA_BYP_12_OFFSET 0XFD40D02C
25457 #undef SERDES_ICM_CFG0_OFFSET
25458 #define SERDES_ICM_CFG0_OFFSET 0XFD410010
25459 #undef SERDES_ICM_CFG1_OFFSET
25460 #define SERDES_ICM_CFG1_OFFSET 0XFD410014
25461 #undef SERDES_L1_TXPMD_TM_45_OFFSET
25462 #define SERDES_L1_TXPMD_TM_45_OFFSET 0XFD404CB4
25463 #undef SERDES_L1_TX_ANA_TM_118_OFFSET
25464 #define SERDES_L1_TX_ANA_TM_118_OFFSET 0XFD4041D8
25465 #undef SERDES_L3_TX_ANA_TM_118_OFFSET
25466 #define SERDES_L3_TX_ANA_TM_118_OFFSET 0XFD40C1D8
25467 #undef SERDES_L3_TM_CDR5_OFFSET
25468 #define SERDES_L3_TM_CDR5_OFFSET 0XFD40DC14
25469 #undef SERDES_L3_TM_CDR16_OFFSET
25470 #define SERDES_L3_TM_CDR16_OFFSET 0XFD40DC40
25471 #undef SERDES_L3_TM_EQ0_OFFSET
25472 #define SERDES_L3_TM_EQ0_OFFSET 0XFD40D94C
25473 #undef SERDES_L3_TM_EQ1_OFFSET
25474 #define SERDES_L3_TM_EQ1_OFFSET 0XFD40D950
25475 #undef SERDES_L1_TXPMD_TM_48_OFFSET
25476 #define SERDES_L1_TXPMD_TM_48_OFFSET 0XFD404CC0
25477 #undef SERDES_L1_TX_ANA_TM_18_OFFSET
25478 #define SERDES_L1_TX_ANA_TM_18_OFFSET 0XFD404048
25479 #undef SERDES_L3_TX_ANA_TM_18_OFFSET
25480 #define SERDES_L3_TX_ANA_TM_18_OFFSET 0XFD40C048
25482 /*PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
25483 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
25484 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/
25485 #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL
25486 #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT
25487 #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK
25488 #define SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL 0x0000000D
25489 #define SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT 0
25490 #define SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK 0x0000001FU
25492 /*PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
25493 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
25494 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/
25495 #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL
25496 #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT
25497 #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK
25498 #define SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL 0x00000008
25499 #define SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT 0
25500 #define SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK 0x0000001FU
25502 /*PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
25503 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
25504 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/
25505 #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL
25506 #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT
25507 #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK
25508 #define SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL 0x0000000F
25509 #define SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT 0
25510 #define SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK 0x0000001FU
25512 /*PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
25513 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
25514 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/
25515 #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL
25516 #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT
25517 #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK
25518 #define SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL 0x0000000E
25519 #define SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT 0
25520 #define SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK 0x0000001FU
25522 /*Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output.*/
25523 #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL
25524 #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT
25525 #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK
25526 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL 0x00000080
25527 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT 7
25528 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK 0x00000080U
25530 /*Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output.*/
25531 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL
25532 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT
25533 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK
25534 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL 0x00000080
25535 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT 7
25536 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK 0x00000080U
25538 /*Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network*/
25539 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL
25540 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT
25541 #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK
25542 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL 0x00000080
25543 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT 3
25544 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK 0x00000008U
25546 /*Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output.*/
25547 #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL
25548 #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT
25549 #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK
25550 #define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL 0x00000080
25551 #define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT 7
25552 #define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK 0x00000080U
25554 /*Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output.*/
25555 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL
25556 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT
25557 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK
25558 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL 0x00000080
25559 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT 7
25560 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK 0x00000080U
25562 /*Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network*/
25563 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL
25564 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT
25565 #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK
25566 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL 0x00000080
25567 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT 1
25568 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK 0x00000002U
25570 /*Enable/Disable coarse code satureation limiting logic*/
25571 #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL
25572 #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT
25573 #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK
25574 #define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL 0x00000000
25575 #define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT 4
25576 #define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK 0x00000010U
25578 /*Spread Spectrum No of Steps [7:0]*/
25579 #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL
25580 #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
25581 #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK
25582 #define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000
25583 #define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0
25584 #define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU
25586 /*Spread Spectrum No of Steps [10:8]*/
25587 #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL
25588 #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
25589 #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK
25590 #define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000
25591 #define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0
25592 #define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U
25594 /*Spread Spectrum No of Steps [7:0]*/
25595 #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL
25596 #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
25597 #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK
25598 #define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000
25599 #define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0
25600 #define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU
25602 /*Spread Spectrum No of Steps [10:8]*/
25603 #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL
25604 #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
25605 #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK
25606 #define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000
25607 #define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0
25608 #define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U
25610 /*Spread Spectrum No of Steps [7:0]*/
25611 #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL
25612 #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
25613 #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK
25614 #define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000
25615 #define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0
25616 #define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU
25618 /*Spread Spectrum No of Steps [10:8]*/
25619 #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL
25620 #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
25621 #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK
25622 #define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000
25623 #define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0
25624 #define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U
25626 /*Step Size for Spread Spectrum [7:0]*/
25627 #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL
25628 #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
25629 #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK
25630 #define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000
25631 #define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0
25632 #define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU
25634 /*Step Size for Spread Spectrum [15:8]*/
25635 #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL
25636 #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
25637 #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK
25638 #define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000
25639 #define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0
25640 #define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU
25642 /*Step Size for Spread Spectrum [23:16]*/
25643 #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL
25644 #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
25645 #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK
25646 #define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000
25647 #define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0
25648 #define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU
25650 /*Step Size for Spread Spectrum [25:24]*/
25651 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL
25652 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
25653 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK
25654 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000
25655 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0
25656 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U
25658 /*Enable/Disable test mode force on SS step size*/
25659 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL
25660 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
25661 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK
25662 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000
25663 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4
25664 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U
25666 /*Enable/Disable test mode force on SS no of steps*/
25667 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL
25668 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
25669 #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK
25670 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000
25671 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5
25672 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U
25674 /*Step Size for Spread Spectrum [7:0]*/
25675 #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL
25676 #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
25677 #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK
25678 #define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000
25679 #define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0
25680 #define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU
25682 /*Step Size for Spread Spectrum [15:8]*/
25683 #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL
25684 #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
25685 #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK
25686 #define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000
25687 #define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0
25688 #define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU
25690 /*Step Size for Spread Spectrum [23:16]*/
25691 #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL
25692 #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
25693 #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK
25694 #define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000
25695 #define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0
25696 #define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU
25698 /*Step Size for Spread Spectrum [25:24]*/
25699 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL
25700 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
25701 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK
25702 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000
25703 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0
25704 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U
25706 /*Enable/Disable test mode force on SS step size*/
25707 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL
25708 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
25709 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK
25710 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000
25711 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4
25712 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U
25714 /*Enable/Disable test mode force on SS no of steps*/
25715 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL
25716 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
25717 #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK
25718 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000
25719 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5
25720 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U
25722 /*Step Size for Spread Spectrum [7:0]*/
25723 #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL
25724 #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
25725 #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK
25726 #define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000
25727 #define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0
25728 #define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU
25730 /*Step Size for Spread Spectrum [15:8]*/
25731 #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL
25732 #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
25733 #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK
25734 #define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000
25735 #define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0
25736 #define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU
25738 /*Step Size for Spread Spectrum [23:16]*/
25739 #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL
25740 #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
25741 #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK
25742 #define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000
25743 #define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0
25744 #define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU
25746 /*Step Size for Spread Spectrum [25:24]*/
25747 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL
25748 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
25749 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK
25750 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000
25751 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0
25752 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U
25754 /*Enable/Disable test mode force on SS step size*/
25755 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL
25756 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
25757 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK
25758 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000
25759 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4
25760 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U
25762 /*Enable/Disable test mode force on SS no of steps*/
25763 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL
25764 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
25765 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK
25766 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000
25767 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5
25768 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U
25770 /*Enable test mode forcing on enable Spread Spectrum*/
25771 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL
25772 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT
25773 #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK
25774 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL 0x00000000
25775 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT 7
25776 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK 0x00000080U
25778 /*Bypass Descrambler*/
25779 #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL
25780 #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT
25781 #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK
25782 #define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000
25783 #define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1
25784 #define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U
25786 /*Enable Bypass for <1> TM_DIG_CTRL_6*/
25787 #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL
25788 #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
25789 #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK
25790 #define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000
25791 #define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0
25792 #define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U
25794 /*Bypass scrambler signal*/
25795 #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL
25796 #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
25797 #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK
25798 #define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000
25799 #define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1
25800 #define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U
25802 /*Enable/disable scrambler bypass signal*/
25803 #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL
25804 #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
25805 #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK
25806 #define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000
25807 #define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0
25808 #define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U
25810 /*Enable test mode force on fractional mode enable*/
25811 #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL
25812 #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT
25813 #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK
25814 #define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL 0x00000000
25815 #define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT 6
25816 #define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK 0x00000040U
25818 /*Bypass 8b10b decoder*/
25819 #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL
25820 #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT
25821 #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK
25822 #define SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL 0x00000000
25823 #define SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT 3
25824 #define SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK 0x00000008U
25826 /*Enable Bypass for <3> TM_DIG_CTRL_6*/
25827 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL
25828 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT
25829 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK
25830 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL 0x00000000
25831 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT 2
25832 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK 0x00000004U
25834 /*Bypass Descrambler*/
25835 #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL
25836 #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT
25837 #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK
25838 #define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000
25839 #define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1
25840 #define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U
25842 /*Enable Bypass for <1> TM_DIG_CTRL_6*/
25843 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL
25844 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
25845 #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK
25846 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000
25847 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0
25848 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U
25850 /*Enable/disable encoder bypass signal*/
25851 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL
25852 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT
25853 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK
25854 #define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL 0x00000000
25855 #define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT 3
25856 #define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK 0x00000008U
25858 /*Bypass scrambler signal*/
25859 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL
25860 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
25861 #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK
25862 #define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000
25863 #define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1
25864 #define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U
25866 /*Enable/disable scrambler bypass signal*/
25867 #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL
25868 #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
25869 #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK
25870 #define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000
25871 #define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0
25872 #define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U
25874 /*PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY*/
25875 #undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_DEFVAL
25876 #undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT
25877 #undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK
25878 #define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_DEFVAL 0x00000001
25879 #define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT 4
25880 #define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK 0x000000F0U
25882 /*Spare- not used*/
25883 #undef SERDES_L0_TM_AUX_0_BIT_2_DEFVAL
25884 #undef SERDES_L0_TM_AUX_0_BIT_2_SHIFT
25885 #undef SERDES_L0_TM_AUX_0_BIT_2_MASK
25886 #define SERDES_L0_TM_AUX_0_BIT_2_DEFVAL 0x00000000
25887 #define SERDES_L0_TM_AUX_0_BIT_2_SHIFT 5
25888 #define SERDES_L0_TM_AUX_0_BIT_2_MASK 0x00000020U
25890 /*Spare- not used*/
25891 #undef SERDES_L2_TM_AUX_0_BIT_2_DEFVAL
25892 #undef SERDES_L2_TM_AUX_0_BIT_2_SHIFT
25893 #undef SERDES_L2_TM_AUX_0_BIT_2_MASK
25894 #define SERDES_L2_TM_AUX_0_BIT_2_DEFVAL 0x00000000
25895 #define SERDES_L2_TM_AUX_0_BIT_2_SHIFT 5
25896 #define SERDES_L2_TM_AUX_0_BIT_2_MASK 0x00000020U
25898 /*Enable Eye Surf*/
25899 #undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL
25900 #undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT
25901 #undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK
25902 #define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000
25903 #define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT 4
25904 #define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U
25906 /*Enable Eye Surf*/
25907 #undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL
25908 #undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT
25909 #undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK
25910 #define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000
25911 #define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT 4
25912 #define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U
25914 /*Enable Eye Surf*/
25915 #undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL
25916 #undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT
25917 #undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK
25918 #define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000
25919 #define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT 4
25920 #define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U
25922 /*Enable Eye Surf*/
25923 #undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL
25924 #undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT
25925 #undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK
25926 #define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000
25927 #define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT 4
25928 #define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U
25930 /*ILL calib counts BYPASSED with calcode bits*/
25931 #undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL
25932 #undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
25933 #undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK
25934 #define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000
25935 #define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7
25936 #define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U
25938 /*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
25939 #undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL
25940 #undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
25941 #undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK
25942 #define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000
25943 #define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0
25944 #define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU
25946 /*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
25947 #undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL
25948 #undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
25949 #undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK
25950 #define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000
25951 #define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0
25952 #define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU
25954 /*G1A pll ctr bypass value*/
25955 #undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL
25956 #undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
25957 #undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK
25958 #define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000
25959 #define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0
25960 #define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU
25962 /*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
25963 #undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL
25964 #undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
25965 #undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK
25966 #define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000
25967 #define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0
25968 #define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU
25970 /*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
25971 #undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL
25972 #undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
25973 #undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK
25974 #define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000
25975 #define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0
25976 #define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU
25978 /*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
25979 #undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL
25980 #undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
25981 #undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK
25982 #define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000
25983 #define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0
25984 #define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU
25986 /*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
25987 #undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL
25988 #undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
25989 #undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK
25990 #define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000
25991 #define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0
25992 #define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU
25994 /*ILL calibration code change wait time*/
25995 #undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL
25996 #undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
25997 #undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK
25998 #define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002
25999 #define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0
26000 #define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU
26002 /*IQ ILL polytrim bypass value*/
26003 #undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL
26004 #undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
26005 #undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK
26006 #define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000
26007 #define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0
26008 #define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU
26010 /*bypass IQ polytrim*/
26011 #undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL
26012 #undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
26013 #undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK
26014 #define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000
26015 #define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0
26016 #define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U
26018 /*E ILL polytrim bypass value*/
26019 #undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL
26020 #undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
26021 #undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK
26022 #define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000
26023 #define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0
26024 #define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU
26026 /*bypass E polytrim*/
26027 #undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL
26028 #undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
26029 #undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK
26030 #define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000
26031 #define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0
26032 #define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U
26034 /*ILL calib counts BYPASSED with calcode bits*/
26035 #undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL
26036 #undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
26037 #undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK
26038 #define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000
26039 #define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7
26040 #define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U
26042 /*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
26043 #undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL
26044 #undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
26045 #undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK
26046 #define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000
26047 #define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0
26048 #define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU
26050 /*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
26051 #undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL
26052 #undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
26053 #undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK
26054 #define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000
26055 #define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0
26056 #define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU
26058 /*G1A pll ctr bypass value*/
26059 #undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL
26060 #undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
26061 #undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK
26062 #define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000
26063 #define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0
26064 #define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU
26066 /*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
26067 #undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL
26068 #undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
26069 #undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK
26070 #define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000
26071 #define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0
26072 #define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU
26074 /*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
26075 #undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL
26076 #undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
26077 #undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK
26078 #define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000
26079 #define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0
26080 #define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU
26082 /*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
26083 #undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL
26084 #undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
26085 #undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK
26086 #define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000
26087 #define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0
26088 #define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU
26090 /*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
26091 #undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL
26092 #undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
26093 #undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK
26094 #define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000
26095 #define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0
26096 #define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU
26098 /*ILL calibration code change wait time*/
26099 #undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL
26100 #undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
26101 #undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK
26102 #define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002
26103 #define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0
26104 #define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU
26106 /*IQ ILL polytrim bypass value*/
26107 #undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL
26108 #undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
26109 #undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK
26110 #define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000
26111 #define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0
26112 #define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU
26114 /*bypass IQ polytrim*/
26115 #undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL
26116 #undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
26117 #undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK
26118 #define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000
26119 #define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0
26120 #define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U
26122 /*E ILL polytrim bypass value*/
26123 #undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL
26124 #undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
26125 #undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK
26126 #define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000
26127 #define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0
26128 #define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU
26130 /*bypass E polytrim*/
26131 #undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL
26132 #undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
26133 #undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK
26134 #define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000
26135 #define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0
26136 #define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U
26138 /*ILL calib counts BYPASSED with calcode bits*/
26139 #undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL
26140 #undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
26141 #undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK
26142 #define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000
26143 #define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7
26144 #define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U
26146 /*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
26147 #undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL
26148 #undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
26149 #undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK
26150 #define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000
26151 #define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0
26152 #define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU
26154 /*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
26155 #undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL
26156 #undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
26157 #undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK
26158 #define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000
26159 #define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0
26160 #define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU
26162 /*G1A pll ctr bypass value*/
26163 #undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL
26164 #undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
26165 #undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK
26166 #define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000
26167 #define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0
26168 #define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU
26170 /*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
26171 #undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL
26172 #undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
26173 #undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK
26174 #define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000
26175 #define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0
26176 #define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU
26178 /*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
26179 #undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL
26180 #undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
26181 #undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK
26182 #define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000
26183 #define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0
26184 #define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU
26186 /*G2A_PCIe1 PLL ctr bypass value*/
26187 #undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL
26188 #undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT
26189 #undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK
26190 #define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL 0x00000000
26191 #define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT 4
26192 #define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK 0x000000F0U
26194 /*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
26195 #undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL
26196 #undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
26197 #undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK
26198 #define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000
26199 #define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0
26200 #define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU
26202 /*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
26203 #undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL
26204 #undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
26205 #undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK
26206 #define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000
26207 #define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0
26208 #define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU
26210 /*ILL calibration code change wait time*/
26211 #undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL
26212 #undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
26213 #undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK
26214 #define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002
26215 #define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0
26216 #define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU
26218 /*IQ ILL polytrim bypass value*/
26219 #undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL
26220 #undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
26221 #undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK
26222 #define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000
26223 #define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0
26224 #define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU
26226 /*bypass IQ polytrim*/
26227 #undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL
26228 #undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
26229 #undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK
26230 #define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000
26231 #define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0
26232 #define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U
26234 /*E ILL polytrim bypass value*/
26235 #undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL
26236 #undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
26237 #undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK
26238 #define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000
26239 #define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0
26240 #define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU
26242 /*bypass E polytrim*/
26243 #undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL
26244 #undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
26245 #undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK
26246 #define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000
26247 #define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0
26248 #define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U
26250 /*pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20*/
26251 #undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL
26252 #undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT
26253 #undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK
26254 #define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL 0x00000000
26255 #define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT 0
26256 #define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK 0x00000003U
26258 /*CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001*/
26259 #undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL
26260 #undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
26261 #undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK
26262 #define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001
26263 #define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0
26264 #define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU
26266 /*Delay apb reset by specified amount*/
26267 #undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL
26268 #undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT
26269 #undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK
26270 #define SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
26271 #define SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT 0
26272 #define SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
26274 /*Enable Bypass for <7> of TM_ANA_BYPS_15*/
26275 #undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
26276 #undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
26277 #undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
26278 #define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
26279 #define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
26280 #define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
26282 /*Enable Bypass for <7> of TM_ANA_BYPS_12*/
26283 #undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
26284 #undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
26285 #undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
26286 #define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
26287 #define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
26288 #define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
26290 /*Delay apb reset by specified amount*/
26291 #undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL
26292 #undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT
26293 #undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK
26294 #define SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
26295 #define SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT 0
26296 #define SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
26298 /*Enable Bypass for <7> of TM_ANA_BYPS_15*/
26299 #undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
26300 #undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
26301 #undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
26302 #define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
26303 #define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
26304 #define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
26306 /*Enable Bypass for <7> of TM_ANA_BYPS_12*/
26307 #undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
26308 #undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
26309 #undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
26310 #define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
26311 #define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
26312 #define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
26314 /*Delay apb reset by specified amount*/
26315 #undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL
26316 #undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT
26317 #undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK
26318 #define SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
26319 #define SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT 0
26320 #define SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
26322 /*Enable Bypass for <7> of TM_ANA_BYPS_15*/
26323 #undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
26324 #undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
26325 #undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
26326 #define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
26327 #define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
26328 #define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
26330 /*Enable Bypass for <7> of TM_ANA_BYPS_12*/
26331 #undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
26332 #undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
26333 #undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
26334 #define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
26335 #define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
26336 #define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
26338 /*Delay apb reset by specified amount*/
26339 #undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL
26340 #undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT
26341 #undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK
26342 #define SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
26343 #define SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT 0
26344 #define SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
26346 /*Enable Bypass for <7> of TM_ANA_BYPS_15*/
26347 #undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
26348 #undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
26349 #undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
26350 #define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
26351 #define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
26352 #define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
26354 /*Enable Bypass for <7> of TM_ANA_BYPS_12*/
26355 #undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
26356 #undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
26357 #undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
26358 #define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
26359 #define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
26360 #define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
26362 /*Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse
26364 #undef SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL
26365 #undef SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT
26366 #undef SERDES_ICM_CFG0_L0_ICM_CFG_MASK
26367 #define SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL 0x00000000
26368 #define SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT 0
26369 #define SERDES_ICM_CFG0_L0_ICM_CFG_MASK 0x00000007U
26371 /*Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused
26373 #undef SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL
26374 #undef SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT
26375 #undef SERDES_ICM_CFG0_L1_ICM_CFG_MASK
26376 #define SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL 0x00000000
26377 #define SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT 4
26378 #define SERDES_ICM_CFG0_L1_ICM_CFG_MASK 0x00000070U
26380 /*Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused
26382 #undef SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL
26383 #undef SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT
26384 #undef SERDES_ICM_CFG1_L2_ICM_CFG_MASK
26385 #define SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL 0x00000000
26386 #define SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT 0
26387 #define SERDES_ICM_CFG1_L2_ICM_CFG_MASK 0x00000007U
26389 /*Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused
26391 #undef SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL
26392 #undef SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT
26393 #undef SERDES_ICM_CFG1_L3_ICM_CFG_MASK
26394 #define SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL 0x00000000
26395 #define SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT 4
26396 #define SERDES_ICM_CFG1_L3_ICM_CFG_MASK 0x00000070U
26398 /*Enable/disable DP post2 path*/
26399 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL
26400 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
26401 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK
26402 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000
26403 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT 5
26404 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK 0x00000020U
26406 /*Override enable/disable of DP post2 path*/
26407 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL
26408 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT
26409 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK
26410 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000
26411 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT 4
26412 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK 0x00000010U
26414 /*Override enable/disable of DP post1 path*/
26415 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL
26416 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT
26417 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK
26418 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL 0x00000000
26419 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT 2
26420 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK 0x00000004U
26422 /*Enable/disable DP main path*/
26423 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL
26424 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT
26425 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK
26426 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000
26427 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT 1
26428 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK 0x00000002U
26430 /*Override enable/disable of DP main path*/
26431 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL
26432 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT
26433 #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK
26434 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000
26435 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT 0
26436 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK 0x00000001U
26438 /*Test register force for enabling/disablign TX deemphasis bits <17:0>*/
26439 #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL
26440 #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
26441 #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK
26442 #define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000
26443 #define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0
26444 #define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U
26446 /*Test register force for enabling/disablign TX deemphasis bits <17:0>*/
26447 #undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL
26448 #undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
26449 #undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK
26450 #define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000
26451 #define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0
26452 #define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U
26454 /*FPHL FSM accumulate cycles*/
26455 #undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL
26456 #undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT
26457 #undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK
26458 #define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL 0x00000000
26459 #define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT 5
26460 #define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK 0x000000E0U
26462 /*FFL Phase0 int gain aka 2ol SD update rate*/
26463 #undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL
26464 #undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT
26465 #undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK
26466 #define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL 0x00000000
26467 #define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT 0
26468 #define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK 0x0000001FU
26470 /*FFL Phase0 prop gain aka 1ol SD update rate*/
26471 #undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL
26472 #undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT
26473 #undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK
26474 #define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL 0x00000000
26475 #define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT 0
26476 #define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK 0x0000001FU
26478 /*EQ stg 2 controls BYPASSED*/
26479 #undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL
26480 #undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT
26481 #undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK
26482 #define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL 0x00000000
26483 #define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT 5
26484 #define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK 0x00000020U
26486 /*EQ STG2 RL PROG*/
26487 #undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL
26488 #undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT
26489 #undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK
26490 #define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL 0x00000000
26491 #define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT 0
26492 #define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK 0x00000003U
26494 /*EQ stg 2 preamp mode val*/
26495 #undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL
26496 #undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT
26497 #undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK
26498 #define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL 0x00000000
26499 #define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT 2
26500 #define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK 0x00000004U
26502 /*Margining factor value*/
26503 #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL
26504 #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT
26505 #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK
26506 #define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL 0x00000000
26507 #define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT 0
26508 #define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK 0x0000001FU
26510 /*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/
26511 #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL
26512 #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
26513 #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK
26514 #define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002
26515 #define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0
26516 #define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU
26518 /*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/
26519 #undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL
26520 #undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
26521 #undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK
26522 #define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002
26523 #define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0
26524 #define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU
26525 #undef CRL_APB_RST_LPD_TOP_OFFSET
26526 #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
26527 #undef USB3_0_FPD_POWER_PRSNT_OFFSET
26528 #define USB3_0_FPD_POWER_PRSNT_OFFSET 0XFF9D0080
26529 #undef USB3_0_FPD_PIPE_CLK_OFFSET
26530 #define USB3_0_FPD_PIPE_CLK_OFFSET 0XFF9D007C
26531 #undef CRL_APB_RST_LPD_TOP_OFFSET
26532 #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
26533 #undef CRL_APB_RST_LPD_IOU0_OFFSET
26534 #define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230
26535 #undef SIOU_SATA_MISC_CTRL_OFFSET
26536 #define SIOU_SATA_MISC_CTRL_OFFSET 0XFD3D0100
26537 #undef CRF_APB_RST_FPD_TOP_OFFSET
26538 #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
26539 #undef CRF_APB_RST_FPD_TOP_OFFSET
26540 #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
26541 #undef CRF_APB_RST_FPD_TOP_OFFSET
26542 #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
26543 #undef DP_DP_PHY_RESET_OFFSET
26544 #define DP_DP_PHY_RESET_OFFSET 0XFD4A0200
26545 #undef DP_DP_TX_PHY_POWER_DOWN_OFFSET
26546 #define DP_DP_TX_PHY_POWER_DOWN_OFFSET 0XFD4A0238
26547 #undef USB3_0_XHCI_GUSB2PHYCFG_OFFSET
26548 #define USB3_0_XHCI_GUSB2PHYCFG_OFFSET 0XFE20C200
26549 #undef USB3_0_XHCI_GFLADJ_OFFSET
26550 #define USB3_0_XHCI_GFLADJ_OFFSET 0XFE20C630
26551 #undef PCIE_ATTRIB_ATTR_25_OFFSET
26552 #define PCIE_ATTRIB_ATTR_25_OFFSET 0XFD480064
26553 #undef PCIE_ATTRIB_ATTR_7_OFFSET
26554 #define PCIE_ATTRIB_ATTR_7_OFFSET 0XFD48001C
26555 #undef PCIE_ATTRIB_ATTR_8_OFFSET
26556 #define PCIE_ATTRIB_ATTR_8_OFFSET 0XFD480020
26557 #undef PCIE_ATTRIB_ATTR_9_OFFSET
26558 #define PCIE_ATTRIB_ATTR_9_OFFSET 0XFD480024
26559 #undef PCIE_ATTRIB_ATTR_10_OFFSET
26560 #define PCIE_ATTRIB_ATTR_10_OFFSET 0XFD480028
26561 #undef PCIE_ATTRIB_ATTR_11_OFFSET
26562 #define PCIE_ATTRIB_ATTR_11_OFFSET 0XFD48002C
26563 #undef PCIE_ATTRIB_ATTR_12_OFFSET
26564 #define PCIE_ATTRIB_ATTR_12_OFFSET 0XFD480030
26565 #undef PCIE_ATTRIB_ATTR_13_OFFSET
26566 #define PCIE_ATTRIB_ATTR_13_OFFSET 0XFD480034
26567 #undef PCIE_ATTRIB_ATTR_14_OFFSET
26568 #define PCIE_ATTRIB_ATTR_14_OFFSET 0XFD480038
26569 #undef PCIE_ATTRIB_ATTR_15_OFFSET
26570 #define PCIE_ATTRIB_ATTR_15_OFFSET 0XFD48003C
26571 #undef PCIE_ATTRIB_ATTR_16_OFFSET
26572 #define PCIE_ATTRIB_ATTR_16_OFFSET 0XFD480040
26573 #undef PCIE_ATTRIB_ATTR_17_OFFSET
26574 #define PCIE_ATTRIB_ATTR_17_OFFSET 0XFD480044
26575 #undef PCIE_ATTRIB_ATTR_18_OFFSET
26576 #define PCIE_ATTRIB_ATTR_18_OFFSET 0XFD480048
26577 #undef PCIE_ATTRIB_ATTR_27_OFFSET
26578 #define PCIE_ATTRIB_ATTR_27_OFFSET 0XFD48006C
26579 #undef PCIE_ATTRIB_ATTR_50_OFFSET
26580 #define PCIE_ATTRIB_ATTR_50_OFFSET 0XFD4800C8
26581 #undef PCIE_ATTRIB_ATTR_105_OFFSET
26582 #define PCIE_ATTRIB_ATTR_105_OFFSET 0XFD4801A4
26583 #undef PCIE_ATTRIB_ATTR_106_OFFSET
26584 #define PCIE_ATTRIB_ATTR_106_OFFSET 0XFD4801A8
26585 #undef PCIE_ATTRIB_ATTR_107_OFFSET
26586 #define PCIE_ATTRIB_ATTR_107_OFFSET 0XFD4801AC
26587 #undef PCIE_ATTRIB_ATTR_108_OFFSET
26588 #define PCIE_ATTRIB_ATTR_108_OFFSET 0XFD4801B0
26589 #undef PCIE_ATTRIB_ATTR_109_OFFSET
26590 #define PCIE_ATTRIB_ATTR_109_OFFSET 0XFD4801B4
26591 #undef PCIE_ATTRIB_ATTR_34_OFFSET
26592 #define PCIE_ATTRIB_ATTR_34_OFFSET 0XFD480088
26593 #undef PCIE_ATTRIB_ATTR_53_OFFSET
26594 #define PCIE_ATTRIB_ATTR_53_OFFSET 0XFD4800D4
26595 #undef PCIE_ATTRIB_ATTR_41_OFFSET
26596 #define PCIE_ATTRIB_ATTR_41_OFFSET 0XFD4800A4
26597 #undef PCIE_ATTRIB_ATTR_97_OFFSET
26598 #define PCIE_ATTRIB_ATTR_97_OFFSET 0XFD480184
26599 #undef PCIE_ATTRIB_ATTR_100_OFFSET
26600 #define PCIE_ATTRIB_ATTR_100_OFFSET 0XFD480190
26601 #undef PCIE_ATTRIB_ATTR_101_OFFSET
26602 #define PCIE_ATTRIB_ATTR_101_OFFSET 0XFD480194
26603 #undef PCIE_ATTRIB_ATTR_37_OFFSET
26604 #define PCIE_ATTRIB_ATTR_37_OFFSET 0XFD480094
26605 #undef PCIE_ATTRIB_ATTR_93_OFFSET
26606 #define PCIE_ATTRIB_ATTR_93_OFFSET 0XFD480174
26607 #undef PCIE_ATTRIB_ID_OFFSET
26608 #define PCIE_ATTRIB_ID_OFFSET 0XFD480200
26609 #undef PCIE_ATTRIB_SUBSYS_ID_OFFSET
26610 #define PCIE_ATTRIB_SUBSYS_ID_OFFSET 0XFD480204
26611 #undef PCIE_ATTRIB_REV_ID_OFFSET
26612 #define PCIE_ATTRIB_REV_ID_OFFSET 0XFD480208
26613 #undef PCIE_ATTRIB_ATTR_24_OFFSET
26614 #define PCIE_ATTRIB_ATTR_24_OFFSET 0XFD480060
26615 #undef PCIE_ATTRIB_ATTR_25_OFFSET
26616 #define PCIE_ATTRIB_ATTR_25_OFFSET 0XFD480064
26617 #undef PCIE_ATTRIB_ATTR_4_OFFSET
26618 #define PCIE_ATTRIB_ATTR_4_OFFSET 0XFD480010
26619 #undef PCIE_ATTRIB_ATTR_89_OFFSET
26620 #define PCIE_ATTRIB_ATTR_89_OFFSET 0XFD480164
26621 #undef PCIE_ATTRIB_ATTR_79_OFFSET
26622 #define PCIE_ATTRIB_ATTR_79_OFFSET 0XFD48013C
26623 #undef PCIE_ATTRIB_ATTR_43_OFFSET
26624 #define PCIE_ATTRIB_ATTR_43_OFFSET 0XFD4800AC
26625 #undef PCIE_ATTRIB_ATTR_48_OFFSET
26626 #define PCIE_ATTRIB_ATTR_48_OFFSET 0XFD4800C0
26627 #undef PCIE_ATTRIB_ATTR_46_OFFSET
26628 #define PCIE_ATTRIB_ATTR_46_OFFSET 0XFD4800B8
26629 #undef PCIE_ATTRIB_ATTR_47_OFFSET
26630 #define PCIE_ATTRIB_ATTR_47_OFFSET 0XFD4800BC
26631 #undef PCIE_ATTRIB_ATTR_44_OFFSET
26632 #define PCIE_ATTRIB_ATTR_44_OFFSET 0XFD4800B0
26633 #undef PCIE_ATTRIB_ATTR_45_OFFSET
26634 #define PCIE_ATTRIB_ATTR_45_OFFSET 0XFD4800B4
26635 #undef PCIE_ATTRIB_CB_OFFSET
26636 #define PCIE_ATTRIB_CB_OFFSET 0XFD48031C
26637 #undef PCIE_ATTRIB_ATTR_35_OFFSET
26638 #define PCIE_ATTRIB_ATTR_35_OFFSET 0XFD48008C
26639 #undef CRF_APB_RST_FPD_TOP_OFFSET
26640 #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
26641 #undef SATA_AHCI_VENDOR_PP2C_OFFSET
26642 #define SATA_AHCI_VENDOR_PP2C_OFFSET 0XFD0C00AC
26643 #undef SATA_AHCI_VENDOR_PP3C_OFFSET
26644 #define SATA_AHCI_VENDOR_PP3C_OFFSET 0XFD0C00B0
26645 #undef SATA_AHCI_VENDOR_PP4C_OFFSET
26646 #define SATA_AHCI_VENDOR_PP4C_OFFSET 0XFD0C00B4
26647 #undef SATA_AHCI_VENDOR_PP5C_OFFSET
26648 #define SATA_AHCI_VENDOR_PP5C_OFFSET 0XFD0C00B8
26650 /*USB 0 reset for control registers*/
26651 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL
26652 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
26653 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK
26654 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF
26655 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10
26656 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U
26658 /*This bit is used to choose between PIPE power present and 1'b1*/
26659 #undef USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL
26660 #undef USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT
26661 #undef USB3_0_FPD_POWER_PRSNT_OPTION_MASK
26662 #define USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL
26663 #define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT 0
26664 #define USB3_0_FPD_POWER_PRSNT_OPTION_MASK 0x00000001U
26666 /*This bit is used to choose between PIPE clock coming from SerDes and the suspend clk*/
26667 #undef USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL
26668 #undef USB3_0_FPD_PIPE_CLK_OPTION_SHIFT
26669 #undef USB3_0_FPD_PIPE_CLK_OPTION_MASK
26670 #define USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL
26671 #define USB3_0_FPD_PIPE_CLK_OPTION_SHIFT 0
26672 #define USB3_0_FPD_PIPE_CLK_OPTION_MASK 0x00000001U
26674 /*USB 0 sleep circuit reset*/
26675 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL
26676 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
26677 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK
26678 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF
26679 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8
26680 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U
26683 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL
26684 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
26685 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK
26686 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF
26687 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6
26688 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U
26691 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL
26692 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
26693 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK
26694 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F
26695 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3
26696 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U
26698 /*Sata PM clock control select*/
26699 #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL
26700 #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT
26701 #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK
26702 #define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL
26703 #define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT 0
26704 #define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK 0x00000003U
26706 /*Sata block level reset*/
26707 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL
26708 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
26709 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK
26710 #define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE
26711 #define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1
26712 #define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U
26714 /*PCIE config reset*/
26715 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL
26716 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
26717 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK
26718 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE
26719 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19
26720 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U
26722 /*PCIE bridge block level reset (AXI interface)*/
26723 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL
26724 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
26725 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK
26726 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE
26727 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18
26728 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U
26730 /*Display Port block level reset (includes DPDMA)*/
26731 #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL
26732 #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
26733 #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK
26734 #define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE
26735 #define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16
26736 #define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U
26738 /*Set to '1' to hold the GT in reset. Clear to release.*/
26739 #undef DP_DP_PHY_RESET_GT_RESET_DEFVAL
26740 #undef DP_DP_PHY_RESET_GT_RESET_SHIFT
26741 #undef DP_DP_PHY_RESET_GT_RESET_MASK
26742 #define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003
26743 #define DP_DP_PHY_RESET_GT_RESET_SHIFT 1
26744 #define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U
26746 /*Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] -
26747 ane0 Bits [3:2] - lane 1*/
26748 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL
26749 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
26750 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK
26751 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000
26752 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0
26753 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU
26755 /*USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to
26756 he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S
26757 C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level
26758 . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
26759 UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger
26760 alue. Note: This field is valid only in device mode.*/
26761 #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL
26762 #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT
26763 #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK
26764 #define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL 0x00000000
26765 #define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT 10
26766 #define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK 0x00003C00U
26768 /*Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio
26769 of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the
26770 time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de
26771 ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power
26772 off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur
26773 ng hibernation. - This bit is valid only in device mode.*/
26774 #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL
26775 #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT
26776 #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK
26777 #define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL 0x00000000
26778 #define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT 9
26779 #define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK 0x00000200U
26781 /*Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen
26782 _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre
26783 to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY.
26784 ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh
26785 n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma
26786 d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet
26788 #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL
26789 #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT
26790 #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK
26791 #define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL 0x00000000
26792 #define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT 8
26793 #define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK 0x00000100U
26795 /*USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P
26796 Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. -
26797 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte
26798 in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i
26799 active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.*/
26800 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL
26801 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT
26802 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK
26803 #define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL 0x00000000
26804 #define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 7
26805 #define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK 0x00000080U
26807 /*Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
26808 full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with
26809 ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
26810 B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.*/
26811 #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL
26812 #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT
26813 #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK
26814 #define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL 0x00000000
26815 #define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT 5
26816 #define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK 0x00000020U
26818 /*ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa
26819 e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons
26820 ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s
26821 lected through DWC_USB3_HSPHY_INTERFACE.*/
26822 #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL
26823 #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT
26824 #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK
26825 #define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL 0x00000000
26826 #define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT 4
26827 #define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK 0x00000010U
26829 /*PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a
26830 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same
26831 lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen
26832 ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I
26833 any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.*/
26834 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL
26835 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT
26836 #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK
26837 #define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL 0x00000000
26838 #define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT 3
26839 #define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK 0x00000008U
26841 /*HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by
26842 a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for
26843 dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta
26844 e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times.
26845 The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this
26846 ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH
26847 clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One
26848 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times*/
26849 #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL
26850 #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT
26851 #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK
26852 #define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL 0x00000000
26853 #define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT 0
26854 #define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK 0x00000007U
26856 /*This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register
26857 alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP
26858 _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF
26859 TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p
26860 riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d
26861 cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc
26862 uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ =
26863 ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P
26864 RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)*/
26865 #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL
26866 #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT
26867 #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK
26868 #define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL 0x00000000
26869 #define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 8
26870 #define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 0x003FFF00U
26872 /*If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root
26873 ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001*/
26874 #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL
26875 #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT
26876 #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK
26877 #define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL 0x00000905
26878 #define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT 9
26879 #define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK 0x00000200U
26881 /*Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
26882 ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
26883 Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
26884 erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator
26885 set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
26886 re size in bytes.; EP=0x0004; RP=0x0000*/
26887 #undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL
26888 #undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT
26889 #undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK
26890 #define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL
26891 #define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT 0
26892 #define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK 0x0000FFFFU
26894 /*Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
26895 ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
26896 Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
26897 erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator
26898 set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
26899 re size in bytes.; EP=0xFFF0; RP=0x0000*/
26900 #undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL
26901 #undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT
26902 #undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK
26903 #define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL
26904 #define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT 0
26905 #define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK 0x0000FFFFU
26907 /*Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if
26908 AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
26909 bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set
26910 o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
26911 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of
26912 '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
26913 ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/
26914 #undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL
26915 #undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT
26916 #undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK
26917 #define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL
26918 #define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT 0
26919 #define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK 0x0000FFFFU
26921 /*Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if
26922 AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
26923 bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set
26924 o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
26925 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of
26926 '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
26927 ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/
26928 #undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL
26929 #undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT
26930 #undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK
26931 #define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL
26932 #define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT 0
26933 #define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK 0x0000FFFFU
26935 /*For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
26936 AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
26937 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
26938 , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
26939 ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
26940 most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to
26941 . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
26942 ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF*/
26943 #undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL
26944 #undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT
26945 #undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK
26946 #define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL
26947 #define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT 0
26948 #define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK 0x0000FFFFU
26950 /*For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
26951 AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
26952 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
26953 , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
26954 ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
26955 most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to
26956 . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
26957 ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF*/
26958 #undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL
26959 #undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT
26960 #undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK
26961 #define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL
26962 #define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT 0
26963 #define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK 0x0000FFFFU
26965 /*For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
26966 AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
26967 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
26968 Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
26969 t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
26970 t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
26971 if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits
26972 f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
26973 bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/
26974 #undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL
26975 #undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT
26976 #undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK
26977 #define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL
26978 #define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT 0
26979 #define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK 0x0000FFFFU
26981 /*For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
26982 AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
26983 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
26984 Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
26985 t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
26986 t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
26987 if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits
26988 f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
26989 bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF*/
26990 #undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL
26991 #undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT
26992 #undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK
26993 #define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL
26994 #define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT 0
26995 #define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK 0x0000FFFFU
26997 /*For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
26998 AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
26999 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
27000 , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
27001 ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
27002 most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to
27003 . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
27004 ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0*/
27005 #undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL
27006 #undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT
27007 #undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK
27008 #define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL
27009 #define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT 0
27010 #define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK 0x0000FFFFU
27012 /*For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
27013 AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
27014 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
27015 , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
27016 ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
27017 most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to
27018 . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
27019 ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0*/
27020 #undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL
27021 #undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT
27022 #undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK
27023 #define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL
27024 #define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT 0
27025 #define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK 0x0000FFFFU
27027 /*For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
27028 AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
27029 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
27030 Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit
27031 refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
27032 R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] =
27033 refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in
27034 ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
27035 permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1*/
27036 #undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL
27037 #undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT
27038 #undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK
27039 #define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL
27040 #define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT 0
27041 #define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK 0x0000FFFFU
27043 /*For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
27044 AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
27045 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
27046 Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit
27047 refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
27048 R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] =
27049 refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in
27050 ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
27051 permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1*/
27052 #undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL
27053 #undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT
27054 #undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK
27055 #define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL
27056 #define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT 0
27057 #define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK 0x0000FFFFU
27059 /*Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred
27060 to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001*/
27061 #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL
27062 #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT
27063 #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK
27064 #define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL 0x00002138
27065 #define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT 8
27066 #define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK 0x00000700U
27068 /*Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1
27069 state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6
27070 32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000*/
27071 #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL
27072 #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT
27073 #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK
27074 #define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL 0x00002138
27075 #define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT 3
27076 #define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK 0x00000038U
27078 /*Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0
27079 00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw
27080 tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r
27081 gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004*/
27082 #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL
27083 #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT
27084 #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK
27085 #define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL 0x00009C02
27086 #define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT 4
27087 #define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK 0x000000F0U
27089 /*PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab
27090 lity.; EP=0x009C; RP=0x0000*/
27091 #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL
27092 #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT
27093 #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK
27094 #define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL 0x00009C02
27095 #define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT 8
27096 #define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK 0x0000FF00U
27098 /*Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l
27099 ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD*/
27100 #undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL
27101 #undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT
27102 #undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK
27103 #define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL
27104 #define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT 0
27105 #define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK 0x000007FFU
27107 /*Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non
27108 osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024*/
27109 #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL
27110 #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT
27111 #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK
27112 #define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL 0x00000248
27113 #define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT 0
27114 #define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK 0x0000007FU
27116 /*Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da
27117 a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and
27118 completion header credits must be <= 80; EP=0x0004; RP=0x000C*/
27119 #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL
27120 #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT
27121 #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK
27122 #define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL 0x00000248
27123 #define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT 7
27124 #define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK 0x00003F80U
27126 /*Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data
27127 redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support
27128 d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be
27129 less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018*/
27130 #undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL
27131 #undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT
27132 #undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK
27133 #define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL
27134 #define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT 0
27135 #define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK 0x000007FFU
27137 /*Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less
27138 han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5*/
27139 #undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL
27140 #undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT
27141 #undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK
27142 #define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL
27143 #define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT 0
27144 #define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK 0x000007FFU
27146 /*Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00
27148 #undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL
27149 #undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT
27150 #undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK
27151 #define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL 0x00007E04
27152 #define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT 15
27153 #define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK 0x00008000U
27155 /*Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001*/
27156 #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL
27157 #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT
27158 #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK
27159 #define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL 0x00007E04
27160 #define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT 14
27161 #define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK 0x00004000U
27163 /*Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER
27164 cap structure; EP=0x0003; RP=0x0003*/
27165 #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL
27166 #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT
27167 #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK
27168 #define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL 0x00007E04
27169 #define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT 12
27170 #define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK 0x00003000U
27172 /*Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n
27173 mber of brams configured for transmit; EP=0x001C; RP=0x001C*/
27174 #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL
27175 #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT
27176 #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK
27177 #define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL 0x00007E04
27178 #define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT 7
27179 #define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK 0x00000F80U
27181 /*Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post
27182 d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020*/
27183 #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL
27184 #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT
27185 #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK
27186 #define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL 0x00007E04
27187 #define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT 0
27188 #define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK 0x0000007FU
27190 /*Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit
27191 0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001*/
27192 #undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL
27193 #undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT
27194 #undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK
27195 #define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL 0x00000100
27196 #define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT 0
27197 #define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK 0x000000FFU
27199 /*PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil
27200 ty.; EP=0x0048; RP=0x0060*/
27201 #undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL
27202 #undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT
27203 #undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK
27204 #define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL 0x00003D48
27205 #define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT 0
27206 #define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK 0x000000FFU
27208 /*MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor
27209 to Cap structure; EP=0x0000; RP=0x0000*/
27210 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL
27211 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT
27212 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK
27213 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL 0x00000160
27214 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT 9
27215 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK 0x00000200U
27217 /*Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or
27218 he management port.; EP=0x0001; RP=0x0000*/
27219 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL
27220 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT
27221 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK
27222 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160
27223 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8
27224 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U
27226 /*MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi
27227 ity.; EP=0x0060; RP=0x0000*/
27228 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL
27229 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT
27230 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK
27231 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL 0x00000160
27232 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT 0
27233 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK 0x000000FFU
27235 /*Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or
27236 he management port.; EP=0x0001; RP=0x0000*/
27237 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL
27238 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT
27239 #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK
27240 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160
27241 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8
27242 #define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U
27244 /*Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004*/
27245 #undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL
27246 #undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT
27247 #undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK
27248 #define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL 0x00000104
27249 #define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT 0
27250 #define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK 0x0000003FU
27252 /*Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00
27254 #undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL
27255 #undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT
27256 #undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK
27257 #define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL 0x00000104
27258 #define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT 6
27259 #define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK 0x00000FC0U
27261 /*TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000*/
27262 #undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL
27263 #undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT
27264 #undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK
27265 #define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL 0x000000F0
27266 #define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT 6
27267 #define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK 0x00000040U
27269 /*Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message
27270 LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL,
27271 Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off;
27272 EP=0x0000; RP=0x07FF*/
27273 #undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL
27274 #undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT
27275 #undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK
27276 #define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL 0x00000000
27277 #define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT 5
27278 #define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK 0x0000FFE0U
27280 /*Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001*/
27281 #undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL
27282 #undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT
27283 #undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK
27284 #define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL 0x00000000
27285 #define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT 1
27286 #define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK 0x00000002U
27288 /*Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism.
27289 Required for Root.; EP=0x0000; RP=0x0001*/
27290 #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL
27291 #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT
27292 #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK
27293 #define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL 0x000009FF
27294 #define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT 9
27295 #define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK 0x00000200U
27297 /*Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
27298 gister.; EP=0x0001; RP=0x0001*/
27299 #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL
27300 #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT
27301 #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK
27302 #define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 0x000009FF
27303 #define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 14
27304 #define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 0x00004000U
27306 /*Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L
27307 _REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000*/
27308 #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL
27309 #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT
27310 #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK
27311 #define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL 0x00000000
27312 #define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT 15
27313 #define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK 0x00008000U
27315 /*Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY
27316 TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is
27317 4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000*/
27318 #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL
27319 #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT
27320 #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK
27321 #define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL 0x00000000
27322 #define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT 0
27323 #define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK 0x00007FFFU
27325 /*Device ID for the the PCIe Cap Structure Device ID field*/
27326 #undef PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL
27327 #undef PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT
27328 #undef PCIE_ATTRIB_ID_CFG_DEV_ID_MASK
27329 #define PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL 0x10EE7024
27330 #define PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT 0
27331 #define PCIE_ATTRIB_ID_CFG_DEV_ID_MASK 0x0000FFFFU
27333 /*Vendor ID for the PCIe Cap Structure Vendor ID field*/
27334 #undef PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL
27335 #undef PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT
27336 #undef PCIE_ATTRIB_ID_CFG_VEND_ID_MASK
27337 #define PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL 0x10EE7024
27338 #define PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT 16
27339 #define PCIE_ATTRIB_ID_CFG_VEND_ID_MASK 0xFFFF0000U
27341 /*Subsystem ID for the the PCIe Cap Structure Subsystem ID field*/
27342 #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL
27343 #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT
27344 #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK
27345 #define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL 0x10EE0007
27346 #define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT 0
27347 #define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK 0x0000FFFFU
27349 /*Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field*/
27350 #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL
27351 #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT
27352 #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK
27353 #define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL 0x10EE0007
27354 #define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT 16
27355 #define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK 0xFFFF0000U
27357 /*Revision ID for the the PCIe Cap Structure*/
27358 #undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL
27359 #undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT
27360 #undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK
27361 #define PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL
27362 #define PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT 0
27363 #define PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK 0x000000FFU
27365 /*Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
27367 #undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL
27368 #undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT
27369 #undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK
27370 #define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL
27371 #define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT 0
27372 #define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK 0x0000FFFFU
27374 /*Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
27376 #undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL
27377 #undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT
27378 #undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK
27379 #define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL 0x00000905
27380 #define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT 0
27381 #define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK 0x000000FFU
27383 /*INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001*/
27384 #undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL
27385 #undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT
27386 #undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK
27387 #define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL 0x00000905
27388 #define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT 8
27389 #define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK 0x00000100U
27391 /*Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or
27392 he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
27393 ges are sent if an error is detected).; EP=0x0001; RP=0x0001*/
27394 #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL
27395 #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT
27396 #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK
27397 #define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000
27398 #define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12
27399 #define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U
27401 /*Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or
27402 he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
27403 ges are sent if an error is detected).; EP=0x0001; RP=0x0001*/
27404 #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL
27405 #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT
27406 #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK
27407 #define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000
27408 #define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12
27409 #define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U
27411 /*VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP
27412 0x0140; RP=0x0140*/
27413 #undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL
27414 #undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT
27415 #undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK
27416 #define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL 0x00002281
27417 #define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT 1
27418 #define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK 0x00001FFEU
27420 /*CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000*/
27421 #undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL
27422 #undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT
27423 #undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK
27424 #define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL 0x00000000
27425 #define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT 5
27426 #define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK 0x00000020U
27428 /*Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o
27429 the management port.; EP=0x0001; RP=0x0000*/
27430 #undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL
27431 #undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT
27432 #undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK
27433 #define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL 0x00000100
27434 #define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT 8
27435 #define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK 0x00000100U
27437 /*MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note
27438 hat the core does not implement the table; that must be implemented in user logic.; EP=0x0003; RP=0x0000*/
27439 #undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL
27440 #undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT
27441 #undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK
27442 #define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL
27443 #define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT 0
27444 #define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK 0x000007FFU
27446 /*MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001;
27448 #undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL
27449 #undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT
27450 #undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK
27451 #define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL
27452 #define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0
27453 #define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x0000FFFFU
27455 /*MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0000;
27457 #undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL
27458 #undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT
27459 #undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK
27460 #define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL
27461 #define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0
27462 #define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x00001FFFU
27464 /*MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP
27465 0x0001; RP=0x0000*/
27466 #undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL
27467 #undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT
27468 #undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK
27469 #define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL
27470 #define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 0
27471 #define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFFFU
27473 /*MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP
27474 0x1000; RP=0x0000*/
27475 #undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL
27476 #undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT
27477 #undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK
27478 #define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL 0x00008000
27479 #define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 3
27480 #define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFF8U
27482 /*DT837748 Enable*/
27483 #undef PCIE_ATTRIB_CB_CB1_DEFVAL
27484 #undef PCIE_ATTRIB_CB_CB1_SHIFT
27485 #undef PCIE_ATTRIB_CB_CB1_MASK
27486 #define PCIE_ATTRIB_CB_CB1_DEFVAL 0x00000001
27487 #define PCIE_ATTRIB_CB_CB1_SHIFT 1
27488 #define PCIE_ATTRIB_CB_CB1_MASK 0x00000002U
27490 /*Active State PM Support. Indicates the level of active state power management supported by the selected PCI Express Link, enc
27491 ded as follows: 0 Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported.; EP=0x0001; RP=0x0001*/
27492 #undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL
27493 #undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT
27494 #undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK
27495 #define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL 0x00001FFD
27496 #define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT 12
27497 #define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK 0x00003000U
27499 /*PCIE control block level reset*/
27500 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL
27501 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
27502 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK
27503 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE
27504 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17
27505 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U
27507 /*Status Read value of PLL Lock*/
27508 #undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
27509 #undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
27510 #undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
27511 #define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
27512 #define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
27513 #define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
27514 #define SERDES_L0_PLL_STATUS_READ_1_OFFSET 0XFD4023E4
27516 /*Status Read value of PLL Lock*/
27517 #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
27518 #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
27519 #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
27520 #define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
27521 #define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
27522 #define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
27523 #define SERDES_L1_PLL_STATUS_READ_1_OFFSET 0XFD4063E4
27525 /*Status Read value of PLL Lock*/
27526 #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
27527 #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
27528 #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
27529 #define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
27530 #define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
27531 #define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
27532 #define SERDES_L2_PLL_STATUS_READ_1_OFFSET 0XFD40A3E4
27534 /*Status Read value of PLL Lock*/
27535 #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
27536 #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
27537 #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
27538 #define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
27539 #define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
27540 #define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
27541 #define SERDES_L3_PLL_STATUS_READ_1_OFFSET 0XFD40E3E4
27543 /*CIBGMN: COMINIT Burst Gap Minimum.*/
27544 #undef SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL
27545 #undef SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT
27546 #undef SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK
27547 #define SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL 0x28184D1B
27548 #define SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT 0
27549 #define SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK 0x000000FFU
27551 /*CIBGMX: COMINIT Burst Gap Maximum.*/
27552 #undef SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL
27553 #undef SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT
27554 #undef SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK
27555 #define SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL 0x28184D1B
27556 #define SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT 8
27557 #define SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK 0x0000FF00U
27559 /*CIBGN: COMINIT Burst Gap Nominal.*/
27560 #undef SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL
27561 #undef SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT
27562 #undef SATA_AHCI_VENDOR_PP2C_CIBGN_MASK
27563 #define SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL 0x28184D1B
27564 #define SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT 16
27565 #define SATA_AHCI_VENDOR_PP2C_CIBGN_MASK 0x00FF0000U
27567 /*CINMP: COMINIT Negate Minimum Period.*/
27568 #undef SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL
27569 #undef SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT
27570 #undef SATA_AHCI_VENDOR_PP2C_CINMP_MASK
27571 #define SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL 0x28184D1B
27572 #define SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT 24
27573 #define SATA_AHCI_VENDOR_PP2C_CINMP_MASK 0xFF000000U
27575 /*CWBGMN: COMWAKE Burst Gap Minimum.*/
27576 #undef SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL
27577 #undef SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT
27578 #undef SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK
27579 #define SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL 0x0E081906
27580 #define SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT 0
27581 #define SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK 0x000000FFU
27583 /*CWBGMX: COMWAKE Burst Gap Maximum.*/
27584 #undef SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL
27585 #undef SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT
27586 #undef SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK
27587 #define SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL 0x0E081906
27588 #define SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT 8
27589 #define SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK 0x0000FF00U
27591 /*CWBGN: COMWAKE Burst Gap Nominal.*/
27592 #undef SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL
27593 #undef SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT
27594 #undef SATA_AHCI_VENDOR_PP3C_CWBGN_MASK
27595 #define SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL 0x0E081906
27596 #define SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT 16
27597 #define SATA_AHCI_VENDOR_PP3C_CWBGN_MASK 0x00FF0000U
27599 /*CWNMP: COMWAKE Negate Minimum Period.*/
27600 #undef SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL
27601 #undef SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT
27602 #undef SATA_AHCI_VENDOR_PP3C_CWNMP_MASK
27603 #define SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL 0x0E081906
27604 #define SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT 24
27605 #define SATA_AHCI_VENDOR_PP3C_CWNMP_MASK 0xFF000000U
27607 /*BMX: COM Burst Maximum.*/
27608 #undef SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL
27609 #undef SATA_AHCI_VENDOR_PP4C_BMX_SHIFT
27610 #undef SATA_AHCI_VENDOR_PP4C_BMX_MASK
27611 #define SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL 0x064A0813
27612 #define SATA_AHCI_VENDOR_PP4C_BMX_SHIFT 0
27613 #define SATA_AHCI_VENDOR_PP4C_BMX_MASK 0x000000FFU
27615 /*BNM: COM Burst Nominal.*/
27616 #undef SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL
27617 #undef SATA_AHCI_VENDOR_PP4C_BNM_SHIFT
27618 #undef SATA_AHCI_VENDOR_PP4C_BNM_MASK
27619 #define SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL 0x064A0813
27620 #define SATA_AHCI_VENDOR_PP4C_BNM_SHIFT 8
27621 #define SATA_AHCI_VENDOR_PP4C_BNM_MASK 0x0000FF00U
27623 /*SFD: Signal Failure Detection, if the signal detection de-asserts for a time greater than this then the OOB detector will det
27624 rmine this is a line idle and cause the PhyInit state machine to exit the Phy Ready State. A value of zero disables the Signa
27625 Failure Detector. The value is based on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving a nominal time of
27626 500ns based on a 150MHz PMCLK.*/
27627 #undef SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL
27628 #undef SATA_AHCI_VENDOR_PP4C_SFD_SHIFT
27629 #undef SATA_AHCI_VENDOR_PP4C_SFD_MASK
27630 #define SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL 0x064A0813
27631 #define SATA_AHCI_VENDOR_PP4C_SFD_SHIFT 16
27632 #define SATA_AHCI_VENDOR_PP4C_SFD_MASK 0x00FF0000U
27634 /*PTST: Partial to Slumber timer value, specific delay the controller should apply while in partial before entering slumber. Th
27635 value is bases on the system clock divided by 128, total delay = (Sys Clock Period) * PTST * 128*/
27636 #undef SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL
27637 #undef SATA_AHCI_VENDOR_PP4C_PTST_SHIFT
27638 #undef SATA_AHCI_VENDOR_PP4C_PTST_MASK
27639 #define SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL 0x064A0813
27640 #define SATA_AHCI_VENDOR_PP4C_PTST_SHIFT 24
27641 #define SATA_AHCI_VENDOR_PP4C_PTST_MASK 0xFF000000U
27643 /*RIT: Retry Interval Timer. The calculated value divided by two, the lower digit of precision is not needed.*/
27644 #undef SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL
27645 #undef SATA_AHCI_VENDOR_PP5C_RIT_SHIFT
27646 #undef SATA_AHCI_VENDOR_PP5C_RIT_MASK
27647 #define SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL 0x3FFC96A4
27648 #define SATA_AHCI_VENDOR_PP5C_RIT_SHIFT 0
27649 #define SATA_AHCI_VENDOR_PP5C_RIT_MASK 0x000FFFFFU
27651 /*RCT: Rate Change Timer, a value based on the 54.2us for which a SATA device will transmit at a fixed rate ALIGNp after OOB ha
27652 completed, for a fast SERDES it is suggested that this value be 54.2us / 4*/
27653 #undef SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL
27654 #undef SATA_AHCI_VENDOR_PP5C_RCT_SHIFT
27655 #undef SATA_AHCI_VENDOR_PP5C_RCT_MASK
27656 #define SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL 0x3FFC96A4
27657 #define SATA_AHCI_VENDOR_PP5C_RCT_SHIFT 20
27658 #define SATA_AHCI_VENDOR_PP5C_RCT_MASK 0xFFF00000U
27659 #undef CRL_APB_RST_LPD_TOP_OFFSET
27660 #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
27661 #undef CRL_APB_RST_LPD_IOU0_OFFSET
27662 #define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230
27663 #undef CRF_APB_RST_FPD_TOP_OFFSET
27664 #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
27665 #undef CRF_APB_RST_FPD_TOP_OFFSET
27666 #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
27667 #undef DP_DP_TX_PHY_POWER_DOWN_OFFSET
27668 #define DP_DP_TX_PHY_POWER_DOWN_OFFSET 0XFD4A0238
27669 #undef DP_DP_PHY_RESET_OFFSET
27670 #define DP_DP_PHY_RESET_OFFSET 0XFD4A0200
27671 #undef CRF_APB_RST_FPD_TOP_OFFSET
27672 #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
27674 /*USB 0 reset for control registers*/
27675 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL
27676 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
27677 #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK
27678 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF
27679 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10
27680 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U
27682 /*USB 0 sleep circuit reset*/
27683 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL
27684 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
27685 #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK
27686 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF
27687 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8
27688 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U
27691 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL
27692 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
27693 #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK
27694 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF
27695 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6
27696 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U
27699 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL
27700 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
27701 #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK
27702 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F
27703 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3
27704 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U
27706 /*Sata block level reset*/
27707 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL
27708 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
27709 #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK
27710 #define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE
27711 #define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1
27712 #define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U
27714 /*PCIE config reset*/
27715 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL
27716 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
27717 #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK
27718 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE
27719 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19
27720 #define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U
27722 /*PCIE control block level reset*/
27723 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL
27724 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
27725 #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK
27726 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE
27727 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17
27728 #define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U
27730 /*PCIE bridge block level reset (AXI interface)*/
27731 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL
27732 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
27733 #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK
27734 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE
27735 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18
27736 #define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U
27738 /*Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] -
27739 ane0 Bits [3:2] - lane 1*/
27740 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL
27741 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
27742 #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK
27743 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000
27744 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0
27745 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU
27747 /*Set to '1' to hold the GT in reset. Clear to release.*/
27748 #undef DP_DP_PHY_RESET_GT_RESET_DEFVAL
27749 #undef DP_DP_PHY_RESET_GT_RESET_SHIFT
27750 #undef DP_DP_PHY_RESET_GT_RESET_MASK
27751 #define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003
27752 #define DP_DP_PHY_RESET_GT_RESET_SHIFT 1
27753 #define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U
27755 /*Display Port block level reset (includes DPDMA)*/
27756 #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL
27757 #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
27758 #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK
27759 #define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE
27760 #define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16
27761 #define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U
27762 #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET
27763 #define PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET 0XFFD80118
27764 #undef PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET
27765 #define PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET 0XFFD80120
27767 /*Power-up Request Interrupt Enable for PL*/
27768 #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL
27769 #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT
27770 #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK
27771 #define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL 0x00000000
27772 #define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT 23
27773 #define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK 0x00800000U
27775 /*Power-up Request Trigger for PL*/
27776 #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL
27777 #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT
27778 #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK
27779 #define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL 0x00000000
27780 #define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT 23
27781 #define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK 0x00800000U
27783 /*Power-up Request Status for PL*/
27784 #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL
27785 #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT
27786 #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK
27787 #define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL 0x00000000
27788 #define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT 23
27789 #define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK 0x00800000U
27790 #define PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET 0XFFD80110
27791 #undef GPIO_MASK_DATA_5_MSW_OFFSET
27792 #define GPIO_MASK_DATA_5_MSW_OFFSET 0XFF0A002C
27793 #undef GPIO_DIRM_5_OFFSET
27794 #define GPIO_DIRM_5_OFFSET 0XFF0A0344
27795 #undef GPIO_OEN_5_OFFSET
27796 #define GPIO_OEN_5_OFFSET 0XFF0A0348
27797 #undef GPIO_DATA_5_OFFSET
27798 #define GPIO_DATA_5_OFFSET 0XFF0A0054
27799 #undef GPIO_DATA_5_OFFSET
27800 #define GPIO_DATA_5_OFFSET 0XFF0A0054
27801 #undef GPIO_DATA_5_OFFSET
27802 #define GPIO_DATA_5_OFFSET 0XFF0A0054
27804 /*Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]*/
27805 #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL
27806 #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT
27807 #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK
27808 #define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL 0x00000000
27809 #define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT 16
27810 #define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK 0xFFFF0000U
27812 /*Operation is the same as DIRM_0[DIRECTION_0]*/
27813 #undef GPIO_DIRM_5_DIRECTION_5_DEFVAL
27814 #undef GPIO_DIRM_5_DIRECTION_5_SHIFT
27815 #undef GPIO_DIRM_5_DIRECTION_5_MASK
27816 #define GPIO_DIRM_5_DIRECTION_5_DEFVAL
27817 #define GPIO_DIRM_5_DIRECTION_5_SHIFT 0
27818 #define GPIO_DIRM_5_DIRECTION_5_MASK 0xFFFFFFFFU
27820 /*Operation is the same as OEN_0[OP_ENABLE_0]*/
27821 #undef GPIO_OEN_5_OP_ENABLE_5_DEFVAL
27822 #undef GPIO_OEN_5_OP_ENABLE_5_SHIFT
27823 #undef GPIO_OEN_5_OP_ENABLE_5_MASK
27824 #define GPIO_OEN_5_OP_ENABLE_5_DEFVAL
27825 #define GPIO_OEN_5_OP_ENABLE_5_SHIFT 0
27826 #define GPIO_OEN_5_OP_ENABLE_5_MASK 0xFFFFFFFFU
27829 #undef GPIO_DATA_5_DATA_5_DEFVAL
27830 #undef GPIO_DATA_5_DATA_5_SHIFT
27831 #undef GPIO_DATA_5_DATA_5_MASK
27832 #define GPIO_DATA_5_DATA_5_DEFVAL
27833 #define GPIO_DATA_5_DATA_5_SHIFT 0
27834 #define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU
27837 #undef GPIO_DATA_5_DATA_5_DEFVAL
27838 #undef GPIO_DATA_5_DATA_5_SHIFT
27839 #undef GPIO_DATA_5_DATA_5_MASK
27840 #define GPIO_DATA_5_DATA_5_DEFVAL
27841 #define GPIO_DATA_5_DATA_5_SHIFT 0
27842 #define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU
27845 #undef GPIO_DATA_5_DATA_5_DEFVAL
27846 #undef GPIO_DATA_5_DATA_5_SHIFT
27847 #undef GPIO_DATA_5_DATA_5_MASK
27848 #define GPIO_DATA_5_DATA_5_DEFVAL
27849 #define GPIO_DATA_5_DATA_5_SHIFT 0
27850 #define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU
27855 unsigned long psu_ps_pl_isolation_removal_data();
27856 unsigned long psu_ps_pl_reset_config_data();
27857 int psu_protection();
27858 int psu_fpd_protection();
27859 int psu_ocm_protection();
27860 int psu_ddr_protection();
27861 int psu_lpd_protection();
27862 int psu_protection_lock();
27863 unsigned long psu_apply_master_tz();