git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.c

   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
   4 *
   5 *  This program is free software; you can redistribute it and/or modify
   6 *  it under the terms of the GNU General Public License as published by
   7 *  the Free Software Foundation; either version 2 of the License, or
   8 *  (at your option) any later version.
   9 *
  10 *  This program is distributed in the hope that it will be useful,
  11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 *  GNU General Public License for more details.
  14 *
  15 *  You should have received a copy of the GNU General Public License along
  16 *  with this program; if not, see <http://www.gnu.org/licenses/>
  17 *
  18 *
  19 ******************************************************************************/
  20
  21 #include <xil_io.h>
  22 #include <sleep.h>
  23 #include "psu_init_gpl.h"
  24
  25 int mask_pollOnValue(u32 add , u32 mask, u32 value );
  26
  27 int mask_poll(u32 add , u32 mask );
  28
  29 void mask_delay(u32 delay);
  30
  31 u32 mask_read(u32 add , u32 mask );
  32
  33 static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned long val)
  34 {
  35         unsigned long RegVal = 0x0;
  36         RegVal = Xil_In32 (offset);
  37         RegVal &= ~(mask);
  38         RegVal |= (val & mask);
  39         Xil_Out32 (offset, RegVal);
  40 }
  41
  42         void prog_reg (unsigned long addr, unsigned long mask, unsigned long shift, unsigned long value) {
  43             int rdata =0;
  44             rdata  = Xil_In32(addr);
  45             rdata  = rdata & (~mask);
  46             rdata  = rdata | (value << shift);
  47             Xil_Out32(addr,rdata);
  48             }
  49
  50 unsigned long psu_pll_init_data() {
  51                 // : RPLL INIT
  52                 /*Register : RPLL_CFG @ 0XFF5E0034</p>
  53
  54                 PLL loop filter resistor control
  55                 PSU_CRL_APB_RPLL_CFG_RES                                                        0x2
  56
  57                 PLL charge pump control
  58                 PSU_CRL_APB_RPLL_CFG_CP                                                         0x3
  59
  60                 PLL loop filter high frequency capacitor control
  61                 PSU_CRL_APB_RPLL_CFG_LFHF                                                       0x3
  62
  63                 Lock circuit counter setting
  64                 PSU_CRL_APB_RPLL_CFG_LOCK_CNT                                                   0x258
  65
  66                 Lock circuit configuration settings for lock windowsize
  67                 PSU_CRL_APB_RPLL_CFG_LOCK_DLY                                                   0x3f
  68
  69                 Helper data. Values are to be looked up in a table from Data Sheet
  70                 (OFFSET, MASK, VALUE)      (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C62U)
  71                 RegMask = (CRL_APB_RPLL_CFG_RES_MASK | CRL_APB_RPLL_CFG_CP_MASK | CRL_APB_RPLL_CFG_LFHF_MASK | CRL_APB_RPLL_CFG_LOCK_CNT_MASK | CRL_APB_RPLL_CFG_LOCK_DLY_MASK |  0 );
  72
  73                 RegVal = ((0x00000002U << CRL_APB_RPLL_CFG_RES_SHIFT
  74                         | 0x00000003U << CRL_APB_RPLL_CFG_CP_SHIFT
  75                         | 0x00000003U << CRL_APB_RPLL_CFG_LFHF_SHIFT
  76                         | 0x00000258U << CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT
  77                         | 0x0000003FU << CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT
  78                         |  0 ) & RegMask); */
  79                 PSU_Mask_Write (CRL_APB_RPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U);
  80         /*############################################################################################################################ */
  81
  82                 // : UPDATE FB_DIV
  83                 /*Register : RPLL_CTRL @ 0XFF5E0030</p>
  84
  85                 Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
  86                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
  87                 PSU_CRL_APB_RPLL_CTRL_PRE_SRC                                                   0x0
  88
  89                 The integer portion of the feedback divider to the PLL
  90                 PSU_CRL_APB_RPLL_CTRL_FBDIV                                                     0x48
  91
  92                 This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
  93                 PSU_CRL_APB_RPLL_CTRL_DIV2                                                      0x1
  94
  95                 PLL Basic Control
  96                 (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00717F00U ,0x00014800U)
  97                 RegMask = (CRL_APB_RPLL_CTRL_PRE_SRC_MASK | CRL_APB_RPLL_CTRL_FBDIV_MASK | CRL_APB_RPLL_CTRL_DIV2_MASK |  0 );
  98
  99                 RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT
 100                         | 0x00000048U << CRL_APB_RPLL_CTRL_FBDIV_SHIFT
 101                         | 0x00000001U << CRL_APB_RPLL_CTRL_DIV2_SHIFT
 102                         |  0 ) & RegMask); */
 103                 PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00717F00U ,0x00014800U);
 104         /*############################################################################################################################ */
 105
 106                 // : BY PASS PLL
 107                 /*Register : RPLL_CTRL @ 0XFF5E0030</p>
 108
 109                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 110                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 111                 PSU_CRL_APB_RPLL_CTRL_BYPASS                                                    1
 112
 113                 PLL Basic Control
 114                 (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000008U ,0x00000008U)
 115                 RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK |  0 );
 116
 117                 RegVal = ((0x00000001U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT
 118                         |  0 ) & RegMask); */
 119                 PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
 120         /*############################################################################################################################ */
 121
 122                 // : ASSERT RESET
 123                 /*Register : RPLL_CTRL @ 0XFF5E0030</p>
 124
 125                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 126                 PSU_CRL_APB_RPLL_CTRL_RESET                                                     1
 127
 128                 PLL Basic Control
 129                 (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000001U ,0x00000001U)
 130                 RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK |  0 );
 131
 132                 RegVal = ((0x00000001U << CRL_APB_RPLL_CTRL_RESET_SHIFT
 133                         |  0 ) & RegMask); */
 134                 PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
 135         /*############################################################################################################################ */
 136
 137                 // : DEASSERT RESET
 138                 /*Register : RPLL_CTRL @ 0XFF5E0030</p>
 139
 140                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 141                 PSU_CRL_APB_RPLL_CTRL_RESET                                                     0
 142
 143                 PLL Basic Control
 144                 (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000001U ,0x00000000U)
 145                 RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK |  0 );
 146
 147                 RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_RESET_SHIFT
 148                         |  0 ) & RegMask); */
 149                 PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
 150         /*############################################################################################################################ */
 151
 152                 // : CHECK PLL STATUS
 153                 /*Register : PLL_STATUS @ 0XFF5E0040</p>
 154
 155                 RPLL is locked
 156                 PSU_CRL_APB_PLL_STATUS_RPLL_LOCK                                                1
 157                 (OFFSET, MASK, VALUE)      (0XFF5E0040, 0x00000002U ,0x00000002U)  */
 158                 mask_poll(CRL_APB_PLL_STATUS_OFFSET,0x00000002U);
 159
 160         /*############################################################################################################################ */
 161
 162                 // : REMOVE PLL BY PASS
 163                 /*Register : RPLL_CTRL @ 0XFF5E0030</p>
 164
 165                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 166                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 167                 PSU_CRL_APB_RPLL_CTRL_BYPASS                                                    0
 168
 169                 PLL Basic Control
 170                 (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000008U ,0x00000000U)
 171                 RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK |  0 );
 172
 173                 RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT
 174                         |  0 ) & RegMask); */
 175                 PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
 176         /*############################################################################################################################ */
 177
 178                 /*Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048</p>
 179
 180                 Divisor value for this clock.
 181                 PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0                                           0x3
 182
 183                 Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
 184                 (OFFSET, MASK, VALUE)      (0XFF5E0048, 0x00003F00U ,0x00000300U)
 185                 RegMask = (CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK |  0 );
 186
 187                 RegVal = ((0x00000003U << CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
 188                         |  0 ) & RegMask); */
 189                 PSU_Mask_Write (CRL_APB_RPLL_TO_FPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
 190         /*############################################################################################################################ */
 191
 192                 // : RPLL FRAC CFG
 193                 /*Register : RPLL_FRAC_CFG @ 0XFF5E0038</p>
 194
 195                 Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 196                  mode and uses DATA of this register for the fractional portion of the feedback divider.
 197                 PSU_CRL_APB_RPLL_FRAC_CFG_ENABLED                                               0x0
 198
 199                 Fractional value for the Feedback value.
 200                 PSU_CRL_APB_RPLL_FRAC_CFG_DATA                                                  0x0
 201
 202                 Fractional control for the PLL
 203                 (OFFSET, MASK, VALUE)      (0XFF5E0038, 0x8000FFFFU ,0x00000000U)
 204                 RegMask = (CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK | CRL_APB_RPLL_FRAC_CFG_DATA_MASK |  0 );
 205
 206                 RegVal = ((0x00000000U << CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT
 207                         | 0x00000000U << CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT
 208                         |  0 ) & RegMask); */
 209                 PSU_Mask_Write (CRL_APB_RPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U);
 210         /*############################################################################################################################ */
 211
 212                 // : IOPLL INIT
 213                 /*Register : IOPLL_CFG @ 0XFF5E0024</p>
 214
 215                 PLL loop filter resistor control
 216                 PSU_CRL_APB_IOPLL_CFG_RES                                                       0xc
 217
 218                 PLL charge pump control
 219                 PSU_CRL_APB_IOPLL_CFG_CP                                                        0x3
 220
 221                 PLL loop filter high frequency capacitor control
 222                 PSU_CRL_APB_IOPLL_CFG_LFHF                                                      0x3
 223
 224                 Lock circuit counter setting
 225                 PSU_CRL_APB_IOPLL_CFG_LOCK_CNT                                                  0x339
 226
 227                 Lock circuit configuration settings for lock windowsize
 228                 PSU_CRL_APB_IOPLL_CFG_LOCK_DLY                                                  0x3f
 229
 230                 Helper data. Values are to be looked up in a table from Data Sheet
 231                 (OFFSET, MASK, VALUE)      (0XFF5E0024, 0xFE7FEDEFU ,0x7E672C6CU)
 232                 RegMask = (CRL_APB_IOPLL_CFG_RES_MASK | CRL_APB_IOPLL_CFG_CP_MASK | CRL_APB_IOPLL_CFG_LFHF_MASK | CRL_APB_IOPLL_CFG_LOCK_CNT_MASK | CRL_APB_IOPLL_CFG_LOCK_DLY_MASK |  0 );
 233
 234                 RegVal = ((0x0000000CU << CRL_APB_IOPLL_CFG_RES_SHIFT
 235                         | 0x00000003U << CRL_APB_IOPLL_CFG_CP_SHIFT
 236                         | 0x00000003U << CRL_APB_IOPLL_CFG_LFHF_SHIFT
 237                         | 0x00000339U << CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT
 238                         | 0x0000003FU << CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT
 239                         |  0 ) & RegMask); */
 240                 PSU_Mask_Write (CRL_APB_IOPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E672C6CU);
 241         /*############################################################################################################################ */
 242
 243                 // : UPDATE FB_DIV
 244                 /*Register : IOPLL_CTRL @ 0XFF5E0020</p>
 245
 246                 Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 247                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
 248                 PSU_CRL_APB_IOPLL_CTRL_PRE_SRC                                                  0x0
 249
 250                 The integer portion of the feedback divider to the PLL
 251                 PSU_CRL_APB_IOPLL_CTRL_FBDIV                                                    0x2d
 252
 253                 This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
 254                 PSU_CRL_APB_IOPLL_CTRL_DIV2                                                     0x0
 255
 256                 PLL Basic Control
 257                 (OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00717F00U ,0x00002D00U)
 258                 RegMask = (CRL_APB_IOPLL_CTRL_PRE_SRC_MASK | CRL_APB_IOPLL_CTRL_FBDIV_MASK | CRL_APB_IOPLL_CTRL_DIV2_MASK |  0 );
 259
 260                 RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT
 261                         | 0x0000002DU << CRL_APB_IOPLL_CTRL_FBDIV_SHIFT
 262                         | 0x00000000U << CRL_APB_IOPLL_CTRL_DIV2_SHIFT
 263                         |  0 ) & RegMask); */
 264                 PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00717F00U ,0x00002D00U);
 265         /*############################################################################################################################ */
 266
 267                 // : BY PASS PLL
 268                 /*Register : IOPLL_CTRL @ 0XFF5E0020</p>
 269
 270                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 271                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 272                 PSU_CRL_APB_IOPLL_CTRL_BYPASS                                                   1
 273
 274                 PLL Basic Control
 275                 (OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000008U ,0x00000008U)
 276                 RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK |  0 );
 277
 278                 RegVal = ((0x00000001U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
 279                         |  0 ) & RegMask); */
 280                 PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
 281         /*############################################################################################################################ */
 282
 283                 // : ASSERT RESET
 284                 /*Register : IOPLL_CTRL @ 0XFF5E0020</p>
 285
 286                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 287                 PSU_CRL_APB_IOPLL_CTRL_RESET                                                    1
 288
 289                 PLL Basic Control
 290                 (OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000001U ,0x00000001U)
 291                 RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK |  0 );
 292
 293                 RegVal = ((0x00000001U << CRL_APB_IOPLL_CTRL_RESET_SHIFT
 294                         |  0 ) & RegMask); */
 295                 PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
 296         /*############################################################################################################################ */
 297
 298                 // : DEASSERT RESET
 299                 /*Register : IOPLL_CTRL @ 0XFF5E0020</p>
 300
 301                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 302                 PSU_CRL_APB_IOPLL_CTRL_RESET                                                    0
 303
 304                 PLL Basic Control
 305                 (OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000001U ,0x00000000U)
 306                 RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK |  0 );
 307
 308                 RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_RESET_SHIFT
 309                         |  0 ) & RegMask); */
 310                 PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
 311         /*############################################################################################################################ */
 312
 313                 // : CHECK PLL STATUS
 314                 /*Register : PLL_STATUS @ 0XFF5E0040</p>
 315
 316                 IOPLL is locked
 317                 PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK                                               1
 318                 (OFFSET, MASK, VALUE)      (0XFF5E0040, 0x00000001U ,0x00000001U)  */
 319                 mask_poll(CRL_APB_PLL_STATUS_OFFSET,0x00000001U);
 320
 321         /*############################################################################################################################ */
 322
 323                 // : REMOVE PLL BY PASS
 324                 /*Register : IOPLL_CTRL @ 0XFF5E0020</p>
 325
 326                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 327                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 328                 PSU_CRL_APB_IOPLL_CTRL_BYPASS                                                   0
 329
 330                 PLL Basic Control
 331                 (OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000008U ,0x00000000U)
 332                 RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK |  0 );
 333
 334                 RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
 335                         |  0 ) & RegMask); */
 336                 PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
 337         /*############################################################################################################################ */
 338
 339                 /*Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044</p>
 340
 341                 Divisor value for this clock.
 342                 PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0                                          0x3
 343
 344                 Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
 345                 (OFFSET, MASK, VALUE)      (0XFF5E0044, 0x00003F00U ,0x00000300U)
 346                 RegMask = (CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK |  0 );
 347
 348                 RegVal = ((0x00000003U << CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
 349                         |  0 ) & RegMask); */
 350                 PSU_Mask_Write (CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
 351         /*############################################################################################################################ */
 352
 353                 // : IOPLL FRAC CFG
 354                 /*Register : IOPLL_FRAC_CFG @ 0XFF5E0028</p>
 355
 356                 Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 357                  mode and uses DATA of this register for the fractional portion of the feedback divider.
 358                 PSU_CRL_APB_IOPLL_FRAC_CFG_ENABLED                                              0x0
 359
 360                 Fractional value for the Feedback value.
 361                 PSU_CRL_APB_IOPLL_FRAC_CFG_DATA                                                 0x0
 362
 363                 Fractional control for the PLL
 364                 (OFFSET, MASK, VALUE)      (0XFF5E0028, 0x8000FFFFU ,0x00000000U)
 365                 RegMask = (CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK | CRL_APB_IOPLL_FRAC_CFG_DATA_MASK |  0 );
 366
 367                 RegVal = ((0x00000000U << CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT
 368                         | 0x00000000U << CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT
 369                         |  0 ) & RegMask); */
 370                 PSU_Mask_Write (CRL_APB_IOPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U);
 371         /*############################################################################################################################ */
 372
 373                 // : APU_PLL INIT
 374                 /*Register : APLL_CFG @ 0XFD1A0024</p>
 375
 376                 PLL loop filter resistor control
 377                 PSU_CRF_APB_APLL_CFG_RES                                                        0x2
 378
 379                 PLL charge pump control
 380                 PSU_CRF_APB_APLL_CFG_CP                                                         0x3
 381
 382                 PLL loop filter high frequency capacitor control
 383                 PSU_CRF_APB_APLL_CFG_LFHF                                                       0x3
 384
 385                 Lock circuit counter setting
 386                 PSU_CRF_APB_APLL_CFG_LOCK_CNT                                                   0x258
 387
 388                 Lock circuit configuration settings for lock windowsize
 389                 PSU_CRF_APB_APLL_CFG_LOCK_DLY                                                   0x3f
 390
 391                 Helper data. Values are to be looked up in a table from Data Sheet
 392                 (OFFSET, MASK, VALUE)      (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U)
 393                 RegMask = (CRF_APB_APLL_CFG_RES_MASK | CRF_APB_APLL_CFG_CP_MASK | CRF_APB_APLL_CFG_LFHF_MASK | CRF_APB_APLL_CFG_LOCK_CNT_MASK | CRF_APB_APLL_CFG_LOCK_DLY_MASK |  0 );
 394
 395                 RegVal = ((0x00000002U << CRF_APB_APLL_CFG_RES_SHIFT
 396                         | 0x00000003U << CRF_APB_APLL_CFG_CP_SHIFT
 397                         | 0x00000003U << CRF_APB_APLL_CFG_LFHF_SHIFT
 398                         | 0x00000258U << CRF_APB_APLL_CFG_LOCK_CNT_SHIFT
 399                         | 0x0000003FU << CRF_APB_APLL_CFG_LOCK_DLY_SHIFT
 400                         |  0 ) & RegMask); */
 401                 PSU_Mask_Write (CRF_APB_APLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U);
 402         /*############################################################################################################################ */
 403
 404                 // : UPDATE FB_DIV
 405                 /*Register : APLL_CTRL @ 0XFD1A0020</p>
 406
 407                 Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 408                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
 409                 PSU_CRF_APB_APLL_CTRL_PRE_SRC                                                   0x0
 410
 411                 The integer portion of the feedback divider to the PLL
 412                 PSU_CRF_APB_APLL_CTRL_FBDIV                                                     0x42
 413
 414                 This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
 415                 PSU_CRF_APB_APLL_CTRL_DIV2                                                      0x1
 416
 417                 PLL Basic Control
 418                 (OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00717F00U ,0x00014200U)
 419                 RegMask = (CRF_APB_APLL_CTRL_PRE_SRC_MASK | CRF_APB_APLL_CTRL_FBDIV_MASK | CRF_APB_APLL_CTRL_DIV2_MASK |  0 );
 420
 421                 RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_PRE_SRC_SHIFT
 422                         | 0x00000042U << CRF_APB_APLL_CTRL_FBDIV_SHIFT
 423                         | 0x00000001U << CRF_APB_APLL_CTRL_DIV2_SHIFT
 424                         |  0 ) & RegMask); */
 425                 PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00717F00U ,0x00014200U);
 426         /*############################################################################################################################ */
 427
 428                 // : BY PASS PLL
 429                 /*Register : APLL_CTRL @ 0XFD1A0020</p>
 430
 431                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 432                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 433                 PSU_CRF_APB_APLL_CTRL_BYPASS                                                    1
 434
 435                 PLL Basic Control
 436                 (OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000008U ,0x00000008U)
 437                 RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK |  0 );
 438
 439                 RegVal = ((0x00000001U << CRF_APB_APLL_CTRL_BYPASS_SHIFT
 440                         |  0 ) & RegMask); */
 441                 PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
 442         /*############################################################################################################################ */
 443
 444                 // : ASSERT RESET
 445                 /*Register : APLL_CTRL @ 0XFD1A0020</p>
 446
 447                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 448                 PSU_CRF_APB_APLL_CTRL_RESET                                                     1
 449
 450                 PLL Basic Control
 451                 (OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000001U ,0x00000001U)
 452                 RegMask = (CRF_APB_APLL_CTRL_RESET_MASK |  0 );
 453
 454                 RegVal = ((0x00000001U << CRF_APB_APLL_CTRL_RESET_SHIFT
 455                         |  0 ) & RegMask); */
 456                 PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
 457         /*############################################################################################################################ */
 458
 459                 // : DEASSERT RESET
 460                 /*Register : APLL_CTRL @ 0XFD1A0020</p>
 461
 462                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 463                 PSU_CRF_APB_APLL_CTRL_RESET                                                     0
 464
 465                 PLL Basic Control
 466                 (OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000001U ,0x00000000U)
 467                 RegMask = (CRF_APB_APLL_CTRL_RESET_MASK |  0 );
 468
 469                 RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_RESET_SHIFT
 470                         |  0 ) & RegMask); */
 471                 PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
 472         /*############################################################################################################################ */
 473
 474                 // : CHECK PLL STATUS
 475                 /*Register : PLL_STATUS @ 0XFD1A0044</p>
 476
 477                 APLL is locked
 478                 PSU_CRF_APB_PLL_STATUS_APLL_LOCK                                                1
 479                 (OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000001U ,0x00000001U)  */
 480                 mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000001U);
 481
 482         /*############################################################################################################################ */
 483
 484                 // : REMOVE PLL BY PASS
 485                 /*Register : APLL_CTRL @ 0XFD1A0020</p>
 486
 487                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 488                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 489                 PSU_CRF_APB_APLL_CTRL_BYPASS                                                    0
 490
 491                 PLL Basic Control
 492                 (OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000008U ,0x00000000U)
 493                 RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK |  0 );
 494
 495                 RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_BYPASS_SHIFT
 496                         |  0 ) & RegMask); */
 497                 PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
 498         /*############################################################################################################################ */
 499
 500                 /*Register : APLL_TO_LPD_CTRL @ 0XFD1A0048</p>
 501
 502                 Divisor value for this clock.
 503                 PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0                                           0x3
 504
 505                 Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes.
 506                 (OFFSET, MASK, VALUE)      (0XFD1A0048, 0x00003F00U ,0x00000300U)
 507                 RegMask = (CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );
 508
 509                 RegVal = ((0x00000003U << CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT
 510                         |  0 ) & RegMask); */
 511                 PSU_Mask_Write (CRF_APB_APLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
 512         /*############################################################################################################################ */
 513
 514                 // : APLL FRAC CFG
 515                 /*Register : APLL_FRAC_CFG @ 0XFD1A0028</p>
 516
 517                 Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 518                  mode and uses DATA of this register for the fractional portion of the feedback divider.
 519                 PSU_CRF_APB_APLL_FRAC_CFG_ENABLED                                               0x0
 520
 521                 Fractional value for the Feedback value.
 522                 PSU_CRF_APB_APLL_FRAC_CFG_DATA                                                  0x0
 523
 524                 Fractional control for the PLL
 525                 (OFFSET, MASK, VALUE)      (0XFD1A0028, 0x8000FFFFU ,0x00000000U)
 526                 RegMask = (CRF_APB_APLL_FRAC_CFG_ENABLED_MASK | CRF_APB_APLL_FRAC_CFG_DATA_MASK |  0 );
 527
 528                 RegVal = ((0x00000000U << CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT
 529                         | 0x00000000U << CRF_APB_APLL_FRAC_CFG_DATA_SHIFT
 530                         |  0 ) & RegMask); */
 531                 PSU_Mask_Write (CRF_APB_APLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U);
 532         /*############################################################################################################################ */
 533
 534                 // : DDR_PLL INIT
 535                 /*Register : DPLL_CFG @ 0XFD1A0030</p>
 536
 537                 PLL loop filter resistor control
 538                 PSU_CRF_APB_DPLL_CFG_RES                                                        0x2
 539
 540                 PLL charge pump control
 541                 PSU_CRF_APB_DPLL_CFG_CP                                                         0x3
 542
 543                 PLL loop filter high frequency capacitor control
 544                 PSU_CRF_APB_DPLL_CFG_LFHF                                                       0x3
 545
 546                 Lock circuit counter setting
 547                 PSU_CRF_APB_DPLL_CFG_LOCK_CNT                                                   0x258
 548
 549                 Lock circuit configuration settings for lock windowsize
 550                 PSU_CRF_APB_DPLL_CFG_LOCK_DLY                                                   0x3f
 551
 552                 Helper data. Values are to be looked up in a table from Data Sheet
 553                 (OFFSET, MASK, VALUE)      (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U)
 554                 RegMask = (CRF_APB_DPLL_CFG_RES_MASK | CRF_APB_DPLL_CFG_CP_MASK | CRF_APB_DPLL_CFG_LFHF_MASK | CRF_APB_DPLL_CFG_LOCK_CNT_MASK | CRF_APB_DPLL_CFG_LOCK_DLY_MASK |  0 );
 555
 556                 RegVal = ((0x00000002U << CRF_APB_DPLL_CFG_RES_SHIFT
 557                         | 0x00000003U << CRF_APB_DPLL_CFG_CP_SHIFT
 558                         | 0x00000003U << CRF_APB_DPLL_CFG_LFHF_SHIFT
 559                         | 0x00000258U << CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT
 560                         | 0x0000003FU << CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT
 561                         |  0 ) & RegMask); */
 562                 PSU_Mask_Write (CRF_APB_DPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U);
 563         /*############################################################################################################################ */
 564
 565                 // : UPDATE FB_DIV
 566                 /*Register : DPLL_CTRL @ 0XFD1A002C</p>
 567
 568                 Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 569                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
 570                 PSU_CRF_APB_DPLL_CTRL_PRE_SRC                                                   0x0
 571
 572                 The integer portion of the feedback divider to the PLL
 573                 PSU_CRF_APB_DPLL_CTRL_FBDIV                                                     0x40
 574
 575                 This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
 576                 PSU_CRF_APB_DPLL_CTRL_DIV2                                                      0x1
 577
 578                 PLL Basic Control
 579                 (OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00717F00U ,0x00014000U)
 580                 RegMask = (CRF_APB_DPLL_CTRL_PRE_SRC_MASK | CRF_APB_DPLL_CTRL_FBDIV_MASK | CRF_APB_DPLL_CTRL_DIV2_MASK |  0 );
 581
 582                 RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT
 583                         | 0x00000040U << CRF_APB_DPLL_CTRL_FBDIV_SHIFT
 584                         | 0x00000001U << CRF_APB_DPLL_CTRL_DIV2_SHIFT
 585                         |  0 ) & RegMask); */
 586                 PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00717F00U ,0x00014000U);
 587         /*############################################################################################################################ */
 588
 589                 // : BY PASS PLL
 590                 /*Register : DPLL_CTRL @ 0XFD1A002C</p>
 591
 592                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 593                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 594                 PSU_CRF_APB_DPLL_CTRL_BYPASS                                                    1
 595
 596                 PLL Basic Control
 597                 (OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000008U ,0x00000008U)
 598                 RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK |  0 );
 599
 600                 RegVal = ((0x00000001U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT
 601                         |  0 ) & RegMask); */
 602                 PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
 603         /*############################################################################################################################ */
 604
 605                 // : ASSERT RESET
 606                 /*Register : DPLL_CTRL @ 0XFD1A002C</p>
 607
 608                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 609                 PSU_CRF_APB_DPLL_CTRL_RESET                                                     1
 610
 611                 PLL Basic Control
 612                 (OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000001U ,0x00000001U)
 613                 RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK |  0 );
 614
 615                 RegVal = ((0x00000001U << CRF_APB_DPLL_CTRL_RESET_SHIFT
 616                         |  0 ) & RegMask); */
 617                 PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
 618         /*############################################################################################################################ */
 619
 620                 // : DEASSERT RESET
 621                 /*Register : DPLL_CTRL @ 0XFD1A002C</p>
 622
 623                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 624                 PSU_CRF_APB_DPLL_CTRL_RESET                                                     0
 625
 626                 PLL Basic Control
 627                 (OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000001U ,0x00000000U)
 628                 RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK |  0 );
 629
 630                 RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_RESET_SHIFT
 631                         |  0 ) & RegMask); */
 632                 PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
 633         /*############################################################################################################################ */
 634
 635                 // : CHECK PLL STATUS
 636                 /*Register : PLL_STATUS @ 0XFD1A0044</p>
 637
 638                 DPLL is locked
 639                 PSU_CRF_APB_PLL_STATUS_DPLL_LOCK                                                1
 640                 (OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000002U ,0x00000002U)  */
 641                 mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000002U);
 642
 643         /*############################################################################################################################ */
 644
 645                 // : REMOVE PLL BY PASS
 646                 /*Register : DPLL_CTRL @ 0XFD1A002C</p>
 647
 648                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 649                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 650                 PSU_CRF_APB_DPLL_CTRL_BYPASS                                                    0
 651
 652                 PLL Basic Control
 653                 (OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000008U ,0x00000000U)
 654                 RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK |  0 );
 655
 656                 RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT
 657                         |  0 ) & RegMask); */
 658                 PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
 659         /*############################################################################################################################ */
 660
 661                 /*Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C</p>
 662
 663                 Divisor value for this clock.
 664                 PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0                                           0x3
 665
 666                 Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes.
 667                 (OFFSET, MASK, VALUE)      (0XFD1A004C, 0x00003F00U ,0x00000300U)
 668                 RegMask = (CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );
 669
 670                 RegVal = ((0x00000003U << CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
 671                         |  0 ) & RegMask); */
 672                 PSU_Mask_Write (CRF_APB_DPLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
 673         /*############################################################################################################################ */
 674
 675                 // : DPLL FRAC CFG
 676                 /*Register : DPLL_FRAC_CFG @ 0XFD1A0034</p>
 677
 678                 Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 679                  mode and uses DATA of this register for the fractional portion of the feedback divider.
 680                 PSU_CRF_APB_DPLL_FRAC_CFG_ENABLED                                               0x0
 681
 682                 Fractional value for the Feedback value.
 683                 PSU_CRF_APB_DPLL_FRAC_CFG_DATA                                                  0x0
 684
 685                 Fractional control for the PLL
 686                 (OFFSET, MASK, VALUE)      (0XFD1A0034, 0x8000FFFFU ,0x00000000U)
 687                 RegMask = (CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK | CRF_APB_DPLL_FRAC_CFG_DATA_MASK |  0 );
 688
 689                 RegVal = ((0x00000000U << CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT
 690                         | 0x00000000U << CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT
 691                         |  0 ) & RegMask); */
 692                 PSU_Mask_Write (CRF_APB_DPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U);
 693         /*############################################################################################################################ */
 694
 695                 // : VIDEO_PLL INIT
 696                 /*Register : VPLL_CFG @ 0XFD1A003C</p>
 697
 698                 PLL loop filter resistor control
 699                 PSU_CRF_APB_VPLL_CFG_RES                                                        0x2
 700
 701                 PLL charge pump control
 702                 PSU_CRF_APB_VPLL_CFG_CP                                                         0x3
 703
 704                 PLL loop filter high frequency capacitor control
 705                 PSU_CRF_APB_VPLL_CFG_LFHF                                                       0x3
 706
 707                 Lock circuit counter setting
 708                 PSU_CRF_APB_VPLL_CFG_LOCK_CNT                                                   0x28a
 709
 710                 Lock circuit configuration settings for lock windowsize
 711                 PSU_CRF_APB_VPLL_CFG_LOCK_DLY                                                   0x3f
 712
 713                 Helper data. Values are to be looked up in a table from Data Sheet
 714                 (OFFSET, MASK, VALUE)      (0XFD1A003C, 0xFE7FEDEFU ,0x7E514C62U)
 715                 RegMask = (CRF_APB_VPLL_CFG_RES_MASK | CRF_APB_VPLL_CFG_CP_MASK | CRF_APB_VPLL_CFG_LFHF_MASK | CRF_APB_VPLL_CFG_LOCK_CNT_MASK | CRF_APB_VPLL_CFG_LOCK_DLY_MASK |  0 );
 716
 717                 RegVal = ((0x00000002U << CRF_APB_VPLL_CFG_RES_SHIFT
 718                         | 0x00000003U << CRF_APB_VPLL_CFG_CP_SHIFT
 719                         | 0x00000003U << CRF_APB_VPLL_CFG_LFHF_SHIFT
 720                         | 0x0000028AU << CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT
 721                         | 0x0000003FU << CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT
 722                         |  0 ) & RegMask); */
 723                 PSU_Mask_Write (CRF_APB_VPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E514C62U);
 724         /*############################################################################################################################ */
 725
 726                 // : UPDATE FB_DIV
 727                 /*Register : VPLL_CTRL @ 0XFD1A0038</p>
 728
 729                 Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 730                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
 731                 PSU_CRF_APB_VPLL_CTRL_PRE_SRC                                                   0x0
 732
 733                 The integer portion of the feedback divider to the PLL
 734                 PSU_CRF_APB_VPLL_CTRL_FBDIV                                                     0x39
 735
 736                 This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
 737                 PSU_CRF_APB_VPLL_CTRL_DIV2                                                      0x1
 738
 739                 PLL Basic Control
 740                 (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00717F00U ,0x00013900U)
 741                 RegMask = (CRF_APB_VPLL_CTRL_PRE_SRC_MASK | CRF_APB_VPLL_CTRL_FBDIV_MASK | CRF_APB_VPLL_CTRL_DIV2_MASK |  0 );
 742
 743                 RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT
 744                         | 0x00000039U << CRF_APB_VPLL_CTRL_FBDIV_SHIFT
 745                         | 0x00000001U << CRF_APB_VPLL_CTRL_DIV2_SHIFT
 746                         |  0 ) & RegMask); */
 747                 PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00717F00U ,0x00013900U);
 748         /*############################################################################################################################ */
 749
 750                 // : BY PASS PLL
 751                 /*Register : VPLL_CTRL @ 0XFD1A0038</p>
 752
 753                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 754                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 755                 PSU_CRF_APB_VPLL_CTRL_BYPASS                                                    1
 756
 757                 PLL Basic Control
 758                 (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000008U ,0x00000008U)
 759                 RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK |  0 );
 760
 761                 RegVal = ((0x00000001U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT
 762                         |  0 ) & RegMask); */
 763                 PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
 764         /*############################################################################################################################ */
 765
 766                 // : ASSERT RESET
 767                 /*Register : VPLL_CTRL @ 0XFD1A0038</p>
 768
 769                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 770                 PSU_CRF_APB_VPLL_CTRL_RESET                                                     1
 771
 772                 PLL Basic Control
 773                 (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000001U ,0x00000001U)
 774                 RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK |  0 );
 775
 776                 RegVal = ((0x00000001U << CRF_APB_VPLL_CTRL_RESET_SHIFT
 777                         |  0 ) & RegMask); */
 778                 PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
 779         /*############################################################################################################################ */
 780
 781                 // : DEASSERT RESET
 782                 /*Register : VPLL_CTRL @ 0XFD1A0038</p>
 783
 784                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 785                 PSU_CRF_APB_VPLL_CTRL_RESET                                                     0
 786
 787                 PLL Basic Control
 788                 (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000001U ,0x00000000U)
 789                 RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK |  0 );
 790
 791                 RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_RESET_SHIFT
 792                         |  0 ) & RegMask); */
 793                 PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
 794         /*############################################################################################################################ */
 795
 796                 // : CHECK PLL STATUS
 797                 /*Register : PLL_STATUS @ 0XFD1A0044</p>
 798
 799                 VPLL is locked
 800                 PSU_CRF_APB_PLL_STATUS_VPLL_LOCK                                                1
 801                 (OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000004U ,0x00000004U)  */
 802                 mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000004U);
 803
 804         /*############################################################################################################################ */
 805
 806                 // : REMOVE PLL BY PASS
 807                 /*Register : VPLL_CTRL @ 0XFD1A0038</p>
 808
 809                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 810                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 811                 PSU_CRF_APB_VPLL_CTRL_BYPASS                                                    0
 812
 813                 PLL Basic Control
 814                 (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000008U ,0x00000000U)
 815                 RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK |  0 );
 816
 817                 RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT
 818                         |  0 ) & RegMask); */
 819                 PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
 820         /*############################################################################################################################ */
 821
 822                 /*Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050</p>
 823
 824                 Divisor value for this clock.
 825                 PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0                                           0x3
 826
 827                 Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes.
 828                 (OFFSET, MASK, VALUE)      (0XFD1A0050, 0x00003F00U ,0x00000300U)
 829                 RegMask = (CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );
 830
 831                 RegVal = ((0x00000003U << CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
 832                         |  0 ) & RegMask); */
 833                 PSU_Mask_Write (CRF_APB_VPLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
 834         /*############################################################################################################################ */
 835
 836                 // : VIDEO FRAC CFG
 837                 /*Register : VPLL_FRAC_CFG @ 0XFD1A0040</p>
 838
 839                 Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 840                  mode and uses DATA of this register for the fractional portion of the feedback divider.
 841                 PSU_CRF_APB_VPLL_FRAC_CFG_ENABLED                                               0x1
 842
 843                 Fractional value for the Feedback value.
 844                 PSU_CRF_APB_VPLL_FRAC_CFG_DATA                                                  0x820c
 845
 846                 Fractional control for the PLL
 847                 (OFFSET, MASK, VALUE)      (0XFD1A0040, 0x8000FFFFU ,0x8000820CU)
 848                 RegMask = (CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK | CRF_APB_VPLL_FRAC_CFG_DATA_MASK |  0 );
 849
 850                 RegVal = ((0x00000001U << CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT
 851                         | 0x0000820CU << CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT
 852                         |  0 ) & RegMask); */
 853                 PSU_Mask_Write (CRF_APB_VPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x8000820CU);
 854         /*############################################################################################################################ */
 855
 856
 857   return 1;
 858 }
 859 unsigned long psu_clock_init_data() {
 860                 // : CLOCK CONTROL SLCR REGISTER
 861                 /*Register : GEM3_REF_CTRL @ 0XFF5E005C</p>
 862
 863                 Clock active for the RX channel
 864                 PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT                                             0x1
 865
 866                 Clock active signal. Switch to 0 to disable the clock
 867                 PSU_CRL_APB_GEM3_REF_CTRL_CLKACT                                                0x1
 868
 869                 6 bit divider
 870                 PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1                                              0x1
 871
 872                 6 bit divider
 873                 PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0                                              0xc
 874
 875                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
 876                 clock. This is not usually an issue, but designers must be aware.)
 877                 PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL                                                0x0
 878
 879                 This register controls this reference clock
 880                 (OFFSET, MASK, VALUE)      (0XFF5E005C, 0x063F3F07U ,0x06010C00U)
 881                 RegMask = (CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK |  0 );
 882
 883                 RegVal = ((0x00000001U << CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT
 884                         | 0x00000001U << CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT
 885                         | 0x00000001U << CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT
 886                         | 0x0000000CU << CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT
 887                         | 0x00000000U << CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT
 888                         |  0 ) & RegMask); */
 889                 PSU_Mask_Write (CRL_APB_GEM3_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010C00U);
 890         /*############################################################################################################################ */
 891
 892                 /*Register : USB0_BUS_REF_CTRL @ 0XFF5E0060</p>
 893
 894                 Clock active signal. Switch to 0 to disable the clock
 895                 PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT                                            0x1
 896
 897                 6 bit divider
 898                 PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1                                          0x1
 899
 900                 6 bit divider
 901                 PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0                                          0x6
 902
 903                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
 904                 clock. This is not usually an issue, but designers must be aware.)
 905                 PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL                                            0x0
 906
 907                 This register controls this reference clock
 908                 (OFFSET, MASK, VALUE)      (0XFF5E0060, 0x023F3F07U ,0x02010600U)
 909                 RegMask = (CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK |  0 );
 910
 911                 RegVal = ((0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT
 912                         | 0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT
 913                         | 0x00000006U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT
 914                         | 0x00000000U << CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT
 915                         |  0 ) & RegMask); */
 916                 PSU_Mask_Write (CRL_APB_USB0_BUS_REF_CTRL_OFFSET ,0x023F3F07U ,0x02010600U);
 917         /*############################################################################################################################ */
 918
 919                 /*Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C</p>
 920
 921                 Clock active signal. Switch to 0 to disable the clock
 922                 PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT                                           0x1
 923
 924                 6 bit divider
 925                 PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1                                         0xf
 926
 927                 6 bit divider
 928                 PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0                                         0x5
 929
 930                 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
 931                 clock. This is not usually an issue, but designers must be aware.)
 932                 PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL                                           0x0
 933
 934                 This register controls this reference clock
 935                 (OFFSET, MASK, VALUE)      (0XFF5E004C, 0x023F3F07U ,0x020F0500U)
 936                 RegMask = (CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK |  0 );
 937
 938                 RegVal = ((0x00000001U << CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT
 939                         | 0x0000000FU << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT
 940                         | 0x00000005U << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT
 941                         | 0x00000000U << CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT
 942                         |  0 ) & RegMask); */
 943                 PSU_Mask_Write (CRL_APB_USB3_DUAL_REF_CTRL_OFFSET ,0x023F3F07U ,0x020F0500U);
 944         /*############################################################################################################################ */
 945
 946                 /*Register : QSPI_REF_CTRL @ 0XFF5E0068</p>
 947
 948                 Clock active signal. Switch to 0 to disable the clock
 949                 PSU_CRL_APB_QSPI_REF_CTRL_CLKACT                                                0x1
 950
 951                 6 bit divider
 952                 PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1                                              0x1
 953
 954                 6 bit divider
 955                 PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0                                              0xc
 956
 957                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
 958                 clock. This is not usually an issue, but designers must be aware.)
 959                 PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL                                                0x0
 960
 961                 This register controls this reference clock
 962                 (OFFSET, MASK, VALUE)      (0XFF5E0068, 0x013F3F07U ,0x01010C00U)
 963                 RegMask = (CRL_APB_QSPI_REF_CTRL_CLKACT_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK | CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK |  0 );
 964
 965                 RegVal = ((0x00000001U << CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT
 966                         | 0x00000001U << CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT
 967                         | 0x0000000CU << CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT
 968                         | 0x00000000U << CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT
 969                         |  0 ) & RegMask); */
 970                 PSU_Mask_Write (CRL_APB_QSPI_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010C00U);
 971         /*############################################################################################################################ */
 972
 973                 /*Register : SDIO1_REF_CTRL @ 0XFF5E0070</p>
 974
 975                 Clock active signal. Switch to 0 to disable the clock
 976                 PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT                                               0x1
 977
 978                 6 bit divider
 979                 PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1                                             0x1
 980
 981                 6 bit divider
 982                 PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0                                             0x6
 983
 984                 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
 985                 clock. This is not usually an issue, but designers must be aware.)
 986                 PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL                                               0x2
 987
 988                 This register controls this reference clock
 989                 (OFFSET, MASK, VALUE)      (0XFF5E0070, 0x013F3F07U ,0x01010602U)
 990                 RegMask = (CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK | CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK |  0 );
 991
 992                 RegVal = ((0x00000001U << CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT
 993                         | 0x00000001U << CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT
 994                         | 0x00000006U << CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT
 995                         | 0x00000002U << CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT
 996                         |  0 ) & RegMask); */
 997                 PSU_Mask_Write (CRL_APB_SDIO1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010602U);
 998         /*############################################################################################################################ */
 999
1000                 /*Register : SDIO_CLK_CTRL @ 0XFF18030C</p>
1001
1002                 MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76]
1003                 PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL                                     0
1004
1005                 SoC Debug Clock Control
1006                 (OFFSET, MASK, VALUE)      (0XFF18030C, 0x00020000U ,0x00000000U)
1007                 RegMask = (IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK |  0 );
1008
1009                 RegVal = ((0x00000000U << IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT
1010                         |  0 ) & RegMask); */
1011                 PSU_Mask_Write (IOU_SLCR_SDIO_CLK_CTRL_OFFSET ,0x00020000U ,0x00000000U);
1012         /*############################################################################################################################ */
1013
1014                 /*Register : UART0_REF_CTRL @ 0XFF5E0074</p>
1015
1016                 Clock active signal. Switch to 0 to disable the clock
1017                 PSU_CRL_APB_UART0_REF_CTRL_CLKACT                                               0x1
1018
1019                 6 bit divider
1020                 PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1                                             0x1
1021
1022                 6 bit divider
1023                 PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0                                             0xf
1024
1025                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1026                 clock. This is not usually an issue, but designers must be aware.)
1027                 PSU_CRL_APB_UART0_REF_CTRL_SRCSEL                                               0x0
1028
1029                 This register controls this reference clock
1030                 (OFFSET, MASK, VALUE)      (0XFF5E0074, 0x013F3F07U ,0x01010F00U)
1031                 RegMask = (CRL_APB_UART0_REF_CTRL_CLKACT_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART0_REF_CTRL_SRCSEL_MASK |  0 );
1032
1033                 RegVal = ((0x00000001U << CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT
1034                         | 0x00000001U << CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT
1035                         | 0x0000000FU << CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT
1036                         | 0x00000000U << CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT
1037                         |  0 ) & RegMask); */
1038                 PSU_Mask_Write (CRL_APB_UART0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
1039         /*############################################################################################################################ */
1040
1041                 /*Register : UART1_REF_CTRL @ 0XFF5E0078</p>
1042
1043                 Clock active signal. Switch to 0 to disable the clock
1044                 PSU_CRL_APB_UART1_REF_CTRL_CLKACT                                               0x1
1045
1046                 6 bit divider
1047                 PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1                                             0x1
1048
1049                 6 bit divider
1050                 PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0                                             0xf
1051
1052                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1053                 clock. This is not usually an issue, but designers must be aware.)
1054                 PSU_CRL_APB_UART1_REF_CTRL_SRCSEL                                               0x0
1055
1056                 This register controls this reference clock
1057                 (OFFSET, MASK, VALUE)      (0XFF5E0078, 0x013F3F07U ,0x01010F00U)
1058                 RegMask = (CRL_APB_UART1_REF_CTRL_CLKACT_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART1_REF_CTRL_SRCSEL_MASK |  0 );
1059
1060                 RegVal = ((0x00000001U << CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT
1061                         | 0x00000001U << CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT
1062                         | 0x0000000FU << CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT
1063                         | 0x00000000U << CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT
1064                         |  0 ) & RegMask); */
1065                 PSU_Mask_Write (CRL_APB_UART1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
1066         /*############################################################################################################################ */
1067
1068                 /*Register : I2C0_REF_CTRL @ 0XFF5E0120</p>
1069
1070                 Clock active signal. Switch to 0 to disable the clock
1071                 PSU_CRL_APB_I2C0_REF_CTRL_CLKACT                                                0x1
1072
1073                 6 bit divider
1074                 PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1                                              0x1
1075
1076                 6 bit divider
1077                 PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0                                              0xf
1078
1079                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1080                 clock. This is not usually an issue, but designers must be aware.)
1081                 PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL                                                0x0
1082
1083                 This register controls this reference clock
1084                 (OFFSET, MASK, VALUE)      (0XFF5E0120, 0x013F3F07U ,0x01010F00U)
1085                 RegMask = (CRL_APB_I2C0_REF_CTRL_CLKACT_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK |  0 );
1086
1087                 RegVal = ((0x00000001U << CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT
1088                         | 0x00000001U << CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT
1089                         | 0x0000000FU << CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT
1090                         | 0x00000000U << CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT
1091                         |  0 ) & RegMask); */
1092                 PSU_Mask_Write (CRL_APB_I2C0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
1093         /*############################################################################################################################ */
1094
1095                 /*Register : I2C1_REF_CTRL @ 0XFF5E0124</p>
1096
1097                 Clock active signal. Switch to 0 to disable the clock
1098                 PSU_CRL_APB_I2C1_REF_CTRL_CLKACT                                                0x1
1099
1100                 6 bit divider
1101                 PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1                                              0x1
1102
1103                 6 bit divider
1104                 PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0                                              0xf
1105
1106                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1107                 clock. This is not usually an issue, but designers must be aware.)
1108                 PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL                                                0x0
1109
1110                 This register controls this reference clock
1111                 (OFFSET, MASK, VALUE)      (0XFF5E0124, 0x013F3F07U ,0x01010F00U)
1112                 RegMask = (CRL_APB_I2C1_REF_CTRL_CLKACT_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK |  0 );
1113
1114                 RegVal = ((0x00000001U << CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT
1115                         | 0x00000001U << CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT
1116                         | 0x0000000FU << CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT
1117                         | 0x00000000U << CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT
1118                         |  0 ) & RegMask); */
1119                 PSU_Mask_Write (CRL_APB_I2C1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
1120         /*############################################################################################################################ */
1121
1122                 /*Register : CAN1_REF_CTRL @ 0XFF5E0088</p>
1123
1124                 Clock active signal. Switch to 0 to disable the clock
1125                 PSU_CRL_APB_CAN1_REF_CTRL_CLKACT                                                0x1
1126
1127                 6 bit divider
1128                 PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1                                              0x1
1129
1130                 6 bit divider
1131                 PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0                                              0xf
1132
1133                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1134                 clock. This is not usually an issue, but designers must be aware.)
1135                 PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL                                                0x0
1136
1137                 This register controls this reference clock
1138                 (OFFSET, MASK, VALUE)      (0XFF5E0088, 0x013F3F07U ,0x01010F00U)
1139                 RegMask = (CRL_APB_CAN1_REF_CTRL_CLKACT_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK | CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK |  0 );
1140
1141                 RegVal = ((0x00000001U << CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT
1142                         | 0x00000001U << CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT
1143                         | 0x0000000FU << CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT
1144                         | 0x00000000U << CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT
1145                         |  0 ) & RegMask); */
1146                 PSU_Mask_Write (CRL_APB_CAN1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
1147         /*############################################################################################################################ */
1148
1149                 /*Register : CPU_R5_CTRL @ 0XFF5E0090</p>
1150
1151                 Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou
1152                 d lead to system hang
1153                 PSU_CRL_APB_CPU_R5_CTRL_CLKACT                                                  0x1
1154
1155                 6 bit divider
1156                 PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0                                                0x3
1157
1158                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1159                 clock. This is not usually an issue, but designers must be aware.)
1160                 PSU_CRL_APB_CPU_R5_CTRL_SRCSEL                                                  0x2
1161
1162                 This register controls this reference clock
1163                 (OFFSET, MASK, VALUE)      (0XFF5E0090, 0x01003F07U ,0x01000302U)
1164                 RegMask = (CRL_APB_CPU_R5_CTRL_CLKACT_MASK | CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK | CRL_APB_CPU_R5_CTRL_SRCSEL_MASK |  0 );
1165
1166                 RegVal = ((0x00000001U << CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT
1167                         | 0x00000003U << CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT
1168                         | 0x00000002U << CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT
1169                         |  0 ) & RegMask); */
1170                 PSU_Mask_Write (CRL_APB_CPU_R5_CTRL_OFFSET ,0x01003F07U ,0x01000302U);
1171         /*############################################################################################################################ */
1172
1173                 /*Register : IOU_SWITCH_CTRL @ 0XFF5E009C</p>
1174
1175                 Clock active signal. Switch to 0 to disable the clock
1176                 PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT                                              0x1
1177
1178                 6 bit divider
1179                 PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0                                            0x6
1180
1181                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1182                 clock. This is not usually an issue, but designers must be aware.)
1183                 PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL                                              0x2
1184
1185                 This register controls this reference clock
1186                 (OFFSET, MASK, VALUE)      (0XFF5E009C, 0x01003F07U ,0x01000602U)
1187                 RegMask = (CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK | CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK |  0 );
1188
1189                 RegVal = ((0x00000001U << CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT
1190                         | 0x00000006U << CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT
1191                         | 0x00000002U << CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT
1192                         |  0 ) & RegMask); */
1193                 PSU_Mask_Write (CRL_APB_IOU_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000602U);
1194         /*############################################################################################################################ */
1195
1196                 /*Register : PCAP_CTRL @ 0XFF5E00A4</p>
1197
1198                 Clock active signal. Switch to 0 to disable the clock
1199                 PSU_CRL_APB_PCAP_CTRL_CLKACT                                                    0x1
1200
1201                 6 bit divider
1202                 PSU_CRL_APB_PCAP_CTRL_DIVISOR0                                                  0x6
1203
1204                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1205                 clock. This is not usually an issue, but designers must be aware.)
1206                 PSU_CRL_APB_PCAP_CTRL_SRCSEL                                                    0x2
1207
1208                 This register controls this reference clock
1209                 (OFFSET, MASK, VALUE)      (0XFF5E00A4, 0x01003F07U ,0x01000602U)
1210                 RegMask = (CRL_APB_PCAP_CTRL_CLKACT_MASK | CRL_APB_PCAP_CTRL_DIVISOR0_MASK | CRL_APB_PCAP_CTRL_SRCSEL_MASK |  0 );
1211
1212                 RegVal = ((0x00000001U << CRL_APB_PCAP_CTRL_CLKACT_SHIFT
1213                         | 0x00000006U << CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT
1214                         | 0x00000002U << CRL_APB_PCAP_CTRL_SRCSEL_SHIFT
1215                         |  0 ) & RegMask); */
1216                 PSU_Mask_Write (CRL_APB_PCAP_CTRL_OFFSET ,0x01003F07U ,0x01000602U);
1217         /*############################################################################################################################ */
1218
1219                 /*Register : LPD_SWITCH_CTRL @ 0XFF5E00A8</p>
1220
1221                 Clock active signal. Switch to 0 to disable the clock
1222                 PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT                                              0x1
1223
1224                 6 bit divider
1225                 PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0                                            0x3
1226
1227                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1228                 clock. This is not usually an issue, but designers must be aware.)
1229                 PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL                                              0x2
1230
1231                 This register controls this reference clock
1232                 (OFFSET, MASK, VALUE)      (0XFF5E00A8, 0x01003F07U ,0x01000302U)
1233                 RegMask = (CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK | CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK |  0 );
1234
1235                 RegVal = ((0x00000001U << CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT
1236                         | 0x00000003U << CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT
1237                         | 0x00000002U << CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT
1238                         |  0 ) & RegMask); */
1239                 PSU_Mask_Write (CRL_APB_LPD_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000302U);
1240         /*############################################################################################################################ */
1241
1242                 /*Register : LPD_LSBUS_CTRL @ 0XFF5E00AC</p>
1243
1244                 Clock active signal. Switch to 0 to disable the clock
1245                 PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT                                               0x1
1246
1247                 6 bit divider
1248                 PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0                                             0xf
1249
1250                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1251                 clock. This is not usually an issue, but designers must be aware.)
1252                 PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL                                               0x2
1253
1254                 This register controls this reference clock
1255                 (OFFSET, MASK, VALUE)      (0XFF5E00AC, 0x01003F07U ,0x01000F02U)
1256                 RegMask = (CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK | CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK | CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK |  0 );
1257
1258                 RegVal = ((0x00000001U << CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT
1259                         | 0x0000000FU << CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT
1260                         | 0x00000002U << CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT
1261                         |  0 ) & RegMask); */
1262                 PSU_Mask_Write (CRL_APB_LPD_LSBUS_CTRL_OFFSET ,0x01003F07U ,0x01000F02U);
1263         /*############################################################################################################################ */
1264
1265                 /*Register : DBG_LPD_CTRL @ 0XFF5E00B0</p>
1266
1267                 Clock active signal. Switch to 0 to disable the clock
1268                 PSU_CRL_APB_DBG_LPD_CTRL_CLKACT                                                 0x1
1269
1270                 6 bit divider
1271                 PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0                                               0x6
1272
1273                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1274                 clock. This is not usually an issue, but designers must be aware.)
1275                 PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL                                                 0x2
1276
1277                 This register controls this reference clock
1278                 (OFFSET, MASK, VALUE)      (0XFF5E00B0, 0x01003F07U ,0x01000602U)
1279                 RegMask = (CRL_APB_DBG_LPD_CTRL_CLKACT_MASK | CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK | CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK |  0 );
1280
1281                 RegVal = ((0x00000001U << CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT
1282                         | 0x00000006U << CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT
1283                         | 0x00000002U << CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT
1284                         |  0 ) & RegMask); */
1285                 PSU_Mask_Write (CRL_APB_DBG_LPD_CTRL_OFFSET ,0x01003F07U ,0x01000602U);
1286         /*############################################################################################################################ */
1287
1288                 /*Register : ADMA_REF_CTRL @ 0XFF5E00B8</p>
1289
1290                 Clock active signal. Switch to 0 to disable the clock
1291                 PSU_CRL_APB_ADMA_REF_CTRL_CLKACT                                                0x1
1292
1293                 6 bit divider
1294                 PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0                                              0x3
1295
1296                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1297                 clock. This is not usually an issue, but designers must be aware.)
1298                 PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL                                                0x2
1299
1300                 This register controls this reference clock
1301                 (OFFSET, MASK, VALUE)      (0XFF5E00B8, 0x01003F07U ,0x01000302U)
1302                 RegMask = (CRL_APB_ADMA_REF_CTRL_CLKACT_MASK | CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK | CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK |  0 );
1303
1304                 RegVal = ((0x00000001U << CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT
1305                         | 0x00000003U << CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT
1306                         | 0x00000002U << CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT
1307                         |  0 ) & RegMask); */
1308                 PSU_Mask_Write (CRL_APB_ADMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000302U);
1309         /*############################################################################################################################ */
1310
1311                 /*Register : PL0_REF_CTRL @ 0XFF5E00C0</p>
1312
1313                 Clock active signal. Switch to 0 to disable the clock
1314                 PSU_CRL_APB_PL0_REF_CTRL_CLKACT                                                 0x1
1315
1316                 6 bit divider
1317                 PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1                                               0x1
1318
1319                 6 bit divider
1320                 PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0                                               0xf
1321
1322                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1323                 clock. This is not usually an issue, but designers must be aware.)
1324                 PSU_CRL_APB_PL0_REF_CTRL_SRCSEL                                                 0x0
1325
1326                 This register controls this reference clock
1327                 (OFFSET, MASK, VALUE)      (0XFF5E00C0, 0x013F3F07U ,0x01010F00U)
1328                 RegMask = (CRL_APB_PL0_REF_CTRL_CLKACT_MASK | CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL0_REF_CTRL_SRCSEL_MASK |  0 );
1329
1330                 RegVal = ((0x00000001U << CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT
1331                         | 0x00000001U << CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT
1332                         | 0x0000000FU << CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT
1333                         | 0x00000000U << CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT
1334                         |  0 ) & RegMask); */
1335                 PSU_Mask_Write (CRL_APB_PL0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
1336         /*############################################################################################################################ */
1337
1338                 /*Register : PL1_REF_CTRL @ 0XFF5E00C4</p>
1339
1340                 Clock active signal. Switch to 0 to disable the clock
1341                 PSU_CRL_APB_PL1_REF_CTRL_CLKACT                                                 0x1
1342
1343                 6 bit divider
1344                 PSU_CRL_APB_PL1_REF_CTRL_DIVISOR1                                               0x4
1345
1346                 6 bit divider
1347                 PSU_CRL_APB_PL1_REF_CTRL_DIVISOR0                                               0xf
1348
1349                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1350                 clock. This is not usually an issue, but designers must be aware.)
1351                 PSU_CRL_APB_PL1_REF_CTRL_SRCSEL                                                 0x0
1352
1353                 This register controls this reference clock
1354                 (OFFSET, MASK, VALUE)      (0XFF5E00C4, 0x013F3F07U ,0x01040F00U)
1355                 RegMask = (CRL_APB_PL1_REF_CTRL_CLKACT_MASK | CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL1_REF_CTRL_SRCSEL_MASK |  0 );
1356
1357                 RegVal = ((0x00000001U << CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT
1358                         | 0x00000004U << CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT
1359                         | 0x0000000FU << CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT
1360                         | 0x00000000U << CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT
1361                         |  0 ) & RegMask); */
1362                 PSU_Mask_Write (CRL_APB_PL1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01040F00U);
1363         /*############################################################################################################################ */
1364
1365                 /*Register : PL2_REF_CTRL @ 0XFF5E00C8</p>
1366
1367                 Clock active signal. Switch to 0 to disable the clock
1368                 PSU_CRL_APB_PL2_REF_CTRL_CLKACT                                                 0x1
1369
1370                 6 bit divider
1371                 PSU_CRL_APB_PL2_REF_CTRL_DIVISOR1                                               0x1
1372
1373                 6 bit divider
1374                 PSU_CRL_APB_PL2_REF_CTRL_DIVISOR0                                               0x4
1375
1376                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1377                 clock. This is not usually an issue, but designers must be aware.)
1378                 PSU_CRL_APB_PL2_REF_CTRL_SRCSEL                                                 0x2
1379
1380                 This register controls this reference clock
1381                 (OFFSET, MASK, VALUE)      (0XFF5E00C8, 0x013F3F07U ,0x01010402U)
1382                 RegMask = (CRL_APB_PL2_REF_CTRL_CLKACT_MASK | CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL2_REF_CTRL_SRCSEL_MASK |  0 );
1383
1384                 RegVal = ((0x00000001U << CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT
1385                         | 0x00000001U << CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT
1386                         | 0x00000004U << CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT
1387                         | 0x00000002U << CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT
1388                         |  0 ) & RegMask); */
1389                 PSU_Mask_Write (CRL_APB_PL2_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010402U);
1390         /*############################################################################################################################ */
1391
1392                 /*Register : PL3_REF_CTRL @ 0XFF5E00CC</p>
1393
1394                 Clock active signal. Switch to 0 to disable the clock
1395                 PSU_CRL_APB_PL3_REF_CTRL_CLKACT                                                 0x1
1396
1397                 6 bit divider
1398                 PSU_CRL_APB_PL3_REF_CTRL_DIVISOR1                                               0x1
1399
1400                 6 bit divider
1401                 PSU_CRL_APB_PL3_REF_CTRL_DIVISOR0                                               0x3
1402
1403                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1404                 clock. This is not usually an issue, but designers must be aware.)
1405                 PSU_CRL_APB_PL3_REF_CTRL_SRCSEL                                                 0x2
1406
1407                 This register controls this reference clock
1408                 (OFFSET, MASK, VALUE)      (0XFF5E00CC, 0x013F3F07U ,0x01010302U)
1409                 RegMask = (CRL_APB_PL3_REF_CTRL_CLKACT_MASK | CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL3_REF_CTRL_SRCSEL_MASK |  0 );
1410
1411                 RegVal = ((0x00000001U << CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT
1412                         | 0x00000001U << CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT
1413                         | 0x00000003U << CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT
1414                         | 0x00000002U << CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT
1415                         |  0 ) & RegMask); */
1416                 PSU_Mask_Write (CRL_APB_PL3_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010302U);
1417         /*############################################################################################################################ */
1418
1419                 /*Register : AMS_REF_CTRL @ 0XFF5E0108</p>
1420
1421                 6 bit divider
1422                 PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1                                               0x1
1423
1424                 6 bit divider
1425                 PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0                                               0x1d
1426
1427                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1428                 clock. This is not usually an issue, but designers must be aware.)
1429                 PSU_CRL_APB_AMS_REF_CTRL_SRCSEL                                                 0x2
1430
1431                 Clock active signal. Switch to 0 to disable the clock
1432                 PSU_CRL_APB_AMS_REF_CTRL_CLKACT                                                 0x1
1433
1434                 This register controls this reference clock
1435                 (OFFSET, MASK, VALUE)      (0XFF5E0108, 0x013F3F07U ,0x01011D02U)
1436                 RegMask = (CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK | CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK | CRL_APB_AMS_REF_CTRL_SRCSEL_MASK | CRL_APB_AMS_REF_CTRL_CLKACT_MASK |  0 );
1437
1438                 RegVal = ((0x00000001U << CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT
1439                         | 0x0000001DU << CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT
1440                         | 0x00000002U << CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT
1441                         | 0x00000001U << CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT
1442                         |  0 ) & RegMask); */
1443                 PSU_Mask_Write (CRL_APB_AMS_REF_CTRL_OFFSET ,0x013F3F07U ,0x01011D02U);
1444         /*############################################################################################################################ */
1445
1446                 /*Register : DLL_REF_CTRL @ 0XFF5E0104</p>
1447
1448                 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
1449                 is not usually an issue, but designers must be aware.)
1450                 PSU_CRL_APB_DLL_REF_CTRL_SRCSEL                                                 0
1451
1452                 This register controls this reference clock
1453                 (OFFSET, MASK, VALUE)      (0XFF5E0104, 0x00000007U ,0x00000000U)
1454                 RegMask = (CRL_APB_DLL_REF_CTRL_SRCSEL_MASK |  0 );
1455
1456                 RegVal = ((0x00000000U << CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT
1457                         |  0 ) & RegMask); */
1458                 PSU_Mask_Write (CRL_APB_DLL_REF_CTRL_OFFSET ,0x00000007U ,0x00000000U);
1459         /*############################################################################################################################ */
1460
1461                 /*Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128</p>
1462
1463                 6 bit divider
1464                 PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0                                         0xf
1465
1466                 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and
1467                  cycles of the new clock. This is not usually an issue, but designers must be aware.)
1468                 PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL                                           0x0
1469
1470                 Clock active signal. Switch to 0 to disable the clock
1471                 PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT                                           0x1
1472
1473                 This register controls this reference clock
1474                 (OFFSET, MASK, VALUE)      (0XFF5E0128, 0x01003F07U ,0x01000F00U)
1475                 RegMask = (CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK | CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK | CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK |  0 );
1476
1477                 RegVal = ((0x0000000FU << CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT
1478                         | 0x00000000U << CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT
1479                         | 0x00000001U << CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT
1480                         |  0 ) & RegMask); */
1481                 PSU_Mask_Write (CRL_APB_TIMESTAMP_REF_CTRL_OFFSET ,0x01003F07U ,0x01000F00U);
1482         /*############################################################################################################################ */
1483
1484                 /*Register : SATA_REF_CTRL @ 0XFD1A00A0</p>
1485
1486                 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1487                 he new clock. This is not usually an issue, but designers must be aware.)
1488                 PSU_CRF_APB_SATA_REF_CTRL_SRCSEL                                                0x0
1489
1490                 Clock active signal. Switch to 0 to disable the clock
1491                 PSU_CRF_APB_SATA_REF_CTRL_CLKACT                                                0x1
1492
1493                 6 bit divider
1494                 PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0                                              0x2
1495
1496                 This register controls this reference clock
1497                 (OFFSET, MASK, VALUE)      (0XFD1A00A0, 0x01003F07U ,0x01000200U)
1498                 RegMask = (CRF_APB_SATA_REF_CTRL_SRCSEL_MASK | CRF_APB_SATA_REF_CTRL_CLKACT_MASK | CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK |  0 );
1499
1500                 RegVal = ((0x00000000U << CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT
1501                         | 0x00000001U << CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT
1502                         | 0x00000002U << CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT
1503                         |  0 ) & RegMask); */
1504                 PSU_Mask_Write (CRF_APB_SATA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
1505         /*############################################################################################################################ */
1506
1507                 /*Register : PCIE_REF_CTRL @ 0XFD1A00B4</p>
1508
1509                 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc
1510                 es of the new clock. This is not usually an issue, but designers must be aware.)
1511                 PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL                                                0x0
1512
1513                 Clock active signal. Switch to 0 to disable the clock
1514                 PSU_CRF_APB_PCIE_REF_CTRL_CLKACT                                                0x1
1515
1516                 6 bit divider
1517                 PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0                                              0x2
1518
1519                 This register controls this reference clock
1520                 (OFFSET, MASK, VALUE)      (0XFD1A00B4, 0x01003F07U ,0x01000200U)
1521                 RegMask = (CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK | CRF_APB_PCIE_REF_CTRL_CLKACT_MASK | CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK |  0 );
1522
1523                 RegVal = ((0x00000000U << CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT
1524                         | 0x00000001U << CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT
1525                         | 0x00000002U << CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT
1526                         |  0 ) & RegMask); */
1527                 PSU_Mask_Write (CRF_APB_PCIE_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
1528         /*############################################################################################################################ */
1529
1530                 /*Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070</p>
1531
1532                 6 bit divider
1533                 PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1                                          0x1
1534
1535                 6 bit divider
1536                 PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0                                          0x3
1537
1538                 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the
1539                 ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
1540                 PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL                                            0x3
1541
1542                 Clock active signal. Switch to 0 to disable the clock
1543                 PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT                                            0x1
1544
1545                 This register controls this reference clock
1546                 (OFFSET, MASK, VALUE)      (0XFD1A0070, 0x013F3F07U ,0x01010303U)
1547                 RegMask = (CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK |  0 );
1548
1549                 RegVal = ((0x00000001U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT
1550                         | 0x00000003U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT
1551                         | 0x00000003U << CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT
1552                         | 0x00000001U << CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT
1553                         |  0 ) & RegMask); */
1554                 PSU_Mask_Write (CRF_APB_DP_VIDEO_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010303U);
1555         /*############################################################################################################################ */
1556
1557                 /*Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074</p>
1558
1559                 6 bit divider
1560                 PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1                                          0x1
1561
1562                 6 bit divider
1563                 PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0                                          0x27
1564
1565                 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the
1566                 ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
1567                 PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL                                            0x0
1568
1569                 Clock active signal. Switch to 0 to disable the clock
1570                 PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT                                            0x1
1571
1572                 This register controls this reference clock
1573                 (OFFSET, MASK, VALUE)      (0XFD1A0074, 0x013F3F07U ,0x01012700U)
1574                 RegMask = (CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK |  0 );
1575
1576                 RegVal = ((0x00000001U << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT
1577                         | 0x00000027U << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT
1578                         | 0x00000000U << CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT
1579                         | 0x00000001U << CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT
1580                         |  0 ) & RegMask); */
1581                 PSU_Mask_Write (CRF_APB_DP_AUDIO_REF_CTRL_OFFSET ,0x013F3F07U ,0x01012700U);
1582         /*############################################################################################################################ */
1583
1584                 /*Register : DP_STC_REF_CTRL @ 0XFD1A007C</p>
1585
1586                 6 bit divider
1587                 PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1                                            0x1
1588
1589                 6 bit divider
1590                 PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0                                            0x11
1591
1592                 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t
1593                 e new clock. This is not usually an issue, but designers must be aware.)
1594                 PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL                                              0x3
1595
1596                 Clock active signal. Switch to 0 to disable the clock
1597                 PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT                                              0x1
1598
1599                 This register controls this reference clock
1600                 (OFFSET, MASK, VALUE)      (0XFD1A007C, 0x013F3F07U ,0x01011103U)
1601                 RegMask = (CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK |  0 );
1602
1603                 RegVal = ((0x00000001U << CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT
1604                         | 0x00000011U << CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT
1605                         | 0x00000003U << CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT
1606                         | 0x00000001U << CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT
1607                         |  0 ) & RegMask); */
1608                 PSU_Mask_Write (CRF_APB_DP_STC_REF_CTRL_OFFSET ,0x013F3F07U ,0x01011103U);
1609         /*############################################################################################################################ */
1610
1611                 /*Register : ACPU_CTRL @ 0XFD1A0060</p>
1612
1613                 6 bit divider
1614                 PSU_CRF_APB_ACPU_CTRL_DIVISOR0                                                  0x1
1615
1616                 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1617                 lock. This is not usually an issue, but designers must be aware.)
1618                 PSU_CRF_APB_ACPU_CTRL_SRCSEL                                                    0x0
1619
1620                 Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock
1621                 PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF                                               0x1
1622
1623                 Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc
1624                  to the entire APU
1625                 PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL                                               0x1
1626
1627                 This register controls this reference clock
1628                 (OFFSET, MASK, VALUE)      (0XFD1A0060, 0x03003F07U ,0x03000100U)
1629                 RegMask = (CRF_APB_ACPU_CTRL_DIVISOR0_MASK | CRF_APB_ACPU_CTRL_SRCSEL_MASK | CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK | CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK |  0 );
1630
1631                 RegVal = ((0x00000001U << CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT
1632                         | 0x00000000U << CRF_APB_ACPU_CTRL_SRCSEL_SHIFT
1633                         | 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT
1634                         | 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT
1635                         |  0 ) & RegMask); */
1636                 PSU_Mask_Write (CRF_APB_ACPU_CTRL_OFFSET ,0x03003F07U ,0x03000100U);
1637         /*############################################################################################################################ */
1638
1639                 /*Register : DBG_TRACE_CTRL @ 0XFD1A0064</p>
1640
1641                 6 bit divider
1642                 PSU_CRF_APB_DBG_TRACE_CTRL_DIVISOR0                                             0x2
1643
1644                 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1645                 he new clock. This is not usually an issue, but designers must be aware.)
1646                 PSU_CRF_APB_DBG_TRACE_CTRL_SRCSEL                                               0x0
1647
1648                 Clock active signal. Switch to 0 to disable the clock
1649                 PSU_CRF_APB_DBG_TRACE_CTRL_CLKACT                                               0x1
1650
1651                 This register controls this reference clock
1652                 (OFFSET, MASK, VALUE)      (0XFD1A0064, 0x01003F07U ,0x01000200U)
1653                 RegMask = (CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK | CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK |  0 );
1654
1655                 RegVal = ((0x00000002U << CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT
1656                         | 0x00000000U << CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT
1657                         | 0x00000001U << CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT
1658                         |  0 ) & RegMask); */
1659                 PSU_Mask_Write (CRF_APB_DBG_TRACE_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
1660         /*############################################################################################################################ */
1661
1662                 /*Register : DBG_FPD_CTRL @ 0XFD1A0068</p>
1663
1664                 6 bit divider
1665                 PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0                                               0x2
1666
1667                 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1668                 he new clock. This is not usually an issue, but designers must be aware.)
1669                 PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL                                                 0x0
1670
1671                 Clock active signal. Switch to 0 to disable the clock
1672                 PSU_CRF_APB_DBG_FPD_CTRL_CLKACT                                                 0x1
1673
1674                 This register controls this reference clock
1675                 (OFFSET, MASK, VALUE)      (0XFD1A0068, 0x01003F07U ,0x01000200U)
1676                 RegMask = (CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK | CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK | CRF_APB_DBG_FPD_CTRL_CLKACT_MASK |  0 );
1677
1678                 RegVal = ((0x00000002U << CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT
1679                         | 0x00000000U << CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT
1680                         | 0x00000001U << CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT
1681                         |  0 ) & RegMask); */
1682                 PSU_Mask_Write (CRF_APB_DBG_FPD_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
1683         /*############################################################################################################################ */
1684
1685                 /*Register : DDR_CTRL @ 0XFD1A0080</p>
1686
1687                 6 bit divider
1688                 PSU_CRF_APB_DDR_CTRL_DIVISOR0                                                   0x2
1689
1690                 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
1691                 s not usually an issue, but designers must be aware.)
1692                 PSU_CRF_APB_DDR_CTRL_SRCSEL                                                     0x0
1693
1694                 This register controls this reference clock
1695                 (OFFSET, MASK, VALUE)      (0XFD1A0080, 0x00003F07U ,0x00000200U)
1696                 RegMask = (CRF_APB_DDR_CTRL_DIVISOR0_MASK | CRF_APB_DDR_CTRL_SRCSEL_MASK |  0 );
1697
1698                 RegVal = ((0x00000002U << CRF_APB_DDR_CTRL_DIVISOR0_SHIFT
1699                         | 0x00000000U << CRF_APB_DDR_CTRL_SRCSEL_SHIFT
1700                         |  0 ) & RegMask); */
1701                 PSU_Mask_Write (CRF_APB_DDR_CTRL_OFFSET ,0x00003F07U ,0x00000200U);
1702         /*############################################################################################################################ */
1703
1704                 /*Register : GPU_REF_CTRL @ 0XFD1A0084</p>
1705
1706                 6 bit divider
1707                 PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0                                               0x1
1708
1709                 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1710                 he new clock. This is not usually an issue, but designers must be aware.)
1711                 PSU_CRF_APB_GPU_REF_CTRL_SRCSEL                                                 0x0
1712
1713                 Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors).
1714                 PSU_CRF_APB_GPU_REF_CTRL_CLKACT                                                 0x1
1715
1716                 Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor
1717                 PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT                                             0x1
1718
1719                 Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor
1720                 PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT                                             0x1
1721
1722                 This register controls this reference clock
1723                 (OFFSET, MASK, VALUE)      (0XFD1A0084, 0x07003F07U ,0x07000100U)
1724                 RegMask = (CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK | CRF_APB_GPU_REF_CTRL_SRCSEL_MASK | CRF_APB_GPU_REF_CTRL_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK |  0 );
1725
1726                 RegVal = ((0x00000001U << CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT
1727                         | 0x00000000U << CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT
1728                         | 0x00000001U << CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT
1729                         | 0x00000001U << CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT
1730                         | 0x00000001U << CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT
1731                         |  0 ) & RegMask); */
1732                 PSU_Mask_Write (CRF_APB_GPU_REF_CTRL_OFFSET ,0x07003F07U ,0x07000100U);
1733         /*############################################################################################################################ */
1734
1735                 /*Register : GDMA_REF_CTRL @ 0XFD1A00B8</p>
1736
1737                 6 bit divider
1738                 PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0                                              0x2
1739
1740                 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1741                 lock. This is not usually an issue, but designers must be aware.)
1742                 PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL                                                0x0
1743
1744                 Clock active signal. Switch to 0 to disable the clock
1745                 PSU_CRF_APB_GDMA_REF_CTRL_CLKACT                                                0x1
1746
1747                 This register controls this reference clock
1748                 (OFFSET, MASK, VALUE)      (0XFD1A00B8, 0x01003F07U ,0x01000200U)
1749                 RegMask = (CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_GDMA_REF_CTRL_CLKACT_MASK |  0 );
1750
1751                 RegVal = ((0x00000002U << CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT
1752                         | 0x00000000U << CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT
1753                         | 0x00000001U << CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT
1754                         |  0 ) & RegMask); */
1755                 PSU_Mask_Write (CRF_APB_GDMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
1756         /*############################################################################################################################ */
1757
1758                 /*Register : DPDMA_REF_CTRL @ 0XFD1A00BC</p>
1759
1760                 6 bit divider
1761                 PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0                                             0x2
1762
1763                 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1764                 lock. This is not usually an issue, but designers must be aware.)
1765                 PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL                                               0x0
1766
1767                 Clock active signal. Switch to 0 to disable the clock
1768                 PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT                                               0x1
1769
1770                 This register controls this reference clock
1771                 (OFFSET, MASK, VALUE)      (0XFD1A00BC, 0x01003F07U ,0x01000200U)
1772                 RegMask = (CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK |  0 );
1773
1774                 RegVal = ((0x00000002U << CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT
1775                         | 0x00000000U << CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT
1776                         | 0x00000001U << CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT
1777                         |  0 ) & RegMask); */
1778                 PSU_Mask_Write (CRF_APB_DPDMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
1779         /*############################################################################################################################ */
1780
1781                 /*Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0</p>
1782
1783                 6 bit divider
1784                 PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0                                            0x2
1785
1786                 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1787                 lock. This is not usually an issue, but designers must be aware.)
1788                 PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL                                              0x2
1789
1790                 Clock active signal. Switch to 0 to disable the clock
1791                 PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT                                              0x1
1792
1793                 This register controls this reference clock
1794                 (OFFSET, MASK, VALUE)      (0XFD1A00C0, 0x01003F07U ,0x01000202U)
1795                 RegMask = (CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK |  0 );
1796
1797                 RegVal = ((0x00000002U << CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT
1798                         | 0x00000002U << CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT
1799                         | 0x00000001U << CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT
1800                         |  0 ) & RegMask); */
1801                 PSU_Mask_Write (CRF_APB_TOPSW_MAIN_CTRL_OFFSET ,0x01003F07U ,0x01000202U);
1802         /*############################################################################################################################ */
1803
1804                 /*Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4</p>
1805
1806                 6 bit divider
1807                 PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0                                           0x5
1808
1809                 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1810                 he new clock. This is not usually an issue, but designers must be aware.)
1811                 PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL                                             0x2
1812
1813                 Clock active signal. Switch to 0 to disable the clock
1814                 PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT                                             0x1
1815
1816                 This register controls this reference clock
1817                 (OFFSET, MASK, VALUE)      (0XFD1A00C4, 0x01003F07U ,0x01000502U)
1818                 RegMask = (CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK |  0 );
1819
1820                 RegVal = ((0x00000005U << CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT
1821                         | 0x00000002U << CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT
1822                         | 0x00000001U << CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT
1823                         |  0 ) & RegMask); */
1824                 PSU_Mask_Write (CRF_APB_TOPSW_LSBUS_CTRL_OFFSET ,0x01003F07U ,0x01000502U);
1825         /*############################################################################################################################ */
1826
1827                 /*Register : DBG_TSTMP_CTRL @ 0XFD1A00F8</p>
1828
1829                 6 bit divider
1830                 PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0                                             0x2
1831
1832                 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1833                 he new clock. This is not usually an issue, but designers must be aware.)
1834                 PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL                                               0x0
1835
1836                 This register controls this reference clock
1837                 (OFFSET, MASK, VALUE)      (0XFD1A00F8, 0x00003F07U ,0x00000200U)
1838                 RegMask = (CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK |  0 );
1839
1840                 RegVal = ((0x00000002U << CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT
1841                         | 0x00000000U << CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT
1842                         |  0 ) & RegMask); */
1843                 PSU_Mask_Write (CRF_APB_DBG_TSTMP_CTRL_OFFSET ,0x00003F07U ,0x00000200U);
1844         /*############################################################################################################################ */
1845
1846                 /*Register : IOU_TTC_APB_CLK @ 0XFF180380</p>
1847
1848                 00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0'
1849                 0" = Select the R5 clock for the APB interface of TTC0
1850                 PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL                                           0
1851
1852                 00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1'
1853                 0" = Select the R5 clock for the APB interface of TTC1
1854                 PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL                                           0
1855
1856                 00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2'
1857                 0" = Select the R5 clock for the APB interface of TTC2
1858                 PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL                                           0
1859
1860                 00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3'
1861                 0" = Select the R5 clock for the APB interface of TTC3
1862                 PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL                                           0
1863
1864                 TTC APB clock select
1865                 (OFFSET, MASK, VALUE)      (0XFF180380, 0x000000FFU ,0x00000000U)
1866                 RegMask = (IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK |  0 );
1867
1868                 RegVal = ((0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT
1869                         | 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT
1870                         | 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT
1871                         | 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT
1872                         |  0 ) & RegMask); */
1873                 PSU_Mask_Write (IOU_SLCR_IOU_TTC_APB_CLK_OFFSET ,0x000000FFU ,0x00000000U);
1874         /*############################################################################################################################ */
1875
1876                 /*Register : WDT_CLK_SEL @ 0XFD610100</p>
1877
1878                 System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO)
1879                 PSU_FPD_SLCR_WDT_CLK_SEL_SELECT                                                 0
1880
1881                 SWDT clock source select
1882                 (OFFSET, MASK, VALUE)      (0XFD610100, 0x00000001U ,0x00000000U)
1883                 RegMask = (FPD_SLCR_WDT_CLK_SEL_SELECT_MASK |  0 );
1884
1885                 RegVal = ((0x00000000U << FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT
1886                         |  0 ) & RegMask); */
1887                 PSU_Mask_Write (FPD_SLCR_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U);
1888         /*############################################################################################################################ */
1889
1890                 /*Register : WDT_CLK_SEL @ 0XFF180300</p>
1891
1892                 System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout
1893                 ia MIO
1894                 PSU_IOU_SLCR_WDT_CLK_SEL_SELECT                                                 0
1895
1896                 SWDT clock source select
1897                 (OFFSET, MASK, VALUE)      (0XFF180300, 0x00000001U ,0x00000000U)
1898                 RegMask = (IOU_SLCR_WDT_CLK_SEL_SELECT_MASK |  0 );
1899
1900                 RegVal = ((0x00000000U << IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT
1901                         |  0 ) & RegMask); */
1902                 PSU_Mask_Write (IOU_SLCR_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U);
1903         /*############################################################################################################################ */
1904
1905                 /*Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050</p>
1906
1907                 System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk
1908                 PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT                                          0
1909
1910                 SWDT clock source select
1911                 (OFFSET, MASK, VALUE)      (0XFF410050, 0x00000001U ,0x00000000U)
1912                 RegMask = (LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK |  0 );
1913
1914                 RegVal = ((0x00000000U << LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT
1915                         |  0 ) & RegMask); */
1916                 PSU_Mask_Write (LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U);
1917         /*############################################################################################################################ */
1918
1919
1920   return 1;
1921 }
1922 unsigned long psu_ddr_init_data() {
1923                 // : DDR INITIALIZATION
1924                 // : DDR CONTROLLER RESET
1925                 /*Register : RST_DDR_SS @ 0XFD1A0108</p>
1926
1927                 DDR block level reset inside of the DDR Sub System
1928                 PSU_CRF_APB_RST_DDR_SS_DDR_RESET                                                0X1
1929
1930                 DDR sub system block level reset
1931                 (OFFSET, MASK, VALUE)      (0XFD1A0108, 0x00000008U ,0x00000008U)
1932                 RegMask = (CRF_APB_RST_DDR_SS_DDR_RESET_MASK |  0 );
1933
1934                 RegVal = ((0x00000001U << CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT
1935                         |  0 ) & RegMask); */
1936                 PSU_Mask_Write (CRF_APB_RST_DDR_SS_OFFSET ,0x00000008U ,0x00000008U);
1937         /*############################################################################################################################ */
1938
1939                 /*Register : MSTR @ 0XFD070000</p>
1940
1941                 Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32
1942                 evice
1943                 PSU_DDRC_MSTR_DEVICE_CONFIG                                                     0x1
1944
1945                 Choose which registers are used. - 0 - Original registers - 1 - Shadow registers
1946                 PSU_DDRC_MSTR_FREQUENCY_MODE                                                    0x0
1947
1948                 Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p
1949                 esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 -
1950                 ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra
1951                 ks - 1111 - Four ranks
1952                 PSU_DDRC_MSTR_ACTIVE_RANKS                                                      0x1
1953
1954                 SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt
1955                  of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls
1956                 he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th
1957                 -fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT
1958                  is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1
1959                 PSU_DDRC_MSTR_BURST_RDWR                                                        0x4
1960
1961                 Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM
1962                 n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d
1963                 l_off_mode is not supported, and this bit must be set to '0'.
1964                 PSU_DDRC_MSTR_DLL_OFF_MODE                                                      0x0
1965
1966                 Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD
1967                 AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w
1968                 dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co
1969                 figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width).
1970                 PSU_DDRC_MSTR_DATA_BUS_WIDTH                                                    0x0
1971
1972                 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed
1973                  only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode
1974                 s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set
1975                 PSU_DDRC_MSTR_GEARDOWN_MODE                                                     0x0
1976
1977                 If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held
1978                 or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in
1979                 PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti
1980                 ing is not supported in DDR4 geardown mode.
1981                 PSU_DDRC_MSTR_EN_2T_TIMING_MODE                                                 0x0
1982
1983                 When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s
1984                 t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable
1985                  (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr
1986                 _parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0'
1987                 PSU_DDRC_MSTR_BURSTCHOP                                                         0x0
1988
1989                 Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su
1990                 port LPDDR4.
1991                 PSU_DDRC_MSTR_LPDDR4                                                            0x0
1992
1993                 Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support
1994                 DR4.
1995                 PSU_DDRC_MSTR_DDR4                                                              0x1
1996
1997                 Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su
1998                 port LPDDR3.
1999                 PSU_DDRC_MSTR_LPDDR3                                                            0x0
2000
2001                 Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su
2002                 port LPDDR2.
2003                 PSU_DDRC_MSTR_LPDDR2                                                            0x0
2004
2005                 Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3
2006
2007                 PSU_DDRC_MSTR_DDR3                                                              0x0
2008
2009                 Master Register
2010                 (OFFSET, MASK, VALUE)      (0XFD070000, 0xE30FBE3DU ,0x41040010U)
2011                 RegMask = (DDRC_MSTR_DEVICE_CONFIG_MASK | DDRC_MSTR_FREQUENCY_MODE_MASK | DDRC_MSTR_ACTIVE_RANKS_MASK | DDRC_MSTR_BURST_RDWR_MASK | DDRC_MSTR_DLL_OFF_MODE_MASK | DDRC_MSTR_DATA_BUS_WIDTH_MASK | DDRC_MSTR_GEARDOWN_MODE_MASK | DDRC_MSTR_EN_2T_TIMING_MODE_MASK | DDRC_MSTR_BURSTCHOP_MASK | DDRC_MSTR_LPDDR4_MASK | DDRC_MSTR_DDR4_MASK | DDRC_MSTR_LPDDR3_MASK | DDRC_MSTR_LPDDR2_MASK | DDRC_MSTR_DDR3_MASK |  0 );
2012
2013                 RegVal = ((0x00000001U << DDRC_MSTR_DEVICE_CONFIG_SHIFT
2014                         | 0x00000000U << DDRC_MSTR_FREQUENCY_MODE_SHIFT
2015                         | 0x00000001U << DDRC_MSTR_ACTIVE_RANKS_SHIFT
2016                         | 0x00000004U << DDRC_MSTR_BURST_RDWR_SHIFT
2017                         | 0x00000000U << DDRC_MSTR_DLL_OFF_MODE_SHIFT
2018                         | 0x00000000U << DDRC_MSTR_DATA_BUS_WIDTH_SHIFT
2019                         | 0x00000000U << DDRC_MSTR_GEARDOWN_MODE_SHIFT
2020                         | 0x00000000U << DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT
2021                         | 0x00000000U << DDRC_MSTR_BURSTCHOP_SHIFT
2022                         | 0x00000000U << DDRC_MSTR_LPDDR4_SHIFT
2023                         | 0x00000001U << DDRC_MSTR_DDR4_SHIFT
2024                         | 0x00000000U << DDRC_MSTR_LPDDR3_SHIFT
2025                         | 0x00000000U << DDRC_MSTR_LPDDR2_SHIFT
2026                         | 0x00000000U << DDRC_MSTR_DDR3_SHIFT
2027                         |  0 ) & RegMask); */
2028                 PSU_Mask_Write (DDRC_MSTR_OFFSET ,0xE30FBE3DU ,0x41040010U);
2029         /*############################################################################################################################ */
2030
2031                 /*Register : MRCTRL0 @ 0XFD070010</p>
2032
2033                 Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL
2034                  automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef
2035                 re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.
2036                 PSU_DDRC_MRCTRL0_MR_WR                                                          0x0
2037
2038                 Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010
2039                  - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD
2040                 R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a
2041                 dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well
2042                 s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou
2043                 put Inversion of RDIMMs.
2044                 PSU_DDRC_MRCTRL0_MR_ADDR                                                        0x0
2045
2046                 Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1
2047                  However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E
2048                 amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks
2049                  and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3
2050                 PSU_DDRC_MRCTRL0_MR_RANK                                                        0x3
2051
2052                 Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not.
2053                 or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca
2054                  be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared
2055                 o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi
2056                 n is not allowed - 1 - Software intervention is allowed
2057                 PSU_DDRC_MRCTRL0_SW_INIT_INT                                                    0x0
2058
2059                 Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode
2060                 PSU_DDRC_MRCTRL0_PDA_EN                                                         0x0
2061
2062                 Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR
2063                 PSU_DDRC_MRCTRL0_MPR_EN                                                         0x0
2064
2065                 Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re
2066                 d
2067                 PSU_DDRC_MRCTRL0_MR_TYPE                                                        0x0
2068
2069                 Mode Register Read/Write Control Register 0. Note: Do not enable more than one of the following fields simultaneously: - sw_i
2070                 it_int - pda_en - mpr_en
2071                 (OFFSET, MASK, VALUE)      (0XFD070010, 0x8000F03FU ,0x00000030U)
2072                 RegMask = (DDRC_MRCTRL0_MR_WR_MASK | DDRC_MRCTRL0_MR_ADDR_MASK | DDRC_MRCTRL0_MR_RANK_MASK | DDRC_MRCTRL0_SW_INIT_INT_MASK | DDRC_MRCTRL0_PDA_EN_MASK | DDRC_MRCTRL0_MPR_EN_MASK | DDRC_MRCTRL0_MR_TYPE_MASK |  0 );
2073
2074                 RegVal = ((0x00000000U << DDRC_MRCTRL0_MR_WR_SHIFT
2075                         | 0x00000000U << DDRC_MRCTRL0_MR_ADDR_SHIFT
2076                         | 0x00000003U << DDRC_MRCTRL0_MR_RANK_SHIFT
2077                         | 0x00000000U << DDRC_MRCTRL0_SW_INIT_INT_SHIFT
2078                         | 0x00000000U << DDRC_MRCTRL0_PDA_EN_SHIFT
2079                         | 0x00000000U << DDRC_MRCTRL0_MPR_EN_SHIFT
2080                         | 0x00000000U << DDRC_MRCTRL0_MR_TYPE_SHIFT
2081                         |  0 ) & RegMask); */
2082                 PSU_Mask_Write (DDRC_MRCTRL0_OFFSET ,0x8000F03FU ,0x00000030U);
2083         /*############################################################################################################################ */
2084
2085                 /*Register : DERATEEN @ 0XFD070020</p>
2086
2087                 Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4
2088                  Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi
2089                 g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer.
2090                 PSU_DDRC_DERATEEN_RC_DERATE_VALUE                                               0x3
2091
2092                 Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f
2093                 r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.
2094                 PSU_DDRC_DERATEEN_DERATE_BYTE                                                   0x0
2095
2096                 Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD
2097                 4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1
2098                 for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not.
2099                 PSU_DDRC_DERATEEN_DERATE_VALUE                                                  0x0
2100
2101                 Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value.
2102                 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4
2103                 mode.
2104                 PSU_DDRC_DERATEEN_DERATE_ENABLE                                                 0x0
2105
2106                 Temperature Derate Enable Register
2107                 (OFFSET, MASK, VALUE)      (0XFD070020, 0x000003F3U ,0x00000300U)
2108                 RegMask = (DDRC_DERATEEN_RC_DERATE_VALUE_MASK | DDRC_DERATEEN_DERATE_BYTE_MASK | DDRC_DERATEEN_DERATE_VALUE_MASK | DDRC_DERATEEN_DERATE_ENABLE_MASK |  0 );
2109
2110                 RegVal = ((0x00000003U << DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT
2111                         | 0x00000000U << DDRC_DERATEEN_DERATE_BYTE_SHIFT
2112                         | 0x00000000U << DDRC_DERATEEN_DERATE_VALUE_SHIFT
2113                         | 0x00000000U << DDRC_DERATEEN_DERATE_ENABLE_SHIFT
2114                         |  0 ) & RegMask); */
2115                 PSU_Mask_Write (DDRC_DERATEEN_OFFSET ,0x000003F3U ,0x00000300U);
2116         /*############################################################################################################################ */
2117
2118                 /*Register : DERATEINT @ 0XFD070024</p>
2119
2120                 Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP
2121                 DR3/LPDDR4. This register must not be set to zero
2122                 PSU_DDRC_DERATEINT_MR4_READ_INTERVAL                                            0x800000
2123
2124                 Temperature Derate Interval Register
2125                 (OFFSET, MASK, VALUE)      (0XFD070024, 0xFFFFFFFFU ,0x00800000U)
2126                 RegMask = (DDRC_DERATEINT_MR4_READ_INTERVAL_MASK |  0 );
2127
2128                 RegVal = ((0x00800000U << DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT
2129                         |  0 ) & RegMask); */
2130                 PSU_Mask_Write (DDRC_DERATEINT_OFFSET ,0xFFFFFFFFU ,0x00800000U);
2131         /*############################################################################################################################ */
2132
2133                 /*Register : PWRCTL @ 0XFD070030</p>
2134
2135                 Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f
2136                 r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state -
2137                  - Allow transition from Self refresh state
2138                 PSU_DDRC_PWRCTL_STAY_IN_SELFREF                                                 0x0
2139
2140                 A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP
2141                 M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft
2142                 are Exit from Self Refresh
2143                 PSU_DDRC_PWRCTL_SELFREF_SW                                                      0x0
2144
2145                 When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m
2146                 st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For
2147                 on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter
2148                 DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY.
2149                 PSU_DDRC_PWRCTL_MPSM_EN                                                         0x0
2150
2151                 Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable
2152                 is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD
2153                 4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in
2154                 ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass
2155                 rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop)
2156                 PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE                                         0x0
2157
2158                 When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re
2159                 et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down
2160                 xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe
2161                  should not be set to 1. FOR PERFORMANCE ONLY.
2162                 PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN                                                0x0
2163
2164                 If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P
2165                 RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation.
2166                 PSU_DDRC_PWRCTL_POWERDOWN_EN                                                    0x0
2167
2168                 If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se
2169                 f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation.
2170                 PSU_DDRC_PWRCTL_SELFREF_EN                                                      0x0
2171
2172                 Low Power Control Register
2173                 (OFFSET, MASK, VALUE)      (0XFD070030, 0x0000007FU ,0x00000000U)
2174                 RegMask = (DDRC_PWRCTL_STAY_IN_SELFREF_MASK | DDRC_PWRCTL_SELFREF_SW_MASK | DDRC_PWRCTL_MPSM_EN_MASK | DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK | DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK | DDRC_PWRCTL_POWERDOWN_EN_MASK | DDRC_PWRCTL_SELFREF_EN_MASK |  0 );
2175
2176                 RegVal = ((0x00000000U << DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT
2177                         | 0x00000000U << DDRC_PWRCTL_SELFREF_SW_SHIFT
2178                         | 0x00000000U << DDRC_PWRCTL_MPSM_EN_SHIFT
2179                         | 0x00000000U << DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT
2180                         | 0x00000000U << DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT
2181                         | 0x00000000U << DDRC_PWRCTL_POWERDOWN_EN_SHIFT
2182                         | 0x00000000U << DDRC_PWRCTL_SELFREF_EN_SHIFT
2183                         |  0 ) & RegMask); */
2184                 PSU_Mask_Write (DDRC_PWRCTL_OFFSET ,0x0000007FU ,0x00000000U);
2185         /*############################################################################################################################ */
2186
2187                 /*Register : PWRTMG @ 0XFD070034</p>
2188
2189                 After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in
2190                 he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
2191                 PSU_DDRC_PWRTMG_SELFREF_TO_X32                                                  0x40
2192
2193                 Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed
2194                 ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul
2195                 iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY.
2196                 PSU_DDRC_PWRTMG_T_DPD_X4096                                                     0x84
2197
2198                 After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th
2199                  PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.
2200                 PSU_DDRC_PWRTMG_POWERDOWN_TO_X32                                                0x10
2201
2202                 Low Power Timing Register
2203                 (OFFSET, MASK, VALUE)      (0XFD070034, 0x00FFFF1FU ,0x00408410U)
2204                 RegMask = (DDRC_PWRTMG_SELFREF_TO_X32_MASK | DDRC_PWRTMG_T_DPD_X4096_MASK | DDRC_PWRTMG_POWERDOWN_TO_X32_MASK |  0 );
2205
2206                 RegVal = ((0x00000040U << DDRC_PWRTMG_SELFREF_TO_X32_SHIFT
2207                         | 0x00000084U << DDRC_PWRTMG_T_DPD_X4096_SHIFT
2208                         | 0x00000010U << DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT
2209                         |  0 ) & RegMask); */
2210                 PSU_Mask_Write (DDRC_PWRTMG_OFFSET ,0x00FFFF1FU ,0x00408410U);
2211         /*############################################################################################################################ */
2212
2213                 /*Register : RFSHCTL0 @ 0XFD070050</p>
2214
2215                 Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu
2216                 d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2
2217                  It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32
2218                 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_
2219                 om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks.
2220                 PSU_DDRC_RFSHCTL0_REFRESH_MARGIN                                                0x2
2221
2222                 If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst
2223                 1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres
2224                  would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF
2225                 HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe
2226                 formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is
2227                 ued to the uMCTL2. FOR PERFORMANCE ONLY.
2228                 PSU_DDRC_RFSHCTL0_REFRESH_TO_X32                                                0x10
2229
2230                 The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re
2231                 reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re
2232                 reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for
2233                 RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe
2234                 . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se
2235                 tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r
2236                 fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea
2237                 ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd
2238                 tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat
2239                 d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY
2240                 initiated update is complete.
2241                 PSU_DDRC_RFSHCTL0_REFRESH_BURST                                                 0x0
2242
2243                 - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n
2244                 t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to
2245                 support LPDDR2/LPDDR3/LPDDR4
2246                 PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH                                              0x0
2247
2248                 Refresh Control Register 0
2249                 (OFFSET, MASK, VALUE)      (0XFD070050, 0x00F1F1F4U ,0x00210000U)
2250                 RegMask = (DDRC_RFSHCTL0_REFRESH_MARGIN_MASK | DDRC_RFSHCTL0_REFRESH_TO_X32_MASK | DDRC_RFSHCTL0_REFRESH_BURST_MASK | DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK |  0 );
2251
2252                 RegVal = ((0x00000002U << DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT
2253                         | 0x00000010U << DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT
2254                         | 0x00000000U << DDRC_RFSHCTL0_REFRESH_BURST_SHIFT
2255                         | 0x00000000U << DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT
2256                         |  0 ) & RegMask); */
2257                 PSU_Mask_Write (DDRC_RFSHCTL0_OFFSET ,0x00F1F1F4U ,0x00210000U);
2258         /*############################################################################################################################ */
2259
2260                 /*Register : RFSHCTL3 @ 0XFD070060</p>
2261
2262                 Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (
2263                 ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup
2264                 orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in
2265                 self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in
2266                 uture version of the uMCTL2.
2267                 PSU_DDRC_RFSHCTL3_REFRESH_MODE                                                  0x0
2268
2269                 Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value
2270                 s automatically updated when exiting reset, so it does not need to be toggled initially.
2271                 PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL                                          0x0
2272
2273                 When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u
2274                 ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis
2275                 auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry
2276                 is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'.
2277                 his register field is changeable on the fly.
2278                 PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH                                              0x1
2279
2280                 Refresh Control Register 3
2281                 (OFFSET, MASK, VALUE)      (0XFD070060, 0x00000073U ,0x00000001U)
2282                 RegMask = (DDRC_RFSHCTL3_REFRESH_MODE_MASK | DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK | DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK |  0 );
2283
2284                 RegVal = ((0x00000000U << DDRC_RFSHCTL3_REFRESH_MODE_SHIFT
2285                         | 0x00000000U << DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT
2286                         | 0x00000001U << DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT
2287                         |  0 ) & RegMask); */
2288                 PSU_Mask_Write (DDRC_RFSHCTL3_OFFSET ,0x00000073U ,0x00000001U);
2289         /*############################################################################################################################ */
2290
2291                 /*Register : RFSHTMG @ 0XFD070064</p>
2292
2293                 tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio
2294                  for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0
2295                 , this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should
2296                 e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va
2297                 ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value
2298                 programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS
2299                 TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks.
2300                 PSU_DDRC_RFSHTMG_T_RFC_NOM_X32                                                  0x82
2301
2302                 Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the
2303                 REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not
2304                  - 0 - tREFBW parameter not used - 1 - tREFBW parameter used
2305                 PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN                                               0x1
2306
2307                 tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t
2308                  RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L
2309                 DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin
2310                  per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above
2311                 equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app
2312                 opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks.
2313                 PSU_DDRC_RFSHTMG_T_RFC_MIN                                                      0x8b
2314
2315                 Refresh Timing Register
2316                 (OFFSET, MASK, VALUE)      (0XFD070064, 0x0FFF83FFU ,0x0082808BU)
2317                 RegMask = (DDRC_RFSHTMG_T_RFC_NOM_X32_MASK | DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK | DDRC_RFSHTMG_T_RFC_MIN_MASK |  0 );
2318
2319                 RegVal = ((0x00000082U << DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT
2320                         | 0x00000001U << DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT
2321                         | 0x0000008BU << DDRC_RFSHTMG_T_RFC_MIN_SHIFT
2322                         |  0 ) & RegMask); */
2323                 PSU_Mask_Write (DDRC_RFSHTMG_OFFSET ,0x0FFF83FFU ,0x0082808BU);
2324         /*############################################################################################################################ */
2325
2326                 /*Register : ECCCFG0 @ 0XFD070070</p>
2327
2328                 Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined
2329                 PSU_DDRC_ECCCFG0_DIS_SCRUB                                                      0x1
2330
2331                 ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur
2332                  use
2333                 PSU_DDRC_ECCCFG0_ECC_MODE                                                       0x0
2334
2335                 ECC Configuration Register 0
2336                 (OFFSET, MASK, VALUE)      (0XFD070070, 0x00000017U ,0x00000010U)
2337                 RegMask = (DDRC_ECCCFG0_DIS_SCRUB_MASK | DDRC_ECCCFG0_ECC_MODE_MASK |  0 );
2338
2339                 RegVal = ((0x00000001U << DDRC_ECCCFG0_DIS_SCRUB_SHIFT
2340                         | 0x00000000U << DDRC_ECCCFG0_ECC_MODE_SHIFT
2341                         |  0 ) & RegMask); */
2342                 PSU_Mask_Write (DDRC_ECCCFG0_OFFSET ,0x00000017U ,0x00000010U);
2343         /*############################################################################################################################ */
2344
2345                 /*Register : ECCCFG1 @ 0XFD070074</p>
2346
2347                 Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison
2348                 ng, if ECCCFG1.data_poison_en=1
2349                 PSU_DDRC_ECCCFG1_DATA_POISON_BIT                                                0x0
2350
2351                 Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers
2352                 PSU_DDRC_ECCCFG1_DATA_POISON_EN                                                 0x0
2353
2354                 ECC Configuration Register 1
2355                 (OFFSET, MASK, VALUE)      (0XFD070074, 0x00000003U ,0x00000000U)
2356                 RegMask = (DDRC_ECCCFG1_DATA_POISON_BIT_MASK | DDRC_ECCCFG1_DATA_POISON_EN_MASK |  0 );
2357
2358                 RegVal = ((0x00000000U << DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT
2359                         | 0x00000000U << DDRC_ECCCFG1_DATA_POISON_EN_SHIFT
2360                         |  0 ) & RegMask); */
2361                 PSU_Mask_Write (DDRC_ECCCFG1_OFFSET ,0x00000003U ,0x00000000U);
2362         /*############################################################################################################################ */
2363
2364                 /*Register : CRCPARCTL1 @ 0XFD0700C4</p>
2365
2366                 The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of
2367                 the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY
2368                 pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC
2369                 L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_
2370                 dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo
2371                 e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks
2372                 PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT                                             0x10
2373
2374                 After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR
2375                 M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins
2376                 the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin
2377                 the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P
2378                 RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte
2379                  handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P
2380                 rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re
2381                 ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in
2382                 he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is
2383                 one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in
2384                 PR Page 1 should be treated as 'Don't care'.
2385                 PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW                                           0x1
2386
2387                 - 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o
2388                  CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o
2389                  disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1)
2390                 PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE                                     0x0
2391
2392                 CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur
2393                 d to support DDR4.
2394                 PSU_DDRC_CRCPARCTL1_CRC_INC_DM                                                  0x0
2395
2396                 CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th
2397                  CRC mode register setting in the DRAM.
2398                 PSU_DDRC_CRCPARCTL1_CRC_ENABLE                                                  0x0
2399
2400                 C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of
2401                 /A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t
2402                 is register should be 1.
2403                 PSU_DDRC_CRCPARCTL1_PARITY_ENABLE                                               0x0
2404
2405                 CRC Parity Control Register1
2406                 (OFFSET, MASK, VALUE)      (0XFD0700C4, 0x3F000391U ,0x10000200U)
2407                 RegMask = (DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK | DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK | DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK | DDRC_CRCPARCTL1_CRC_INC_DM_MASK | DDRC_CRCPARCTL1_CRC_ENABLE_MASK | DDRC_CRCPARCTL1_PARITY_ENABLE_MASK |  0 );
2408
2409                 RegVal = ((0x00000010U << DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT
2410                         | 0x00000001U << DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT
2411                         | 0x00000000U << DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT
2412                         | 0x00000000U << DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT
2413                         | 0x00000000U << DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT
2414                         | 0x00000000U << DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT
2415                         |  0 ) & RegMask); */
2416                 PSU_Mask_Write (DDRC_CRCPARCTL1_OFFSET ,0x3F000391U ,0x10000200U);
2417         /*############################################################################################################################ */
2418
2419                 /*Register : CRCPARCTL2 @ 0XFD0700C8</p>
2420
2421                 Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values
2422                  - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte
2423                 er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.
2424                 PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX                                          0x40
2425
2426                 Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: -
2427                 tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer
2428                 value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.
2429                 PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX                                          0x5
2430
2431                 Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be
2432                 ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis
2433                 er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy
2434                 les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er
2435                 or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme
2436                 ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON
2437                 max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en
2438                 bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK)
2439                 + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de
2440                 ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The
2441                 ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set
2442                 to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-
2443                  Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D
2444                 PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM
2445                 _FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C
2446                 C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo
2447                 e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte
2448                  bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP
2449                 H-6 Values of 0, 1 and 2 are illegal.
2450                 PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4                                0x1f
2451
2452                 CRC Parity Control Register2
2453                 (OFFSET, MASK, VALUE)      (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU)
2454                 RegMask = (DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK | DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK | DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK |  0 );
2455
2456                 RegVal = ((0x00000040U << DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT
2457                         | 0x00000005U << DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT
2458                         | 0x0000001FU << DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT
2459                         |  0 ) & RegMask); */
2460                 PSU_Mask_Write (DDRC_CRCPARCTL2_OFFSET ,0x01FF1F3FU ,0x0040051FU);
2461         /*############################################################################################################################ */
2462
2463                 /*Register : INIT0 @ 0XFD0700D0</p>
2464
2465                 If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u
2466                  in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip
2467                 ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll
2468                 r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported
2469                 or LPDDR4 in this version of the uMCTL2.
2470                 PSU_DDRC_INIT0_SKIP_DRAM_INIT                                                   0x0
2471
2472                 Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires
2473                  400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr
2474                 grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M
2475                 MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value.
2476                 PSU_DDRC_INIT0_POST_CKE_X1024                                                   0x2
2477
2478                 Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2
2479                 pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4:
2480                 tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u
2481                  to next integer value.
2482                 PSU_DDRC_INIT0_PRE_CKE_X1024                                                    0x106
2483
2484                 SDRAM Initialization Register 0
2485                 (OFFSET, MASK, VALUE)      (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U)
2486                 RegMask = (DDRC_INIT0_SKIP_DRAM_INIT_MASK | DDRC_INIT0_POST_CKE_X1024_MASK | DDRC_INIT0_PRE_CKE_X1024_MASK |  0 );
2487
2488                 RegVal = ((0x00000000U << DDRC_INIT0_SKIP_DRAM_INIT_SHIFT
2489                         | 0x00000002U << DDRC_INIT0_POST_CKE_X1024_SHIFT
2490                         | 0x00000106U << DDRC_INIT0_PRE_CKE_X1024_SHIFT
2491                         |  0 ) & RegMask); */
2492                 PSU_Mask_Write (DDRC_INIT0_OFFSET ,0xC3FF0FFFU ,0x00020106U);
2493         /*############################################################################################################################ */
2494
2495                 /*Register : INIT1 @ 0XFD0700D4</p>
2496
2497                 Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or
2498                 LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1
2499                 PSU_DDRC_INIT1_DRAM_RSTN_X1024                                                  0x2
2500
2501                 Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl
2502                 bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero.
2503                 PSU_DDRC_INIT1_FINAL_WAIT_X32                                                   0x0
2504
2505                 Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle
2506                 . There is no known specific requirement for this; it may be set to zero.
2507                 PSU_DDRC_INIT1_PRE_OCD_X32                                                      0x0
2508
2509                 SDRAM Initialization Register 1
2510                 (OFFSET, MASK, VALUE)      (0XFD0700D4, 0x01FF7F0FU ,0x00020000U)
2511                 RegMask = (DDRC_INIT1_DRAM_RSTN_X1024_MASK | DDRC_INIT1_FINAL_WAIT_X32_MASK | DDRC_INIT1_PRE_OCD_X32_MASK |  0 );
2512
2513                 RegVal = ((0x00000002U << DDRC_INIT1_DRAM_RSTN_X1024_SHIFT
2514                         | 0x00000000U << DDRC_INIT1_FINAL_WAIT_X32_SHIFT
2515                         | 0x00000000U << DDRC_INIT1_PRE_OCD_X32_SHIFT
2516                         |  0 ) & RegMask); */
2517                 PSU_Mask_Write (DDRC_INIT1_OFFSET ,0x01FF7F0FU ,0x00020000U);
2518         /*############################################################################################################################ */
2519
2520                 /*Register : INIT2 @ 0XFD0700D8</p>
2521
2522                 Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles.
2523                 PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32                                             0x23
2524
2525                 Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc
2526                 e. LPDDR2/LPDDR3 typically requires 5 x tCK delay.
2527                 PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1                                              0x5
2528
2529                 SDRAM Initialization Register 2
2530                 (OFFSET, MASK, VALUE)      (0XFD0700D8, 0x0000FF0FU ,0x00002305U)
2531                 RegMask = (DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK | DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK |  0 );
2532
2533                 RegVal = ((0x00000023U << DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT
2534                         | 0x00000005U << DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT
2535                         |  0 ) & RegMask); */
2536                 PSU_Mask_Write (DDRC_INIT2_OFFSET ,0x0000FF0FU ,0x00002305U);
2537         /*############################################################################################################################ */
2538
2539                 /*Register : INIT3 @ 0XFD0700DC</p>
2540
2541                 DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately
2542                  DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1
2543                 register
2544                 PSU_DDRC_INIT3_MR                                                               0x930
2545
2546                 DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those
2547                 bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi
2548                  bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V
2549                 lue to write to MR2 register
2550                 PSU_DDRC_INIT3_EMR                                                              0x301
2551
2552                 SDRAM Initialization Register 3
2553                 (OFFSET, MASK, VALUE)      (0XFD0700DC, 0xFFFFFFFFU ,0x09300301U)
2554                 RegMask = (DDRC_INIT3_MR_MASK | DDRC_INIT3_EMR_MASK |  0 );
2555
2556                 RegVal = ((0x00000930U << DDRC_INIT3_MR_SHIFT
2557                         | 0x00000301U << DDRC_INIT3_EMR_SHIFT
2558                         |  0 ) & RegMask); */
2559                 PSU_Mask_Write (DDRC_INIT3_OFFSET ,0xFFFFFFFFU ,0x09300301U);
2560         /*############################################################################################################################ */
2561
2562                 /*Register : INIT4 @ 0XFD0700E0</p>
2563
2564                 DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3
2565                 egister mDDR: Unused
2566                 PSU_DDRC_INIT4_EMR2                                                             0x20
2567
2568                 DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to
2569                 rite to MR13 register
2570                 PSU_DDRC_INIT4_EMR3                                                             0x200
2571
2572                 SDRAM Initialization Register 4
2573                 (OFFSET, MASK, VALUE)      (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U)
2574                 RegMask = (DDRC_INIT4_EMR2_MASK | DDRC_INIT4_EMR3_MASK |  0 );
2575
2576                 RegVal = ((0x00000020U << DDRC_INIT4_EMR2_SHIFT
2577                         | 0x00000200U << DDRC_INIT4_EMR3_SHIFT
2578                         |  0 ) & RegMask); */
2579                 PSU_Mask_Write (DDRC_INIT4_OFFSET ,0xFFFFFFFFU ,0x00200200U);
2580         /*############################################################################################################################ */
2581
2582                 /*Register : INIT5 @ 0XFD0700E4</p>
2583
2584                 ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock
2585                 ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us.
2586                 PSU_DDRC_INIT5_DEV_ZQINIT_X32                                                   0x21
2587
2588                 Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD
2589                 3 typically requires 10 us.
2590                 PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024                                              0x4
2591
2592                 SDRAM Initialization Register 5
2593                 (OFFSET, MASK, VALUE)      (0XFD0700E4, 0x00FF03FFU ,0x00210004U)
2594                 RegMask = (DDRC_INIT5_DEV_ZQINIT_X32_MASK | DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK |  0 );
2595
2596                 RegVal = ((0x00000021U << DDRC_INIT5_DEV_ZQINIT_X32_SHIFT
2597                         | 0x00000004U << DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT
2598                         |  0 ) & RegMask); */
2599                 PSU_Mask_Write (DDRC_INIT5_OFFSET ,0x00FF03FFU ,0x00210004U);
2600         /*############################################################################################################################ */
2601
2602                 /*Register : INIT6 @ 0XFD0700E8</p>
2603
2604                 DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.
2605                 PSU_DDRC_INIT6_MR4                                                              0x0
2606
2607                 DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.
2608                 PSU_DDRC_INIT6_MR5                                                              0x6c0
2609
2610                 SDRAM Initialization Register 6
2611                 (OFFSET, MASK, VALUE)      (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U)
2612                 RegMask = (DDRC_INIT6_MR4_MASK | DDRC_INIT6_MR5_MASK |  0 );
2613
2614                 RegVal = ((0x00000000U << DDRC_INIT6_MR4_SHIFT
2615                         | 0x000006C0U << DDRC_INIT6_MR5_SHIFT
2616                         |  0 ) & RegMask); */
2617                 PSU_Mask_Write (DDRC_INIT6_OFFSET ,0xFFFFFFFFU ,0x000006C0U);
2618         /*############################################################################################################################ */
2619
2620                 /*Register : INIT7 @ 0XFD0700EC</p>
2621
2622                 DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.
2623                 PSU_DDRC_INIT7_MR6                                                              0x819
2624
2625                 SDRAM Initialization Register 7
2626                 (OFFSET, MASK, VALUE)      (0XFD0700EC, 0xFFFF0000U ,0x08190000U)
2627                 RegMask = (DDRC_INIT7_MR6_MASK |  0 );
2628
2629                 RegVal = ((0x00000819U << DDRC_INIT7_MR6_SHIFT
2630                         |  0 ) & RegMask); */
2631                 PSU_Mask_Write (DDRC_INIT7_OFFSET ,0xFFFF0000U ,0x08190000U);
2632         /*############################################################################################################################ */
2633
2634                 /*Register : DIMMCTL @ 0XFD0700F0</p>
2635
2636                 Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab
2637                 ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i
2638                  address mirroring is enabled.
2639                 PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING                                          0x0
2640
2641                 Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
2642                  be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output
2643                 nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no
2644                 effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena
2645                 led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled
2646                 PSU_DDRC_DIMMCTL_MRS_BG1_EN                                                     0x1
2647
2648                 Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
2649                  be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled,
2650                 his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address
2651                 f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled
2652                 PSU_DDRC_DIMMCTL_MRS_A17_EN                                                     0x0
2653
2654                 Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default,
2655                 which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17,
2656                 A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi
2657                 lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated.
2658                 or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi
2659                  has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out
2660                 ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs.
2661                 PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN                                             0x0
2662
2663                 Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD
2664                 4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits
2665                 re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t
2666                 at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe
2667                 sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar
2668                  swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr
2669                 ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3
2670                 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid,
2671                 hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d
2672                 ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do
2673                 not implement address mirroring
2674                 PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN                                              0x0
2675
2676                 Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD
2677                 R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M
2678                 CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t
2679                  each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses
2680                 PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN                                             0x0
2681
2682                 DIMM Control Register
2683                 (OFFSET, MASK, VALUE)      (0XFD0700F0, 0x0000003FU ,0x00000010U)
2684                 RegMask = (DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK | DDRC_DIMMCTL_MRS_BG1_EN_MASK | DDRC_DIMMCTL_MRS_A17_EN_MASK | DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK | DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK | DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK |  0 );
2685
2686                 RegVal = ((0x00000000U << DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT
2687                         | 0x00000001U << DDRC_DIMMCTL_MRS_BG1_EN_SHIFT
2688                         | 0x00000000U << DDRC_DIMMCTL_MRS_A17_EN_SHIFT
2689                         | 0x00000000U << DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT
2690                         | 0x00000000U << DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT
2691                         | 0x00000000U << DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT
2692                         |  0 ) & RegMask); */
2693                 PSU_Mask_Write (DDRC_DIMMCTL_OFFSET ,0x0000003FU ,0x00000010U);
2694         /*############################################################################################################################ */
2695
2696                 /*Register : RANKCTL @ 0XFD0700F4</p>
2697
2698                 Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
2699                 e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c
2700                 nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs
2701                 ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa
2702                 ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed
2703                 n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi
2704                 ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement
2705                 or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u
2706                  to the next integer.
2707                 PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP                                               0x6
2708
2709                 Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
2710                 e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co
2711                 sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg
2712                 p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl
2713                 ), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing
2714                 requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r
2715                 quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and
2716                 ound it up to the next integer.
2717                 PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP                                               0x6
2718
2719                 Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ
2720                 nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content
2721                 on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl
2722                 -by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran
2723                 _rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f
2724                 om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv
2725                 ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to
2726                 llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair
2727                 ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as
2728                 ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x
2729                 . FOR PERFORMANCE ONLY.
2730                 PSU_DDRC_RANKCTL_MAX_RANK_RD                                                    0xf
2731
2732                 Rank Control Register
2733                 (OFFSET, MASK, VALUE)      (0XFD0700F4, 0x00000FFFU ,0x0000066FU)
2734                 RegMask = (DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK | DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK | DDRC_RANKCTL_MAX_RANK_RD_MASK |  0 );
2735
2736                 RegVal = ((0x00000006U << DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT
2737                         | 0x00000006U << DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT
2738                         | 0x0000000FU << DDRC_RANKCTL_MAX_RANK_RD_SHIFT
2739                         |  0 ) & RegMask); */
2740                 PSU_Mask_Write (DDRC_RANKCTL_OFFSET ,0x00000FFFU ,0x0000066FU);
2741         /*############################################################################################################################ */
2742
2743                 /*Register : DRAMTMG0 @ 0XFD070100</p>
2744
2745                 Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles
2746                  15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th
2747                  value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR =
2748                 Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this
2749                 arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations
2750                 with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.
2751                 PSU_DDRC_DRAMTMG0_WR2PRE                                                        0x11
2752
2753                 tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated
2754                 in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next
2755                 nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks
2756                 PSU_DDRC_DRAMTMG0_T_FAW                                                         0xc
2757
2758                 tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi
2759                 imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2
2760                  No rounding up. Unit: Multiples of 1024 clocks.
2761                 PSU_DDRC_DRAMTMG0_T_RAS_MAX                                                     0x24
2762
2763                 tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode,
2764                 rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t
2765                  (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks
2766                 PSU_DDRC_DRAMTMG0_T_RAS_MIN                                                     0x12
2767
2768                 SDRAM Timing Register 0
2769                 (OFFSET, MASK, VALUE)      (0XFD070100, 0x7F3F7F3FU ,0x110C2412U)
2770                 RegMask = (DDRC_DRAMTMG0_WR2PRE_MASK | DDRC_DRAMTMG0_T_FAW_MASK | DDRC_DRAMTMG0_T_RAS_MAX_MASK | DDRC_DRAMTMG0_T_RAS_MIN_MASK |  0 );
2771
2772                 RegVal = ((0x00000011U << DDRC_DRAMTMG0_WR2PRE_SHIFT
2773                         | 0x0000000CU << DDRC_DRAMTMG0_T_FAW_SHIFT
2774                         | 0x00000024U << DDRC_DRAMTMG0_T_RAS_MAX_SHIFT
2775                         | 0x00000012U << DDRC_DRAMTMG0_T_RAS_MIN_SHIFT
2776                         |  0 ) & RegMask); */
2777                 PSU_Mask_Write (DDRC_DRAMTMG0_OFFSET ,0x7F3F7F3FU ,0x110C2412U);
2778         /*############################################################################################################################ */
2779
2780                 /*Register : DRAMTMG1 @ 0XFD070104</p>
2781
2782                 tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi
2783                  is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2,
2784                 rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks
2785                 PSU_DDRC_DRAMTMG1_T_XP                                                          0x4
2786
2787                 tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D
2788                 R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2
2789                 S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL
2790                 2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf
2791                 gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val
2792                 e. Unit: Clocks.
2793                 PSU_DDRC_DRAMTMG1_RD2PRE                                                        0x4
2794
2795                 tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun
2796                  up to next integer value. Unit: Clocks.
2797                 PSU_DDRC_DRAMTMG1_T_RC                                                          0x19
2798
2799                 SDRAM Timing Register 1
2800                 (OFFSET, MASK, VALUE)      (0XFD070104, 0x001F1F7FU ,0x00040419U)
2801                 RegMask = (DDRC_DRAMTMG1_T_XP_MASK | DDRC_DRAMTMG1_RD2PRE_MASK | DDRC_DRAMTMG1_T_RC_MASK |  0 );
2802
2803                 RegVal = ((0x00000004U << DDRC_DRAMTMG1_T_XP_SHIFT
2804                         | 0x00000004U << DDRC_DRAMTMG1_RD2PRE_SHIFT
2805                         | 0x00000019U << DDRC_DRAMTMG1_T_RC_SHIFT
2806                         |  0 ) & RegMask); */
2807                 PSU_Mask_Write (DDRC_DRAMTMG1_OFFSET ,0x001F1F7FU ,0x00040419U);
2808         /*############################################################################################################################ */
2809
2810                 /*Register : DRAMTMG2 @ 0XFD070108</p>
2811
2812                 Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s
2813                 t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e
2814                 tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above
2815                 equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ
2816                  is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
2817                 PSU_DDRC_DRAMTMG2_WRITE_LATENCY                                                 0x7
2818
2819                 Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if
2820                 using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For
2821                 onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte
2822                 er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci
2823                 s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
2824                 PSU_DDRC_DRAMTMG2_READ_LATENCY                                                  0x8
2825
2826                 DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL
2827                 PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B
2828                 /2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include
2829                 time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL =
2830                 urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l
2831                 tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L
2832                 DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf
2833                 gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.
2834                 PSU_DDRC_DRAMTMG2_RD2WR                                                         0x6
2835
2836                 DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba
2837                 k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al
2838                  per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs
2839                  length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re
2840                 d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman
2841                  delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu
2842                 ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.
2843                 PSU_DDRC_DRAMTMG2_WR2RD                                                         0xe
2844
2845                 SDRAM Timing Register 2
2846                 (OFFSET, MASK, VALUE)      (0XFD070108, 0x3F3F3F3FU ,0x0708060EU)
2847                 RegMask = (DDRC_DRAMTMG2_WRITE_LATENCY_MASK | DDRC_DRAMTMG2_READ_LATENCY_MASK | DDRC_DRAMTMG2_RD2WR_MASK | DDRC_DRAMTMG2_WR2RD_MASK |  0 );
2848
2849                 RegVal = ((0x00000007U << DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT
2850                         | 0x00000008U << DDRC_DRAMTMG2_READ_LATENCY_SHIFT
2851                         | 0x00000006U << DDRC_DRAMTMG2_RD2WR_SHIFT
2852                         | 0x0000000EU << DDRC_DRAMTMG2_WR2RD_SHIFT
2853                         |  0 ) & RegMask); */
2854                 PSU_Mask_Write (DDRC_DRAMTMG2_OFFSET ,0x3F3F3F3FU ,0x0708060EU);
2855         /*############################################################################################################################ */
2856
2857                 /*Register : DRAMTMG3 @ 0XFD07010C</p>
2858
2859                 Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o
2860                  LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW
2861                 nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i
2862                  used for the time from a MRW/MRR to a MRW/MRR.
2863                 PSU_DDRC_DRAMTMG3_T_MRW                                                         0x5
2864
2865                 tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time
2866                 rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c
2867                 nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD
2868                 4 is used, set to tMRD_PAR(tMOD+PL) instead.
2869                 PSU_DDRC_DRAMTMG3_T_MRD                                                         0x4
2870
2871                 tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari
2872                 y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer
2873                  if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO
2874                  + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip.
2875                 PSU_DDRC_DRAMTMG3_T_MOD                                                         0xc
2876
2877                 SDRAM Timing Register 3
2878                 (OFFSET, MASK, VALUE)      (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU)
2879                 RegMask = (DDRC_DRAMTMG3_T_MRW_MASK | DDRC_DRAMTMG3_T_MRD_MASK | DDRC_DRAMTMG3_T_MOD_MASK |  0 );
2880
2881                 RegVal = ((0x00000005U << DDRC_DRAMTMG3_T_MRW_SHIFT
2882                         | 0x00000004U << DDRC_DRAMTMG3_T_MRD_SHIFT
2883                         | 0x0000000CU << DDRC_DRAMTMG3_T_MOD_SHIFT
2884                         |  0 ) & RegMask); */
2885                 PSU_Mask_Write (DDRC_DRAMTMG3_OFFSET ,0x3FF3F3FFU ,0x0050400CU);
2886         /*############################################################################################################################ */
2887
2888                 /*Register : DRAMTMG4 @ 0XFD070110</p>
2889
2890                 tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog
2891                 am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im
2892                 lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.
2893                 PSU_DDRC_DRAMTMG4_T_RCD                                                         0x8
2894
2895                 DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum
2896                 time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou
2897                 d it up to the next integer value. Unit: clocks.
2898                 PSU_DDRC_DRAMTMG4_T_CCD                                                         0x3
2899
2900                 DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee
2901                  activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round
2902                 it up to the next integer value. Unit: Clocks.
2903                 PSU_DDRC_DRAMTMG4_T_RRD                                                         0x3
2904
2905                 tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU
2906                 (tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO
2907                 2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
2908                 PSU_DDRC_DRAMTMG4_T_RP                                                          0x9
2909
2910                 SDRAM Timing Register 4
2911                 (OFFSET, MASK, VALUE)      (0XFD070110, 0x1F0F0F1FU ,0x08030309U)
2912                 RegMask = (DDRC_DRAMTMG4_T_RCD_MASK | DDRC_DRAMTMG4_T_CCD_MASK | DDRC_DRAMTMG4_T_RRD_MASK | DDRC_DRAMTMG4_T_RP_MASK |  0 );
2913
2914                 RegVal = ((0x00000008U << DDRC_DRAMTMG4_T_RCD_SHIFT
2915                         | 0x00000003U << DDRC_DRAMTMG4_T_CCD_SHIFT
2916                         | 0x00000003U << DDRC_DRAMTMG4_T_RRD_SHIFT
2917                         | 0x00000009U << DDRC_DRAMTMG4_T_RP_SHIFT
2918                         |  0 ) & RegMask); */
2919                 PSU_Mask_Write (DDRC_DRAMTMG4_OFFSET ,0x1F0F0F1FU ,0x08030309U);
2920         /*############################################################################################################################ */
2921
2922                 /*Register : DRAMTMG5 @ 0XFD070114</p>
2923
2924                 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab
2925                 e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4:
2926                 tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in
2927                 eger.
2928                 PSU_DDRC_DRAMTMG5_T_CKSRX                                                       0x6
2929
2930                 This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte
2931                  SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4:
2932                 ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up
2933                 to next integer.
2934                 PSU_DDRC_DRAMTMG5_T_CKSRE                                                       0x6
2935
2936                 Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se
2937                 tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE
2938                  1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege
2939                 .
2940                 PSU_DDRC_DRAMTMG5_T_CKESR                                                       0x4
2941
2942                 Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of
2943                 CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set
2944                 his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th
2945                  next integer value. Unit: Clocks.
2946                 PSU_DDRC_DRAMTMG5_T_CKE                                                         0x3
2947
2948                 SDRAM Timing Register 5
2949                 (OFFSET, MASK, VALUE)      (0XFD070114, 0x0F0F3F1FU ,0x06060403U)
2950                 RegMask = (DDRC_DRAMTMG5_T_CKSRX_MASK | DDRC_DRAMTMG5_T_CKSRE_MASK | DDRC_DRAMTMG5_T_CKESR_MASK | DDRC_DRAMTMG5_T_CKE_MASK |  0 );
2951
2952                 RegVal = ((0x00000006U << DDRC_DRAMTMG5_T_CKSRX_SHIFT
2953                         | 0x00000006U << DDRC_DRAMTMG5_T_CKSRE_SHIFT
2954                         | 0x00000004U << DDRC_DRAMTMG5_T_CKESR_SHIFT
2955                         | 0x00000003U << DDRC_DRAMTMG5_T_CKE_SHIFT
2956                         |  0 ) & RegMask); */
2957                 PSU_Mask_Write (DDRC_DRAMTMG5_OFFSET ,0x0F0F3F1FU ,0x06060403U);
2958         /*############################################################################################################################ */
2959
2960                 /*Register : DRAMTMG6 @ 0XFD070118</p>
2961
2962                 This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after
2963                 PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom
2964                 ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3
2965                 devices.
2966                 PSU_DDRC_DRAMTMG6_T_CKDPDE                                                      0x1
2967
2968                 This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock
2969                 table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr
2970                 gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD
2971                 R or LPDDR2 devices.
2972                 PSU_DDRC_DRAMTMG6_T_CKDPDX                                                      0x1
2973
2974                 This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the
2975                 lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP +
2976                 2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it
2977                 p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
2978                 PSU_DDRC_DRAMTMG6_T_CKCSX                                                       0x4
2979
2980                 SDRAM Timing Register 6
2981                 (OFFSET, MASK, VALUE)      (0XFD070118, 0x0F0F000FU ,0x01010004U)
2982                 RegMask = (DDRC_DRAMTMG6_T_CKDPDE_MASK | DDRC_DRAMTMG6_T_CKDPDX_MASK | DDRC_DRAMTMG6_T_CKCSX_MASK |  0 );
2983
2984                 RegVal = ((0x00000001U << DDRC_DRAMTMG6_T_CKDPDE_SHIFT
2985                         | 0x00000001U << DDRC_DRAMTMG6_T_CKDPDX_SHIFT
2986                         | 0x00000004U << DDRC_DRAMTMG6_T_CKCSX_SHIFT
2987                         |  0 ) & RegMask); */
2988                 PSU_Mask_Write (DDRC_DRAMTMG6_OFFSET ,0x0F0F000FU ,0x01010004U);
2989         /*############################################################################################################################ */
2990
2991                 /*Register : DRAMTMG7 @ 0XFD07011C</p>
2992
2993                 This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE.
2994                 ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t
2995                 is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L
2996                 DDR2/LPDDR3/LPDDR4 devices.
2997                 PSU_DDRC_DRAMTMG7_T_CKPDE                                                       0x6
2998
2999                 This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable
3000                 time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO=
3001                 , program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti
3002                 g mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
3003                 PSU_DDRC_DRAMTMG7_T_CKPDX                                                       0x6
3004
3005                 SDRAM Timing Register 7
3006                 (OFFSET, MASK, VALUE)      (0XFD07011C, 0x00000F0FU ,0x00000606U)
3007                 RegMask = (DDRC_DRAMTMG7_T_CKPDE_MASK | DDRC_DRAMTMG7_T_CKPDX_MASK |  0 );
3008
3009                 RegVal = ((0x00000006U << DDRC_DRAMTMG7_T_CKPDE_SHIFT
3010                         | 0x00000006U << DDRC_DRAMTMG7_T_CKPDX_SHIFT
3011                         |  0 ) & RegMask); */
3012                 PSU_Mask_Write (DDRC_DRAMTMG7_OFFSET ,0x00000F0FU ,0x00000606U);
3013         /*############################################################################################################################ */
3014
3015                 /*Register : DRAMTMG8 @ 0XFD070120</p>
3016
3017                 tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT
3018                 O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi
3019                  is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32.
3020                 PSU_DDRC_DRAMTMG8_T_XS_FAST_X32                                                 0x4
3021
3022                 tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_
3023                 ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note:
3024                 nsure this is less than or equal to t_xs_x32.
3025                 PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32                                                0x4
3026
3027                 tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the
3028                 bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
3029                 DR4 SDRAMs.
3030                 PSU_DDRC_DRAMTMG8_T_XS_DLL_X32                                                  0xd
3031
3032                 tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the
3033                 above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
3034                 DDR4 SDRAMs.
3035                 PSU_DDRC_DRAMTMG8_T_XS_X32                                                      0x6
3036
3037                 SDRAM Timing Register 8
3038                 (OFFSET, MASK, VALUE)      (0XFD070120, 0x7F7F7F7FU ,0x04040D06U)
3039                 RegMask = (DDRC_DRAMTMG8_T_XS_FAST_X32_MASK | DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK | DDRC_DRAMTMG8_T_XS_DLL_X32_MASK | DDRC_DRAMTMG8_T_XS_X32_MASK |  0 );
3040
3041                 RegVal = ((0x00000004U << DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT
3042                         | 0x00000004U << DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT
3043                         | 0x0000000DU << DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT
3044                         | 0x00000006U << DDRC_DRAMTMG8_T_XS_X32_SHIFT
3045                         |  0 ) & RegMask); */
3046                 PSU_Mask_Write (DDRC_DRAMTMG8_OFFSET ,0x7F7F7F7FU ,0x04040D06U);
3047         /*############################################################################################################################ */
3048
3049                 /*Register : DRAMTMG9 @ 0XFD070124</p>
3050
3051                 DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2
3052                 PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE                                              0x0
3053
3054                 tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a'
3055                 o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro
3056                 nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks.
3057                 PSU_DDRC_DRAMTMG9_T_CCD_S                                                       0x2
3058
3059                 tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_
3060                 ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D
3061                 R4. Unit: Clocks.
3062                 PSU_DDRC_DRAMTMG9_T_RRD_S                                                       0x2
3063
3064                 CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn
3065                 round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4
3066                  Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm
3067                 d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T
3068                 is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using
3069                 he above equation by 2, and round it up to next integer.
3070                 PSU_DDRC_DRAMTMG9_WR2RD_S                                                       0xb
3071
3072                 SDRAM Timing Register 9
3073                 (OFFSET, MASK, VALUE)      (0XFD070124, 0x40070F3FU ,0x0002020BU)
3074                 RegMask = (DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK | DDRC_DRAMTMG9_T_CCD_S_MASK | DDRC_DRAMTMG9_T_RRD_S_MASK | DDRC_DRAMTMG9_WR2RD_S_MASK |  0 );
3075
3076                 RegVal = ((0x00000000U << DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT
3077                         | 0x00000002U << DDRC_DRAMTMG9_T_CCD_S_SHIFT
3078                         | 0x00000002U << DDRC_DRAMTMG9_T_RRD_S_SHIFT
3079                         | 0x0000000BU << DDRC_DRAMTMG9_WR2RD_S_SHIFT
3080                         |  0 ) & RegMask); */
3081                 PSU_Mask_Write (DDRC_DRAMTMG9_OFFSET ,0x40070F3FU ,0x0002020BU);
3082         /*############################################################################################################################ */
3083
3084                 /*Register : DRAMTMG11 @ 0XFD07012C</p>
3085
3086                 tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program
3087                 this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult
3088                 ples of 32 clocks.
3089                 PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32                                            0x6f
3090
3091                 tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t
3092                  RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks.
3093                 PSU_DDRC_DRAMTMG11_T_MPX_LH                                                     0x7
3094
3095                 tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it
3096                 up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks.
3097                 PSU_DDRC_DRAMTMG11_T_MPX_S                                                      0x1
3098
3099                 tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F
3100                 r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i
3101                 teger.
3102                 PSU_DDRC_DRAMTMG11_T_CKMPE                                                      0xe
3103
3104                 SDRAM Timing Register 11
3105                 (OFFSET, MASK, VALUE)      (0XFD07012C, 0x7F1F031FU ,0x6F07010EU)
3106                 RegMask = (DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK | DDRC_DRAMTMG11_T_MPX_LH_MASK | DDRC_DRAMTMG11_T_MPX_S_MASK | DDRC_DRAMTMG11_T_CKMPE_MASK |  0 );
3107
3108                 RegVal = ((0x0000006FU << DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT
3109                         | 0x00000007U << DDRC_DRAMTMG11_T_MPX_LH_SHIFT
3110                         | 0x00000001U << DDRC_DRAMTMG11_T_MPX_S_SHIFT
3111                         | 0x0000000EU << DDRC_DRAMTMG11_T_CKMPE_SHIFT
3112                         |  0 ) & RegMask); */
3113                 PSU_Mask_Write (DDRC_DRAMTMG11_OFFSET ,0x7F1F031FU ,0x6F07010EU);
3114         /*############################################################################################################################ */
3115
3116                 /*Register : DRAMTMG12 @ 0XFD070130</p>
3117
3118                 tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_
3119                 REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value.
3120                 PSU_DDRC_DRAMTMG12_T_CMDCKE                                                     0x2
3121
3122                 tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM
3123                 /2) and round it up to next integer value.
3124                 PSU_DDRC_DRAMTMG12_T_CKEHCMD                                                    0x6
3125
3126                 tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th
3127                 s to (tMRD_PDA/2) and round it up to next integer value.
3128                 PSU_DDRC_DRAMTMG12_T_MRD_PDA                                                    0x8
3129
3130                 SDRAM Timing Register 12
3131                 (OFFSET, MASK, VALUE)      (0XFD070130, 0x00030F1FU ,0x00020608U)
3132                 RegMask = (DDRC_DRAMTMG12_T_CMDCKE_MASK | DDRC_DRAMTMG12_T_CKEHCMD_MASK | DDRC_DRAMTMG12_T_MRD_PDA_MASK |  0 );
3133
3134                 RegVal = ((0x00000002U << DDRC_DRAMTMG12_T_CMDCKE_SHIFT
3135                         | 0x00000006U << DDRC_DRAMTMG12_T_CKEHCMD_SHIFT
3136                         | 0x00000008U << DDRC_DRAMTMG12_T_MRD_PDA_SHIFT
3137                         |  0 ) & RegMask); */
3138                 PSU_Mask_Write (DDRC_DRAMTMG12_OFFSET ,0x00030F1FU ,0x00020608U);
3139         /*############################################################################################################################ */
3140
3141                 /*Register : ZQCTL0 @ 0XFD070180</p>
3142
3143                 - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is
3144                 ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s
3145                 ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
3146                 PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ                                                     0x1
3147
3148                 - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3
3149                 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power
3150                 own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo
3151                 ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
3152                 PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL                                                    0x0
3153
3154                 - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r
3155                 nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov
3156                 rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
3157                 PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED                                              0x0
3158
3159                 - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable
3160                 ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des
3161                 gns supporting DDR4 devices.
3162                 PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL                                                  0x0
3163
3164                 tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat
3165                 on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo
3166                 er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va
3167                 ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for
3168                 esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
3169                 PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP                                                   0x100
3170
3171                 tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC
3172                 ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t
3173                 e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic
3174                 s.
3175                 PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP                                                  0x40
3176
3177                 ZQ Control Register 0
3178                 (OFFSET, MASK, VALUE)      (0XFD070180, 0xF7FF03FFU ,0x81000040U)
3179                 RegMask = (DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK | DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK | DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK | DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK | DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK | DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK |  0 );
3180
3181                 RegVal = ((0x00000001U << DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT
3182                         | 0x00000000U << DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT
3183                         | 0x00000000U << DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT
3184                         | 0x00000000U << DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT
3185                         | 0x00000100U << DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT
3186                         | 0x00000040U << DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT
3187                         |  0 ) & RegMask); */
3188                 PSU_Mask_Write (DDRC_ZQCTL0_OFFSET ,0xF7FF03FFU ,0x81000040U);
3189         /*############################################################################################################################ */
3190
3191                 /*Register : ZQCTL1 @ 0XFD070184</p>
3192
3193                 tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati
3194                 ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is
3195                 nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.
3196                 PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP                                                  0x20
3197
3198                 Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/
3199                 PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs
3200                 upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
3201                 PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024                                       0x19707
3202
3203                 ZQ Control Register 1
3204                 (OFFSET, MASK, VALUE)      (0XFD070184, 0x3FFFFFFFU ,0x02019707U)
3205                 RegMask = (DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK | DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK |  0 );
3206
3207                 RegVal = ((0x00000020U << DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT
3208                         | 0x00019707U << DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT
3209                         |  0 ) & RegMask); */
3210                 PSU_Mask_Write (DDRC_ZQCTL1_OFFSET ,0x3FFFFFFFU ,0x02019707U);
3211         /*############################################################################################################################ */
3212
3213                 /*Register : DFITMG0 @ 0XFD070190</p>
3214
3215                 Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
3216                 s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
3217                 , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
3218                  this parameter by RDIMM's extra cycle of latency in terms of DFI clock.
3219                 PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY                                               0x4
3220
3221                 Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
3222                 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
3223                 fer to PHY specification for correct value.
3224                 PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR                                             0x1
3225
3226                 Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
3227                 ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
3228                 , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
3229                  latency through the RDIMM. Unit: Clocks
3230                 PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN                                                0xb
3231
3232                 Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
3233                 .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
3234                 HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
3235                 e.
3236                 PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR                                             0x1
3237
3238                 Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
3239                  dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
3240                 te, max supported value is 8. Unit: Clocks
3241                 PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA                                                0x2
3242
3243                 Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
3244                  parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
3245                  necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
3246                 rough the RDIMM.
3247                 PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT                                                 0xb
3248
3249                 DFI Timing Register 0
3250                 (OFFSET, MASK, VALUE)      (0XFD070190, 0x1FBFBF3FU ,0x048B820BU)
3251                 RegMask = (DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK | DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK | DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK | DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK | DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK | DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK |  0 );
3252
3253                 RegVal = ((0x00000004U << DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT
3254                         | 0x00000001U << DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT
3255                         | 0x0000000BU << DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT
3256                         | 0x00000001U << DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT
3257                         | 0x00000002U << DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT
3258                         | 0x0000000BU << DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT
3259                         |  0 ) & RegMask); */
3260                 PSU_Mask_Write (DDRC_DFITMG0_OFFSET ,0x1FBFBF3FU ,0x048B820BU);
3261         /*############################################################################################################################ */
3262
3263                 /*Register : DFITMG1 @ 0XFD070194</p>
3264
3265                 Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven.
3266                 his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If
3267                 the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
3268                 PSU_DDRC_DFITMG1_DFI_T_CMD_LAT                                                  0x0
3269
3270                 Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa
3271                  is driven.
3272                 PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT                                                0x0
3273
3274                 Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr
3275                 nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo
3276                  correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to
3277                 phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ
3278                 RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni
3279                 : Clocks
3280                 PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY                                             0x3
3281
3282                 Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to
3283                 he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase
3284                 ligned, this timing parameter should be rounded up to the next integer value.
3285                 PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE                                         0x3
3286
3287                 Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first
3288                 alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are
3289                 not phase aligned, this timing parameter should be rounded up to the next integer value.
3290                 PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE                                          0x4
3291
3292                 DFI Timing Register 1
3293                 (OFFSET, MASK, VALUE)      (0XFD070194, 0xF31F0F0FU ,0x00030304U)
3294                 RegMask = (DDRC_DFITMG1_DFI_T_CMD_LAT_MASK | DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK | DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK | DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK | DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK |  0 );
3295
3296                 RegVal = ((0x00000000U << DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT
3297                         | 0x00000000U << DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT
3298                         | 0x00000003U << DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT
3299                         | 0x00000003U << DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT
3300                         | 0x00000004U << DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT
3301                         |  0 ) & RegMask); */
3302                 PSU_Mask_Write (DDRC_DFITMG1_OFFSET ,0xF31F0F0FU ,0x00030304U);
3303         /*############################################################################################################################ */
3304
3305                 /*Register : DFILPCFG0 @ 0XFD070198</p>
3306
3307                 Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi
3308                 g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always.
3309                 PSU_DDRC_DFILPCFG0_DFI_TLP_RESP                                                 0x7
3310
3311                 Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16
3312                 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7
3313                 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD -
3314                 31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device
3315                 .
3316                 PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD                                            0x0
3317
3318                 Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres
3319                 nt for designs supporting mDDR or LPDDR2/LPDDR3 devices.
3320                 PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD                                                0x0
3321
3322                 Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy
3323                 les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 -
3324                 048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131
3325                 72 cycles - 0xE - 262144 cycles - 0xF - Unlimited
3326                 PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR                                             0x0
3327
3328                 Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled
3329                 PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR                                                 0x1
3330
3331                 Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl
3332                 s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20
3333                 8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107
3334                  cycles - 0xE - 262144 cycles - 0xF - Unlimited
3335                 PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD                                             0x0
3336
3337                 Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled
3338                 PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD                                                 0x1
3339
3340                 DFI Low Power Configuration Register 0
3341                 (OFFSET, MASK, VALUE)      (0XFD070198, 0x0FF1F1F1U ,0x07000101U)
3342                 RegMask = (DDRC_DFILPCFG0_DFI_TLP_RESP_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK | DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK |  0 );
3343
3344                 RegVal = ((0x00000007U << DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT
3345                         | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT
3346                         | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT
3347                         | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT
3348                         | 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT
3349                         | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT
3350                         | 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT
3351                         |  0 ) & RegMask); */
3352                 PSU_Mask_Write (DDRC_DFILPCFG0_OFFSET ,0x0FF1F1F1U ,0x07000101U);
3353         /*############################################################################################################################ */
3354
3355                 /*Register : DFILPCFG1 @ 0XFD07019C</p>
3356
3357                 Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0
3358                 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles
3359                  0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0
3360                 D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices.
3361                 PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM                                           0x2
3362
3363                 Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is
3364                 only present for designs supporting DDR4 devices.
3365                 PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM                                               0x1
3366
3367                 DFI Low Power Configuration Register 1
3368                 (OFFSET, MASK, VALUE)      (0XFD07019C, 0x000000F1U ,0x00000021U)
3369                 RegMask = (DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK | DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK |  0 );
3370
3371                 RegVal = ((0x00000002U << DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT
3372                         | 0x00000001U << DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT
3373                         |  0 ) & RegMask); */
3374                 PSU_Mask_Write (DDRC_DFILPCFG1_OFFSET ,0x000000F1U ,0x00000021U);
3375         /*############################################################################################################################ */
3376
3377                 /*Register : DFIUPD1 @ 0XFD0701A4</p>
3378
3379                 This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl
3380                 ). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir
3381                 t read request when the uMCTL2 is idle. Unit: 1024 clocks
3382                 PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024                               0x41
3383
3384                 This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request;
3385                 hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this
3386                 idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca
3387                 e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance.
3388                 Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x
3389                 024. Unit: 1024 clocks
3390                 PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024                               0xe2
3391
3392                 DFI Update Register 1
3393                 (OFFSET, MASK, VALUE)      (0XFD0701A4, 0x00FF00FFU ,0x004100E2U)
3394                 RegMask = (DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK | DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK |  0 );
3395
3396                 RegVal = ((0x00000041U << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT
3397                         | 0x000000E2U << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT
3398                         |  0 ) & RegMask); */
3399                 PSU_Mask_Write (DDRC_DFIUPD1_OFFSET ,0x00FF00FFU ,0x004100E2U);
3400         /*############################################################################################################################ */
3401
3402                 /*Register : DFIMISC @ 0XFD0701B0</p>
3403
3404                 Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high
3405                 PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY                                           0x0
3406
3407                 DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only
3408                 in designs configured to support DDR4 and LPDDR4.
3409                 PSU_DDRC_DFIMISC_PHY_DBI_MODE                                                   0x0
3410
3411                 PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa
3412                 ion
3413                 PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN                                           0x0
3414
3415                 DFI Miscellaneous Control Register
3416                 (OFFSET, MASK, VALUE)      (0XFD0701B0, 0x00000007U ,0x00000000U)
3417                 RegMask = (DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK | DDRC_DFIMISC_PHY_DBI_MODE_MASK | DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK |  0 );
3418
3419                 RegVal = ((0x00000000U << DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT
3420                         | 0x00000000U << DDRC_DFIMISC_PHY_DBI_MODE_SHIFT
3421                         | 0x00000000U << DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT
3422                         |  0 ) & RegMask); */
3423                 PSU_Mask_Write (DDRC_DFIMISC_OFFSET ,0x00000007U ,0x00000000U);
3424         /*############################################################################################################################ */
3425
3426                 /*Register : DFITMG2 @ 0XFD0701B4</p>
3427
3428                 >Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign
3429                 l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.
3430                 PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT                                               0x9
3431
3432                 Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign
3433                 l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.
3434                 PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT                                               0x6
3435
3436                 DFI Timing Register 2
3437                 (OFFSET, MASK, VALUE)      (0XFD0701B4, 0x00003F3FU ,0x00000906U)
3438                 RegMask = (DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK | DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK |  0 );
3439
3440                 RegVal = ((0x00000009U << DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT
3441                         | 0x00000006U << DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT
3442                         |  0 ) & RegMask); */
3443                 PSU_Mask_Write (DDRC_DFITMG2_OFFSET ,0x00003F3FU ,0x00000906U);
3444         /*############################################################################################################################ */
3445
3446                 /*Register : DBICTL @ 0XFD0701C0</p>
3447
3448                 Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value
3449                 as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]
3450                 PSU_DDRC_DBICTL_RD_DBI_EN                                                       0x0
3451
3452                 Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va
3453                 ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]
3454                 PSU_DDRC_DBICTL_WR_DBI_EN                                                       0x0
3455
3456                 DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's
3457                 mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR
3458                 : Set this to inverted value of MR13[5] which is opposite polarity from this signal
3459                 PSU_DDRC_DBICTL_DM_EN                                                           0x1
3460
3461                 DM/DBI Control Register
3462                 (OFFSET, MASK, VALUE)      (0XFD0701C0, 0x00000007U ,0x00000001U)
3463                 RegMask = (DDRC_DBICTL_RD_DBI_EN_MASK | DDRC_DBICTL_WR_DBI_EN_MASK | DDRC_DBICTL_DM_EN_MASK |  0 );
3464
3465                 RegVal = ((0x00000000U << DDRC_DBICTL_RD_DBI_EN_SHIFT
3466                         | 0x00000000U << DDRC_DBICTL_WR_DBI_EN_SHIFT
3467                         | 0x00000001U << DDRC_DBICTL_DM_EN_SHIFT
3468                         |  0 ) & RegMask); */
3469                 PSU_Mask_Write (DDRC_DBICTL_OFFSET ,0x00000007U ,0x00000001U);
3470         /*############################################################################################################################ */
3471
3472                 /*Register : ADDRMAP0 @ 0XFD070200</p>
3473
3474                 Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres
3475                  bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0.
3476                 PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0                                               0x1f
3477
3478                 Address Map Register 0
3479                 (OFFSET, MASK, VALUE)      (0XFD070200, 0x0000001FU ,0x0000001FU)
3480                 RegMask = (DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK |  0 );
3481
3482                 RegVal = ((0x0000001FU << DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT
3483                         |  0 ) & RegMask); */
3484                 PSU_Mask_Write (DDRC_ADDRMAP0_OFFSET ,0x0000001FU ,0x0000001FU);
3485         /*############################################################################################################################ */
3486
3487                 /*Register : ADDRMAP1 @ 0XFD070204</p>
3488
3489                 Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address
3490                 bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0.
3491                 PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2                                               0x1f
3492
3493                 Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f
3494                 r each of the bank address bits is determined by adding the internal base to the value of this field.
3495                 PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1                                               0xa
3496
3497                 Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f
3498                 r each of the bank address bits is determined by adding the internal base to the value of this field.
3499                 PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0                                               0xa
3500
3501                 Address Map Register 1
3502                 (OFFSET, MASK, VALUE)      (0XFD070204, 0x001F1F1FU ,0x001F0A0AU)
3503                 RegMask = (DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK | DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK | DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK |  0 );
3504
3505                 RegVal = ((0x0000001FU << DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT
3506                         | 0x0000000AU << DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT
3507                         | 0x0000000AU << DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT
3508                         |  0 ) & RegMask); */
3509                 PSU_Mask_Write (DDRC_ADDRMAP1_OFFSET ,0x001F1F1FU ,0x001F0A0AU);
3510         /*############################################################################################################################ */
3511
3512                 /*Register : ADDRMAP2 @ 0XFD070208</p>
3513
3514                 - Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre
3515                 s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali
3516                  Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o
3517                  this field. If set to 15, this column address bit is set to 0.
3518                 PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5                                                0x0
3519
3520                 - Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre
3521                 s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid
3522                 Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of
3523                 this field. If set to 15, this column address bit is set to 0.
3524                 PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4                                                0x0
3525
3526                 - Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre
3527                 s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid
3528                 Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi
3529                 ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i
3530                  this case.
3531                 PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3                                                0x0
3532
3533                 - Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre
3534                 s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid
3535                 Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi
3536                 ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0.
3537                 PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2                                                0x0
3538
3539                 Address Map Register 2
3540                 (OFFSET, MASK, VALUE)      (0XFD070208, 0x0F0F0F0FU ,0x00000000U)
3541                 RegMask = (DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK |  0 );
3542
3543                 RegVal = ((0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT
3544                         | 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT
3545                         | 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT
3546                         | 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT
3547                         |  0 ) & RegMask); */
3548                 PSU_Mask_Write (DDRC_ADDRMAP2_OFFSET ,0x0F0F0F0FU ,0x00000000U);
3549         /*############################################################################################################################ */
3550
3551                 /*Register : ADDRMAP3 @ 0XFD07020C</p>
3552
3553                 - Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre
3554                 s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as
3555                 column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i
3556                  determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note:
3557                 er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr
3558                 ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an
3559                  hence column bit 10 is used.
3560                 PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9                                                0x0
3561
3562                 - Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre
3563                 s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i
3564                  LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i
3565                 ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif
3566                 cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col
3567                 mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use
3568                 .
3569                 PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8                                                0x0
3570
3571                 - Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre
3572                 s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid
3573                 Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of
3574                 this field. If set to 15, this column address bit is set to 0.
3575                 PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7                                                0x0
3576
3577                 - Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre
3578                 s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid
3579                 Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of
3580                 this field. If set to 15, this column address bit is set to 0.
3581                 PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6                                                0x0
3582
3583                 Address Map Register 3
3584                 (OFFSET, MASK, VALUE)      (0XFD07020C, 0x0F0F0F0FU ,0x00000000U)
3585                 RegMask = (DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK |  0 );
3586
3587                 RegVal = ((0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT
3588                         | 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT
3589                         | 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT
3590                         | 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT
3591                         |  0 ) & RegMask); */
3592                 PSU_Mask_Write (DDRC_ADDRMAP3_OFFSET ,0x0F0F0F0FU ,0x00000000U);
3593         /*############################################################################################################################ */
3594
3595                 /*Register : ADDRMAP4 @ 0XFD070210</p>
3596
3597                 - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width
3598                 mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must
3599                 e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern
3600                 l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati
3601                 n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a
3602                 dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.
3603                 PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11                                               0xf
3604
3605                 - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width
3606                 mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED.
3607                 To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d
3608                 termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per
3609                 JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address
3610                 bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h
3611                 nce column bit 10 is used.
3612                 PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10                                               0xf
3613
3614                 Address Map Register 4
3615                 (OFFSET, MASK, VALUE)      (0XFD070210, 0x00000F0FU ,0x00000F0FU)
3616                 RegMask = (DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK | DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK |  0 );
3617
3618                 RegVal = ((0x0000000FU << DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT
3619                         | 0x0000000FU << DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT
3620                         |  0 ) & RegMask); */
3621                 PSU_Mask_Write (DDRC_ADDRMAP4_OFFSET ,0x00000F0FU ,0x00000F0FU);
3622         /*############################################################################################################################ */
3623
3624                 /*Register : ADDRMAP5 @ 0XFD070214</p>
3625
3626                 Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre
3627                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0.
3628                 PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11                                               0x8
3629
3630                 Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address
3631                 bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF
3632                 ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value
3633                 5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.
3634                 PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10                                             0xf
3635
3636                 Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo
3637                  each of the row address bits is determined by adding the internal base to the value of this field.
3638                 PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1                                                0x8
3639
3640                 Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo
3641                  each of the row address bits is determined by adding the internal base to the value of this field.
3642                 PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0                                                0x8
3643
3644                 Address Map Register 5
3645                 (OFFSET, MASK, VALUE)      (0XFD070214, 0x0F0F0F0FU ,0x080F0808U)
3646                 RegMask = (DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK |  0 );
3647
3648                 RegVal = ((0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT
3649                         | 0x0000000FU << DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT
3650                         | 0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT
3651                         | 0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT
3652                         |  0 ) & RegMask); */
3653                 PSU_Mask_Write (DDRC_ADDRMAP5_OFFSET ,0x0F0F0F0FU ,0x080F0808U);
3654         /*############################################################################################################################ */
3655
3656                 /*Register : ADDRMAP6 @ 0XFD070218</p>
3657
3658                 Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address
3659                 having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on
3660                 y in designs configured to support LPDDR3.
3661                 PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB                                               0x0
3662
3663                 Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre
3664                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0.
3665                 PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15                                               0xf
3666
3667                 Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre
3668                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0.
3669                 PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14                                               0x8
3670
3671                 Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre
3672                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0.
3673                 PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13                                               0x8
3674
3675                 Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre
3676                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0.
3677                 PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12                                               0x8
3678
3679                 Address Map Register 6
3680                 (OFFSET, MASK, VALUE)      (0XFD070218, 0x8F0F0F0FU ,0x0F080808U)
3681                 RegMask = (DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK |  0 );
3682
3683                 RegVal = ((0x00000000U << DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT
3684                         | 0x0000000FU << DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT
3685                         | 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT
3686                         | 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT
3687                         | 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT
3688                         |  0 ) & RegMask); */
3689                 PSU_Mask_Write (DDRC_ADDRMAP6_OFFSET ,0x8F0F0F0FU ,0x0F080808U);
3690         /*############################################################################################################################ */
3691
3692                 /*Register : ADDRMAP7 @ 0XFD07021C</p>
3693
3694                 Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre
3695                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0.
3696                 PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17                                               0xf
3697
3698                 Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre
3699                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0.
3700                 PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16                                               0xf
3701
3702                 Address Map Register 7
3703                 (OFFSET, MASK, VALUE)      (0XFD07021C, 0x00000F0FU ,0x00000F0FU)
3704                 RegMask = (DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK | DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK |  0 );
3705
3706                 RegVal = ((0x0000000FU << DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT
3707                         | 0x0000000FU << DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT
3708                         |  0 ) & RegMask); */
3709                 PSU_Mask_Write (DDRC_ADDRMAP7_OFFSET ,0x00000F0FU ,0x00000F0FU);
3710         /*############################################################################################################################ */
3711
3712                 /*Register : ADDRMAP8 @ 0XFD070220</p>
3713
3714                 Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF
3715                 address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If
3716                 et to 31, bank group address bit 1 is set to 0.
3717                 PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1                                                 0x8
3718
3719                 Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address
3720                 bit for each of the bank group address bits is determined by adding the internal base to the value of this field.
3721                 PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0                                                 0x8
3722
3723                 Address Map Register 8
3724                 (OFFSET, MASK, VALUE)      (0XFD070220, 0x00001F1FU ,0x00000808U)
3725                 RegMask = (DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK | DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK |  0 );
3726
3727                 RegVal = ((0x00000008U << DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT
3728                         | 0x00000008U << DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT
3729                         |  0 ) & RegMask); */
3730                 PSU_Mask_Write (DDRC_ADDRMAP8_OFFSET ,0x00001F1FU ,0x00000808U);
3731         /*############################################################################################################################ */
3732
3733                 /*Register : ADDRMAP9 @ 0XFD070224</p>
3734
3735                 Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f
3736                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
3737                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
3738                 PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5                                                0x8
3739
3740                 Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f
3741                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
3742                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
3743                 PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4                                                0x8
3744
3745                 Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo
3746                  each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
3747                 d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
3748                 PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3                                                0x8
3749
3750                 Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo
3751                  each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
3752                 d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
3753                 PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2                                                0x8
3754
3755                 Address Map Register 9
3756                 (OFFSET, MASK, VALUE)      (0XFD070224, 0x0F0F0F0FU ,0x08080808U)
3757                 RegMask = (DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK |  0 );
3758
3759                 RegVal = ((0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT
3760                         | 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT
3761                         | 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT
3762                         | 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT
3763                         |  0 ) & RegMask); */
3764                 PSU_Mask_Write (DDRC_ADDRMAP9_OFFSET ,0x0F0F0F0FU ,0x08080808U);
3765         /*############################################################################################################################ */
3766
3767                 /*Register : ADDRMAP10 @ 0XFD070228</p>
3768
3769                 Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f
3770                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
3771                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
3772                 PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9                                               0x8
3773
3774                 Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f
3775                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
3776                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
3777                 PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8                                               0x8
3778
3779                 Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f
3780                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
3781                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
3782                 PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7                                               0x8
3783
3784                 Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f
3785                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
3786                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
3787                 PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6                                               0x8
3788
3789                 Address Map Register 10
3790                 (OFFSET, MASK, VALUE)      (0XFD070228, 0x0F0F0F0FU ,0x08080808U)
3791                 RegMask = (DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK |  0 );
3792
3793                 RegVal = ((0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT
3794                         | 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT
3795                         | 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT
3796                         | 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT
3797                         |  0 ) & RegMask); */
3798                 PSU_Mask_Write (DDRC_ADDRMAP10_OFFSET ,0x0F0F0F0FU ,0x08080808U);
3799         /*############################################################################################################################ */
3800
3801                 /*Register : ADDRMAP11 @ 0XFD07022C</p>
3802
3803                 Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit
3804                 or each of the row address bits is determined by adding the internal base to the value of this field. This register field is
3805                 sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
3806                 PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10                                              0x8
3807
3808                 Address Map Register 11
3809                 (OFFSET, MASK, VALUE)      (0XFD07022C, 0x0000000FU ,0x00000008U)
3810                 RegMask = (DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK |  0 );
3811
3812                 RegVal = ((0x00000008U << DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT
3813                         |  0 ) & RegMask); */
3814                 PSU_Mask_Write (DDRC_ADDRMAP11_OFFSET ,0x0000000FU ,0x00000008U);
3815         /*############################################################################################################################ */
3816
3817                 /*Register : ODTCFG @ 0XFD070240</p>
3818
3819                 Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/
3820                 67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: -
3821                 L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1
3822                 CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
3823                 PSU_DDRC_ODTCFG_WR_ODT_HOLD                                                     0x6
3824
3825                 The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must
3826                 remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/
3827                 67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation
3828                  DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))
3829                 PSU_DDRC_ODTCFG_WR_ODT_DELAY                                                    0x0
3830
3831                 Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066)
3832                  0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (
3833                 tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC
3834                 )
3835                 PSU_DDRC_ODTCFG_RD_ODT_HOLD                                                     0x6
3836
3837                 The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must
3838                 emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066),
3839                 CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C
3840                 L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK
3841                 write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0,
3842                 uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)
3843                 PSU_DDRC_ODTCFG_RD_ODT_DELAY                                                    0x0
3844
3845                 ODT Configuration Register
3846                 (OFFSET, MASK, VALUE)      (0XFD070240, 0x0F1F0F7CU ,0x06000600U)
3847                 RegMask = (DDRC_ODTCFG_WR_ODT_HOLD_MASK | DDRC_ODTCFG_WR_ODT_DELAY_MASK | DDRC_ODTCFG_RD_ODT_HOLD_MASK | DDRC_ODTCFG_RD_ODT_DELAY_MASK |  0 );
3848
3849                 RegVal = ((0x00000006U << DDRC_ODTCFG_WR_ODT_HOLD_SHIFT
3850                         | 0x00000000U << DDRC_ODTCFG_WR_ODT_DELAY_SHIFT
3851                         | 0x00000006U << DDRC_ODTCFG_RD_ODT_HOLD_SHIFT
3852                         | 0x00000000U << DDRC_ODTCFG_RD_ODT_DELAY_SHIFT
3853                         |  0 ) & RegMask); */
3854                 PSU_Mask_Write (DDRC_ODTCFG_OFFSET ,0x0F1F0F7CU ,0x06000600U);
3855         /*############################################################################################################################ */
3856
3857                 /*Register : ODTMAP @ 0XFD070244</p>
3858
3859                 Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can
3860                 e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
3861                  etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks
3862                 PSU_DDRC_ODTMAP_RANK1_RD_ODT                                                    0x0
3863
3864                 Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b
3865                  turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
3866                 etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks
3867                 PSU_DDRC_ODTMAP_RANK1_WR_ODT                                                    0x0
3868
3869                 Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can
3870                 e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
3871                  etc. For each rank, set its bit to 1 to enable its ODT.
3872                 PSU_DDRC_ODTMAP_RANK0_RD_ODT                                                    0x0
3873
3874                 Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b
3875                  turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
3876                 etc. For each rank, set its bit to 1 to enable its ODT.
3877                 PSU_DDRC_ODTMAP_RANK0_WR_ODT                                                    0x1
3878
3879                 ODT/Rank Map Register
3880                 (OFFSET, MASK, VALUE)      (0XFD070244, 0x00003333U ,0x00000001U)
3881                 RegMask = (DDRC_ODTMAP_RANK1_RD_ODT_MASK | DDRC_ODTMAP_RANK1_WR_ODT_MASK | DDRC_ODTMAP_RANK0_RD_ODT_MASK | DDRC_ODTMAP_RANK0_WR_ODT_MASK |  0 );
3882
3883                 RegVal = ((0x00000000U << DDRC_ODTMAP_RANK1_RD_ODT_SHIFT
3884                         | 0x00000000U << DDRC_ODTMAP_RANK1_WR_ODT_SHIFT
3885                         | 0x00000000U << DDRC_ODTMAP_RANK0_RD_ODT_SHIFT
3886                         | 0x00000001U << DDRC_ODTMAP_RANK0_WR_ODT_SHIFT
3887                         |  0 ) & RegMask); */
3888                 PSU_Mask_Write (DDRC_ODTMAP_OFFSET ,0x00003333U ,0x00000001U);
3889         /*############################################################################################################################ */
3890
3891                 /*Register : SCHED @ 0XFD070250</p>
3892
3893                 When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is
3894                 non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t
3895                 ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this
3896                 egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true.
3897                 OR PERFORMANCE ONLY
3898                 PSU_DDRC_SCHED_RDWR_IDLE_GAP                                                    0x1
3899
3900                 UNUSED
3901                 PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS                                           0x0
3902
3903                 Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i
3904                  the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries
3905                 to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high
3906                 priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les
3907                  than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar
3908                 sing out of single bit error correction RMW operation.
3909                 PSU_DDRC_SCHED_LPR_NUM_ENTRIES                                                  0x20
3910
3911                 If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri
3912                 e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this
3913                 egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca
3914                 es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed
3915                 s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n
3916                 ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open
3917                 age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea
3918                 ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY.
3919                 PSU_DDRC_SCHED_PAGECLOSE                                                        0x0
3920
3921                 If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.
3922                 PSU_DDRC_SCHED_PREFER_WRITE                                                     0x0
3923
3924                 Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio
3925                 ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si
3926                 e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t
3927                 ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY.
3928                 PSU_DDRC_SCHED_FORCE_LOW_PRI_N                                                  0x1
3929
3930                 Scheduler Control Register
3931                 (OFFSET, MASK, VALUE)      (0XFD070250, 0x7FFF3F07U ,0x01002001U)
3932                 RegMask = (DDRC_SCHED_RDWR_IDLE_GAP_MASK | DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK | DDRC_SCHED_LPR_NUM_ENTRIES_MASK | DDRC_SCHED_PAGECLOSE_MASK | DDRC_SCHED_PREFER_WRITE_MASK | DDRC_SCHED_FORCE_LOW_PRI_N_MASK |  0 );
3933
3934                 RegVal = ((0x00000001U << DDRC_SCHED_RDWR_IDLE_GAP_SHIFT
3935                         | 0x00000000U << DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT
3936                         | 0x00000020U << DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT
3937                         | 0x00000000U << DDRC_SCHED_PAGECLOSE_SHIFT
3938                         | 0x00000000U << DDRC_SCHED_PREFER_WRITE_SHIFT
3939                         | 0x00000001U << DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT
3940                         |  0 ) & RegMask); */
3941                 PSU_Mask_Write (DDRC_SCHED_OFFSET ,0x7FFF3F07U ,0x01002001U);
3942         /*############################################################################################################################ */
3943
3944                 /*Register : PERFLPR1 @ 0XFD070264</p>
3945
3946                 Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o
3947                  transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.
3948                 PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH                                           0x8
3949
3950                 Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis
3951                 er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not
3952                 be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
3953                 PSU_DDRC_PERFLPR1_LPR_MAX_STARVE                                                0x40
3954
3955                 Low Priority Read CAM Register 1
3956                 (OFFSET, MASK, VALUE)      (0XFD070264, 0xFF00FFFFU ,0x08000040U)
3957                 RegMask = (DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK | DDRC_PERFLPR1_LPR_MAX_STARVE_MASK |  0 );
3958
3959                 RegVal = ((0x00000008U << DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT
3960                         | 0x00000040U << DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT
3961                         |  0 ) & RegMask); */
3962                 PSU_Mask_Write (DDRC_PERFLPR1_OFFSET ,0xFF00FFFFU ,0x08000040U);
3963         /*############################################################################################################################ */
3964
3965                 /*Register : PERFWR1 @ 0XFD07026C</p>
3966
3967                 Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of
3968                 transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.
3969                 PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH                                              0x8
3970
3971                 Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist
3972                 r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not
3973                 e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
3974                 PSU_DDRC_PERFWR1_W_MAX_STARVE                                                   0x40
3975
3976                 Write CAM Register 1
3977                 (OFFSET, MASK, VALUE)      (0XFD07026C, 0xFF00FFFFU ,0x08000040U)
3978                 RegMask = (DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK | DDRC_PERFWR1_W_MAX_STARVE_MASK |  0 );
3979
3980                 RegVal = ((0x00000008U << DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT
3981                         | 0x00000040U << DDRC_PERFWR1_W_MAX_STARVE_SHIFT
3982                         |  0 ) & RegMask); */
3983                 PSU_Mask_Write (DDRC_PERFWR1_OFFSET ,0xFF00FFFFU ,0x08000040U);
3984         /*############################################################################################################################ */
3985
3986                 /*Register : DQMAP5 @ 0XFD070294</p>
3987
3988                 All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for
3989                 all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and
3990                 wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su
3991                 port DDR4.
3992                 PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP                                                0x1
3993
3994                 DQ Map Register 5
3995                 (OFFSET, MASK, VALUE)      (0XFD070294, 0x00000001U ,0x00000001U)
3996                 RegMask = (DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK |  0 );
3997
3998                 RegVal = ((0x00000001U << DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT
3999                         |  0 ) & RegMask); */
4000                 PSU_Mask_Write (DDRC_DQMAP5_OFFSET ,0x00000001U ,0x00000001U);
4001         /*############################################################################################################################ */
4002
4003                 /*Register : DBG0 @ 0XFD070300</p>
4004
4005                 When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo
4006                 lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d
4007                 s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY.
4008                 PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT                                            0x0
4009
4010                 When 1, disable write combine. FOR DEBUG ONLY
4011                 PSU_DDRC_DBG0_DIS_WC                                                            0x0
4012
4013                 Debug Register 0
4014                 (OFFSET, MASK, VALUE)      (0XFD070300, 0x00000011U ,0x00000000U)
4015                 RegMask = (DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK | DDRC_DBG0_DIS_WC_MASK |  0 );
4016
4017                 RegVal = ((0x00000000U << DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT
4018                         | 0x00000000U << DDRC_DBG0_DIS_WC_SHIFT
4019                         |  0 ) & RegMask); */
4020                 PSU_Mask_Write (DDRC_DBG0_OFFSET ,0x00000011U ,0x00000000U);
4021         /*############################################################################################################################ */
4022
4023                 /*Register : DBGCMD @ 0XFD07030C</p>
4024
4025                 Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1,
4026                 the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this
4027                 register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank
4028                 _refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static
4029                  and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0).
4030                 PSU_DDRC_DBGCMD_HW_REF_ZQ_EN                                                    0x0
4031
4032                 Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in
4033                 he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.
4034                 PSU_DDRC_DBGCMD_CTRLUPD                                                         0x0
4035
4036                 Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to
4037                 he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w
4038                 en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor
4039                 d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M
4040                 de.
4041                 PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT                                                  0x0
4042
4043                 Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1
4044                 refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
4045                 be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
4046                 wn operating modes or Maximum Power Saving Mode.
4047                 PSU_DDRC_DBGCMD_RANK1_REFRESH                                                   0x0
4048
4049                 Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0
4050                 refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
4051                 be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
4052                 wn operating modes or Maximum Power Saving Mode.
4053                 PSU_DDRC_DBGCMD_RANK0_REFRESH                                                   0x0
4054
4055                 Command Debug Register
4056                 (OFFSET, MASK, VALUE)      (0XFD07030C, 0x80000033U ,0x00000000U)
4057                 RegMask = (DDRC_DBGCMD_HW_REF_ZQ_EN_MASK | DDRC_DBGCMD_CTRLUPD_MASK | DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK | DDRC_DBGCMD_RANK1_REFRESH_MASK | DDRC_DBGCMD_RANK0_REFRESH_MASK |  0 );
4058
4059                 RegVal = ((0x00000000U << DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT
4060                         | 0x00000000U << DDRC_DBGCMD_CTRLUPD_SHIFT
4061                         | 0x00000000U << DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT
4062                         | 0x00000000U << DDRC_DBGCMD_RANK1_REFRESH_SHIFT
4063                         | 0x00000000U << DDRC_DBGCMD_RANK0_REFRESH_SHIFT
4064                         |  0 ) & RegMask); */
4065                 PSU_Mask_Write (DDRC_DBGCMD_OFFSET ,0x80000033U ,0x00000000U);
4066         /*############################################################################################################################ */
4067
4068                 /*Register : SWCTL @ 0XFD070320</p>
4069
4070                 Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back
4071                 egister to 1 once programming is done.
4072                 PSU_DDRC_SWCTL_SW_DONE                                                          0x0
4073
4074                 Software register programming control enable
4075                 (OFFSET, MASK, VALUE)      (0XFD070320, 0x00000001U ,0x00000000U)
4076                 RegMask = (DDRC_SWCTL_SW_DONE_MASK |  0 );
4077
4078                 RegVal = ((0x00000000U << DDRC_SWCTL_SW_DONE_SHIFT
4079                         |  0 ) & RegMask); */
4080                 PSU_Mask_Write (DDRC_SWCTL_OFFSET ,0x00000001U ,0x00000000U);
4081         /*############################################################################################################################ */
4082
4083                 /*Register : PCCFG @ 0XFD070400</p>
4084
4085                 Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t
4086                 e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo
4087                 h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par
4088                 ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc
4089                 _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_
4090                 ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP
4091                 DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4
4092                 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share
4093                 -AC is enabled
4094                 PSU_DDRC_PCCFG_BL_EXP_MODE                                                      0x0
4095
4096                 Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P
4097                 rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p
4098                 ge DDRC transactions.
4099                 PSU_DDRC_PCCFG_PAGEMATCH_LIMIT                                                  0x0
4100
4101                 If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based
4102                 n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica
4103                 _lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.
4104                 PSU_DDRC_PCCFG_GO2CRITICAL_EN                                                   0x1
4105
4106                 Port Common Configuration Register
4107                 (OFFSET, MASK, VALUE)      (0XFD070400, 0x00000111U ,0x00000001U)
4108                 RegMask = (DDRC_PCCFG_BL_EXP_MODE_MASK | DDRC_PCCFG_PAGEMATCH_LIMIT_MASK | DDRC_PCCFG_GO2CRITICAL_EN_MASK |  0 );
4109
4110                 RegVal = ((0x00000000U << DDRC_PCCFG_BL_EXP_MODE_SHIFT
4111                         | 0x00000000U << DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT
4112                         | 0x00000001U << DDRC_PCCFG_GO2CRITICAL_EN_SHIFT
4113                         |  0 ) & RegMask); */
4114                 PSU_Mask_Write (DDRC_PCCFG_OFFSET ,0x00000111U ,0x00000001U);
4115         /*############################################################################################################################ */
4116
4117                 /*Register : PCFGR_0 @ 0XFD070404</p>
4118
4119                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4120                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4121                 imit register.
4122                 PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN                                           0x0
4123
4124                 If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
4125                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
4126                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
4127                 ess handshaking (it is not associated with any particular command).
4128                 PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN                                              0x1
4129
4130                 If set to 1, enables aging function for the read channel of the port.
4131                 PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN                                               0x0
4132
4133                 Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
4134                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4135                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
4136                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
4137                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
4138                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
4139                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
4140                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
4141                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
4142                 he two LSBs of this register field are tied internally to 2'b00.
4143                 PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY                                               0xf
4144
4145                 Port n Configuration Read Register
4146                 (OFFSET, MASK, VALUE)      (0XFD070404, 0x000073FFU ,0x0000200FU)
4147                 RegMask = (DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK |  0 );
4148
4149                 RegVal = ((0x00000000U << DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT
4150                         | 0x00000001U << DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT
4151                         | 0x00000000U << DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT
4152                         | 0x0000000FU << DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT
4153                         |  0 ) & RegMask); */
4154                 PSU_Mask_Write (DDRC_PCFGR_0_OFFSET ,0x000073FFU ,0x0000200FU);
4155         /*############################################################################################################################ */
4156
4157                 /*Register : PCFGW_0 @ 0XFD070408</p>
4158
4159                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4160                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4161                 imit register.
4162                 PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN                                           0x1
4163
4164                 If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
4165                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
4166                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
4167                 not associated with any particular command).
4168                 PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN                                              0x1
4169
4170                 If set to 1, enables aging function for the write channel of the port.
4171                 PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN                                               0x0
4172
4173                 Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
4174                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4175                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
4176                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
4177                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
4178                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
4179                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
4180                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.
4181                 PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY                                               0xf
4182
4183                 Port n Configuration Write Register
4184                 (OFFSET, MASK, VALUE)      (0XFD070408, 0x000073FFU ,0x0000600FU)
4185                 RegMask = (DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK |  0 );
4186
4187                 RegVal = ((0x00000001U << DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT
4188                         | 0x00000001U << DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT
4189                         | 0x00000000U << DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT
4190                         | 0x0000000FU << DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT
4191                         |  0 ) & RegMask); */
4192                 PSU_Mask_Write (DDRC_PCFGW_0_OFFSET ,0x000073FFU ,0x0000600FU);
4193         /*############################################################################################################################ */
4194
4195                 /*Register : PCTRL_0 @ 0XFD070490</p>
4196
4197                 Enables port n.
4198                 PSU_DDRC_PCTRL_0_PORT_EN                                                        0x1
4199
4200                 Port n Control Register
4201                 (OFFSET, MASK, VALUE)      (0XFD070490, 0x00000001U ,0x00000001U)
4202                 RegMask = (DDRC_PCTRL_0_PORT_EN_MASK |  0 );
4203
4204                 RegVal = ((0x00000001U << DDRC_PCTRL_0_PORT_EN_SHIFT
4205                         |  0 ) & RegMask); */
4206                 PSU_Mask_Write (DDRC_PCTRL_0_OFFSET ,0x00000001U ,0x00000001U);
4207         /*############################################################################################################################ */
4208
4209                 /*Register : PCFGQOS0_0 @ 0XFD070494</p>
4210
4211                 This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
4212                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
4213                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4214                 PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1                                            0x2
4215
4216                 This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
4217                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
4218                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4219                 PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0                                            0x0
4220
4221                 Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
4222                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
4223                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
4224                  values.
4225                 PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1                                             0xb
4226
4227                 Port n Read QoS Configuration Register 0
4228                 (OFFSET, MASK, VALUE)      (0XFD070494, 0x0033000FU ,0x0020000BU)
4229                 RegMask = (DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK |  0 );
4230
4231                 RegVal = ((0x00000002U << DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT
4232                         | 0x00000000U << DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT
4233                         | 0x0000000BU << DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT
4234                         |  0 ) & RegMask); */
4235                 PSU_Mask_Write (DDRC_PCFGQOS0_0_OFFSET ,0x0033000FU ,0x0020000BU);
4236         /*############################################################################################################################ */
4237
4238                 /*Register : PCFGQOS1_0 @ 0XFD070498</p>
4239
4240                 Specifies the timeout value for transactions mapped to the red address queue.
4241                 PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR                                           0x0
4242
4243                 Specifies the timeout value for transactions mapped to the blue address queue.
4244                 PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB                                           0x0
4245
4246                 Port n Read QoS Configuration Register 1
4247                 (OFFSET, MASK, VALUE)      (0XFD070498, 0x07FF07FFU ,0x00000000U)
4248                 RegMask = (DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK |  0 );
4249
4250                 RegVal = ((0x00000000U << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT
4251                         | 0x00000000U << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT
4252                         |  0 ) & RegMask); */
4253                 PSU_Mask_Write (DDRC_PCFGQOS1_0_OFFSET ,0x07FF07FFU ,0x00000000U);
4254         /*############################################################################################################################ */
4255
4256                 /*Register : PCFGR_1 @ 0XFD0704B4</p>
4257
4258                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4259                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4260                 imit register.
4261                 PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN                                           0x0
4262
4263                 If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
4264                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
4265                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
4266                 ess handshaking (it is not associated with any particular command).
4267                 PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN                                              0x1
4268
4269                 If set to 1, enables aging function for the read channel of the port.
4270                 PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN                                               0x0
4271
4272                 Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
4273                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4274                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
4275                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
4276                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
4277                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
4278                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
4279                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
4280                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
4281                 he two LSBs of this register field are tied internally to 2'b00.
4282                 PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY                                               0xf
4283
4284                 Port n Configuration Read Register
4285                 (OFFSET, MASK, VALUE)      (0XFD0704B4, 0x000073FFU ,0x0000200FU)
4286                 RegMask = (DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK |  0 );
4287
4288                 RegVal = ((0x00000000U << DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT
4289                         | 0x00000001U << DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT
4290                         | 0x00000000U << DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT
4291                         | 0x0000000FU << DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT
4292                         |  0 ) & RegMask); */
4293                 PSU_Mask_Write (DDRC_PCFGR_1_OFFSET ,0x000073FFU ,0x0000200FU);
4294         /*############################################################################################################################ */
4295
4296                 /*Register : PCFGW_1 @ 0XFD0704B8</p>
4297
4298                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4299                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4300                 imit register.
4301                 PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN                                           0x1
4302
4303                 If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
4304                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
4305                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
4306                 not associated with any particular command).
4307                 PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN                                              0x1
4308
4309                 If set to 1, enables aging function for the write channel of the port.
4310                 PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN                                               0x0
4311
4312                 Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
4313                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4314                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
4315                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
4316                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
4317                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
4318                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
4319                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.
4320                 PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY                                               0xf
4321
4322                 Port n Configuration Write Register
4323                 (OFFSET, MASK, VALUE)      (0XFD0704B8, 0x000073FFU ,0x0000600FU)
4324                 RegMask = (DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK |  0 );
4325
4326                 RegVal = ((0x00000001U << DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT
4327                         | 0x00000001U << DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT
4328                         | 0x00000000U << DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT
4329                         | 0x0000000FU << DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT
4330                         |  0 ) & RegMask); */
4331                 PSU_Mask_Write (DDRC_PCFGW_1_OFFSET ,0x000073FFU ,0x0000600FU);
4332         /*############################################################################################################################ */
4333
4334                 /*Register : PCTRL_1 @ 0XFD070540</p>
4335
4336                 Enables port n.
4337                 PSU_DDRC_PCTRL_1_PORT_EN                                                        0x1
4338
4339                 Port n Control Register
4340                 (OFFSET, MASK, VALUE)      (0XFD070540, 0x00000001U ,0x00000001U)
4341                 RegMask = (DDRC_PCTRL_1_PORT_EN_MASK |  0 );
4342
4343                 RegVal = ((0x00000001U << DDRC_PCTRL_1_PORT_EN_SHIFT
4344                         |  0 ) & RegMask); */
4345                 PSU_Mask_Write (DDRC_PCTRL_1_OFFSET ,0x00000001U ,0x00000001U);
4346         /*############################################################################################################################ */
4347
4348                 /*Register : PCFGQOS0_1 @ 0XFD070544</p>
4349
4350                 This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address
4351                 ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2
4352                 s set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4353                 PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2                                            0x2
4354
4355                 This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
4356                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
4357                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4358                 PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1                                            0x0
4359
4360                 This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
4361                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
4362                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4363                 PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0                                            0x0
4364
4365                 Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
4366                 el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
4367                 directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers
4368                 ust be set to distinct values.
4369                 PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2                                             0xb
4370
4371                 Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
4372                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
4373                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
4374                  values.
4375                 PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1                                             0x3
4376
4377                 Port n Read QoS Configuration Register 0
4378                 (OFFSET, MASK, VALUE)      (0XFD070544, 0x03330F0FU ,0x02000B03U)
4379                 RegMask = (DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK |  0 );
4380
4381                 RegVal = ((0x00000002U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT
4382                         | 0x00000000U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT
4383                         | 0x00000000U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT
4384                         | 0x0000000BU << DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT
4385                         | 0x00000003U << DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT
4386                         |  0 ) & RegMask); */
4387                 PSU_Mask_Write (DDRC_PCFGQOS0_1_OFFSET ,0x03330F0FU ,0x02000B03U);
4388         /*############################################################################################################################ */
4389
4390                 /*Register : PCFGQOS1_1 @ 0XFD070548</p>
4391
4392                 Specifies the timeout value for transactions mapped to the red address queue.
4393                 PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR                                           0x0
4394
4395                 Specifies the timeout value for transactions mapped to the blue address queue.
4396                 PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB                                           0x0
4397
4398                 Port n Read QoS Configuration Register 1
4399                 (OFFSET, MASK, VALUE)      (0XFD070548, 0x07FF07FFU ,0x00000000U)
4400                 RegMask = (DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK |  0 );
4401
4402                 RegVal = ((0x00000000U << DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT
4403                         | 0x00000000U << DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT
4404                         |  0 ) & RegMask); */
4405                 PSU_Mask_Write (DDRC_PCFGQOS1_1_OFFSET ,0x07FF07FFU ,0x00000000U);
4406         /*############################################################################################################################ */
4407
4408                 /*Register : PCFGR_2 @ 0XFD070564</p>
4409
4410                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4411                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4412                 imit register.
4413                 PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN                                           0x0
4414
4415                 If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
4416                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
4417                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
4418                 ess handshaking (it is not associated with any particular command).
4419                 PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN                                              0x1
4420
4421                 If set to 1, enables aging function for the read channel of the port.
4422                 PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN                                               0x0
4423
4424                 Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
4425                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4426                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
4427                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
4428                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
4429                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
4430                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
4431                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
4432                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
4433                 he two LSBs of this register field are tied internally to 2'b00.
4434                 PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY                                               0xf
4435
4436                 Port n Configuration Read Register
4437                 (OFFSET, MASK, VALUE)      (0XFD070564, 0x000073FFU ,0x0000200FU)
4438                 RegMask = (DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK |  0 );
4439
4440                 RegVal = ((0x00000000U << DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT
4441                         | 0x00000001U << DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT
4442                         | 0x00000000U << DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT
4443                         | 0x0000000FU << DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT
4444                         |  0 ) & RegMask); */
4445                 PSU_Mask_Write (DDRC_PCFGR_2_OFFSET ,0x000073FFU ,0x0000200FU);
4446         /*############################################################################################################################ */
4447
4448                 /*Register : PCFGW_2 @ 0XFD070568</p>
4449
4450                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4451                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4452                 imit register.
4453                 PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN                                           0x1
4454
4455                 If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
4456                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
4457                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
4458                 not associated with any particular command).
4459                 PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN                                              0x1
4460
4461                 If set to 1, enables aging function for the write channel of the port.
4462                 PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN                                               0x0
4463
4464                 Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
4465                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4466                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
4467                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
4468                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
4469                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
4470                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
4471                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.
4472                 PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY                                               0xf
4473
4474                 Port n Configuration Write Register
4475                 (OFFSET, MASK, VALUE)      (0XFD070568, 0x000073FFU ,0x0000600FU)
4476                 RegMask = (DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK |  0 );
4477
4478                 RegVal = ((0x00000001U << DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT
4479                         | 0x00000001U << DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT
4480                         | 0x00000000U << DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT
4481                         | 0x0000000FU << DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT
4482                         |  0 ) & RegMask); */
4483                 PSU_Mask_Write (DDRC_PCFGW_2_OFFSET ,0x000073FFU ,0x0000600FU);
4484         /*############################################################################################################################ */
4485
4486                 /*Register : PCTRL_2 @ 0XFD0705F0</p>
4487
4488                 Enables port n.
4489                 PSU_DDRC_PCTRL_2_PORT_EN                                                        0x1
4490
4491                 Port n Control Register
4492                 (OFFSET, MASK, VALUE)      (0XFD0705F0, 0x00000001U ,0x00000001U)
4493                 RegMask = (DDRC_PCTRL_2_PORT_EN_MASK |  0 );
4494
4495                 RegVal = ((0x00000001U << DDRC_PCTRL_2_PORT_EN_SHIFT
4496                         |  0 ) & RegMask); */
4497                 PSU_Mask_Write (DDRC_PCTRL_2_OFFSET ,0x00000001U ,0x00000001U);
4498         /*############################################################################################################################ */
4499
4500                 /*Register : PCFGQOS0_2 @ 0XFD0705F4</p>
4501
4502                 This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address
4503                 ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2
4504                 s set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4505                 PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2                                            0x2
4506
4507                 This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
4508                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
4509                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4510                 PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1                                            0x0
4511
4512                 This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
4513                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
4514                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4515                 PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0                                            0x0
4516
4517                 Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
4518                 el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
4519                 directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers
4520                 ust be set to distinct values.
4521                 PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2                                             0xb
4522
4523                 Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
4524                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
4525                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
4526                  values.
4527                 PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1                                             0x3
4528
4529                 Port n Read QoS Configuration Register 0
4530                 (OFFSET, MASK, VALUE)      (0XFD0705F4, 0x03330F0FU ,0x02000B03U)
4531                 RegMask = (DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK |  0 );
4532
4533                 RegVal = ((0x00000002U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT
4534                         | 0x00000000U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT
4535                         | 0x00000000U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT
4536                         | 0x0000000BU << DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT
4537                         | 0x00000003U << DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT
4538                         |  0 ) & RegMask); */
4539                 PSU_Mask_Write (DDRC_PCFGQOS0_2_OFFSET ,0x03330F0FU ,0x02000B03U);
4540         /*############################################################################################################################ */
4541
4542                 /*Register : PCFGQOS1_2 @ 0XFD0705F8</p>
4543
4544                 Specifies the timeout value for transactions mapped to the red address queue.
4545                 PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR                                           0x0
4546
4547                 Specifies the timeout value for transactions mapped to the blue address queue.
4548                 PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB                                           0x0
4549
4550                 Port n Read QoS Configuration Register 1
4551                 (OFFSET, MASK, VALUE)      (0XFD0705F8, 0x07FF07FFU ,0x00000000U)
4552                 RegMask = (DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK |  0 );
4553
4554                 RegVal = ((0x00000000U << DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT
4555                         | 0x00000000U << DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT
4556                         |  0 ) & RegMask); */
4557                 PSU_Mask_Write (DDRC_PCFGQOS1_2_OFFSET ,0x07FF07FFU ,0x00000000U);
4558         /*############################################################################################################################ */
4559
4560                 /*Register : PCFGR_3 @ 0XFD070614</p>
4561
4562                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4563                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4564                 imit register.
4565                 PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN                                           0x0
4566
4567                 If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
4568                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
4569                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
4570                 ess handshaking (it is not associated with any particular command).
4571                 PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN                                              0x1
4572
4573                 If set to 1, enables aging function for the read channel of the port.
4574                 PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN                                               0x0
4575
4576                 Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
4577                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4578                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
4579                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
4580                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
4581                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
4582                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
4583                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
4584                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
4585                 he two LSBs of this register field are tied internally to 2'b00.
4586                 PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY                                               0xf
4587
4588                 Port n Configuration Read Register
4589                 (OFFSET, MASK, VALUE)      (0XFD070614, 0x000073FFU ,0x0000200FU)
4590                 RegMask = (DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK |  0 );
4591
4592                 RegVal = ((0x00000000U << DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT
4593                         | 0x00000001U << DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT
4594                         | 0x00000000U << DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT
4595                         | 0x0000000FU << DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT
4596                         |  0 ) & RegMask); */
4597                 PSU_Mask_Write (DDRC_PCFGR_3_OFFSET ,0x000073FFU ,0x0000200FU);
4598         /*############################################################################################################################ */
4599
4600                 /*Register : PCFGW_3 @ 0XFD070618</p>
4601
4602                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4603                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4604                 imit register.
4605                 PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN                                           0x1
4606
4607                 If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
4608                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
4609                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
4610                 not associated with any particular command).
4611                 PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN                                              0x1
4612
4613                 If set to 1, enables aging function for the write channel of the port.
4614                 PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN                                               0x0
4615
4616                 Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
4617                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4618                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
4619                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
4620                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
4621                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
4622                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
4623                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.
4624                 PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY                                               0xf
4625
4626                 Port n Configuration Write Register
4627                 (OFFSET, MASK, VALUE)      (0XFD070618, 0x000073FFU ,0x0000600FU)
4628                 RegMask = (DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK |  0 );
4629
4630                 RegVal = ((0x00000001U << DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT
4631                         | 0x00000001U << DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT
4632                         | 0x00000000U << DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT
4633                         | 0x0000000FU << DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT
4634                         |  0 ) & RegMask); */
4635                 PSU_Mask_Write (DDRC_PCFGW_3_OFFSET ,0x000073FFU ,0x0000600FU);
4636         /*############################################################################################################################ */
4637
4638                 /*Register : PCTRL_3 @ 0XFD0706A0</p>
4639
4640                 Enables port n.
4641                 PSU_DDRC_PCTRL_3_PORT_EN                                                        0x1
4642
4643                 Port n Control Register
4644                 (OFFSET, MASK, VALUE)      (0XFD0706A0, 0x00000001U ,0x00000001U)
4645                 RegMask = (DDRC_PCTRL_3_PORT_EN_MASK |  0 );
4646
4647                 RegVal = ((0x00000001U << DDRC_PCTRL_3_PORT_EN_SHIFT
4648                         |  0 ) & RegMask); */
4649                 PSU_Mask_Write (DDRC_PCTRL_3_OFFSET ,0x00000001U ,0x00000001U);
4650         /*############################################################################################################################ */
4651
4652                 /*Register : PCFGQOS0_3 @ 0XFD0706A4</p>
4653
4654                 This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
4655                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
4656                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4657                 PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1                                            0x1
4658
4659                 This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
4660                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
4661                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4662                 PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0                                            0x0
4663
4664                 Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
4665                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
4666                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
4667                  values.
4668                 PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1                                             0x3
4669
4670                 Port n Read QoS Configuration Register 0
4671                 (OFFSET, MASK, VALUE)      (0XFD0706A4, 0x0033000FU ,0x00100003U)
4672                 RegMask = (DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK |  0 );
4673
4674                 RegVal = ((0x00000001U << DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT
4675                         | 0x00000000U << DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT
4676                         | 0x00000003U << DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT
4677                         |  0 ) & RegMask); */
4678                 PSU_Mask_Write (DDRC_PCFGQOS0_3_OFFSET ,0x0033000FU ,0x00100003U);
4679         /*############################################################################################################################ */
4680
4681                 /*Register : PCFGQOS1_3 @ 0XFD0706A8</p>
4682
4683                 Specifies the timeout value for transactions mapped to the red address queue.
4684                 PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR                                           0x0
4685
4686                 Specifies the timeout value for transactions mapped to the blue address queue.
4687                 PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB                                           0x4f
4688
4689                 Port n Read QoS Configuration Register 1
4690                 (OFFSET, MASK, VALUE)      (0XFD0706A8, 0x07FF07FFU ,0x0000004FU)
4691                 RegMask = (DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK |  0 );
4692
4693                 RegVal = ((0x00000000U << DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT
4694                         | 0x0000004FU << DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT
4695                         |  0 ) & RegMask); */
4696                 PSU_Mask_Write (DDRC_PCFGQOS1_3_OFFSET ,0x07FF07FFU ,0x0000004FU);
4697         /*############################################################################################################################ */
4698
4699                 /*Register : PCFGWQOS0_3 @ 0XFD0706AC</p>
4700
4701                 This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
4702                 VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
4703                 PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1                                           0x1
4704
4705                 This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
4706                 VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
4707                 PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0                                           0x0
4708
4709                 Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
4710                 rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
4711                 s to higher port priority.
4712                 PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL                                             0x3
4713
4714                 Port n Write QoS Configuration Register 0
4715                 (OFFSET, MASK, VALUE)      (0XFD0706AC, 0x0033000FU ,0x00100003U)
4716                 RegMask = (DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK |  0 );
4717
4718                 RegVal = ((0x00000001U << DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT
4719                         | 0x00000000U << DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT
4720                         | 0x00000003U << DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT
4721                         |  0 ) & RegMask); */
4722                 PSU_Mask_Write (DDRC_PCFGWQOS0_3_OFFSET ,0x0033000FU ,0x00100003U);
4723         /*############################################################################################################################ */
4724
4725                 /*Register : PCFGWQOS1_3 @ 0XFD0706B0</p>
4726
4727                 Specifies the timeout value for write transactions.
4728                 PSU_DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT                                           0x4f
4729
4730                 Port n Write QoS Configuration Register 1
4731                 (OFFSET, MASK, VALUE)      (0XFD0706B0, 0x000007FFU ,0x0000004FU)
4732                 RegMask = (DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK |  0 );
4733
4734                 RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT
4735                         |  0 ) & RegMask); */
4736                 PSU_Mask_Write (DDRC_PCFGWQOS1_3_OFFSET ,0x000007FFU ,0x0000004FU);
4737         /*############################################################################################################################ */
4738
4739                 /*Register : PCFGR_4 @ 0XFD0706C4</p>
4740
4741                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4742                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4743                 imit register.
4744                 PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN                                           0x1
4745
4746                 If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
4747                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
4748                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
4749                 ess handshaking (it is not associated with any particular command).
4750                 PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN                                              0x1
4751
4752                 If set to 1, enables aging function for the read channel of the port.
4753                 PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN                                               0x0
4754
4755                 Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
4756                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4757                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
4758                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
4759                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
4760                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
4761                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
4762                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
4763                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
4764                 he two LSBs of this register field are tied internally to 2'b00.
4765                 PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY                                               0xf
4766
4767                 Port n Configuration Read Register
4768                 (OFFSET, MASK, VALUE)      (0XFD0706C4, 0x000073FFU ,0x0000600FU)
4769                 RegMask = (DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK |  0 );
4770
4771                 RegVal = ((0x00000001U << DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT
4772                         | 0x00000001U << DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT
4773                         | 0x00000000U << DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT
4774                         | 0x0000000FU << DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT
4775                         |  0 ) & RegMask); */
4776                 PSU_Mask_Write (DDRC_PCFGR_4_OFFSET ,0x000073FFU ,0x0000600FU);
4777         /*############################################################################################################################ */
4778
4779                 /*Register : PCFGW_4 @ 0XFD0706C8</p>
4780
4781                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4782                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4783                 imit register.
4784                 PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN                                           0x1
4785
4786                 If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
4787                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
4788                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
4789                 not associated with any particular command).
4790                 PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN                                              0x1
4791
4792                 If set to 1, enables aging function for the write channel of the port.
4793                 PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN                                               0x0
4794
4795                 Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
4796                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4797                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
4798                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
4799                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
4800                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
4801                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
4802                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.
4803                 PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY                                               0xf
4804
4805                 Port n Configuration Write Register
4806                 (OFFSET, MASK, VALUE)      (0XFD0706C8, 0x000073FFU ,0x0000600FU)
4807                 RegMask = (DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK |  0 );
4808
4809                 RegVal = ((0x00000001U << DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT
4810                         | 0x00000001U << DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT
4811                         | 0x00000000U << DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT
4812                         | 0x0000000FU << DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT
4813                         |  0 ) & RegMask); */
4814                 PSU_Mask_Write (DDRC_PCFGW_4_OFFSET ,0x000073FFU ,0x0000600FU);
4815         /*############################################################################################################################ */
4816
4817                 /*Register : PCTRL_4 @ 0XFD070750</p>
4818
4819                 Enables port n.
4820                 PSU_DDRC_PCTRL_4_PORT_EN                                                        0x1
4821
4822                 Port n Control Register
4823                 (OFFSET, MASK, VALUE)      (0XFD070750, 0x00000001U ,0x00000001U)
4824                 RegMask = (DDRC_PCTRL_4_PORT_EN_MASK |  0 );
4825
4826                 RegVal = ((0x00000001U << DDRC_PCTRL_4_PORT_EN_SHIFT
4827                         |  0 ) & RegMask); */
4828                 PSU_Mask_Write (DDRC_PCTRL_4_OFFSET ,0x00000001U ,0x00000001U);
4829         /*############################################################################################################################ */
4830
4831                 /*Register : PCFGQOS0_4 @ 0XFD070754</p>
4832
4833                 This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
4834                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
4835                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4836                 PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1                                            0x1
4837
4838                 This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
4839                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
4840                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4841                 PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0                                            0x0
4842
4843                 Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
4844                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
4845                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
4846                  values.
4847                 PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1                                             0x3
4848
4849                 Port n Read QoS Configuration Register 0
4850                 (OFFSET, MASK, VALUE)      (0XFD070754, 0x0033000FU ,0x00100003U)
4851                 RegMask = (DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK |  0 );
4852
4853                 RegVal = ((0x00000001U << DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT
4854                         | 0x00000000U << DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT
4855                         | 0x00000003U << DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT
4856                         |  0 ) & RegMask); */
4857                 PSU_Mask_Write (DDRC_PCFGQOS0_4_OFFSET ,0x0033000FU ,0x00100003U);
4858         /*############################################################################################################################ */
4859
4860                 /*Register : PCFGQOS1_4 @ 0XFD070758</p>
4861
4862                 Specifies the timeout value for transactions mapped to the red address queue.
4863                 PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR                                           0x0
4864
4865                 Specifies the timeout value for transactions mapped to the blue address queue.
4866                 PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB                                           0x4f
4867
4868                 Port n Read QoS Configuration Register 1
4869                 (OFFSET, MASK, VALUE)      (0XFD070758, 0x07FF07FFU ,0x0000004FU)
4870                 RegMask = (DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK |  0 );
4871
4872                 RegVal = ((0x00000000U << DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT
4873                         | 0x0000004FU << DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT
4874                         |  0 ) & RegMask); */
4875                 PSU_Mask_Write (DDRC_PCFGQOS1_4_OFFSET ,0x07FF07FFU ,0x0000004FU);
4876         /*############################################################################################################################ */
4877
4878                 /*Register : PCFGWQOS0_4 @ 0XFD07075C</p>
4879
4880                 This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
4881                 VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
4882                 PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1                                           0x1
4883
4884                 This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
4885                 VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
4886                 PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0                                           0x0
4887
4888                 Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
4889                 rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
4890                 s to higher port priority.
4891                 PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL                                             0x3
4892
4893                 Port n Write QoS Configuration Register 0
4894                 (OFFSET, MASK, VALUE)      (0XFD07075C, 0x0033000FU ,0x00100003U)
4895                 RegMask = (DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK |  0 );
4896
4897                 RegVal = ((0x00000001U << DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT
4898                         | 0x00000000U << DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT
4899                         | 0x00000003U << DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT
4900                         |  0 ) & RegMask); */
4901                 PSU_Mask_Write (DDRC_PCFGWQOS0_4_OFFSET ,0x0033000FU ,0x00100003U);
4902         /*############################################################################################################################ */
4903
4904                 /*Register : PCFGWQOS1_4 @ 0XFD070760</p>
4905
4906                 Specifies the timeout value for write transactions.
4907                 PSU_DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT                                           0x4f
4908
4909                 Port n Write QoS Configuration Register 1
4910                 (OFFSET, MASK, VALUE)      (0XFD070760, 0x000007FFU ,0x0000004FU)
4911                 RegMask = (DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK |  0 );
4912
4913                 RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT
4914                         |  0 ) & RegMask); */
4915                 PSU_Mask_Write (DDRC_PCFGWQOS1_4_OFFSET ,0x000007FFU ,0x0000004FU);
4916         /*############################################################################################################################ */
4917
4918                 /*Register : PCFGR_5 @ 0XFD070774</p>
4919
4920                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4921                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4922                 imit register.
4923                 PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN                                           0x0
4924
4925                 If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
4926                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
4927                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
4928                 ess handshaking (it is not associated with any particular command).
4929                 PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN                                              0x1
4930
4931                 If set to 1, enables aging function for the read channel of the port.
4932                 PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN                                               0x0
4933
4934                 Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
4935                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4936                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
4937                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
4938                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
4939                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
4940                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
4941                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
4942                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
4943                 he two LSBs of this register field are tied internally to 2'b00.
4944                 PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY                                               0xf
4945
4946                 Port n Configuration Read Register
4947                 (OFFSET, MASK, VALUE)      (0XFD070774, 0x000073FFU ,0x0000200FU)
4948                 RegMask = (DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK |  0 );
4949
4950                 RegVal = ((0x00000000U << DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT
4951                         | 0x00000001U << DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT
4952                         | 0x00000000U << DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT
4953                         | 0x0000000FU << DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT
4954                         |  0 ) & RegMask); */
4955                 PSU_Mask_Write (DDRC_PCFGR_5_OFFSET ,0x000073FFU ,0x0000200FU);
4956         /*############################################################################################################################ */
4957
4958                 /*Register : PCFGW_5 @ 0XFD070778</p>
4959
4960                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4961                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4962                 imit register.
4963                 PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN                                           0x1
4964
4965                 If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
4966                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
4967                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
4968                 not associated with any particular command).
4969                 PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN                                              0x1
4970
4971                 If set to 1, enables aging function for the write channel of the port.
4972                 PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN                                               0x0
4973
4974                 Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
4975                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4976                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
4977                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
4978                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
4979                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
4980                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
4981                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.
4982                 PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY                                               0xf
4983
4984                 Port n Configuration Write Register
4985                 (OFFSET, MASK, VALUE)      (0XFD070778, 0x000073FFU ,0x0000600FU)
4986                 RegMask = (DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK |  0 );
4987
4988                 RegVal = ((0x00000001U << DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT
4989                         | 0x00000001U << DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT
4990                         | 0x00000000U << DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT
4991                         | 0x0000000FU << DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT
4992                         |  0 ) & RegMask); */
4993                 PSU_Mask_Write (DDRC_PCFGW_5_OFFSET ,0x000073FFU ,0x0000600FU);
4994         /*############################################################################################################################ */
4995
4996                 /*Register : PCTRL_5 @ 0XFD070800</p>
4997
4998                 Enables port n.
4999                 PSU_DDRC_PCTRL_5_PORT_EN                                                        0x1
5000
5001                 Port n Control Register
5002                 (OFFSET, MASK, VALUE)      (0XFD070800, 0x00000001U ,0x00000001U)
5003                 RegMask = (DDRC_PCTRL_5_PORT_EN_MASK |  0 );
5004
5005                 RegVal = ((0x00000001U << DDRC_PCTRL_5_PORT_EN_SHIFT
5006                         |  0 ) & RegMask); */
5007                 PSU_Mask_Write (DDRC_PCTRL_5_OFFSET ,0x00000001U ,0x00000001U);
5008         /*############################################################################################################################ */
5009
5010                 /*Register : PCFGQOS0_5 @ 0XFD070804</p>
5011
5012                 This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
5013                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
5014                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
5015                 PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1                                            0x1
5016
5017                 This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
5018                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
5019                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
5020                 PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0                                            0x0
5021
5022                 Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
5023                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
5024                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
5025                  values.
5026                 PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1                                             0x3
5027
5028                 Port n Read QoS Configuration Register 0
5029                 (OFFSET, MASK, VALUE)      (0XFD070804, 0x0033000FU ,0x00100003U)
5030                 RegMask = (DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK |  0 );
5031
5032                 RegVal = ((0x00000001U << DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT
5033                         | 0x00000000U << DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT
5034                         | 0x00000003U << DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT
5035                         |  0 ) & RegMask); */
5036                 PSU_Mask_Write (DDRC_PCFGQOS0_5_OFFSET ,0x0033000FU ,0x00100003U);
5037         /*############################################################################################################################ */
5038
5039                 /*Register : PCFGQOS1_5 @ 0XFD070808</p>
5040
5041                 Specifies the timeout value for transactions mapped to the red address queue.
5042                 PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR                                           0x0
5043
5044                 Specifies the timeout value for transactions mapped to the blue address queue.
5045                 PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB                                           0x4f
5046
5047                 Port n Read QoS Configuration Register 1
5048                 (OFFSET, MASK, VALUE)      (0XFD070808, 0x07FF07FFU ,0x0000004FU)
5049                 RegMask = (DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK |  0 );
5050
5051                 RegVal = ((0x00000000U << DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT
5052                         | 0x0000004FU << DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT
5053                         |  0 ) & RegMask); */
5054                 PSU_Mask_Write (DDRC_PCFGQOS1_5_OFFSET ,0x07FF07FFU ,0x0000004FU);
5055         /*############################################################################################################################ */
5056
5057                 /*Register : PCFGWQOS0_5 @ 0XFD07080C</p>
5058
5059                 This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5060                 VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
5061                 PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1                                           0x1
5062
5063                 This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5064                 VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
5065                 PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0                                           0x0
5066
5067                 Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
5068                 rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
5069                 s to higher port priority.
5070                 PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL                                             0x3
5071
5072                 Port n Write QoS Configuration Register 0
5073                 (OFFSET, MASK, VALUE)      (0XFD07080C, 0x0033000FU ,0x00100003U)
5074                 RegMask = (DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK |  0 );
5075
5076                 RegVal = ((0x00000001U << DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT
5077                         | 0x00000000U << DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT
5078                         | 0x00000003U << DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT
5079                         |  0 ) & RegMask); */
5080                 PSU_Mask_Write (DDRC_PCFGWQOS0_5_OFFSET ,0x0033000FU ,0x00100003U);
5081         /*############################################################################################################################ */
5082
5083                 /*Register : PCFGWQOS1_5 @ 0XFD070810</p>
5084
5085                 Specifies the timeout value for write transactions.
5086                 PSU_DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT                                           0x4f
5087
5088                 Port n Write QoS Configuration Register 1
5089                 (OFFSET, MASK, VALUE)      (0XFD070810, 0x000007FFU ,0x0000004FU)
5090                 RegMask = (DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK |  0 );
5091
5092                 RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT
5093                         |  0 ) & RegMask); */
5094                 PSU_Mask_Write (DDRC_PCFGWQOS1_5_OFFSET ,0x000007FFU ,0x0000004FU);
5095         /*############################################################################################################################ */
5096
5097                 /*Register : SARBASE0 @ 0XFD070F04</p>
5098
5099                 Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
5100                  by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
5101                 PSU_DDRC_SARBASE0_BASE_ADDR                                                     0x0
5102
5103                 SAR Base Address Register n
5104                 (OFFSET, MASK, VALUE)      (0XFD070F04, 0x000001FFU ,0x00000000U)
5105                 RegMask = (DDRC_SARBASE0_BASE_ADDR_MASK |  0 );
5106
5107                 RegVal = ((0x00000000U << DDRC_SARBASE0_BASE_ADDR_SHIFT
5108                         |  0 ) & RegMask); */
5109                 PSU_Mask_Write (DDRC_SARBASE0_OFFSET ,0x000001FFU ,0x00000000U);
5110         /*############################################################################################################################ */
5111
5112                 /*Register : SARSIZE0 @ 0XFD070F08</p>
5113
5114                 Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
5115                 e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1.
5116                 or example, if register is programmed to 0, region will have 1 block.
5117                 PSU_DDRC_SARSIZE0_NBLOCKS                                                       0x0
5118
5119                 SAR Size Register n
5120                 (OFFSET, MASK, VALUE)      (0XFD070F08, 0x000000FFU ,0x00000000U)
5121                 RegMask = (DDRC_SARSIZE0_NBLOCKS_MASK |  0 );
5122
5123                 RegVal = ((0x00000000U << DDRC_SARSIZE0_NBLOCKS_SHIFT
5124                         |  0 ) & RegMask); */
5125                 PSU_Mask_Write (DDRC_SARSIZE0_OFFSET ,0x000000FFU ,0x00000000U);
5126         /*############################################################################################################################ */
5127
5128                 /*Register : SARBASE1 @ 0XFD070F0C</p>
5129
5130                 Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
5131                  by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
5132                 PSU_DDRC_SARBASE1_BASE_ADDR                                                     0x10
5133
5134                 SAR Base Address Register n
5135                 (OFFSET, MASK, VALUE)      (0XFD070F0C, 0x000001FFU ,0x00000010U)
5136                 RegMask = (DDRC_SARBASE1_BASE_ADDR_MASK |  0 );
5137
5138                 RegVal = ((0x00000010U << DDRC_SARBASE1_BASE_ADDR_SHIFT
5139                         |  0 ) & RegMask); */
5140                 PSU_Mask_Write (DDRC_SARBASE1_OFFSET ,0x000001FFU ,0x00000010U);
5141         /*############################################################################################################################ */
5142
5143                 /*Register : SARSIZE1 @ 0XFD070F10</p>
5144
5145                 Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
5146                 e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1.
5147                 or example, if register is programmed to 0, region will have 1 block.
5148                 PSU_DDRC_SARSIZE1_NBLOCKS                                                       0xf
5149
5150                 SAR Size Register n
5151                 (OFFSET, MASK, VALUE)      (0XFD070F10, 0x000000FFU ,0x0000000FU)
5152                 RegMask = (DDRC_SARSIZE1_NBLOCKS_MASK |  0 );
5153
5154                 RegVal = ((0x0000000FU << DDRC_SARSIZE1_NBLOCKS_SHIFT
5155                         |  0 ) & RegMask); */
5156                 PSU_Mask_Write (DDRC_SARSIZE1_OFFSET ,0x000000FFU ,0x0000000FU);
5157         /*############################################################################################################################ */
5158
5159                 /*Register : DFITMG0_SHADOW @ 0XFD072190</p>
5160
5161                 Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
5162                 s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
5163                 , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
5164                  this parameter by RDIMM's extra cycle of latency in terms of DFI clock.
5165                 PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY                                        0x7
5166
5167                 Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
5168                 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
5169                 fer to PHY specification for correct value.
5170                 PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR                                      0x1
5171
5172                 Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
5173                 ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
5174                 , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
5175                  latency through the RDIMM. Unit: Clocks
5176                 PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN                                         0x2
5177
5178                 Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
5179                 .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
5180                 HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
5181                 e.
5182                 PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR                                      0x1
5183
5184                 Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
5185                  dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
5186                 te, max supported value is 8. Unit: Clocks
5187                 PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA                                         0x0
5188
5189                 Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
5190                  parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
5191                  necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
5192                 rough the RDIMM.
5193                 PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT                                          0x2
5194
5195                 DFI Timing Shadow Register 0
5196                 (OFFSET, MASK, VALUE)      (0XFD072190, 0x1FBFBF3FU ,0x07828002U)
5197                 RegMask = (DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK | DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK | DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK | DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK | DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK | DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK |  0 );
5198
5199                 RegVal = ((0x00000007U << DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT
5200                         | 0x00000001U << DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT
5201                         | 0x00000002U << DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT
5202                         | 0x00000001U << DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT
5203                         | 0x00000000U << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT
5204                         | 0x00000002U << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT
5205                         |  0 ) & RegMask); */
5206                 PSU_Mask_Write (DDRC_DFITMG0_SHADOW_OFFSET ,0x1FBFBF3FU ,0x07828002U);
5207         /*############################################################################################################################ */
5208
5209                 // : DDR CONTROLLER RESET
5210                 /*Register : RST_DDR_SS @ 0XFD1A0108</p>
5211
5212                 DDR block level reset inside of the DDR Sub System
5213                 PSU_CRF_APB_RST_DDR_SS_DDR_RESET                                                0X0
5214
5215                 DDR sub system block level reset
5216                 (OFFSET, MASK, VALUE)      (0XFD1A0108, 0x00000008U ,0x00000000U)
5217                 RegMask = (CRF_APB_RST_DDR_SS_DDR_RESET_MASK |  0 );
5218
5219                 RegVal = ((0x00000000U << CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT
5220                         |  0 ) & RegMask); */
5221                 PSU_Mask_Write (CRF_APB_RST_DDR_SS_OFFSET ,0x00000008U ,0x00000000U);
5222         /*############################################################################################################################ */
5223
5224                 // : DDR PHY
5225                 /*Register : PGCR0 @ 0XFD080010</p>
5226
5227                 Address Copy
5228                 PSU_DDR_PHY_PGCR0_ADCP                                                          0x0
5229
5230                 Reserved. Returns zeroes on reads.
5231                 PSU_DDR_PHY_PGCR0_RESERVED_30_27                                                0x0
5232
5233                 PHY FIFO Reset
5234                 PSU_DDR_PHY_PGCR0_PHYFRST                                                       0x1
5235
5236                 Oscillator Mode Address/Command Delay Line Select
5237                 PSU_DDR_PHY_PGCR0_OSCACDL                                                       0x3
5238
5239                 Reserved. Returns zeroes on reads.
5240                 PSU_DDR_PHY_PGCR0_RESERVED_23_19                                                0x0
5241
5242                 Digital Test Output Select
5243                 PSU_DDR_PHY_PGCR0_DTOSEL                                                        0x0
5244
5245                 Reserved. Returns zeroes on reads.
5246                 PSU_DDR_PHY_PGCR0_RESERVED_13                                                   0x0
5247
5248                 Oscillator Mode Division
5249                 PSU_DDR_PHY_PGCR0_OSCDIV                                                        0xf
5250
5251                 Oscillator Enable
5252                 PSU_DDR_PHY_PGCR0_OSCEN                                                         0x0
5253
5254                 Reserved. Returns zeroes on reads.
5255                 PSU_DDR_PHY_PGCR0_RESERVED_7_0                                                  0x0
5256
5257                 PHY General Configuration Register 0
5258                 (OFFSET, MASK, VALUE)      (0XFD080010, 0xFFFFFFFFU ,0x07001E00U)
5259                 RegMask = (DDR_PHY_PGCR0_ADCP_MASK | DDR_PHY_PGCR0_RESERVED_30_27_MASK | DDR_PHY_PGCR0_PHYFRST_MASK | DDR_PHY_PGCR0_OSCACDL_MASK | DDR_PHY_PGCR0_RESERVED_23_19_MASK | DDR_PHY_PGCR0_DTOSEL_MASK | DDR_PHY_PGCR0_RESERVED_13_MASK | DDR_PHY_PGCR0_OSCDIV_MASK | DDR_PHY_PGCR0_OSCEN_MASK | DDR_PHY_PGCR0_RESERVED_7_0_MASK |  0 );
5260
5261                 RegVal = ((0x00000000U << DDR_PHY_PGCR0_ADCP_SHIFT
5262                         | 0x00000000U << DDR_PHY_PGCR0_RESERVED_30_27_SHIFT
5263                         | 0x00000001U << DDR_PHY_PGCR0_PHYFRST_SHIFT
5264                         | 0x00000003U << DDR_PHY_PGCR0_OSCACDL_SHIFT
5265                         | 0x00000000U << DDR_PHY_PGCR0_RESERVED_23_19_SHIFT
5266                         | 0x00000000U << DDR_PHY_PGCR0_DTOSEL_SHIFT
5267                         | 0x00000000U << DDR_PHY_PGCR0_RESERVED_13_SHIFT
5268                         | 0x0000000FU << DDR_PHY_PGCR0_OSCDIV_SHIFT
5269                         | 0x00000000U << DDR_PHY_PGCR0_OSCEN_SHIFT
5270                         | 0x00000000U << DDR_PHY_PGCR0_RESERVED_7_0_SHIFT
5271                         |  0 ) & RegMask); */
5272                 PSU_Mask_Write (DDR_PHY_PGCR0_OFFSET ,0xFFFFFFFFU ,0x07001E00U);
5273         /*############################################################################################################################ */
5274
5275                 /*Register : PGCR2 @ 0XFD080018</p>
5276
5277                 Clear Training Status Registers
5278                 PSU_DDR_PHY_PGCR2_CLRTSTAT                                                      0x0
5279
5280                 Clear Impedance Calibration
5281                 PSU_DDR_PHY_PGCR2_CLRZCAL                                                       0x0
5282
5283                 Clear Parity Error
5284                 PSU_DDR_PHY_PGCR2_CLRPERR                                                       0x0
5285
5286                 Initialization Complete Pin Configuration
5287                 PSU_DDR_PHY_PGCR2_ICPC                                                          0x0
5288
5289                 Data Training PUB Mode Exit Timer
5290                 PSU_DDR_PHY_PGCR2_DTPMXTMR                                                      0xf
5291
5292                 Initialization Bypass
5293                 PSU_DDR_PHY_PGCR2_INITFSMBYP                                                    0x0
5294
5295                 PLL FSM Bypass
5296                 PSU_DDR_PHY_PGCR2_PLLFSMBYP                                                     0x0
5297
5298                 Refresh Period
5299                 PSU_DDR_PHY_PGCR2_TREFPRD                                                       0x10028
5300
5301                 PHY General Configuration Register 2
5302                 (OFFSET, MASK, VALUE)      (0XFD080018, 0xFFFFFFFFU ,0x00F10028U)
5303                 RegMask = (DDR_PHY_PGCR2_CLRTSTAT_MASK | DDR_PHY_PGCR2_CLRZCAL_MASK | DDR_PHY_PGCR2_CLRPERR_MASK | DDR_PHY_PGCR2_ICPC_MASK | DDR_PHY_PGCR2_DTPMXTMR_MASK | DDR_PHY_PGCR2_INITFSMBYP_MASK | DDR_PHY_PGCR2_PLLFSMBYP_MASK | DDR_PHY_PGCR2_TREFPRD_MASK |  0 );
5304
5305                 RegVal = ((0x00000000U << DDR_PHY_PGCR2_CLRTSTAT_SHIFT
5306                         | 0x00000000U << DDR_PHY_PGCR2_CLRZCAL_SHIFT
5307                         | 0x00000000U << DDR_PHY_PGCR2_CLRPERR_SHIFT
5308                         | 0x00000000U << DDR_PHY_PGCR2_ICPC_SHIFT
5309                         | 0x0000000FU << DDR_PHY_PGCR2_DTPMXTMR_SHIFT
5310                         | 0x00000000U << DDR_PHY_PGCR2_INITFSMBYP_SHIFT
5311                         | 0x00000000U << DDR_PHY_PGCR2_PLLFSMBYP_SHIFT
5312                         | 0x00010028U << DDR_PHY_PGCR2_TREFPRD_SHIFT
5313                         |  0 ) & RegMask); */
5314                 PSU_Mask_Write (DDR_PHY_PGCR2_OFFSET ,0xFFFFFFFFU ,0x00F10028U);
5315         /*############################################################################################################################ */
5316
5317                 /*Register : PGCR3 @ 0XFD08001C</p>
5318
5319                 CKN Enable
5320                 PSU_DDR_PHY_PGCR3_CKNEN                                                         0x55
5321
5322                 CK Enable
5323                 PSU_DDR_PHY_PGCR3_CKEN                                                          0xaa
5324
5325                 Reserved. Return zeroes on reads.
5326                 PSU_DDR_PHY_PGCR3_RESERVED_15                                                   0x0
5327
5328                 Enable Clock Gating for AC [0] ctl_rd_clk
5329                 PSU_DDR_PHY_PGCR3_GATEACRDCLK                                                   0x2
5330
5331                 Enable Clock Gating for AC [0] ddr_clk
5332                 PSU_DDR_PHY_PGCR3_GATEACDDRCLK                                                  0x2
5333
5334                 Enable Clock Gating for AC [0] ctl_clk
5335                 PSU_DDR_PHY_PGCR3_GATEACCTLCLK                                                  0x2
5336
5337                 Reserved. Return zeroes on reads.
5338                 PSU_DDR_PHY_PGCR3_RESERVED_8                                                    0x0
5339
5340                 Controls DDL Bypass Modes
5341                 PSU_DDR_PHY_PGCR3_DDLBYPMODE                                                    0x2
5342
5343                 IO Loop-Back Select
5344                 PSU_DDR_PHY_PGCR3_IOLB                                                          0x0
5345
5346                 AC Receive FIFO Read Mode
5347                 PSU_DDR_PHY_PGCR3_RDMODE                                                        0x0
5348
5349                 Read FIFO Reset Disable
5350                 PSU_DDR_PHY_PGCR3_DISRST                                                        0x0
5351
5352                 Clock Level when Clock Gating
5353                 PSU_DDR_PHY_PGCR3_CLKLEVEL                                                      0x0
5354
5355                 PHY General Configuration Register 3
5356                 (OFFSET, MASK, VALUE)      (0XFD08001C, 0xFFFFFFFFU ,0x55AA5480U)
5357                 RegMask = (DDR_PHY_PGCR3_CKNEN_MASK | DDR_PHY_PGCR3_CKEN_MASK | DDR_PHY_PGCR3_RESERVED_15_MASK | DDR_PHY_PGCR3_GATEACRDCLK_MASK | DDR_PHY_PGCR3_GATEACDDRCLK_MASK | DDR_PHY_PGCR3_GATEACCTLCLK_MASK | DDR_PHY_PGCR3_RESERVED_8_MASK | DDR_PHY_PGCR3_DDLBYPMODE_MASK | DDR_PHY_PGCR3_IOLB_MASK | DDR_PHY_PGCR3_RDMODE_MASK | DDR_PHY_PGCR3_DISRST_MASK | DDR_PHY_PGCR3_CLKLEVEL_MASK |  0 );
5358
5359                 RegVal = ((0x00000055U << DDR_PHY_PGCR3_CKNEN_SHIFT
5360                         | 0x000000AAU << DDR_PHY_PGCR3_CKEN_SHIFT
5361                         | 0x00000000U << DDR_PHY_PGCR3_RESERVED_15_SHIFT
5362                         | 0x00000002U << DDR_PHY_PGCR3_GATEACRDCLK_SHIFT
5363                         | 0x00000002U << DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT
5364                         | 0x00000002U << DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT
5365                         | 0x00000000U << DDR_PHY_PGCR3_RESERVED_8_SHIFT
5366                         | 0x00000002U << DDR_PHY_PGCR3_DDLBYPMODE_SHIFT
5367                         | 0x00000000U << DDR_PHY_PGCR3_IOLB_SHIFT
5368                         | 0x00000000U << DDR_PHY_PGCR3_RDMODE_SHIFT
5369                         | 0x00000000U << DDR_PHY_PGCR3_DISRST_SHIFT
5370                         | 0x00000000U << DDR_PHY_PGCR3_CLKLEVEL_SHIFT
5371                         |  0 ) & RegMask); */
5372                 PSU_Mask_Write (DDR_PHY_PGCR3_OFFSET ,0xFFFFFFFFU ,0x55AA5480U);
5373         /*############################################################################################################################ */
5374
5375                 /*Register : PGCR5 @ 0XFD080024</p>
5376
5377                 Frequency B Ratio Term
5378                 PSU_DDR_PHY_PGCR5_FRQBT                                                         0x1
5379
5380                 Frequency A Ratio Term
5381                 PSU_DDR_PHY_PGCR5_FRQAT                                                         0x1
5382
5383                 DFI Disconnect Time Period
5384                 PSU_DDR_PHY_PGCR5_DISCNPERIOD                                                   0x0
5385
5386                 Receiver bias core side control
5387                 PSU_DDR_PHY_PGCR5_VREF_RBCTRL                                                   0xf
5388
5389                 Reserved. Return zeroes on reads.
5390                 PSU_DDR_PHY_PGCR5_RESERVED_3                                                    0x0
5391
5392                 Internal VREF generator REFSEL ragne select
5393                 PSU_DDR_PHY_PGCR5_DXREFISELRANGE                                                0x1
5394
5395                 DDL Page Read Write select
5396                 PSU_DDR_PHY_PGCR5_DDLPGACT                                                      0x0
5397
5398                 DDL Page Read Write select
5399                 PSU_DDR_PHY_PGCR5_DDLPGRW                                                       0x0
5400
5401                 PHY General Configuration Register 5
5402                 (OFFSET, MASK, VALUE)      (0XFD080024, 0xFFFFFFFFU ,0x010100F4U)
5403                 RegMask = (DDR_PHY_PGCR5_FRQBT_MASK | DDR_PHY_PGCR5_FRQAT_MASK | DDR_PHY_PGCR5_DISCNPERIOD_MASK | DDR_PHY_PGCR5_VREF_RBCTRL_MASK | DDR_PHY_PGCR5_RESERVED_3_MASK | DDR_PHY_PGCR5_DXREFISELRANGE_MASK | DDR_PHY_PGCR5_DDLPGACT_MASK | DDR_PHY_PGCR5_DDLPGRW_MASK |  0 );
5404
5405                 RegVal = ((0x00000001U << DDR_PHY_PGCR5_FRQBT_SHIFT
5406                         | 0x00000001U << DDR_PHY_PGCR5_FRQAT_SHIFT
5407                         | 0x00000000U << DDR_PHY_PGCR5_DISCNPERIOD_SHIFT
5408                         | 0x0000000FU << DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT
5409                         | 0x00000000U << DDR_PHY_PGCR5_RESERVED_3_SHIFT
5410                         | 0x00000001U << DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT
5411                         | 0x00000000U << DDR_PHY_PGCR5_DDLPGACT_SHIFT
5412                         | 0x00000000U << DDR_PHY_PGCR5_DDLPGRW_SHIFT
5413                         |  0 ) & RegMask); */
5414                 PSU_Mask_Write (DDR_PHY_PGCR5_OFFSET ,0xFFFFFFFFU ,0x010100F4U);
5415         /*############################################################################################################################ */
5416
5417                 /*Register : PTR0 @ 0XFD080040</p>
5418
5419                 PLL Power-Down Time
5420                 PSU_DDR_PHY_PTR0_TPLLPD                                                         0x2f0
5421
5422                 PLL Gear Shift Time
5423                 PSU_DDR_PHY_PTR0_TPLLGS                                                         0x60
5424
5425                 PHY Reset Time
5426                 PSU_DDR_PHY_PTR0_TPHYRST                                                        0x10
5427
5428                 PHY Timing Register 0
5429                 (OFFSET, MASK, VALUE)      (0XFD080040, 0xFFFFFFFFU ,0x5E001810U)
5430                 RegMask = (DDR_PHY_PTR0_TPLLPD_MASK | DDR_PHY_PTR0_TPLLGS_MASK | DDR_PHY_PTR0_TPHYRST_MASK |  0 );
5431
5432                 RegVal = ((0x000002F0U << DDR_PHY_PTR0_TPLLPD_SHIFT
5433                         | 0x00000060U << DDR_PHY_PTR0_TPLLGS_SHIFT
5434                         | 0x00000010U << DDR_PHY_PTR0_TPHYRST_SHIFT
5435                         |  0 ) & RegMask); */
5436                 PSU_Mask_Write (DDR_PHY_PTR0_OFFSET ,0xFFFFFFFFU ,0x5E001810U);
5437         /*############################################################################################################################ */
5438
5439                 /*Register : PTR1 @ 0XFD080044</p>
5440
5441                 PLL Lock Time
5442                 PSU_DDR_PHY_PTR1_TPLLLOCK                                                       0x80
5443
5444                 Reserved. Returns zeroes on reads.
5445                 PSU_DDR_PHY_PTR1_RESERVED_15_13                                                 0x0
5446
5447                 PLL Reset Time
5448                 PSU_DDR_PHY_PTR1_TPLLRST                                                        0x5f0
5449
5450                 PHY Timing Register 1
5451                 (OFFSET, MASK, VALUE)      (0XFD080044, 0xFFFFFFFFU ,0x008005F0U)
5452                 RegMask = (DDR_PHY_PTR1_TPLLLOCK_MASK | DDR_PHY_PTR1_RESERVED_15_13_MASK | DDR_PHY_PTR1_TPLLRST_MASK |  0 );
5453
5454                 RegVal = ((0x00000080U << DDR_PHY_PTR1_TPLLLOCK_SHIFT
5455                         | 0x00000000U << DDR_PHY_PTR1_RESERVED_15_13_SHIFT
5456                         | 0x000005F0U << DDR_PHY_PTR1_TPLLRST_SHIFT
5457                         |  0 ) & RegMask); */
5458                 PSU_Mask_Write (DDR_PHY_PTR1_OFFSET ,0xFFFFFFFFU ,0x008005F0U);
5459         /*############################################################################################################################ */
5460
5461                 /*Register : DSGCR @ 0XFD080090</p>
5462
5463                 Reserved. Return zeroes on reads.
5464                 PSU_DDR_PHY_DSGCR_RESERVED_31_28                                                0x0
5465
5466                 When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d
5467                 fault calculation.
5468                 PSU_DDR_PHY_DSGCR_RDBICLSEL                                                     0x0
5469
5470                 When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value.
5471                 PSU_DDR_PHY_DSGCR_RDBICL                                                        0x2
5472
5473                 PHY Impedance Update Enable
5474                 PSU_DDR_PHY_DSGCR_PHYZUEN                                                       0x1
5475
5476                 Reserved. Return zeroes on reads.
5477                 PSU_DDR_PHY_DSGCR_RESERVED_22                                                   0x0
5478
5479                 SDRAM Reset Output Enable
5480                 PSU_DDR_PHY_DSGCR_RSTOE                                                         0x1
5481
5482                 Single Data Rate Mode
5483                 PSU_DDR_PHY_DSGCR_SDRMODE                                                       0x0
5484
5485                 Reserved. Return zeroes on reads.
5486                 PSU_DDR_PHY_DSGCR_RESERVED_18                                                   0x0
5487
5488                 ATO Analog Test Enable
5489                 PSU_DDR_PHY_DSGCR_ATOAE                                                         0x0
5490
5491                 DTO Output Enable
5492                 PSU_DDR_PHY_DSGCR_DTOOE                                                         0x0
5493
5494                 DTO I/O Mode
5495                 PSU_DDR_PHY_DSGCR_DTOIOM                                                        0x0
5496
5497                 DTO Power Down Receiver
5498                 PSU_DDR_PHY_DSGCR_DTOPDR                                                        0x1
5499
5500                 Reserved. Return zeroes on reads
5501                 PSU_DDR_PHY_DSGCR_RESERVED_13                                                   0x0
5502
5503                 DTO On-Die Termination
5504                 PSU_DDR_PHY_DSGCR_DTOODT                                                        0x0
5505
5506                 PHY Update Acknowledge Delay
5507                 PSU_DDR_PHY_DSGCR_PUAD                                                          0x4
5508
5509                 Controller Update Acknowledge Enable
5510                 PSU_DDR_PHY_DSGCR_CUAEN                                                         0x1
5511
5512                 Reserved. Return zeroes on reads
5513                 PSU_DDR_PHY_DSGCR_RESERVED_4_3                                                  0x0
5514
5515                 Controller Impedance Update Enable
5516                 PSU_DDR_PHY_DSGCR_CTLZUEN                                                       0x0
5517
5518                 Reserved. Return zeroes on reads
5519                 PSU_DDR_PHY_DSGCR_RESERVED_1                                                    0x0
5520
5521                 PHY Update Request Enable
5522                 PSU_DDR_PHY_DSGCR_PUREN                                                         0x1
5523
5524                 DDR System General Configuration Register
5525                 (OFFSET, MASK, VALUE)      (0XFD080090, 0xFFFFFFFFU ,0x02A04121U)
5526                 RegMask = (DDR_PHY_DSGCR_RESERVED_31_28_MASK | DDR_PHY_DSGCR_RDBICLSEL_MASK | DDR_PHY_DSGCR_RDBICL_MASK | DDR_PHY_DSGCR_PHYZUEN_MASK | DDR_PHY_DSGCR_RESERVED_22_MASK | DDR_PHY_DSGCR_RSTOE_MASK | DDR_PHY_DSGCR_SDRMODE_MASK | DDR_PHY_DSGCR_RESERVED_18_MASK | DDR_PHY_DSGCR_ATOAE_MASK | DDR_PHY_DSGCR_DTOOE_MASK | DDR_PHY_DSGCR_DTOIOM_MASK | DDR_PHY_DSGCR_DTOPDR_MASK | DDR_PHY_DSGCR_RESERVED_13_MASK | DDR_PHY_DSGCR_DTOODT_MASK | DDR_PHY_DSGCR_PUAD_MASK | DDR_PHY_DSGCR_CUAEN_MASK | DDR_PHY_DSGCR_RESERVED_4_3_MASK | DDR_PHY_DSGCR_CTLZUEN_MASK | DDR_PHY_DSGCR_RESERVED_1_MASK | DDR_PHY_DSGCR_PUREN_MASK |  0 );
5527
5528                 RegVal = ((0x00000000U << DDR_PHY_DSGCR_RESERVED_31_28_SHIFT
5529                         | 0x00000000U << DDR_PHY_DSGCR_RDBICLSEL_SHIFT
5530                         | 0x00000002U << DDR_PHY_DSGCR_RDBICL_SHIFT
5531                         | 0x00000001U << DDR_PHY_DSGCR_PHYZUEN_SHIFT
5532                         | 0x00000000U << DDR_PHY_DSGCR_RESERVED_22_SHIFT
5533                         | 0x00000001U << DDR_PHY_DSGCR_RSTOE_SHIFT
5534                         | 0x00000000U << DDR_PHY_DSGCR_SDRMODE_SHIFT
5535                         | 0x00000000U << DDR_PHY_DSGCR_RESERVED_18_SHIFT
5536                         | 0x00000000U << DDR_PHY_DSGCR_ATOAE_SHIFT
5537                         | 0x00000000U << DDR_PHY_DSGCR_DTOOE_SHIFT
5538                         | 0x00000000U << DDR_PHY_DSGCR_DTOIOM_SHIFT
5539                         | 0x00000001U << DDR_PHY_DSGCR_DTOPDR_SHIFT
5540                         | 0x00000000U << DDR_PHY_DSGCR_RESERVED_13_SHIFT
5541                         | 0x00000000U << DDR_PHY_DSGCR_DTOODT_SHIFT
5542                         | 0x00000004U << DDR_PHY_DSGCR_PUAD_SHIFT
5543                         | 0x00000001U << DDR_PHY_DSGCR_CUAEN_SHIFT
5544                         | 0x00000000U << DDR_PHY_DSGCR_RESERVED_4_3_SHIFT
5545                         | 0x00000000U << DDR_PHY_DSGCR_CTLZUEN_SHIFT
5546                         | 0x00000000U << DDR_PHY_DSGCR_RESERVED_1_SHIFT
5547                         | 0x00000001U << DDR_PHY_DSGCR_PUREN_SHIFT
5548                         |  0 ) & RegMask); */
5549                 PSU_Mask_Write (DDR_PHY_DSGCR_OFFSET ,0xFFFFFFFFU ,0x02A04121U);
5550         /*############################################################################################################################ */
5551
5552                 /*Register : DCR @ 0XFD080100</p>
5553
5554                 DDR4 Gear Down Timing.
5555                 PSU_DDR_PHY_DCR_GEARDN                                                          0x0
5556
5557                 Un-used Bank Group
5558                 PSU_DDR_PHY_DCR_UBG                                                             0x0
5559
5560                 Un-buffered DIMM Address Mirroring
5561                 PSU_DDR_PHY_DCR_UDIMM                                                           0x0
5562
5563                 DDR 2T Timing
5564                 PSU_DDR_PHY_DCR_DDR2T                                                           0x0
5565
5566                 No Simultaneous Rank Access
5567                 PSU_DDR_PHY_DCR_NOSRA                                                           0x1
5568
5569                 Reserved. Return zeroes on reads.
5570                 PSU_DDR_PHY_DCR_RESERVED_26_18                                                  0x0
5571
5572                 Byte Mask
5573                 PSU_DDR_PHY_DCR_BYTEMASK                                                        0x1
5574
5575                 DDR Type
5576                 PSU_DDR_PHY_DCR_DDRTYPE                                                         0x0
5577
5578                 Multi-Purpose Register (MPR) DQ (DDR3 Only)
5579                 PSU_DDR_PHY_DCR_MPRDQ                                                           0x0
5580
5581                 Primary DQ (DDR3 Only)
5582                 PSU_DDR_PHY_DCR_PDQ                                                             0x0
5583
5584                 DDR 8-Bank
5585                 PSU_DDR_PHY_DCR_DDR8BNK                                                         0x1
5586
5587                 DDR Mode
5588                 PSU_DDR_PHY_DCR_DDRMD                                                           0x4
5589
5590                 DRAM Configuration Register
5591                 (OFFSET, MASK, VALUE)      (0XFD080100, 0xFFFFFFFFU ,0x0800040CU)
5592                 RegMask = (DDR_PHY_DCR_GEARDN_MASK | DDR_PHY_DCR_UBG_MASK | DDR_PHY_DCR_UDIMM_MASK | DDR_PHY_DCR_DDR2T_MASK | DDR_PHY_DCR_NOSRA_MASK | DDR_PHY_DCR_RESERVED_26_18_MASK | DDR_PHY_DCR_BYTEMASK_MASK | DDR_PHY_DCR_DDRTYPE_MASK | DDR_PHY_DCR_MPRDQ_MASK | DDR_PHY_DCR_PDQ_MASK | DDR_PHY_DCR_DDR8BNK_MASK | DDR_PHY_DCR_DDRMD_MASK |  0 );
5593
5594                 RegVal = ((0x00000000U << DDR_PHY_DCR_GEARDN_SHIFT
5595                         | 0x00000000U << DDR_PHY_DCR_UBG_SHIFT
5596                         | 0x00000000U << DDR_PHY_DCR_UDIMM_SHIFT
5597                         | 0x00000000U << DDR_PHY_DCR_DDR2T_SHIFT
5598                         | 0x00000001U << DDR_PHY_DCR_NOSRA_SHIFT
5599                         | 0x00000000U << DDR_PHY_DCR_RESERVED_26_18_SHIFT
5600                         | 0x00000001U << DDR_PHY_DCR_BYTEMASK_SHIFT
5601                         | 0x00000000U << DDR_PHY_DCR_DDRTYPE_SHIFT
5602                         | 0x00000000U << DDR_PHY_DCR_MPRDQ_SHIFT
5603                         | 0x00000000U << DDR_PHY_DCR_PDQ_SHIFT
5604                         | 0x00000001U << DDR_PHY_DCR_DDR8BNK_SHIFT
5605                         | 0x00000004U << DDR_PHY_DCR_DDRMD_SHIFT
5606                         |  0 ) & RegMask); */
5607                 PSU_Mask_Write (DDR_PHY_DCR_OFFSET ,0xFFFFFFFFU ,0x0800040CU);
5608         /*############################################################################################################################ */
5609
5610                 /*Register : DTPR0 @ 0XFD080110</p>
5611
5612                 Reserved. Return zeroes on reads.
5613                 PSU_DDR_PHY_DTPR0_RESERVED_31_29                                                0x0
5614
5615                 Activate to activate command delay (different banks)
5616                 PSU_DDR_PHY_DTPR0_TRRD                                                          0x6
5617
5618                 Reserved. Return zeroes on reads.
5619                 PSU_DDR_PHY_DTPR0_RESERVED_23                                                   0x0
5620
5621                 Activate to precharge command delay
5622                 PSU_DDR_PHY_DTPR0_TRAS                                                          0x24
5623
5624                 Reserved. Return zeroes on reads.
5625                 PSU_DDR_PHY_DTPR0_RESERVED_15                                                   0x0
5626
5627                 Precharge command period
5628                 PSU_DDR_PHY_DTPR0_TRP                                                           0xf
5629
5630                 Reserved. Return zeroes on reads.
5631                 PSU_DDR_PHY_DTPR0_RESERVED_7_5                                                  0x0
5632
5633                 Internal read to precharge command delay
5634                 PSU_DDR_PHY_DTPR0_TRTP                                                          0x9
5635
5636                 DRAM Timing Parameters Register 0
5637                 (OFFSET, MASK, VALUE)      (0XFD080110, 0xFFFFFFFFU ,0x06240F09U)
5638                 RegMask = (DDR_PHY_DTPR0_RESERVED_31_29_MASK | DDR_PHY_DTPR0_TRRD_MASK | DDR_PHY_DTPR0_RESERVED_23_MASK | DDR_PHY_DTPR0_TRAS_MASK | DDR_PHY_DTPR0_RESERVED_15_MASK | DDR_PHY_DTPR0_TRP_MASK | DDR_PHY_DTPR0_RESERVED_7_5_MASK | DDR_PHY_DTPR0_TRTP_MASK |  0 );
5639
5640                 RegVal = ((0x00000000U << DDR_PHY_DTPR0_RESERVED_31_29_SHIFT
5641                         | 0x00000006U << DDR_PHY_DTPR0_TRRD_SHIFT
5642                         | 0x00000000U << DDR_PHY_DTPR0_RESERVED_23_SHIFT
5643                         | 0x00000024U << DDR_PHY_DTPR0_TRAS_SHIFT
5644                         | 0x00000000U << DDR_PHY_DTPR0_RESERVED_15_SHIFT
5645                         | 0x0000000FU << DDR_PHY_DTPR0_TRP_SHIFT
5646                         | 0x00000000U << DDR_PHY_DTPR0_RESERVED_7_5_SHIFT
5647                         | 0x00000009U << DDR_PHY_DTPR0_TRTP_SHIFT
5648                         |  0 ) & RegMask); */
5649                 PSU_Mask_Write (DDR_PHY_DTPR0_OFFSET ,0xFFFFFFFFU ,0x06240F09U);
5650         /*############################################################################################################################ */
5651
5652                 /*Register : DTPR1 @ 0XFD080114</p>
5653
5654                 Reserved. Return zeroes on reads.
5655                 PSU_DDR_PHY_DTPR1_RESERVED_31                                                   0x0
5656
5657                 Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge.
5658                 PSU_DDR_PHY_DTPR1_TWLMRD                                                        0x28
5659
5660                 Reserved. Return zeroes on reads.
5661                 PSU_DDR_PHY_DTPR1_RESERVED_23                                                   0x0
5662
5663                 4-bank activate period
5664                 PSU_DDR_PHY_DTPR1_TFAW                                                          0x18
5665
5666                 Reserved. Return zeroes on reads.
5667                 PSU_DDR_PHY_DTPR1_RESERVED_15_11                                                0x0
5668
5669                 Load mode update delay (DDR4 and DDR3 only)
5670                 PSU_DDR_PHY_DTPR1_TMOD                                                          0x7
5671
5672                 Reserved. Return zeroes on reads.
5673                 PSU_DDR_PHY_DTPR1_RESERVED_7_5                                                  0x0
5674
5675                 Load mode cycle time
5676                 PSU_DDR_PHY_DTPR1_TMRD                                                          0x8
5677
5678                 DRAM Timing Parameters Register 1
5679                 (OFFSET, MASK, VALUE)      (0XFD080114, 0xFFFFFFFFU ,0x28180708U)
5680                 RegMask = (DDR_PHY_DTPR1_RESERVED_31_MASK | DDR_PHY_DTPR1_TWLMRD_MASK | DDR_PHY_DTPR1_RESERVED_23_MASK | DDR_PHY_DTPR1_TFAW_MASK | DDR_PHY_DTPR1_RESERVED_15_11_MASK | DDR_PHY_DTPR1_TMOD_MASK | DDR_PHY_DTPR1_RESERVED_7_5_MASK | DDR_PHY_DTPR1_TMRD_MASK |  0 );
5681
5682                 RegVal = ((0x00000000U << DDR_PHY_DTPR1_RESERVED_31_SHIFT
5683                         | 0x00000028U << DDR_PHY_DTPR1_TWLMRD_SHIFT
5684                         | 0x00000000U << DDR_PHY_DTPR1_RESERVED_23_SHIFT
5685                         | 0x00000018U << DDR_PHY_DTPR1_TFAW_SHIFT
5686                         | 0x00000000U << DDR_PHY_DTPR1_RESERVED_15_11_SHIFT
5687                         | 0x00000007U << DDR_PHY_DTPR1_TMOD_SHIFT
5688                         | 0x00000000U << DDR_PHY_DTPR1_RESERVED_7_5_SHIFT
5689                         | 0x00000008U << DDR_PHY_DTPR1_TMRD_SHIFT
5690                         |  0 ) & RegMask); */
5691                 PSU_Mask_Write (DDR_PHY_DTPR1_OFFSET ,0xFFFFFFFFU ,0x28180708U);
5692         /*############################################################################################################################ */
5693
5694                 /*Register : DTPR2 @ 0XFD080118</p>
5695
5696                 Reserved. Return zeroes on reads.
5697                 PSU_DDR_PHY_DTPR2_RESERVED_31_29                                                0x0
5698
5699                 Read to Write command delay. Valid values are
5700                 PSU_DDR_PHY_DTPR2_TRTW                                                          0x0
5701
5702                 Reserved. Return zeroes on reads.
5703                 PSU_DDR_PHY_DTPR2_RESERVED_27_25                                                0x0
5704
5705                 Read to ODT delay (DDR3 only)
5706                 PSU_DDR_PHY_DTPR2_TRTODT                                                        0x0
5707
5708                 Reserved. Return zeroes on reads.
5709                 PSU_DDR_PHY_DTPR2_RESERVED_23_20                                                0x0
5710
5711                 CKE minimum pulse width
5712                 PSU_DDR_PHY_DTPR2_TCKE                                                          0x8
5713
5714                 Reserved. Return zeroes on reads.
5715                 PSU_DDR_PHY_DTPR2_RESERVED_15_10                                                0x0
5716
5717                 Self refresh exit delay
5718                 PSU_DDR_PHY_DTPR2_TXS                                                           0x200
5719
5720                 DRAM Timing Parameters Register 2
5721                 (OFFSET, MASK, VALUE)      (0XFD080118, 0xFFFFFFFFU ,0x00080200U)
5722                 RegMask = (DDR_PHY_DTPR2_RESERVED_31_29_MASK | DDR_PHY_DTPR2_TRTW_MASK | DDR_PHY_DTPR2_RESERVED_27_25_MASK | DDR_PHY_DTPR2_TRTODT_MASK | DDR_PHY_DTPR2_RESERVED_23_20_MASK | DDR_PHY_DTPR2_TCKE_MASK | DDR_PHY_DTPR2_RESERVED_15_10_MASK | DDR_PHY_DTPR2_TXS_MASK |  0 );
5723
5724                 RegVal = ((0x00000000U << DDR_PHY_DTPR2_RESERVED_31_29_SHIFT
5725                         | 0x00000000U << DDR_PHY_DTPR2_TRTW_SHIFT
5726                         | 0x00000000U << DDR_PHY_DTPR2_RESERVED_27_25_SHIFT
5727                         | 0x00000000U << DDR_PHY_DTPR2_TRTODT_SHIFT
5728                         | 0x00000000U << DDR_PHY_DTPR2_RESERVED_23_20_SHIFT
5729                         | 0x00000008U << DDR_PHY_DTPR2_TCKE_SHIFT
5730                         | 0x00000000U << DDR_PHY_DTPR2_RESERVED_15_10_SHIFT
5731                         | 0x00000200U << DDR_PHY_DTPR2_TXS_SHIFT
5732                         |  0 ) & RegMask); */
5733                 PSU_Mask_Write (DDR_PHY_DTPR2_OFFSET ,0xFFFFFFFFU ,0x00080200U);
5734         /*############################################################################################################################ */
5735
5736                 /*Register : DTPR3 @ 0XFD08011C</p>
5737
5738                 ODT turn-off delay extension
5739                 PSU_DDR_PHY_DTPR3_TOFDX                                                         0x4
5740
5741                 Read to read and write to write command delay
5742                 PSU_DDR_PHY_DTPR3_TCCD                                                          0x0
5743
5744                 DLL locking time
5745                 PSU_DDR_PHY_DTPR3_TDLLK                                                         0x300
5746
5747                 Reserved. Return zeroes on reads.
5748                 PSU_DDR_PHY_DTPR3_RESERVED_15_12                                                0x0
5749
5750                 Maximum DQS output access time from CK/CK# (LPDDR2/3 only)
5751                 PSU_DDR_PHY_DTPR3_TDQSCKMAX                                                     0x8
5752
5753                 Reserved. Return zeroes on reads.
5754                 PSU_DDR_PHY_DTPR3_RESERVED_7_3                                                  0x0
5755
5756                 DQS output access time from CK/CK# (LPDDR2/3 only)
5757                 PSU_DDR_PHY_DTPR3_TDQSCK                                                        0x0
5758
5759                 DRAM Timing Parameters Register 3
5760                 (OFFSET, MASK, VALUE)      (0XFD08011C, 0xFFFFFFFFU ,0x83000800U)
5761                 RegMask = (DDR_PHY_DTPR3_TOFDX_MASK | DDR_PHY_DTPR3_TCCD_MASK | DDR_PHY_DTPR3_TDLLK_MASK | DDR_PHY_DTPR3_RESERVED_15_12_MASK | DDR_PHY_DTPR3_TDQSCKMAX_MASK | DDR_PHY_DTPR3_RESERVED_7_3_MASK | DDR_PHY_DTPR3_TDQSCK_MASK |  0 );
5762
5763                 RegVal = ((0x00000004U << DDR_PHY_DTPR3_TOFDX_SHIFT
5764                         | 0x00000000U << DDR_PHY_DTPR3_TCCD_SHIFT
5765                         | 0x00000300U << DDR_PHY_DTPR3_TDLLK_SHIFT
5766                         | 0x00000000U << DDR_PHY_DTPR3_RESERVED_15_12_SHIFT
5767                         | 0x00000008U << DDR_PHY_DTPR3_TDQSCKMAX_SHIFT
5768                         | 0x00000000U << DDR_PHY_DTPR3_RESERVED_7_3_SHIFT
5769                         | 0x00000000U << DDR_PHY_DTPR3_TDQSCK_SHIFT
5770                         |  0 ) & RegMask); */
5771                 PSU_Mask_Write (DDR_PHY_DTPR3_OFFSET ,0xFFFFFFFFU ,0x83000800U);
5772         /*############################################################################################################################ */
5773
5774                 /*Register : DTPR4 @ 0XFD080120</p>
5775
5776                 Reserved. Return zeroes on reads.
5777                 PSU_DDR_PHY_DTPR4_RESERVED_31_30                                                0x0
5778
5779                 ODT turn-on/turn-off delays (DDR2 only)
5780                 PSU_DDR_PHY_DTPR4_TAOND_TAOFD                                                   0x0
5781
5782                 Reserved. Return zeroes on reads.
5783                 PSU_DDR_PHY_DTPR4_RESERVED_27_26                                                0x0
5784
5785                 Refresh-to-Refresh
5786                 PSU_DDR_PHY_DTPR4_TRFC                                                          0x116
5787
5788                 Reserved. Return zeroes on reads.
5789                 PSU_DDR_PHY_DTPR4_RESERVED_15_14                                                0x0
5790
5791                 Write leveling output delay
5792                 PSU_DDR_PHY_DTPR4_TWLO                                                          0x2b
5793
5794                 Reserved. Return zeroes on reads.
5795                 PSU_DDR_PHY_DTPR4_RESERVED_7_5                                                  0x0
5796
5797                 Power down exit delay
5798                 PSU_DDR_PHY_DTPR4_TXP                                                           0x8
5799
5800                 DRAM Timing Parameters Register 4
5801                 (OFFSET, MASK, VALUE)      (0XFD080120, 0xFFFFFFFFU ,0x01162B08U)
5802                 RegMask = (DDR_PHY_DTPR4_RESERVED_31_30_MASK | DDR_PHY_DTPR4_TAOND_TAOFD_MASK | DDR_PHY_DTPR4_RESERVED_27_26_MASK | DDR_PHY_DTPR4_TRFC_MASK | DDR_PHY_DTPR4_RESERVED_15_14_MASK | DDR_PHY_DTPR4_TWLO_MASK | DDR_PHY_DTPR4_RESERVED_7_5_MASK | DDR_PHY_DTPR4_TXP_MASK |  0 );
5803
5804                 RegVal = ((0x00000000U << DDR_PHY_DTPR4_RESERVED_31_30_SHIFT
5805                         | 0x00000000U << DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT
5806                         | 0x00000000U << DDR_PHY_DTPR4_RESERVED_27_26_SHIFT
5807                         | 0x00000116U << DDR_PHY_DTPR4_TRFC_SHIFT
5808                         | 0x00000000U << DDR_PHY_DTPR4_RESERVED_15_14_SHIFT
5809                         | 0x0000002BU << DDR_PHY_DTPR4_TWLO_SHIFT
5810                         | 0x00000000U << DDR_PHY_DTPR4_RESERVED_7_5_SHIFT
5811                         | 0x00000008U << DDR_PHY_DTPR4_TXP_SHIFT
5812                         |  0 ) & RegMask); */
5813                 PSU_Mask_Write (DDR_PHY_DTPR4_OFFSET ,0xFFFFFFFFU ,0x01162B08U);
5814         /*############################################################################################################################ */
5815
5816                 /*Register : DTPR5 @ 0XFD080124</p>
5817
5818                 Reserved. Return zeroes on reads.
5819                 PSU_DDR_PHY_DTPR5_RESERVED_31_24                                                0x0
5820
5821                 Activate to activate command delay (same bank)
5822                 PSU_DDR_PHY_DTPR5_TRC                                                           0x32
5823
5824                 Reserved. Return zeroes on reads.
5825                 PSU_DDR_PHY_DTPR5_RESERVED_15                                                   0x0
5826
5827                 Activate to read or write delay
5828                 PSU_DDR_PHY_DTPR5_TRCD                                                          0xf
5829
5830                 Reserved. Return zeroes on reads.
5831                 PSU_DDR_PHY_DTPR5_RESERVED_7_5                                                  0x0
5832
5833                 Internal write to read command delay
5834                 PSU_DDR_PHY_DTPR5_TWTR                                                          0x9
5835
5836                 DRAM Timing Parameters Register 5
5837                 (OFFSET, MASK, VALUE)      (0XFD080124, 0xFFFFFFFFU ,0x00320F09U)
5838                 RegMask = (DDR_PHY_DTPR5_RESERVED_31_24_MASK | DDR_PHY_DTPR5_TRC_MASK | DDR_PHY_DTPR5_RESERVED_15_MASK | DDR_PHY_DTPR5_TRCD_MASK | DDR_PHY_DTPR5_RESERVED_7_5_MASK | DDR_PHY_DTPR5_TWTR_MASK |  0 );
5839
5840                 RegVal = ((0x00000000U << DDR_PHY_DTPR5_RESERVED_31_24_SHIFT
5841                         | 0x00000032U << DDR_PHY_DTPR5_TRC_SHIFT
5842                         | 0x00000000U << DDR_PHY_DTPR5_RESERVED_15_SHIFT
5843                         | 0x0000000FU << DDR_PHY_DTPR5_TRCD_SHIFT
5844                         | 0x00000000U << DDR_PHY_DTPR5_RESERVED_7_5_SHIFT
5845                         | 0x00000009U << DDR_PHY_DTPR5_TWTR_SHIFT
5846                         |  0 ) & RegMask); */
5847                 PSU_Mask_Write (DDR_PHY_DTPR5_OFFSET ,0xFFFFFFFFU ,0x00320F09U);
5848         /*############################################################################################################################ */
5849
5850                 /*Register : DTPR6 @ 0XFD080128</p>
5851
5852                 PUB Write Latency Enable
5853                 PSU_DDR_PHY_DTPR6_PUBWLEN                                                       0x0
5854
5855                 PUB Read Latency Enable
5856                 PSU_DDR_PHY_DTPR6_PUBRLEN                                                       0x0
5857
5858                 Reserved. Return zeroes on reads.
5859                 PSU_DDR_PHY_DTPR6_RESERVED_29_14                                                0x0
5860
5861                 Write Latency
5862                 PSU_DDR_PHY_DTPR6_PUBWL                                                         0xe
5863
5864                 Reserved. Return zeroes on reads.
5865                 PSU_DDR_PHY_DTPR6_RESERVED_7_6                                                  0x0
5866
5867                 Read Latency
5868                 PSU_DDR_PHY_DTPR6_PUBRL                                                         0xf
5869
5870                 DRAM Timing Parameters Register 6
5871                 (OFFSET, MASK, VALUE)      (0XFD080128, 0xFFFFFFFFU ,0x00000E0FU)
5872                 RegMask = (DDR_PHY_DTPR6_PUBWLEN_MASK | DDR_PHY_DTPR6_PUBRLEN_MASK | DDR_PHY_DTPR6_RESERVED_29_14_MASK | DDR_PHY_DTPR6_PUBWL_MASK | DDR_PHY_DTPR6_RESERVED_7_6_MASK | DDR_PHY_DTPR6_PUBRL_MASK |  0 );
5873
5874                 RegVal = ((0x00000000U << DDR_PHY_DTPR6_PUBWLEN_SHIFT
5875                         | 0x00000000U << DDR_PHY_DTPR6_PUBRLEN_SHIFT
5876                         | 0x00000000U << DDR_PHY_DTPR6_RESERVED_29_14_SHIFT
5877                         | 0x0000000EU << DDR_PHY_DTPR6_PUBWL_SHIFT
5878                         | 0x00000000U << DDR_PHY_DTPR6_RESERVED_7_6_SHIFT
5879                         | 0x0000000FU << DDR_PHY_DTPR6_PUBRL_SHIFT
5880                         |  0 ) & RegMask); */
5881                 PSU_Mask_Write (DDR_PHY_DTPR6_OFFSET ,0xFFFFFFFFU ,0x00000E0FU);
5882         /*############################################################################################################################ */
5883
5884                 /*Register : RDIMMGCR0 @ 0XFD080140</p>
5885
5886                 Reserved. Return zeroes on reads.
5887                 PSU_DDR_PHY_RDIMMGCR0_RESERVED_31                                               0x0
5888
5889                 RDMIMM Quad CS Enable
5890                 PSU_DDR_PHY_RDIMMGCR0_QCSEN                                                     0x0
5891
5892                 Reserved. Return zeroes on reads.
5893                 PSU_DDR_PHY_RDIMMGCR0_RESERVED_29_28                                            0x0
5894
5895                 RDIMM Outputs I/O Mode
5896                 PSU_DDR_PHY_RDIMMGCR0_RDIMMIOM                                                  0x1
5897
5898                 Reserved. Return zeroes on reads.
5899                 PSU_DDR_PHY_RDIMMGCR0_RESERVED_26_24                                            0x0
5900
5901                 ERROUT# Output Enable
5902                 PSU_DDR_PHY_RDIMMGCR0_ERROUTOE                                                  0x0
5903
5904                 ERROUT# I/O Mode
5905                 PSU_DDR_PHY_RDIMMGCR0_ERROUTIOM                                                 0x1
5906
5907                 ERROUT# Power Down Receiver
5908                 PSU_DDR_PHY_RDIMMGCR0_ERROUTPDR                                                 0x0
5909
5910                 Reserved. Return zeroes on reads.
5911                 PSU_DDR_PHY_RDIMMGCR0_RESERVED_20                                               0x0
5912
5913                 ERROUT# On-Die Termination
5914                 PSU_DDR_PHY_RDIMMGCR0_ERROUTODT                                                 0x0
5915
5916                 Load Reduced DIMM
5917                 PSU_DDR_PHY_RDIMMGCR0_LRDIMM                                                    0x0
5918
5919                 PAR_IN I/O Mode
5920                 PSU_DDR_PHY_RDIMMGCR0_PARINIOM                                                  0x0
5921
5922                 Reserved. Return zeroes on reads.
5923                 PSU_DDR_PHY_RDIMMGCR0_RESERVED_16_8                                             0x0
5924
5925                 Reserved. Return zeroes on reads.
5926                 PSU_DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD                                             0x0
5927
5928                 Rank Mirror Enable.
5929                 PSU_DDR_PHY_RDIMMGCR0_RNKMRREN                                                  0x2
5930
5931                 Reserved. Return zeroes on reads.
5932                 PSU_DDR_PHY_RDIMMGCR0_RESERVED_3                                                0x0
5933
5934                 Stop on Parity Error
5935                 PSU_DDR_PHY_RDIMMGCR0_SOPERR                                                    0x0
5936
5937                 Parity Error No Registering
5938                 PSU_DDR_PHY_RDIMMGCR0_ERRNOREG                                                  0x0
5939
5940                 Registered DIMM
5941                 PSU_DDR_PHY_RDIMMGCR0_RDIMM                                                     0x0
5942
5943                 RDIMM General Configuration Register 0
5944                 (OFFSET, MASK, VALUE)      (0XFD080140, 0xFFFFFFFFU ,0x08400020U)
5945                 RegMask = (DDR_PHY_RDIMMGCR0_RESERVED_31_MASK | DDR_PHY_RDIMMGCR0_QCSEN_MASK | DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK | DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK | DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK | DDR_PHY_RDIMMGCR0_ERROUTOE_MASK | DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK | DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK | DDR_PHY_RDIMMGCR0_RESERVED_20_MASK | DDR_PHY_RDIMMGCR0_ERROUTODT_MASK | DDR_PHY_RDIMMGCR0_LRDIMM_MASK | DDR_PHY_RDIMMGCR0_PARINIOM_MASK | DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK | DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK | DDR_PHY_RDIMMGCR0_RNKMRREN_MASK | DDR_PHY_RDIMMGCR0_RESERVED_3_MASK | DDR_PHY_RDIMMGCR0_SOPERR_MASK | DDR_PHY_RDIMMGCR0_ERRNOREG_MASK | DDR_PHY_RDIMMGCR0_RDIMM_MASK |  0 );
5946
5947                 RegVal = ((0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT
5948                         | 0x00000000U << DDR_PHY_RDIMMGCR0_QCSEN_SHIFT
5949                         | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT
5950                         | 0x00000001U << DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT
5951                         | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT
5952                         | 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT
5953                         | 0x00000001U << DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT
5954                         | 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT
5955                         | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT
5956                         | 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT
5957                         | 0x00000000U << DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT
5958                         | 0x00000000U << DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT
5959                         | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT
5960                         | 0x00000000U << DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT
5961                         | 0x00000002U << DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT
5962                         | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT
5963                         | 0x00000000U << DDR_PHY_RDIMMGCR0_SOPERR_SHIFT
5964                         | 0x00000000U << DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT
5965                         | 0x00000000U << DDR_PHY_RDIMMGCR0_RDIMM_SHIFT
5966                         |  0 ) & RegMask); */
5967                 PSU_Mask_Write (DDR_PHY_RDIMMGCR0_OFFSET ,0xFFFFFFFFU ,0x08400020U);
5968         /*############################################################################################################################ */
5969
5970                 /*Register : RDIMMGCR1 @ 0XFD080144</p>
5971
5972                 Reserved. Return zeroes on reads.
5973                 PSU_DDR_PHY_RDIMMGCR1_RESERVED_31_29                                            0x0
5974
5975                 Address [17] B-side Inversion Disable
5976                 PSU_DDR_PHY_RDIMMGCR1_A17BID                                                    0x0
5977
5978                 Reserved. Return zeroes on reads.
5979                 PSU_DDR_PHY_RDIMMGCR1_RESERVED_27                                               0x0
5980
5981                 Command word to command word programming delay
5982                 PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L2                                                 0x0
5983
5984                 Reserved. Return zeroes on reads.
5985                 PSU_DDR_PHY_RDIMMGCR1_RESERVED_23                                               0x0
5986
5987                 Command word to command word programming delay
5988                 PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L                                                  0x0
5989
5990                 Reserved. Return zeroes on reads.
5991                 PSU_DDR_PHY_RDIMMGCR1_RESERVED_19                                               0x0
5992
5993                 Command word to command word programming delay
5994                 PSU_DDR_PHY_RDIMMGCR1_TBCMRD                                                    0x0
5995
5996                 Reserved. Return zeroes on reads.
5997                 PSU_DDR_PHY_RDIMMGCR1_RESERVED_15_14                                            0x0
5998
5999                 Stabilization time
6000                 PSU_DDR_PHY_RDIMMGCR1_TBCSTAB                                                   0xc80
6001
6002                 RDIMM General Configuration Register 1
6003                 (OFFSET, MASK, VALUE)      (0XFD080144, 0xFFFFFFFFU ,0x00000C80U)
6004                 RegMask = (DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK | DDR_PHY_RDIMMGCR1_A17BID_MASK | DDR_PHY_RDIMMGCR1_RESERVED_27_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK | DDR_PHY_RDIMMGCR1_RESERVED_23_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK | DDR_PHY_RDIMMGCR1_RESERVED_19_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_MASK | DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK | DDR_PHY_RDIMMGCR1_TBCSTAB_MASK |  0 );
6005
6006                 RegVal = ((0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT
6007                         | 0x00000000U << DDR_PHY_RDIMMGCR1_A17BID_SHIFT
6008                         | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT
6009                         | 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT
6010                         | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT
6011                         | 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT
6012                         | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT
6013                         | 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT
6014                         | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT
6015                         | 0x00000C80U << DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT
6016                         |  0 ) & RegMask); */
6017                 PSU_Mask_Write (DDR_PHY_RDIMMGCR1_OFFSET ,0xFFFFFFFFU ,0x00000C80U);
6018         /*############################################################################################################################ */
6019
6020                 /*Register : RDIMMCR0 @ 0XFD080150</p>
6021
6022                 DDR4/DDR3 Control Word 7
6023                 PSU_DDR_PHY_RDIMMCR0_RC7                                                        0x0
6024
6025                 DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved
6026                 PSU_DDR_PHY_RDIMMCR0_RC6                                                        0x0
6027
6028                 DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)
6029                 PSU_DDR_PHY_RDIMMCR0_RC5                                                        0x0
6030
6031                 DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 Control Word 4 (Control Signals Driver C
6032                 aracteristics Control Word)
6033                 PSU_DDR_PHY_RDIMMCR0_RC4                                                        0x0
6034
6035                 DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control Word 3 (Command/Address Signals Dr
6036                 ver Characteristrics Control Word)
6037                 PSU_DDR_PHY_RDIMMCR0_RC3                                                        0x0
6038
6039                 DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word)
6040                 PSU_DDR_PHY_RDIMMCR0_RC2                                                        0x0
6041
6042                 DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)
6043                 PSU_DDR_PHY_RDIMMCR0_RC1                                                        0x0
6044
6045                 DDR4/DDR3 Control Word 0 (Global Features Control Word)
6046                 PSU_DDR_PHY_RDIMMCR0_RC0                                                        0x0
6047
6048                 RDIMM Control Register 0
6049                 (OFFSET, MASK, VALUE)      (0XFD080150, 0xFFFFFFFFU ,0x00000000U)
6050                 RegMask = (DDR_PHY_RDIMMCR0_RC7_MASK | DDR_PHY_RDIMMCR0_RC6_MASK | DDR_PHY_RDIMMCR0_RC5_MASK | DDR_PHY_RDIMMCR0_RC4_MASK | DDR_PHY_RDIMMCR0_RC3_MASK | DDR_PHY_RDIMMCR0_RC2_MASK | DDR_PHY_RDIMMCR0_RC1_MASK | DDR_PHY_RDIMMCR0_RC0_MASK |  0 );
6051
6052                 RegVal = ((0x00000000U << DDR_PHY_RDIMMCR0_RC7_SHIFT
6053                         | 0x00000000U << DDR_PHY_RDIMMCR0_RC6_SHIFT
6054                         | 0x00000000U << DDR_PHY_RDIMMCR0_RC5_SHIFT
6055                         | 0x00000000U << DDR_PHY_RDIMMCR0_RC4_SHIFT
6056                         | 0x00000000U << DDR_PHY_RDIMMCR0_RC3_SHIFT
6057                         | 0x00000000U << DDR_PHY_RDIMMCR0_RC2_SHIFT
6058                         | 0x00000000U << DDR_PHY_RDIMMCR0_RC1_SHIFT
6059                         | 0x00000000U << DDR_PHY_RDIMMCR0_RC0_SHIFT
6060                         |  0 ) & RegMask); */
6061                 PSU_Mask_Write (DDR_PHY_RDIMMCR0_OFFSET ,0xFFFFFFFFU ,0x00000000U);
6062         /*############################################################################################################################ */
6063
6064                 /*Register : RDIMMCR1 @ 0XFD080154</p>
6065
6066                 Control Word 15
6067                 PSU_DDR_PHY_RDIMMCR1_RC15                                                       0x0
6068
6069                 DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved
6070                 PSU_DDR_PHY_RDIMMCR1_RC14                                                       0x0
6071
6072                 DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved
6073                 PSU_DDR_PHY_RDIMMCR1_RC13                                                       0x0
6074
6075                 DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved
6076                 PSU_DDR_PHY_RDIMMCR1_RC12                                                       0x0
6077
6078                 DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con
6079                 rol Word)
6080                 PSU_DDR_PHY_RDIMMCR1_RC11                                                       0x0
6081
6082                 DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)
6083                 PSU_DDR_PHY_RDIMMCR1_RC10                                                       0x2
6084
6085                 DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)
6086                 PSU_DDR_PHY_RDIMMCR1_RC9                                                        0x0
6087
6088                 DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting
6089                 Control Word)
6090                 PSU_DDR_PHY_RDIMMCR1_RC8                                                        0x0
6091
6092                 RDIMM Control Register 1
6093                 (OFFSET, MASK, VALUE)      (0XFD080154, 0xFFFFFFFFU ,0x00000200U)
6094                 RegMask = (DDR_PHY_RDIMMCR1_RC15_MASK | DDR_PHY_RDIMMCR1_RC14_MASK | DDR_PHY_RDIMMCR1_RC13_MASK | DDR_PHY_RDIMMCR1_RC12_MASK | DDR_PHY_RDIMMCR1_RC11_MASK | DDR_PHY_RDIMMCR1_RC10_MASK | DDR_PHY_RDIMMCR1_RC9_MASK | DDR_PHY_RDIMMCR1_RC8_MASK |  0 );
6095
6096                 RegVal = ((0x00000000U << DDR_PHY_RDIMMCR1_RC15_SHIFT
6097                         | 0x00000000U << DDR_PHY_RDIMMCR1_RC14_SHIFT
6098                         | 0x00000000U << DDR_PHY_RDIMMCR1_RC13_SHIFT
6099                         | 0x00000000U << DDR_PHY_RDIMMCR1_RC12_SHIFT
6100                         | 0x00000000U << DDR_PHY_RDIMMCR1_RC11_SHIFT
6101                         | 0x00000002U << DDR_PHY_RDIMMCR1_RC10_SHIFT
6102                         | 0x00000000U << DDR_PHY_RDIMMCR1_RC9_SHIFT
6103                         | 0x00000000U << DDR_PHY_RDIMMCR1_RC8_SHIFT
6104                         |  0 ) & RegMask); */
6105                 PSU_Mask_Write (DDR_PHY_RDIMMCR1_OFFSET ,0xFFFFFFFFU ,0x00000200U);
6106         /*############################################################################################################################ */
6107
6108                 /*Register : MR0 @ 0XFD080180</p>
6109
6110                 Reserved. Return zeroes on reads.
6111                 PSU_DDR_PHY_MR0_RESERVED_31_8                                                   0x8
6112
6113                 CA Terminating Rank
6114                 PSU_DDR_PHY_MR0_CATR                                                            0x0
6115
6116                 Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6117                 PSU_DDR_PHY_MR0_RSVD_6_5                                                        0x1
6118
6119                 Built-in Self-Test for RZQ
6120                 PSU_DDR_PHY_MR0_RZQI                                                            0x2
6121
6122                 Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6123                 PSU_DDR_PHY_MR0_RSVD_2_0                                                        0x0
6124
6125                 LPDDR4 Mode Register 0
6126                 (OFFSET, MASK, VALUE)      (0XFD080180, 0xFFFFFFFFU ,0x00000830U)
6127                 RegMask = (DDR_PHY_MR0_RESERVED_31_8_MASK | DDR_PHY_MR0_CATR_MASK | DDR_PHY_MR0_RSVD_6_5_MASK | DDR_PHY_MR0_RZQI_MASK | DDR_PHY_MR0_RSVD_2_0_MASK |  0 );
6128
6129                 RegVal = ((0x00000008U << DDR_PHY_MR0_RESERVED_31_8_SHIFT
6130                         | 0x00000000U << DDR_PHY_MR0_CATR_SHIFT
6131                         | 0x00000001U << DDR_PHY_MR0_RSVD_6_5_SHIFT
6132                         | 0x00000002U << DDR_PHY_MR0_RZQI_SHIFT
6133                         | 0x00000000U << DDR_PHY_MR0_RSVD_2_0_SHIFT
6134                         |  0 ) & RegMask); */
6135                 PSU_Mask_Write (DDR_PHY_MR0_OFFSET ,0xFFFFFFFFU ,0x00000830U);
6136         /*############################################################################################################################ */
6137
6138                 /*Register : MR1 @ 0XFD080184</p>
6139
6140                 Reserved. Return zeroes on reads.
6141                 PSU_DDR_PHY_MR1_RESERVED_31_8                                                   0x3
6142
6143                 Read Postamble Length
6144                 PSU_DDR_PHY_MR1_RDPST                                                           0x0
6145
6146                 Write-recovery for auto-precharge command
6147                 PSU_DDR_PHY_MR1_NWR                                                             0x0
6148
6149                 Read Preamble Length
6150                 PSU_DDR_PHY_MR1_RDPRE                                                           0x0
6151
6152                 Write Preamble Length
6153                 PSU_DDR_PHY_MR1_WRPRE                                                           0x0
6154
6155                 Burst Length
6156                 PSU_DDR_PHY_MR1_BL                                                              0x1
6157
6158                 LPDDR4 Mode Register 1
6159                 (OFFSET, MASK, VALUE)      (0XFD080184, 0xFFFFFFFFU ,0x00000301U)
6160                 RegMask = (DDR_PHY_MR1_RESERVED_31_8_MASK | DDR_PHY_MR1_RDPST_MASK | DDR_PHY_MR1_NWR_MASK | DDR_PHY_MR1_RDPRE_MASK | DDR_PHY_MR1_WRPRE_MASK | DDR_PHY_MR1_BL_MASK |  0 );
6161
6162                 RegVal = ((0x00000003U << DDR_PHY_MR1_RESERVED_31_8_SHIFT
6163                         | 0x00000000U << DDR_PHY_MR1_RDPST_SHIFT
6164                         | 0x00000000U << DDR_PHY_MR1_NWR_SHIFT
6165                         | 0x00000000U << DDR_PHY_MR1_RDPRE_SHIFT
6166                         | 0x00000000U << DDR_PHY_MR1_WRPRE_SHIFT
6167                         | 0x00000001U << DDR_PHY_MR1_BL_SHIFT
6168                         |  0 ) & RegMask); */
6169                 PSU_Mask_Write (DDR_PHY_MR1_OFFSET ,0xFFFFFFFFU ,0x00000301U);
6170         /*############################################################################################################################ */
6171
6172                 /*Register : MR2 @ 0XFD080188</p>
6173
6174                 Reserved. Return zeroes on reads.
6175                 PSU_DDR_PHY_MR2_RESERVED_31_8                                                   0x0
6176
6177                 Write Leveling
6178                 PSU_DDR_PHY_MR2_WRL                                                             0x0
6179
6180                 Write Latency Set
6181                 PSU_DDR_PHY_MR2_WLS                                                             0x0
6182
6183                 Write Latency
6184                 PSU_DDR_PHY_MR2_WL                                                              0x4
6185
6186                 Read Latency
6187                 PSU_DDR_PHY_MR2_RL                                                              0x0
6188
6189                 LPDDR4 Mode Register 2
6190                 (OFFSET, MASK, VALUE)      (0XFD080188, 0xFFFFFFFFU ,0x00000020U)
6191                 RegMask = (DDR_PHY_MR2_RESERVED_31_8_MASK | DDR_PHY_MR2_WRL_MASK | DDR_PHY_MR2_WLS_MASK | DDR_PHY_MR2_WL_MASK | DDR_PHY_MR2_RL_MASK |  0 );
6192
6193                 RegVal = ((0x00000000U << DDR_PHY_MR2_RESERVED_31_8_SHIFT
6194                         | 0x00000000U << DDR_PHY_MR2_WRL_SHIFT
6195                         | 0x00000000U << DDR_PHY_MR2_WLS_SHIFT
6196                         | 0x00000004U << DDR_PHY_MR2_WL_SHIFT
6197                         | 0x00000000U << DDR_PHY_MR2_RL_SHIFT
6198                         |  0 ) & RegMask); */
6199                 PSU_Mask_Write (DDR_PHY_MR2_OFFSET ,0xFFFFFFFFU ,0x00000020U);
6200         /*############################################################################################################################ */
6201
6202                 /*Register : MR3 @ 0XFD08018C</p>
6203
6204                 Reserved. Return zeroes on reads.
6205                 PSU_DDR_PHY_MR3_RESERVED_31_8                                                   0x2
6206
6207                 DBI-Write Enable
6208                 PSU_DDR_PHY_MR3_DBIWR                                                           0x0
6209
6210                 DBI-Read Enable
6211                 PSU_DDR_PHY_MR3_DBIRD                                                           0x0
6212
6213                 Pull-down Drive Strength
6214                 PSU_DDR_PHY_MR3_PDDS                                                            0x0
6215
6216                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6217                 PSU_DDR_PHY_MR3_RSVD                                                            0x0
6218
6219                 Write Postamble Length
6220                 PSU_DDR_PHY_MR3_WRPST                                                           0x0
6221
6222                 Pull-up Calibration Point
6223                 PSU_DDR_PHY_MR3_PUCAL                                                           0x0
6224
6225                 LPDDR4 Mode Register 3
6226                 (OFFSET, MASK, VALUE)      (0XFD08018C, 0xFFFFFFFFU ,0x00000200U)
6227                 RegMask = (DDR_PHY_MR3_RESERVED_31_8_MASK | DDR_PHY_MR3_DBIWR_MASK | DDR_PHY_MR3_DBIRD_MASK | DDR_PHY_MR3_PDDS_MASK | DDR_PHY_MR3_RSVD_MASK | DDR_PHY_MR3_WRPST_MASK | DDR_PHY_MR3_PUCAL_MASK |  0 );
6228
6229                 RegVal = ((0x00000002U << DDR_PHY_MR3_RESERVED_31_8_SHIFT
6230                         | 0x00000000U << DDR_PHY_MR3_DBIWR_SHIFT
6231                         | 0x00000000U << DDR_PHY_MR3_DBIRD_SHIFT
6232                         | 0x00000000U << DDR_PHY_MR3_PDDS_SHIFT
6233                         | 0x00000000U << DDR_PHY_MR3_RSVD_SHIFT
6234                         | 0x00000000U << DDR_PHY_MR3_WRPST_SHIFT
6235                         | 0x00000000U << DDR_PHY_MR3_PUCAL_SHIFT
6236                         |  0 ) & RegMask); */
6237                 PSU_Mask_Write (DDR_PHY_MR3_OFFSET ,0xFFFFFFFFU ,0x00000200U);
6238         /*############################################################################################################################ */
6239
6240                 /*Register : MR4 @ 0XFD080190</p>
6241
6242                 Reserved. Return zeroes on reads.
6243                 PSU_DDR_PHY_MR4_RESERVED_31_16                                                  0x0
6244
6245                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6246                 PSU_DDR_PHY_MR4_RSVD_15_13                                                      0x0
6247
6248                 Write Preamble
6249                 PSU_DDR_PHY_MR4_WRP                                                             0x0
6250
6251                 Read Preamble
6252                 PSU_DDR_PHY_MR4_RDP                                                             0x0
6253
6254                 Read Preamble Training Mode
6255                 PSU_DDR_PHY_MR4_RPTM                                                            0x0
6256
6257                 Self Refresh Abort
6258                 PSU_DDR_PHY_MR4_SRA                                                             0x0
6259
6260                 CS to Command Latency Mode
6261                 PSU_DDR_PHY_MR4_CS2CMDL                                                         0x0
6262
6263                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6264                 PSU_DDR_PHY_MR4_RSVD1                                                           0x0
6265
6266                 Internal VREF Monitor
6267                 PSU_DDR_PHY_MR4_IVM                                                             0x0
6268
6269                 Temperature Controlled Refresh Mode
6270                 PSU_DDR_PHY_MR4_TCRM                                                            0x0
6271
6272                 Temperature Controlled Refresh Range
6273                 PSU_DDR_PHY_MR4_TCRR                                                            0x0
6274
6275                 Maximum Power Down Mode
6276                 PSU_DDR_PHY_MR4_MPDM                                                            0x0
6277
6278                 This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0.
6279                 PSU_DDR_PHY_MR4_RSVD_0                                                          0x0
6280
6281                 DDR4 Mode Register 4
6282                 (OFFSET, MASK, VALUE)      (0XFD080190, 0xFFFFFFFFU ,0x00000000U)
6283                 RegMask = (DDR_PHY_MR4_RESERVED_31_16_MASK | DDR_PHY_MR4_RSVD_15_13_MASK | DDR_PHY_MR4_WRP_MASK | DDR_PHY_MR4_RDP_MASK | DDR_PHY_MR4_RPTM_MASK | DDR_PHY_MR4_SRA_MASK | DDR_PHY_MR4_CS2CMDL_MASK | DDR_PHY_MR4_RSVD1_MASK | DDR_PHY_MR4_IVM_MASK | DDR_PHY_MR4_TCRM_MASK | DDR_PHY_MR4_TCRR_MASK | DDR_PHY_MR4_MPDM_MASK | DDR_PHY_MR4_RSVD_0_MASK |  0 );
6284
6285                 RegVal = ((0x00000000U << DDR_PHY_MR4_RESERVED_31_16_SHIFT
6286                         | 0x00000000U << DDR_PHY_MR4_RSVD_15_13_SHIFT
6287                         | 0x00000000U << DDR_PHY_MR4_WRP_SHIFT
6288                         | 0x00000000U << DDR_PHY_MR4_RDP_SHIFT
6289                         | 0x00000000U << DDR_PHY_MR4_RPTM_SHIFT
6290                         | 0x00000000U << DDR_PHY_MR4_SRA_SHIFT
6291                         | 0x00000000U << DDR_PHY_MR4_CS2CMDL_SHIFT
6292                         | 0x00000000U << DDR_PHY_MR4_RSVD1_SHIFT
6293                         | 0x00000000U << DDR_PHY_MR4_IVM_SHIFT
6294                         | 0x00000000U << DDR_PHY_MR4_TCRM_SHIFT
6295                         | 0x00000000U << DDR_PHY_MR4_TCRR_SHIFT
6296                         | 0x00000000U << DDR_PHY_MR4_MPDM_SHIFT
6297                         | 0x00000000U << DDR_PHY_MR4_RSVD_0_SHIFT
6298                         |  0 ) & RegMask); */
6299                 PSU_Mask_Write (DDR_PHY_MR4_OFFSET ,0xFFFFFFFFU ,0x00000000U);
6300         /*############################################################################################################################ */
6301
6302                 /*Register : MR5 @ 0XFD080194</p>
6303
6304                 Reserved. Return zeroes on reads.
6305                 PSU_DDR_PHY_MR5_RESERVED_31_16                                                  0x0
6306
6307                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6308                 PSU_DDR_PHY_MR5_RSVD                                                            0x0
6309
6310                 Read DBI
6311                 PSU_DDR_PHY_MR5_RDBI                                                            0x0
6312
6313                 Write DBI
6314                 PSU_DDR_PHY_MR5_WDBI                                                            0x0
6315
6316                 Data Mask
6317                 PSU_DDR_PHY_MR5_DM                                                              0x1
6318
6319                 CA Parity Persistent Error
6320                 PSU_DDR_PHY_MR5_CAPPE                                                           0x1
6321
6322                 RTT_PARK
6323                 PSU_DDR_PHY_MR5_RTTPARK                                                         0x3
6324
6325                 ODT Input Buffer during Power Down mode
6326                 PSU_DDR_PHY_MR5_ODTIBPD                                                         0x0
6327
6328                 C/A Parity Error Status
6329                 PSU_DDR_PHY_MR5_CAPES                                                           0x0
6330
6331                 CRC Error Clear
6332                 PSU_DDR_PHY_MR5_CRCEC                                                           0x0
6333
6334                 C/A Parity Latency Mode
6335                 PSU_DDR_PHY_MR5_CAPM                                                            0x0
6336
6337                 DDR4 Mode Register 5
6338                 (OFFSET, MASK, VALUE)      (0XFD080194, 0xFFFFFFFFU ,0x000006C0U)
6339                 RegMask = (DDR_PHY_MR5_RESERVED_31_16_MASK | DDR_PHY_MR5_RSVD_MASK | DDR_PHY_MR5_RDBI_MASK | DDR_PHY_MR5_WDBI_MASK | DDR_PHY_MR5_DM_MASK | DDR_PHY_MR5_CAPPE_MASK | DDR_PHY_MR5_RTTPARK_MASK | DDR_PHY_MR5_ODTIBPD_MASK | DDR_PHY_MR5_CAPES_MASK | DDR_PHY_MR5_CRCEC_MASK | DDR_PHY_MR5_CAPM_MASK |  0 );
6340
6341                 RegVal = ((0x00000000U << DDR_PHY_MR5_RESERVED_31_16_SHIFT
6342                         | 0x00000000U << DDR_PHY_MR5_RSVD_SHIFT
6343                         | 0x00000000U << DDR_PHY_MR5_RDBI_SHIFT
6344                         | 0x00000000U << DDR_PHY_MR5_WDBI_SHIFT
6345                         | 0x00000001U << DDR_PHY_MR5_DM_SHIFT
6346                         | 0x00000001U << DDR_PHY_MR5_CAPPE_SHIFT
6347                         | 0x00000003U << DDR_PHY_MR5_RTTPARK_SHIFT
6348                         | 0x00000000U << DDR_PHY_MR5_ODTIBPD_SHIFT
6349                         | 0x00000000U << DDR_PHY_MR5_CAPES_SHIFT
6350                         | 0x00000000U << DDR_PHY_MR5_CRCEC_SHIFT
6351                         | 0x00000000U << DDR_PHY_MR5_CAPM_SHIFT
6352                         |  0 ) & RegMask); */
6353                 PSU_Mask_Write (DDR_PHY_MR5_OFFSET ,0xFFFFFFFFU ,0x000006C0U);
6354         /*############################################################################################################################ */
6355
6356                 /*Register : MR6 @ 0XFD080198</p>
6357
6358                 Reserved. Return zeroes on reads.
6359                 PSU_DDR_PHY_MR6_RESERVED_31_16                                                  0x0
6360
6361                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6362                 PSU_DDR_PHY_MR6_RSVD_15_13                                                      0x0
6363
6364                 CAS_n to CAS_n command delay for same bank group (tCCD_L)
6365                 PSU_DDR_PHY_MR6_TCCDL                                                           0x2
6366
6367                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6368                 PSU_DDR_PHY_MR6_RSVD_9_8                                                        0x0
6369
6370                 VrefDQ Training Enable
6371                 PSU_DDR_PHY_MR6_VDDQTEN                                                         0x0
6372
6373                 VrefDQ Training Range
6374                 PSU_DDR_PHY_MR6_VDQTRG                                                          0x0
6375
6376                 VrefDQ Training Values
6377                 PSU_DDR_PHY_MR6_VDQTVAL                                                         0x19
6378
6379                 DDR4 Mode Register 6
6380                 (OFFSET, MASK, VALUE)      (0XFD080198, 0xFFFFFFFFU ,0x00000819U)
6381                 RegMask = (DDR_PHY_MR6_RESERVED_31_16_MASK | DDR_PHY_MR6_RSVD_15_13_MASK | DDR_PHY_MR6_TCCDL_MASK | DDR_PHY_MR6_RSVD_9_8_MASK | DDR_PHY_MR6_VDDQTEN_MASK | DDR_PHY_MR6_VDQTRG_MASK | DDR_PHY_MR6_VDQTVAL_MASK |  0 );
6382
6383                 RegVal = ((0x00000000U << DDR_PHY_MR6_RESERVED_31_16_SHIFT
6384                         | 0x00000000U << DDR_PHY_MR6_RSVD_15_13_SHIFT
6385                         | 0x00000002U << DDR_PHY_MR6_TCCDL_SHIFT
6386                         | 0x00000000U << DDR_PHY_MR6_RSVD_9_8_SHIFT
6387                         | 0x00000000U << DDR_PHY_MR6_VDDQTEN_SHIFT
6388                         | 0x00000000U << DDR_PHY_MR6_VDQTRG_SHIFT
6389                         | 0x00000019U << DDR_PHY_MR6_VDQTVAL_SHIFT
6390                         |  0 ) & RegMask); */
6391                 PSU_Mask_Write (DDR_PHY_MR6_OFFSET ,0xFFFFFFFFU ,0x00000819U);
6392         /*############################################################################################################################ */
6393
6394                 /*Register : MR11 @ 0XFD0801AC</p>
6395
6396                 Reserved. Return zeroes on reads.
6397                 PSU_DDR_PHY_MR11_RESERVED_31_8                                                  0x0
6398
6399                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6400                 PSU_DDR_PHY_MR11_RSVD                                                           0x0
6401
6402                 Power Down Control
6403                 PSU_DDR_PHY_MR11_PDCTL                                                          0x0
6404
6405                 DQ Bus Receiver On-Die-Termination
6406                 PSU_DDR_PHY_MR11_DQODT                                                          0x0
6407
6408                 LPDDR4 Mode Register 11
6409                 (OFFSET, MASK, VALUE)      (0XFD0801AC, 0xFFFFFFFFU ,0x00000000U)
6410                 RegMask = (DDR_PHY_MR11_RESERVED_31_8_MASK | DDR_PHY_MR11_RSVD_MASK | DDR_PHY_MR11_PDCTL_MASK | DDR_PHY_MR11_DQODT_MASK |  0 );
6411
6412                 RegVal = ((0x00000000U << DDR_PHY_MR11_RESERVED_31_8_SHIFT
6413                         | 0x00000000U << DDR_PHY_MR11_RSVD_SHIFT
6414                         | 0x00000000U << DDR_PHY_MR11_PDCTL_SHIFT
6415                         | 0x00000000U << DDR_PHY_MR11_DQODT_SHIFT
6416                         |  0 ) & RegMask); */
6417                 PSU_Mask_Write (DDR_PHY_MR11_OFFSET ,0xFFFFFFFFU ,0x00000000U);
6418         /*############################################################################################################################ */
6419
6420                 /*Register : MR12 @ 0XFD0801B0</p>
6421
6422                 Reserved. Return zeroes on reads.
6423                 PSU_DDR_PHY_MR12_RESERVED_31_8                                                  0x0
6424
6425                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6426                 PSU_DDR_PHY_MR12_RSVD                                                           0x0
6427
6428                 VREF_CA Range Select.
6429                 PSU_DDR_PHY_MR12_VR_CA                                                          0x1
6430
6431                 Controls the VREF(ca) levels for Frequency-Set-Point[1:0].
6432                 PSU_DDR_PHY_MR12_VREF_CA                                                        0xd
6433
6434                 LPDDR4 Mode Register 12
6435                 (OFFSET, MASK, VALUE)      (0XFD0801B0, 0xFFFFFFFFU ,0x0000004DU)
6436                 RegMask = (DDR_PHY_MR12_RESERVED_31_8_MASK | DDR_PHY_MR12_RSVD_MASK | DDR_PHY_MR12_VR_CA_MASK | DDR_PHY_MR12_VREF_CA_MASK |  0 );
6437
6438                 RegVal = ((0x00000000U << DDR_PHY_MR12_RESERVED_31_8_SHIFT
6439                         | 0x00000000U << DDR_PHY_MR12_RSVD_SHIFT
6440                         | 0x00000001U << DDR_PHY_MR12_VR_CA_SHIFT
6441                         | 0x0000000DU << DDR_PHY_MR12_VREF_CA_SHIFT
6442                         |  0 ) & RegMask); */
6443                 PSU_Mask_Write (DDR_PHY_MR12_OFFSET ,0xFFFFFFFFU ,0x0000004DU);
6444         /*############################################################################################################################ */
6445
6446                 /*Register : MR13 @ 0XFD0801B4</p>
6447
6448                 Reserved. Return zeroes on reads.
6449                 PSU_DDR_PHY_MR13_RESERVED_31_8                                                  0x0
6450
6451                 Frequency Set Point Operation Mode
6452                 PSU_DDR_PHY_MR13_FSPOP                                                          0x0
6453
6454                 Frequency Set Point Write Enable
6455                 PSU_DDR_PHY_MR13_FSPWR                                                          0x0
6456
6457                 Data Mask Enable
6458                 PSU_DDR_PHY_MR13_DMD                                                            0x0
6459
6460                 Refresh Rate Option
6461                 PSU_DDR_PHY_MR13_RRO                                                            0x0
6462
6463                 VREF Current Generator
6464                 PSU_DDR_PHY_MR13_VRCG                                                           0x1
6465
6466                 VREF Output
6467                 PSU_DDR_PHY_MR13_VRO                                                            0x0
6468
6469                 Read Preamble Training Mode
6470                 PSU_DDR_PHY_MR13_RPT                                                            0x0
6471
6472                 Command Bus Training
6473                 PSU_DDR_PHY_MR13_CBT                                                            0x0
6474
6475                 LPDDR4 Mode Register 13
6476                 (OFFSET, MASK, VALUE)      (0XFD0801B4, 0xFFFFFFFFU ,0x00000008U)
6477                 RegMask = (DDR_PHY_MR13_RESERVED_31_8_MASK | DDR_PHY_MR13_FSPOP_MASK | DDR_PHY_MR13_FSPWR_MASK | DDR_PHY_MR13_DMD_MASK | DDR_PHY_MR13_RRO_MASK | DDR_PHY_MR13_VRCG_MASK | DDR_PHY_MR13_VRO_MASK | DDR_PHY_MR13_RPT_MASK | DDR_PHY_MR13_CBT_MASK |  0 );
6478
6479                 RegVal = ((0x00000000U << DDR_PHY_MR13_RESERVED_31_8_SHIFT
6480                         | 0x00000000U << DDR_PHY_MR13_FSPOP_SHIFT
6481                         | 0x00000000U << DDR_PHY_MR13_FSPWR_SHIFT
6482                         | 0x00000000U << DDR_PHY_MR13_DMD_SHIFT
6483                         | 0x00000000U << DDR_PHY_MR13_RRO_SHIFT
6484                         | 0x00000001U << DDR_PHY_MR13_VRCG_SHIFT
6485                         | 0x00000000U << DDR_PHY_MR13_VRO_SHIFT
6486                         | 0x00000000U << DDR_PHY_MR13_RPT_SHIFT
6487                         | 0x00000000U << DDR_PHY_MR13_CBT_SHIFT
6488                         |  0 ) & RegMask); */
6489                 PSU_Mask_Write (DDR_PHY_MR13_OFFSET ,0xFFFFFFFFU ,0x00000008U);
6490         /*############################################################################################################################ */
6491
6492                 /*Register : MR14 @ 0XFD0801B8</p>
6493
6494                 Reserved. Return zeroes on reads.
6495                 PSU_DDR_PHY_MR14_RESERVED_31_8                                                  0x0
6496
6497                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6498                 PSU_DDR_PHY_MR14_RSVD                                                           0x0
6499
6500                 VREFDQ Range Selects.
6501                 PSU_DDR_PHY_MR14_VR_DQ                                                          0x1
6502
6503                 Reserved. Return zeroes on reads.
6504                 PSU_DDR_PHY_MR14_VREF_DQ                                                        0xd
6505
6506                 LPDDR4 Mode Register 14
6507                 (OFFSET, MASK, VALUE)      (0XFD0801B8, 0xFFFFFFFFU ,0x0000004DU)
6508                 RegMask = (DDR_PHY_MR14_RESERVED_31_8_MASK | DDR_PHY_MR14_RSVD_MASK | DDR_PHY_MR14_VR_DQ_MASK | DDR_PHY_MR14_VREF_DQ_MASK |  0 );
6509
6510                 RegVal = ((0x00000000U << DDR_PHY_MR14_RESERVED_31_8_SHIFT
6511                         | 0x00000000U << DDR_PHY_MR14_RSVD_SHIFT
6512                         | 0x00000001U << DDR_PHY_MR14_VR_DQ_SHIFT
6513                         | 0x0000000DU << DDR_PHY_MR14_VREF_DQ_SHIFT
6514                         |  0 ) & RegMask); */
6515                 PSU_Mask_Write (DDR_PHY_MR14_OFFSET ,0xFFFFFFFFU ,0x0000004DU);
6516         /*############################################################################################################################ */
6517
6518                 /*Register : MR22 @ 0XFD0801D8</p>
6519
6520                 Reserved. Return zeroes on reads.
6521                 PSU_DDR_PHY_MR22_RESERVED_31_8                                                  0x0
6522
6523                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6524                 PSU_DDR_PHY_MR22_RSVD                                                           0x0
6525
6526                 CA ODT termination disable.
6527                 PSU_DDR_PHY_MR22_ODTD_CA                                                        0x0
6528
6529                 ODT CS override.
6530                 PSU_DDR_PHY_MR22_ODTE_CS                                                        0x0
6531
6532                 ODT CK override.
6533                 PSU_DDR_PHY_MR22_ODTE_CK                                                        0x0
6534
6535                 Controller ODT value for VOH calibration.
6536                 PSU_DDR_PHY_MR22_CODT                                                           0x0
6537
6538                 LPDDR4 Mode Register 22
6539                 (OFFSET, MASK, VALUE)      (0XFD0801D8, 0xFFFFFFFFU ,0x00000000U)
6540                 RegMask = (DDR_PHY_MR22_RESERVED_31_8_MASK | DDR_PHY_MR22_RSVD_MASK | DDR_PHY_MR22_ODTD_CA_MASK | DDR_PHY_MR22_ODTE_CS_MASK | DDR_PHY_MR22_ODTE_CK_MASK | DDR_PHY_MR22_CODT_MASK |  0 );
6541
6542                 RegVal = ((0x00000000U << DDR_PHY_MR22_RESERVED_31_8_SHIFT
6543                         | 0x00000000U << DDR_PHY_MR22_RSVD_SHIFT
6544                         | 0x00000000U << DDR_PHY_MR22_ODTD_CA_SHIFT
6545                         | 0x00000000U << DDR_PHY_MR22_ODTE_CS_SHIFT
6546                         | 0x00000000U << DDR_PHY_MR22_ODTE_CK_SHIFT
6547                         | 0x00000000U << DDR_PHY_MR22_CODT_SHIFT
6548                         |  0 ) & RegMask); */
6549                 PSU_Mask_Write (DDR_PHY_MR22_OFFSET ,0xFFFFFFFFU ,0x00000000U);
6550         /*############################################################################################################################ */
6551
6552                 /*Register : DTCR0 @ 0XFD080200</p>
6553
6554                 Refresh During Training
6555                 PSU_DDR_PHY_DTCR0_RFSHDT                                                        0x8
6556
6557                 Reserved. Return zeroes on reads.
6558                 PSU_DDR_PHY_DTCR0_RESERVED_27_26                                                0x0
6559
6560                 Data Training Debug Rank Select
6561                 PSU_DDR_PHY_DTCR0_DTDRS                                                         0x0
6562
6563                 Data Training with Early/Extended Gate
6564                 PSU_DDR_PHY_DTCR0_DTEXG                                                         0x0
6565
6566                 Data Training Extended Write DQS
6567                 PSU_DDR_PHY_DTCR0_DTEXD                                                         0x0
6568
6569                 Data Training Debug Step
6570                 PSU_DDR_PHY_DTCR0_DTDSTP                                                        0x0
6571
6572                 Data Training Debug Enable
6573                 PSU_DDR_PHY_DTCR0_DTDEN                                                         0x0
6574
6575                 Data Training Debug Byte Select
6576                 PSU_DDR_PHY_DTCR0_DTDBS                                                         0x0
6577
6578                 Data Training read DBI deskewing configuration
6579                 PSU_DDR_PHY_DTCR0_DTRDBITR                                                      0x2
6580
6581                 Reserved. Return zeroes on reads.
6582                 PSU_DDR_PHY_DTCR0_RESERVED_13                                                   0x0
6583
6584                 Data Training Write Bit Deskew Data Mask
6585                 PSU_DDR_PHY_DTCR0_DTWBDDM                                                       0x1
6586
6587                 Refreshes Issued During Entry to Training
6588                 PSU_DDR_PHY_DTCR0_RFSHEN                                                        0x1
6589
6590                 Data Training Compare Data
6591                 PSU_DDR_PHY_DTCR0_DTCMPD                                                        0x1
6592
6593                 Data Training Using MPR
6594                 PSU_DDR_PHY_DTCR0_DTMPR                                                         0x1
6595
6596                 Reserved. Return zeroes on reads.
6597                 PSU_DDR_PHY_DTCR0_RESERVED_5_4                                                  0x0
6598
6599                 Data Training Repeat Number
6600                 PSU_DDR_PHY_DTCR0_DTRPTN                                                        0x7
6601
6602                 Data Training Configuration Register 0
6603                 (OFFSET, MASK, VALUE)      (0XFD080200, 0xFFFFFFFFU ,0x800091C7U)
6604                 RegMask = (DDR_PHY_DTCR0_RFSHDT_MASK | DDR_PHY_DTCR0_RESERVED_27_26_MASK | DDR_PHY_DTCR0_DTDRS_MASK | DDR_PHY_DTCR0_DTEXG_MASK | DDR_PHY_DTCR0_DTEXD_MASK | DDR_PHY_DTCR0_DTDSTP_MASK | DDR_PHY_DTCR0_DTDEN_MASK | DDR_PHY_DTCR0_DTDBS_MASK | DDR_PHY_DTCR0_DTRDBITR_MASK | DDR_PHY_DTCR0_RESERVED_13_MASK | DDR_PHY_DTCR0_DTWBDDM_MASK | DDR_PHY_DTCR0_RFSHEN_MASK | DDR_PHY_DTCR0_DTCMPD_MASK | DDR_PHY_DTCR0_DTMPR_MASK | DDR_PHY_DTCR0_RESERVED_5_4_MASK | DDR_PHY_DTCR0_DTRPTN_MASK |  0 );
6605
6606                 RegVal = ((0x00000008U << DDR_PHY_DTCR0_RFSHDT_SHIFT
6607                         | 0x00000000U << DDR_PHY_DTCR0_RESERVED_27_26_SHIFT
6608                         | 0x00000000U << DDR_PHY_DTCR0_DTDRS_SHIFT
6609                         | 0x00000000U << DDR_PHY_DTCR0_DTEXG_SHIFT
6610                         | 0x00000000U << DDR_PHY_DTCR0_DTEXD_SHIFT
6611                         | 0x00000000U << DDR_PHY_DTCR0_DTDSTP_SHIFT
6612                         | 0x00000000U << DDR_PHY_DTCR0_DTDEN_SHIFT
6613                         | 0x00000000U << DDR_PHY_DTCR0_DTDBS_SHIFT
6614                         | 0x00000002U << DDR_PHY_DTCR0_DTRDBITR_SHIFT
6615                         | 0x00000000U << DDR_PHY_DTCR0_RESERVED_13_SHIFT
6616                         | 0x00000001U << DDR_PHY_DTCR0_DTWBDDM_SHIFT
6617                         | 0x00000001U << DDR_PHY_DTCR0_RFSHEN_SHIFT
6618                         | 0x00000001U << DDR_PHY_DTCR0_DTCMPD_SHIFT
6619                         | 0x00000001U << DDR_PHY_DTCR0_DTMPR_SHIFT
6620                         | 0x00000000U << DDR_PHY_DTCR0_RESERVED_5_4_SHIFT
6621                         | 0x00000007U << DDR_PHY_DTCR0_DTRPTN_SHIFT
6622                         |  0 ) & RegMask); */
6623                 PSU_Mask_Write (DDR_PHY_DTCR0_OFFSET ,0xFFFFFFFFU ,0x800091C7U);
6624         /*############################################################################################################################ */
6625
6626                 /*Register : DTCR1 @ 0XFD080204</p>
6627
6628                 Rank Enable.
6629                 PSU_DDR_PHY_DTCR1_RANKEN_RSVD                                                   0x0
6630
6631                 Rank Enable.
6632                 PSU_DDR_PHY_DTCR1_RANKEN                                                        0x1
6633
6634                 Reserved. Return zeroes on reads.
6635                 PSU_DDR_PHY_DTCR1_RESERVED_15_14                                                0x0
6636
6637                 Data Training Rank
6638                 PSU_DDR_PHY_DTCR1_DTRANK                                                        0x0
6639
6640                 Reserved. Return zeroes on reads.
6641                 PSU_DDR_PHY_DTCR1_RESERVED_11                                                   0x0
6642
6643                 Read Leveling Gate Sampling Difference
6644                 PSU_DDR_PHY_DTCR1_RDLVLGDIFF                                                    0x2
6645
6646                 Reserved. Return zeroes on reads.
6647                 PSU_DDR_PHY_DTCR1_RESERVED_7                                                    0x0
6648
6649                 Read Leveling Gate Shift
6650                 PSU_DDR_PHY_DTCR1_RDLVLGS                                                       0x3
6651
6652                 Reserved. Return zeroes on reads.
6653                 PSU_DDR_PHY_DTCR1_RESERVED_3                                                    0x0
6654
6655                 Read Preamble Training enable
6656                 PSU_DDR_PHY_DTCR1_RDPRMVL_TRN                                                   0x1
6657
6658                 Read Leveling Enable
6659                 PSU_DDR_PHY_DTCR1_RDLVLEN                                                       0x1
6660
6661                 Basic Gate Training Enable
6662                 PSU_DDR_PHY_DTCR1_BSTEN                                                         0x0
6663
6664                 Data Training Configuration Register 1
6665                 (OFFSET, MASK, VALUE)      (0XFD080204, 0xFFFFFFFFU ,0x00010236U)
6666                 RegMask = (DDR_PHY_DTCR1_RANKEN_RSVD_MASK | DDR_PHY_DTCR1_RANKEN_MASK | DDR_PHY_DTCR1_RESERVED_15_14_MASK | DDR_PHY_DTCR1_DTRANK_MASK | DDR_PHY_DTCR1_RESERVED_11_MASK | DDR_PHY_DTCR1_RDLVLGDIFF_MASK | DDR_PHY_DTCR1_RESERVED_7_MASK | DDR_PHY_DTCR1_RDLVLGS_MASK | DDR_PHY_DTCR1_RESERVED_3_MASK | DDR_PHY_DTCR1_RDPRMVL_TRN_MASK | DDR_PHY_DTCR1_RDLVLEN_MASK | DDR_PHY_DTCR1_BSTEN_MASK |  0 );
6667
6668                 RegVal = ((0x00000000U << DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT
6669                         | 0x00000001U << DDR_PHY_DTCR1_RANKEN_SHIFT
6670                         | 0x00000000U << DDR_PHY_DTCR1_RESERVED_15_14_SHIFT
6671                         | 0x00000000U << DDR_PHY_DTCR1_DTRANK_SHIFT
6672                         | 0x00000000U << DDR_PHY_DTCR1_RESERVED_11_SHIFT
6673                         | 0x00000002U << DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT
6674                         | 0x00000000U << DDR_PHY_DTCR1_RESERVED_7_SHIFT
6675                         | 0x00000003U << DDR_PHY_DTCR1_RDLVLGS_SHIFT
6676                         | 0x00000000U << DDR_PHY_DTCR1_RESERVED_3_SHIFT
6677                         | 0x00000001U << DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT
6678                         | 0x00000001U << DDR_PHY_DTCR1_RDLVLEN_SHIFT
6679                         | 0x00000000U << DDR_PHY_DTCR1_BSTEN_SHIFT
6680                         |  0 ) & RegMask); */
6681                 PSU_Mask_Write (DDR_PHY_DTCR1_OFFSET ,0xFFFFFFFFU ,0x00010236U);
6682         /*############################################################################################################################ */
6683
6684                 /*Register : CATR0 @ 0XFD080240</p>
6685
6686                 Reserved. Return zeroes on reads.
6687                 PSU_DDR_PHY_CATR0_RESERVED_31_21                                                0x0
6688
6689                 Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command
6690                 PSU_DDR_PHY_CATR0_CACD                                                          0x14
6691
6692                 Reserved. Return zeroes on reads.
6693                 PSU_DDR_PHY_CATR0_RESERVED_15_13                                                0x0
6694
6695                 Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha
6696                  been sent to the memory
6697                 PSU_DDR_PHY_CATR0_CAADR                                                         0x10
6698
6699                 CA_1 Response Byte Lane 1
6700                 PSU_DDR_PHY_CATR0_CA1BYTE1                                                      0x5
6701
6702                 CA_1 Response Byte Lane 0
6703                 PSU_DDR_PHY_CATR0_CA1BYTE0                                                      0x4
6704
6705                 CA Training Register 0
6706                 (OFFSET, MASK, VALUE)      (0XFD080240, 0xFFFFFFFFU ,0x00141054U)
6707                 RegMask = (DDR_PHY_CATR0_RESERVED_31_21_MASK | DDR_PHY_CATR0_CACD_MASK | DDR_PHY_CATR0_RESERVED_15_13_MASK | DDR_PHY_CATR0_CAADR_MASK | DDR_PHY_CATR0_CA1BYTE1_MASK | DDR_PHY_CATR0_CA1BYTE0_MASK |  0 );
6708
6709                 RegVal = ((0x00000000U << DDR_PHY_CATR0_RESERVED_31_21_SHIFT
6710                         | 0x00000014U << DDR_PHY_CATR0_CACD_SHIFT
6711                         | 0x00000000U << DDR_PHY_CATR0_RESERVED_15_13_SHIFT
6712                         | 0x00000010U << DDR_PHY_CATR0_CAADR_SHIFT
6713                         | 0x00000005U << DDR_PHY_CATR0_CA1BYTE1_SHIFT
6714                         | 0x00000004U << DDR_PHY_CATR0_CA1BYTE0_SHIFT
6715                         |  0 ) & RegMask); */
6716                 PSU_Mask_Write (DDR_PHY_CATR0_OFFSET ,0xFFFFFFFFU ,0x00141054U);
6717         /*############################################################################################################################ */
6718
6719                 /*Register : BISTLSR @ 0XFD080414</p>
6720
6721                 LFSR seed for pseudo-random BIST patterns
6722                 PSU_DDR_PHY_BISTLSR_SEED                                                        0x12341000
6723
6724                 BIST LFSR Seed Register
6725                 (OFFSET, MASK, VALUE)      (0XFD080414, 0xFFFFFFFFU ,0x12341000U)
6726                 RegMask = (DDR_PHY_BISTLSR_SEED_MASK |  0 );
6727
6728                 RegVal = ((0x12341000U << DDR_PHY_BISTLSR_SEED_SHIFT
6729                         |  0 ) & RegMask); */
6730                 PSU_Mask_Write (DDR_PHY_BISTLSR_OFFSET ,0xFFFFFFFFU ,0x12341000U);
6731         /*############################################################################################################################ */
6732
6733                 /*Register : RIOCR5 @ 0XFD0804F4</p>
6734
6735                 Reserved. Return zeroes on reads.
6736                 PSU_DDR_PHY_RIOCR5_RESERVED_31_16                                               0x0
6737
6738                 Reserved. Return zeros on reads.
6739                 PSU_DDR_PHY_RIOCR5_ODTOEMODE_RSVD                                               0x0
6740
6741                 SDRAM On-die Termination Output Enable (OE) Mode Selection.
6742                 PSU_DDR_PHY_RIOCR5_ODTOEMODE                                                    0x5
6743
6744                 Rank I/O Configuration Register 5
6745                 (OFFSET, MASK, VALUE)      (0XFD0804F4, 0xFFFFFFFFU ,0x00000005U)
6746                 RegMask = (DDR_PHY_RIOCR5_RESERVED_31_16_MASK | DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK | DDR_PHY_RIOCR5_ODTOEMODE_MASK |  0 );
6747
6748                 RegVal = ((0x00000000U << DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT
6749                         | 0x00000000U << DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT
6750                         | 0x00000005U << DDR_PHY_RIOCR5_ODTOEMODE_SHIFT
6751                         |  0 ) & RegMask); */
6752                 PSU_Mask_Write (DDR_PHY_RIOCR5_OFFSET ,0xFFFFFFFFU ,0x00000005U);
6753         /*############################################################################################################################ */
6754
6755                 /*Register : ACIOCR0 @ 0XFD080500</p>
6756
6757                 Address/Command Slew Rate (D3F I/O Only)
6758                 PSU_DDR_PHY_ACIOCR0_ACSR                                                        0x0
6759
6760                 SDRAM Reset I/O Mode
6761                 PSU_DDR_PHY_ACIOCR0_RSTIOM                                                      0x1
6762
6763                 SDRAM Reset Power Down Receiver
6764                 PSU_DDR_PHY_ACIOCR0_RSTPDR                                                      0x1
6765
6766                 Reserved. Return zeroes on reads.
6767                 PSU_DDR_PHY_ACIOCR0_RESERVED_27                                                 0x0
6768
6769                 SDRAM Reset On-Die Termination
6770                 PSU_DDR_PHY_ACIOCR0_RSTODT                                                      0x0
6771
6772                 Reserved. Return zeroes on reads.
6773                 PSU_DDR_PHY_ACIOCR0_RESERVED_25_10                                              0x0
6774
6775                 CK Duty Cycle Correction
6776                 PSU_DDR_PHY_ACIOCR0_CKDCC                                                       0x0
6777
6778                 AC Power Down Receiver Mode
6779                 PSU_DDR_PHY_ACIOCR0_ACPDRMODE                                                   0x2
6780
6781                 AC On-die Termination Mode
6782                 PSU_DDR_PHY_ACIOCR0_ACODTMODE                                                   0x2
6783
6784                 Reserved. Return zeroes on reads.
6785                 PSU_DDR_PHY_ACIOCR0_RESERVED_1                                                  0x0
6786
6787                 Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.
6788                 PSU_DDR_PHY_ACIOCR0_ACRANKCLKSEL                                                0x0
6789
6790                 AC I/O Configuration Register 0
6791                 (OFFSET, MASK, VALUE)      (0XFD080500, 0xFFFFFFFFU ,0x30000028U)
6792                 RegMask = (DDR_PHY_ACIOCR0_ACSR_MASK | DDR_PHY_ACIOCR0_RSTIOM_MASK | DDR_PHY_ACIOCR0_RSTPDR_MASK | DDR_PHY_ACIOCR0_RESERVED_27_MASK | DDR_PHY_ACIOCR0_RSTODT_MASK | DDR_PHY_ACIOCR0_RESERVED_25_10_MASK | DDR_PHY_ACIOCR0_CKDCC_MASK | DDR_PHY_ACIOCR0_ACPDRMODE_MASK | DDR_PHY_ACIOCR0_ACODTMODE_MASK | DDR_PHY_ACIOCR0_RESERVED_1_MASK | DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK |  0 );
6793
6794                 RegVal = ((0x00000000U << DDR_PHY_ACIOCR0_ACSR_SHIFT
6795                         | 0x00000001U << DDR_PHY_ACIOCR0_RSTIOM_SHIFT
6796                         | 0x00000001U << DDR_PHY_ACIOCR0_RSTPDR_SHIFT
6797                         | 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_27_SHIFT
6798                         | 0x00000000U << DDR_PHY_ACIOCR0_RSTODT_SHIFT
6799                         | 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT
6800                         | 0x00000000U << DDR_PHY_ACIOCR0_CKDCC_SHIFT
6801                         | 0x00000002U << DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT
6802                         | 0x00000002U << DDR_PHY_ACIOCR0_ACODTMODE_SHIFT
6803                         | 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_1_SHIFT
6804                         | 0x00000000U << DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT
6805                         |  0 ) & RegMask); */
6806                 PSU_Mask_Write (DDR_PHY_ACIOCR0_OFFSET ,0xFFFFFFFFU ,0x30000028U);
6807         /*############################################################################################################################ */
6808
6809                 /*Register : ACIOCR2 @ 0XFD080508</p>
6810
6811                 Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice
6812                 PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE                                               0x0
6813
6814                 Clock gating for Output Enable D slices [0]
6815                 PSU_DDR_PHY_ACIOCR2_ACOECLKGATE0                                                0x0
6816
6817                 Clock gating for Power Down Receiver D slices [0]
6818                 PSU_DDR_PHY_ACIOCR2_ACPDRCLKGATE0                                               0x0
6819
6820                 Clock gating for Termination Enable D slices [0]
6821                 PSU_DDR_PHY_ACIOCR2_ACTECLKGATE0                                                0x0
6822
6823                 Clock gating for CK# D slices [1:0]
6824                 PSU_DDR_PHY_ACIOCR2_CKNCLKGATE0                                                 0x2
6825
6826                 Clock gating for CK D slices [1:0]
6827                 PSU_DDR_PHY_ACIOCR2_CKCLKGATE0                                                  0x2
6828
6829                 Clock gating for AC D slices [23:0]
6830                 PSU_DDR_PHY_ACIOCR2_ACCLKGATE0                                                  0x0
6831
6832                 AC I/O Configuration Register 2
6833                 (OFFSET, MASK, VALUE)      (0XFD080508, 0xFFFFFFFFU ,0x0A000000U)
6834                 RegMask = (DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK | DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK | DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK | DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK | DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK | DDR_PHY_ACIOCR2_CKCLKGATE0_MASK | DDR_PHY_ACIOCR2_ACCLKGATE0_MASK |  0 );
6835
6836                 RegVal = ((0x00000000U << DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT
6837                         | 0x00000000U << DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT
6838                         | 0x00000000U << DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT
6839                         | 0x00000000U << DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT
6840                         | 0x00000002U << DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT
6841                         | 0x00000002U << DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT
6842                         | 0x00000000U << DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT
6843                         |  0 ) & RegMask); */
6844                 PSU_Mask_Write (DDR_PHY_ACIOCR2_OFFSET ,0xFFFFFFFFU ,0x0A000000U);
6845         /*############################################################################################################################ */
6846
6847                 /*Register : ACIOCR3 @ 0XFD08050C</p>
6848
6849                 SDRAM Parity Output Enable (OE) Mode Selection
6850                 PSU_DDR_PHY_ACIOCR3_PAROEMODE                                                   0x0
6851
6852                 SDRAM Bank Group Output Enable (OE) Mode Selection
6853                 PSU_DDR_PHY_ACIOCR3_BGOEMODE                                                    0x0
6854
6855                 SDRAM Bank Address Output Enable (OE) Mode Selection
6856                 PSU_DDR_PHY_ACIOCR3_BAOEMODE                                                    0x0
6857
6858                 SDRAM A[17] Output Enable (OE) Mode Selection
6859                 PSU_DDR_PHY_ACIOCR3_A17OEMODE                                                   0x0
6860
6861                 SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection
6862                 PSU_DDR_PHY_ACIOCR3_A16OEMODE                                                   0x0
6863
6864                 SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)
6865                 PSU_DDR_PHY_ACIOCR3_ACTOEMODE                                                   0x0
6866
6867                 Reserved. Return zeroes on reads.
6868                 PSU_DDR_PHY_ACIOCR3_RESERVED_15_8                                               0x0
6869
6870                 Reserved. Return zeros on reads.
6871                 PSU_DDR_PHY_ACIOCR3_CKOEMODE_RSVD                                               0x0
6872
6873                 SDRAM CK Output Enable (OE) Mode Selection.
6874                 PSU_DDR_PHY_ACIOCR3_CKOEMODE                                                    0x9
6875
6876                 AC I/O Configuration Register 3
6877                 (OFFSET, MASK, VALUE)      (0XFD08050C, 0xFFFFFFFFU ,0x00000009U)
6878                 RegMask = (DDR_PHY_ACIOCR3_PAROEMODE_MASK | DDR_PHY_ACIOCR3_BGOEMODE_MASK | DDR_PHY_ACIOCR3_BAOEMODE_MASK | DDR_PHY_ACIOCR3_A17OEMODE_MASK | DDR_PHY_ACIOCR3_A16OEMODE_MASK | DDR_PHY_ACIOCR3_ACTOEMODE_MASK | DDR_PHY_ACIOCR3_RESERVED_15_8_MASK | DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK | DDR_PHY_ACIOCR3_CKOEMODE_MASK |  0 );
6879
6880                 RegVal = ((0x00000000U << DDR_PHY_ACIOCR3_PAROEMODE_SHIFT
6881                         | 0x00000000U << DDR_PHY_ACIOCR3_BGOEMODE_SHIFT
6882                         | 0x00000000U << DDR_PHY_ACIOCR3_BAOEMODE_SHIFT
6883                         | 0x00000000U << DDR_PHY_ACIOCR3_A17OEMODE_SHIFT
6884                         | 0x00000000U << DDR_PHY_ACIOCR3_A16OEMODE_SHIFT
6885                         | 0x00000000U << DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT
6886                         | 0x00000000U << DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT
6887                         | 0x00000000U << DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT
6888                         | 0x00000009U << DDR_PHY_ACIOCR3_CKOEMODE_SHIFT
6889                         |  0 ) & RegMask); */
6890                 PSU_Mask_Write (DDR_PHY_ACIOCR3_OFFSET ,0xFFFFFFFFU ,0x00000009U);
6891         /*############################################################################################################################ */
6892
6893                 /*Register : ACIOCR4 @ 0XFD080510</p>
6894
6895                 Clock gating for AC LB slices and loopback read valid slices
6896                 PSU_DDR_PHY_ACIOCR4_LBCLKGATE                                                   0x0
6897
6898                 Clock gating for Output Enable D slices [1]
6899                 PSU_DDR_PHY_ACIOCR4_ACOECLKGATE1                                                0x0
6900
6901                 Clock gating for Power Down Receiver D slices [1]
6902                 PSU_DDR_PHY_ACIOCR4_ACPDRCLKGATE1                                               0x0
6903
6904                 Clock gating for Termination Enable D slices [1]
6905                 PSU_DDR_PHY_ACIOCR4_ACTECLKGATE1                                                0x0
6906
6907                 Clock gating for CK# D slices [3:2]
6908                 PSU_DDR_PHY_ACIOCR4_CKNCLKGATE1                                                 0x2
6909
6910                 Clock gating for CK D slices [3:2]
6911                 PSU_DDR_PHY_ACIOCR4_CKCLKGATE1                                                  0x2
6912
6913                 Clock gating for AC D slices [47:24]
6914                 PSU_DDR_PHY_ACIOCR4_ACCLKGATE1                                                  0x0
6915
6916                 AC I/O Configuration Register 4
6917                 (OFFSET, MASK, VALUE)      (0XFD080510, 0xFFFFFFFFU ,0x0A000000U)
6918                 RegMask = (DDR_PHY_ACIOCR4_LBCLKGATE_MASK | DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK | DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK | DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK | DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK | DDR_PHY_ACIOCR4_CKCLKGATE1_MASK | DDR_PHY_ACIOCR4_ACCLKGATE1_MASK |  0 );
6919
6920                 RegVal = ((0x00000000U << DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT
6921                         | 0x00000000U << DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT
6922                         | 0x00000000U << DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT
6923                         | 0x00000000U << DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT
6924                         | 0x00000002U << DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT
6925                         | 0x00000002U << DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT
6926                         | 0x00000000U << DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT
6927                         |  0 ) & RegMask); */
6928                 PSU_Mask_Write (DDR_PHY_ACIOCR4_OFFSET ,0xFFFFFFFFU ,0x0A000000U);
6929         /*############################################################################################################################ */
6930
6931                 /*Register : IOVCR0 @ 0XFD080520</p>
6932
6933                 Reserved. Return zeroes on reads.
6934                 PSU_DDR_PHY_IOVCR0_RESERVED_31_29                                               0x0
6935
6936                 Address/command lane VREF Pad Enable
6937                 PSU_DDR_PHY_IOVCR0_ACREFPEN                                                     0x0
6938
6939                 Address/command lane Internal VREF Enable
6940                 PSU_DDR_PHY_IOVCR0_ACREFEEN                                                     0x0
6941
6942                 Address/command lane Single-End VREF Enable
6943                 PSU_DDR_PHY_IOVCR0_ACREFSEN                                                     0x1
6944
6945                 Address/command lane Internal VREF Enable
6946                 PSU_DDR_PHY_IOVCR0_ACREFIEN                                                     0x1
6947
6948                 External VREF generato REFSEL range select
6949                 PSU_DDR_PHY_IOVCR0_ACREFESELRANGE                                               0x0
6950
6951                 Address/command lane External VREF Select
6952                 PSU_DDR_PHY_IOVCR0_ACREFESEL                                                    0x0
6953
6954                 Single ended VREF generator REFSEL range select
6955                 PSU_DDR_PHY_IOVCR0_ACREFSSELRANGE                                               0x1
6956
6957                 Address/command lane Single-End VREF Select
6958                 PSU_DDR_PHY_IOVCR0_ACREFSSEL                                                    0x30
6959
6960                 Internal VREF generator REFSEL ragne select
6961                 PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE                                              0x1
6962
6963                 REFSEL Control for internal AC IOs
6964                 PSU_DDR_PHY_IOVCR0_ACVREFISEL                                                   0x30
6965
6966                 IO VREF Control Register 0
6967                 (OFFSET, MASK, VALUE)      (0XFD080520, 0xFFFFFFFFU ,0x0300B0B0U)
6968                 RegMask = (DDR_PHY_IOVCR0_RESERVED_31_29_MASK | DDR_PHY_IOVCR0_ACREFPEN_MASK | DDR_PHY_IOVCR0_ACREFEEN_MASK | DDR_PHY_IOVCR0_ACREFSEN_MASK | DDR_PHY_IOVCR0_ACREFIEN_MASK | DDR_PHY_IOVCR0_ACREFESELRANGE_MASK | DDR_PHY_IOVCR0_ACREFESEL_MASK | DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK | DDR_PHY_IOVCR0_ACREFSSEL_MASK | DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK | DDR_PHY_IOVCR0_ACVREFISEL_MASK |  0 );
6969
6970                 RegVal = ((0x00000000U << DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT
6971                         | 0x00000000U << DDR_PHY_IOVCR0_ACREFPEN_SHIFT
6972                         | 0x00000000U << DDR_PHY_IOVCR0_ACREFEEN_SHIFT
6973                         | 0x00000001U << DDR_PHY_IOVCR0_ACREFSEN_SHIFT
6974                         | 0x00000001U << DDR_PHY_IOVCR0_ACREFIEN_SHIFT
6975                         | 0x00000000U << DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT
6976                         | 0x00000000U << DDR_PHY_IOVCR0_ACREFESEL_SHIFT
6977                         | 0x00000001U << DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT
6978                         | 0x00000030U << DDR_PHY_IOVCR0_ACREFSSEL_SHIFT
6979                         | 0x00000001U << DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT
6980                         | 0x00000030U << DDR_PHY_IOVCR0_ACVREFISEL_SHIFT
6981                         |  0 ) & RegMask); */
6982                 PSU_Mask_Write (DDR_PHY_IOVCR0_OFFSET ,0xFFFFFFFFU ,0x0300B0B0U);
6983         /*############################################################################################################################ */
6984
6985                 /*Register : VTCR0 @ 0XFD080528</p>
6986
6987                 Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training
6988                 PSU_DDR_PHY_VTCR0_TVREF                                                         0x7
6989
6990                 DRM DQ VREF training Enable
6991                 PSU_DDR_PHY_VTCR0_DVEN                                                          0x1
6992
6993                 Per Device Addressability Enable
6994                 PSU_DDR_PHY_VTCR0_PDAEN                                                         0x1
6995
6996                 Reserved. Returns zeroes on reads.
6997                 PSU_DDR_PHY_VTCR0_RESERVED_26                                                   0x0
6998
6999                 VREF Word Count
7000                 PSU_DDR_PHY_VTCR0_VWCR                                                          0x4
7001
7002                 DRAM DQ VREF step size used during DRAM VREF training
7003                 PSU_DDR_PHY_VTCR0_DVSS                                                          0x0
7004
7005                 Maximum VREF limit value used during DRAM VREF training
7006                 PSU_DDR_PHY_VTCR0_DVMAX                                                         0x32
7007
7008                 Minimum VREF limit value used during DRAM VREF training
7009                 PSU_DDR_PHY_VTCR0_DVMIN                                                         0x0
7010
7011                 Initial DRAM DQ VREF value used during DRAM VREF training
7012                 PSU_DDR_PHY_VTCR0_DVINIT                                                        0x19
7013
7014                 VREF Training Control Register 0
7015                 (OFFSET, MASK, VALUE)      (0XFD080528, 0xFFFFFFFFU ,0xF9032019U)
7016                 RegMask = (DDR_PHY_VTCR0_TVREF_MASK | DDR_PHY_VTCR0_DVEN_MASK | DDR_PHY_VTCR0_PDAEN_MASK | DDR_PHY_VTCR0_RESERVED_26_MASK | DDR_PHY_VTCR0_VWCR_MASK | DDR_PHY_VTCR0_DVSS_MASK | DDR_PHY_VTCR0_DVMAX_MASK | DDR_PHY_VTCR0_DVMIN_MASK | DDR_PHY_VTCR0_DVINIT_MASK |  0 );
7017
7018                 RegVal = ((0x00000007U << DDR_PHY_VTCR0_TVREF_SHIFT
7019                         | 0x00000001U << DDR_PHY_VTCR0_DVEN_SHIFT
7020                         | 0x00000001U << DDR_PHY_VTCR0_PDAEN_SHIFT
7021                         | 0x00000000U << DDR_PHY_VTCR0_RESERVED_26_SHIFT
7022                         | 0x00000004U << DDR_PHY_VTCR0_VWCR_SHIFT
7023                         | 0x00000000U << DDR_PHY_VTCR0_DVSS_SHIFT
7024                         | 0x00000032U << DDR_PHY_VTCR0_DVMAX_SHIFT
7025                         | 0x00000000U << DDR_PHY_VTCR0_DVMIN_SHIFT
7026                         | 0x00000019U << DDR_PHY_VTCR0_DVINIT_SHIFT
7027                         |  0 ) & RegMask); */
7028                 PSU_Mask_Write (DDR_PHY_VTCR0_OFFSET ,0xFFFFFFFFU ,0xF9032019U);
7029         /*############################################################################################################################ */
7030
7031                 /*Register : VTCR1 @ 0XFD08052C</p>
7032
7033                 Host VREF step size used during VREF training. The register value of N indicates step size of (N+1)
7034                 PSU_DDR_PHY_VTCR1_HVSS                                                          0x0
7035
7036                 Reserved. Returns zeroes on reads.
7037                 PSU_DDR_PHY_VTCR1_RESERVED_27                                                   0x0
7038
7039                 Maximum VREF limit value used during DRAM VREF training.
7040                 PSU_DDR_PHY_VTCR1_HVMAX                                                         0x7f
7041
7042                 Reserved. Returns zeroes on reads.
7043                 PSU_DDR_PHY_VTCR1_RESERVED_19                                                   0x0
7044
7045                 Minimum VREF limit value used during DRAM VREF training.
7046                 PSU_DDR_PHY_VTCR1_HVMIN                                                         0x0
7047
7048                 Reserved. Returns zeroes on reads.
7049                 PSU_DDR_PHY_VTCR1_RESERVED_11                                                   0x0
7050
7051                 Static Host Vref Rank Value
7052                 PSU_DDR_PHY_VTCR1_SHRNK                                                         0x0
7053
7054                 Static Host Vref Rank Enable
7055                 PSU_DDR_PHY_VTCR1_SHREN                                                         0x1
7056
7057                 Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training
7058                 PSU_DDR_PHY_VTCR1_TVREFIO                                                       0x7
7059
7060                 Eye LCDL Offset value for VREF training
7061                 PSU_DDR_PHY_VTCR1_EOFF                                                          0x0
7062
7063                 Number of LCDL Eye points for which VREF training is repeated
7064                 PSU_DDR_PHY_VTCR1_ENUM                                                          0x0
7065
7066                 HOST (IO) internal VREF training Enable
7067                 PSU_DDR_PHY_VTCR1_HVEN                                                          0x1
7068
7069                 Host IO Type Control
7070                 PSU_DDR_PHY_VTCR1_HVIO                                                          0x1
7071
7072                 VREF Training Control Register 1
7073                 (OFFSET, MASK, VALUE)      (0XFD08052C, 0xFFFFFFFFU ,0x07F001E3U)
7074                 RegMask = (DDR_PHY_VTCR1_HVSS_MASK | DDR_PHY_VTCR1_RESERVED_27_MASK | DDR_PHY_VTCR1_HVMAX_MASK | DDR_PHY_VTCR1_RESERVED_19_MASK | DDR_PHY_VTCR1_HVMIN_MASK | DDR_PHY_VTCR1_RESERVED_11_MASK | DDR_PHY_VTCR1_SHRNK_MASK | DDR_PHY_VTCR1_SHREN_MASK | DDR_PHY_VTCR1_TVREFIO_MASK | DDR_PHY_VTCR1_EOFF_MASK | DDR_PHY_VTCR1_ENUM_MASK | DDR_PHY_VTCR1_HVEN_MASK | DDR_PHY_VTCR1_HVIO_MASK |  0 );
7075
7076                 RegVal = ((0x00000000U << DDR_PHY_VTCR1_HVSS_SHIFT
7077                         | 0x00000000U << DDR_PHY_VTCR1_RESERVED_27_SHIFT
7078                         | 0x0000007FU << DDR_PHY_VTCR1_HVMAX_SHIFT
7079                         | 0x00000000U << DDR_PHY_VTCR1_RESERVED_19_SHIFT
7080                         | 0x00000000U << DDR_PHY_VTCR1_HVMIN_SHIFT
7081                         | 0x00000000U << DDR_PHY_VTCR1_RESERVED_11_SHIFT
7082                         | 0x00000000U << DDR_PHY_VTCR1_SHRNK_SHIFT
7083                         | 0x00000001U << DDR_PHY_VTCR1_SHREN_SHIFT
7084                         | 0x00000007U << DDR_PHY_VTCR1_TVREFIO_SHIFT
7085                         | 0x00000000U << DDR_PHY_VTCR1_EOFF_SHIFT
7086                         | 0x00000000U << DDR_PHY_VTCR1_ENUM_SHIFT
7087                         | 0x00000001U << DDR_PHY_VTCR1_HVEN_SHIFT
7088                         | 0x00000001U << DDR_PHY_VTCR1_HVIO_SHIFT
7089                         |  0 ) & RegMask); */
7090                 PSU_Mask_Write (DDR_PHY_VTCR1_OFFSET ,0xFFFFFFFFU ,0x07F001E3U);
7091         /*############################################################################################################################ */
7092
7093                 /*Register : ACBDLR1 @ 0XFD080544</p>
7094
7095                 Reserved. Return zeroes on reads.
7096                 PSU_DDR_PHY_ACBDLR1_RESERVED_31_30                                              0x0
7097
7098                 Delay select for the BDL on Parity.
7099                 PSU_DDR_PHY_ACBDLR1_PARBD                                                       0x0
7100
7101                 Reserved. Return zeroes on reads.
7102                 PSU_DDR_PHY_ACBDLR1_RESERVED_23_22                                              0x0
7103
7104                 Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE.
7105                 PSU_DDR_PHY_ACBDLR1_A16BD                                                       0x0
7106
7107                 Reserved. Return zeroes on reads.
7108                 PSU_DDR_PHY_ACBDLR1_RESERVED_15_14                                              0x0
7109
7110                 Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS.
7111                 PSU_DDR_PHY_ACBDLR1_A17BD                                                       0x0
7112
7113                 Reserved. Return zeroes on reads.
7114                 PSU_DDR_PHY_ACBDLR1_RESERVED_7_6                                                0x0
7115
7116                 Delay select for the BDL on ACTN.
7117                 PSU_DDR_PHY_ACBDLR1_ACTBD                                                       0x0
7118
7119                 AC Bit Delay Line Register 1
7120                 (OFFSET, MASK, VALUE)      (0XFD080544, 0xFFFFFFFFU ,0x00000000U)
7121                 RegMask = (DDR_PHY_ACBDLR1_RESERVED_31_30_MASK | DDR_PHY_ACBDLR1_PARBD_MASK | DDR_PHY_ACBDLR1_RESERVED_23_22_MASK | DDR_PHY_ACBDLR1_A16BD_MASK | DDR_PHY_ACBDLR1_RESERVED_15_14_MASK | DDR_PHY_ACBDLR1_A17BD_MASK | DDR_PHY_ACBDLR1_RESERVED_7_6_MASK | DDR_PHY_ACBDLR1_ACTBD_MASK |  0 );
7122
7123                 RegVal = ((0x00000000U << DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT
7124                         | 0x00000000U << DDR_PHY_ACBDLR1_PARBD_SHIFT
7125                         | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT
7126                         | 0x00000000U << DDR_PHY_ACBDLR1_A16BD_SHIFT
7127                         | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT
7128                         | 0x00000000U << DDR_PHY_ACBDLR1_A17BD_SHIFT
7129                         | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT
7130                         | 0x00000000U << DDR_PHY_ACBDLR1_ACTBD_SHIFT
7131                         |  0 ) & RegMask); */
7132                 PSU_Mask_Write (DDR_PHY_ACBDLR1_OFFSET ,0xFFFFFFFFU ,0x00000000U);
7133         /*############################################################################################################################ */
7134
7135                 /*Register : ACBDLR2 @ 0XFD080548</p>
7136
7137                 Reserved. Return zeroes on reads.
7138                 PSU_DDR_PHY_ACBDLR2_RESERVED_31_30                                              0x0
7139
7140                 Delay select for the BDL on BG[1].
7141                 PSU_DDR_PHY_ACBDLR2_BG1BD                                                       0x0
7142
7143                 Reserved. Return zeroes on reads.
7144                 PSU_DDR_PHY_ACBDLR2_RESERVED_23_22                                              0x0
7145
7146                 Delay select for the BDL on BG[0].
7147                 PSU_DDR_PHY_ACBDLR2_BG0BD                                                       0x0
7148
7149                 Reser.ved Return zeroes on reads.
7150                 PSU_DDR_PHY_ACBDLR2_RESERVED_15_14                                              0x0
7151
7152                 Delay select for the BDL on BA[1].
7153                 PSU_DDR_PHY_ACBDLR2_BA1BD                                                       0x0
7154
7155                 Reserved. Return zeroes on reads.
7156                 PSU_DDR_PHY_ACBDLR2_RESERVED_7_6                                                0x0
7157
7158                 Delay select for the BDL on BA[0].
7159                 PSU_DDR_PHY_ACBDLR2_BA0BD                                                       0x0
7160
7161                 AC Bit Delay Line Register 2
7162                 (OFFSET, MASK, VALUE)      (0XFD080548, 0xFFFFFFFFU ,0x00000000U)
7163                 RegMask = (DDR_PHY_ACBDLR2_RESERVED_31_30_MASK | DDR_PHY_ACBDLR2_BG1BD_MASK | DDR_PHY_ACBDLR2_RESERVED_23_22_MASK | DDR_PHY_ACBDLR2_BG0BD_MASK | DDR_PHY_ACBDLR2_RESERVED_15_14_MASK | DDR_PHY_ACBDLR2_BA1BD_MASK | DDR_PHY_ACBDLR2_RESERVED_7_6_MASK | DDR_PHY_ACBDLR2_BA0BD_MASK |  0 );
7164
7165                 RegVal = ((0x00000000U << DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT
7166                         | 0x00000000U << DDR_PHY_ACBDLR2_BG1BD_SHIFT
7167                         | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT
7168                         | 0x00000000U << DDR_PHY_ACBDLR2_BG0BD_SHIFT
7169                         | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT
7170                         | 0x00000000U << DDR_PHY_ACBDLR2_BA1BD_SHIFT
7171                         | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT
7172                         | 0x00000000U << DDR_PHY_ACBDLR2_BA0BD_SHIFT
7173                         |  0 ) & RegMask); */
7174                 PSU_Mask_Write (DDR_PHY_ACBDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
7175         /*############################################################################################################################ */
7176
7177                 /*Register : ACBDLR6 @ 0XFD080558</p>
7178
7179                 Reserved. Return zeroes on reads.
7180                 PSU_DDR_PHY_ACBDLR6_RESERVED_31_30                                              0x0
7181
7182                 Delay select for the BDL on Address A[3].
7183                 PSU_DDR_PHY_ACBDLR6_A03BD                                                       0x0
7184
7185                 Reserved. Return zeroes on reads.
7186                 PSU_DDR_PHY_ACBDLR6_RESERVED_23_22                                              0x0
7187
7188                 Delay select for the BDL on Address A[2].
7189                 PSU_DDR_PHY_ACBDLR6_A02BD                                                       0x0
7190
7191                 Reserved. Return zeroes on reads.
7192                 PSU_DDR_PHY_ACBDLR6_RESERVED_15_14                                              0x0
7193
7194                 Delay select for the BDL on Address A[1].
7195                 PSU_DDR_PHY_ACBDLR6_A01BD                                                       0x0
7196
7197                 Reserved. Return zeroes on reads.
7198                 PSU_DDR_PHY_ACBDLR6_RESERVED_7_6                                                0x0
7199
7200                 Delay select for the BDL on Address A[0].
7201                 PSU_DDR_PHY_ACBDLR6_A00BD                                                       0x0
7202
7203                 AC Bit Delay Line Register 6
7204                 (OFFSET, MASK, VALUE)      (0XFD080558, 0xFFFFFFFFU ,0x00000000U)
7205                 RegMask = (DDR_PHY_ACBDLR6_RESERVED_31_30_MASK | DDR_PHY_ACBDLR6_A03BD_MASK | DDR_PHY_ACBDLR6_RESERVED_23_22_MASK | DDR_PHY_ACBDLR6_A02BD_MASK | DDR_PHY_ACBDLR6_RESERVED_15_14_MASK | DDR_PHY_ACBDLR6_A01BD_MASK | DDR_PHY_ACBDLR6_RESERVED_7_6_MASK | DDR_PHY_ACBDLR6_A00BD_MASK |  0 );
7206
7207                 RegVal = ((0x00000000U << DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT
7208                         | 0x00000000U << DDR_PHY_ACBDLR6_A03BD_SHIFT
7209                         | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT
7210                         | 0x00000000U << DDR_PHY_ACBDLR6_A02BD_SHIFT
7211                         | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT
7212                         | 0x00000000U << DDR_PHY_ACBDLR6_A01BD_SHIFT
7213                         | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT
7214                         | 0x00000000U << DDR_PHY_ACBDLR6_A00BD_SHIFT
7215                         |  0 ) & RegMask); */
7216                 PSU_Mask_Write (DDR_PHY_ACBDLR6_OFFSET ,0xFFFFFFFFU ,0x00000000U);
7217         /*############################################################################################################################ */
7218
7219                 /*Register : ACBDLR7 @ 0XFD08055C</p>
7220
7221                 Reserved. Return zeroes on reads.
7222                 PSU_DDR_PHY_ACBDLR7_RESERVED_31_30                                              0x0
7223
7224                 Delay select for the BDL on Address A[7].
7225                 PSU_DDR_PHY_ACBDLR7_A07BD                                                       0x0
7226
7227                 Reserved. Return zeroes on reads.
7228                 PSU_DDR_PHY_ACBDLR7_RESERVED_23_22                                              0x0
7229
7230                 Delay select for the BDL on Address A[6].
7231                 PSU_DDR_PHY_ACBDLR7_A06BD                                                       0x0
7232
7233                 Reserved. Return zeroes on reads.
7234                 PSU_DDR_PHY_ACBDLR7_RESERVED_15_14                                              0x0
7235
7236                 Delay select for the BDL on Address A[5].
7237                 PSU_DDR_PHY_ACBDLR7_A05BD                                                       0x0
7238
7239                 Reserved. Return zeroes on reads.
7240                 PSU_DDR_PHY_ACBDLR7_RESERVED_7_6                                                0x0
7241
7242                 Delay select for the BDL on Address A[4].
7243                 PSU_DDR_PHY_ACBDLR7_A04BD                                                       0x0
7244
7245                 AC Bit Delay Line Register 7
7246                 (OFFSET, MASK, VALUE)      (0XFD08055C, 0xFFFFFFFFU ,0x00000000U)
7247                 RegMask = (DDR_PHY_ACBDLR7_RESERVED_31_30_MASK | DDR_PHY_ACBDLR7_A07BD_MASK | DDR_PHY_ACBDLR7_RESERVED_23_22_MASK | DDR_PHY_ACBDLR7_A06BD_MASK | DDR_PHY_ACBDLR7_RESERVED_15_14_MASK | DDR_PHY_ACBDLR7_A05BD_MASK | DDR_PHY_ACBDLR7_RESERVED_7_6_MASK | DDR_PHY_ACBDLR7_A04BD_MASK |  0 );
7248
7249                 RegVal = ((0x00000000U << DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT
7250                         | 0x00000000U << DDR_PHY_ACBDLR7_A07BD_SHIFT
7251                         | 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT
7252                         | 0x00000000U << DDR_PHY_ACBDLR7_A06BD_SHIFT
7253                         | 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT
7254                         | 0x00000000U << DDR_PHY_ACBDLR7_A05BD_SHIFT
7255                         | 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT
7256                         | 0x00000000U << DDR_PHY_ACBDLR7_A04BD_SHIFT
7257                         |  0 ) & RegMask); */
7258                 PSU_Mask_Write (DDR_PHY_ACBDLR7_OFFSET ,0xFFFFFFFFU ,0x00000000U);
7259         /*############################################################################################################################ */
7260
7261                 /*Register : ACBDLR8 @ 0XFD080560</p>
7262
7263                 Reserved. Return zeroes on reads.
7264                 PSU_DDR_PHY_ACBDLR8_RESERVED_31_30                                              0x0
7265
7266                 Delay select for the BDL on Address A[11].
7267                 PSU_DDR_PHY_ACBDLR8_A11BD                                                       0x0
7268
7269                 Reserved. Return zeroes on reads.
7270                 PSU_DDR_PHY_ACBDLR8_RESERVED_23_22                                              0x0
7271
7272                 Delay select for the BDL on Address A[10].
7273                 PSU_DDR_PHY_ACBDLR8_A10BD                                                       0x0
7274
7275                 Reserved. Return zeroes on reads.
7276                 PSU_DDR_PHY_ACBDLR8_RESERVED_15_14                                              0x0
7277
7278                 Delay select for the BDL on Address A[9].
7279                 PSU_DDR_PHY_ACBDLR8_A09BD                                                       0x0
7280
7281                 Reserved. Return zeroes on reads.
7282                 PSU_DDR_PHY_ACBDLR8_RESERVED_7_6                                                0x0
7283
7284                 Delay select for the BDL on Address A[8].
7285                 PSU_DDR_PHY_ACBDLR8_A08BD                                                       0x0
7286
7287                 AC Bit Delay Line Register 8
7288                 (OFFSET, MASK, VALUE)      (0XFD080560, 0xFFFFFFFFU ,0x00000000U)
7289                 RegMask = (DDR_PHY_ACBDLR8_RESERVED_31_30_MASK | DDR_PHY_ACBDLR8_A11BD_MASK | DDR_PHY_ACBDLR8_RESERVED_23_22_MASK | DDR_PHY_ACBDLR8_A10BD_MASK | DDR_PHY_ACBDLR8_RESERVED_15_14_MASK | DDR_PHY_ACBDLR8_A09BD_MASK | DDR_PHY_ACBDLR8_RESERVED_7_6_MASK | DDR_PHY_ACBDLR8_A08BD_MASK |  0 );
7290
7291                 RegVal = ((0x00000000U << DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT
7292                         | 0x00000000U << DDR_PHY_ACBDLR8_A11BD_SHIFT
7293                         | 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT
7294                         | 0x00000000U << DDR_PHY_ACBDLR8_A10BD_SHIFT
7295                         | 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT
7296                         | 0x00000000U << DDR_PHY_ACBDLR8_A09BD_SHIFT
7297                         | 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT
7298                         | 0x00000000U << DDR_PHY_ACBDLR8_A08BD_SHIFT
7299                         |  0 ) & RegMask); */
7300                 PSU_Mask_Write (DDR_PHY_ACBDLR8_OFFSET ,0xFFFFFFFFU ,0x00000000U);
7301         /*############################################################################################################################ */
7302
7303                 /*Register : ACBDLR9 @ 0XFD080564</p>
7304
7305                 Reserved. Return zeroes on reads.
7306                 PSU_DDR_PHY_ACBDLR9_RESERVED_31_30                                              0x0
7307
7308                 Delay select for the BDL on Address A[15].
7309                 PSU_DDR_PHY_ACBDLR9_A15BD                                                       0x0
7310
7311                 Reserved. Return zeroes on reads.
7312                 PSU_DDR_PHY_ACBDLR9_RESERVED_23_22                                              0x0
7313
7314                 Delay select for the BDL on Address A[14].
7315                 PSU_DDR_PHY_ACBDLR9_A14BD                                                       0x0
7316
7317                 Reserved. Return zeroes on reads.
7318                 PSU_DDR_PHY_ACBDLR9_RESERVED_15_14                                              0x0
7319
7320                 Delay select for the BDL on Address A[13].
7321                 PSU_DDR_PHY_ACBDLR9_A13BD                                                       0x0
7322
7323                 Reserved. Return zeroes on reads.
7324                 PSU_DDR_PHY_ACBDLR9_RESERVED_7_6                                                0x0
7325
7326                 Delay select for the BDL on Address A[12].
7327                 PSU_DDR_PHY_ACBDLR9_A12BD                                                       0x0
7328
7329                 AC Bit Delay Line Register 9
7330                 (OFFSET, MASK, VALUE)      (0XFD080564, 0xFFFFFFFFU ,0x00000000U)
7331                 RegMask = (DDR_PHY_ACBDLR9_RESERVED_31_30_MASK | DDR_PHY_ACBDLR9_A15BD_MASK | DDR_PHY_ACBDLR9_RESERVED_23_22_MASK | DDR_PHY_ACBDLR9_A14BD_MASK | DDR_PHY_ACBDLR9_RESERVED_15_14_MASK | DDR_PHY_ACBDLR9_A13BD_MASK | DDR_PHY_ACBDLR9_RESERVED_7_6_MASK | DDR_PHY_ACBDLR9_A12BD_MASK |  0 );
7332
7333                 RegVal = ((0x00000000U << DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT
7334                         | 0x00000000U << DDR_PHY_ACBDLR9_A15BD_SHIFT
7335                         | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT
7336                         | 0x00000000U << DDR_PHY_ACBDLR9_A14BD_SHIFT
7337                         | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT
7338                         | 0x00000000U << DDR_PHY_ACBDLR9_A13BD_SHIFT
7339                         | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT
7340                         | 0x00000000U << DDR_PHY_ACBDLR9_A12BD_SHIFT
7341                         |  0 ) & RegMask); */
7342                 PSU_Mask_Write (DDR_PHY_ACBDLR9_OFFSET ,0xFFFFFFFFU ,0x00000000U);
7343         /*############################################################################################################################ */
7344
7345                 /*Register : ZQCR @ 0XFD080680</p>
7346
7347                 Reserved. Return zeroes on reads.
7348                 PSU_DDR_PHY_ZQCR_RESERVED_31_26                                                 0x0
7349
7350                 ZQ VREF Range
7351                 PSU_DDR_PHY_ZQCR_ZQREFISELRANGE                                                 0x0
7352
7353                 Programmable Wait for Frequency B
7354                 PSU_DDR_PHY_ZQCR_PGWAIT_FRQB                                                    0x11
7355
7356                 Programmable Wait for Frequency A
7357                 PSU_DDR_PHY_ZQCR_PGWAIT_FRQA                                                    0x11
7358
7359                 ZQ VREF Pad Enable
7360                 PSU_DDR_PHY_ZQCR_ZQREFPEN                                                       0x0
7361
7362                 ZQ Internal VREF Enable
7363                 PSU_DDR_PHY_ZQCR_ZQREFIEN                                                       0x1
7364
7365                 Choice of termination mode
7366                 PSU_DDR_PHY_ZQCR_ODT_MODE                                                       0x1
7367
7368                 Force ZCAL VT update
7369                 PSU_DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE                                           0x0
7370
7371                 IO VT Drift Limit
7372                 PSU_DDR_PHY_ZQCR_IODLMT                                                         0x2
7373
7374                 Averaging algorithm enable, if set, enables averaging algorithm
7375                 PSU_DDR_PHY_ZQCR_AVGEN                                                          0x1
7376
7377                 Maximum number of averaging rounds to be used by averaging algorithm
7378                 PSU_DDR_PHY_ZQCR_AVGMAX                                                         0x2
7379
7380                 ZQ Calibration Type
7381                 PSU_DDR_PHY_ZQCR_ZCALT                                                          0x0
7382
7383                 ZQ Power Down
7384                 PSU_DDR_PHY_ZQCR_ZQPD                                                           0x0
7385
7386                 ZQ Impedance Control Register
7387                 (OFFSET, MASK, VALUE)      (0XFD080680, 0xFFFFFFFFU ,0x008A2A58U)
7388                 RegMask = (DDR_PHY_ZQCR_RESERVED_31_26_MASK | DDR_PHY_ZQCR_ZQREFISELRANGE_MASK | DDR_PHY_ZQCR_PGWAIT_FRQB_MASK | DDR_PHY_ZQCR_PGWAIT_FRQA_MASK | DDR_PHY_ZQCR_ZQREFPEN_MASK | DDR_PHY_ZQCR_ZQREFIEN_MASK | DDR_PHY_ZQCR_ODT_MODE_MASK | DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK | DDR_PHY_ZQCR_IODLMT_MASK | DDR_PHY_ZQCR_AVGEN_MASK | DDR_PHY_ZQCR_AVGMAX_MASK | DDR_PHY_ZQCR_ZCALT_MASK | DDR_PHY_ZQCR_ZQPD_MASK |  0 );
7389
7390                 RegVal = ((0x00000000U << DDR_PHY_ZQCR_RESERVED_31_26_SHIFT
7391                         | 0x00000000U << DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT
7392                         | 0x00000011U << DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT
7393                         | 0x00000011U << DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT
7394                         | 0x00000000U << DDR_PHY_ZQCR_ZQREFPEN_SHIFT
7395                         | 0x00000001U << DDR_PHY_ZQCR_ZQREFIEN_SHIFT
7396                         | 0x00000001U << DDR_PHY_ZQCR_ODT_MODE_SHIFT
7397                         | 0x00000000U << DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT
7398                         | 0x00000002U << DDR_PHY_ZQCR_IODLMT_SHIFT
7399                         | 0x00000001U << DDR_PHY_ZQCR_AVGEN_SHIFT
7400                         | 0x00000002U << DDR_PHY_ZQCR_AVGMAX_SHIFT
7401                         | 0x00000000U << DDR_PHY_ZQCR_ZCALT_SHIFT
7402                         | 0x00000000U << DDR_PHY_ZQCR_ZQPD_SHIFT
7403                         |  0 ) & RegMask); */
7404                 PSU_Mask_Write (DDR_PHY_ZQCR_OFFSET ,0xFFFFFFFFU ,0x008A2A58U);
7405         /*############################################################################################################################ */
7406
7407                 /*Register : ZQ0PR0 @ 0XFD080684</p>
7408
7409                 Pull-down drive strength ZCTRL over-ride enable
7410                 PSU_DDR_PHY_ZQ0PR0_PD_DRV_ZDEN                                                  0x0
7411
7412                 Pull-up drive strength ZCTRL over-ride enable
7413                 PSU_DDR_PHY_ZQ0PR0_PU_DRV_ZDEN                                                  0x0
7414
7415                 Pull-down termination ZCTRL over-ride enable
7416                 PSU_DDR_PHY_ZQ0PR0_PD_ODT_ZDEN                                                  0x0
7417
7418                 Pull-up termination ZCTRL over-ride enable
7419                 PSU_DDR_PHY_ZQ0PR0_PU_ODT_ZDEN                                                  0x0
7420
7421                 Calibration segment bypass
7422                 PSU_DDR_PHY_ZQ0PR0_ZSEGBYP                                                      0x0
7423
7424                 VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
7425                 PSU_DDR_PHY_ZQ0PR0_ZLE_MODE                                                     0x0
7426
7427                 Termination adjustment
7428                 PSU_DDR_PHY_ZQ0PR0_ODT_ADJUST                                                   0x0
7429
7430                 Pulldown drive strength adjustment
7431                 PSU_DDR_PHY_ZQ0PR0_PD_DRV_ADJUST                                                0x0
7432
7433                 Pullup drive strength adjustment
7434                 PSU_DDR_PHY_ZQ0PR0_PU_DRV_ADJUST                                                0x0
7435
7436                 DRAM Impedance Divide Ratio
7437                 PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT                                               0x7
7438
7439                 HOST Impedance Divide Ratio
7440                 PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT                                               0x7
7441
7442                 Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
7443                 PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD                                            0xd
7444
7445                 Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
7446                 PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU                                            0xd
7447
7448                 ZQ n Impedance Control Program Register 0
7449                 (OFFSET, MASK, VALUE)      (0XFD080684, 0xFFFFFFFFU ,0x000077DDU)
7450                 RegMask = (DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK | DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK | DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK | DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK | DDR_PHY_ZQ0PR0_ZSEGBYP_MASK | DDR_PHY_ZQ0PR0_ZLE_MODE_MASK | DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK | DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK | DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK | DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK | DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK | DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK | DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK |  0 );
7451
7452                 RegVal = ((0x00000000U << DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT
7453                         | 0x00000000U << DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT
7454                         | 0x00000000U << DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT
7455                         | 0x00000000U << DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT
7456                         | 0x00000000U << DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT
7457                         | 0x00000000U << DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT
7458                         | 0x00000000U << DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT
7459                         | 0x00000000U << DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT
7460                         | 0x00000000U << DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT
7461                         | 0x00000007U << DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT
7462                         | 0x00000007U << DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT
7463                         | 0x0000000DU << DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT
7464                         | 0x0000000DU << DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT
7465                         |  0 ) & RegMask); */
7466                 PSU_Mask_Write (DDR_PHY_ZQ0PR0_OFFSET ,0xFFFFFFFFU ,0x000077DDU);
7467         /*############################################################################################################################ */
7468
7469                 /*Register : ZQ0OR0 @ 0XFD080694</p>
7470
7471                 Reserved. Return zeros on reads.
7472                 PSU_DDR_PHY_ZQ0OR0_RESERVED_31_26                                               0x0
7473
7474                 Override value for the pull-up output impedance
7475                 PSU_DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD                                            0x1e1
7476
7477                 Reserved. Return zeros on reads.
7478                 PSU_DDR_PHY_ZQ0OR0_RESERVED_15_10                                               0x0
7479
7480                 Override value for the pull-down output impedance
7481                 PSU_DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD                                            0x210
7482
7483                 ZQ n Impedance Control Override Data Register 0
7484                 (OFFSET, MASK, VALUE)      (0XFD080694, 0xFFFFFFFFU ,0x01E10210U)
7485                 RegMask = (DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK | DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK | DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK | DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK |  0 );
7486
7487                 RegVal = ((0x00000000U << DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT
7488                         | 0x000001E1U << DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT
7489                         | 0x00000000U << DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT
7490                         | 0x00000210U << DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT
7491                         |  0 ) & RegMask); */
7492                 PSU_Mask_Write (DDR_PHY_ZQ0OR0_OFFSET ,0xFFFFFFFFU ,0x01E10210U);
7493         /*############################################################################################################################ */
7494
7495                 /*Register : ZQ0OR1 @ 0XFD080698</p>
7496
7497                 Reserved. Return zeros on reads.
7498                 PSU_DDR_PHY_ZQ0OR1_RESERVED_31_26                                               0x0
7499
7500                 Override value for the pull-up termination
7501                 PSU_DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD                                            0x1e1
7502
7503                 Reserved. Return zeros on reads.
7504                 PSU_DDR_PHY_ZQ0OR1_RESERVED_15_10                                               0x0
7505
7506                 Override value for the pull-down termination
7507                 PSU_DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD                                            0x0
7508
7509                 ZQ n Impedance Control Override Data Register 1
7510                 (OFFSET, MASK, VALUE)      (0XFD080698, 0xFFFFFFFFU ,0x01E10000U)
7511                 RegMask = (DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK | DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK | DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK | DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK |  0 );
7512
7513                 RegVal = ((0x00000000U << DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT
7514                         | 0x000001E1U << DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT
7515                         | 0x00000000U << DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT
7516                         | 0x00000000U << DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT
7517                         |  0 ) & RegMask); */
7518                 PSU_Mask_Write (DDR_PHY_ZQ0OR1_OFFSET ,0xFFFFFFFFU ,0x01E10000U);
7519         /*############################################################################################################################ */
7520
7521                 /*Register : ZQ1PR0 @ 0XFD0806A4</p>
7522
7523                 Pull-down drive strength ZCTRL over-ride enable
7524                 PSU_DDR_PHY_ZQ1PR0_PD_DRV_ZDEN                                                  0x0
7525
7526                 Pull-up drive strength ZCTRL over-ride enable
7527                 PSU_DDR_PHY_ZQ1PR0_PU_DRV_ZDEN                                                  0x0
7528
7529                 Pull-down termination ZCTRL over-ride enable
7530                 PSU_DDR_PHY_ZQ1PR0_PD_ODT_ZDEN                                                  0x0
7531
7532                 Pull-up termination ZCTRL over-ride enable
7533                 PSU_DDR_PHY_ZQ1PR0_PU_ODT_ZDEN                                                  0x0
7534
7535                 Calibration segment bypass
7536                 PSU_DDR_PHY_ZQ1PR0_ZSEGBYP                                                      0x0
7537
7538                 VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
7539                 PSU_DDR_PHY_ZQ1PR0_ZLE_MODE                                                     0x0
7540
7541                 Termination adjustment
7542                 PSU_DDR_PHY_ZQ1PR0_ODT_ADJUST                                                   0x0
7543
7544                 Pulldown drive strength adjustment
7545                 PSU_DDR_PHY_ZQ1PR0_PD_DRV_ADJUST                                                0x1
7546
7547                 Pullup drive strength adjustment
7548                 PSU_DDR_PHY_ZQ1PR0_PU_DRV_ADJUST                                                0x0
7549
7550                 DRAM Impedance Divide Ratio
7551                 PSU_DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT                                               0x7
7552
7553                 HOST Impedance Divide Ratio
7554                 PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT                                               0xb
7555
7556                 Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
7557                 PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD                                            0xd
7558
7559                 Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
7560                 PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU                                            0xb
7561
7562                 ZQ n Impedance Control Program Register 0
7563                 (OFFSET, MASK, VALUE)      (0XFD0806A4, 0xFFFFFFFFU ,0x00087BDBU)
7564                 RegMask = (DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK | DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK | DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK | DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK | DDR_PHY_ZQ1PR0_ZSEGBYP_MASK | DDR_PHY_ZQ1PR0_ZLE_MODE_MASK | DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK | DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK | DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK | DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK | DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK | DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK | DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK |  0 );
7565
7566                 RegVal = ((0x00000000U << DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT
7567                         | 0x00000000U << DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT
7568                         | 0x00000000U << DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT
7569                         | 0x00000000U << DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT
7570                         | 0x00000000U << DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT
7571                         | 0x00000000U << DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT
7572                         | 0x00000000U << DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT
7573                         | 0x00000001U << DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT
7574                         | 0x00000000U << DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT
7575                         | 0x00000007U << DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT
7576                         | 0x0000000BU << DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT
7577                         | 0x0000000DU << DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT
7578                         | 0x0000000BU << DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT
7579                         |  0 ) & RegMask); */
7580                 PSU_Mask_Write (DDR_PHY_ZQ1PR0_OFFSET ,0xFFFFFFFFU ,0x00087BDBU);
7581         /*############################################################################################################################ */
7582
7583                 /*Register : DX0GCR0 @ 0XFD080700</p>
7584
7585                 Calibration Bypass
7586                 PSU_DDR_PHY_DX0GCR0_CALBYP                                                      0x0
7587
7588                 Master Delay Line Enable
7589                 PSU_DDR_PHY_DX0GCR0_MDLEN                                                       0x1
7590
7591                 Configurable ODT(TE) Phase Shift
7592                 PSU_DDR_PHY_DX0GCR0_CODTSHFT                                                    0x0
7593
7594                 DQS Duty Cycle Correction
7595                 PSU_DDR_PHY_DX0GCR0_DQSDCC                                                      0x0
7596
7597                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
7598                 PSU_DDR_PHY_DX0GCR0_RDDLY                                                       0x8
7599
7600                 Reserved. Return zeroes on reads.
7601                 PSU_DDR_PHY_DX0GCR0_RESERVED_19_14                                              0x0
7602
7603                 DQSNSE Power Down Receiver
7604                 PSU_DDR_PHY_DX0GCR0_DQSNSEPDR                                                   0x0
7605
7606                 DQSSE Power Down Receiver
7607                 PSU_DDR_PHY_DX0GCR0_DQSSEPDR                                                    0x0
7608
7609                 RTT On Additive Latency
7610                 PSU_DDR_PHY_DX0GCR0_RTTOAL                                                      0x0
7611
7612                 RTT Output Hold
7613                 PSU_DDR_PHY_DX0GCR0_RTTOH                                                       0x3
7614
7615                 Configurable PDR Phase Shift
7616                 PSU_DDR_PHY_DX0GCR0_CPDRSHFT                                                    0x0
7617
7618                 DQSR Power Down
7619                 PSU_DDR_PHY_DX0GCR0_DQSRPD                                                      0x0
7620
7621                 DQSG Power Down Receiver
7622                 PSU_DDR_PHY_DX0GCR0_DQSGPDR                                                     0x0
7623
7624                 Reserved. Return zeroes on reads.
7625                 PSU_DDR_PHY_DX0GCR0_RESERVED_4                                                  0x0
7626
7627                 DQSG On-Die Termination
7628                 PSU_DDR_PHY_DX0GCR0_DQSGODT                                                     0x0
7629
7630                 DQSG Output Enable
7631                 PSU_DDR_PHY_DX0GCR0_DQSGOE                                                      0x1
7632
7633                 Reserved. Return zeroes on reads.
7634                 PSU_DDR_PHY_DX0GCR0_RESERVED_1_0                                                0x0
7635
7636                 DATX8 n General Configuration Register 0
7637                 (OFFSET, MASK, VALUE)      (0XFD080700, 0xFFFFFFFFU ,0x40800604U)
7638                 RegMask = (DDR_PHY_DX0GCR0_CALBYP_MASK | DDR_PHY_DX0GCR0_MDLEN_MASK | DDR_PHY_DX0GCR0_CODTSHFT_MASK | DDR_PHY_DX0GCR0_DQSDCC_MASK | DDR_PHY_DX0GCR0_RDDLY_MASK | DDR_PHY_DX0GCR0_RESERVED_19_14_MASK | DDR_PHY_DX0GCR0_DQSNSEPDR_MASK | DDR_PHY_DX0GCR0_DQSSEPDR_MASK | DDR_PHY_DX0GCR0_RTTOAL_MASK | DDR_PHY_DX0GCR0_RTTOH_MASK | DDR_PHY_DX0GCR0_CPDRSHFT_MASK | DDR_PHY_DX0GCR0_DQSRPD_MASK | DDR_PHY_DX0GCR0_DQSGPDR_MASK | DDR_PHY_DX0GCR0_RESERVED_4_MASK | DDR_PHY_DX0GCR0_DQSGODT_MASK | DDR_PHY_DX0GCR0_DQSGOE_MASK | DDR_PHY_DX0GCR0_RESERVED_1_0_MASK |  0 );
7639
7640                 RegVal = ((0x00000000U << DDR_PHY_DX0GCR0_CALBYP_SHIFT
7641                         | 0x00000001U << DDR_PHY_DX0GCR0_MDLEN_SHIFT
7642                         | 0x00000000U << DDR_PHY_DX0GCR0_CODTSHFT_SHIFT
7643                         | 0x00000000U << DDR_PHY_DX0GCR0_DQSDCC_SHIFT
7644                         | 0x00000008U << DDR_PHY_DX0GCR0_RDDLY_SHIFT
7645                         | 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT
7646                         | 0x00000000U << DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT
7647                         | 0x00000000U << DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT
7648                         | 0x00000000U << DDR_PHY_DX0GCR0_RTTOAL_SHIFT
7649                         | 0x00000003U << DDR_PHY_DX0GCR0_RTTOH_SHIFT
7650                         | 0x00000000U << DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT
7651                         | 0x00000000U << DDR_PHY_DX0GCR0_DQSRPD_SHIFT
7652                         | 0x00000000U << DDR_PHY_DX0GCR0_DQSGPDR_SHIFT
7653                         | 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_4_SHIFT
7654                         | 0x00000000U << DDR_PHY_DX0GCR0_DQSGODT_SHIFT
7655                         | 0x00000001U << DDR_PHY_DX0GCR0_DQSGOE_SHIFT
7656                         | 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT
7657                         |  0 ) & RegMask); */
7658                 PSU_Mask_Write (DDR_PHY_DX0GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
7659         /*############################################################################################################################ */
7660
7661                 /*Register : DX0GCR4 @ 0XFD080710</p>
7662
7663                 Byte lane VREF IOM (Used only by D4MU IOs)
7664                 PSU_DDR_PHY_DX0GCR4_RESERVED_31_29                                              0x0
7665
7666                 Byte Lane VREF Pad Enable
7667                 PSU_DDR_PHY_DX0GCR4_DXREFPEN                                                    0x0
7668
7669                 Byte Lane Internal VREF Enable
7670                 PSU_DDR_PHY_DX0GCR4_DXREFEEN                                                    0x3
7671
7672                 Byte Lane Single-End VREF Enable
7673                 PSU_DDR_PHY_DX0GCR4_DXREFSEN                                                    0x1
7674
7675                 Reserved. Returns zeros on reads.
7676                 PSU_DDR_PHY_DX0GCR4_RESERVED_24                                                 0x0
7677
7678                 External VREF generator REFSEL range select
7679                 PSU_DDR_PHY_DX0GCR4_DXREFESELRANGE                                              0x0
7680
7681                 Byte Lane External VREF Select
7682                 PSU_DDR_PHY_DX0GCR4_DXREFESEL                                                   0x0
7683
7684                 Single ended VREF generator REFSEL range select
7685                 PSU_DDR_PHY_DX0GCR4_DXREFSSELRANGE                                              0x1
7686
7687                 Byte Lane Single-End VREF Select
7688                 PSU_DDR_PHY_DX0GCR4_DXREFSSEL                                                   0x30
7689
7690                 Reserved. Returns zeros on reads.
7691                 PSU_DDR_PHY_DX0GCR4_RESERVED_7_6                                                0x0
7692
7693                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
7694                 PSU_DDR_PHY_DX0GCR4_DXREFIEN                                                    0xf
7695
7696                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
7697                 PSU_DDR_PHY_DX0GCR4_DXREFIMON                                                   0x0
7698
7699                 DATX8 n General Configuration Register 4
7700                 (OFFSET, MASK, VALUE)      (0XFD080710, 0xFFFFFFFFU ,0x0E00B03CU)
7701                 RegMask = (DDR_PHY_DX0GCR4_RESERVED_31_29_MASK | DDR_PHY_DX0GCR4_DXREFPEN_MASK | DDR_PHY_DX0GCR4_DXREFEEN_MASK | DDR_PHY_DX0GCR4_DXREFSEN_MASK | DDR_PHY_DX0GCR4_RESERVED_24_MASK | DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX0GCR4_DXREFESEL_MASK | DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX0GCR4_DXREFSSEL_MASK | DDR_PHY_DX0GCR4_RESERVED_7_6_MASK | DDR_PHY_DX0GCR4_DXREFIEN_MASK | DDR_PHY_DX0GCR4_DXREFIMON_MASK |  0 );
7702
7703                 RegVal = ((0x00000000U << DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT
7704                         | 0x00000000U << DDR_PHY_DX0GCR4_DXREFPEN_SHIFT
7705                         | 0x00000003U << DDR_PHY_DX0GCR4_DXREFEEN_SHIFT
7706                         | 0x00000001U << DDR_PHY_DX0GCR4_DXREFSEN_SHIFT
7707                         | 0x00000000U << DDR_PHY_DX0GCR4_RESERVED_24_SHIFT
7708                         | 0x00000000U << DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT
7709                         | 0x00000000U << DDR_PHY_DX0GCR4_DXREFESEL_SHIFT
7710                         | 0x00000001U << DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT
7711                         | 0x00000030U << DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT
7712                         | 0x00000000U << DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT
7713                         | 0x0000000FU << DDR_PHY_DX0GCR4_DXREFIEN_SHIFT
7714                         | 0x00000000U << DDR_PHY_DX0GCR4_DXREFIMON_SHIFT
7715                         |  0 ) & RegMask); */
7716                 PSU_Mask_Write (DDR_PHY_DX0GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
7717         /*############################################################################################################################ */
7718
7719                 /*Register : DX0GCR5 @ 0XFD080714</p>
7720
7721                 Reserved. Returns zeros on reads.
7722                 PSU_DDR_PHY_DX0GCR5_RESERVED_31                                                 0x0
7723
7724                 Byte Lane internal VREF Select for Rank 3
7725                 PSU_DDR_PHY_DX0GCR5_DXREFISELR3                                                 0x9
7726
7727                 Reserved. Returns zeros on reads.
7728                 PSU_DDR_PHY_DX0GCR5_RESERVED_23                                                 0x0
7729
7730                 Byte Lane internal VREF Select for Rank 2
7731                 PSU_DDR_PHY_DX0GCR5_DXREFISELR2                                                 0x9
7732
7733                 Reserved. Returns zeros on reads.
7734                 PSU_DDR_PHY_DX0GCR5_RESERVED_15                                                 0x0
7735
7736                 Byte Lane internal VREF Select for Rank 1
7737                 PSU_DDR_PHY_DX0GCR5_DXREFISELR1                                                 0x4f
7738
7739                 Reserved. Returns zeros on reads.
7740                 PSU_DDR_PHY_DX0GCR5_RESERVED_7                                                  0x0
7741
7742                 Byte Lane internal VREF Select for Rank 0
7743                 PSU_DDR_PHY_DX0GCR5_DXREFISELR0                                                 0x4f
7744
7745                 DATX8 n General Configuration Register 5
7746                 (OFFSET, MASK, VALUE)      (0XFD080714, 0xFFFFFFFFU ,0x09094F4FU)
7747                 RegMask = (DDR_PHY_DX0GCR5_RESERVED_31_MASK | DDR_PHY_DX0GCR5_DXREFISELR3_MASK | DDR_PHY_DX0GCR5_RESERVED_23_MASK | DDR_PHY_DX0GCR5_DXREFISELR2_MASK | DDR_PHY_DX0GCR5_RESERVED_15_MASK | DDR_PHY_DX0GCR5_DXREFISELR1_MASK | DDR_PHY_DX0GCR5_RESERVED_7_MASK | DDR_PHY_DX0GCR5_DXREFISELR0_MASK |  0 );
7748
7749                 RegVal = ((0x00000000U << DDR_PHY_DX0GCR5_RESERVED_31_SHIFT
7750                         | 0x00000009U << DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT
7751                         | 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_23_SHIFT
7752                         | 0x00000009U << DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT
7753                         | 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_15_SHIFT
7754                         | 0x0000004FU << DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT
7755                         | 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_7_SHIFT
7756                         | 0x0000004FU << DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT
7757                         |  0 ) & RegMask); */
7758                 PSU_Mask_Write (DDR_PHY_DX0GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
7759         /*############################################################################################################################ */
7760
7761                 /*Register : DX0GCR6 @ 0XFD080718</p>
7762
7763                 Reserved. Returns zeros on reads.
7764                 PSU_DDR_PHY_DX0GCR6_RESERVED_31_30                                              0x0
7765
7766                 DRAM DQ VREF Select for Rank3
7767                 PSU_DDR_PHY_DX0GCR6_DXDQVREFR3                                                  0x9
7768
7769                 Reserved. Returns zeros on reads.
7770                 PSU_DDR_PHY_DX0GCR6_RESERVED_23_22                                              0x0
7771
7772                 DRAM DQ VREF Select for Rank2
7773                 PSU_DDR_PHY_DX0GCR6_DXDQVREFR2                                                  0x9
7774
7775                 Reserved. Returns zeros on reads.
7776                 PSU_DDR_PHY_DX0GCR6_RESERVED_15_14                                              0x0
7777
7778                 DRAM DQ VREF Select for Rank1
7779                 PSU_DDR_PHY_DX0GCR6_DXDQVREFR1                                                  0x2b
7780
7781                 Reserved. Returns zeros on reads.
7782                 PSU_DDR_PHY_DX0GCR6_RESERVED_7_6                                                0x0
7783
7784                 DRAM DQ VREF Select for Rank0
7785                 PSU_DDR_PHY_DX0GCR6_DXDQVREFR0                                                  0x2b
7786
7787                 DATX8 n General Configuration Register 6
7788                 (OFFSET, MASK, VALUE)      (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU)
7789                 RegMask = (DDR_PHY_DX0GCR6_RESERVED_31_30_MASK | DDR_PHY_DX0GCR6_DXDQVREFR3_MASK | DDR_PHY_DX0GCR6_RESERVED_23_22_MASK | DDR_PHY_DX0GCR6_DXDQVREFR2_MASK | DDR_PHY_DX0GCR6_RESERVED_15_14_MASK | DDR_PHY_DX0GCR6_DXDQVREFR1_MASK | DDR_PHY_DX0GCR6_RESERVED_7_6_MASK | DDR_PHY_DX0GCR6_DXDQVREFR0_MASK |  0 );
7790
7791                 RegVal = ((0x00000000U << DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT
7792                         | 0x00000009U << DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT
7793                         | 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT
7794                         | 0x00000009U << DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT
7795                         | 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT
7796                         | 0x0000002BU << DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT
7797                         | 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT
7798                         | 0x0000002BU << DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT
7799                         |  0 ) & RegMask); */
7800                 PSU_Mask_Write (DDR_PHY_DX0GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
7801         /*############################################################################################################################ */
7802
7803                 /*Register : DX0LCDLR2 @ 0XFD080788</p>
7804
7805                 Reserved. Return zeroes on reads.
7806                 PSU_DDR_PHY_DX0LCDLR2_RESERVED_31_25                                            0x0
7807
7808                 Reserved. Caution, do not write to this register field.
7809                 PSU_DDR_PHY_DX0LCDLR2_RESERVED_24_16                                            0x0
7810
7811                 Reserved. Return zeroes on reads.
7812                 PSU_DDR_PHY_DX0LCDLR2_RESERVED_15_9                                             0x0
7813
7814                 Read DQS Gating Delay
7815                 PSU_DDR_PHY_DX0LCDLR2_DQSGD                                                     0x0
7816
7817                 DATX8 n Local Calibrated Delay Line Register 2
7818                 (OFFSET, MASK, VALUE)      (0XFD080788, 0xFFFFFFFFU ,0x00000000U)
7819                 RegMask = (DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX0LCDLR2_DQSGD_MASK |  0 );
7820
7821                 RegVal = ((0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT
7822                         | 0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT
7823                         | 0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT
7824                         | 0x00000000U << DDR_PHY_DX0LCDLR2_DQSGD_SHIFT
7825                         |  0 ) & RegMask); */
7826                 PSU_Mask_Write (DDR_PHY_DX0LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
7827         /*############################################################################################################################ */
7828
7829                 /*Register : DX0GTR0 @ 0XFD0807C0</p>
7830
7831                 Reserved. Return zeroes on reads.
7832                 PSU_DDR_PHY_DX0GTR0_RESERVED_31_24                                              0x0
7833
7834                 DQ Write Path Latency Pipeline
7835                 PSU_DDR_PHY_DX0GTR0_WDQSL                                                       0x0
7836
7837                 Reserved. Caution, do not write to this register field.
7838                 PSU_DDR_PHY_DX0GTR0_RESERVED_23_20                                              0x0
7839
7840                 Write Leveling System Latency
7841                 PSU_DDR_PHY_DX0GTR0_WLSL                                                        0x2
7842
7843                 Reserved. Return zeroes on reads.
7844                 PSU_DDR_PHY_DX0GTR0_RESERVED_15_13                                              0x0
7845
7846                 Reserved. Caution, do not write to this register field.
7847                 PSU_DDR_PHY_DX0GTR0_RESERVED_12_8                                               0x0
7848
7849                 Reserved. Return zeroes on reads.
7850                 PSU_DDR_PHY_DX0GTR0_RESERVED_7_5                                                0x0
7851
7852                 DQS Gating System Latency
7853                 PSU_DDR_PHY_DX0GTR0_DGSL                                                        0x0
7854
7855                 DATX8 n General Timing Register 0
7856                 (OFFSET, MASK, VALUE)      (0XFD0807C0, 0xFFFFFFFFU ,0x00020000U)
7857                 RegMask = (DDR_PHY_DX0GTR0_RESERVED_31_24_MASK | DDR_PHY_DX0GTR0_WDQSL_MASK | DDR_PHY_DX0GTR0_RESERVED_23_20_MASK | DDR_PHY_DX0GTR0_WLSL_MASK | DDR_PHY_DX0GTR0_RESERVED_15_13_MASK | DDR_PHY_DX0GTR0_RESERVED_12_8_MASK | DDR_PHY_DX0GTR0_RESERVED_7_5_MASK | DDR_PHY_DX0GTR0_DGSL_MASK |  0 );
7858
7859                 RegVal = ((0x00000000U << DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT
7860                         | 0x00000000U << DDR_PHY_DX0GTR0_WDQSL_SHIFT
7861                         | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT
7862                         | 0x00000002U << DDR_PHY_DX0GTR0_WLSL_SHIFT
7863                         | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT
7864                         | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT
7865                         | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT
7866                         | 0x00000000U << DDR_PHY_DX0GTR0_DGSL_SHIFT
7867                         |  0 ) & RegMask); */
7868                 PSU_Mask_Write (DDR_PHY_DX0GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
7869         /*############################################################################################################################ */
7870
7871                 /*Register : DX1GCR0 @ 0XFD080800</p>
7872
7873                 Calibration Bypass
7874                 PSU_DDR_PHY_DX1GCR0_CALBYP                                                      0x0
7875
7876                 Master Delay Line Enable
7877                 PSU_DDR_PHY_DX1GCR0_MDLEN                                                       0x1
7878
7879                 Configurable ODT(TE) Phase Shift
7880                 PSU_DDR_PHY_DX1GCR0_CODTSHFT                                                    0x0
7881
7882                 DQS Duty Cycle Correction
7883                 PSU_DDR_PHY_DX1GCR0_DQSDCC                                                      0x0
7884
7885                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
7886                 PSU_DDR_PHY_DX1GCR0_RDDLY                                                       0x8
7887
7888                 Reserved. Return zeroes on reads.
7889                 PSU_DDR_PHY_DX1GCR0_RESERVED_19_14                                              0x0
7890
7891                 DQSNSE Power Down Receiver
7892                 PSU_DDR_PHY_DX1GCR0_DQSNSEPDR                                                   0x0
7893
7894                 DQSSE Power Down Receiver
7895                 PSU_DDR_PHY_DX1GCR0_DQSSEPDR                                                    0x0
7896
7897                 RTT On Additive Latency
7898                 PSU_DDR_PHY_DX1GCR0_RTTOAL                                                      0x0
7899
7900                 RTT Output Hold
7901                 PSU_DDR_PHY_DX1GCR0_RTTOH                                                       0x3
7902
7903                 Configurable PDR Phase Shift
7904                 PSU_DDR_PHY_DX1GCR0_CPDRSHFT                                                    0x0
7905
7906                 DQSR Power Down
7907                 PSU_DDR_PHY_DX1GCR0_DQSRPD                                                      0x0
7908
7909                 DQSG Power Down Receiver
7910                 PSU_DDR_PHY_DX1GCR0_DQSGPDR                                                     0x0
7911
7912                 Reserved. Return zeroes on reads.
7913                 PSU_DDR_PHY_DX1GCR0_RESERVED_4                                                  0x0
7914
7915                 DQSG On-Die Termination
7916                 PSU_DDR_PHY_DX1GCR0_DQSGODT                                                     0x0
7917
7918                 DQSG Output Enable
7919                 PSU_DDR_PHY_DX1GCR0_DQSGOE                                                      0x1
7920
7921                 Reserved. Return zeroes on reads.
7922                 PSU_DDR_PHY_DX1GCR0_RESERVED_1_0                                                0x0
7923
7924                 DATX8 n General Configuration Register 0
7925                 (OFFSET, MASK, VALUE)      (0XFD080800, 0xFFFFFFFFU ,0x40800604U)
7926                 RegMask = (DDR_PHY_DX1GCR0_CALBYP_MASK | DDR_PHY_DX1GCR0_MDLEN_MASK | DDR_PHY_DX1GCR0_CODTSHFT_MASK | DDR_PHY_DX1GCR0_DQSDCC_MASK | DDR_PHY_DX1GCR0_RDDLY_MASK | DDR_PHY_DX1GCR0_RESERVED_19_14_MASK | DDR_PHY_DX1GCR0_DQSNSEPDR_MASK | DDR_PHY_DX1GCR0_DQSSEPDR_MASK | DDR_PHY_DX1GCR0_RTTOAL_MASK | DDR_PHY_DX1GCR0_RTTOH_MASK | DDR_PHY_DX1GCR0_CPDRSHFT_MASK | DDR_PHY_DX1GCR0_DQSRPD_MASK | DDR_PHY_DX1GCR0_DQSGPDR_MASK | DDR_PHY_DX1GCR0_RESERVED_4_MASK | DDR_PHY_DX1GCR0_DQSGODT_MASK | DDR_PHY_DX1GCR0_DQSGOE_MASK | DDR_PHY_DX1GCR0_RESERVED_1_0_MASK |  0 );
7927
7928                 RegVal = ((0x00000000U << DDR_PHY_DX1GCR0_CALBYP_SHIFT
7929                         | 0x00000001U << DDR_PHY_DX1GCR0_MDLEN_SHIFT
7930                         | 0x00000000U << DDR_PHY_DX1GCR0_CODTSHFT_SHIFT
7931                         | 0x00000000U << DDR_PHY_DX1GCR0_DQSDCC_SHIFT
7932                         | 0x00000008U << DDR_PHY_DX1GCR0_RDDLY_SHIFT
7933                         | 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT
7934                         | 0x00000000U << DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT
7935                         | 0x00000000U << DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT
7936                         | 0x00000000U << DDR_PHY_DX1GCR0_RTTOAL_SHIFT
7937                         | 0x00000003U << DDR_PHY_DX1GCR0_RTTOH_SHIFT
7938                         | 0x00000000U << DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT
7939                         | 0x00000000U << DDR_PHY_DX1GCR0_DQSRPD_SHIFT
7940                         | 0x00000000U << DDR_PHY_DX1GCR0_DQSGPDR_SHIFT
7941                         | 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_4_SHIFT
7942                         | 0x00000000U << DDR_PHY_DX1GCR0_DQSGODT_SHIFT
7943                         | 0x00000001U << DDR_PHY_DX1GCR0_DQSGOE_SHIFT
7944                         | 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT
7945                         |  0 ) & RegMask); */
7946                 PSU_Mask_Write (DDR_PHY_DX1GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
7947         /*############################################################################################################################ */
7948
7949                 /*Register : DX1GCR4 @ 0XFD080810</p>
7950
7951                 Byte lane VREF IOM (Used only by D4MU IOs)
7952                 PSU_DDR_PHY_DX1GCR4_RESERVED_31_29                                              0x0
7953
7954                 Byte Lane VREF Pad Enable
7955                 PSU_DDR_PHY_DX1GCR4_DXREFPEN                                                    0x0
7956
7957                 Byte Lane Internal VREF Enable
7958                 PSU_DDR_PHY_DX1GCR4_DXREFEEN                                                    0x3
7959
7960                 Byte Lane Single-End VREF Enable
7961                 PSU_DDR_PHY_DX1GCR4_DXREFSEN                                                    0x1
7962
7963                 Reserved. Returns zeros on reads.
7964                 PSU_DDR_PHY_DX1GCR4_RESERVED_24                                                 0x0
7965
7966                 External VREF generator REFSEL range select
7967                 PSU_DDR_PHY_DX1GCR4_DXREFESELRANGE                                              0x0
7968
7969                 Byte Lane External VREF Select
7970                 PSU_DDR_PHY_DX1GCR4_DXREFESEL                                                   0x0
7971
7972                 Single ended VREF generator REFSEL range select
7973                 PSU_DDR_PHY_DX1GCR4_DXREFSSELRANGE                                              0x1
7974
7975                 Byte Lane Single-End VREF Select
7976                 PSU_DDR_PHY_DX1GCR4_DXREFSSEL                                                   0x30
7977
7978                 Reserved. Returns zeros on reads.
7979                 PSU_DDR_PHY_DX1GCR4_RESERVED_7_6                                                0x0
7980
7981                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
7982                 PSU_DDR_PHY_DX1GCR4_DXREFIEN                                                    0xf
7983
7984                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
7985                 PSU_DDR_PHY_DX1GCR4_DXREFIMON                                                   0x0
7986
7987                 DATX8 n General Configuration Register 4
7988                 (OFFSET, MASK, VALUE)      (0XFD080810, 0xFFFFFFFFU ,0x0E00B03CU)
7989                 RegMask = (DDR_PHY_DX1GCR4_RESERVED_31_29_MASK | DDR_PHY_DX1GCR4_DXREFPEN_MASK | DDR_PHY_DX1GCR4_DXREFEEN_MASK | DDR_PHY_DX1GCR4_DXREFSEN_MASK | DDR_PHY_DX1GCR4_RESERVED_24_MASK | DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX1GCR4_DXREFESEL_MASK | DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX1GCR4_DXREFSSEL_MASK | DDR_PHY_DX1GCR4_RESERVED_7_6_MASK | DDR_PHY_DX1GCR4_DXREFIEN_MASK | DDR_PHY_DX1GCR4_DXREFIMON_MASK |  0 );
7990
7991                 RegVal = ((0x00000000U << DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT
7992                         | 0x00000000U << DDR_PHY_DX1GCR4_DXREFPEN_SHIFT
7993                         | 0x00000003U << DDR_PHY_DX1GCR4_DXREFEEN_SHIFT
7994                         | 0x00000001U << DDR_PHY_DX1GCR4_DXREFSEN_SHIFT
7995                         | 0x00000000U << DDR_PHY_DX1GCR4_RESERVED_24_SHIFT
7996                         | 0x00000000U << DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT
7997                         | 0x00000000U << DDR_PHY_DX1GCR4_DXREFESEL_SHIFT
7998                         | 0x00000001U << DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT
7999                         | 0x00000030U << DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT
8000                         | 0x00000000U << DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT
8001                         | 0x0000000FU << DDR_PHY_DX1GCR4_DXREFIEN_SHIFT
8002                         | 0x00000000U << DDR_PHY_DX1GCR4_DXREFIMON_SHIFT
8003                         |  0 ) & RegMask); */
8004                 PSU_Mask_Write (DDR_PHY_DX1GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
8005         /*############################################################################################################################ */
8006
8007                 /*Register : DX1GCR5 @ 0XFD080814</p>
8008
8009                 Reserved. Returns zeros on reads.
8010                 PSU_DDR_PHY_DX1GCR5_RESERVED_31                                                 0x0
8011
8012                 Byte Lane internal VREF Select for Rank 3
8013                 PSU_DDR_PHY_DX1GCR5_DXREFISELR3                                                 0x9
8014
8015                 Reserved. Returns zeros on reads.
8016                 PSU_DDR_PHY_DX1GCR5_RESERVED_23                                                 0x0
8017
8018                 Byte Lane internal VREF Select for Rank 2
8019                 PSU_DDR_PHY_DX1GCR5_DXREFISELR2                                                 0x9
8020
8021                 Reserved. Returns zeros on reads.
8022                 PSU_DDR_PHY_DX1GCR5_RESERVED_15                                                 0x0
8023
8024                 Byte Lane internal VREF Select for Rank 1
8025                 PSU_DDR_PHY_DX1GCR5_DXREFISELR1                                                 0x4f
8026
8027                 Reserved. Returns zeros on reads.
8028                 PSU_DDR_PHY_DX1GCR5_RESERVED_7                                                  0x0
8029
8030                 Byte Lane internal VREF Select for Rank 0
8031                 PSU_DDR_PHY_DX1GCR5_DXREFISELR0                                                 0x4f
8032
8033                 DATX8 n General Configuration Register 5
8034                 (OFFSET, MASK, VALUE)      (0XFD080814, 0xFFFFFFFFU ,0x09094F4FU)
8035                 RegMask = (DDR_PHY_DX1GCR5_RESERVED_31_MASK | DDR_PHY_DX1GCR5_DXREFISELR3_MASK | DDR_PHY_DX1GCR5_RESERVED_23_MASK | DDR_PHY_DX1GCR5_DXREFISELR2_MASK | DDR_PHY_DX1GCR5_RESERVED_15_MASK | DDR_PHY_DX1GCR5_DXREFISELR1_MASK | DDR_PHY_DX1GCR5_RESERVED_7_MASK | DDR_PHY_DX1GCR5_DXREFISELR0_MASK |  0 );
8036
8037                 RegVal = ((0x00000000U << DDR_PHY_DX1GCR5_RESERVED_31_SHIFT
8038                         | 0x00000009U << DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT
8039                         | 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_23_SHIFT
8040                         | 0x00000009U << DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT
8041                         | 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_15_SHIFT
8042                         | 0x0000004FU << DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT
8043                         | 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_7_SHIFT
8044                         | 0x0000004FU << DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT
8045                         |  0 ) & RegMask); */
8046                 PSU_Mask_Write (DDR_PHY_DX1GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
8047         /*############################################################################################################################ */
8048
8049                 /*Register : DX1GCR6 @ 0XFD080818</p>
8050
8051                 Reserved. Returns zeros on reads.
8052                 PSU_DDR_PHY_DX1GCR6_RESERVED_31_30                                              0x0
8053
8054                 DRAM DQ VREF Select for Rank3
8055                 PSU_DDR_PHY_DX1GCR6_DXDQVREFR3                                                  0x9
8056
8057                 Reserved. Returns zeros on reads.
8058                 PSU_DDR_PHY_DX1GCR6_RESERVED_23_22                                              0x0
8059
8060                 DRAM DQ VREF Select for Rank2
8061                 PSU_DDR_PHY_DX1GCR6_DXDQVREFR2                                                  0x9
8062
8063                 Reserved. Returns zeros on reads.
8064                 PSU_DDR_PHY_DX1GCR6_RESERVED_15_14                                              0x0
8065
8066                 DRAM DQ VREF Select for Rank1
8067                 PSU_DDR_PHY_DX1GCR6_DXDQVREFR1                                                  0x2b
8068
8069                 Reserved. Returns zeros on reads.
8070                 PSU_DDR_PHY_DX1GCR6_RESERVED_7_6                                                0x0
8071
8072                 DRAM DQ VREF Select for Rank0
8073                 PSU_DDR_PHY_DX1GCR6_DXDQVREFR0                                                  0x2b
8074
8075                 DATX8 n General Configuration Register 6
8076                 (OFFSET, MASK, VALUE)      (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU)
8077                 RegMask = (DDR_PHY_DX1GCR6_RESERVED_31_30_MASK | DDR_PHY_DX1GCR6_DXDQVREFR3_MASK | DDR_PHY_DX1GCR6_RESERVED_23_22_MASK | DDR_PHY_DX1GCR6_DXDQVREFR2_MASK | DDR_PHY_DX1GCR6_RESERVED_15_14_MASK | DDR_PHY_DX1GCR6_DXDQVREFR1_MASK | DDR_PHY_DX1GCR6_RESERVED_7_6_MASK | DDR_PHY_DX1GCR6_DXDQVREFR0_MASK |  0 );
8078
8079                 RegVal = ((0x00000000U << DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT
8080                         | 0x00000009U << DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT
8081                         | 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT
8082                         | 0x00000009U << DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT
8083                         | 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT
8084                         | 0x0000002BU << DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT
8085                         | 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT
8086                         | 0x0000002BU << DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT
8087                         |  0 ) & RegMask); */
8088                 PSU_Mask_Write (DDR_PHY_DX1GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
8089         /*############################################################################################################################ */
8090
8091                 /*Register : DX1LCDLR2 @ 0XFD080888</p>
8092
8093                 Reserved. Return zeroes on reads.
8094                 PSU_DDR_PHY_DX1LCDLR2_RESERVED_31_25                                            0x0
8095
8096                 Reserved. Caution, do not write to this register field.
8097                 PSU_DDR_PHY_DX1LCDLR2_RESERVED_24_16                                            0x0
8098
8099                 Reserved. Return zeroes on reads.
8100                 PSU_DDR_PHY_DX1LCDLR2_RESERVED_15_9                                             0x0
8101
8102                 Read DQS Gating Delay
8103                 PSU_DDR_PHY_DX1LCDLR2_DQSGD                                                     0x0
8104
8105                 DATX8 n Local Calibrated Delay Line Register 2
8106                 (OFFSET, MASK, VALUE)      (0XFD080888, 0xFFFFFFFFU ,0x00000000U)
8107                 RegMask = (DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX1LCDLR2_DQSGD_MASK |  0 );
8108
8109                 RegVal = ((0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT
8110                         | 0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT
8111                         | 0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT
8112                         | 0x00000000U << DDR_PHY_DX1LCDLR2_DQSGD_SHIFT
8113                         |  0 ) & RegMask); */
8114                 PSU_Mask_Write (DDR_PHY_DX1LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
8115         /*############################################################################################################################ */
8116
8117                 /*Register : DX1GTR0 @ 0XFD0808C0</p>
8118
8119                 Reserved. Return zeroes on reads.
8120                 PSU_DDR_PHY_DX1GTR0_RESERVED_31_24                                              0x0
8121
8122                 DQ Write Path Latency Pipeline
8123                 PSU_DDR_PHY_DX1GTR0_WDQSL                                                       0x0
8124
8125                 Reserved. Caution, do not write to this register field.
8126                 PSU_DDR_PHY_DX1GTR0_RESERVED_23_20                                              0x0
8127
8128                 Write Leveling System Latency
8129                 PSU_DDR_PHY_DX1GTR0_WLSL                                                        0x2
8130
8131                 Reserved. Return zeroes on reads.
8132                 PSU_DDR_PHY_DX1GTR0_RESERVED_15_13                                              0x0
8133
8134                 Reserved. Caution, do not write to this register field.
8135                 PSU_DDR_PHY_DX1GTR0_RESERVED_12_8                                               0x0
8136
8137                 Reserved. Return zeroes on reads.
8138                 PSU_DDR_PHY_DX1GTR0_RESERVED_7_5                                                0x0
8139
8140                 DQS Gating System Latency
8141                 PSU_DDR_PHY_DX1GTR0_DGSL                                                        0x0
8142
8143                 DATX8 n General Timing Register 0
8144                 (OFFSET, MASK, VALUE)      (0XFD0808C0, 0xFFFFFFFFU ,0x00020000U)
8145                 RegMask = (DDR_PHY_DX1GTR0_RESERVED_31_24_MASK | DDR_PHY_DX1GTR0_WDQSL_MASK | DDR_PHY_DX1GTR0_RESERVED_23_20_MASK | DDR_PHY_DX1GTR0_WLSL_MASK | DDR_PHY_DX1GTR0_RESERVED_15_13_MASK | DDR_PHY_DX1GTR0_RESERVED_12_8_MASK | DDR_PHY_DX1GTR0_RESERVED_7_5_MASK | DDR_PHY_DX1GTR0_DGSL_MASK |  0 );
8146
8147                 RegVal = ((0x00000000U << DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT
8148                         | 0x00000000U << DDR_PHY_DX1GTR0_WDQSL_SHIFT
8149                         | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT
8150                         | 0x00000002U << DDR_PHY_DX1GTR0_WLSL_SHIFT
8151                         | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT
8152                         | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT
8153                         | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT
8154                         | 0x00000000U << DDR_PHY_DX1GTR0_DGSL_SHIFT
8155                         |  0 ) & RegMask); */
8156                 PSU_Mask_Write (DDR_PHY_DX1GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
8157         /*############################################################################################################################ */
8158
8159                 /*Register : DX2GCR0 @ 0XFD080900</p>
8160
8161                 Calibration Bypass
8162                 PSU_DDR_PHY_DX2GCR0_CALBYP                                                      0x0
8163
8164                 Master Delay Line Enable
8165                 PSU_DDR_PHY_DX2GCR0_MDLEN                                                       0x1
8166
8167                 Configurable ODT(TE) Phase Shift
8168                 PSU_DDR_PHY_DX2GCR0_CODTSHFT                                                    0x0
8169
8170                 DQS Duty Cycle Correction
8171                 PSU_DDR_PHY_DX2GCR0_DQSDCC                                                      0x0
8172
8173                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
8174                 PSU_DDR_PHY_DX2GCR0_RDDLY                                                       0x8
8175
8176                 Reserved. Return zeroes on reads.
8177                 PSU_DDR_PHY_DX2GCR0_RESERVED_19_14                                              0x0
8178
8179                 DQSNSE Power Down Receiver
8180                 PSU_DDR_PHY_DX2GCR0_DQSNSEPDR                                                   0x0
8181
8182                 DQSSE Power Down Receiver
8183                 PSU_DDR_PHY_DX2GCR0_DQSSEPDR                                                    0x0
8184
8185                 RTT On Additive Latency
8186                 PSU_DDR_PHY_DX2GCR0_RTTOAL                                                      0x0
8187
8188                 RTT Output Hold
8189                 PSU_DDR_PHY_DX2GCR0_RTTOH                                                       0x3
8190
8191                 Configurable PDR Phase Shift
8192                 PSU_DDR_PHY_DX2GCR0_CPDRSHFT                                                    0x0
8193
8194                 DQSR Power Down
8195                 PSU_DDR_PHY_DX2GCR0_DQSRPD                                                      0x0
8196
8197                 DQSG Power Down Receiver
8198                 PSU_DDR_PHY_DX2GCR0_DQSGPDR                                                     0x0
8199
8200                 Reserved. Return zeroes on reads.
8201                 PSU_DDR_PHY_DX2GCR0_RESERVED_4                                                  0x0
8202
8203                 DQSG On-Die Termination
8204                 PSU_DDR_PHY_DX2GCR0_DQSGODT                                                     0x0
8205
8206                 DQSG Output Enable
8207                 PSU_DDR_PHY_DX2GCR0_DQSGOE                                                      0x1
8208
8209                 Reserved. Return zeroes on reads.
8210                 PSU_DDR_PHY_DX2GCR0_RESERVED_1_0                                                0x0
8211
8212                 DATX8 n General Configuration Register 0
8213                 (OFFSET, MASK, VALUE)      (0XFD080900, 0xFFFFFFFFU ,0x40800604U)
8214                 RegMask = (DDR_PHY_DX2GCR0_CALBYP_MASK | DDR_PHY_DX2GCR0_MDLEN_MASK | DDR_PHY_DX2GCR0_CODTSHFT_MASK | DDR_PHY_DX2GCR0_DQSDCC_MASK | DDR_PHY_DX2GCR0_RDDLY_MASK | DDR_PHY_DX2GCR0_RESERVED_19_14_MASK | DDR_PHY_DX2GCR0_DQSNSEPDR_MASK | DDR_PHY_DX2GCR0_DQSSEPDR_MASK | DDR_PHY_DX2GCR0_RTTOAL_MASK | DDR_PHY_DX2GCR0_RTTOH_MASK | DDR_PHY_DX2GCR0_CPDRSHFT_MASK | DDR_PHY_DX2GCR0_DQSRPD_MASK | DDR_PHY_DX2GCR0_DQSGPDR_MASK | DDR_PHY_DX2GCR0_RESERVED_4_MASK | DDR_PHY_DX2GCR0_DQSGODT_MASK | DDR_PHY_DX2GCR0_DQSGOE_MASK | DDR_PHY_DX2GCR0_RESERVED_1_0_MASK |  0 );
8215
8216                 RegVal = ((0x00000000U << DDR_PHY_DX2GCR0_CALBYP_SHIFT
8217                         | 0x00000001U << DDR_PHY_DX2GCR0_MDLEN_SHIFT
8218                         | 0x00000000U << DDR_PHY_DX2GCR0_CODTSHFT_SHIFT
8219                         | 0x00000000U << DDR_PHY_DX2GCR0_DQSDCC_SHIFT
8220                         | 0x00000008U << DDR_PHY_DX2GCR0_RDDLY_SHIFT
8221                         | 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT
8222                         | 0x00000000U << DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT
8223                         | 0x00000000U << DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT
8224                         | 0x00000000U << DDR_PHY_DX2GCR0_RTTOAL_SHIFT
8225                         | 0x00000003U << DDR_PHY_DX2GCR0_RTTOH_SHIFT
8226                         | 0x00000000U << DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT
8227                         | 0x00000000U << DDR_PHY_DX2GCR0_DQSRPD_SHIFT
8228                         | 0x00000000U << DDR_PHY_DX2GCR0_DQSGPDR_SHIFT
8229                         | 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_4_SHIFT
8230                         | 0x00000000U << DDR_PHY_DX2GCR0_DQSGODT_SHIFT
8231                         | 0x00000001U << DDR_PHY_DX2GCR0_DQSGOE_SHIFT
8232                         | 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT
8233                         |  0 ) & RegMask); */
8234                 PSU_Mask_Write (DDR_PHY_DX2GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
8235         /*############################################################################################################################ */
8236
8237                 /*Register : DX2GCR1 @ 0XFD080904</p>
8238
8239                 Enables the PDR mode for DQ[7:0]
8240                 PSU_DDR_PHY_DX2GCR1_DXPDRMODE                                                   0x0
8241
8242                 Reserved. Returns zeroes on reads.
8243                 PSU_DDR_PHY_DX2GCR1_RESERVED_15                                                 0x0
8244
8245                 Select the delayed or non-delayed read data strobe #
8246                 PSU_DDR_PHY_DX2GCR1_QSNSEL                                                      0x1
8247
8248                 Select the delayed or non-delayed read data strobe
8249                 PSU_DDR_PHY_DX2GCR1_QSSEL                                                       0x1
8250
8251                 Enables Read Data Strobe in a byte lane
8252                 PSU_DDR_PHY_DX2GCR1_OEEN                                                        0x1
8253
8254                 Enables PDR in a byte lane
8255                 PSU_DDR_PHY_DX2GCR1_PDREN                                                       0x1
8256
8257                 Enables ODT/TE in a byte lane
8258                 PSU_DDR_PHY_DX2GCR1_TEEN                                                        0x1
8259
8260                 Enables Write Data strobe in a byte lane
8261                 PSU_DDR_PHY_DX2GCR1_DSEN                                                        0x1
8262
8263                 Enables DM pin in a byte lane
8264                 PSU_DDR_PHY_DX2GCR1_DMEN                                                        0x1
8265
8266                 Enables DQ corresponding to each bit in a byte
8267                 PSU_DDR_PHY_DX2GCR1_DQEN                                                        0xff
8268
8269                 DATX8 n General Configuration Register 1
8270                 (OFFSET, MASK, VALUE)      (0XFD080904, 0xFFFFFFFFU ,0x00007FFFU)
8271                 RegMask = (DDR_PHY_DX2GCR1_DXPDRMODE_MASK | DDR_PHY_DX2GCR1_RESERVED_15_MASK | DDR_PHY_DX2GCR1_QSNSEL_MASK | DDR_PHY_DX2GCR1_QSSEL_MASK | DDR_PHY_DX2GCR1_OEEN_MASK | DDR_PHY_DX2GCR1_PDREN_MASK | DDR_PHY_DX2GCR1_TEEN_MASK | DDR_PHY_DX2GCR1_DSEN_MASK | DDR_PHY_DX2GCR1_DMEN_MASK | DDR_PHY_DX2GCR1_DQEN_MASK |  0 );
8272
8273                 RegVal = ((0x00000000U << DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT
8274                         | 0x00000000U << DDR_PHY_DX2GCR1_RESERVED_15_SHIFT
8275                         | 0x00000001U << DDR_PHY_DX2GCR1_QSNSEL_SHIFT
8276                         | 0x00000001U << DDR_PHY_DX2GCR1_QSSEL_SHIFT
8277                         | 0x00000001U << DDR_PHY_DX2GCR1_OEEN_SHIFT
8278                         | 0x00000001U << DDR_PHY_DX2GCR1_PDREN_SHIFT
8279                         | 0x00000001U << DDR_PHY_DX2GCR1_TEEN_SHIFT
8280                         | 0x00000001U << DDR_PHY_DX2GCR1_DSEN_SHIFT
8281                         | 0x00000001U << DDR_PHY_DX2GCR1_DMEN_SHIFT
8282                         | 0x000000FFU << DDR_PHY_DX2GCR1_DQEN_SHIFT
8283                         |  0 ) & RegMask); */
8284                 PSU_Mask_Write (DDR_PHY_DX2GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
8285         /*############################################################################################################################ */
8286
8287                 /*Register : DX2GCR4 @ 0XFD080910</p>
8288
8289                 Byte lane VREF IOM (Used only by D4MU IOs)
8290                 PSU_DDR_PHY_DX2GCR4_RESERVED_31_29                                              0x0
8291
8292                 Byte Lane VREF Pad Enable
8293                 PSU_DDR_PHY_DX2GCR4_DXREFPEN                                                    0x0
8294
8295                 Byte Lane Internal VREF Enable
8296                 PSU_DDR_PHY_DX2GCR4_DXREFEEN                                                    0x3
8297
8298                 Byte Lane Single-End VREF Enable
8299                 PSU_DDR_PHY_DX2GCR4_DXREFSEN                                                    0x1
8300
8301                 Reserved. Returns zeros on reads.
8302                 PSU_DDR_PHY_DX2GCR4_RESERVED_24                                                 0x0
8303
8304                 External VREF generator REFSEL range select
8305                 PSU_DDR_PHY_DX2GCR4_DXREFESELRANGE                                              0x0
8306
8307                 Byte Lane External VREF Select
8308                 PSU_DDR_PHY_DX2GCR4_DXREFESEL                                                   0x0
8309
8310                 Single ended VREF generator REFSEL range select
8311                 PSU_DDR_PHY_DX2GCR4_DXREFSSELRANGE                                              0x1
8312
8313                 Byte Lane Single-End VREF Select
8314                 PSU_DDR_PHY_DX2GCR4_DXREFSSEL                                                   0x30
8315
8316                 Reserved. Returns zeros on reads.
8317                 PSU_DDR_PHY_DX2GCR4_RESERVED_7_6                                                0x0
8318
8319                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
8320                 PSU_DDR_PHY_DX2GCR4_DXREFIEN                                                    0xf
8321
8322                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
8323                 PSU_DDR_PHY_DX2GCR4_DXREFIMON                                                   0x0
8324
8325                 DATX8 n General Configuration Register 4
8326                 (OFFSET, MASK, VALUE)      (0XFD080910, 0xFFFFFFFFU ,0x0E00B03CU)
8327                 RegMask = (DDR_PHY_DX2GCR4_RESERVED_31_29_MASK | DDR_PHY_DX2GCR4_DXREFPEN_MASK | DDR_PHY_DX2GCR4_DXREFEEN_MASK | DDR_PHY_DX2GCR4_DXREFSEN_MASK | DDR_PHY_DX2GCR4_RESERVED_24_MASK | DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX2GCR4_DXREFESEL_MASK | DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX2GCR4_DXREFSSEL_MASK | DDR_PHY_DX2GCR4_RESERVED_7_6_MASK | DDR_PHY_DX2GCR4_DXREFIEN_MASK | DDR_PHY_DX2GCR4_DXREFIMON_MASK |  0 );
8328
8329                 RegVal = ((0x00000000U << DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT
8330                         | 0x00000000U << DDR_PHY_DX2GCR4_DXREFPEN_SHIFT
8331                         | 0x00000003U << DDR_PHY_DX2GCR4_DXREFEEN_SHIFT
8332                         | 0x00000001U << DDR_PHY_DX2GCR4_DXREFSEN_SHIFT
8333                         | 0x00000000U << DDR_PHY_DX2GCR4_RESERVED_24_SHIFT
8334                         | 0x00000000U << DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT
8335                         | 0x00000000U << DDR_PHY_DX2GCR4_DXREFESEL_SHIFT
8336                         | 0x00000001U << DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT
8337                         | 0x00000030U << DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT
8338                         | 0x00000000U << DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT
8339                         | 0x0000000FU << DDR_PHY_DX2GCR4_DXREFIEN_SHIFT
8340                         | 0x00000000U << DDR_PHY_DX2GCR4_DXREFIMON_SHIFT
8341                         |  0 ) & RegMask); */
8342                 PSU_Mask_Write (DDR_PHY_DX2GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
8343         /*############################################################################################################################ */
8344
8345                 /*Register : DX2GCR5 @ 0XFD080914</p>
8346
8347                 Reserved. Returns zeros on reads.
8348                 PSU_DDR_PHY_DX2GCR5_RESERVED_31                                                 0x0
8349
8350                 Byte Lane internal VREF Select for Rank 3
8351                 PSU_DDR_PHY_DX2GCR5_DXREFISELR3                                                 0x9
8352
8353                 Reserved. Returns zeros on reads.
8354                 PSU_DDR_PHY_DX2GCR5_RESERVED_23                                                 0x0
8355
8356                 Byte Lane internal VREF Select for Rank 2
8357                 PSU_DDR_PHY_DX2GCR5_DXREFISELR2                                                 0x9
8358
8359                 Reserved. Returns zeros on reads.
8360                 PSU_DDR_PHY_DX2GCR5_RESERVED_15                                                 0x0
8361
8362                 Byte Lane internal VREF Select for Rank 1
8363                 PSU_DDR_PHY_DX2GCR5_DXREFISELR1                                                 0x4f
8364
8365                 Reserved. Returns zeros on reads.
8366                 PSU_DDR_PHY_DX2GCR5_RESERVED_7                                                  0x0
8367
8368                 Byte Lane internal VREF Select for Rank 0
8369                 PSU_DDR_PHY_DX2GCR5_DXREFISELR0                                                 0x4f
8370
8371                 DATX8 n General Configuration Register 5
8372                 (OFFSET, MASK, VALUE)      (0XFD080914, 0xFFFFFFFFU ,0x09094F4FU)
8373                 RegMask = (DDR_PHY_DX2GCR5_RESERVED_31_MASK | DDR_PHY_DX2GCR5_DXREFISELR3_MASK | DDR_PHY_DX2GCR5_RESERVED_23_MASK | DDR_PHY_DX2GCR5_DXREFISELR2_MASK | DDR_PHY_DX2GCR5_RESERVED_15_MASK | DDR_PHY_DX2GCR5_DXREFISELR1_MASK | DDR_PHY_DX2GCR5_RESERVED_7_MASK | DDR_PHY_DX2GCR5_DXREFISELR0_MASK |  0 );
8374
8375                 RegVal = ((0x00000000U << DDR_PHY_DX2GCR5_RESERVED_31_SHIFT
8376                         | 0x00000009U << DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT
8377                         | 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_23_SHIFT
8378                         | 0x00000009U << DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT
8379                         | 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_15_SHIFT
8380                         | 0x0000004FU << DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT
8381                         | 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_7_SHIFT
8382                         | 0x0000004FU << DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT
8383                         |  0 ) & RegMask); */
8384                 PSU_Mask_Write (DDR_PHY_DX2GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
8385         /*############################################################################################################################ */
8386
8387                 /*Register : DX2GCR6 @ 0XFD080918</p>
8388
8389                 Reserved. Returns zeros on reads.
8390                 PSU_DDR_PHY_DX2GCR6_RESERVED_31_30                                              0x0
8391
8392                 DRAM DQ VREF Select for Rank3
8393                 PSU_DDR_PHY_DX2GCR6_DXDQVREFR3                                                  0x9
8394
8395                 Reserved. Returns zeros on reads.
8396                 PSU_DDR_PHY_DX2GCR6_RESERVED_23_22                                              0x0
8397
8398                 DRAM DQ VREF Select for Rank2
8399                 PSU_DDR_PHY_DX2GCR6_DXDQVREFR2                                                  0x9
8400
8401                 Reserved. Returns zeros on reads.
8402                 PSU_DDR_PHY_DX2GCR6_RESERVED_15_14                                              0x0
8403
8404                 DRAM DQ VREF Select for Rank1
8405                 PSU_DDR_PHY_DX2GCR6_DXDQVREFR1                                                  0x2b
8406
8407                 Reserved. Returns zeros on reads.
8408                 PSU_DDR_PHY_DX2GCR6_RESERVED_7_6                                                0x0
8409
8410                 DRAM DQ VREF Select for Rank0
8411                 PSU_DDR_PHY_DX2GCR6_DXDQVREFR0                                                  0x2b
8412
8413                 DATX8 n General Configuration Register 6
8414                 (OFFSET, MASK, VALUE)      (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU)
8415                 RegMask = (DDR_PHY_DX2GCR6_RESERVED_31_30_MASK | DDR_PHY_DX2GCR6_DXDQVREFR3_MASK | DDR_PHY_DX2GCR6_RESERVED_23_22_MASK | DDR_PHY_DX2GCR6_DXDQVREFR2_MASK | DDR_PHY_DX2GCR6_RESERVED_15_14_MASK | DDR_PHY_DX2GCR6_DXDQVREFR1_MASK | DDR_PHY_DX2GCR6_RESERVED_7_6_MASK | DDR_PHY_DX2GCR6_DXDQVREFR0_MASK |  0 );
8416
8417                 RegVal = ((0x00000000U << DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT
8418                         | 0x00000009U << DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT
8419                         | 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT
8420                         | 0x00000009U << DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT
8421                         | 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT
8422                         | 0x0000002BU << DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT
8423                         | 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT
8424                         | 0x0000002BU << DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT
8425                         |  0 ) & RegMask); */
8426                 PSU_Mask_Write (DDR_PHY_DX2GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
8427         /*############################################################################################################################ */
8428
8429                 /*Register : DX2LCDLR2 @ 0XFD080988</p>
8430
8431                 Reserved. Return zeroes on reads.
8432                 PSU_DDR_PHY_DX2LCDLR2_RESERVED_31_25                                            0x0
8433
8434                 Reserved. Caution, do not write to this register field.
8435                 PSU_DDR_PHY_DX2LCDLR2_RESERVED_24_16                                            0x0
8436
8437                 Reserved. Return zeroes on reads.
8438                 PSU_DDR_PHY_DX2LCDLR2_RESERVED_15_9                                             0x0
8439
8440                 Read DQS Gating Delay
8441                 PSU_DDR_PHY_DX2LCDLR2_DQSGD                                                     0x0
8442
8443                 DATX8 n Local Calibrated Delay Line Register 2
8444                 (OFFSET, MASK, VALUE)      (0XFD080988, 0xFFFFFFFFU ,0x00000000U)
8445                 RegMask = (DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX2LCDLR2_DQSGD_MASK |  0 );
8446
8447                 RegVal = ((0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT
8448                         | 0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT
8449                         | 0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT
8450                         | 0x00000000U << DDR_PHY_DX2LCDLR2_DQSGD_SHIFT
8451                         |  0 ) & RegMask); */
8452                 PSU_Mask_Write (DDR_PHY_DX2LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
8453         /*############################################################################################################################ */
8454
8455                 /*Register : DX2GTR0 @ 0XFD0809C0</p>
8456
8457                 Reserved. Return zeroes on reads.
8458                 PSU_DDR_PHY_DX2GTR0_RESERVED_31_24                                              0x0
8459
8460                 DQ Write Path Latency Pipeline
8461                 PSU_DDR_PHY_DX2GTR0_WDQSL                                                       0x0
8462
8463                 Reserved. Caution, do not write to this register field.
8464                 PSU_DDR_PHY_DX2GTR0_RESERVED_23_20                                              0x0
8465
8466                 Write Leveling System Latency
8467                 PSU_DDR_PHY_DX2GTR0_WLSL                                                        0x2
8468
8469                 Reserved. Return zeroes on reads.
8470                 PSU_DDR_PHY_DX2GTR0_RESERVED_15_13                                              0x0
8471
8472                 Reserved. Caution, do not write to this register field.
8473                 PSU_DDR_PHY_DX2GTR0_RESERVED_12_8                                               0x0
8474
8475                 Reserved. Return zeroes on reads.
8476                 PSU_DDR_PHY_DX2GTR0_RESERVED_7_5                                                0x0
8477
8478                 DQS Gating System Latency
8479                 PSU_DDR_PHY_DX2GTR0_DGSL                                                        0x0
8480
8481                 DATX8 n General Timing Register 0
8482                 (OFFSET, MASK, VALUE)      (0XFD0809C0, 0xFFFFFFFFU ,0x00020000U)
8483                 RegMask = (DDR_PHY_DX2GTR0_RESERVED_31_24_MASK | DDR_PHY_DX2GTR0_WDQSL_MASK | DDR_PHY_DX2GTR0_RESERVED_23_20_MASK | DDR_PHY_DX2GTR0_WLSL_MASK | DDR_PHY_DX2GTR0_RESERVED_15_13_MASK | DDR_PHY_DX2GTR0_RESERVED_12_8_MASK | DDR_PHY_DX2GTR0_RESERVED_7_5_MASK | DDR_PHY_DX2GTR0_DGSL_MASK |  0 );
8484
8485                 RegVal = ((0x00000000U << DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT
8486                         | 0x00000000U << DDR_PHY_DX2GTR0_WDQSL_SHIFT
8487                         | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT
8488                         | 0x00000002U << DDR_PHY_DX2GTR0_WLSL_SHIFT
8489                         | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT
8490                         | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT
8491                         | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT
8492                         | 0x00000000U << DDR_PHY_DX2GTR0_DGSL_SHIFT
8493                         |  0 ) & RegMask); */
8494                 PSU_Mask_Write (DDR_PHY_DX2GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
8495         /*############################################################################################################################ */
8496
8497                 /*Register : DX3GCR0 @ 0XFD080A00</p>
8498
8499                 Calibration Bypass
8500                 PSU_DDR_PHY_DX3GCR0_CALBYP                                                      0x0
8501
8502                 Master Delay Line Enable
8503                 PSU_DDR_PHY_DX3GCR0_MDLEN                                                       0x1
8504
8505                 Configurable ODT(TE) Phase Shift
8506                 PSU_DDR_PHY_DX3GCR0_CODTSHFT                                                    0x0
8507
8508                 DQS Duty Cycle Correction
8509                 PSU_DDR_PHY_DX3GCR0_DQSDCC                                                      0x0
8510
8511                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
8512                 PSU_DDR_PHY_DX3GCR0_RDDLY                                                       0x8
8513
8514                 Reserved. Return zeroes on reads.
8515                 PSU_DDR_PHY_DX3GCR0_RESERVED_19_14                                              0x0
8516
8517                 DQSNSE Power Down Receiver
8518                 PSU_DDR_PHY_DX3GCR0_DQSNSEPDR                                                   0x0
8519
8520                 DQSSE Power Down Receiver
8521                 PSU_DDR_PHY_DX3GCR0_DQSSEPDR                                                    0x0
8522
8523                 RTT On Additive Latency
8524                 PSU_DDR_PHY_DX3GCR0_RTTOAL                                                      0x0
8525
8526                 RTT Output Hold
8527                 PSU_DDR_PHY_DX3GCR0_RTTOH                                                       0x3
8528
8529                 Configurable PDR Phase Shift
8530                 PSU_DDR_PHY_DX3GCR0_CPDRSHFT                                                    0x0
8531
8532                 DQSR Power Down
8533                 PSU_DDR_PHY_DX3GCR0_DQSRPD                                                      0x0
8534
8535                 DQSG Power Down Receiver
8536                 PSU_DDR_PHY_DX3GCR0_DQSGPDR                                                     0x0
8537
8538                 Reserved. Return zeroes on reads.
8539                 PSU_DDR_PHY_DX3GCR0_RESERVED_4                                                  0x0
8540
8541                 DQSG On-Die Termination
8542                 PSU_DDR_PHY_DX3GCR0_DQSGODT                                                     0x0
8543
8544                 DQSG Output Enable
8545                 PSU_DDR_PHY_DX3GCR0_DQSGOE                                                      0x1
8546
8547                 Reserved. Return zeroes on reads.
8548                 PSU_DDR_PHY_DX3GCR0_RESERVED_1_0                                                0x0
8549
8550                 DATX8 n General Configuration Register 0
8551                 (OFFSET, MASK, VALUE)      (0XFD080A00, 0xFFFFFFFFU ,0x40800604U)
8552                 RegMask = (DDR_PHY_DX3GCR0_CALBYP_MASK | DDR_PHY_DX3GCR0_MDLEN_MASK | DDR_PHY_DX3GCR0_CODTSHFT_MASK | DDR_PHY_DX3GCR0_DQSDCC_MASK | DDR_PHY_DX3GCR0_RDDLY_MASK | DDR_PHY_DX3GCR0_RESERVED_19_14_MASK | DDR_PHY_DX3GCR0_DQSNSEPDR_MASK | DDR_PHY_DX3GCR0_DQSSEPDR_MASK | DDR_PHY_DX3GCR0_RTTOAL_MASK | DDR_PHY_DX3GCR0_RTTOH_MASK | DDR_PHY_DX3GCR0_CPDRSHFT_MASK | DDR_PHY_DX3GCR0_DQSRPD_MASK | DDR_PHY_DX3GCR0_DQSGPDR_MASK | DDR_PHY_DX3GCR0_RESERVED_4_MASK | DDR_PHY_DX3GCR0_DQSGODT_MASK | DDR_PHY_DX3GCR0_DQSGOE_MASK | DDR_PHY_DX3GCR0_RESERVED_1_0_MASK |  0 );
8553
8554                 RegVal = ((0x00000000U << DDR_PHY_DX3GCR0_CALBYP_SHIFT
8555                         | 0x00000001U << DDR_PHY_DX3GCR0_MDLEN_SHIFT
8556                         | 0x00000000U << DDR_PHY_DX3GCR0_CODTSHFT_SHIFT
8557                         | 0x00000000U << DDR_PHY_DX3GCR0_DQSDCC_SHIFT
8558                         | 0x00000008U << DDR_PHY_DX3GCR0_RDDLY_SHIFT
8559                         | 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT
8560                         | 0x00000000U << DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT
8561                         | 0x00000000U << DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT
8562                         | 0x00000000U << DDR_PHY_DX3GCR0_RTTOAL_SHIFT
8563                         | 0x00000003U << DDR_PHY_DX3GCR0_RTTOH_SHIFT
8564                         | 0x00000000U << DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT
8565                         | 0x00000000U << DDR_PHY_DX3GCR0_DQSRPD_SHIFT
8566                         | 0x00000000U << DDR_PHY_DX3GCR0_DQSGPDR_SHIFT
8567                         | 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_4_SHIFT
8568                         | 0x00000000U << DDR_PHY_DX3GCR0_DQSGODT_SHIFT
8569                         | 0x00000001U << DDR_PHY_DX3GCR0_DQSGOE_SHIFT
8570                         | 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT
8571                         |  0 ) & RegMask); */
8572                 PSU_Mask_Write (DDR_PHY_DX3GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
8573         /*############################################################################################################################ */
8574
8575                 /*Register : DX3GCR1 @ 0XFD080A04</p>
8576
8577                 Enables the PDR mode for DQ[7:0]
8578                 PSU_DDR_PHY_DX3GCR1_DXPDRMODE                                                   0x0
8579
8580                 Reserved. Returns zeroes on reads.
8581                 PSU_DDR_PHY_DX3GCR1_RESERVED_15                                                 0x0
8582
8583                 Select the delayed or non-delayed read data strobe #
8584                 PSU_DDR_PHY_DX3GCR1_QSNSEL                                                      0x1
8585
8586                 Select the delayed or non-delayed read data strobe
8587                 PSU_DDR_PHY_DX3GCR1_QSSEL                                                       0x1
8588
8589                 Enables Read Data Strobe in a byte lane
8590                 PSU_DDR_PHY_DX3GCR1_OEEN                                                        0x1
8591
8592                 Enables PDR in a byte lane
8593                 PSU_DDR_PHY_DX3GCR1_PDREN                                                       0x1
8594
8595                 Enables ODT/TE in a byte lane
8596                 PSU_DDR_PHY_DX3GCR1_TEEN                                                        0x1
8597
8598                 Enables Write Data strobe in a byte lane
8599                 PSU_DDR_PHY_DX3GCR1_DSEN                                                        0x1
8600
8601                 Enables DM pin in a byte lane
8602                 PSU_DDR_PHY_DX3GCR1_DMEN                                                        0x1
8603
8604                 Enables DQ corresponding to each bit in a byte
8605                 PSU_DDR_PHY_DX3GCR1_DQEN                                                        0xff
8606
8607                 DATX8 n General Configuration Register 1
8608                 (OFFSET, MASK, VALUE)      (0XFD080A04, 0xFFFFFFFFU ,0x00007FFFU)
8609                 RegMask = (DDR_PHY_DX3GCR1_DXPDRMODE_MASK | DDR_PHY_DX3GCR1_RESERVED_15_MASK | DDR_PHY_DX3GCR1_QSNSEL_MASK | DDR_PHY_DX3GCR1_QSSEL_MASK | DDR_PHY_DX3GCR1_OEEN_MASK | DDR_PHY_DX3GCR1_PDREN_MASK | DDR_PHY_DX3GCR1_TEEN_MASK | DDR_PHY_DX3GCR1_DSEN_MASK | DDR_PHY_DX3GCR1_DMEN_MASK | DDR_PHY_DX3GCR1_DQEN_MASK |  0 );
8610
8611                 RegVal = ((0x00000000U << DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT
8612                         | 0x00000000U << DDR_PHY_DX3GCR1_RESERVED_15_SHIFT
8613                         | 0x00000001U << DDR_PHY_DX3GCR1_QSNSEL_SHIFT
8614                         | 0x00000001U << DDR_PHY_DX3GCR1_QSSEL_SHIFT
8615                         | 0x00000001U << DDR_PHY_DX3GCR1_OEEN_SHIFT
8616                         | 0x00000001U << DDR_PHY_DX3GCR1_PDREN_SHIFT
8617                         | 0x00000001U << DDR_PHY_DX3GCR1_TEEN_SHIFT
8618                         | 0x00000001U << DDR_PHY_DX3GCR1_DSEN_SHIFT
8619                         | 0x00000001U << DDR_PHY_DX3GCR1_DMEN_SHIFT
8620                         | 0x000000FFU << DDR_PHY_DX3GCR1_DQEN_SHIFT
8621                         |  0 ) & RegMask); */
8622                 PSU_Mask_Write (DDR_PHY_DX3GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
8623         /*############################################################################################################################ */
8624
8625                 /*Register : DX3GCR4 @ 0XFD080A10</p>
8626
8627                 Byte lane VREF IOM (Used only by D4MU IOs)
8628                 PSU_DDR_PHY_DX3GCR4_RESERVED_31_29                                              0x0
8629
8630                 Byte Lane VREF Pad Enable
8631                 PSU_DDR_PHY_DX3GCR4_DXREFPEN                                                    0x0
8632
8633                 Byte Lane Internal VREF Enable
8634                 PSU_DDR_PHY_DX3GCR4_DXREFEEN                                                    0x3
8635
8636                 Byte Lane Single-End VREF Enable
8637                 PSU_DDR_PHY_DX3GCR4_DXREFSEN                                                    0x1
8638
8639                 Reserved. Returns zeros on reads.
8640                 PSU_DDR_PHY_DX3GCR4_RESERVED_24                                                 0x0
8641
8642                 External VREF generator REFSEL range select
8643                 PSU_DDR_PHY_DX3GCR4_DXREFESELRANGE                                              0x0
8644
8645                 Byte Lane External VREF Select
8646                 PSU_DDR_PHY_DX3GCR4_DXREFESEL                                                   0x0
8647
8648                 Single ended VREF generator REFSEL range select
8649                 PSU_DDR_PHY_DX3GCR4_DXREFSSELRANGE                                              0x1
8650
8651                 Byte Lane Single-End VREF Select
8652                 PSU_DDR_PHY_DX3GCR4_DXREFSSEL                                                   0x30
8653
8654                 Reserved. Returns zeros on reads.
8655                 PSU_DDR_PHY_DX3GCR4_RESERVED_7_6                                                0x0
8656
8657                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
8658                 PSU_DDR_PHY_DX3GCR4_DXREFIEN                                                    0xf
8659
8660                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
8661                 PSU_DDR_PHY_DX3GCR4_DXREFIMON                                                   0x0
8662
8663                 DATX8 n General Configuration Register 4
8664                 (OFFSET, MASK, VALUE)      (0XFD080A10, 0xFFFFFFFFU ,0x0E00B03CU)
8665                 RegMask = (DDR_PHY_DX3GCR4_RESERVED_31_29_MASK | DDR_PHY_DX3GCR4_DXREFPEN_MASK | DDR_PHY_DX3GCR4_DXREFEEN_MASK | DDR_PHY_DX3GCR4_DXREFSEN_MASK | DDR_PHY_DX3GCR4_RESERVED_24_MASK | DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX3GCR4_DXREFESEL_MASK | DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX3GCR4_DXREFSSEL_MASK | DDR_PHY_DX3GCR4_RESERVED_7_6_MASK | DDR_PHY_DX3GCR4_DXREFIEN_MASK | DDR_PHY_DX3GCR4_DXREFIMON_MASK |  0 );
8666
8667                 RegVal = ((0x00000000U << DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT
8668                         | 0x00000000U << DDR_PHY_DX3GCR4_DXREFPEN_SHIFT
8669                         | 0x00000003U << DDR_PHY_DX3GCR4_DXREFEEN_SHIFT
8670                         | 0x00000001U << DDR_PHY_DX3GCR4_DXREFSEN_SHIFT
8671                         | 0x00000000U << DDR_PHY_DX3GCR4_RESERVED_24_SHIFT
8672                         | 0x00000000U << DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT
8673                         | 0x00000000U << DDR_PHY_DX3GCR4_DXREFESEL_SHIFT
8674                         | 0x00000001U << DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT
8675                         | 0x00000030U << DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT
8676                         | 0x00000000U << DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT
8677                         | 0x0000000FU << DDR_PHY_DX3GCR4_DXREFIEN_SHIFT
8678                         | 0x00000000U << DDR_PHY_DX3GCR4_DXREFIMON_SHIFT
8679                         |  0 ) & RegMask); */
8680                 PSU_Mask_Write (DDR_PHY_DX3GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
8681         /*############################################################################################################################ */
8682
8683                 /*Register : DX3GCR5 @ 0XFD080A14</p>
8684
8685                 Reserved. Returns zeros on reads.
8686                 PSU_DDR_PHY_DX3GCR5_RESERVED_31                                                 0x0
8687
8688                 Byte Lane internal VREF Select for Rank 3
8689                 PSU_DDR_PHY_DX3GCR5_DXREFISELR3                                                 0x9
8690
8691                 Reserved. Returns zeros on reads.
8692                 PSU_DDR_PHY_DX3GCR5_RESERVED_23                                                 0x0
8693
8694                 Byte Lane internal VREF Select for Rank 2
8695                 PSU_DDR_PHY_DX3GCR5_DXREFISELR2                                                 0x9
8696
8697                 Reserved. Returns zeros on reads.
8698                 PSU_DDR_PHY_DX3GCR5_RESERVED_15                                                 0x0
8699
8700                 Byte Lane internal VREF Select for Rank 1
8701                 PSU_DDR_PHY_DX3GCR5_DXREFISELR1                                                 0x4f
8702
8703                 Reserved. Returns zeros on reads.
8704                 PSU_DDR_PHY_DX3GCR5_RESERVED_7                                                  0x0
8705
8706                 Byte Lane internal VREF Select for Rank 0
8707                 PSU_DDR_PHY_DX3GCR5_DXREFISELR0                                                 0x4f
8708
8709                 DATX8 n General Configuration Register 5
8710                 (OFFSET, MASK, VALUE)      (0XFD080A14, 0xFFFFFFFFU ,0x09094F4FU)
8711                 RegMask = (DDR_PHY_DX3GCR5_RESERVED_31_MASK | DDR_PHY_DX3GCR5_DXREFISELR3_MASK | DDR_PHY_DX3GCR5_RESERVED_23_MASK | DDR_PHY_DX3GCR5_DXREFISELR2_MASK | DDR_PHY_DX3GCR5_RESERVED_15_MASK | DDR_PHY_DX3GCR5_DXREFISELR1_MASK | DDR_PHY_DX3GCR5_RESERVED_7_MASK | DDR_PHY_DX3GCR5_DXREFISELR0_MASK |  0 );
8712
8713                 RegVal = ((0x00000000U << DDR_PHY_DX3GCR5_RESERVED_31_SHIFT
8714                         | 0x00000009U << DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT
8715                         | 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_23_SHIFT
8716                         | 0x00000009U << DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT
8717                         | 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_15_SHIFT
8718                         | 0x0000004FU << DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT
8719                         | 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_7_SHIFT
8720                         | 0x0000004FU << DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT
8721                         |  0 ) & RegMask); */
8722                 PSU_Mask_Write (DDR_PHY_DX3GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
8723         /*############################################################################################################################ */
8724
8725                 /*Register : DX3GCR6 @ 0XFD080A18</p>
8726
8727                 Reserved. Returns zeros on reads.
8728                 PSU_DDR_PHY_DX3GCR6_RESERVED_31_30                                              0x0
8729
8730                 DRAM DQ VREF Select for Rank3
8731                 PSU_DDR_PHY_DX3GCR6_DXDQVREFR3                                                  0x9
8732
8733                 Reserved. Returns zeros on reads.
8734                 PSU_DDR_PHY_DX3GCR6_RESERVED_23_22                                              0x0
8735
8736                 DRAM DQ VREF Select for Rank2
8737                 PSU_DDR_PHY_DX3GCR6_DXDQVREFR2                                                  0x9
8738
8739                 Reserved. Returns zeros on reads.
8740                 PSU_DDR_PHY_DX3GCR6_RESERVED_15_14                                              0x0
8741
8742                 DRAM DQ VREF Select for Rank1
8743                 PSU_DDR_PHY_DX3GCR6_DXDQVREFR1                                                  0x2b
8744
8745                 Reserved. Returns zeros on reads.
8746                 PSU_DDR_PHY_DX3GCR6_RESERVED_7_6                                                0x0
8747
8748                 DRAM DQ VREF Select for Rank0
8749                 PSU_DDR_PHY_DX3GCR6_DXDQVREFR0                                                  0x2b
8750
8751                 DATX8 n General Configuration Register 6
8752                 (OFFSET, MASK, VALUE)      (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU)
8753                 RegMask = (DDR_PHY_DX3GCR6_RESERVED_31_30_MASK | DDR_PHY_DX3GCR6_DXDQVREFR3_MASK | DDR_PHY_DX3GCR6_RESERVED_23_22_MASK | DDR_PHY_DX3GCR6_DXDQVREFR2_MASK | DDR_PHY_DX3GCR6_RESERVED_15_14_MASK | DDR_PHY_DX3GCR6_DXDQVREFR1_MASK | DDR_PHY_DX3GCR6_RESERVED_7_6_MASK | DDR_PHY_DX3GCR6_DXDQVREFR0_MASK |  0 );
8754
8755                 RegVal = ((0x00000000U << DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT
8756                         | 0x00000009U << DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT
8757                         | 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT
8758                         | 0x00000009U << DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT
8759                         | 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT
8760                         | 0x0000002BU << DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT
8761                         | 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT
8762                         | 0x0000002BU << DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT
8763                         |  0 ) & RegMask); */
8764                 PSU_Mask_Write (DDR_PHY_DX3GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
8765         /*############################################################################################################################ */
8766
8767                 /*Register : DX3LCDLR2 @ 0XFD080A88</p>
8768
8769                 Reserved. Return zeroes on reads.
8770                 PSU_DDR_PHY_DX3LCDLR2_RESERVED_31_25                                            0x0
8771
8772                 Reserved. Caution, do not write to this register field.
8773                 PSU_DDR_PHY_DX3LCDLR2_RESERVED_24_16                                            0x0
8774
8775                 Reserved. Return zeroes on reads.
8776                 PSU_DDR_PHY_DX3LCDLR2_RESERVED_15_9                                             0x0
8777
8778                 Read DQS Gating Delay
8779                 PSU_DDR_PHY_DX3LCDLR2_DQSGD                                                     0x0
8780
8781                 DATX8 n Local Calibrated Delay Line Register 2
8782                 (OFFSET, MASK, VALUE)      (0XFD080A88, 0xFFFFFFFFU ,0x00000000U)
8783                 RegMask = (DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX3LCDLR2_DQSGD_MASK |  0 );
8784
8785                 RegVal = ((0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT
8786                         | 0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT
8787                         | 0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT
8788                         | 0x00000000U << DDR_PHY_DX3LCDLR2_DQSGD_SHIFT
8789                         |  0 ) & RegMask); */
8790                 PSU_Mask_Write (DDR_PHY_DX3LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
8791         /*############################################################################################################################ */
8792
8793                 /*Register : DX3GTR0 @ 0XFD080AC0</p>
8794
8795                 Reserved. Return zeroes on reads.
8796                 PSU_DDR_PHY_DX3GTR0_RESERVED_31_24                                              0x0
8797
8798                 DQ Write Path Latency Pipeline
8799                 PSU_DDR_PHY_DX3GTR0_WDQSL                                                       0x0
8800
8801                 Reserved. Caution, do not write to this register field.
8802                 PSU_DDR_PHY_DX3GTR0_RESERVED_23_20                                              0x0
8803
8804                 Write Leveling System Latency
8805                 PSU_DDR_PHY_DX3GTR0_WLSL                                                        0x2
8806
8807                 Reserved. Return zeroes on reads.
8808                 PSU_DDR_PHY_DX3GTR0_RESERVED_15_13                                              0x0
8809
8810                 Reserved. Caution, do not write to this register field.
8811                 PSU_DDR_PHY_DX3GTR0_RESERVED_12_8                                               0x0
8812
8813                 Reserved. Return zeroes on reads.
8814                 PSU_DDR_PHY_DX3GTR0_RESERVED_7_5                                                0x0
8815
8816                 DQS Gating System Latency
8817                 PSU_DDR_PHY_DX3GTR0_DGSL                                                        0x0
8818
8819                 DATX8 n General Timing Register 0
8820                 (OFFSET, MASK, VALUE)      (0XFD080AC0, 0xFFFFFFFFU ,0x00020000U)
8821                 RegMask = (DDR_PHY_DX3GTR0_RESERVED_31_24_MASK | DDR_PHY_DX3GTR0_WDQSL_MASK | DDR_PHY_DX3GTR0_RESERVED_23_20_MASK | DDR_PHY_DX3GTR0_WLSL_MASK | DDR_PHY_DX3GTR0_RESERVED_15_13_MASK | DDR_PHY_DX3GTR0_RESERVED_12_8_MASK | DDR_PHY_DX3GTR0_RESERVED_7_5_MASK | DDR_PHY_DX3GTR0_DGSL_MASK |  0 );
8822
8823                 RegVal = ((0x00000000U << DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT
8824                         | 0x00000000U << DDR_PHY_DX3GTR0_WDQSL_SHIFT
8825                         | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT
8826                         | 0x00000002U << DDR_PHY_DX3GTR0_WLSL_SHIFT
8827                         | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT
8828                         | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT
8829                         | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT
8830                         | 0x00000000U << DDR_PHY_DX3GTR0_DGSL_SHIFT
8831                         |  0 ) & RegMask); */
8832                 PSU_Mask_Write (DDR_PHY_DX3GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
8833         /*############################################################################################################################ */
8834
8835                 /*Register : DX4GCR0 @ 0XFD080B00</p>
8836
8837                 Calibration Bypass
8838                 PSU_DDR_PHY_DX4GCR0_CALBYP                                                      0x0
8839
8840                 Master Delay Line Enable
8841                 PSU_DDR_PHY_DX4GCR0_MDLEN                                                       0x1
8842
8843                 Configurable ODT(TE) Phase Shift
8844                 PSU_DDR_PHY_DX4GCR0_CODTSHFT                                                    0x0
8845
8846                 DQS Duty Cycle Correction
8847                 PSU_DDR_PHY_DX4GCR0_DQSDCC                                                      0x0
8848
8849                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
8850                 PSU_DDR_PHY_DX4GCR0_RDDLY                                                       0x8
8851
8852                 Reserved. Return zeroes on reads.
8853                 PSU_DDR_PHY_DX4GCR0_RESERVED_19_14                                              0x0
8854
8855                 DQSNSE Power Down Receiver
8856                 PSU_DDR_PHY_DX4GCR0_DQSNSEPDR                                                   0x0
8857
8858                 DQSSE Power Down Receiver
8859                 PSU_DDR_PHY_DX4GCR0_DQSSEPDR                                                    0x0
8860
8861                 RTT On Additive Latency
8862                 PSU_DDR_PHY_DX4GCR0_RTTOAL                                                      0x0
8863
8864                 RTT Output Hold
8865                 PSU_DDR_PHY_DX4GCR0_RTTOH                                                       0x3
8866
8867                 Configurable PDR Phase Shift
8868                 PSU_DDR_PHY_DX4GCR0_CPDRSHFT                                                    0x0
8869
8870                 DQSR Power Down
8871                 PSU_DDR_PHY_DX4GCR0_DQSRPD                                                      0x0
8872
8873                 DQSG Power Down Receiver
8874                 PSU_DDR_PHY_DX4GCR0_DQSGPDR                                                     0x0
8875
8876                 Reserved. Return zeroes on reads.
8877                 PSU_DDR_PHY_DX4GCR0_RESERVED_4                                                  0x0
8878
8879                 DQSG On-Die Termination
8880                 PSU_DDR_PHY_DX4GCR0_DQSGODT                                                     0x0
8881
8882                 DQSG Output Enable
8883                 PSU_DDR_PHY_DX4GCR0_DQSGOE                                                      0x1
8884
8885                 Reserved. Return zeroes on reads.
8886                 PSU_DDR_PHY_DX4GCR0_RESERVED_1_0                                                0x0
8887
8888                 DATX8 n General Configuration Register 0
8889                 (OFFSET, MASK, VALUE)      (0XFD080B00, 0xFFFFFFFFU ,0x40800604U)
8890                 RegMask = (DDR_PHY_DX4GCR0_CALBYP_MASK | DDR_PHY_DX4GCR0_MDLEN_MASK | DDR_PHY_DX4GCR0_CODTSHFT_MASK | DDR_PHY_DX4GCR0_DQSDCC_MASK | DDR_PHY_DX4GCR0_RDDLY_MASK | DDR_PHY_DX4GCR0_RESERVED_19_14_MASK | DDR_PHY_DX4GCR0_DQSNSEPDR_MASK | DDR_PHY_DX4GCR0_DQSSEPDR_MASK | DDR_PHY_DX4GCR0_RTTOAL_MASK | DDR_PHY_DX4GCR0_RTTOH_MASK | DDR_PHY_DX4GCR0_CPDRSHFT_MASK | DDR_PHY_DX4GCR0_DQSRPD_MASK | DDR_PHY_DX4GCR0_DQSGPDR_MASK | DDR_PHY_DX4GCR0_RESERVED_4_MASK | DDR_PHY_DX4GCR0_DQSGODT_MASK | DDR_PHY_DX4GCR0_DQSGOE_MASK | DDR_PHY_DX4GCR0_RESERVED_1_0_MASK |  0 );
8891
8892                 RegVal = ((0x00000000U << DDR_PHY_DX4GCR0_CALBYP_SHIFT
8893                         | 0x00000001U << DDR_PHY_DX4GCR0_MDLEN_SHIFT
8894                         | 0x00000000U << DDR_PHY_DX4GCR0_CODTSHFT_SHIFT
8895                         | 0x00000000U << DDR_PHY_DX4GCR0_DQSDCC_SHIFT
8896                         | 0x00000008U << DDR_PHY_DX4GCR0_RDDLY_SHIFT
8897                         | 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT
8898                         | 0x00000000U << DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT
8899                         | 0x00000000U << DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT
8900                         | 0x00000000U << DDR_PHY_DX4GCR0_RTTOAL_SHIFT
8901                         | 0x00000003U << DDR_PHY_DX4GCR0_RTTOH_SHIFT
8902                         | 0x00000000U << DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT
8903                         | 0x00000000U << DDR_PHY_DX4GCR0_DQSRPD_SHIFT
8904                         | 0x00000000U << DDR_PHY_DX4GCR0_DQSGPDR_SHIFT
8905                         | 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_4_SHIFT
8906                         | 0x00000000U << DDR_PHY_DX4GCR0_DQSGODT_SHIFT
8907                         | 0x00000001U << DDR_PHY_DX4GCR0_DQSGOE_SHIFT
8908                         | 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT
8909                         |  0 ) & RegMask); */
8910                 PSU_Mask_Write (DDR_PHY_DX4GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
8911         /*############################################################################################################################ */
8912
8913                 /*Register : DX4GCR1 @ 0XFD080B04</p>
8914
8915                 Enables the PDR mode for DQ[7:0]
8916                 PSU_DDR_PHY_DX4GCR1_DXPDRMODE                                                   0x0
8917
8918                 Reserved. Returns zeroes on reads.
8919                 PSU_DDR_PHY_DX4GCR1_RESERVED_15                                                 0x0
8920
8921                 Select the delayed or non-delayed read data strobe #
8922                 PSU_DDR_PHY_DX4GCR1_QSNSEL                                                      0x1
8923
8924                 Select the delayed or non-delayed read data strobe
8925                 PSU_DDR_PHY_DX4GCR1_QSSEL                                                       0x1
8926
8927                 Enables Read Data Strobe in a byte lane
8928                 PSU_DDR_PHY_DX4GCR1_OEEN                                                        0x1
8929
8930                 Enables PDR in a byte lane
8931                 PSU_DDR_PHY_DX4GCR1_PDREN                                                       0x1
8932
8933                 Enables ODT/TE in a byte lane
8934                 PSU_DDR_PHY_DX4GCR1_TEEN                                                        0x1
8935
8936                 Enables Write Data strobe in a byte lane
8937                 PSU_DDR_PHY_DX4GCR1_DSEN                                                        0x1
8938
8939                 Enables DM pin in a byte lane
8940                 PSU_DDR_PHY_DX4GCR1_DMEN                                                        0x1
8941
8942                 Enables DQ corresponding to each bit in a byte
8943                 PSU_DDR_PHY_DX4GCR1_DQEN                                                        0xff
8944
8945                 DATX8 n General Configuration Register 1
8946                 (OFFSET, MASK, VALUE)      (0XFD080B04, 0xFFFFFFFFU ,0x00007FFFU)
8947                 RegMask = (DDR_PHY_DX4GCR1_DXPDRMODE_MASK | DDR_PHY_DX4GCR1_RESERVED_15_MASK | DDR_PHY_DX4GCR1_QSNSEL_MASK | DDR_PHY_DX4GCR1_QSSEL_MASK | DDR_PHY_DX4GCR1_OEEN_MASK | DDR_PHY_DX4GCR1_PDREN_MASK | DDR_PHY_DX4GCR1_TEEN_MASK | DDR_PHY_DX4GCR1_DSEN_MASK | DDR_PHY_DX4GCR1_DMEN_MASK | DDR_PHY_DX4GCR1_DQEN_MASK |  0 );
8948
8949                 RegVal = ((0x00000000U << DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT
8950                         | 0x00000000U << DDR_PHY_DX4GCR1_RESERVED_15_SHIFT
8951                         | 0x00000001U << DDR_PHY_DX4GCR1_QSNSEL_SHIFT
8952                         | 0x00000001U << DDR_PHY_DX4GCR1_QSSEL_SHIFT
8953                         | 0x00000001U << DDR_PHY_DX4GCR1_OEEN_SHIFT
8954                         | 0x00000001U << DDR_PHY_DX4GCR1_PDREN_SHIFT
8955                         | 0x00000001U << DDR_PHY_DX4GCR1_TEEN_SHIFT
8956                         | 0x00000001U << DDR_PHY_DX4GCR1_DSEN_SHIFT
8957                         | 0x00000001U << DDR_PHY_DX4GCR1_DMEN_SHIFT
8958                         | 0x000000FFU << DDR_PHY_DX4GCR1_DQEN_SHIFT
8959                         |  0 ) & RegMask); */
8960                 PSU_Mask_Write (DDR_PHY_DX4GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
8961         /*############################################################################################################################ */
8962
8963                 /*Register : DX4GCR4 @ 0XFD080B10</p>
8964
8965                 Byte lane VREF IOM (Used only by D4MU IOs)
8966                 PSU_DDR_PHY_DX4GCR4_RESERVED_31_29                                              0x0
8967
8968                 Byte Lane VREF Pad Enable
8969                 PSU_DDR_PHY_DX4GCR4_DXREFPEN                                                    0x0
8970
8971                 Byte Lane Internal VREF Enable
8972                 PSU_DDR_PHY_DX4GCR4_DXREFEEN                                                    0x3
8973
8974                 Byte Lane Single-End VREF Enable
8975                 PSU_DDR_PHY_DX4GCR4_DXREFSEN                                                    0x1
8976
8977                 Reserved. Returns zeros on reads.
8978                 PSU_DDR_PHY_DX4GCR4_RESERVED_24                                                 0x0
8979
8980                 External VREF generator REFSEL range select
8981                 PSU_DDR_PHY_DX4GCR4_DXREFESELRANGE                                              0x0
8982
8983                 Byte Lane External VREF Select
8984                 PSU_DDR_PHY_DX4GCR4_DXREFESEL                                                   0x0
8985
8986                 Single ended VREF generator REFSEL range select
8987                 PSU_DDR_PHY_DX4GCR4_DXREFSSELRANGE                                              0x1
8988
8989                 Byte Lane Single-End VREF Select
8990                 PSU_DDR_PHY_DX4GCR4_DXREFSSEL                                                   0x30
8991
8992                 Reserved. Returns zeros on reads.
8993                 PSU_DDR_PHY_DX4GCR4_RESERVED_7_6                                                0x0
8994
8995                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
8996                 PSU_DDR_PHY_DX4GCR4_DXREFIEN                                                    0xf
8997
8998                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
8999                 PSU_DDR_PHY_DX4GCR4_DXREFIMON                                                   0x0
9000
9001                 DATX8 n General Configuration Register 4
9002                 (OFFSET, MASK, VALUE)      (0XFD080B10, 0xFFFFFFFFU ,0x0E00B03CU)
9003                 RegMask = (DDR_PHY_DX4GCR4_RESERVED_31_29_MASK | DDR_PHY_DX4GCR4_DXREFPEN_MASK | DDR_PHY_DX4GCR4_DXREFEEN_MASK | DDR_PHY_DX4GCR4_DXREFSEN_MASK | DDR_PHY_DX4GCR4_RESERVED_24_MASK | DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX4GCR4_DXREFESEL_MASK | DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX4GCR4_DXREFSSEL_MASK | DDR_PHY_DX4GCR4_RESERVED_7_6_MASK | DDR_PHY_DX4GCR4_DXREFIEN_MASK | DDR_PHY_DX4GCR4_DXREFIMON_MASK |  0 );
9004
9005                 RegVal = ((0x00000000U << DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT
9006                         | 0x00000000U << DDR_PHY_DX4GCR4_DXREFPEN_SHIFT
9007                         | 0x00000003U << DDR_PHY_DX4GCR4_DXREFEEN_SHIFT
9008                         | 0x00000001U << DDR_PHY_DX4GCR4_DXREFSEN_SHIFT
9009                         | 0x00000000U << DDR_PHY_DX4GCR4_RESERVED_24_SHIFT
9010                         | 0x00000000U << DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT
9011                         | 0x00000000U << DDR_PHY_DX4GCR4_DXREFESEL_SHIFT
9012                         | 0x00000001U << DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT
9013                         | 0x00000030U << DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT
9014                         | 0x00000000U << DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT
9015                         | 0x0000000FU << DDR_PHY_DX4GCR4_DXREFIEN_SHIFT
9016                         | 0x00000000U << DDR_PHY_DX4GCR4_DXREFIMON_SHIFT
9017                         |  0 ) & RegMask); */
9018                 PSU_Mask_Write (DDR_PHY_DX4GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
9019         /*############################################################################################################################ */
9020
9021                 /*Register : DX4GCR5 @ 0XFD080B14</p>
9022
9023                 Reserved. Returns zeros on reads.
9024                 PSU_DDR_PHY_DX4GCR5_RESERVED_31                                                 0x0
9025
9026                 Byte Lane internal VREF Select for Rank 3
9027                 PSU_DDR_PHY_DX4GCR5_DXREFISELR3                                                 0x9
9028
9029                 Reserved. Returns zeros on reads.
9030                 PSU_DDR_PHY_DX4GCR5_RESERVED_23                                                 0x0
9031
9032                 Byte Lane internal VREF Select for Rank 2
9033                 PSU_DDR_PHY_DX4GCR5_DXREFISELR2                                                 0x9
9034
9035                 Reserved. Returns zeros on reads.
9036                 PSU_DDR_PHY_DX4GCR5_RESERVED_15                                                 0x0
9037
9038                 Byte Lane internal VREF Select for Rank 1
9039                 PSU_DDR_PHY_DX4GCR5_DXREFISELR1                                                 0x4f
9040
9041                 Reserved. Returns zeros on reads.
9042                 PSU_DDR_PHY_DX4GCR5_RESERVED_7                                                  0x0
9043
9044                 Byte Lane internal VREF Select for Rank 0
9045                 PSU_DDR_PHY_DX4GCR5_DXREFISELR0                                                 0x4f
9046
9047                 DATX8 n General Configuration Register 5
9048                 (OFFSET, MASK, VALUE)      (0XFD080B14, 0xFFFFFFFFU ,0x09094F4FU)
9049                 RegMask = (DDR_PHY_DX4GCR5_RESERVED_31_MASK | DDR_PHY_DX4GCR5_DXREFISELR3_MASK | DDR_PHY_DX4GCR5_RESERVED_23_MASK | DDR_PHY_DX4GCR5_DXREFISELR2_MASK | DDR_PHY_DX4GCR5_RESERVED_15_MASK | DDR_PHY_DX4GCR5_DXREFISELR1_MASK | DDR_PHY_DX4GCR5_RESERVED_7_MASK | DDR_PHY_DX4GCR5_DXREFISELR0_MASK |  0 );
9050
9051                 RegVal = ((0x00000000U << DDR_PHY_DX4GCR5_RESERVED_31_SHIFT
9052                         | 0x00000009U << DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT
9053                         | 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_23_SHIFT
9054                         | 0x00000009U << DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT
9055                         | 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_15_SHIFT
9056                         | 0x0000004FU << DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT
9057                         | 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_7_SHIFT
9058                         | 0x0000004FU << DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT
9059                         |  0 ) & RegMask); */
9060                 PSU_Mask_Write (DDR_PHY_DX4GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
9061         /*############################################################################################################################ */
9062
9063                 /*Register : DX4GCR6 @ 0XFD080B18</p>
9064
9065                 Reserved. Returns zeros on reads.
9066                 PSU_DDR_PHY_DX4GCR6_RESERVED_31_30                                              0x0
9067
9068                 DRAM DQ VREF Select for Rank3
9069                 PSU_DDR_PHY_DX4GCR6_DXDQVREFR3                                                  0x9
9070
9071                 Reserved. Returns zeros on reads.
9072                 PSU_DDR_PHY_DX4GCR6_RESERVED_23_22                                              0x0
9073
9074                 DRAM DQ VREF Select for Rank2
9075                 PSU_DDR_PHY_DX4GCR6_DXDQVREFR2                                                  0x9
9076
9077                 Reserved. Returns zeros on reads.
9078                 PSU_DDR_PHY_DX4GCR6_RESERVED_15_14                                              0x0
9079
9080                 DRAM DQ VREF Select for Rank1
9081                 PSU_DDR_PHY_DX4GCR6_DXDQVREFR1                                                  0x2b
9082
9083                 Reserved. Returns zeros on reads.
9084                 PSU_DDR_PHY_DX4GCR6_RESERVED_7_6                                                0x0
9085
9086                 DRAM DQ VREF Select for Rank0
9087                 PSU_DDR_PHY_DX4GCR6_DXDQVREFR0                                                  0x2b
9088
9089                 DATX8 n General Configuration Register 6
9090                 (OFFSET, MASK, VALUE)      (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU)
9091                 RegMask = (DDR_PHY_DX4GCR6_RESERVED_31_30_MASK | DDR_PHY_DX4GCR6_DXDQVREFR3_MASK | DDR_PHY_DX4GCR6_RESERVED_23_22_MASK | DDR_PHY_DX4GCR6_DXDQVREFR2_MASK | DDR_PHY_DX4GCR6_RESERVED_15_14_MASK | DDR_PHY_DX4GCR6_DXDQVREFR1_MASK | DDR_PHY_DX4GCR6_RESERVED_7_6_MASK | DDR_PHY_DX4GCR6_DXDQVREFR0_MASK |  0 );
9092
9093                 RegVal = ((0x00000000U << DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT
9094                         | 0x00000009U << DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT
9095                         | 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT
9096                         | 0x00000009U << DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT
9097                         | 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT
9098                         | 0x0000002BU << DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT
9099                         | 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT
9100                         | 0x0000002BU << DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT
9101                         |  0 ) & RegMask); */
9102                 PSU_Mask_Write (DDR_PHY_DX4GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
9103         /*############################################################################################################################ */
9104
9105                 /*Register : DX4LCDLR2 @ 0XFD080B88</p>
9106
9107                 Reserved. Return zeroes on reads.
9108                 PSU_DDR_PHY_DX4LCDLR2_RESERVED_31_25                                            0x0
9109
9110                 Reserved. Caution, do not write to this register field.
9111                 PSU_DDR_PHY_DX4LCDLR2_RESERVED_24_16                                            0x0
9112
9113                 Reserved. Return zeroes on reads.
9114                 PSU_DDR_PHY_DX4LCDLR2_RESERVED_15_9                                             0x0
9115
9116                 Read DQS Gating Delay
9117                 PSU_DDR_PHY_DX4LCDLR2_DQSGD                                                     0x0
9118
9119                 DATX8 n Local Calibrated Delay Line Register 2
9120                 (OFFSET, MASK, VALUE)      (0XFD080B88, 0xFFFFFFFFU ,0x00000000U)
9121                 RegMask = (DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX4LCDLR2_DQSGD_MASK |  0 );
9122
9123                 RegVal = ((0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT
9124                         | 0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT
9125                         | 0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT
9126                         | 0x00000000U << DDR_PHY_DX4LCDLR2_DQSGD_SHIFT
9127                         |  0 ) & RegMask); */
9128                 PSU_Mask_Write (DDR_PHY_DX4LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
9129         /*############################################################################################################################ */
9130
9131                 /*Register : DX4GTR0 @ 0XFD080BC0</p>
9132
9133                 Reserved. Return zeroes on reads.
9134                 PSU_DDR_PHY_DX4GTR0_RESERVED_31_24                                              0x0
9135
9136                 DQ Write Path Latency Pipeline
9137                 PSU_DDR_PHY_DX4GTR0_WDQSL                                                       0x0
9138
9139                 Reserved. Caution, do not write to this register field.
9140                 PSU_DDR_PHY_DX4GTR0_RESERVED_23_20                                              0x0
9141
9142                 Write Leveling System Latency
9143                 PSU_DDR_PHY_DX4GTR0_WLSL                                                        0x2
9144
9145                 Reserved. Return zeroes on reads.
9146                 PSU_DDR_PHY_DX4GTR0_RESERVED_15_13                                              0x0
9147
9148                 Reserved. Caution, do not write to this register field.
9149                 PSU_DDR_PHY_DX4GTR0_RESERVED_12_8                                               0x0
9150
9151                 Reserved. Return zeroes on reads.
9152                 PSU_DDR_PHY_DX4GTR0_RESERVED_7_5                                                0x0
9153
9154                 DQS Gating System Latency
9155                 PSU_DDR_PHY_DX4GTR0_DGSL                                                        0x0
9156
9157                 DATX8 n General Timing Register 0
9158                 (OFFSET, MASK, VALUE)      (0XFD080BC0, 0xFFFFFFFFU ,0x00020000U)
9159                 RegMask = (DDR_PHY_DX4GTR0_RESERVED_31_24_MASK | DDR_PHY_DX4GTR0_WDQSL_MASK | DDR_PHY_DX4GTR0_RESERVED_23_20_MASK | DDR_PHY_DX4GTR0_WLSL_MASK | DDR_PHY_DX4GTR0_RESERVED_15_13_MASK | DDR_PHY_DX4GTR0_RESERVED_12_8_MASK | DDR_PHY_DX4GTR0_RESERVED_7_5_MASK | DDR_PHY_DX4GTR0_DGSL_MASK |  0 );
9160
9161                 RegVal = ((0x00000000U << DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT
9162                         | 0x00000000U << DDR_PHY_DX4GTR0_WDQSL_SHIFT
9163                         | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT
9164                         | 0x00000002U << DDR_PHY_DX4GTR0_WLSL_SHIFT
9165                         | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT
9166                         | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT
9167                         | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT
9168                         | 0x00000000U << DDR_PHY_DX4GTR0_DGSL_SHIFT
9169                         |  0 ) & RegMask); */
9170                 PSU_Mask_Write (DDR_PHY_DX4GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
9171         /*############################################################################################################################ */
9172
9173                 /*Register : DX5GCR0 @ 0XFD080C00</p>
9174
9175                 Calibration Bypass
9176                 PSU_DDR_PHY_DX5GCR0_CALBYP                                                      0x0
9177
9178                 Master Delay Line Enable
9179                 PSU_DDR_PHY_DX5GCR0_MDLEN                                                       0x1
9180
9181                 Configurable ODT(TE) Phase Shift
9182                 PSU_DDR_PHY_DX5GCR0_CODTSHFT                                                    0x0
9183
9184                 DQS Duty Cycle Correction
9185                 PSU_DDR_PHY_DX5GCR0_DQSDCC                                                      0x0
9186
9187                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
9188                 PSU_DDR_PHY_DX5GCR0_RDDLY                                                       0x8
9189
9190                 Reserved. Return zeroes on reads.
9191                 PSU_DDR_PHY_DX5GCR0_RESERVED_19_14                                              0x0
9192
9193                 DQSNSE Power Down Receiver
9194                 PSU_DDR_PHY_DX5GCR0_DQSNSEPDR                                                   0x0
9195
9196                 DQSSE Power Down Receiver
9197                 PSU_DDR_PHY_DX5GCR0_DQSSEPDR                                                    0x0
9198
9199                 RTT On Additive Latency
9200                 PSU_DDR_PHY_DX5GCR0_RTTOAL                                                      0x0
9201
9202                 RTT Output Hold
9203                 PSU_DDR_PHY_DX5GCR0_RTTOH                                                       0x3
9204
9205                 Configurable PDR Phase Shift
9206                 PSU_DDR_PHY_DX5GCR0_CPDRSHFT                                                    0x0
9207
9208                 DQSR Power Down
9209                 PSU_DDR_PHY_DX5GCR0_DQSRPD                                                      0x0
9210
9211                 DQSG Power Down Receiver
9212                 PSU_DDR_PHY_DX5GCR0_DQSGPDR                                                     0x0
9213
9214                 Reserved. Return zeroes on reads.
9215                 PSU_DDR_PHY_DX5GCR0_RESERVED_4                                                  0x0
9216
9217                 DQSG On-Die Termination
9218                 PSU_DDR_PHY_DX5GCR0_DQSGODT                                                     0x0
9219
9220                 DQSG Output Enable
9221                 PSU_DDR_PHY_DX5GCR0_DQSGOE                                                      0x1
9222
9223                 Reserved. Return zeroes on reads.
9224                 PSU_DDR_PHY_DX5GCR0_RESERVED_1_0                                                0x0
9225
9226                 DATX8 n General Configuration Register 0
9227                 (OFFSET, MASK, VALUE)      (0XFD080C00, 0xFFFFFFFFU ,0x40800604U)
9228                 RegMask = (DDR_PHY_DX5GCR0_CALBYP_MASK | DDR_PHY_DX5GCR0_MDLEN_MASK | DDR_PHY_DX5GCR0_CODTSHFT_MASK | DDR_PHY_DX5GCR0_DQSDCC_MASK | DDR_PHY_DX5GCR0_RDDLY_MASK | DDR_PHY_DX5GCR0_RESERVED_19_14_MASK | DDR_PHY_DX5GCR0_DQSNSEPDR_MASK | DDR_PHY_DX5GCR0_DQSSEPDR_MASK | DDR_PHY_DX5GCR0_RTTOAL_MASK | DDR_PHY_DX5GCR0_RTTOH_MASK | DDR_PHY_DX5GCR0_CPDRSHFT_MASK | DDR_PHY_DX5GCR0_DQSRPD_MASK | DDR_PHY_DX5GCR0_DQSGPDR_MASK | DDR_PHY_DX5GCR0_RESERVED_4_MASK | DDR_PHY_DX5GCR0_DQSGODT_MASK | DDR_PHY_DX5GCR0_DQSGOE_MASK | DDR_PHY_DX5GCR0_RESERVED_1_0_MASK |  0 );
9229
9230                 RegVal = ((0x00000000U << DDR_PHY_DX5GCR0_CALBYP_SHIFT
9231                         | 0x00000001U << DDR_PHY_DX5GCR0_MDLEN_SHIFT
9232                         | 0x00000000U << DDR_PHY_DX5GCR0_CODTSHFT_SHIFT
9233                         | 0x00000000U << DDR_PHY_DX5GCR0_DQSDCC_SHIFT
9234                         | 0x00000008U << DDR_PHY_DX5GCR0_RDDLY_SHIFT
9235                         | 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT
9236                         | 0x00000000U << DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT
9237                         | 0x00000000U << DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT
9238                         | 0x00000000U << DDR_PHY_DX5GCR0_RTTOAL_SHIFT
9239                         | 0x00000003U << DDR_PHY_DX5GCR0_RTTOH_SHIFT
9240                         | 0x00000000U << DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT
9241                         | 0x00000000U << DDR_PHY_DX5GCR0_DQSRPD_SHIFT
9242                         | 0x00000000U << DDR_PHY_DX5GCR0_DQSGPDR_SHIFT
9243                         | 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_4_SHIFT
9244                         | 0x00000000U << DDR_PHY_DX5GCR0_DQSGODT_SHIFT
9245                         | 0x00000001U << DDR_PHY_DX5GCR0_DQSGOE_SHIFT
9246                         | 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT
9247                         |  0 ) & RegMask); */
9248                 PSU_Mask_Write (DDR_PHY_DX5GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
9249         /*############################################################################################################################ */
9250
9251                 /*Register : DX5GCR1 @ 0XFD080C04</p>
9252
9253                 Enables the PDR mode for DQ[7:0]
9254                 PSU_DDR_PHY_DX5GCR1_DXPDRMODE                                                   0x0
9255
9256                 Reserved. Returns zeroes on reads.
9257                 PSU_DDR_PHY_DX5GCR1_RESERVED_15                                                 0x0
9258
9259                 Select the delayed or non-delayed read data strobe #
9260                 PSU_DDR_PHY_DX5GCR1_QSNSEL                                                      0x1
9261
9262                 Select the delayed or non-delayed read data strobe
9263                 PSU_DDR_PHY_DX5GCR1_QSSEL                                                       0x1
9264
9265                 Enables Read Data Strobe in a byte lane
9266                 PSU_DDR_PHY_DX5GCR1_OEEN                                                        0x1
9267
9268                 Enables PDR in a byte lane
9269                 PSU_DDR_PHY_DX5GCR1_PDREN                                                       0x1
9270
9271                 Enables ODT/TE in a byte lane
9272                 PSU_DDR_PHY_DX5GCR1_TEEN                                                        0x1
9273
9274                 Enables Write Data strobe in a byte lane
9275                 PSU_DDR_PHY_DX5GCR1_DSEN                                                        0x1
9276
9277                 Enables DM pin in a byte lane
9278                 PSU_DDR_PHY_DX5GCR1_DMEN                                                        0x1
9279
9280                 Enables DQ corresponding to each bit in a byte
9281                 PSU_DDR_PHY_DX5GCR1_DQEN                                                        0xff
9282
9283                 DATX8 n General Configuration Register 1
9284                 (OFFSET, MASK, VALUE)      (0XFD080C04, 0xFFFFFFFFU ,0x00007FFFU)
9285                 RegMask = (DDR_PHY_DX5GCR1_DXPDRMODE_MASK | DDR_PHY_DX5GCR1_RESERVED_15_MASK | DDR_PHY_DX5GCR1_QSNSEL_MASK | DDR_PHY_DX5GCR1_QSSEL_MASK | DDR_PHY_DX5GCR1_OEEN_MASK | DDR_PHY_DX5GCR1_PDREN_MASK | DDR_PHY_DX5GCR1_TEEN_MASK | DDR_PHY_DX5GCR1_DSEN_MASK | DDR_PHY_DX5GCR1_DMEN_MASK | DDR_PHY_DX5GCR1_DQEN_MASK |  0 );
9286
9287                 RegVal = ((0x00000000U << DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT
9288                         | 0x00000000U << DDR_PHY_DX5GCR1_RESERVED_15_SHIFT
9289                         | 0x00000001U << DDR_PHY_DX5GCR1_QSNSEL_SHIFT
9290                         | 0x00000001U << DDR_PHY_DX5GCR1_QSSEL_SHIFT
9291                         | 0x00000001U << DDR_PHY_DX5GCR1_OEEN_SHIFT
9292                         | 0x00000001U << DDR_PHY_DX5GCR1_PDREN_SHIFT
9293                         | 0x00000001U << DDR_PHY_DX5GCR1_TEEN_SHIFT
9294                         | 0x00000001U << DDR_PHY_DX5GCR1_DSEN_SHIFT
9295                         | 0x00000001U << DDR_PHY_DX5GCR1_DMEN_SHIFT
9296                         | 0x000000FFU << DDR_PHY_DX5GCR1_DQEN_SHIFT
9297                         |  0 ) & RegMask); */
9298                 PSU_Mask_Write (DDR_PHY_DX5GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
9299         /*############################################################################################################################ */
9300
9301                 /*Register : DX5GCR4 @ 0XFD080C10</p>
9302
9303                 Byte lane VREF IOM (Used only by D4MU IOs)
9304                 PSU_DDR_PHY_DX5GCR4_RESERVED_31_29                                              0x0
9305
9306                 Byte Lane VREF Pad Enable
9307                 PSU_DDR_PHY_DX5GCR4_DXREFPEN                                                    0x0
9308
9309                 Byte Lane Internal VREF Enable
9310                 PSU_DDR_PHY_DX5GCR4_DXREFEEN                                                    0x3
9311
9312                 Byte Lane Single-End VREF Enable
9313                 PSU_DDR_PHY_DX5GCR4_DXREFSEN                                                    0x1
9314
9315                 Reserved. Returns zeros on reads.
9316                 PSU_DDR_PHY_DX5GCR4_RESERVED_24                                                 0x0
9317
9318                 External VREF generator REFSEL range select
9319                 PSU_DDR_PHY_DX5GCR4_DXREFESELRANGE                                              0x0
9320
9321                 Byte Lane External VREF Select
9322                 PSU_DDR_PHY_DX5GCR4_DXREFESEL                                                   0x0
9323
9324                 Single ended VREF generator REFSEL range select
9325                 PSU_DDR_PHY_DX5GCR4_DXREFSSELRANGE                                              0x1
9326
9327                 Byte Lane Single-End VREF Select
9328                 PSU_DDR_PHY_DX5GCR4_DXREFSSEL                                                   0x30
9329
9330                 Reserved. Returns zeros on reads.
9331                 PSU_DDR_PHY_DX5GCR4_RESERVED_7_6                                                0x0
9332
9333                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
9334                 PSU_DDR_PHY_DX5GCR4_DXREFIEN                                                    0xf
9335
9336                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
9337                 PSU_DDR_PHY_DX5GCR4_DXREFIMON                                                   0x0
9338
9339                 DATX8 n General Configuration Register 4
9340                 (OFFSET, MASK, VALUE)      (0XFD080C10, 0xFFFFFFFFU ,0x0E00B03CU)
9341                 RegMask = (DDR_PHY_DX5GCR4_RESERVED_31_29_MASK | DDR_PHY_DX5GCR4_DXREFPEN_MASK | DDR_PHY_DX5GCR4_DXREFEEN_MASK | DDR_PHY_DX5GCR4_DXREFSEN_MASK | DDR_PHY_DX5GCR4_RESERVED_24_MASK | DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX5GCR4_DXREFESEL_MASK | DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX5GCR4_DXREFSSEL_MASK | DDR_PHY_DX5GCR4_RESERVED_7_6_MASK | DDR_PHY_DX5GCR4_DXREFIEN_MASK | DDR_PHY_DX5GCR4_DXREFIMON_MASK |  0 );
9342
9343                 RegVal = ((0x00000000U << DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT
9344                         | 0x00000000U << DDR_PHY_DX5GCR4_DXREFPEN_SHIFT
9345                         | 0x00000003U << DDR_PHY_DX5GCR4_DXREFEEN_SHIFT
9346                         | 0x00000001U << DDR_PHY_DX5GCR4_DXREFSEN_SHIFT
9347                         | 0x00000000U << DDR_PHY_DX5GCR4_RESERVED_24_SHIFT
9348                         | 0x00000000U << DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT
9349                         | 0x00000000U << DDR_PHY_DX5GCR4_DXREFESEL_SHIFT
9350                         | 0x00000001U << DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT
9351                         | 0x00000030U << DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT
9352                         | 0x00000000U << DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT
9353                         | 0x0000000FU << DDR_PHY_DX5GCR4_DXREFIEN_SHIFT
9354                         | 0x00000000U << DDR_PHY_DX5GCR4_DXREFIMON_SHIFT
9355                         |  0 ) & RegMask); */
9356                 PSU_Mask_Write (DDR_PHY_DX5GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
9357         /*############################################################################################################################ */
9358
9359                 /*Register : DX5GCR5 @ 0XFD080C14</p>
9360
9361                 Reserved. Returns zeros on reads.
9362                 PSU_DDR_PHY_DX5GCR5_RESERVED_31                                                 0x0
9363
9364                 Byte Lane internal VREF Select for Rank 3
9365                 PSU_DDR_PHY_DX5GCR5_DXREFISELR3                                                 0x9
9366
9367                 Reserved. Returns zeros on reads.
9368                 PSU_DDR_PHY_DX5GCR5_RESERVED_23                                                 0x0
9369
9370                 Byte Lane internal VREF Select for Rank 2
9371                 PSU_DDR_PHY_DX5GCR5_DXREFISELR2                                                 0x9
9372
9373                 Reserved. Returns zeros on reads.
9374                 PSU_DDR_PHY_DX5GCR5_RESERVED_15                                                 0x0
9375
9376                 Byte Lane internal VREF Select for Rank 1
9377                 PSU_DDR_PHY_DX5GCR5_DXREFISELR1                                                 0x4f
9378
9379                 Reserved. Returns zeros on reads.
9380                 PSU_DDR_PHY_DX5GCR5_RESERVED_7                                                  0x0
9381
9382                 Byte Lane internal VREF Select for Rank 0
9383                 PSU_DDR_PHY_DX5GCR5_DXREFISELR0                                                 0x4f
9384
9385                 DATX8 n General Configuration Register 5
9386                 (OFFSET, MASK, VALUE)      (0XFD080C14, 0xFFFFFFFFU ,0x09094F4FU)
9387                 RegMask = (DDR_PHY_DX5GCR5_RESERVED_31_MASK | DDR_PHY_DX5GCR5_DXREFISELR3_MASK | DDR_PHY_DX5GCR5_RESERVED_23_MASK | DDR_PHY_DX5GCR5_DXREFISELR2_MASK | DDR_PHY_DX5GCR5_RESERVED_15_MASK | DDR_PHY_DX5GCR5_DXREFISELR1_MASK | DDR_PHY_DX5GCR5_RESERVED_7_MASK | DDR_PHY_DX5GCR5_DXREFISELR0_MASK |  0 );
9388
9389                 RegVal = ((0x00000000U << DDR_PHY_DX5GCR5_RESERVED_31_SHIFT
9390                         | 0x00000009U << DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT
9391                         | 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_23_SHIFT
9392                         | 0x00000009U << DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT
9393                         | 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_15_SHIFT
9394                         | 0x0000004FU << DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT
9395                         | 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_7_SHIFT
9396                         | 0x0000004FU << DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT
9397                         |  0 ) & RegMask); */
9398                 PSU_Mask_Write (DDR_PHY_DX5GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
9399         /*############################################################################################################################ */
9400
9401                 /*Register : DX5GCR6 @ 0XFD080C18</p>
9402
9403                 Reserved. Returns zeros on reads.
9404                 PSU_DDR_PHY_DX5GCR6_RESERVED_31_30                                              0x0
9405
9406                 DRAM DQ VREF Select for Rank3
9407                 PSU_DDR_PHY_DX5GCR6_DXDQVREFR3                                                  0x9
9408
9409                 Reserved. Returns zeros on reads.
9410                 PSU_DDR_PHY_DX5GCR6_RESERVED_23_22                                              0x0
9411
9412                 DRAM DQ VREF Select for Rank2
9413                 PSU_DDR_PHY_DX5GCR6_DXDQVREFR2                                                  0x9
9414
9415                 Reserved. Returns zeros on reads.
9416                 PSU_DDR_PHY_DX5GCR6_RESERVED_15_14                                              0x0
9417
9418                 DRAM DQ VREF Select for Rank1
9419                 PSU_DDR_PHY_DX5GCR6_DXDQVREFR1                                                  0x2b
9420
9421                 Reserved. Returns zeros on reads.
9422                 PSU_DDR_PHY_DX5GCR6_RESERVED_7_6                                                0x0
9423
9424                 DRAM DQ VREF Select for Rank0
9425                 PSU_DDR_PHY_DX5GCR6_DXDQVREFR0                                                  0x2b
9426
9427                 DATX8 n General Configuration Register 6
9428                 (OFFSET, MASK, VALUE)      (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU)
9429                 RegMask = (DDR_PHY_DX5GCR6_RESERVED_31_30_MASK | DDR_PHY_DX5GCR6_DXDQVREFR3_MASK | DDR_PHY_DX5GCR6_RESERVED_23_22_MASK | DDR_PHY_DX5GCR6_DXDQVREFR2_MASK | DDR_PHY_DX5GCR6_RESERVED_15_14_MASK | DDR_PHY_DX5GCR6_DXDQVREFR1_MASK | DDR_PHY_DX5GCR6_RESERVED_7_6_MASK | DDR_PHY_DX5GCR6_DXDQVREFR0_MASK |  0 );
9430
9431                 RegVal = ((0x00000000U << DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT
9432                         | 0x00000009U << DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT
9433                         | 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT
9434                         | 0x00000009U << DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT
9435                         | 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT
9436                         | 0x0000002BU << DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT
9437                         | 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT
9438                         | 0x0000002BU << DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT
9439                         |  0 ) & RegMask); */
9440                 PSU_Mask_Write (DDR_PHY_DX5GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
9441         /*############################################################################################################################ */
9442
9443                 /*Register : DX5LCDLR2 @ 0XFD080C88</p>
9444
9445                 Reserved. Return zeroes on reads.
9446                 PSU_DDR_PHY_DX5LCDLR2_RESERVED_31_25                                            0x0
9447
9448                 Reserved. Caution, do not write to this register field.
9449                 PSU_DDR_PHY_DX5LCDLR2_RESERVED_24_16                                            0x0
9450
9451                 Reserved. Return zeroes on reads.
9452                 PSU_DDR_PHY_DX5LCDLR2_RESERVED_15_9                                             0x0
9453
9454                 Read DQS Gating Delay
9455                 PSU_DDR_PHY_DX5LCDLR2_DQSGD                                                     0x0
9456
9457                 DATX8 n Local Calibrated Delay Line Register 2
9458                 (OFFSET, MASK, VALUE)      (0XFD080C88, 0xFFFFFFFFU ,0x00000000U)
9459                 RegMask = (DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX5LCDLR2_DQSGD_MASK |  0 );
9460
9461                 RegVal = ((0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT
9462                         | 0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT
9463                         | 0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT
9464                         | 0x00000000U << DDR_PHY_DX5LCDLR2_DQSGD_SHIFT
9465                         |  0 ) & RegMask); */
9466                 PSU_Mask_Write (DDR_PHY_DX5LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
9467         /*############################################################################################################################ */
9468
9469                 /*Register : DX5GTR0 @ 0XFD080CC0</p>
9470
9471                 Reserved. Return zeroes on reads.
9472                 PSU_DDR_PHY_DX5GTR0_RESERVED_31_24                                              0x0
9473
9474                 DQ Write Path Latency Pipeline
9475                 PSU_DDR_PHY_DX5GTR0_WDQSL                                                       0x0
9476
9477                 Reserved. Caution, do not write to this register field.
9478                 PSU_DDR_PHY_DX5GTR0_RESERVED_23_20                                              0x0
9479
9480                 Write Leveling System Latency
9481                 PSU_DDR_PHY_DX5GTR0_WLSL                                                        0x2
9482
9483                 Reserved. Return zeroes on reads.
9484                 PSU_DDR_PHY_DX5GTR0_RESERVED_15_13                                              0x0
9485
9486                 Reserved. Caution, do not write to this register field.
9487                 PSU_DDR_PHY_DX5GTR0_RESERVED_12_8                                               0x0
9488
9489                 Reserved. Return zeroes on reads.
9490                 PSU_DDR_PHY_DX5GTR0_RESERVED_7_5                                                0x0
9491
9492                 DQS Gating System Latency
9493                 PSU_DDR_PHY_DX5GTR0_DGSL                                                        0x0
9494
9495                 DATX8 n General Timing Register 0
9496                 (OFFSET, MASK, VALUE)      (0XFD080CC0, 0xFFFFFFFFU ,0x00020000U)
9497                 RegMask = (DDR_PHY_DX5GTR0_RESERVED_31_24_MASK | DDR_PHY_DX5GTR0_WDQSL_MASK | DDR_PHY_DX5GTR0_RESERVED_23_20_MASK | DDR_PHY_DX5GTR0_WLSL_MASK | DDR_PHY_DX5GTR0_RESERVED_15_13_MASK | DDR_PHY_DX5GTR0_RESERVED_12_8_MASK | DDR_PHY_DX5GTR0_RESERVED_7_5_MASK | DDR_PHY_DX5GTR0_DGSL_MASK |  0 );
9498
9499                 RegVal = ((0x00000000U << DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT
9500                         | 0x00000000U << DDR_PHY_DX5GTR0_WDQSL_SHIFT
9501                         | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT
9502                         | 0x00000002U << DDR_PHY_DX5GTR0_WLSL_SHIFT
9503                         | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT
9504                         | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT
9505                         | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT
9506                         | 0x00000000U << DDR_PHY_DX5GTR0_DGSL_SHIFT
9507                         |  0 ) & RegMask); */
9508                 PSU_Mask_Write (DDR_PHY_DX5GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
9509         /*############################################################################################################################ */
9510
9511                 /*Register : DX6GCR0 @ 0XFD080D00</p>
9512
9513                 Calibration Bypass
9514                 PSU_DDR_PHY_DX6GCR0_CALBYP                                                      0x0
9515
9516                 Master Delay Line Enable
9517                 PSU_DDR_PHY_DX6GCR0_MDLEN                                                       0x1
9518
9519                 Configurable ODT(TE) Phase Shift
9520                 PSU_DDR_PHY_DX6GCR0_CODTSHFT                                                    0x0
9521
9522                 DQS Duty Cycle Correction
9523                 PSU_DDR_PHY_DX6GCR0_DQSDCC                                                      0x0
9524
9525                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
9526                 PSU_DDR_PHY_DX6GCR0_RDDLY                                                       0x8
9527
9528                 Reserved. Return zeroes on reads.
9529                 PSU_DDR_PHY_DX6GCR0_RESERVED_19_14                                              0x0
9530
9531                 DQSNSE Power Down Receiver
9532                 PSU_DDR_PHY_DX6GCR0_DQSNSEPDR                                                   0x0
9533
9534                 DQSSE Power Down Receiver
9535                 PSU_DDR_PHY_DX6GCR0_DQSSEPDR                                                    0x0
9536
9537                 RTT On Additive Latency
9538                 PSU_DDR_PHY_DX6GCR0_RTTOAL                                                      0x0
9539
9540                 RTT Output Hold
9541                 PSU_DDR_PHY_DX6GCR0_RTTOH                                                       0x3
9542
9543                 Configurable PDR Phase Shift
9544                 PSU_DDR_PHY_DX6GCR0_CPDRSHFT                                                    0x0
9545
9546                 DQSR Power Down
9547                 PSU_DDR_PHY_DX6GCR0_DQSRPD                                                      0x0
9548
9549                 DQSG Power Down Receiver
9550                 PSU_DDR_PHY_DX6GCR0_DQSGPDR                                                     0x0
9551
9552                 Reserved. Return zeroes on reads.
9553                 PSU_DDR_PHY_DX6GCR0_RESERVED_4                                                  0x0
9554
9555                 DQSG On-Die Termination
9556                 PSU_DDR_PHY_DX6GCR0_DQSGODT                                                     0x0
9557
9558                 DQSG Output Enable
9559                 PSU_DDR_PHY_DX6GCR0_DQSGOE                                                      0x1
9560
9561                 Reserved. Return zeroes on reads.
9562                 PSU_DDR_PHY_DX6GCR0_RESERVED_1_0                                                0x0
9563
9564                 DATX8 n General Configuration Register 0
9565                 (OFFSET, MASK, VALUE)      (0XFD080D00, 0xFFFFFFFFU ,0x40800604U)
9566                 RegMask = (DDR_PHY_DX6GCR0_CALBYP_MASK | DDR_PHY_DX6GCR0_MDLEN_MASK | DDR_PHY_DX6GCR0_CODTSHFT_MASK | DDR_PHY_DX6GCR0_DQSDCC_MASK | DDR_PHY_DX6GCR0_RDDLY_MASK | DDR_PHY_DX6GCR0_RESERVED_19_14_MASK | DDR_PHY_DX6GCR0_DQSNSEPDR_MASK | DDR_PHY_DX6GCR0_DQSSEPDR_MASK | DDR_PHY_DX6GCR0_RTTOAL_MASK | DDR_PHY_DX6GCR0_RTTOH_MASK | DDR_PHY_DX6GCR0_CPDRSHFT_MASK | DDR_PHY_DX6GCR0_DQSRPD_MASK | DDR_PHY_DX6GCR0_DQSGPDR_MASK | DDR_PHY_DX6GCR0_RESERVED_4_MASK | DDR_PHY_DX6GCR0_DQSGODT_MASK | DDR_PHY_DX6GCR0_DQSGOE_MASK | DDR_PHY_DX6GCR0_RESERVED_1_0_MASK |  0 );
9567
9568                 RegVal = ((0x00000000U << DDR_PHY_DX6GCR0_CALBYP_SHIFT
9569                         | 0x00000001U << DDR_PHY_DX6GCR0_MDLEN_SHIFT
9570                         | 0x00000000U << DDR_PHY_DX6GCR0_CODTSHFT_SHIFT
9571                         | 0x00000000U << DDR_PHY_DX6GCR0_DQSDCC_SHIFT
9572                         | 0x00000008U << DDR_PHY_DX6GCR0_RDDLY_SHIFT
9573                         | 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT
9574                         | 0x00000000U << DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT
9575                         | 0x00000000U << DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT
9576                         | 0x00000000U << DDR_PHY_DX6GCR0_RTTOAL_SHIFT
9577                         | 0x00000003U << DDR_PHY_DX6GCR0_RTTOH_SHIFT
9578                         | 0x00000000U << DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT
9579                         | 0x00000000U << DDR_PHY_DX6GCR0_DQSRPD_SHIFT
9580                         | 0x00000000U << DDR_PHY_DX6GCR0_DQSGPDR_SHIFT
9581                         | 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_4_SHIFT
9582                         | 0x00000000U << DDR_PHY_DX6GCR0_DQSGODT_SHIFT
9583                         | 0x00000001U << DDR_PHY_DX6GCR0_DQSGOE_SHIFT
9584                         | 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT
9585                         |  0 ) & RegMask); */
9586                 PSU_Mask_Write (DDR_PHY_DX6GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
9587         /*############################################################################################################################ */
9588
9589                 /*Register : DX6GCR1 @ 0XFD080D04</p>
9590
9591                 Enables the PDR mode for DQ[7:0]
9592                 PSU_DDR_PHY_DX6GCR1_DXPDRMODE                                                   0x0
9593
9594                 Reserved. Returns zeroes on reads.
9595                 PSU_DDR_PHY_DX6GCR1_RESERVED_15                                                 0x0
9596
9597                 Select the delayed or non-delayed read data strobe #
9598                 PSU_DDR_PHY_DX6GCR1_QSNSEL                                                      0x1
9599
9600                 Select the delayed or non-delayed read data strobe
9601                 PSU_DDR_PHY_DX6GCR1_QSSEL                                                       0x1
9602
9603                 Enables Read Data Strobe in a byte lane
9604                 PSU_DDR_PHY_DX6GCR1_OEEN                                                        0x1
9605
9606                 Enables PDR in a byte lane
9607                 PSU_DDR_PHY_DX6GCR1_PDREN                                                       0x1
9608
9609                 Enables ODT/TE in a byte lane
9610                 PSU_DDR_PHY_DX6GCR1_TEEN                                                        0x1
9611
9612                 Enables Write Data strobe in a byte lane
9613                 PSU_DDR_PHY_DX6GCR1_DSEN                                                        0x1
9614
9615                 Enables DM pin in a byte lane
9616                 PSU_DDR_PHY_DX6GCR1_DMEN                                                        0x1
9617
9618                 Enables DQ corresponding to each bit in a byte
9619                 PSU_DDR_PHY_DX6GCR1_DQEN                                                        0xff
9620
9621                 DATX8 n General Configuration Register 1
9622                 (OFFSET, MASK, VALUE)      (0XFD080D04, 0xFFFFFFFFU ,0x00007FFFU)
9623                 RegMask = (DDR_PHY_DX6GCR1_DXPDRMODE_MASK | DDR_PHY_DX6GCR1_RESERVED_15_MASK | DDR_PHY_DX6GCR1_QSNSEL_MASK | DDR_PHY_DX6GCR1_QSSEL_MASK | DDR_PHY_DX6GCR1_OEEN_MASK | DDR_PHY_DX6GCR1_PDREN_MASK | DDR_PHY_DX6GCR1_TEEN_MASK | DDR_PHY_DX6GCR1_DSEN_MASK | DDR_PHY_DX6GCR1_DMEN_MASK | DDR_PHY_DX6GCR1_DQEN_MASK |  0 );
9624
9625                 RegVal = ((0x00000000U << DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT
9626                         | 0x00000000U << DDR_PHY_DX6GCR1_RESERVED_15_SHIFT
9627                         | 0x00000001U << DDR_PHY_DX6GCR1_QSNSEL_SHIFT
9628                         | 0x00000001U << DDR_PHY_DX6GCR1_QSSEL_SHIFT
9629                         | 0x00000001U << DDR_PHY_DX6GCR1_OEEN_SHIFT
9630                         | 0x00000001U << DDR_PHY_DX6GCR1_PDREN_SHIFT
9631                         | 0x00000001U << DDR_PHY_DX6GCR1_TEEN_SHIFT
9632                         | 0x00000001U << DDR_PHY_DX6GCR1_DSEN_SHIFT
9633                         | 0x00000001U << DDR_PHY_DX6GCR1_DMEN_SHIFT
9634                         | 0x000000FFU << DDR_PHY_DX6GCR1_DQEN_SHIFT
9635                         |  0 ) & RegMask); */
9636                 PSU_Mask_Write (DDR_PHY_DX6GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
9637         /*############################################################################################################################ */
9638
9639                 /*Register : DX6GCR4 @ 0XFD080D10</p>
9640
9641                 Byte lane VREF IOM (Used only by D4MU IOs)
9642                 PSU_DDR_PHY_DX6GCR4_RESERVED_31_29                                              0x0
9643
9644                 Byte Lane VREF Pad Enable
9645                 PSU_DDR_PHY_DX6GCR4_DXREFPEN                                                    0x0
9646
9647                 Byte Lane Internal VREF Enable
9648                 PSU_DDR_PHY_DX6GCR4_DXREFEEN                                                    0x3
9649
9650                 Byte Lane Single-End VREF Enable
9651                 PSU_DDR_PHY_DX6GCR4_DXREFSEN                                                    0x1
9652
9653                 Reserved. Returns zeros on reads.
9654                 PSU_DDR_PHY_DX6GCR4_RESERVED_24                                                 0x0
9655
9656                 External VREF generator REFSEL range select
9657                 PSU_DDR_PHY_DX6GCR4_DXREFESELRANGE                                              0x0
9658
9659                 Byte Lane External VREF Select
9660                 PSU_DDR_PHY_DX6GCR4_DXREFESEL                                                   0x0
9661
9662                 Single ended VREF generator REFSEL range select
9663                 PSU_DDR_PHY_DX6GCR4_DXREFSSELRANGE                                              0x1
9664
9665                 Byte Lane Single-End VREF Select
9666                 PSU_DDR_PHY_DX6GCR4_DXREFSSEL                                                   0x30
9667
9668                 Reserved. Returns zeros on reads.
9669                 PSU_DDR_PHY_DX6GCR4_RESERVED_7_6                                                0x0
9670
9671                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
9672                 PSU_DDR_PHY_DX6GCR4_DXREFIEN                                                    0xf
9673
9674                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
9675                 PSU_DDR_PHY_DX6GCR4_DXREFIMON                                                   0x0
9676
9677                 DATX8 n General Configuration Register 4
9678                 (OFFSET, MASK, VALUE)      (0XFD080D10, 0xFFFFFFFFU ,0x0E00B03CU)
9679                 RegMask = (DDR_PHY_DX6GCR4_RESERVED_31_29_MASK | DDR_PHY_DX6GCR4_DXREFPEN_MASK | DDR_PHY_DX6GCR4_DXREFEEN_MASK | DDR_PHY_DX6GCR4_DXREFSEN_MASK | DDR_PHY_DX6GCR4_RESERVED_24_MASK | DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX6GCR4_DXREFESEL_MASK | DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX6GCR4_DXREFSSEL_MASK | DDR_PHY_DX6GCR4_RESERVED_7_6_MASK | DDR_PHY_DX6GCR4_DXREFIEN_MASK | DDR_PHY_DX6GCR4_DXREFIMON_MASK |  0 );
9680
9681                 RegVal = ((0x00000000U << DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT
9682                         | 0x00000000U << DDR_PHY_DX6GCR4_DXREFPEN_SHIFT
9683                         | 0x00000003U << DDR_PHY_DX6GCR4_DXREFEEN_SHIFT
9684                         | 0x00000001U << DDR_PHY_DX6GCR4_DXREFSEN_SHIFT
9685                         | 0x00000000U << DDR_PHY_DX6GCR4_RESERVED_24_SHIFT
9686                         | 0x00000000U << DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT
9687                         | 0x00000000U << DDR_PHY_DX6GCR4_DXREFESEL_SHIFT
9688                         | 0x00000001U << DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT
9689                         | 0x00000030U << DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT
9690                         | 0x00000000U << DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT
9691                         | 0x0000000FU << DDR_PHY_DX6GCR4_DXREFIEN_SHIFT
9692                         | 0x00000000U << DDR_PHY_DX6GCR4_DXREFIMON_SHIFT
9693                         |  0 ) & RegMask); */
9694                 PSU_Mask_Write (DDR_PHY_DX6GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
9695         /*############################################################################################################################ */
9696
9697                 /*Register : DX6GCR5 @ 0XFD080D14</p>
9698
9699                 Reserved. Returns zeros on reads.
9700                 PSU_DDR_PHY_DX6GCR5_RESERVED_31                                                 0x0
9701
9702                 Byte Lane internal VREF Select for Rank 3
9703                 PSU_DDR_PHY_DX6GCR5_DXREFISELR3                                                 0x9
9704
9705                 Reserved. Returns zeros on reads.
9706                 PSU_DDR_PHY_DX6GCR5_RESERVED_23                                                 0x0
9707
9708                 Byte Lane internal VREF Select for Rank 2
9709                 PSU_DDR_PHY_DX6GCR5_DXREFISELR2                                                 0x9
9710
9711                 Reserved. Returns zeros on reads.
9712                 PSU_DDR_PHY_DX6GCR5_RESERVED_15                                                 0x0
9713
9714                 Byte Lane internal VREF Select for Rank 1
9715                 PSU_DDR_PHY_DX6GCR5_DXREFISELR1                                                 0x4f
9716
9717                 Reserved. Returns zeros on reads.
9718                 PSU_DDR_PHY_DX6GCR5_RESERVED_7                                                  0x0
9719
9720                 Byte Lane internal VREF Select for Rank 0
9721                 PSU_DDR_PHY_DX6GCR5_DXREFISELR0                                                 0x4f
9722
9723                 DATX8 n General Configuration Register 5
9724                 (OFFSET, MASK, VALUE)      (0XFD080D14, 0xFFFFFFFFU ,0x09094F4FU)
9725                 RegMask = (DDR_PHY_DX6GCR5_RESERVED_31_MASK | DDR_PHY_DX6GCR5_DXREFISELR3_MASK | DDR_PHY_DX6GCR5_RESERVED_23_MASK | DDR_PHY_DX6GCR5_DXREFISELR2_MASK | DDR_PHY_DX6GCR5_RESERVED_15_MASK | DDR_PHY_DX6GCR5_DXREFISELR1_MASK | DDR_PHY_DX6GCR5_RESERVED_7_MASK | DDR_PHY_DX6GCR5_DXREFISELR0_MASK |  0 );
9726
9727                 RegVal = ((0x00000000U << DDR_PHY_DX6GCR5_RESERVED_31_SHIFT
9728                         | 0x00000009U << DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT
9729                         | 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_23_SHIFT
9730                         | 0x00000009U << DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT
9731                         | 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_15_SHIFT
9732                         | 0x0000004FU << DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT
9733                         | 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_7_SHIFT
9734                         | 0x0000004FU << DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT
9735                         |  0 ) & RegMask); */
9736                 PSU_Mask_Write (DDR_PHY_DX6GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
9737         /*############################################################################################################################ */
9738
9739                 /*Register : DX6GCR6 @ 0XFD080D18</p>
9740
9741                 Reserved. Returns zeros on reads.
9742                 PSU_DDR_PHY_DX6GCR6_RESERVED_31_30                                              0x0
9743
9744                 DRAM DQ VREF Select for Rank3
9745                 PSU_DDR_PHY_DX6GCR6_DXDQVREFR3                                                  0x9
9746
9747                 Reserved. Returns zeros on reads.
9748                 PSU_DDR_PHY_DX6GCR6_RESERVED_23_22                                              0x0
9749
9750                 DRAM DQ VREF Select for Rank2
9751                 PSU_DDR_PHY_DX6GCR6_DXDQVREFR2                                                  0x9
9752
9753                 Reserved. Returns zeros on reads.
9754                 PSU_DDR_PHY_DX6GCR6_RESERVED_15_14                                              0x0
9755
9756                 DRAM DQ VREF Select for Rank1
9757                 PSU_DDR_PHY_DX6GCR6_DXDQVREFR1                                                  0x2b
9758
9759                 Reserved. Returns zeros on reads.
9760                 PSU_DDR_PHY_DX6GCR6_RESERVED_7_6                                                0x0
9761
9762                 DRAM DQ VREF Select for Rank0
9763                 PSU_DDR_PHY_DX6GCR6_DXDQVREFR0                                                  0x2b
9764
9765                 DATX8 n General Configuration Register 6
9766                 (OFFSET, MASK, VALUE)      (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU)
9767                 RegMask = (DDR_PHY_DX6GCR6_RESERVED_31_30_MASK | DDR_PHY_DX6GCR6_DXDQVREFR3_MASK | DDR_PHY_DX6GCR6_RESERVED_23_22_MASK | DDR_PHY_DX6GCR6_DXDQVREFR2_MASK | DDR_PHY_DX6GCR6_RESERVED_15_14_MASK | DDR_PHY_DX6GCR6_DXDQVREFR1_MASK | DDR_PHY_DX6GCR6_RESERVED_7_6_MASK | DDR_PHY_DX6GCR6_DXDQVREFR0_MASK |  0 );
9768
9769                 RegVal = ((0x00000000U << DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT
9770                         | 0x00000009U << DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT
9771                         | 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT
9772                         | 0x00000009U << DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT
9773                         | 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT
9774                         | 0x0000002BU << DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT
9775                         | 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT
9776                         | 0x0000002BU << DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT
9777                         |  0 ) & RegMask); */
9778                 PSU_Mask_Write (DDR_PHY_DX6GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
9779         /*############################################################################################################################ */
9780
9781                 /*Register : DX6LCDLR2 @ 0XFD080D88</p>
9782
9783                 Reserved. Return zeroes on reads.
9784                 PSU_DDR_PHY_DX6LCDLR2_RESERVED_31_25                                            0x0
9785
9786                 Reserved. Caution, do not write to this register field.
9787                 PSU_DDR_PHY_DX6LCDLR2_RESERVED_24_16                                            0x0
9788
9789                 Reserved. Return zeroes on reads.
9790                 PSU_DDR_PHY_DX6LCDLR2_RESERVED_15_9                                             0x0
9791
9792                 Read DQS Gating Delay
9793                 PSU_DDR_PHY_DX6LCDLR2_DQSGD                                                     0x0
9794
9795                 DATX8 n Local Calibrated Delay Line Register 2
9796                 (OFFSET, MASK, VALUE)      (0XFD080D88, 0xFFFFFFFFU ,0x00000000U)
9797                 RegMask = (DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX6LCDLR2_DQSGD_MASK |  0 );
9798
9799                 RegVal = ((0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT
9800                         | 0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT
9801                         | 0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT
9802                         | 0x00000000U << DDR_PHY_DX6LCDLR2_DQSGD_SHIFT
9803                         |  0 ) & RegMask); */
9804                 PSU_Mask_Write (DDR_PHY_DX6LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
9805         /*############################################################################################################################ */
9806
9807                 /*Register : DX6GTR0 @ 0XFD080DC0</p>
9808
9809                 Reserved. Return zeroes on reads.
9810                 PSU_DDR_PHY_DX6GTR0_RESERVED_31_24                                              0x0
9811
9812                 DQ Write Path Latency Pipeline
9813                 PSU_DDR_PHY_DX6GTR0_WDQSL                                                       0x0
9814
9815                 Reserved. Caution, do not write to this register field.
9816                 PSU_DDR_PHY_DX6GTR0_RESERVED_23_20                                              0x0
9817
9818                 Write Leveling System Latency
9819                 PSU_DDR_PHY_DX6GTR0_WLSL                                                        0x2
9820
9821                 Reserved. Return zeroes on reads.
9822                 PSU_DDR_PHY_DX6GTR0_RESERVED_15_13                                              0x0
9823
9824                 Reserved. Caution, do not write to this register field.
9825                 PSU_DDR_PHY_DX6GTR0_RESERVED_12_8                                               0x0
9826
9827                 Reserved. Return zeroes on reads.
9828                 PSU_DDR_PHY_DX6GTR0_RESERVED_7_5                                                0x0
9829
9830                 DQS Gating System Latency
9831                 PSU_DDR_PHY_DX6GTR0_DGSL                                                        0x0
9832
9833                 DATX8 n General Timing Register 0
9834                 (OFFSET, MASK, VALUE)      (0XFD080DC0, 0xFFFFFFFFU ,0x00020000U)
9835                 RegMask = (DDR_PHY_DX6GTR0_RESERVED_31_24_MASK | DDR_PHY_DX6GTR0_WDQSL_MASK | DDR_PHY_DX6GTR0_RESERVED_23_20_MASK | DDR_PHY_DX6GTR0_WLSL_MASK | DDR_PHY_DX6GTR0_RESERVED_15_13_MASK | DDR_PHY_DX6GTR0_RESERVED_12_8_MASK | DDR_PHY_DX6GTR0_RESERVED_7_5_MASK | DDR_PHY_DX6GTR0_DGSL_MASK |  0 );
9836
9837                 RegVal = ((0x00000000U << DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT
9838                         | 0x00000000U << DDR_PHY_DX6GTR0_WDQSL_SHIFT
9839                         | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT
9840                         | 0x00000002U << DDR_PHY_DX6GTR0_WLSL_SHIFT
9841                         | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT
9842                         | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT
9843                         | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT
9844                         | 0x00000000U << DDR_PHY_DX6GTR0_DGSL_SHIFT
9845                         |  0 ) & RegMask); */
9846                 PSU_Mask_Write (DDR_PHY_DX6GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
9847         /*############################################################################################################################ */
9848
9849                 /*Register : DX7GCR0 @ 0XFD080E00</p>
9850
9851                 Calibration Bypass
9852                 PSU_DDR_PHY_DX7GCR0_CALBYP                                                      0x0
9853
9854                 Master Delay Line Enable
9855                 PSU_DDR_PHY_DX7GCR0_MDLEN                                                       0x1
9856
9857                 Configurable ODT(TE) Phase Shift
9858                 PSU_DDR_PHY_DX7GCR0_CODTSHFT                                                    0x0
9859
9860                 DQS Duty Cycle Correction
9861                 PSU_DDR_PHY_DX7GCR0_DQSDCC                                                      0x0
9862
9863                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
9864                 PSU_DDR_PHY_DX7GCR0_RDDLY                                                       0x8
9865
9866                 Reserved. Return zeroes on reads.
9867                 PSU_DDR_PHY_DX7GCR0_RESERVED_19_14                                              0x0
9868
9869                 DQSNSE Power Down Receiver
9870                 PSU_DDR_PHY_DX7GCR0_DQSNSEPDR                                                   0x0
9871
9872                 DQSSE Power Down Receiver
9873                 PSU_DDR_PHY_DX7GCR0_DQSSEPDR                                                    0x0
9874
9875                 RTT On Additive Latency
9876                 PSU_DDR_PHY_DX7GCR0_RTTOAL                                                      0x0
9877
9878                 RTT Output Hold
9879                 PSU_DDR_PHY_DX7GCR0_RTTOH                                                       0x3
9880
9881                 Configurable PDR Phase Shift
9882                 PSU_DDR_PHY_DX7GCR0_CPDRSHFT                                                    0x0
9883
9884                 DQSR Power Down
9885                 PSU_DDR_PHY_DX7GCR0_DQSRPD                                                      0x0
9886
9887                 DQSG Power Down Receiver
9888                 PSU_DDR_PHY_DX7GCR0_DQSGPDR                                                     0x0
9889
9890                 Reserved. Return zeroes on reads.
9891                 PSU_DDR_PHY_DX7GCR0_RESERVED_4                                                  0x0
9892
9893                 DQSG On-Die Termination
9894                 PSU_DDR_PHY_DX7GCR0_DQSGODT                                                     0x0
9895
9896                 DQSG Output Enable
9897                 PSU_DDR_PHY_DX7GCR0_DQSGOE                                                      0x1
9898
9899                 Reserved. Return zeroes on reads.
9900                 PSU_DDR_PHY_DX7GCR0_RESERVED_1_0                                                0x0
9901
9902                 DATX8 n General Configuration Register 0
9903                 (OFFSET, MASK, VALUE)      (0XFD080E00, 0xFFFFFFFFU ,0x40800604U)
9904                 RegMask = (DDR_PHY_DX7GCR0_CALBYP_MASK | DDR_PHY_DX7GCR0_MDLEN_MASK | DDR_PHY_DX7GCR0_CODTSHFT_MASK | DDR_PHY_DX7GCR0_DQSDCC_MASK | DDR_PHY_DX7GCR0_RDDLY_MASK | DDR_PHY_DX7GCR0_RESERVED_19_14_MASK | DDR_PHY_DX7GCR0_DQSNSEPDR_MASK | DDR_PHY_DX7GCR0_DQSSEPDR_MASK | DDR_PHY_DX7GCR0_RTTOAL_MASK | DDR_PHY_DX7GCR0_RTTOH_MASK | DDR_PHY_DX7GCR0_CPDRSHFT_MASK | DDR_PHY_DX7GCR0_DQSRPD_MASK | DDR_PHY_DX7GCR0_DQSGPDR_MASK | DDR_PHY_DX7GCR0_RESERVED_4_MASK | DDR_PHY_DX7GCR0_DQSGODT_MASK | DDR_PHY_DX7GCR0_DQSGOE_MASK | DDR_PHY_DX7GCR0_RESERVED_1_0_MASK |  0 );
9905
9906                 RegVal = ((0x00000000U << DDR_PHY_DX7GCR0_CALBYP_SHIFT
9907                         | 0x00000001U << DDR_PHY_DX7GCR0_MDLEN_SHIFT
9908                         | 0x00000000U << DDR_PHY_DX7GCR0_CODTSHFT_SHIFT
9909                         | 0x00000000U << DDR_PHY_DX7GCR0_DQSDCC_SHIFT
9910                         | 0x00000008U << DDR_PHY_DX7GCR0_RDDLY_SHIFT
9911                         | 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT
9912                         | 0x00000000U << DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT
9913                         | 0x00000000U << DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT
9914                         | 0x00000000U << DDR_PHY_DX7GCR0_RTTOAL_SHIFT
9915                         | 0x00000003U << DDR_PHY_DX7GCR0_RTTOH_SHIFT
9916                         | 0x00000000U << DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT
9917                         | 0x00000000U << DDR_PHY_DX7GCR0_DQSRPD_SHIFT
9918                         | 0x00000000U << DDR_PHY_DX7GCR0_DQSGPDR_SHIFT
9919                         | 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_4_SHIFT
9920                         | 0x00000000U << DDR_PHY_DX7GCR0_DQSGODT_SHIFT
9921                         | 0x00000001U << DDR_PHY_DX7GCR0_DQSGOE_SHIFT
9922                         | 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT
9923                         |  0 ) & RegMask); */
9924                 PSU_Mask_Write (DDR_PHY_DX7GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
9925         /*############################################################################################################################ */
9926
9927                 /*Register : DX7GCR1 @ 0XFD080E04</p>
9928
9929                 Enables the PDR mode for DQ[7:0]
9930                 PSU_DDR_PHY_DX7GCR1_DXPDRMODE                                                   0x0
9931
9932                 Reserved. Returns zeroes on reads.
9933                 PSU_DDR_PHY_DX7GCR1_RESERVED_15                                                 0x0
9934
9935                 Select the delayed or non-delayed read data strobe #
9936                 PSU_DDR_PHY_DX7GCR1_QSNSEL                                                      0x1
9937
9938                 Select the delayed or non-delayed read data strobe
9939                 PSU_DDR_PHY_DX7GCR1_QSSEL                                                       0x1
9940
9941                 Enables Read Data Strobe in a byte lane
9942                 PSU_DDR_PHY_DX7GCR1_OEEN                                                        0x1
9943
9944                 Enables PDR in a byte lane
9945                 PSU_DDR_PHY_DX7GCR1_PDREN                                                       0x1
9946
9947                 Enables ODT/TE in a byte lane
9948                 PSU_DDR_PHY_DX7GCR1_TEEN                                                        0x1
9949
9950                 Enables Write Data strobe in a byte lane
9951                 PSU_DDR_PHY_DX7GCR1_DSEN                                                        0x1
9952
9953                 Enables DM pin in a byte lane
9954                 PSU_DDR_PHY_DX7GCR1_DMEN                                                        0x1
9955
9956                 Enables DQ corresponding to each bit in a byte
9957                 PSU_DDR_PHY_DX7GCR1_DQEN                                                        0xff
9958
9959                 DATX8 n General Configuration Register 1
9960                 (OFFSET, MASK, VALUE)      (0XFD080E04, 0xFFFFFFFFU ,0x00007FFFU)
9961                 RegMask = (DDR_PHY_DX7GCR1_DXPDRMODE_MASK | DDR_PHY_DX7GCR1_RESERVED_15_MASK | DDR_PHY_DX7GCR1_QSNSEL_MASK | DDR_PHY_DX7GCR1_QSSEL_MASK | DDR_PHY_DX7GCR1_OEEN_MASK | DDR_PHY_DX7GCR1_PDREN_MASK | DDR_PHY_DX7GCR1_TEEN_MASK | DDR_PHY_DX7GCR1_DSEN_MASK | DDR_PHY_DX7GCR1_DMEN_MASK | DDR_PHY_DX7GCR1_DQEN_MASK |  0 );
9962
9963                 RegVal = ((0x00000000U << DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT
9964                         | 0x00000000U << DDR_PHY_DX7GCR1_RESERVED_15_SHIFT
9965                         | 0x00000001U << DDR_PHY_DX7GCR1_QSNSEL_SHIFT
9966                         | 0x00000001U << DDR_PHY_DX7GCR1_QSSEL_SHIFT
9967                         | 0x00000001U << DDR_PHY_DX7GCR1_OEEN_SHIFT
9968                         | 0x00000001U << DDR_PHY_DX7GCR1_PDREN_SHIFT
9969                         | 0x00000001U << DDR_PHY_DX7GCR1_TEEN_SHIFT
9970                         | 0x00000001U << DDR_PHY_DX7GCR1_DSEN_SHIFT
9971                         | 0x00000001U << DDR_PHY_DX7GCR1_DMEN_SHIFT
9972                         | 0x000000FFU << DDR_PHY_DX7GCR1_DQEN_SHIFT
9973                         |  0 ) & RegMask); */
9974                 PSU_Mask_Write (DDR_PHY_DX7GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
9975         /*############################################################################################################################ */
9976
9977                 /*Register : DX7GCR4 @ 0XFD080E10</p>
9978
9979                 Byte lane VREF IOM (Used only by D4MU IOs)
9980                 PSU_DDR_PHY_DX7GCR4_RESERVED_31_29                                              0x0
9981
9982                 Byte Lane VREF Pad Enable
9983                 PSU_DDR_PHY_DX7GCR4_DXREFPEN                                                    0x0
9984
9985                 Byte Lane Internal VREF Enable
9986                 PSU_DDR_PHY_DX7GCR4_DXREFEEN                                                    0x3
9987
9988                 Byte Lane Single-End VREF Enable
9989                 PSU_DDR_PHY_DX7GCR4_DXREFSEN                                                    0x1
9990
9991                 Reserved. Returns zeros on reads.
9992                 PSU_DDR_PHY_DX7GCR4_RESERVED_24                                                 0x0
9993
9994                 External VREF generator REFSEL range select
9995                 PSU_DDR_PHY_DX7GCR4_DXREFESELRANGE                                              0x0
9996
9997                 Byte Lane External VREF Select
9998                 PSU_DDR_PHY_DX7GCR4_DXREFESEL                                                   0x0
9999
10000                 Single ended VREF generator REFSEL range select
10001                 PSU_DDR_PHY_DX7GCR4_DXREFSSELRANGE                                              0x1
10002
10003                 Byte Lane Single-End VREF Select
10004                 PSU_DDR_PHY_DX7GCR4_DXREFSSEL                                                   0x30
10005
10006                 Reserved. Returns zeros on reads.
10007                 PSU_DDR_PHY_DX7GCR4_RESERVED_7_6                                                0x0
10008
10009                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
10010                 PSU_DDR_PHY_DX7GCR4_DXREFIEN                                                    0xf
10011
10012                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
10013                 PSU_DDR_PHY_DX7GCR4_DXREFIMON                                                   0x0
10014
10015                 DATX8 n General Configuration Register 4
10016                 (OFFSET, MASK, VALUE)      (0XFD080E10, 0xFFFFFFFFU ,0x0E00B03CU)
10017                 RegMask = (DDR_PHY_DX7GCR4_RESERVED_31_29_MASK | DDR_PHY_DX7GCR4_DXREFPEN_MASK | DDR_PHY_DX7GCR4_DXREFEEN_MASK | DDR_PHY_DX7GCR4_DXREFSEN_MASK | DDR_PHY_DX7GCR4_RESERVED_24_MASK | DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX7GCR4_DXREFESEL_MASK | DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX7GCR4_DXREFSSEL_MASK | DDR_PHY_DX7GCR4_RESERVED_7_6_MASK | DDR_PHY_DX7GCR4_DXREFIEN_MASK | DDR_PHY_DX7GCR4_DXREFIMON_MASK |  0 );
10018
10019                 RegVal = ((0x00000000U << DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT
10020                         | 0x00000000U << DDR_PHY_DX7GCR4_DXREFPEN_SHIFT
10021                         | 0x00000003U << DDR_PHY_DX7GCR4_DXREFEEN_SHIFT
10022                         | 0x00000001U << DDR_PHY_DX7GCR4_DXREFSEN_SHIFT
10023                         | 0x00000000U << DDR_PHY_DX7GCR4_RESERVED_24_SHIFT
10024                         | 0x00000000U << DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT
10025                         | 0x00000000U << DDR_PHY_DX7GCR4_DXREFESEL_SHIFT
10026                         | 0x00000001U << DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT
10027                         | 0x00000030U << DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT
10028                         | 0x00000000U << DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT
10029                         | 0x0000000FU << DDR_PHY_DX7GCR4_DXREFIEN_SHIFT
10030                         | 0x00000000U << DDR_PHY_DX7GCR4_DXREFIMON_SHIFT
10031                         |  0 ) & RegMask); */
10032                 PSU_Mask_Write (DDR_PHY_DX7GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
10033         /*############################################################################################################################ */
10034
10035                 /*Register : DX7GCR5 @ 0XFD080E14</p>
10036
10037                 Reserved. Returns zeros on reads.
10038                 PSU_DDR_PHY_DX7GCR5_RESERVED_31                                                 0x0
10039
10040                 Byte Lane internal VREF Select for Rank 3
10041                 PSU_DDR_PHY_DX7GCR5_DXREFISELR3                                                 0x9
10042
10043                 Reserved. Returns zeros on reads.
10044                 PSU_DDR_PHY_DX7GCR5_RESERVED_23                                                 0x0
10045
10046                 Byte Lane internal VREF Select for Rank 2
10047                 PSU_DDR_PHY_DX7GCR5_DXREFISELR2                                                 0x9
10048
10049                 Reserved. Returns zeros on reads.
10050                 PSU_DDR_PHY_DX7GCR5_RESERVED_15                                                 0x0
10051
10052                 Byte Lane internal VREF Select for Rank 1
10053                 PSU_DDR_PHY_DX7GCR5_DXREFISELR1                                                 0x4f
10054
10055                 Reserved. Returns zeros on reads.
10056                 PSU_DDR_PHY_DX7GCR5_RESERVED_7                                                  0x0
10057
10058                 Byte Lane internal VREF Select for Rank 0
10059                 PSU_DDR_PHY_DX7GCR5_DXREFISELR0                                                 0x4f
10060
10061                 DATX8 n General Configuration Register 5
10062                 (OFFSET, MASK, VALUE)      (0XFD080E14, 0xFFFFFFFFU ,0x09094F4FU)
10063                 RegMask = (DDR_PHY_DX7GCR5_RESERVED_31_MASK | DDR_PHY_DX7GCR5_DXREFISELR3_MASK | DDR_PHY_DX7GCR5_RESERVED_23_MASK | DDR_PHY_DX7GCR5_DXREFISELR2_MASK | DDR_PHY_DX7GCR5_RESERVED_15_MASK | DDR_PHY_DX7GCR5_DXREFISELR1_MASK | DDR_PHY_DX7GCR5_RESERVED_7_MASK | DDR_PHY_DX7GCR5_DXREFISELR0_MASK |  0 );
10064
10065                 RegVal = ((0x00000000U << DDR_PHY_DX7GCR5_RESERVED_31_SHIFT
10066                         | 0x00000009U << DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT
10067                         | 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_23_SHIFT
10068                         | 0x00000009U << DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT
10069                         | 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_15_SHIFT
10070                         | 0x0000004FU << DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT
10071                         | 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_7_SHIFT
10072                         | 0x0000004FU << DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT
10073                         |  0 ) & RegMask); */
10074                 PSU_Mask_Write (DDR_PHY_DX7GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
10075         /*############################################################################################################################ */
10076
10077                 /*Register : DX7GCR6 @ 0XFD080E18</p>
10078
10079                 Reserved. Returns zeros on reads.
10080                 PSU_DDR_PHY_DX7GCR6_RESERVED_31_30                                              0x0
10081
10082                 DRAM DQ VREF Select for Rank3
10083                 PSU_DDR_PHY_DX7GCR6_DXDQVREFR3                                                  0x9
10084
10085                 Reserved. Returns zeros on reads.
10086                 PSU_DDR_PHY_DX7GCR6_RESERVED_23_22                                              0x0
10087
10088                 DRAM DQ VREF Select for Rank2
10089                 PSU_DDR_PHY_DX7GCR6_DXDQVREFR2                                                  0x9
10090
10091                 Reserved. Returns zeros on reads.
10092                 PSU_DDR_PHY_DX7GCR6_RESERVED_15_14                                              0x0
10093
10094                 DRAM DQ VREF Select for Rank1
10095                 PSU_DDR_PHY_DX7GCR6_DXDQVREFR1                                                  0x2b
10096
10097                 Reserved. Returns zeros on reads.
10098                 PSU_DDR_PHY_DX7GCR6_RESERVED_7_6                                                0x0
10099
10100                 DRAM DQ VREF Select for Rank0
10101                 PSU_DDR_PHY_DX7GCR6_DXDQVREFR0                                                  0x2b
10102
10103                 DATX8 n General Configuration Register 6
10104                 (OFFSET, MASK, VALUE)      (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU)
10105                 RegMask = (DDR_PHY_DX7GCR6_RESERVED_31_30_MASK | DDR_PHY_DX7GCR6_DXDQVREFR3_MASK | DDR_PHY_DX7GCR6_RESERVED_23_22_MASK | DDR_PHY_DX7GCR6_DXDQVREFR2_MASK | DDR_PHY_DX7GCR6_RESERVED_15_14_MASK | DDR_PHY_DX7GCR6_DXDQVREFR1_MASK | DDR_PHY_DX7GCR6_RESERVED_7_6_MASK | DDR_PHY_DX7GCR6_DXDQVREFR0_MASK |  0 );
10106
10107                 RegVal = ((0x00000000U << DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT
10108                         | 0x00000009U << DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT
10109                         | 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT
10110                         | 0x00000009U << DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT
10111                         | 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT
10112                         | 0x0000002BU << DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT
10113                         | 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT
10114                         | 0x0000002BU << DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT
10115                         |  0 ) & RegMask); */
10116                 PSU_Mask_Write (DDR_PHY_DX7GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
10117         /*############################################################################################################################ */
10118
10119                 /*Register : DX7LCDLR2 @ 0XFD080E88</p>
10120
10121                 Reserved. Return zeroes on reads.
10122                 PSU_DDR_PHY_DX7LCDLR2_RESERVED_31_25                                            0x0
10123
10124                 Reserved. Caution, do not write to this register field.
10125                 PSU_DDR_PHY_DX7LCDLR2_RESERVED_24_16                                            0x0
10126
10127                 Reserved. Return zeroes on reads.
10128                 PSU_DDR_PHY_DX7LCDLR2_RESERVED_15_9                                             0x0
10129
10130                 Read DQS Gating Delay
10131                 PSU_DDR_PHY_DX7LCDLR2_DQSGD                                                     0xa
10132
10133                 DATX8 n Local Calibrated Delay Line Register 2
10134                 (OFFSET, MASK, VALUE)      (0XFD080E88, 0xFFFFFFFFU ,0x0000000AU)
10135                 RegMask = (DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX7LCDLR2_DQSGD_MASK |  0 );
10136
10137                 RegVal = ((0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT
10138                         | 0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT
10139                         | 0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT
10140                         | 0x0000000AU << DDR_PHY_DX7LCDLR2_DQSGD_SHIFT
10141                         |  0 ) & RegMask); */
10142                 PSU_Mask_Write (DDR_PHY_DX7LCDLR2_OFFSET ,0xFFFFFFFFU ,0x0000000AU);
10143         /*############################################################################################################################ */
10144
10145                 /*Register : DX7GTR0 @ 0XFD080EC0</p>
10146
10147                 Reserved. Return zeroes on reads.
10148                 PSU_DDR_PHY_DX7GTR0_RESERVED_31_24                                              0x0
10149
10150                 DQ Write Path Latency Pipeline
10151                 PSU_DDR_PHY_DX7GTR0_WDQSL                                                       0x0
10152
10153                 Reserved. Caution, do not write to this register field.
10154                 PSU_DDR_PHY_DX7GTR0_RESERVED_23_20                                              0x0
10155
10156                 Write Leveling System Latency
10157                 PSU_DDR_PHY_DX7GTR0_WLSL                                                        0x2
10158
10159                 Reserved. Return zeroes on reads.
10160                 PSU_DDR_PHY_DX7GTR0_RESERVED_15_13                                              0x0
10161
10162                 Reserved. Caution, do not write to this register field.
10163                 PSU_DDR_PHY_DX7GTR0_RESERVED_12_8                                               0x0
10164
10165                 Reserved. Return zeroes on reads.
10166                 PSU_DDR_PHY_DX7GTR0_RESERVED_7_5                                                0x0
10167
10168                 DQS Gating System Latency
10169                 PSU_DDR_PHY_DX7GTR0_DGSL                                                        0x0
10170
10171                 DATX8 n General Timing Register 0
10172                 (OFFSET, MASK, VALUE)      (0XFD080EC0, 0xFFFFFFFFU ,0x00020000U)
10173                 RegMask = (DDR_PHY_DX7GTR0_RESERVED_31_24_MASK | DDR_PHY_DX7GTR0_WDQSL_MASK | DDR_PHY_DX7GTR0_RESERVED_23_20_MASK | DDR_PHY_DX7GTR0_WLSL_MASK | DDR_PHY_DX7GTR0_RESERVED_15_13_MASK | DDR_PHY_DX7GTR0_RESERVED_12_8_MASK | DDR_PHY_DX7GTR0_RESERVED_7_5_MASK | DDR_PHY_DX7GTR0_DGSL_MASK |  0 );
10174
10175                 RegVal = ((0x00000000U << DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT
10176                         | 0x00000000U << DDR_PHY_DX7GTR0_WDQSL_SHIFT
10177                         | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT
10178                         | 0x00000002U << DDR_PHY_DX7GTR0_WLSL_SHIFT
10179                         | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT
10180                         | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT
10181                         | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT
10182                         | 0x00000000U << DDR_PHY_DX7GTR0_DGSL_SHIFT
10183                         |  0 ) & RegMask); */
10184                 PSU_Mask_Write (DDR_PHY_DX7GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
10185         /*############################################################################################################################ */
10186
10187                 /*Register : DX8GCR0 @ 0XFD080F00</p>
10188
10189                 Calibration Bypass
10190                 PSU_DDR_PHY_DX8GCR0_CALBYP                                                      0x0
10191
10192                 Master Delay Line Enable
10193                 PSU_DDR_PHY_DX8GCR0_MDLEN                                                       0x1
10194
10195                 Configurable ODT(TE) Phase Shift
10196                 PSU_DDR_PHY_DX8GCR0_CODTSHFT                                                    0x0
10197
10198                 DQS Duty Cycle Correction
10199                 PSU_DDR_PHY_DX8GCR0_DQSDCC                                                      0x0
10200
10201                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
10202                 PSU_DDR_PHY_DX8GCR0_RDDLY                                                       0x8
10203
10204                 Reserved. Return zeroes on reads.
10205                 PSU_DDR_PHY_DX8GCR0_RESERVED_19_14                                              0x0
10206
10207                 DQSNSE Power Down Receiver
10208                 PSU_DDR_PHY_DX8GCR0_DQSNSEPDR                                                   0x0
10209
10210                 DQSSE Power Down Receiver
10211                 PSU_DDR_PHY_DX8GCR0_DQSSEPDR                                                    0x0
10212
10213                 RTT On Additive Latency
10214                 PSU_DDR_PHY_DX8GCR0_RTTOAL                                                      0x0
10215
10216                 RTT Output Hold
10217                 PSU_DDR_PHY_DX8GCR0_RTTOH                                                       0x3
10218
10219                 Configurable PDR Phase Shift
10220                 PSU_DDR_PHY_DX8GCR0_CPDRSHFT                                                    0x0
10221
10222                 DQSR Power Down
10223                 PSU_DDR_PHY_DX8GCR0_DQSRPD                                                      0x0
10224
10225                 DQSG Power Down Receiver
10226                 PSU_DDR_PHY_DX8GCR0_DQSGPDR                                                     0x1
10227
10228                 Reserved. Return zeroes on reads.
10229                 PSU_DDR_PHY_DX8GCR0_RESERVED_4                                                  0x0
10230
10231                 DQSG On-Die Termination
10232                 PSU_DDR_PHY_DX8GCR0_DQSGODT                                                     0x0
10233
10234                 DQSG Output Enable
10235                 PSU_DDR_PHY_DX8GCR0_DQSGOE                                                      0x1
10236
10237                 Reserved. Return zeroes on reads.
10238                 PSU_DDR_PHY_DX8GCR0_RESERVED_1_0                                                0x0
10239
10240                 DATX8 n General Configuration Register 0
10241                 (OFFSET, MASK, VALUE)      (0XFD080F00, 0xFFFFFFFFU ,0x40800624U)
10242                 RegMask = (DDR_PHY_DX8GCR0_CALBYP_MASK | DDR_PHY_DX8GCR0_MDLEN_MASK | DDR_PHY_DX8GCR0_CODTSHFT_MASK | DDR_PHY_DX8GCR0_DQSDCC_MASK | DDR_PHY_DX8GCR0_RDDLY_MASK | DDR_PHY_DX8GCR0_RESERVED_19_14_MASK | DDR_PHY_DX8GCR0_DQSNSEPDR_MASK | DDR_PHY_DX8GCR0_DQSSEPDR_MASK | DDR_PHY_DX8GCR0_RTTOAL_MASK | DDR_PHY_DX8GCR0_RTTOH_MASK | DDR_PHY_DX8GCR0_CPDRSHFT_MASK | DDR_PHY_DX8GCR0_DQSRPD_MASK | DDR_PHY_DX8GCR0_DQSGPDR_MASK | DDR_PHY_DX8GCR0_RESERVED_4_MASK | DDR_PHY_DX8GCR0_DQSGODT_MASK | DDR_PHY_DX8GCR0_DQSGOE_MASK | DDR_PHY_DX8GCR0_RESERVED_1_0_MASK |  0 );
10243
10244                 RegVal = ((0x00000000U << DDR_PHY_DX8GCR0_CALBYP_SHIFT
10245                         | 0x00000001U << DDR_PHY_DX8GCR0_MDLEN_SHIFT
10246                         | 0x00000000U << DDR_PHY_DX8GCR0_CODTSHFT_SHIFT
10247                         | 0x00000000U << DDR_PHY_DX8GCR0_DQSDCC_SHIFT
10248                         | 0x00000008U << DDR_PHY_DX8GCR0_RDDLY_SHIFT
10249                         | 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT
10250                         | 0x00000000U << DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT
10251                         | 0x00000000U << DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT
10252                         | 0x00000000U << DDR_PHY_DX8GCR0_RTTOAL_SHIFT
10253                         | 0x00000003U << DDR_PHY_DX8GCR0_RTTOH_SHIFT
10254                         | 0x00000000U << DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT
10255                         | 0x00000000U << DDR_PHY_DX8GCR0_DQSRPD_SHIFT
10256                         | 0x00000001U << DDR_PHY_DX8GCR0_DQSGPDR_SHIFT
10257                         | 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_4_SHIFT
10258                         | 0x00000000U << DDR_PHY_DX8GCR0_DQSGODT_SHIFT
10259                         | 0x00000001U << DDR_PHY_DX8GCR0_DQSGOE_SHIFT
10260                         | 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT
10261                         |  0 ) & RegMask); */
10262                 PSU_Mask_Write (DDR_PHY_DX8GCR0_OFFSET ,0xFFFFFFFFU ,0x40800624U);
10263         /*############################################################################################################################ */
10264
10265                 /*Register : DX8GCR1 @ 0XFD080F04</p>
10266
10267                 Enables the PDR mode for DQ[7:0]
10268                 PSU_DDR_PHY_DX8GCR1_DXPDRMODE                                                   0x0
10269
10270                 Reserved. Returns zeroes on reads.
10271                 PSU_DDR_PHY_DX8GCR1_RESERVED_15                                                 0x0
10272
10273                 Select the delayed or non-delayed read data strobe #
10274                 PSU_DDR_PHY_DX8GCR1_QSNSEL                                                      0x1
10275
10276                 Select the delayed or non-delayed read data strobe
10277                 PSU_DDR_PHY_DX8GCR1_QSSEL                                                       0x1
10278
10279                 Enables Read Data Strobe in a byte lane
10280                 PSU_DDR_PHY_DX8GCR1_OEEN                                                        0x1
10281
10282                 Enables PDR in a byte lane
10283                 PSU_DDR_PHY_DX8GCR1_PDREN                                                       0x1
10284
10285                 Enables ODT/TE in a byte lane
10286                 PSU_DDR_PHY_DX8GCR1_TEEN                                                        0x1
10287
10288                 Enables Write Data strobe in a byte lane
10289                 PSU_DDR_PHY_DX8GCR1_DSEN                                                        0x1
10290
10291                 Enables DM pin in a byte lane
10292                 PSU_DDR_PHY_DX8GCR1_DMEN                                                        0x1
10293
10294                 Enables DQ corresponding to each bit in a byte
10295                 PSU_DDR_PHY_DX8GCR1_DQEN                                                        0x0
10296
10297                 DATX8 n General Configuration Register 1
10298                 (OFFSET, MASK, VALUE)      (0XFD080F04, 0xFFFFFFFFU ,0x00007F00U)
10299                 RegMask = (DDR_PHY_DX8GCR1_DXPDRMODE_MASK | DDR_PHY_DX8GCR1_RESERVED_15_MASK | DDR_PHY_DX8GCR1_QSNSEL_MASK | DDR_PHY_DX8GCR1_QSSEL_MASK | DDR_PHY_DX8GCR1_OEEN_MASK | DDR_PHY_DX8GCR1_PDREN_MASK | DDR_PHY_DX8GCR1_TEEN_MASK | DDR_PHY_DX8GCR1_DSEN_MASK | DDR_PHY_DX8GCR1_DMEN_MASK | DDR_PHY_DX8GCR1_DQEN_MASK |  0 );
10300
10301                 RegVal = ((0x00000000U << DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT
10302                         | 0x00000000U << DDR_PHY_DX8GCR1_RESERVED_15_SHIFT
10303                         | 0x00000001U << DDR_PHY_DX8GCR1_QSNSEL_SHIFT
10304                         | 0x00000001U << DDR_PHY_DX8GCR1_QSSEL_SHIFT
10305                         | 0x00000001U << DDR_PHY_DX8GCR1_OEEN_SHIFT
10306                         | 0x00000001U << DDR_PHY_DX8GCR1_PDREN_SHIFT
10307                         | 0x00000001U << DDR_PHY_DX8GCR1_TEEN_SHIFT
10308                         | 0x00000001U << DDR_PHY_DX8GCR1_DSEN_SHIFT
10309                         | 0x00000001U << DDR_PHY_DX8GCR1_DMEN_SHIFT
10310                         | 0x00000000U << DDR_PHY_DX8GCR1_DQEN_SHIFT
10311                         |  0 ) & RegMask); */
10312                 PSU_Mask_Write (DDR_PHY_DX8GCR1_OFFSET ,0xFFFFFFFFU ,0x00007F00U);
10313         /*############################################################################################################################ */
10314
10315                 /*Register : DX8GCR4 @ 0XFD080F10</p>
10316
10317                 Byte lane VREF IOM (Used only by D4MU IOs)
10318                 PSU_DDR_PHY_DX8GCR4_RESERVED_31_29                                              0x0
10319
10320                 Byte Lane VREF Pad Enable
10321                 PSU_DDR_PHY_DX8GCR4_DXREFPEN                                                    0x0
10322
10323                 Byte Lane Internal VREF Enable
10324                 PSU_DDR_PHY_DX8GCR4_DXREFEEN                                                    0x3
10325
10326                 Byte Lane Single-End VREF Enable
10327                 PSU_DDR_PHY_DX8GCR4_DXREFSEN                                                    0x1
10328
10329                 Reserved. Returns zeros on reads.
10330                 PSU_DDR_PHY_DX8GCR4_RESERVED_24                                                 0x0
10331
10332                 External VREF generator REFSEL range select
10333                 PSU_DDR_PHY_DX8GCR4_DXREFESELRANGE                                              0x0
10334
10335                 Byte Lane External VREF Select
10336                 PSU_DDR_PHY_DX8GCR4_DXREFESEL                                                   0x0
10337
10338                 Single ended VREF generator REFSEL range select
10339                 PSU_DDR_PHY_DX8GCR4_DXREFSSELRANGE                                              0x1
10340
10341                 Byte Lane Single-End VREF Select
10342                 PSU_DDR_PHY_DX8GCR4_DXREFSSEL                                                   0x30
10343
10344                 Reserved. Returns zeros on reads.
10345                 PSU_DDR_PHY_DX8GCR4_RESERVED_7_6                                                0x0
10346
10347                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
10348                 PSU_DDR_PHY_DX8GCR4_DXREFIEN                                                    0xf
10349
10350                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
10351                 PSU_DDR_PHY_DX8GCR4_DXREFIMON                                                   0x0
10352
10353                 DATX8 n General Configuration Register 4
10354                 (OFFSET, MASK, VALUE)      (0XFD080F10, 0xFFFFFFFFU ,0x0E00B03CU)
10355                 RegMask = (DDR_PHY_DX8GCR4_RESERVED_31_29_MASK | DDR_PHY_DX8GCR4_DXREFPEN_MASK | DDR_PHY_DX8GCR4_DXREFEEN_MASK | DDR_PHY_DX8GCR4_DXREFSEN_MASK | DDR_PHY_DX8GCR4_RESERVED_24_MASK | DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX8GCR4_DXREFESEL_MASK | DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX8GCR4_DXREFSSEL_MASK | DDR_PHY_DX8GCR4_RESERVED_7_6_MASK | DDR_PHY_DX8GCR4_DXREFIEN_MASK | DDR_PHY_DX8GCR4_DXREFIMON_MASK |  0 );
10356
10357                 RegVal = ((0x00000000U << DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT
10358                         | 0x00000000U << DDR_PHY_DX8GCR4_DXREFPEN_SHIFT
10359                         | 0x00000003U << DDR_PHY_DX8GCR4_DXREFEEN_SHIFT
10360                         | 0x00000001U << DDR_PHY_DX8GCR4_DXREFSEN_SHIFT
10361                         | 0x00000000U << DDR_PHY_DX8GCR4_RESERVED_24_SHIFT
10362                         | 0x00000000U << DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT
10363                         | 0x00000000U << DDR_PHY_DX8GCR4_DXREFESEL_SHIFT
10364                         | 0x00000001U << DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT
10365                         | 0x00000030U << DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT
10366                         | 0x00000000U << DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT
10367                         | 0x0000000FU << DDR_PHY_DX8GCR4_DXREFIEN_SHIFT
10368                         | 0x00000000U << DDR_PHY_DX8GCR4_DXREFIMON_SHIFT
10369                         |  0 ) & RegMask); */
10370                 PSU_Mask_Write (DDR_PHY_DX8GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
10371         /*############################################################################################################################ */
10372
10373                 /*Register : DX8GCR5 @ 0XFD080F14</p>
10374
10375                 Reserved. Returns zeros on reads.
10376                 PSU_DDR_PHY_DX8GCR5_RESERVED_31                                                 0x0
10377
10378                 Byte Lane internal VREF Select for Rank 3
10379                 PSU_DDR_PHY_DX8GCR5_DXREFISELR3                                                 0x9
10380
10381                 Reserved. Returns zeros on reads.
10382                 PSU_DDR_PHY_DX8GCR5_RESERVED_23                                                 0x0
10383
10384                 Byte Lane internal VREF Select for Rank 2
10385                 PSU_DDR_PHY_DX8GCR5_DXREFISELR2                                                 0x9
10386
10387                 Reserved. Returns zeros on reads.
10388                 PSU_DDR_PHY_DX8GCR5_RESERVED_15                                                 0x0
10389
10390                 Byte Lane internal VREF Select for Rank 1
10391                 PSU_DDR_PHY_DX8GCR5_DXREFISELR1                                                 0x4f
10392
10393                 Reserved. Returns zeros on reads.
10394                 PSU_DDR_PHY_DX8GCR5_RESERVED_7                                                  0x0
10395
10396                 Byte Lane internal VREF Select for Rank 0
10397                 PSU_DDR_PHY_DX8GCR5_DXREFISELR0                                                 0x4f
10398
10399                 DATX8 n General Configuration Register 5
10400                 (OFFSET, MASK, VALUE)      (0XFD080F14, 0xFFFFFFFFU ,0x09094F4FU)
10401                 RegMask = (DDR_PHY_DX8GCR5_RESERVED_31_MASK | DDR_PHY_DX8GCR5_DXREFISELR3_MASK | DDR_PHY_DX8GCR5_RESERVED_23_MASK | DDR_PHY_DX8GCR5_DXREFISELR2_MASK | DDR_PHY_DX8GCR5_RESERVED_15_MASK | DDR_PHY_DX8GCR5_DXREFISELR1_MASK | DDR_PHY_DX8GCR5_RESERVED_7_MASK | DDR_PHY_DX8GCR5_DXREFISELR0_MASK |  0 );
10402
10403                 RegVal = ((0x00000000U << DDR_PHY_DX8GCR5_RESERVED_31_SHIFT
10404                         | 0x00000009U << DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT
10405                         | 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_23_SHIFT
10406                         | 0x00000009U << DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT
10407                         | 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_15_SHIFT
10408                         | 0x0000004FU << DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT
10409                         | 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_7_SHIFT
10410                         | 0x0000004FU << DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT
10411                         |  0 ) & RegMask); */
10412                 PSU_Mask_Write (DDR_PHY_DX8GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU);
10413         /*############################################################################################################################ */
10414
10415                 /*Register : DX8GCR6 @ 0XFD080F18</p>
10416
10417                 Reserved. Returns zeros on reads.
10418                 PSU_DDR_PHY_DX8GCR6_RESERVED_31_30                                              0x0
10419
10420                 DRAM DQ VREF Select for Rank3
10421                 PSU_DDR_PHY_DX8GCR6_DXDQVREFR3                                                  0x9
10422
10423                 Reserved. Returns zeros on reads.
10424                 PSU_DDR_PHY_DX8GCR6_RESERVED_23_22                                              0x0
10425
10426                 DRAM DQ VREF Select for Rank2
10427                 PSU_DDR_PHY_DX8GCR6_DXDQVREFR2                                                  0x9
10428
10429                 Reserved. Returns zeros on reads.
10430                 PSU_DDR_PHY_DX8GCR6_RESERVED_15_14                                              0x0
10431
10432                 DRAM DQ VREF Select for Rank1
10433                 PSU_DDR_PHY_DX8GCR6_DXDQVREFR1                                                  0x2b
10434
10435                 Reserved. Returns zeros on reads.
10436                 PSU_DDR_PHY_DX8GCR6_RESERVED_7_6                                                0x0
10437
10438                 DRAM DQ VREF Select for Rank0
10439                 PSU_DDR_PHY_DX8GCR6_DXDQVREFR0                                                  0x2b
10440
10441                 DATX8 n General Configuration Register 6
10442                 (OFFSET, MASK, VALUE)      (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU)
10443                 RegMask = (DDR_PHY_DX8GCR6_RESERVED_31_30_MASK | DDR_PHY_DX8GCR6_DXDQVREFR3_MASK | DDR_PHY_DX8GCR6_RESERVED_23_22_MASK | DDR_PHY_DX8GCR6_DXDQVREFR2_MASK | DDR_PHY_DX8GCR6_RESERVED_15_14_MASK | DDR_PHY_DX8GCR6_DXDQVREFR1_MASK | DDR_PHY_DX8GCR6_RESERVED_7_6_MASK | DDR_PHY_DX8GCR6_DXDQVREFR0_MASK |  0 );
10444
10445                 RegVal = ((0x00000000U << DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT
10446                         | 0x00000009U << DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT
10447                         | 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT
10448                         | 0x00000009U << DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT
10449                         | 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT
10450                         | 0x0000002BU << DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT
10451                         | 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT
10452                         | 0x0000002BU << DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT
10453                         |  0 ) & RegMask); */
10454                 PSU_Mask_Write (DDR_PHY_DX8GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
10455         /*############################################################################################################################ */
10456
10457                 /*Register : DX8LCDLR2 @ 0XFD080F88</p>
10458
10459                 Reserved. Return zeroes on reads.
10460                 PSU_DDR_PHY_DX8LCDLR2_RESERVED_31_25                                            0x0
10461
10462                 Reserved. Caution, do not write to this register field.
10463                 PSU_DDR_PHY_DX8LCDLR2_RESERVED_24_16                                            0x0
10464
10465                 Reserved. Return zeroes on reads.
10466                 PSU_DDR_PHY_DX8LCDLR2_RESERVED_15_9                                             0x0
10467
10468                 Read DQS Gating Delay
10469                 PSU_DDR_PHY_DX8LCDLR2_DQSGD                                                     0x0
10470
10471                 DATX8 n Local Calibrated Delay Line Register 2
10472                 (OFFSET, MASK, VALUE)      (0XFD080F88, 0xFFFFFFFFU ,0x00000000U)
10473                 RegMask = (DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX8LCDLR2_DQSGD_MASK |  0 );
10474
10475                 RegVal = ((0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT
10476                         | 0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT
10477                         | 0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT
10478                         | 0x00000000U << DDR_PHY_DX8LCDLR2_DQSGD_SHIFT
10479                         |  0 ) & RegMask); */
10480                 PSU_Mask_Write (DDR_PHY_DX8LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
10481         /*############################################################################################################################ */
10482
10483                 /*Register : DX8GTR0 @ 0XFD080FC0</p>
10484
10485                 Reserved. Return zeroes on reads.
10486                 PSU_DDR_PHY_DX8GTR0_RESERVED_31_24                                              0x0
10487
10488                 DQ Write Path Latency Pipeline
10489                 PSU_DDR_PHY_DX8GTR0_WDQSL                                                       0x0
10490
10491                 Reserved. Caution, do not write to this register field.
10492                 PSU_DDR_PHY_DX8GTR0_RESERVED_23_20                                              0x0
10493
10494                 Write Leveling System Latency
10495                 PSU_DDR_PHY_DX8GTR0_WLSL                                                        0x2
10496
10497                 Reserved. Return zeroes on reads.
10498                 PSU_DDR_PHY_DX8GTR0_RESERVED_15_13                                              0x0
10499
10500                 Reserved. Caution, do not write to this register field.
10501                 PSU_DDR_PHY_DX8GTR0_RESERVED_12_8                                               0x0
10502
10503                 Reserved. Return zeroes on reads.
10504                 PSU_DDR_PHY_DX8GTR0_RESERVED_7_5                                                0x0
10505
10506                 DQS Gating System Latency
10507                 PSU_DDR_PHY_DX8GTR0_DGSL                                                        0x0
10508
10509                 DATX8 n General Timing Register 0
10510                 (OFFSET, MASK, VALUE)      (0XFD080FC0, 0xFFFFFFFFU ,0x00020000U)
10511                 RegMask = (DDR_PHY_DX8GTR0_RESERVED_31_24_MASK | DDR_PHY_DX8GTR0_WDQSL_MASK | DDR_PHY_DX8GTR0_RESERVED_23_20_MASK | DDR_PHY_DX8GTR0_WLSL_MASK | DDR_PHY_DX8GTR0_RESERVED_15_13_MASK | DDR_PHY_DX8GTR0_RESERVED_12_8_MASK | DDR_PHY_DX8GTR0_RESERVED_7_5_MASK | DDR_PHY_DX8GTR0_DGSL_MASK |  0 );
10512
10513                 RegVal = ((0x00000000U << DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT
10514                         | 0x00000000U << DDR_PHY_DX8GTR0_WDQSL_SHIFT
10515                         | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT
10516                         | 0x00000002U << DDR_PHY_DX8GTR0_WLSL_SHIFT
10517                         | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT
10518                         | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT
10519                         | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT
10520                         | 0x00000000U << DDR_PHY_DX8GTR0_DGSL_SHIFT
10521                         |  0 ) & RegMask); */
10522                 PSU_Mask_Write (DDR_PHY_DX8GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
10523         /*############################################################################################################################ */
10524
10525                 /*Register : DX8SL0OSC @ 0XFD081400</p>
10526
10527                 Reserved. Return zeroes on reads.
10528                 PSU_DDR_PHY_DX8SL0OSC_RESERVED_31_30                                            0x0
10529
10530                 Enable Clock Gating for DX ddr_clk
10531                 PSU_DDR_PHY_DX8SL0OSC_GATEDXRDCLK                                               0x2
10532
10533                 Enable Clock Gating for DX ctl_rd_clk
10534                 PSU_DDR_PHY_DX8SL0OSC_GATEDXDDRCLK                                              0x2
10535
10536                 Enable Clock Gating for DX ctl_clk
10537                 PSU_DDR_PHY_DX8SL0OSC_GATEDXCTLCLK                                              0x2
10538
10539                 Selects the level to which clocks will be stalled when clock gating is enabled.
10540                 PSU_DDR_PHY_DX8SL0OSC_CLKLEVEL                                                  0x0
10541
10542                 Loopback Mode
10543                 PSU_DDR_PHY_DX8SL0OSC_LBMODE                                                    0x0
10544
10545                 Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
10546                 PSU_DDR_PHY_DX8SL0OSC_LBGSDQS                                                   0x0
10547
10548                 Loopback DQS Gating
10549                 PSU_DDR_PHY_DX8SL0OSC_LBGDQS                                                    0x0
10550
10551                 Loopback DQS Shift
10552                 PSU_DDR_PHY_DX8SL0OSC_LBDQSS                                                    0x0
10553
10554                 PHY High-Speed Reset
10555                 PSU_DDR_PHY_DX8SL0OSC_PHYHRST                                                   0x1
10556
10557                 PHY FIFO Reset
10558                 PSU_DDR_PHY_DX8SL0OSC_PHYFRST                                                   0x1
10559
10560                 Delay Line Test Start
10561                 PSU_DDR_PHY_DX8SL0OSC_DLTST                                                     0x0
10562
10563                 Delay Line Test Mode
10564                 PSU_DDR_PHY_DX8SL0OSC_DLTMODE                                                   0x0
10565
10566                 Reserved. Caution, do not write to this register field.
10567                 PSU_DDR_PHY_DX8SL0OSC_RESERVED_12_11                                            0x3
10568
10569                 Oscillator Mode Write-Data Delay Line Select
10570                 PSU_DDR_PHY_DX8SL0OSC_OSCWDDL                                                   0x3
10571
10572                 Reserved. Caution, do not write to this register field.
10573                 PSU_DDR_PHY_DX8SL0OSC_RESERVED_8_7                                              0x3
10574
10575                 Oscillator Mode Write-Leveling Delay Line Select
10576                 PSU_DDR_PHY_DX8SL0OSC_OSCWDL                                                    0x3
10577
10578                 Oscillator Mode Division
10579                 PSU_DDR_PHY_DX8SL0OSC_OSCDIV                                                    0xf
10580
10581                 Oscillator Enable
10582                 PSU_DDR_PHY_DX8SL0OSC_OSCEN                                                     0x0
10583
10584                 DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
10585                 (OFFSET, MASK, VALUE)      (0XFD081400, 0xFFFFFFFFU ,0x2A019FFEU)
10586                 RegMask = (DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL0OSC_LBMODE_MASK | DDR_PHY_DX8SL0OSC_LBGSDQS_MASK | DDR_PHY_DX8SL0OSC_LBGDQS_MASK | DDR_PHY_DX8SL0OSC_LBDQSS_MASK | DDR_PHY_DX8SL0OSC_PHYHRST_MASK | DDR_PHY_DX8SL0OSC_PHYFRST_MASK | DDR_PHY_DX8SL0OSC_DLTST_MASK | DDR_PHY_DX8SL0OSC_DLTMODE_MASK | DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL0OSC_OSCWDDL_MASK | DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL0OSC_OSCWDL_MASK | DDR_PHY_DX8SL0OSC_OSCDIV_MASK | DDR_PHY_DX8SL0OSC_OSCEN_MASK |  0 );
10587
10588                 RegVal = ((0x00000000U << DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT
10589                         | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT
10590                         | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT
10591                         | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT
10592                         | 0x00000000U << DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT
10593                         | 0x00000000U << DDR_PHY_DX8SL0OSC_LBMODE_SHIFT
10594                         | 0x00000000U << DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT
10595                         | 0x00000000U << DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT
10596                         | 0x00000000U << DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT
10597                         | 0x00000001U << DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT
10598                         | 0x00000001U << DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT
10599                         | 0x00000000U << DDR_PHY_DX8SL0OSC_DLTST_SHIFT
10600                         | 0x00000000U << DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT
10601                         | 0x00000003U << DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT
10602                         | 0x00000003U << DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT
10603                         | 0x00000003U << DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT
10604                         | 0x00000003U << DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT
10605                         | 0x0000000FU << DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT
10606                         | 0x00000000U << DDR_PHY_DX8SL0OSC_OSCEN_SHIFT
10607                         |  0 ) & RegMask); */
10608                 PSU_Mask_Write (DDR_PHY_DX8SL0OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU);
10609         /*############################################################################################################################ */
10610
10611                 /*Register : DX8SL0DQSCTL @ 0XFD08141C</p>
10612
10613                 Reserved. Return zeroes on reads.
10614                 PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25                                         0x0
10615
10616                 Read Path Rise-to-Rise Mode
10617                 PSU_DDR_PHY_DX8SL0DQSCTL_RRRMODE                                                0x1
10618
10619                 Reserved. Return zeroes on reads.
10620                 PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22                                         0x0
10621
10622                 Write Path Rise-to-Rise Mode
10623                 PSU_DDR_PHY_DX8SL0DQSCTL_WRRMODE                                                0x1
10624
10625                 DQS Gate Extension
10626                 PSU_DDR_PHY_DX8SL0DQSCTL_DQSGX                                                  0x0
10627
10628                 Low Power PLL Power Down
10629                 PSU_DDR_PHY_DX8SL0DQSCTL_LPPLLPD                                                0x1
10630
10631                 Low Power I/O Power Down
10632                 PSU_DDR_PHY_DX8SL0DQSCTL_LPIOPD                                                 0x1
10633
10634                 Reserved. Return zeroes on reads.
10635                 PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15                                         0x0
10636
10637                 QS Counter Enable
10638                 PSU_DDR_PHY_DX8SL0DQSCTL_QSCNTEN                                                0x1
10639
10640                 Unused DQ I/O Mode
10641                 PSU_DDR_PHY_DX8SL0DQSCTL_UDQIOM                                                 0x0
10642
10643                 Reserved. Return zeroes on reads.
10644                 PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10                                         0x0
10645
10646                 Data Slew Rate
10647                 PSU_DDR_PHY_DX8SL0DQSCTL_DXSR                                                   0x3
10648
10649                 DQS_N Resistor
10650                 PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES                                                0x0
10651
10652                 DQS Resistor
10653                 PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES                                                 0x0
10654
10655                 DATX8 0-1 DQS Control Register
10656                 (OFFSET, MASK, VALUE)      (0XFD08141C, 0xFFFFFFFFU ,0x01264300U)
10657                 RegMask = (DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL0DQSCTL_DXSR_MASK | DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK |  0 );
10658
10659                 RegVal = ((0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT
10660                         | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT
10661                         | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT
10662                         | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT
10663                         | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT
10664                         | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT
10665                         | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT
10666                         | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT
10667                         | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT
10668                         | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT
10669                         | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT
10670                         | 0x00000003U << DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT
10671                         | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT
10672                         | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT
10673                         |  0 ) & RegMask); */
10674                 PSU_Mask_Write (DDR_PHY_DX8SL0DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U);
10675         /*############################################################################################################################ */
10676
10677                 /*Register : DX8SL0DXCTL2 @ 0XFD08142C</p>
10678
10679                 Reserved. Return zeroes on reads.
10680                 PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24                                         0x0
10681
10682                 Configurable Read Data Enable
10683                 PSU_DDR_PHY_DX8SL0DXCTL2_CRDEN                                                  0x0
10684
10685                 OX Extension during Post-amble
10686                 PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX                                                 0x0
10687
10688                 OE Extension during Pre-amble
10689                 PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX                                                 0x1
10690
10691                 Reserved. Return zeroes on reads.
10692                 PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17                                            0x0
10693
10694                 I/O Assisted Gate Select
10695                 PSU_DDR_PHY_DX8SL0DXCTL2_IOAG                                                   0x0
10696
10697                 I/O Loopback Select
10698                 PSU_DDR_PHY_DX8SL0DXCTL2_IOLB                                                   0x0
10699
10700                 Reserved. Return zeroes on reads.
10701                 PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13                                         0x0
10702
10703                 Low Power Wakeup Threshold
10704                 PSU_DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH                                         0xc
10705
10706                 Read Data Bus Inversion Enable
10707                 PSU_DDR_PHY_DX8SL0DXCTL2_RDBI                                                   0x0
10708
10709                 Write Data Bus Inversion Enable
10710                 PSU_DDR_PHY_DX8SL0DXCTL2_WDBI                                                   0x0
10711
10712                 PUB Read FIFO Bypass
10713                 PSU_DDR_PHY_DX8SL0DXCTL2_PRFBYP                                                 0x0
10714
10715                 DATX8 Receive FIFO Read Mode
10716                 PSU_DDR_PHY_DX8SL0DXCTL2_RDMODE                                                 0x0
10717
10718                 Disables the Read FIFO Reset
10719                 PSU_DDR_PHY_DX8SL0DXCTL2_DISRST                                                 0x0
10720
10721                 Read DQS Gate I/O Loopback
10722                 PSU_DDR_PHY_DX8SL0DXCTL2_DQSGLB                                                 0x0
10723
10724                 Reserved. Return zeroes on reads.
10725                 PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0                                             0x0
10726
10727                 DATX8 0-1 DX Control Register 2
10728                 (OFFSET, MASK, VALUE)      (0XFD08142C, 0xFFFFFFFFU ,0x00041800U)
10729                 RegMask = (DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL0DXCTL2_IOAG_MASK | DDR_PHY_DX8SL0DXCTL2_IOLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL0DXCTL2_RDBI_MASK | DDR_PHY_DX8SL0DXCTL2_WDBI_MASK | DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL0DXCTL2_DISRST_MASK | DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK |  0 );
10730
10731                 RegVal = ((0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT
10732                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT
10733                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT
10734                         | 0x00000001U << DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT
10735                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT
10736                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT
10737                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT
10738                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT
10739                         | 0x0000000CU << DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT
10740                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT
10741                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT
10742                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT
10743                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT
10744                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT
10745                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT
10746                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT
10747                         |  0 ) & RegMask); */
10748                 PSU_Mask_Write (DDR_PHY_DX8SL0DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U);
10749         /*############################################################################################################################ */
10750
10751                 /*Register : DX8SL0IOCR @ 0XFD081430</p>
10752
10753                 Reserved. Return zeroes on reads.
10754                 PSU_DDR_PHY_DX8SL0IOCR_RESERVED_31                                              0x0
10755
10756                 PVREF_DAC REFSEL range select
10757                 PSU_DDR_PHY_DX8SL0IOCR_DXDACRANGE                                               0x7
10758
10759                 IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
10760                 PSU_DDR_PHY_DX8SL0IOCR_DXVREFIOM                                                0x0
10761
10762                 DX IO Mode
10763                 PSU_DDR_PHY_DX8SL0IOCR_DXIOM                                                    0x2
10764
10765                 DX IO Transmitter Mode
10766                 PSU_DDR_PHY_DX8SL0IOCR_DXTXM                                                    0x0
10767
10768                 DX IO Receiver Mode
10769                 PSU_DDR_PHY_DX8SL0IOCR_DXRXM                                                    0x0
10770
10771                 DATX8 0-1 I/O Configuration Register
10772                 (OFFSET, MASK, VALUE)      (0XFD081430, 0xFFFFFFFFU ,0x70800000U)
10773                 RegMask = (DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL0IOCR_DXIOM_MASK | DDR_PHY_DX8SL0IOCR_DXTXM_MASK | DDR_PHY_DX8SL0IOCR_DXRXM_MASK |  0 );
10774
10775                 RegVal = ((0x00000000U << DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT
10776                         | 0x00000007U << DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT
10777                         | 0x00000000U << DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT
10778                         | 0x00000002U << DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT
10779                         | 0x00000000U << DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT
10780                         | 0x00000000U << DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT
10781                         |  0 ) & RegMask); */
10782                 PSU_Mask_Write (DDR_PHY_DX8SL0IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
10783         /*############################################################################################################################ */
10784
10785                 /*Register : DX8SL1OSC @ 0XFD081440</p>
10786
10787                 Reserved. Return zeroes on reads.
10788                 PSU_DDR_PHY_DX8SL1OSC_RESERVED_31_30                                            0x0
10789
10790                 Enable Clock Gating for DX ddr_clk
10791                 PSU_DDR_PHY_DX8SL1OSC_GATEDXRDCLK                                               0x2
10792
10793                 Enable Clock Gating for DX ctl_rd_clk
10794                 PSU_DDR_PHY_DX8SL1OSC_GATEDXDDRCLK                                              0x2
10795
10796                 Enable Clock Gating for DX ctl_clk
10797                 PSU_DDR_PHY_DX8SL1OSC_GATEDXCTLCLK                                              0x2
10798
10799                 Selects the level to which clocks will be stalled when clock gating is enabled.
10800                 PSU_DDR_PHY_DX8SL1OSC_CLKLEVEL                                                  0x0
10801
10802                 Loopback Mode
10803                 PSU_DDR_PHY_DX8SL1OSC_LBMODE                                                    0x0
10804
10805                 Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
10806                 PSU_DDR_PHY_DX8SL1OSC_LBGSDQS                                                   0x0
10807
10808                 Loopback DQS Gating
10809                 PSU_DDR_PHY_DX8SL1OSC_LBGDQS                                                    0x0
10810
10811                 Loopback DQS Shift
10812                 PSU_DDR_PHY_DX8SL1OSC_LBDQSS                                                    0x0
10813
10814                 PHY High-Speed Reset
10815                 PSU_DDR_PHY_DX8SL1OSC_PHYHRST                                                   0x1
10816
10817                 PHY FIFO Reset
10818                 PSU_DDR_PHY_DX8SL1OSC_PHYFRST                                                   0x1
10819
10820                 Delay Line Test Start
10821                 PSU_DDR_PHY_DX8SL1OSC_DLTST                                                     0x0
10822
10823                 Delay Line Test Mode
10824                 PSU_DDR_PHY_DX8SL1OSC_DLTMODE                                                   0x0
10825
10826                 Reserved. Caution, do not write to this register field.
10827                 PSU_DDR_PHY_DX8SL1OSC_RESERVED_12_11                                            0x3
10828
10829                 Oscillator Mode Write-Data Delay Line Select
10830                 PSU_DDR_PHY_DX8SL1OSC_OSCWDDL                                                   0x3
10831
10832                 Reserved. Caution, do not write to this register field.
10833                 PSU_DDR_PHY_DX8SL1OSC_RESERVED_8_7                                              0x3
10834
10835                 Oscillator Mode Write-Leveling Delay Line Select
10836                 PSU_DDR_PHY_DX8SL1OSC_OSCWDL                                                    0x3
10837
10838                 Oscillator Mode Division
10839                 PSU_DDR_PHY_DX8SL1OSC_OSCDIV                                                    0xf
10840
10841                 Oscillator Enable
10842                 PSU_DDR_PHY_DX8SL1OSC_OSCEN                                                     0x0
10843
10844                 DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
10845                 (OFFSET, MASK, VALUE)      (0XFD081440, 0xFFFFFFFFU ,0x2A019FFEU)
10846                 RegMask = (DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL1OSC_LBMODE_MASK | DDR_PHY_DX8SL1OSC_LBGSDQS_MASK | DDR_PHY_DX8SL1OSC_LBGDQS_MASK | DDR_PHY_DX8SL1OSC_LBDQSS_MASK | DDR_PHY_DX8SL1OSC_PHYHRST_MASK | DDR_PHY_DX8SL1OSC_PHYFRST_MASK | DDR_PHY_DX8SL1OSC_DLTST_MASK | DDR_PHY_DX8SL1OSC_DLTMODE_MASK | DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL1OSC_OSCWDDL_MASK | DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL1OSC_OSCWDL_MASK | DDR_PHY_DX8SL1OSC_OSCDIV_MASK | DDR_PHY_DX8SL1OSC_OSCEN_MASK |  0 );
10847
10848                 RegVal = ((0x00000000U << DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT
10849                         | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT
10850                         | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT
10851                         | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT
10852                         | 0x00000000U << DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT
10853                         | 0x00000000U << DDR_PHY_DX8SL1OSC_LBMODE_SHIFT
10854                         | 0x00000000U << DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT
10855                         | 0x00000000U << DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT
10856                         | 0x00000000U << DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT
10857                         | 0x00000001U << DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT
10858                         | 0x00000001U << DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT
10859                         | 0x00000000U << DDR_PHY_DX8SL1OSC_DLTST_SHIFT
10860                         | 0x00000000U << DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT
10861                         | 0x00000003U << DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT
10862                         | 0x00000003U << DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT
10863                         | 0x00000003U << DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT
10864                         | 0x00000003U << DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT
10865                         | 0x0000000FU << DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT
10866                         | 0x00000000U << DDR_PHY_DX8SL1OSC_OSCEN_SHIFT
10867                         |  0 ) & RegMask); */
10868                 PSU_Mask_Write (DDR_PHY_DX8SL1OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU);
10869         /*############################################################################################################################ */
10870
10871                 /*Register : DX8SL1DQSCTL @ 0XFD08145C</p>
10872
10873                 Reserved. Return zeroes on reads.
10874                 PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25                                         0x0
10875
10876                 Read Path Rise-to-Rise Mode
10877                 PSU_DDR_PHY_DX8SL1DQSCTL_RRRMODE                                                0x1
10878
10879                 Reserved. Return zeroes on reads.
10880                 PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22                                         0x0
10881
10882                 Write Path Rise-to-Rise Mode
10883                 PSU_DDR_PHY_DX8SL1DQSCTL_WRRMODE                                                0x1
10884
10885                 DQS Gate Extension
10886                 PSU_DDR_PHY_DX8SL1DQSCTL_DQSGX                                                  0x0
10887
10888                 Low Power PLL Power Down
10889                 PSU_DDR_PHY_DX8SL1DQSCTL_LPPLLPD                                                0x1
10890
10891                 Low Power I/O Power Down
10892                 PSU_DDR_PHY_DX8SL1DQSCTL_LPIOPD                                                 0x1
10893
10894                 Reserved. Return zeroes on reads.
10895                 PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15                                         0x0
10896
10897                 QS Counter Enable
10898                 PSU_DDR_PHY_DX8SL1DQSCTL_QSCNTEN                                                0x1
10899
10900                 Unused DQ I/O Mode
10901                 PSU_DDR_PHY_DX8SL1DQSCTL_UDQIOM                                                 0x0
10902
10903                 Reserved. Return zeroes on reads.
10904                 PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10                                         0x0
10905
10906                 Data Slew Rate
10907                 PSU_DDR_PHY_DX8SL1DQSCTL_DXSR                                                   0x3
10908
10909                 DQS_N Resistor
10910                 PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES                                                0x0
10911
10912                 DQS Resistor
10913                 PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES                                                 0x0
10914
10915                 DATX8 0-1 DQS Control Register
10916                 (OFFSET, MASK, VALUE)      (0XFD08145C, 0xFFFFFFFFU ,0x01264300U)
10917                 RegMask = (DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL1DQSCTL_DXSR_MASK | DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK |  0 );
10918
10919                 RegVal = ((0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT
10920                         | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT
10921                         | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT
10922                         | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT
10923                         | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT
10924                         | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT
10925                         | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT
10926                         | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT
10927                         | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT
10928                         | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT
10929                         | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT
10930                         | 0x00000003U << DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT
10931                         | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT
10932                         | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT
10933                         |  0 ) & RegMask); */
10934                 PSU_Mask_Write (DDR_PHY_DX8SL1DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U);
10935         /*############################################################################################################################ */
10936
10937                 /*Register : DX8SL1DXCTL2 @ 0XFD08146C</p>
10938
10939                 Reserved. Return zeroes on reads.
10940                 PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24                                         0x0
10941
10942                 Configurable Read Data Enable
10943                 PSU_DDR_PHY_DX8SL1DXCTL2_CRDEN                                                  0x0
10944
10945                 OX Extension during Post-amble
10946                 PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX                                                 0x0
10947
10948                 OE Extension during Pre-amble
10949                 PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX                                                 0x1
10950
10951                 Reserved. Return zeroes on reads.
10952                 PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17                                            0x0
10953
10954                 I/O Assisted Gate Select
10955                 PSU_DDR_PHY_DX8SL1DXCTL2_IOAG                                                   0x0
10956
10957                 I/O Loopback Select
10958                 PSU_DDR_PHY_DX8SL1DXCTL2_IOLB                                                   0x0
10959
10960                 Reserved. Return zeroes on reads.
10961                 PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13                                         0x0
10962
10963                 Low Power Wakeup Threshold
10964                 PSU_DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH                                         0xc
10965
10966                 Read Data Bus Inversion Enable
10967                 PSU_DDR_PHY_DX8SL1DXCTL2_RDBI                                                   0x0
10968
10969                 Write Data Bus Inversion Enable
10970                 PSU_DDR_PHY_DX8SL1DXCTL2_WDBI                                                   0x0
10971
10972                 PUB Read FIFO Bypass
10973                 PSU_DDR_PHY_DX8SL1DXCTL2_PRFBYP                                                 0x0
10974
10975                 DATX8 Receive FIFO Read Mode
10976                 PSU_DDR_PHY_DX8SL1DXCTL2_RDMODE                                                 0x0
10977
10978                 Disables the Read FIFO Reset
10979                 PSU_DDR_PHY_DX8SL1DXCTL2_DISRST                                                 0x0
10980
10981                 Read DQS Gate I/O Loopback
10982                 PSU_DDR_PHY_DX8SL1DXCTL2_DQSGLB                                                 0x0
10983
10984                 Reserved. Return zeroes on reads.
10985                 PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0                                             0x0
10986
10987                 DATX8 0-1 DX Control Register 2
10988                 (OFFSET, MASK, VALUE)      (0XFD08146C, 0xFFFFFFFFU ,0x00041800U)
10989                 RegMask = (DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL1DXCTL2_IOAG_MASK | DDR_PHY_DX8SL1DXCTL2_IOLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL1DXCTL2_RDBI_MASK | DDR_PHY_DX8SL1DXCTL2_WDBI_MASK | DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL1DXCTL2_DISRST_MASK | DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK |  0 );
10990
10991                 RegVal = ((0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT
10992                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT
10993                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT
10994                         | 0x00000001U << DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT
10995                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT
10996                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT
10997                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT
10998                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT
10999                         | 0x0000000CU << DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT
11000                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT
11001                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT
11002                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT
11003                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT
11004                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT
11005                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT
11006                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT
11007                         |  0 ) & RegMask); */
11008                 PSU_Mask_Write (DDR_PHY_DX8SL1DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U);
11009         /*############################################################################################################################ */
11010
11011                 /*Register : DX8SL1IOCR @ 0XFD081470</p>
11012
11013                 Reserved. Return zeroes on reads.
11014                 PSU_DDR_PHY_DX8SL1IOCR_RESERVED_31                                              0x0
11015
11016                 PVREF_DAC REFSEL range select
11017                 PSU_DDR_PHY_DX8SL1IOCR_DXDACRANGE                                               0x7
11018
11019                 IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
11020                 PSU_DDR_PHY_DX8SL1IOCR_DXVREFIOM                                                0x0
11021
11022                 DX IO Mode
11023                 PSU_DDR_PHY_DX8SL1IOCR_DXIOM                                                    0x2
11024
11025                 DX IO Transmitter Mode
11026                 PSU_DDR_PHY_DX8SL1IOCR_DXTXM                                                    0x0
11027
11028                 DX IO Receiver Mode
11029                 PSU_DDR_PHY_DX8SL1IOCR_DXRXM                                                    0x0
11030
11031                 DATX8 0-1 I/O Configuration Register
11032                 (OFFSET, MASK, VALUE)      (0XFD081470, 0xFFFFFFFFU ,0x70800000U)
11033                 RegMask = (DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL1IOCR_DXIOM_MASK | DDR_PHY_DX8SL1IOCR_DXTXM_MASK | DDR_PHY_DX8SL1IOCR_DXRXM_MASK |  0 );
11034
11035                 RegVal = ((0x00000000U << DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT
11036                         | 0x00000007U << DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT
11037                         | 0x00000000U << DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT
11038                         | 0x00000002U << DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT
11039                         | 0x00000000U << DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT
11040                         | 0x00000000U << DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT
11041                         |  0 ) & RegMask); */
11042                 PSU_Mask_Write (DDR_PHY_DX8SL1IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
11043         /*############################################################################################################################ */
11044
11045                 /*Register : DX8SL2OSC @ 0XFD081480</p>
11046
11047                 Reserved. Return zeroes on reads.
11048                 PSU_DDR_PHY_DX8SL2OSC_RESERVED_31_30                                            0x0
11049
11050                 Enable Clock Gating for DX ddr_clk
11051                 PSU_DDR_PHY_DX8SL2OSC_GATEDXRDCLK                                               0x2
11052
11053                 Enable Clock Gating for DX ctl_rd_clk
11054                 PSU_DDR_PHY_DX8SL2OSC_GATEDXDDRCLK                                              0x2
11055
11056                 Enable Clock Gating for DX ctl_clk
11057                 PSU_DDR_PHY_DX8SL2OSC_GATEDXCTLCLK                                              0x2
11058
11059                 Selects the level to which clocks will be stalled when clock gating is enabled.
11060                 PSU_DDR_PHY_DX8SL2OSC_CLKLEVEL                                                  0x0
11061
11062                 Loopback Mode
11063                 PSU_DDR_PHY_DX8SL2OSC_LBMODE                                                    0x0
11064
11065                 Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
11066                 PSU_DDR_PHY_DX8SL2OSC_LBGSDQS                                                   0x0
11067
11068                 Loopback DQS Gating
11069                 PSU_DDR_PHY_DX8SL2OSC_LBGDQS                                                    0x0
11070
11071                 Loopback DQS Shift
11072                 PSU_DDR_PHY_DX8SL2OSC_LBDQSS                                                    0x0
11073
11074                 PHY High-Speed Reset
11075                 PSU_DDR_PHY_DX8SL2OSC_PHYHRST                                                   0x1
11076
11077                 PHY FIFO Reset
11078                 PSU_DDR_PHY_DX8SL2OSC_PHYFRST                                                   0x1
11079
11080                 Delay Line Test Start
11081                 PSU_DDR_PHY_DX8SL2OSC_DLTST                                                     0x0
11082
11083                 Delay Line Test Mode
11084                 PSU_DDR_PHY_DX8SL2OSC_DLTMODE                                                   0x0
11085
11086                 Reserved. Caution, do not write to this register field.
11087                 PSU_DDR_PHY_DX8SL2OSC_RESERVED_12_11                                            0x3
11088
11089                 Oscillator Mode Write-Data Delay Line Select
11090                 PSU_DDR_PHY_DX8SL2OSC_OSCWDDL                                                   0x3
11091
11092                 Reserved. Caution, do not write to this register field.
11093                 PSU_DDR_PHY_DX8SL2OSC_RESERVED_8_7                                              0x3
11094
11095                 Oscillator Mode Write-Leveling Delay Line Select
11096                 PSU_DDR_PHY_DX8SL2OSC_OSCWDL                                                    0x3
11097
11098                 Oscillator Mode Division
11099                 PSU_DDR_PHY_DX8SL2OSC_OSCDIV                                                    0xf
11100
11101                 Oscillator Enable
11102                 PSU_DDR_PHY_DX8SL2OSC_OSCEN                                                     0x0
11103
11104                 DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
11105                 (OFFSET, MASK, VALUE)      (0XFD081480, 0xFFFFFFFFU ,0x2A019FFEU)
11106                 RegMask = (DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL2OSC_LBMODE_MASK | DDR_PHY_DX8SL2OSC_LBGSDQS_MASK | DDR_PHY_DX8SL2OSC_LBGDQS_MASK | DDR_PHY_DX8SL2OSC_LBDQSS_MASK | DDR_PHY_DX8SL2OSC_PHYHRST_MASK | DDR_PHY_DX8SL2OSC_PHYFRST_MASK | DDR_PHY_DX8SL2OSC_DLTST_MASK | DDR_PHY_DX8SL2OSC_DLTMODE_MASK | DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL2OSC_OSCWDDL_MASK | DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL2OSC_OSCWDL_MASK | DDR_PHY_DX8SL2OSC_OSCDIV_MASK | DDR_PHY_DX8SL2OSC_OSCEN_MASK |  0 );
11107
11108                 RegVal = ((0x00000000U << DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT
11109                         | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT
11110                         | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT
11111                         | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT
11112                         | 0x00000000U << DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT
11113                         | 0x00000000U << DDR_PHY_DX8SL2OSC_LBMODE_SHIFT
11114                         | 0x00000000U << DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT
11115                         | 0x00000000U << DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT
11116                         | 0x00000000U << DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT
11117                         | 0x00000001U << DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT
11118                         | 0x00000001U << DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT
11119                         | 0x00000000U << DDR_PHY_DX8SL2OSC_DLTST_SHIFT
11120                         | 0x00000000U << DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT
11121                         | 0x00000003U << DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT
11122                         | 0x00000003U << DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT
11123                         | 0x00000003U << DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT
11124                         | 0x00000003U << DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT
11125                         | 0x0000000FU << DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT
11126                         | 0x00000000U << DDR_PHY_DX8SL2OSC_OSCEN_SHIFT
11127                         |  0 ) & RegMask); */
11128                 PSU_Mask_Write (DDR_PHY_DX8SL2OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU);
11129         /*############################################################################################################################ */
11130
11131                 /*Register : DX8SL2DQSCTL @ 0XFD08149C</p>
11132
11133                 Reserved. Return zeroes on reads.
11134                 PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25                                         0x0
11135
11136                 Read Path Rise-to-Rise Mode
11137                 PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE                                                0x1
11138
11139                 Reserved. Return zeroes on reads.
11140                 PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22                                         0x0
11141
11142                 Write Path Rise-to-Rise Mode
11143                 PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE                                                0x1
11144
11145                 DQS Gate Extension
11146                 PSU_DDR_PHY_DX8SL2DQSCTL_DQSGX                                                  0x0
11147
11148                 Low Power PLL Power Down
11149                 PSU_DDR_PHY_DX8SL2DQSCTL_LPPLLPD                                                0x1
11150
11151                 Low Power I/O Power Down
11152                 PSU_DDR_PHY_DX8SL2DQSCTL_LPIOPD                                                 0x1
11153
11154                 Reserved. Return zeroes on reads.
11155                 PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15                                         0x0
11156
11157                 QS Counter Enable
11158                 PSU_DDR_PHY_DX8SL2DQSCTL_QSCNTEN                                                0x1
11159
11160                 Unused DQ I/O Mode
11161                 PSU_DDR_PHY_DX8SL2DQSCTL_UDQIOM                                                 0x0
11162
11163                 Reserved. Return zeroes on reads.
11164                 PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10                                         0x0
11165
11166                 Data Slew Rate
11167                 PSU_DDR_PHY_DX8SL2DQSCTL_DXSR                                                   0x3
11168
11169                 DQS_N Resistor
11170                 PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES                                                0x0
11171
11172                 DQS Resistor
11173                 PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES                                                 0x0
11174
11175                 DATX8 0-1 DQS Control Register
11176                 (OFFSET, MASK, VALUE)      (0XFD08149C, 0xFFFFFFFFU ,0x01264300U)
11177                 RegMask = (DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL2DQSCTL_DXSR_MASK | DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK |  0 );
11178
11179                 RegVal = ((0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT
11180                         | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT
11181                         | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT
11182                         | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT
11183                         | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT
11184                         | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT
11185                         | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT
11186                         | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT
11187                         | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT
11188                         | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT
11189                         | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT
11190                         | 0x00000003U << DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT
11191                         | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT
11192                         | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT
11193                         |  0 ) & RegMask); */
11194                 PSU_Mask_Write (DDR_PHY_DX8SL2DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U);
11195         /*############################################################################################################################ */
11196
11197                 /*Register : DX8SL2DXCTL2 @ 0XFD0814AC</p>
11198
11199                 Reserved. Return zeroes on reads.
11200                 PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24                                         0x0
11201
11202                 Configurable Read Data Enable
11203                 PSU_DDR_PHY_DX8SL2DXCTL2_CRDEN                                                  0x0
11204
11205                 OX Extension during Post-amble
11206                 PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX                                                 0x0
11207
11208                 OE Extension during Pre-amble
11209                 PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX                                                 0x1
11210
11211                 Reserved. Return zeroes on reads.
11212                 PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17                                            0x0
11213
11214                 I/O Assisted Gate Select
11215                 PSU_DDR_PHY_DX8SL2DXCTL2_IOAG                                                   0x0
11216
11217                 I/O Loopback Select
11218                 PSU_DDR_PHY_DX8SL2DXCTL2_IOLB                                                   0x0
11219
11220                 Reserved. Return zeroes on reads.
11221                 PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13                                         0x0
11222
11223                 Low Power Wakeup Threshold
11224                 PSU_DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH                                         0xc
11225
11226                 Read Data Bus Inversion Enable
11227                 PSU_DDR_PHY_DX8SL2DXCTL2_RDBI                                                   0x0
11228
11229                 Write Data Bus Inversion Enable
11230                 PSU_DDR_PHY_DX8SL2DXCTL2_WDBI                                                   0x0
11231
11232                 PUB Read FIFO Bypass
11233                 PSU_DDR_PHY_DX8SL2DXCTL2_PRFBYP                                                 0x0
11234
11235                 DATX8 Receive FIFO Read Mode
11236                 PSU_DDR_PHY_DX8SL2DXCTL2_RDMODE                                                 0x0
11237
11238                 Disables the Read FIFO Reset
11239                 PSU_DDR_PHY_DX8SL2DXCTL2_DISRST                                                 0x0
11240
11241                 Read DQS Gate I/O Loopback
11242                 PSU_DDR_PHY_DX8SL2DXCTL2_DQSGLB                                                 0x0
11243
11244                 Reserved. Return zeroes on reads.
11245                 PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0                                             0x0
11246
11247                 DATX8 0-1 DX Control Register 2
11248                 (OFFSET, MASK, VALUE)      (0XFD0814AC, 0xFFFFFFFFU ,0x00041800U)
11249                 RegMask = (DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL2DXCTL2_IOAG_MASK | DDR_PHY_DX8SL2DXCTL2_IOLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL2DXCTL2_RDBI_MASK | DDR_PHY_DX8SL2DXCTL2_WDBI_MASK | DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL2DXCTL2_DISRST_MASK | DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK |  0 );
11250
11251                 RegVal = ((0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT
11252                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT
11253                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT
11254                         | 0x00000001U << DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT
11255                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT
11256                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT
11257                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT
11258                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT
11259                         | 0x0000000CU << DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT
11260                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT
11261                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT
11262                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT
11263                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT
11264                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT
11265                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT
11266                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT
11267                         |  0 ) & RegMask); */
11268                 PSU_Mask_Write (DDR_PHY_DX8SL2DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U);
11269         /*############################################################################################################################ */
11270
11271                 /*Register : DX8SL2IOCR @ 0XFD0814B0</p>
11272
11273                 Reserved. Return zeroes on reads.
11274                 PSU_DDR_PHY_DX8SL2IOCR_RESERVED_31                                              0x0
11275
11276                 PVREF_DAC REFSEL range select
11277                 PSU_DDR_PHY_DX8SL2IOCR_DXDACRANGE                                               0x7
11278
11279                 IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
11280                 PSU_DDR_PHY_DX8SL2IOCR_DXVREFIOM                                                0x0
11281
11282                 DX IO Mode
11283                 PSU_DDR_PHY_DX8SL2IOCR_DXIOM                                                    0x2
11284
11285                 DX IO Transmitter Mode
11286                 PSU_DDR_PHY_DX8SL2IOCR_DXTXM                                                    0x0
11287
11288                 DX IO Receiver Mode
11289                 PSU_DDR_PHY_DX8SL2IOCR_DXRXM                                                    0x0
11290
11291                 DATX8 0-1 I/O Configuration Register
11292                 (OFFSET, MASK, VALUE)      (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U)
11293                 RegMask = (DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL2IOCR_DXIOM_MASK | DDR_PHY_DX8SL2IOCR_DXTXM_MASK | DDR_PHY_DX8SL2IOCR_DXRXM_MASK |  0 );
11294
11295                 RegVal = ((0x00000000U << DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT
11296                         | 0x00000007U << DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT
11297                         | 0x00000000U << DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT
11298                         | 0x00000002U << DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT
11299                         | 0x00000000U << DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT
11300                         | 0x00000000U << DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT
11301                         |  0 ) & RegMask); */
11302                 PSU_Mask_Write (DDR_PHY_DX8SL2IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
11303         /*############################################################################################################################ */
11304
11305                 /*Register : DX8SL3OSC @ 0XFD0814C0</p>
11306
11307                 Reserved. Return zeroes on reads.
11308                 PSU_DDR_PHY_DX8SL3OSC_RESERVED_31_30                                            0x0
11309
11310                 Enable Clock Gating for DX ddr_clk
11311                 PSU_DDR_PHY_DX8SL3OSC_GATEDXRDCLK                                               0x2
11312
11313                 Enable Clock Gating for DX ctl_rd_clk
11314                 PSU_DDR_PHY_DX8SL3OSC_GATEDXDDRCLK                                              0x2
11315
11316                 Enable Clock Gating for DX ctl_clk
11317                 PSU_DDR_PHY_DX8SL3OSC_GATEDXCTLCLK                                              0x2
11318
11319                 Selects the level to which clocks will be stalled when clock gating is enabled.
11320                 PSU_DDR_PHY_DX8SL3OSC_CLKLEVEL                                                  0x0
11321
11322                 Loopback Mode
11323                 PSU_DDR_PHY_DX8SL3OSC_LBMODE                                                    0x0
11324
11325                 Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
11326                 PSU_DDR_PHY_DX8SL3OSC_LBGSDQS                                                   0x0
11327
11328                 Loopback DQS Gating
11329                 PSU_DDR_PHY_DX8SL3OSC_LBGDQS                                                    0x0
11330
11331                 Loopback DQS Shift
11332                 PSU_DDR_PHY_DX8SL3OSC_LBDQSS                                                    0x0
11333
11334                 PHY High-Speed Reset
11335                 PSU_DDR_PHY_DX8SL3OSC_PHYHRST                                                   0x1
11336
11337                 PHY FIFO Reset
11338                 PSU_DDR_PHY_DX8SL3OSC_PHYFRST                                                   0x1
11339
11340                 Delay Line Test Start
11341                 PSU_DDR_PHY_DX8SL3OSC_DLTST                                                     0x0
11342
11343                 Delay Line Test Mode
11344                 PSU_DDR_PHY_DX8SL3OSC_DLTMODE                                                   0x0
11345
11346                 Reserved. Caution, do not write to this register field.
11347                 PSU_DDR_PHY_DX8SL3OSC_RESERVED_12_11                                            0x3
11348
11349                 Oscillator Mode Write-Data Delay Line Select
11350                 PSU_DDR_PHY_DX8SL3OSC_OSCWDDL                                                   0x3
11351
11352                 Reserved. Caution, do not write to this register field.
11353                 PSU_DDR_PHY_DX8SL3OSC_RESERVED_8_7                                              0x3
11354
11355                 Oscillator Mode Write-Leveling Delay Line Select
11356                 PSU_DDR_PHY_DX8SL3OSC_OSCWDL                                                    0x3
11357
11358                 Oscillator Mode Division
11359                 PSU_DDR_PHY_DX8SL3OSC_OSCDIV                                                    0xf
11360
11361                 Oscillator Enable
11362                 PSU_DDR_PHY_DX8SL3OSC_OSCEN                                                     0x0
11363
11364                 DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
11365                 (OFFSET, MASK, VALUE)      (0XFD0814C0, 0xFFFFFFFFU ,0x2A019FFEU)
11366                 RegMask = (DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL3OSC_LBMODE_MASK | DDR_PHY_DX8SL3OSC_LBGSDQS_MASK | DDR_PHY_DX8SL3OSC_LBGDQS_MASK | DDR_PHY_DX8SL3OSC_LBDQSS_MASK | DDR_PHY_DX8SL3OSC_PHYHRST_MASK | DDR_PHY_DX8SL3OSC_PHYFRST_MASK | DDR_PHY_DX8SL3OSC_DLTST_MASK | DDR_PHY_DX8SL3OSC_DLTMODE_MASK | DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL3OSC_OSCWDDL_MASK | DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL3OSC_OSCWDL_MASK | DDR_PHY_DX8SL3OSC_OSCDIV_MASK | DDR_PHY_DX8SL3OSC_OSCEN_MASK |  0 );
11367
11368                 RegVal = ((0x00000000U << DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT
11369                         | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT
11370                         | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT
11371                         | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT
11372                         | 0x00000000U << DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT
11373                         | 0x00000000U << DDR_PHY_DX8SL3OSC_LBMODE_SHIFT
11374                         | 0x00000000U << DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT
11375                         | 0x00000000U << DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT
11376                         | 0x00000000U << DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT
11377                         | 0x00000001U << DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT
11378                         | 0x00000001U << DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT
11379                         | 0x00000000U << DDR_PHY_DX8SL3OSC_DLTST_SHIFT
11380                         | 0x00000000U << DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT
11381                         | 0x00000003U << DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT
11382                         | 0x00000003U << DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT
11383                         | 0x00000003U << DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT
11384                         | 0x00000003U << DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT
11385                         | 0x0000000FU << DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT
11386                         | 0x00000000U << DDR_PHY_DX8SL3OSC_OSCEN_SHIFT
11387                         |  0 ) & RegMask); */
11388                 PSU_Mask_Write (DDR_PHY_DX8SL3OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU);
11389         /*############################################################################################################################ */
11390
11391                 /*Register : DX8SL3DQSCTL @ 0XFD0814DC</p>
11392
11393                 Reserved. Return zeroes on reads.
11394                 PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25                                         0x0
11395
11396                 Read Path Rise-to-Rise Mode
11397                 PSU_DDR_PHY_DX8SL3DQSCTL_RRRMODE                                                0x1
11398
11399                 Reserved. Return zeroes on reads.
11400                 PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22                                         0x0
11401
11402                 Write Path Rise-to-Rise Mode
11403                 PSU_DDR_PHY_DX8SL3DQSCTL_WRRMODE                                                0x1
11404
11405                 DQS Gate Extension
11406                 PSU_DDR_PHY_DX8SL3DQSCTL_DQSGX                                                  0x0
11407
11408                 Low Power PLL Power Down
11409                 PSU_DDR_PHY_DX8SL3DQSCTL_LPPLLPD                                                0x1
11410
11411                 Low Power I/O Power Down
11412                 PSU_DDR_PHY_DX8SL3DQSCTL_LPIOPD                                                 0x1
11413
11414                 Reserved. Return zeroes on reads.
11415                 PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15                                         0x0
11416
11417                 QS Counter Enable
11418                 PSU_DDR_PHY_DX8SL3DQSCTL_QSCNTEN                                                0x1
11419
11420                 Unused DQ I/O Mode
11421                 PSU_DDR_PHY_DX8SL3DQSCTL_UDQIOM                                                 0x0
11422
11423                 Reserved. Return zeroes on reads.
11424                 PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10                                         0x0
11425
11426                 Data Slew Rate
11427                 PSU_DDR_PHY_DX8SL3DQSCTL_DXSR                                                   0x3
11428
11429                 DQS_N Resistor
11430                 PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES                                                0x0
11431
11432                 DQS Resistor
11433                 PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES                                                 0x0
11434
11435                 DATX8 0-1 DQS Control Register
11436                 (OFFSET, MASK, VALUE)      (0XFD0814DC, 0xFFFFFFFFU ,0x01264300U)
11437                 RegMask = (DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL3DQSCTL_DXSR_MASK | DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK |  0 );
11438
11439                 RegVal = ((0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT
11440                         | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT
11441                         | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT
11442                         | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT
11443                         | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT
11444                         | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT
11445                         | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT
11446                         | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT
11447                         | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT
11448                         | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT
11449                         | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT
11450                         | 0x00000003U << DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT
11451                         | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT
11452                         | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT
11453                         |  0 ) & RegMask); */
11454                 PSU_Mask_Write (DDR_PHY_DX8SL3DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U);
11455         /*############################################################################################################################ */
11456
11457                 /*Register : DX8SL3DXCTL2 @ 0XFD0814EC</p>
11458
11459                 Reserved. Return zeroes on reads.
11460                 PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24                                         0x0
11461
11462                 Configurable Read Data Enable
11463                 PSU_DDR_PHY_DX8SL3DXCTL2_CRDEN                                                  0x0
11464
11465                 OX Extension during Post-amble
11466                 PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX                                                 0x0
11467
11468                 OE Extension during Pre-amble
11469                 PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX                                                 0x1
11470
11471                 Reserved. Return zeroes on reads.
11472                 PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17                                            0x0
11473
11474                 I/O Assisted Gate Select
11475                 PSU_DDR_PHY_DX8SL3DXCTL2_IOAG                                                   0x0
11476
11477                 I/O Loopback Select
11478                 PSU_DDR_PHY_DX8SL3DXCTL2_IOLB                                                   0x0
11479
11480                 Reserved. Return zeroes on reads.
11481                 PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13                                         0x0
11482
11483                 Low Power Wakeup Threshold
11484                 PSU_DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH                                         0xc
11485
11486                 Read Data Bus Inversion Enable
11487                 PSU_DDR_PHY_DX8SL3DXCTL2_RDBI                                                   0x0
11488
11489                 Write Data Bus Inversion Enable
11490                 PSU_DDR_PHY_DX8SL3DXCTL2_WDBI                                                   0x0
11491
11492                 PUB Read FIFO Bypass
11493                 PSU_DDR_PHY_DX8SL3DXCTL2_PRFBYP                                                 0x0
11494
11495                 DATX8 Receive FIFO Read Mode
11496                 PSU_DDR_PHY_DX8SL3DXCTL2_RDMODE                                                 0x0
11497
11498                 Disables the Read FIFO Reset
11499                 PSU_DDR_PHY_DX8SL3DXCTL2_DISRST                                                 0x0
11500
11501                 Read DQS Gate I/O Loopback
11502                 PSU_DDR_PHY_DX8SL3DXCTL2_DQSGLB                                                 0x0
11503
11504                 Reserved. Return zeroes on reads.
11505                 PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0                                             0x0
11506
11507                 DATX8 0-1 DX Control Register 2
11508                 (OFFSET, MASK, VALUE)      (0XFD0814EC, 0xFFFFFFFFU ,0x00041800U)
11509                 RegMask = (DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL3DXCTL2_IOAG_MASK | DDR_PHY_DX8SL3DXCTL2_IOLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL3DXCTL2_RDBI_MASK | DDR_PHY_DX8SL3DXCTL2_WDBI_MASK | DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL3DXCTL2_DISRST_MASK | DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK |  0 );
11510
11511                 RegVal = ((0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT
11512                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT
11513                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT
11514                         | 0x00000001U << DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT
11515                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT
11516                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT
11517                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT
11518                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT
11519                         | 0x0000000CU << DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT
11520                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT
11521                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT
11522                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT
11523                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT
11524                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT
11525                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT
11526                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT
11527                         |  0 ) & RegMask); */
11528                 PSU_Mask_Write (DDR_PHY_DX8SL3DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U);
11529         /*############################################################################################################################ */
11530
11531                 /*Register : DX8SL3IOCR @ 0XFD0814F0</p>
11532
11533                 Reserved. Return zeroes on reads.
11534                 PSU_DDR_PHY_DX8SL3IOCR_RESERVED_31                                              0x0
11535
11536                 PVREF_DAC REFSEL range select
11537                 PSU_DDR_PHY_DX8SL3IOCR_DXDACRANGE                                               0x7
11538
11539                 IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
11540                 PSU_DDR_PHY_DX8SL3IOCR_DXVREFIOM                                                0x0
11541
11542                 DX IO Mode
11543                 PSU_DDR_PHY_DX8SL3IOCR_DXIOM                                                    0x2
11544
11545                 DX IO Transmitter Mode
11546                 PSU_DDR_PHY_DX8SL3IOCR_DXTXM                                                    0x0
11547
11548                 DX IO Receiver Mode
11549                 PSU_DDR_PHY_DX8SL3IOCR_DXRXM                                                    0x0
11550
11551                 DATX8 0-1 I/O Configuration Register
11552                 (OFFSET, MASK, VALUE)      (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U)
11553                 RegMask = (DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL3IOCR_DXIOM_MASK | DDR_PHY_DX8SL3IOCR_DXTXM_MASK | DDR_PHY_DX8SL3IOCR_DXRXM_MASK |  0 );
11554
11555                 RegVal = ((0x00000000U << DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT
11556                         | 0x00000007U << DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT
11557                         | 0x00000000U << DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT
11558                         | 0x00000002U << DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT
11559                         | 0x00000000U << DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT
11560                         | 0x00000000U << DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT
11561                         |  0 ) & RegMask); */
11562                 PSU_Mask_Write (DDR_PHY_DX8SL3IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
11563         /*############################################################################################################################ */
11564
11565                 /*Register : DX8SL4OSC @ 0XFD081500</p>
11566
11567                 Reserved. Return zeroes on reads.
11568                 PSU_DDR_PHY_DX8SL4OSC_RESERVED_31_30                                            0x0
11569
11570                 Enable Clock Gating for DX ddr_clk
11571                 PSU_DDR_PHY_DX8SL4OSC_GATEDXRDCLK                                               0x2
11572
11573                 Enable Clock Gating for DX ctl_rd_clk
11574                 PSU_DDR_PHY_DX8SL4OSC_GATEDXDDRCLK                                              0x2
11575
11576                 Enable Clock Gating for DX ctl_clk
11577                 PSU_DDR_PHY_DX8SL4OSC_GATEDXCTLCLK                                              0x2
11578
11579                 Selects the level to which clocks will be stalled when clock gating is enabled.
11580                 PSU_DDR_PHY_DX8SL4OSC_CLKLEVEL                                                  0x0
11581
11582                 Loopback Mode
11583                 PSU_DDR_PHY_DX8SL4OSC_LBMODE                                                    0x0
11584
11585                 Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
11586                 PSU_DDR_PHY_DX8SL4OSC_LBGSDQS                                                   0x0
11587
11588                 Loopback DQS Gating
11589                 PSU_DDR_PHY_DX8SL4OSC_LBGDQS                                                    0x0
11590
11591                 Loopback DQS Shift
11592                 PSU_DDR_PHY_DX8SL4OSC_LBDQSS                                                    0x0
11593
11594                 PHY High-Speed Reset
11595                 PSU_DDR_PHY_DX8SL4OSC_PHYHRST                                                   0x1
11596
11597                 PHY FIFO Reset
11598                 PSU_DDR_PHY_DX8SL4OSC_PHYFRST                                                   0x1
11599
11600                 Delay Line Test Start
11601                 PSU_DDR_PHY_DX8SL4OSC_DLTST                                                     0x0
11602
11603                 Delay Line Test Mode
11604                 PSU_DDR_PHY_DX8SL4OSC_DLTMODE                                                   0x0
11605
11606                 Reserved. Caution, do not write to this register field.
11607                 PSU_DDR_PHY_DX8SL4OSC_RESERVED_12_11                                            0x3
11608
11609                 Oscillator Mode Write-Data Delay Line Select
11610                 PSU_DDR_PHY_DX8SL4OSC_OSCWDDL                                                   0x3
11611
11612                 Reserved. Caution, do not write to this register field.
11613                 PSU_DDR_PHY_DX8SL4OSC_RESERVED_8_7                                              0x3
11614
11615                 Oscillator Mode Write-Leveling Delay Line Select
11616                 PSU_DDR_PHY_DX8SL4OSC_OSCWDL                                                    0x3
11617
11618                 Oscillator Mode Division
11619                 PSU_DDR_PHY_DX8SL4OSC_OSCDIV                                                    0xf
11620
11621                 Oscillator Enable
11622                 PSU_DDR_PHY_DX8SL4OSC_OSCEN                                                     0x0
11623
11624                 DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register
11625                 (OFFSET, MASK, VALUE)      (0XFD081500, 0xFFFFFFFFU ,0x2A019FFEU)
11626                 RegMask = (DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL4OSC_LBMODE_MASK | DDR_PHY_DX8SL4OSC_LBGSDQS_MASK | DDR_PHY_DX8SL4OSC_LBGDQS_MASK | DDR_PHY_DX8SL4OSC_LBDQSS_MASK | DDR_PHY_DX8SL4OSC_PHYHRST_MASK | DDR_PHY_DX8SL4OSC_PHYFRST_MASK | DDR_PHY_DX8SL4OSC_DLTST_MASK | DDR_PHY_DX8SL4OSC_DLTMODE_MASK | DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL4OSC_OSCWDDL_MASK | DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL4OSC_OSCWDL_MASK | DDR_PHY_DX8SL4OSC_OSCDIV_MASK | DDR_PHY_DX8SL4OSC_OSCEN_MASK |  0 );
11627
11628                 RegVal = ((0x00000000U << DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT
11629                         | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT
11630                         | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT
11631                         | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT
11632                         | 0x00000000U << DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT
11633                         | 0x00000000U << DDR_PHY_DX8SL4OSC_LBMODE_SHIFT
11634                         | 0x00000000U << DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT
11635                         | 0x00000000U << DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT
11636                         | 0x00000000U << DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT
11637                         | 0x00000001U << DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT
11638                         | 0x00000001U << DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT
11639                         | 0x00000000U << DDR_PHY_DX8SL4OSC_DLTST_SHIFT
11640                         | 0x00000000U << DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT
11641                         | 0x00000003U << DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT
11642                         | 0x00000003U << DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT
11643                         | 0x00000003U << DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT
11644                         | 0x00000003U << DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT
11645                         | 0x0000000FU << DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT
11646                         | 0x00000000U << DDR_PHY_DX8SL4OSC_OSCEN_SHIFT
11647                         |  0 ) & RegMask); */
11648                 PSU_Mask_Write (DDR_PHY_DX8SL4OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU);
11649         /*############################################################################################################################ */
11650
11651                 /*Register : DX8SL4DQSCTL @ 0XFD08151C</p>
11652
11653                 Reserved. Return zeroes on reads.
11654                 PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25                                         0x0
11655
11656                 Read Path Rise-to-Rise Mode
11657                 PSU_DDR_PHY_DX8SL4DQSCTL_RRRMODE                                                0x1
11658
11659                 Reserved. Return zeroes on reads.
11660                 PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22                                         0x0
11661
11662                 Write Path Rise-to-Rise Mode
11663                 PSU_DDR_PHY_DX8SL4DQSCTL_WRRMODE                                                0x1
11664
11665                 DQS Gate Extension
11666                 PSU_DDR_PHY_DX8SL4DQSCTL_DQSGX                                                  0x0
11667
11668                 Low Power PLL Power Down
11669                 PSU_DDR_PHY_DX8SL4DQSCTL_LPPLLPD                                                0x1
11670
11671                 Low Power I/O Power Down
11672                 PSU_DDR_PHY_DX8SL4DQSCTL_LPIOPD                                                 0x1
11673
11674                 Reserved. Return zeroes on reads.
11675                 PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15                                         0x0
11676
11677                 QS Counter Enable
11678                 PSU_DDR_PHY_DX8SL4DQSCTL_QSCNTEN                                                0x1
11679
11680                 Unused DQ I/O Mode
11681                 PSU_DDR_PHY_DX8SL4DQSCTL_UDQIOM                                                 0x0
11682
11683                 Reserved. Return zeroes on reads.
11684                 PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10                                         0x0
11685
11686                 Data Slew Rate
11687                 PSU_DDR_PHY_DX8SL4DQSCTL_DXSR                                                   0x3
11688
11689                 DQS_N Resistor
11690                 PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES                                                0x0
11691
11692                 DQS Resistor
11693                 PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES                                                 0x0
11694
11695                 DATX8 0-1 DQS Control Register
11696                 (OFFSET, MASK, VALUE)      (0XFD08151C, 0xFFFFFFFFU ,0x01264300U)
11697                 RegMask = (DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL4DQSCTL_DXSR_MASK | DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK |  0 );
11698
11699                 RegVal = ((0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT
11700                         | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT
11701                         | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT
11702                         | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT
11703                         | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT
11704                         | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT
11705                         | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT
11706                         | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT
11707                         | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT
11708                         | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT
11709                         | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT
11710                         | 0x00000003U << DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT
11711                         | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT
11712                         | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT
11713                         |  0 ) & RegMask); */
11714                 PSU_Mask_Write (DDR_PHY_DX8SL4DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U);
11715         /*############################################################################################################################ */
11716
11717                 /*Register : DX8SL4DXCTL2 @ 0XFD08152C</p>
11718
11719                 Reserved. Return zeroes on reads.
11720                 PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24                                         0x0
11721
11722                 Configurable Read Data Enable
11723                 PSU_DDR_PHY_DX8SL4DXCTL2_CRDEN                                                  0x0
11724
11725                 OX Extension during Post-amble
11726                 PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX                                                 0x0
11727
11728                 OE Extension during Pre-amble
11729                 PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX                                                 0x1
11730
11731                 Reserved. Return zeroes on reads.
11732                 PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17                                            0x0
11733
11734                 I/O Assisted Gate Select
11735                 PSU_DDR_PHY_DX8SL4DXCTL2_IOAG                                                   0x0
11736
11737                 I/O Loopback Select
11738                 PSU_DDR_PHY_DX8SL4DXCTL2_IOLB                                                   0x0
11739
11740                 Reserved. Return zeroes on reads.
11741                 PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13                                         0x0
11742
11743                 Low Power Wakeup Threshold
11744                 PSU_DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH                                         0xc
11745
11746                 Read Data Bus Inversion Enable
11747                 PSU_DDR_PHY_DX8SL4DXCTL2_RDBI                                                   0x0
11748
11749                 Write Data Bus Inversion Enable
11750                 PSU_DDR_PHY_DX8SL4DXCTL2_WDBI                                                   0x0
11751
11752                 PUB Read FIFO Bypass
11753                 PSU_DDR_PHY_DX8SL4DXCTL2_PRFBYP                                                 0x0
11754
11755                 DATX8 Receive FIFO Read Mode
11756                 PSU_DDR_PHY_DX8SL4DXCTL2_RDMODE                                                 0x0
11757
11758                 Disables the Read FIFO Reset
11759                 PSU_DDR_PHY_DX8SL4DXCTL2_DISRST                                                 0x0
11760
11761                 Read DQS Gate I/O Loopback
11762                 PSU_DDR_PHY_DX8SL4DXCTL2_DQSGLB                                                 0x0
11763
11764                 Reserved. Return zeroes on reads.
11765                 PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0                                             0x0
11766
11767                 DATX8 0-1 DX Control Register 2
11768                 (OFFSET, MASK, VALUE)      (0XFD08152C, 0xFFFFFFFFU ,0x00041800U)
11769                 RegMask = (DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL4DXCTL2_IOAG_MASK | DDR_PHY_DX8SL4DXCTL2_IOLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL4DXCTL2_RDBI_MASK | DDR_PHY_DX8SL4DXCTL2_WDBI_MASK | DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL4DXCTL2_DISRST_MASK | DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK |  0 );
11770
11771                 RegVal = ((0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT
11772                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT
11773                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT
11774                         | 0x00000001U << DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT
11775                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT
11776                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT
11777                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT
11778                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT
11779                         | 0x0000000CU << DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT
11780                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT
11781                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT
11782                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT
11783                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT
11784                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT
11785                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT
11786                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT
11787                         |  0 ) & RegMask); */
11788                 PSU_Mask_Write (DDR_PHY_DX8SL4DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U);
11789         /*############################################################################################################################ */
11790
11791                 /*Register : DX8SL4IOCR @ 0XFD081530</p>
11792
11793                 Reserved. Return zeroes on reads.
11794                 PSU_DDR_PHY_DX8SL4IOCR_RESERVED_31                                              0x0
11795
11796                 PVREF_DAC REFSEL range select
11797                 PSU_DDR_PHY_DX8SL4IOCR_DXDACRANGE                                               0x7
11798
11799                 IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
11800                 PSU_DDR_PHY_DX8SL4IOCR_DXVREFIOM                                                0x0
11801
11802                 DX IO Mode
11803                 PSU_DDR_PHY_DX8SL4IOCR_DXIOM                                                    0x2
11804
11805                 DX IO Transmitter Mode
11806                 PSU_DDR_PHY_DX8SL4IOCR_DXTXM                                                    0x0
11807
11808                 DX IO Receiver Mode
11809                 PSU_DDR_PHY_DX8SL4IOCR_DXRXM                                                    0x0
11810
11811                 DATX8 0-1 I/O Configuration Register
11812                 (OFFSET, MASK, VALUE)      (0XFD081530, 0xFFFFFFFFU ,0x70800000U)
11813                 RegMask = (DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL4IOCR_DXIOM_MASK | DDR_PHY_DX8SL4IOCR_DXTXM_MASK | DDR_PHY_DX8SL4IOCR_DXRXM_MASK |  0 );
11814
11815                 RegVal = ((0x00000000U << DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT
11816                         | 0x00000007U << DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT
11817                         | 0x00000000U << DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT
11818                         | 0x00000002U << DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT
11819                         | 0x00000000U << DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT
11820                         | 0x00000000U << DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT
11821                         |  0 ) & RegMask); */
11822                 PSU_Mask_Write (DDR_PHY_DX8SL4IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
11823         /*############################################################################################################################ */
11824
11825                 /*Register : DX8SLbDQSCTL @ 0XFD0817DC</p>
11826
11827                 Reserved. Return zeroes on reads.
11828                 PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25                                         0x0
11829
11830                 Read Path Rise-to-Rise Mode
11831                 PSU_DDR_PHY_DX8SLBDQSCTL_RRRMODE                                                0x1
11832
11833                 Reserved. Return zeroes on reads.
11834                 PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22                                         0x0
11835
11836                 Write Path Rise-to-Rise Mode
11837                 PSU_DDR_PHY_DX8SLBDQSCTL_WRRMODE                                                0x1
11838
11839                 DQS Gate Extension
11840                 PSU_DDR_PHY_DX8SLBDQSCTL_DQSGX                                                  0x0
11841
11842                 Low Power PLL Power Down
11843                 PSU_DDR_PHY_DX8SLBDQSCTL_LPPLLPD                                                0x1
11844
11845                 Low Power I/O Power Down
11846                 PSU_DDR_PHY_DX8SLBDQSCTL_LPIOPD                                                 0x1
11847
11848                 Reserved. Return zeroes on reads.
11849                 PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15                                         0x0
11850
11851                 QS Counter Enable
11852                 PSU_DDR_PHY_DX8SLBDQSCTL_QSCNTEN                                                0x1
11853
11854                 Unused DQ I/O Mode
11855                 PSU_DDR_PHY_DX8SLBDQSCTL_UDQIOM                                                 0x0
11856
11857                 Reserved. Return zeroes on reads.
11858                 PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10                                         0x0
11859
11860                 Data Slew Rate
11861                 PSU_DDR_PHY_DX8SLBDQSCTL_DXSR                                                   0x3
11862
11863                 DQS# Resistor
11864                 PSU_DDR_PHY_DX8SLBDQSCTL_DQSNRES                                                0xc
11865
11866                 DQS Resistor
11867                 PSU_DDR_PHY_DX8SLBDQSCTL_DQSRES                                                 0x4
11868
11869                 DATX8 0-8 DQS Control Register
11870                 (OFFSET, MASK, VALUE)      (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U)
11871                 RegMask = (DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK | DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK | DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SLBDQSCTL_DXSR_MASK | DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK | DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK |  0 );
11872
11873                 RegVal = ((0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT
11874                         | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT
11875                         | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT
11876                         | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT
11877                         | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT
11878                         | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT
11879                         | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT
11880                         | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT
11881                         | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT
11882                         | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT
11883                         | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT
11884                         | 0x00000003U << DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT
11885                         | 0x0000000CU << DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT
11886                         | 0x00000004U << DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT
11887                         |  0 ) & RegMask); */
11888                 PSU_Mask_Write (DDR_PHY_DX8SLBDQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
11889         /*############################################################################################################################ */
11890
11891                 /*Register : PIR @ 0XFD080004</p>
11892
11893                 Reserved. Return zeroes on reads.
11894                 PSU_DDR_PHY_PIR_RESERVED_31                                                     0x0
11895
11896                 Impedance Calibration Bypass
11897                 PSU_DDR_PHY_PIR_ZCALBYP                                                         0x0
11898
11899                 Digital Delay Line (DDL) Calibration Pause
11900                 PSU_DDR_PHY_PIR_DCALPSE                                                         0x0
11901
11902                 Reserved. Return zeroes on reads.
11903                 PSU_DDR_PHY_PIR_RESERVED_28_21                                                  0x0
11904
11905                 Write DQS2DQ Training
11906                 PSU_DDR_PHY_PIR_DQS2DQ                                                          0x0
11907
11908                 RDIMM Initialization
11909                 PSU_DDR_PHY_PIR_RDIMMINIT                                                       0x0
11910
11911                 Controller DRAM Initialization
11912                 PSU_DDR_PHY_PIR_CTLDINIT                                                        0x1
11913
11914                 VREF Training
11915                 PSU_DDR_PHY_PIR_VREF                                                            0x0
11916
11917                 Static Read Training
11918                 PSU_DDR_PHY_PIR_SRD                                                             0x0
11919
11920                 Write Data Eye Training
11921                 PSU_DDR_PHY_PIR_WREYE                                                           0x0
11922
11923                 Read Data Eye Training
11924                 PSU_DDR_PHY_PIR_RDEYE                                                           0x0
11925
11926                 Write Data Bit Deskew
11927                 PSU_DDR_PHY_PIR_WRDSKW                                                          0x0
11928
11929                 Read Data Bit Deskew
11930                 PSU_DDR_PHY_PIR_RDDSKW                                                          0x0
11931
11932                 Write Leveling Adjust
11933                 PSU_DDR_PHY_PIR_WLADJ                                                           0x0
11934
11935                 Read DQS Gate Training
11936                 PSU_DDR_PHY_PIR_QSGATE                                                          0x0
11937
11938                 Write Leveling
11939                 PSU_DDR_PHY_PIR_WL                                                              0x0
11940
11941                 DRAM Initialization
11942                 PSU_DDR_PHY_PIR_DRAMINIT                                                        0x0
11943
11944                 DRAM Reset (DDR3/DDR4/LPDDR4 Only)
11945                 PSU_DDR_PHY_PIR_DRAMRST                                                         0x0
11946
11947                 PHY Reset
11948                 PSU_DDR_PHY_PIR_PHYRST                                                          0x1
11949
11950                 Digital Delay Line (DDL) Calibration
11951                 PSU_DDR_PHY_PIR_DCAL                                                            0x1
11952
11953                 PLL Initialiazation
11954                 PSU_DDR_PHY_PIR_PLLINIT                                                         0x1
11955
11956                 Reserved. Return zeroes on reads.
11957                 PSU_DDR_PHY_PIR_RESERVED_3                                                      0x0
11958
11959                 CA Training
11960                 PSU_DDR_PHY_PIR_CA                                                              0x0
11961
11962                 Impedance Calibration
11963                 PSU_DDR_PHY_PIR_ZCAL                                                            0x1
11964
11965                 Initialization Trigger
11966                 PSU_DDR_PHY_PIR_INIT                                                            0x1
11967
11968                 PHY Initialization Register
11969                 (OFFSET, MASK, VALUE)      (0XFD080004, 0xFFFFFFFFU ,0x00040073U)
11970                 RegMask = (DDR_PHY_PIR_RESERVED_31_MASK | DDR_PHY_PIR_ZCALBYP_MASK | DDR_PHY_PIR_DCALPSE_MASK | DDR_PHY_PIR_RESERVED_28_21_MASK | DDR_PHY_PIR_DQS2DQ_MASK | DDR_PHY_PIR_RDIMMINIT_MASK | DDR_PHY_PIR_CTLDINIT_MASK | DDR_PHY_PIR_VREF_MASK | DDR_PHY_PIR_SRD_MASK | DDR_PHY_PIR_WREYE_MASK | DDR_PHY_PIR_RDEYE_MASK | DDR_PHY_PIR_WRDSKW_MASK | DDR_PHY_PIR_RDDSKW_MASK | DDR_PHY_PIR_WLADJ_MASK | DDR_PHY_PIR_QSGATE_MASK | DDR_PHY_PIR_WL_MASK | DDR_PHY_PIR_DRAMINIT_MASK | DDR_PHY_PIR_DRAMRST_MASK | DDR_PHY_PIR_PHYRST_MASK | DDR_PHY_PIR_DCAL_MASK | DDR_PHY_PIR_PLLINIT_MASK | DDR_PHY_PIR_RESERVED_3_MASK | DDR_PHY_PIR_CA_MASK | DDR_PHY_PIR_ZCAL_MASK | DDR_PHY_PIR_INIT_MASK |  0 );
11971
11972                 RegVal = ((0x00000000U << DDR_PHY_PIR_RESERVED_31_SHIFT
11973                         | 0x00000000U << DDR_PHY_PIR_ZCALBYP_SHIFT
11974                         | 0x00000000U << DDR_PHY_PIR_DCALPSE_SHIFT
11975                         | 0x00000000U << DDR_PHY_PIR_RESERVED_28_21_SHIFT
11976                         | 0x00000000U << DDR_PHY_PIR_DQS2DQ_SHIFT
11977                         | 0x00000000U << DDR_PHY_PIR_RDIMMINIT_SHIFT
11978                         | 0x00000001U << DDR_PHY_PIR_CTLDINIT_SHIFT
11979                         | 0x00000000U << DDR_PHY_PIR_VREF_SHIFT
11980                         | 0x00000000U << DDR_PHY_PIR_SRD_SHIFT
11981                         | 0x00000000U << DDR_PHY_PIR_WREYE_SHIFT
11982                         | 0x00000000U << DDR_PHY_PIR_RDEYE_SHIFT
11983                         | 0x00000000U << DDR_PHY_PIR_WRDSKW_SHIFT
11984                         | 0x00000000U << DDR_PHY_PIR_RDDSKW_SHIFT
11985                         | 0x00000000U << DDR_PHY_PIR_WLADJ_SHIFT
11986                         | 0x00000000U << DDR_PHY_PIR_QSGATE_SHIFT
11987                         | 0x00000000U << DDR_PHY_PIR_WL_SHIFT
11988                         | 0x00000000U << DDR_PHY_PIR_DRAMINIT_SHIFT
11989                         | 0x00000000U << DDR_PHY_PIR_DRAMRST_SHIFT
11990                         | 0x00000001U << DDR_PHY_PIR_PHYRST_SHIFT
11991                         | 0x00000001U << DDR_PHY_PIR_DCAL_SHIFT
11992                         | 0x00000001U << DDR_PHY_PIR_PLLINIT_SHIFT
11993                         | 0x00000000U << DDR_PHY_PIR_RESERVED_3_SHIFT
11994                         | 0x00000000U << DDR_PHY_PIR_CA_SHIFT
11995                         | 0x00000001U << DDR_PHY_PIR_ZCAL_SHIFT
11996                         | 0x00000001U << DDR_PHY_PIR_INIT_SHIFT
11997                         |  0 ) & RegMask); */
11998                 PSU_Mask_Write (DDR_PHY_PIR_OFFSET ,0xFFFFFFFFU ,0x00040073U);
11999         /*############################################################################################################################ */
12000
12001
12002   return 1;
12003 }
12004 unsigned long psu_mio_init_data() {
12005                 // : MIO PROGRAMMING
12006                 /*Register : MIO_PIN_0 @ 0XFF180000</p>
12007
12008                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)
12009                 PSU_IOU_SLCR_MIO_PIN_0_L0_SEL                                                   1
12010
12011                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12012                 PSU_IOU_SLCR_MIO_PIN_0_L1_SEL                                                   0
12013
12014                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp
12015                 t, test_scan_out[0]- (Test Scan Port) 3= Not Used
12016                 PSU_IOU_SLCR_MIO_PIN_0_L2_SEL                                                   0
12017
12018                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can
12019                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
12020                 ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
12021                 ) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
12022                 lk- (Trace Port Clock)
12023                 PSU_IOU_SLCR_MIO_PIN_0_L3_SEL                                                   0
12024
12025                 Configures MIO Pin 0 peripheral interface mapping. S
12026                 (OFFSET, MASK, VALUE)      (0XFF180000, 0x000000FEU ,0x00000002U)
12027                 RegMask = (IOU_SLCR_MIO_PIN_0_L0_SEL_MASK | IOU_SLCR_MIO_PIN_0_L1_SEL_MASK | IOU_SLCR_MIO_PIN_0_L2_SEL_MASK | IOU_SLCR_MIO_PIN_0_L3_SEL_MASK |  0 );
12028
12029                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT
12030                         | 0x00000000U << IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT
12031                         | 0x00000000U << IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT
12032                         | 0x00000000U << IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT
12033                         |  0 ) & RegMask); */
12034                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_0_OFFSET ,0x000000FEU ,0x00000002U);
12035         /*############################################################################################################################ */
12036
12037                 /*Register : MIO_PIN_1 @ 0XFF180004</p>
12038
12039                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data
12040                 us)
12041                 PSU_IOU_SLCR_MIO_PIN_1_L0_SEL                                                   1
12042
12043                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12044                 PSU_IOU_SLCR_MIO_PIN_1_L1_SEL                                                   0
12045
12046                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp
12047                 t, test_scan_out[1]- (Test Scan Port) 3= Not Used
12048                 PSU_IOU_SLCR_MIO_PIN_1_L2_SEL                                                   0
12049
12050                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can
12051                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
12052                  3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o
12053                 t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
12054                 Signal)
12055                 PSU_IOU_SLCR_MIO_PIN_1_L3_SEL                                                   0
12056
12057                 Configures MIO Pin 1 peripheral interface mapping
12058                 (OFFSET, MASK, VALUE)      (0XFF180004, 0x000000FEU ,0x00000002U)
12059                 RegMask = (IOU_SLCR_MIO_PIN_1_L0_SEL_MASK | IOU_SLCR_MIO_PIN_1_L1_SEL_MASK | IOU_SLCR_MIO_PIN_1_L2_SEL_MASK | IOU_SLCR_MIO_PIN_1_L3_SEL_MASK |  0 );
12060
12061                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT
12062                         | 0x00000000U << IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT
12063                         | 0x00000000U << IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT
12064                         | 0x00000000U << IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT
12065                         |  0 ) & RegMask); */
12066                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_1_OFFSET ,0x000000FEU ,0x00000002U);
12067         /*############################################################################################################################ */
12068
12069                 /*Register : MIO_PIN_2 @ 0XFF180008</p>
12070
12071                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)
12072                 PSU_IOU_SLCR_MIO_PIN_2_L0_SEL                                                   1
12073
12074                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12075                 PSU_IOU_SLCR_MIO_PIN_2_L1_SEL                                                   0
12076
12077                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp
12078                 t, test_scan_out[2]- (Test Scan Port) 3= Not Used
12079                 PSU_IOU_SLCR_MIO_PIN_2_L2_SEL                                                   0
12080
12081                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can
12082                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
12083                  3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in
12084                  (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
12085                 PSU_IOU_SLCR_MIO_PIN_2_L3_SEL                                                   0
12086
12087                 Configures MIO Pin 2 peripheral interface mapping
12088                 (OFFSET, MASK, VALUE)      (0XFF180008, 0x000000FEU ,0x00000002U)
12089                 RegMask = (IOU_SLCR_MIO_PIN_2_L0_SEL_MASK | IOU_SLCR_MIO_PIN_2_L1_SEL_MASK | IOU_SLCR_MIO_PIN_2_L2_SEL_MASK | IOU_SLCR_MIO_PIN_2_L3_SEL_MASK |  0 );
12090
12091                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT
12092                         | 0x00000000U << IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT
12093                         | 0x00000000U << IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT
12094                         | 0x00000000U << IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT
12095                         |  0 ) & RegMask); */
12096                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_2_OFFSET ,0x000000FEU ,0x00000002U);
12097         /*############################################################################################################################ */
12098
12099                 /*Register : MIO_PIN_3 @ 0XFF18000C</p>
12100
12101                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)
12102                 PSU_IOU_SLCR_MIO_PIN_3_L0_SEL                                                   1
12103
12104                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12105                 PSU_IOU_SLCR_MIO_PIN_3_L1_SEL                                                   0
12106
12107                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp
12108                 t, test_scan_out[3]- (Test Scan Port) 3= Not Used
12109                 PSU_IOU_SLCR_MIO_PIN_3_L2_SEL                                                   0
12110
12111                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can
12112                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
12113                 ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
12114                 - (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
12115                 output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
12116                 PSU_IOU_SLCR_MIO_PIN_3_L3_SEL                                                   0
12117
12118                 Configures MIO Pin 3 peripheral interface mapping
12119                 (OFFSET, MASK, VALUE)      (0XFF18000C, 0x000000FEU ,0x00000002U)
12120                 RegMask = (IOU_SLCR_MIO_PIN_3_L0_SEL_MASK | IOU_SLCR_MIO_PIN_3_L1_SEL_MASK | IOU_SLCR_MIO_PIN_3_L2_SEL_MASK | IOU_SLCR_MIO_PIN_3_L3_SEL_MASK |  0 );
12121
12122                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT
12123                         | 0x00000000U << IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT
12124                         | 0x00000000U << IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT
12125                         | 0x00000000U << IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT
12126                         |  0 ) & RegMask); */
12127                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_3_OFFSET ,0x000000FEU ,0x00000002U);
12128         /*############################################################################################################################ */
12129
12130                 /*Register : MIO_PIN_4 @ 0XFF180010</p>
12131
12132                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data
12133                 us)
12134                 PSU_IOU_SLCR_MIO_PIN_4_L0_SEL                                                   1
12135
12136                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12137                 PSU_IOU_SLCR_MIO_PIN_4_L1_SEL                                                   0
12138
12139                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp
12140                 t, test_scan_out[4]- (Test Scan Port) 3= Not Used
12141                 PSU_IOU_SLCR_MIO_PIN_4_L2_SEL                                                   0
12142
12143                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can
12144                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
12145                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
12146                 - (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
12147                 utput, tracedq[2]- (Trace Port Databus)
12148                 PSU_IOU_SLCR_MIO_PIN_4_L3_SEL                                                   0
12149
12150                 Configures MIO Pin 4 peripheral interface mapping
12151                 (OFFSET, MASK, VALUE)      (0XFF180010, 0x000000FEU ,0x00000002U)
12152                 RegMask = (IOU_SLCR_MIO_PIN_4_L0_SEL_MASK | IOU_SLCR_MIO_PIN_4_L1_SEL_MASK | IOU_SLCR_MIO_PIN_4_L2_SEL_MASK | IOU_SLCR_MIO_PIN_4_L3_SEL_MASK |  0 );
12153
12154                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT
12155                         | 0x00000000U << IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT
12156                         | 0x00000000U << IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT
12157                         | 0x00000000U << IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT
12158                         |  0 ) & RegMask); */
12159                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_4_OFFSET ,0x000000FEU ,0x00000002U);
12160         /*############################################################################################################################ */
12161
12162                 /*Register : MIO_PIN_5 @ 0XFF180014</p>
12163
12164                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)
12165                 PSU_IOU_SLCR_MIO_PIN_5_L0_SEL                                                   1
12166
12167                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12168                 PSU_IOU_SLCR_MIO_PIN_5_L1_SEL                                                   0
12169
12170                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp
12171                 t, test_scan_out[5]- (Test Scan Port) 3= Not Used
12172                 PSU_IOU_SLCR_MIO_PIN_5_L2_SEL                                                   0
12173
12174                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can
12175                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
12176                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
12177                 si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
12178                  trace, Output, tracedq[3]- (Trace Port Databus)
12179                 PSU_IOU_SLCR_MIO_PIN_5_L3_SEL                                                   0
12180
12181                 Configures MIO Pin 5 peripheral interface mapping
12182                 (OFFSET, MASK, VALUE)      (0XFF180014, 0x000000FEU ,0x00000002U)
12183                 RegMask = (IOU_SLCR_MIO_PIN_5_L0_SEL_MASK | IOU_SLCR_MIO_PIN_5_L1_SEL_MASK | IOU_SLCR_MIO_PIN_5_L2_SEL_MASK | IOU_SLCR_MIO_PIN_5_L3_SEL_MASK |  0 );
12184
12185                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT
12186                         | 0x00000000U << IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT
12187                         | 0x00000000U << IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT
12188                         | 0x00000000U << IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT
12189                         |  0 ) & RegMask); */
12190                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_5_OFFSET ,0x000000FEU ,0x00000002U);
12191         /*############################################################################################################################ */
12192
12193                 /*Register : MIO_PIN_6 @ 0XFF180018</p>
12194
12195                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)
12196                 PSU_IOU_SLCR_MIO_PIN_6_L0_SEL                                                   1
12197
12198                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12199                 PSU_IOU_SLCR_MIO_PIN_6_L1_SEL                                                   0
12200
12201                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp
12202                 t, test_scan_out[6]- (Test Scan Port) 3= Not Used
12203                 PSU_IOU_SLCR_MIO_PIN_6_L2_SEL                                                   0
12204
12205                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can
12206                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
12207                  3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1
12208                 sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
12209                 Output, tracedq[4]- (Trace Port Databus)
12210                 PSU_IOU_SLCR_MIO_PIN_6_L3_SEL                                                   0
12211
12212                 Configures MIO Pin 6 peripheral interface mapping
12213                 (OFFSET, MASK, VALUE)      (0XFF180018, 0x000000FEU ,0x00000002U)
12214                 RegMask = (IOU_SLCR_MIO_PIN_6_L0_SEL_MASK | IOU_SLCR_MIO_PIN_6_L1_SEL_MASK | IOU_SLCR_MIO_PIN_6_L2_SEL_MASK | IOU_SLCR_MIO_PIN_6_L3_SEL_MASK |  0 );
12215
12216                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT
12217                         | 0x00000000U << IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT
12218                         | 0x00000000U << IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT
12219                         | 0x00000000U << IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT
12220                         |  0 ) & RegMask); */
12221                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_6_OFFSET ,0x000000FEU ,0x00000002U);
12222         /*############################################################################################################################ */
12223
12224                 /*Register : MIO_PIN_7 @ 0XFF18001C</p>
12225
12226                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)
12227                 PSU_IOU_SLCR_MIO_PIN_7_L0_SEL                                                   1
12228
12229                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12230                 PSU_IOU_SLCR_MIO_PIN_7_L1_SEL                                                   0
12231
12232                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp
12233                 t, test_scan_out[7]- (Test Scan Port) 3= Not Used
12234                 PSU_IOU_SLCR_MIO_PIN_7_L2_SEL                                                   0
12235
12236                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can
12237                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
12238                 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
12239                 tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output,
12240                 racedq[5]- (Trace Port Databus)
12241                 PSU_IOU_SLCR_MIO_PIN_7_L3_SEL                                                   0
12242
12243                 Configures MIO Pin 7 peripheral interface mapping
12244                 (OFFSET, MASK, VALUE)      (0XFF18001C, 0x000000FEU ,0x00000002U)
12245                 RegMask = (IOU_SLCR_MIO_PIN_7_L0_SEL_MASK | IOU_SLCR_MIO_PIN_7_L1_SEL_MASK | IOU_SLCR_MIO_PIN_7_L2_SEL_MASK | IOU_SLCR_MIO_PIN_7_L3_SEL_MASK |  0 );
12246
12247                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT
12248                         | 0x00000000U << IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT
12249                         | 0x00000000U << IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT
12250                         | 0x00000000U << IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT
12251                         |  0 ) & RegMask); */
12252                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_7_OFFSET ,0x000000FEU ,0x00000002U);
12253         /*############################################################################################################################ */
12254
12255                 /*Register : MIO_PIN_8 @ 0XFF180020</p>
12256
12257                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
12258                 [0]- (QSPI Upper Databus)
12259                 PSU_IOU_SLCR_MIO_PIN_8_L0_SEL                                                   1
12260
12261                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12262                 PSU_IOU_SLCR_MIO_PIN_8_L1_SEL                                                   0
12263
12264                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp
12265                 t, test_scan_out[8]- (Test Scan Port) 3= Not Used
12266                 PSU_IOU_SLCR_MIO_PIN_8_L2_SEL                                                   0
12267
12268                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can
12269                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
12270                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc
12271                 , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr
12272                 ce Port Databus)
12273                 PSU_IOU_SLCR_MIO_PIN_8_L3_SEL                                                   0
12274
12275                 Configures MIO Pin 8 peripheral interface mapping
12276                 (OFFSET, MASK, VALUE)      (0XFF180020, 0x000000FEU ,0x00000002U)
12277                 RegMask = (IOU_SLCR_MIO_PIN_8_L0_SEL_MASK | IOU_SLCR_MIO_PIN_8_L1_SEL_MASK | IOU_SLCR_MIO_PIN_8_L2_SEL_MASK | IOU_SLCR_MIO_PIN_8_L3_SEL_MASK |  0 );
12278
12279                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT
12280                         | 0x00000000U << IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT
12281                         | 0x00000000U << IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT
12282                         | 0x00000000U << IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT
12283                         |  0 ) & RegMask); */
12284                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_8_OFFSET ,0x000000FEU ,0x00000002U);
12285         /*############################################################################################################################ */
12286
12287                 /*Register : MIO_PIN_9 @ 0XFF180024</p>
12288
12289                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
12290                 [1]- (QSPI Upper Databus)
12291                 PSU_IOU_SLCR_MIO_PIN_9_L0_SEL                                                   1
12292
12293                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
12294                 PSU_IOU_SLCR_MIO_PIN_9_L1_SEL                                                   0
12295
12296                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp
12297                 t, test_scan_out[9]- (Test Scan Port) 3= Not Used
12298                 PSU_IOU_SLCR_MIO_PIN_9_L2_SEL                                                   0
12299
12300                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can
12301                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
12302                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
12303                 utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U
12304                 RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)
12305                 PSU_IOU_SLCR_MIO_PIN_9_L3_SEL                                                   0
12306
12307                 Configures MIO Pin 9 peripheral interface mapping
12308                 (OFFSET, MASK, VALUE)      (0XFF180024, 0x000000FEU ,0x00000002U)
12309                 RegMask = (IOU_SLCR_MIO_PIN_9_L0_SEL_MASK | IOU_SLCR_MIO_PIN_9_L1_SEL_MASK | IOU_SLCR_MIO_PIN_9_L2_SEL_MASK | IOU_SLCR_MIO_PIN_9_L3_SEL_MASK |  0 );
12310
12311                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT
12312                         | 0x00000000U << IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT
12313                         | 0x00000000U << IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT
12314                         | 0x00000000U << IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT
12315                         |  0 ) & RegMask); */
12316                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_9_OFFSET ,0x000000FEU ,0x00000002U);
12317         /*############################################################################################################################ */
12318
12319                 /*Register : MIO_PIN_10 @ 0XFF180028</p>
12320
12321                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
12322                 [2]- (QSPI Upper Databus)
12323                 PSU_IOU_SLCR_MIO_PIN_10_L0_SEL                                                  1
12324
12325                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
12326                 PSU_IOU_SLCR_MIO_PIN_10_L1_SEL                                                  0
12327
12328                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out
12329                 ut, test_scan_out[10]- (Test Scan Port) 3= Not Used
12330                 PSU_IOU_SLCR_MIO_PIN_10_L2_SEL                                                  0
12331
12332                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c
12333                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
12334                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
12335                 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
12336                 t, tracedq[8]- (Trace Port Databus)
12337                 PSU_IOU_SLCR_MIO_PIN_10_L3_SEL                                                  0
12338
12339                 Configures MIO Pin 10 peripheral interface mapping
12340                 (OFFSET, MASK, VALUE)      (0XFF180028, 0x000000FEU ,0x00000002U)
12341                 RegMask = (IOU_SLCR_MIO_PIN_10_L0_SEL_MASK | IOU_SLCR_MIO_PIN_10_L1_SEL_MASK | IOU_SLCR_MIO_PIN_10_L2_SEL_MASK | IOU_SLCR_MIO_PIN_10_L3_SEL_MASK |  0 );
12342
12343                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT
12344                         | 0x00000000U << IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT
12345                         | 0x00000000U << IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT
12346                         | 0x00000000U << IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT
12347                         |  0 ) & RegMask); */
12348                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_10_OFFSET ,0x000000FEU ,0x00000002U);
12349         /*############################################################################################################################ */
12350
12351                 /*Register : MIO_PIN_11 @ 0XFF18002C</p>
12352
12353                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
12354                 [3]- (QSPI Upper Databus)
12355                 PSU_IOU_SLCR_MIO_PIN_11_L0_SEL                                                  1
12356
12357                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
12358                 PSU_IOU_SLCR_MIO_PIN_11_L1_SEL                                                  0
12359
12360                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out
12361                 ut, test_scan_out[11]- (Test Scan Port) 3= Not Used
12362                 PSU_IOU_SLCR_MIO_PIN_11_L2_SEL                                                  0
12363
12364                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c
12365                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
12366                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
12367                 i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
12368                 tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
12369                 PSU_IOU_SLCR_MIO_PIN_11_L3_SEL                                                  0
12370
12371                 Configures MIO Pin 11 peripheral interface mapping
12372                 (OFFSET, MASK, VALUE)      (0XFF18002C, 0x000000FEU ,0x00000002U)
12373                 RegMask = (IOU_SLCR_MIO_PIN_11_L0_SEL_MASK | IOU_SLCR_MIO_PIN_11_L1_SEL_MASK | IOU_SLCR_MIO_PIN_11_L2_SEL_MASK | IOU_SLCR_MIO_PIN_11_L3_SEL_MASK |  0 );
12374
12375                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT
12376                         | 0x00000000U << IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT
12377                         | 0x00000000U << IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT
12378                         | 0x00000000U << IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT
12379                         |  0 ) & RegMask); */
12380                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_11_OFFSET ,0x000000FEU ,0x00000002U);
12381         /*############################################################################################################################ */
12382
12383                 /*Register : MIO_PIN_12 @ 0XFF180030</p>
12384
12385                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)
12386                 PSU_IOU_SLCR_MIO_PIN_12_L0_SEL                                                  1
12387
12388                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
12389
12390                 PSU_IOU_SLCR_MIO_PIN_12_L1_SEL                                                  0
12391
12392                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out
12393                 ut, test_scan_out[12]- (Test Scan Port) 3= Not Used
12394                 PSU_IOU_SLCR_MIO_PIN_12_L2_SEL                                                  0
12395
12396                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c
12397                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
12398                 al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl
12399                 ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac
12400                 dq[10]- (Trace Port Databus)
12401                 PSU_IOU_SLCR_MIO_PIN_12_L3_SEL                                                  0
12402
12403                 Configures MIO Pin 12 peripheral interface mapping
12404                 (OFFSET, MASK, VALUE)      (0XFF180030, 0x000000FEU ,0x00000002U)
12405                 RegMask = (IOU_SLCR_MIO_PIN_12_L0_SEL_MASK | IOU_SLCR_MIO_PIN_12_L1_SEL_MASK | IOU_SLCR_MIO_PIN_12_L2_SEL_MASK | IOU_SLCR_MIO_PIN_12_L3_SEL_MASK |  0 );
12406
12407                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT
12408                         | 0x00000000U << IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT
12409                         | 0x00000000U << IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT
12410                         | 0x00000000U << IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT
12411                         |  0 ) & RegMask); */
12412                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_12_OFFSET ,0x000000FEU ,0x00000002U);
12413         /*############################################################################################################################ */
12414
12415                 /*Register : MIO_PIN_13 @ 0XFF180034</p>
12416
12417                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12418                 PSU_IOU_SLCR_MIO_PIN_13_L0_SEL                                                  0
12419
12420                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)
12421                 PSU_IOU_SLCR_MIO_PIN_13_L1_SEL                                                  0
12422
12423                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
12424                 bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port
12425                  3= Not Used
12426                 PSU_IOU_SLCR_MIO_PIN_13_L2_SEL                                                  0
12427
12428                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c
12429                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
12430                 l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave
12431                 out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat
12432                 bus)
12433                 PSU_IOU_SLCR_MIO_PIN_13_L3_SEL                                                  0
12434
12435                 Configures MIO Pin 13 peripheral interface mapping
12436                 (OFFSET, MASK, VALUE)      (0XFF180034, 0x000000FEU ,0x00000000U)
12437                 RegMask = (IOU_SLCR_MIO_PIN_13_L0_SEL_MASK | IOU_SLCR_MIO_PIN_13_L1_SEL_MASK | IOU_SLCR_MIO_PIN_13_L2_SEL_MASK | IOU_SLCR_MIO_PIN_13_L3_SEL_MASK |  0 );
12438
12439                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT
12440                         | 0x00000000U << IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT
12441                         | 0x00000000U << IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT
12442                         | 0x00000000U << IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT
12443                         |  0 ) & RegMask); */
12444                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_13_OFFSET ,0x000000FEU ,0x00000000U);
12445         /*############################################################################################################################ */
12446
12447                 /*Register : MIO_PIN_14 @ 0XFF180038</p>
12448
12449                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12450                 PSU_IOU_SLCR_MIO_PIN_14_L0_SEL                                                  0
12451
12452                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)
12453                 PSU_IOU_SLCR_MIO_PIN_14_L1_SEL                                                  0
12454
12455                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
12456                 bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port
12457                  3= Not Used
12458                 PSU_IOU_SLCR_MIO_PIN_14_L2_SEL                                                  0
12459
12460                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c
12461                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
12462                 l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_
12463                 n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)
12464                 PSU_IOU_SLCR_MIO_PIN_14_L3_SEL                                                  2
12465
12466                 Configures MIO Pin 14 peripheral interface mapping
12467                 (OFFSET, MASK, VALUE)      (0XFF180038, 0x000000FEU ,0x00000040U)
12468                 RegMask = (IOU_SLCR_MIO_PIN_14_L0_SEL_MASK | IOU_SLCR_MIO_PIN_14_L1_SEL_MASK | IOU_SLCR_MIO_PIN_14_L2_SEL_MASK | IOU_SLCR_MIO_PIN_14_L3_SEL_MASK |  0 );
12469
12470                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT
12471                         | 0x00000000U << IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT
12472                         | 0x00000000U << IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT
12473                         | 0x00000002U << IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT
12474                         |  0 ) & RegMask); */
12475                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_14_OFFSET ,0x000000FEU ,0x00000040U);
12476         /*############################################################################################################################ */
12477
12478                 /*Register : MIO_PIN_15 @ 0XFF18003C</p>
12479
12480                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12481                 PSU_IOU_SLCR_MIO_PIN_15_L0_SEL                                                  0
12482
12483                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)
12484                 PSU_IOU_SLCR_MIO_PIN_15_L1_SEL                                                  0
12485
12486                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
12487                 bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port
12488                  3= Not Used
12489                 PSU_IOU_SLCR_MIO_PIN_15_L2_SEL                                                  0
12490
12491                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c
12492                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
12493                 al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out
12494                 0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri
12495                 l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
12496                 PSU_IOU_SLCR_MIO_PIN_15_L3_SEL                                                  2
12497
12498                 Configures MIO Pin 15 peripheral interface mapping
12499                 (OFFSET, MASK, VALUE)      (0XFF18003C, 0x000000FEU ,0x00000040U)
12500                 RegMask = (IOU_SLCR_MIO_PIN_15_L0_SEL_MASK | IOU_SLCR_MIO_PIN_15_L1_SEL_MASK | IOU_SLCR_MIO_PIN_15_L2_SEL_MASK | IOU_SLCR_MIO_PIN_15_L3_SEL_MASK |  0 );
12501
12502                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT
12503                         | 0x00000000U << IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT
12504                         | 0x00000000U << IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT
12505                         | 0x00000002U << IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT
12506                         |  0 ) & RegMask); */
12507                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_15_OFFSET ,0x000000FEU ,0x00000040U);
12508         /*############################################################################################################################ */
12509
12510                 /*Register : MIO_PIN_16 @ 0XFF180040</p>
12511
12512                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12513                 PSU_IOU_SLCR_MIO_PIN_16_L0_SEL                                                  0
12514
12515                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND
12516                 ata Bus)
12517                 PSU_IOU_SLCR_MIO_PIN_16_L1_SEL                                                  0
12518
12519                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
12520                 bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port
12521                  3= Not Used
12522                 PSU_IOU_SLCR_MIO_PIN_16_L2_SEL                                                  0
12523
12524                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c
12525                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
12526                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
12527                 so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
12528                  Output, tracedq[14]- (Trace Port Databus)
12529                 PSU_IOU_SLCR_MIO_PIN_16_L3_SEL                                                  2
12530
12531                 Configures MIO Pin 16 peripheral interface mapping
12532                 (OFFSET, MASK, VALUE)      (0XFF180040, 0x000000FEU ,0x00000040U)
12533                 RegMask = (IOU_SLCR_MIO_PIN_16_L0_SEL_MASK | IOU_SLCR_MIO_PIN_16_L1_SEL_MASK | IOU_SLCR_MIO_PIN_16_L2_SEL_MASK | IOU_SLCR_MIO_PIN_16_L3_SEL_MASK |  0 );
12534
12535                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT
12536                         | 0x00000000U << IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT
12537                         | 0x00000000U << IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT
12538                         | 0x00000002U << IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT
12539                         |  0 ) & RegMask); */
12540                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_16_OFFSET ,0x000000FEU ,0x00000040U);
12541         /*############################################################################################################################ */
12542
12543                 /*Register : MIO_PIN_17 @ 0XFF180044</p>
12544
12545                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12546                 PSU_IOU_SLCR_MIO_PIN_17_L0_SEL                                                  0
12547
12548                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND
12549                 ata Bus)
12550                 PSU_IOU_SLCR_MIO_PIN_17_L1_SEL                                                  0
12551
12552                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
12553                 bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port
12554                  3= Not Used
12555                 PSU_IOU_SLCR_MIO_PIN_17_L2_SEL                                                  0
12556
12557                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c
12558                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
12559                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
12560                 0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
12561                 7= trace, Output, tracedq[15]- (Trace Port Databus)
12562                 PSU_IOU_SLCR_MIO_PIN_17_L3_SEL                                                  2
12563
12564                 Configures MIO Pin 17 peripheral interface mapping
12565                 (OFFSET, MASK, VALUE)      (0XFF180044, 0x000000FEU ,0x00000040U)
12566                 RegMask = (IOU_SLCR_MIO_PIN_17_L0_SEL_MASK | IOU_SLCR_MIO_PIN_17_L1_SEL_MASK | IOU_SLCR_MIO_PIN_17_L2_SEL_MASK | IOU_SLCR_MIO_PIN_17_L3_SEL_MASK |  0 );
12567
12568                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT
12569                         | 0x00000000U << IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT
12570                         | 0x00000000U << IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT
12571                         | 0x00000002U << IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT
12572                         |  0 ) & RegMask); */
12573                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_17_OFFSET ,0x000000FEU ,0x00000040U);
12574         /*############################################################################################################################ */
12575
12576                 /*Register : MIO_PIN_18 @ 0XFF180048</p>
12577
12578                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12579                 PSU_IOU_SLCR_MIO_PIN_18_L0_SEL                                                  0
12580
12581                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND
12582                 ata Bus)
12583                 PSU_IOU_SLCR_MIO_PIN_18_L1_SEL                                                  0
12584
12585                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
12586                 bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port
12587                  3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12588                 PSU_IOU_SLCR_MIO_PIN_18_L2_SEL                                                  0
12589
12590                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c
12591                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
12592                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
12593                 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
12594                 PSU_IOU_SLCR_MIO_PIN_18_L3_SEL                                                  6
12595
12596                 Configures MIO Pin 18 peripheral interface mapping
12597                 (OFFSET, MASK, VALUE)      (0XFF180048, 0x000000FEU ,0x000000C0U)
12598                 RegMask = (IOU_SLCR_MIO_PIN_18_L0_SEL_MASK | IOU_SLCR_MIO_PIN_18_L1_SEL_MASK | IOU_SLCR_MIO_PIN_18_L2_SEL_MASK | IOU_SLCR_MIO_PIN_18_L3_SEL_MASK |  0 );
12599
12600                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT
12601                         | 0x00000000U << IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT
12602                         | 0x00000000U << IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT
12603                         | 0x00000006U << IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT
12604                         |  0 ) & RegMask); */
12605                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_18_OFFSET ,0x000000FEU ,0x000000C0U);
12606         /*############################################################################################################################ */
12607
12608                 /*Register : MIO_PIN_19 @ 0XFF18004C</p>
12609
12610                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12611                 PSU_IOU_SLCR_MIO_PIN_19_L0_SEL                                                  0
12612
12613                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND
12614                 ata Bus)
12615                 PSU_IOU_SLCR_MIO_PIN_19_L1_SEL                                                  0
12616
12617                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
12618                 bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port
12619                  3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12620                 PSU_IOU_SLCR_MIO_PIN_19_L2_SEL                                                  0
12621
12622                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c
12623                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
12624                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
12625                  ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
12626                 PSU_IOU_SLCR_MIO_PIN_19_L3_SEL                                                  6
12627
12628                 Configures MIO Pin 19 peripheral interface mapping
12629                 (OFFSET, MASK, VALUE)      (0XFF18004C, 0x000000FEU ,0x000000C0U)
12630                 RegMask = (IOU_SLCR_MIO_PIN_19_L0_SEL_MASK | IOU_SLCR_MIO_PIN_19_L1_SEL_MASK | IOU_SLCR_MIO_PIN_19_L2_SEL_MASK | IOU_SLCR_MIO_PIN_19_L3_SEL_MASK |  0 );
12631
12632                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT
12633                         | 0x00000000U << IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT
12634                         | 0x00000000U << IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT
12635                         | 0x00000006U << IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT
12636                         |  0 ) & RegMask); */
12637                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_19_OFFSET ,0x000000FEU ,0x000000C0U);
12638         /*############################################################################################################################ */
12639
12640                 /*Register : MIO_PIN_20 @ 0XFF180050</p>
12641
12642                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12643                 PSU_IOU_SLCR_MIO_PIN_20_L0_SEL                                                  0
12644
12645                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND
12646                 ata Bus)
12647                 PSU_IOU_SLCR_MIO_PIN_20_L1_SEL                                                  0
12648
12649                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
12650                 bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port
12651                  3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12652                 PSU_IOU_SLCR_MIO_PIN_20_L2_SEL                                                  0
12653
12654                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c
12655                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
12656                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t
12657                 c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
12658                 PSU_IOU_SLCR_MIO_PIN_20_L3_SEL                                                  6
12659
12660                 Configures MIO Pin 20 peripheral interface mapping
12661                 (OFFSET, MASK, VALUE)      (0XFF180050, 0x000000FEU ,0x000000C0U)
12662                 RegMask = (IOU_SLCR_MIO_PIN_20_L0_SEL_MASK | IOU_SLCR_MIO_PIN_20_L1_SEL_MASK | IOU_SLCR_MIO_PIN_20_L2_SEL_MASK | IOU_SLCR_MIO_PIN_20_L3_SEL_MASK |  0 );
12663
12664                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT
12665                         | 0x00000000U << IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT
12666                         | 0x00000000U << IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT
12667                         | 0x00000006U << IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT
12668                         |  0 ) & RegMask); */
12669                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_20_OFFSET ,0x000000FEU ,0x000000C0U);
12670         /*############################################################################################################################ */
12671
12672                 /*Register : MIO_PIN_21 @ 0XFF180054</p>
12673
12674                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12675                 PSU_IOU_SLCR_MIO_PIN_21_L0_SEL                                                  0
12676
12677                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND
12678                 ata Bus)
12679                 PSU_IOU_SLCR_MIO_PIN_21_L1_SEL                                                  0
12680
12681                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
12682                  Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port)
12683                 = csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12684                 PSU_IOU_SLCR_MIO_PIN_21_L2_SEL                                                  0
12685
12686                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c
12687                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
12688                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
12689                  Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd-
12690                 UART receiver serial input) 7= Not Used
12691                 PSU_IOU_SLCR_MIO_PIN_21_L3_SEL                                                  6
12692
12693                 Configures MIO Pin 21 peripheral interface mapping
12694                 (OFFSET, MASK, VALUE)      (0XFF180054, 0x000000FEU ,0x000000C0U)
12695                 RegMask = (IOU_SLCR_MIO_PIN_21_L0_SEL_MASK | IOU_SLCR_MIO_PIN_21_L1_SEL_MASK | IOU_SLCR_MIO_PIN_21_L2_SEL_MASK | IOU_SLCR_MIO_PIN_21_L3_SEL_MASK |  0 );
12696
12697                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT
12698                         | 0x00000000U << IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT
12699                         | 0x00000000U << IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT
12700                         | 0x00000006U << IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT
12701                         |  0 ) & RegMask); */
12702                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_21_OFFSET ,0x000000FEU ,0x000000C0U);
12703         /*############################################################################################################################ */
12704
12705                 /*Register : MIO_PIN_22 @ 0XFF180058</p>
12706
12707                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12708                 PSU_IOU_SLCR_MIO_PIN_22_L0_SEL                                                  0
12709
12710                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)
12711                 PSU_IOU_SLCR_MIO_PIN_22_L1_SEL                                                  0
12712
12713                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]-
12714                 (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12715                 PSU_IOU_SLCR_MIO_PIN_22_L2_SEL                                                  0
12716
12717                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c
12718                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
12719                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
12720                 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not
12721                 sed
12722                 PSU_IOU_SLCR_MIO_PIN_22_L3_SEL                                                  0
12723
12724                 Configures MIO Pin 22 peripheral interface mapping
12725                 (OFFSET, MASK, VALUE)      (0XFF180058, 0x000000FEU ,0x00000000U)
12726                 RegMask = (IOU_SLCR_MIO_PIN_22_L0_SEL_MASK | IOU_SLCR_MIO_PIN_22_L1_SEL_MASK | IOU_SLCR_MIO_PIN_22_L2_SEL_MASK | IOU_SLCR_MIO_PIN_22_L3_SEL_MASK |  0 );
12727
12728                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT
12729                         | 0x00000000U << IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT
12730                         | 0x00000000U << IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT
12731                         | 0x00000000U << IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT
12732                         |  0 ) & RegMask); */
12733                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_22_OFFSET ,0x000000FEU ,0x00000000U);
12734         /*############################################################################################################################ */
12735
12736                 /*Register : MIO_PIN_23 @ 0XFF18005C</p>
12737
12738                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12739                 PSU_IOU_SLCR_MIO_PIN_23_L0_SEL                                                  0
12740
12741                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND
12742                 ata Bus)
12743                 PSU_IOU_SLCR_MIO_PIN_23_L1_SEL                                                  0
12744
12745                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in
12746                 23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper
12747
12748                 PSU_IOU_SLCR_MIO_PIN_23_L2_SEL                                                  0
12749
12750                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c
12751                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
12752                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
12753                 i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
12754                 tput) 7= Not Used
12755                 PSU_IOU_SLCR_MIO_PIN_23_L3_SEL                                                  0
12756
12757                 Configures MIO Pin 23 peripheral interface mapping
12758                 (OFFSET, MASK, VALUE)      (0XFF18005C, 0x000000FEU ,0x00000000U)
12759                 RegMask = (IOU_SLCR_MIO_PIN_23_L0_SEL_MASK | IOU_SLCR_MIO_PIN_23_L1_SEL_MASK | IOU_SLCR_MIO_PIN_23_L2_SEL_MASK | IOU_SLCR_MIO_PIN_23_L3_SEL_MASK |  0 );
12760
12761                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT
12762                         | 0x00000000U << IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT
12763                         | 0x00000000U << IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT
12764                         | 0x00000000U << IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT
12765                         |  0 ) & RegMask); */
12766                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_23_OFFSET ,0x000000FEU ,0x00000000U);
12767         /*############################################################################################################################ */
12768
12769                 /*Register : MIO_PIN_24 @ 0XFF180060</p>
12770
12771                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12772                 PSU_IOU_SLCR_MIO_PIN_24_L0_SEL                                                  0
12773
12774                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND
12775                 ata Bus)
12776                 PSU_IOU_SLCR_MIO_PIN_24_L1_SEL                                                  0
12777
12778                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test
12779                 scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex
12780                  Tamper)
12781                 PSU_IOU_SLCR_MIO_PIN_24_L2_SEL                                                  0
12782
12783                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c
12784                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
12785                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1,
12786                 Output, ua1_txd- (UART transmitter serial output) 7= Not Used
12787                 PSU_IOU_SLCR_MIO_PIN_24_L3_SEL                                                  1
12788
12789                 Configures MIO Pin 24 peripheral interface mapping
12790                 (OFFSET, MASK, VALUE)      (0XFF180060, 0x000000FEU ,0x00000020U)
12791                 RegMask = (IOU_SLCR_MIO_PIN_24_L0_SEL_MASK | IOU_SLCR_MIO_PIN_24_L1_SEL_MASK | IOU_SLCR_MIO_PIN_24_L2_SEL_MASK | IOU_SLCR_MIO_PIN_24_L3_SEL_MASK |  0 );
12792
12793                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT
12794                         | 0x00000000U << IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT
12795                         | 0x00000000U << IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT
12796                         | 0x00000001U << IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT
12797                         |  0 ) & RegMask); */
12798                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_24_OFFSET ,0x000000FEU ,0x00000020U);
12799         /*############################################################################################################################ */
12800
12801                 /*Register : MIO_PIN_25 @ 0XFF180064</p>
12802
12803                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12804                 PSU_IOU_SLCR_MIO_PIN_25_L0_SEL                                                  0
12805
12806                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)
12807                 PSU_IOU_SLCR_MIO_PIN_25_L1_SEL                                                  0
12808
12809                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input,
12810                 test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C
12811                 U Ext Tamper)
12812                 PSU_IOU_SLCR_MIO_PIN_25_L2_SEL                                                  0
12813
12814                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c
12815                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
12816                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform
12817                 lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
12818                 PSU_IOU_SLCR_MIO_PIN_25_L3_SEL                                                  1
12819
12820                 Configures MIO Pin 25 peripheral interface mapping
12821                 (OFFSET, MASK, VALUE)      (0XFF180064, 0x000000FEU ,0x00000020U)
12822                 RegMask = (IOU_SLCR_MIO_PIN_25_L0_SEL_MASK | IOU_SLCR_MIO_PIN_25_L1_SEL_MASK | IOU_SLCR_MIO_PIN_25_L2_SEL_MASK | IOU_SLCR_MIO_PIN_25_L3_SEL_MASK |  0 );
12823
12824                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT
12825                         | 0x00000000U << IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT
12826                         | 0x00000000U << IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT
12827                         | 0x00000001U << IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT
12828                         |  0 ) & RegMask); */
12829                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_25_OFFSET ,0x000000FEU ,0x00000020U);
12830         /*############################################################################################################################ */
12831
12832                 /*Register : MIO_PIN_26 @ 0XFF180068</p>
12833
12834                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)
12835                 PSU_IOU_SLCR_MIO_PIN_26_L0_SEL                                                  0
12836
12837                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
12838                 PSU_IOU_SLCR_MIO_PIN_26_L1_SEL                                                  0
12839
12840                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc
12841                 n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12842                 PSU_IOU_SLCR_MIO_PIN_26_L2_SEL                                                  0
12843
12844                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can
12845                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
12846                  3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock
12847                  5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]-
12848                 Trace Port Databus)
12849                 PSU_IOU_SLCR_MIO_PIN_26_L3_SEL                                                  0
12850
12851                 Configures MIO Pin 26 peripheral interface mapping
12852                 (OFFSET, MASK, VALUE)      (0XFF180068, 0x000000FEU ,0x00000000U)
12853                 RegMask = (IOU_SLCR_MIO_PIN_26_L0_SEL_MASK | IOU_SLCR_MIO_PIN_26_L1_SEL_MASK | IOU_SLCR_MIO_PIN_26_L2_SEL_MASK | IOU_SLCR_MIO_PIN_26_L3_SEL_MASK |  0 );
12854
12855                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT
12856                         | 0x00000000U << IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT
12857                         | 0x00000000U << IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT
12858                         | 0x00000000U << IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT
12859                         |  0 ) & RegMask); */
12860                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_26_OFFSET ,0x000000FEU ,0x00000000U);
12861         /*############################################################################################################################ */
12862
12863                 /*Register : MIO_PIN_27 @ 0XFF18006C</p>
12864
12865                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)
12866                 PSU_IOU_SLCR_MIO_PIN_27_L0_SEL                                                  0
12867
12868                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
12869                 PSU_IOU_SLCR_MIO_PIN_27_L1_SEL                                                  0
12870
12871                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc
12872                 n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
12873                 t, dp_aux_data_out- (Dp Aux Data)
12874                 PSU_IOU_SLCR_MIO_PIN_27_L2_SEL                                                  3
12875
12876                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can
12877                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
12878                 ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
12879                 ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port
12880                 atabus)
12881                 PSU_IOU_SLCR_MIO_PIN_27_L3_SEL                                                  0
12882
12883                 Configures MIO Pin 27 peripheral interface mapping
12884                 (OFFSET, MASK, VALUE)      (0XFF18006C, 0x000000FEU ,0x00000018U)
12885                 RegMask = (IOU_SLCR_MIO_PIN_27_L0_SEL_MASK | IOU_SLCR_MIO_PIN_27_L1_SEL_MASK | IOU_SLCR_MIO_PIN_27_L2_SEL_MASK | IOU_SLCR_MIO_PIN_27_L3_SEL_MASK |  0 );
12886
12887                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT
12888                         | 0x00000000U << IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT
12889                         | 0x00000003U << IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT
12890                         | 0x00000000U << IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT
12891                         |  0 ) & RegMask); */
12892                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_27_OFFSET ,0x000000FEU ,0x00000018U);
12893         /*############################################################################################################################ */
12894
12895                 /*Register : MIO_PIN_28 @ 0XFF180070</p>
12896
12897                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)
12898                 PSU_IOU_SLCR_MIO_PIN_28_L0_SEL                                                  0
12899
12900                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
12901                 PSU_IOU_SLCR_MIO_PIN_28_L1_SEL                                                  0
12902
12903                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc
12904                 n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
12905                 PSU_IOU_SLCR_MIO_PIN_28_L2_SEL                                                  3
12906
12907                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can
12908                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
12909                 ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
12910                 - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
12911                 PSU_IOU_SLCR_MIO_PIN_28_L3_SEL                                                  0
12912
12913                 Configures MIO Pin 28 peripheral interface mapping
12914                 (OFFSET, MASK, VALUE)      (0XFF180070, 0x000000FEU ,0x00000018U)
12915                 RegMask = (IOU_SLCR_MIO_PIN_28_L0_SEL_MASK | IOU_SLCR_MIO_PIN_28_L1_SEL_MASK | IOU_SLCR_MIO_PIN_28_L2_SEL_MASK | IOU_SLCR_MIO_PIN_28_L3_SEL_MASK |  0 );
12916
12917                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT
12918                         | 0x00000000U << IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT
12919                         | 0x00000003U << IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT
12920                         | 0x00000000U << IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT
12921                         |  0 ) & RegMask); */
12922                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_28_OFFSET ,0x000000FEU ,0x00000018U);
12923         /*############################################################################################################################ */
12924
12925                 /*Register : MIO_PIN_29 @ 0XFF180074</p>
12926
12927                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)
12928                 PSU_IOU_SLCR_MIO_PIN_29_L0_SEL                                                  0
12929
12930                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
12931                 PSU_IOU_SLCR_MIO_PIN_29_L1_SEL                                                  0
12932
12933                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc
12934                 n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
12935                 t, dp_aux_data_out- (Dp Aux Data)
12936                 PSU_IOU_SLCR_MIO_PIN_29_L2_SEL                                                  3
12937
12938                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can
12939                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
12940                  3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]
12941                  (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
12942                 ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
12943                 PSU_IOU_SLCR_MIO_PIN_29_L3_SEL                                                  0
12944
12945                 Configures MIO Pin 29 peripheral interface mapping
12946                 (OFFSET, MASK, VALUE)      (0XFF180074, 0x000000FEU ,0x00000018U)
12947                 RegMask = (IOU_SLCR_MIO_PIN_29_L0_SEL_MASK | IOU_SLCR_MIO_PIN_29_L1_SEL_MASK | IOU_SLCR_MIO_PIN_29_L2_SEL_MASK | IOU_SLCR_MIO_PIN_29_L3_SEL_MASK |  0 );
12948
12949                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT
12950                         | 0x00000000U << IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT
12951                         | 0x00000003U << IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT
12952                         | 0x00000000U << IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT
12953                         |  0 ) & RegMask); */
12954                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_29_OFFSET ,0x000000FEU ,0x00000018U);
12955         /*############################################################################################################################ */
12956
12957                 /*Register : MIO_PIN_30 @ 0XFF180078</p>
12958
12959                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)
12960                 PSU_IOU_SLCR_MIO_PIN_30_L0_SEL                                                  0
12961
12962                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
12963                 PSU_IOU_SLCR_MIO_PIN_30_L1_SEL                                                  0
12964
12965                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc
12966                 n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
12967                 PSU_IOU_SLCR_MIO_PIN_30_L2_SEL                                                  3
12968
12969                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can
12970                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
12971                  3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so
12972                  (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output
12973                  tracedq[8]- (Trace Port Databus)
12974                 PSU_IOU_SLCR_MIO_PIN_30_L3_SEL                                                  0
12975
12976                 Configures MIO Pin 30 peripheral interface mapping
12977                 (OFFSET, MASK, VALUE)      (0XFF180078, 0x000000FEU ,0x00000018U)
12978                 RegMask = (IOU_SLCR_MIO_PIN_30_L0_SEL_MASK | IOU_SLCR_MIO_PIN_30_L1_SEL_MASK | IOU_SLCR_MIO_PIN_30_L2_SEL_MASK | IOU_SLCR_MIO_PIN_30_L3_SEL_MASK |  0 );
12979
12980                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT
12981                         | 0x00000000U << IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT
12982                         | 0x00000003U << IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT
12983                         | 0x00000000U << IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT
12984                         |  0 ) & RegMask); */
12985                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_30_OFFSET ,0x000000FEU ,0x00000018U);
12986         /*############################################################################################################################ */
12987
12988                 /*Register : MIO_PIN_31 @ 0XFF18007C</p>
12989
12990                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)
12991                 PSU_IOU_SLCR_MIO_PIN_31_L0_SEL                                                  0
12992
12993                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
12994                 PSU_IOU_SLCR_MIO_PIN_31_L1_SEL                                                  0
12995
12996                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc
12997                 n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12998                 PSU_IOU_SLCR_MIO_PIN_31_L2_SEL                                                  0
12999
13000                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can
13001                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
13002                 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi
13003                 _si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out
13004                 ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)
13005                 PSU_IOU_SLCR_MIO_PIN_31_L3_SEL                                                  0
13006
13007                 Configures MIO Pin 31 peripheral interface mapping
13008                 (OFFSET, MASK, VALUE)      (0XFF18007C, 0x000000FEU ,0x00000000U)
13009                 RegMask = (IOU_SLCR_MIO_PIN_31_L0_SEL_MASK | IOU_SLCR_MIO_PIN_31_L1_SEL_MASK | IOU_SLCR_MIO_PIN_31_L2_SEL_MASK | IOU_SLCR_MIO_PIN_31_L3_SEL_MASK |  0 );
13010
13011                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT
13012                         | 0x00000000U << IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT
13013                         | 0x00000000U << IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT
13014                         | 0x00000000U << IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT
13015                         |  0 ) & RegMask); */
13016                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_31_OFFSET ,0x000000FEU ,0x00000000U);
13017         /*############################################################################################################################ */
13018
13019                 /*Register : MIO_PIN_32 @ 0XFF180080</p>
13020
13021                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)
13022                 PSU_IOU_SLCR_MIO_PIN_32_L0_SEL                                                  0
13023
13024                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
13025
13026                 PSU_IOU_SLCR_MIO_PIN_32_L1_SEL                                                  0
13027
13028                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S
13029                 an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
13030                 PSU_IOU_SLCR_MIO_PIN_32_L2_SEL                                                  1
13031
13032                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can
13033                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
13034                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi
13035                 _sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7=
13036                 race, Output, tracedq[10]- (Trace Port Databus)
13037                 PSU_IOU_SLCR_MIO_PIN_32_L3_SEL                                                  0
13038
13039                 Configures MIO Pin 32 peripheral interface mapping
13040                 (OFFSET, MASK, VALUE)      (0XFF180080, 0x000000FEU ,0x00000008U)
13041                 RegMask = (IOU_SLCR_MIO_PIN_32_L0_SEL_MASK | IOU_SLCR_MIO_PIN_32_L1_SEL_MASK | IOU_SLCR_MIO_PIN_32_L2_SEL_MASK | IOU_SLCR_MIO_PIN_32_L3_SEL_MASK |  0 );
13042
13043                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT
13044                         | 0x00000000U << IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT
13045                         | 0x00000001U << IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT
13046                         | 0x00000000U << IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT
13047                         |  0 ) & RegMask); */
13048                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_32_OFFSET ,0x000000FEU ,0x00000008U);
13049         /*############################################################################################################################ */
13050
13051                 /*Register : MIO_PIN_33 @ 0XFF180084</p>
13052
13053                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)
13054                 PSU_IOU_SLCR_MIO_PIN_33_L0_SEL                                                  0
13055
13056                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
13057                 PSU_IOU_SLCR_MIO_PIN_33_L1_SEL                                                  0
13058
13059                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S
13060                 an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
13061                 PSU_IOU_SLCR_MIO_PIN_33_L2_SEL                                                  1
13062
13063                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can
13064                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
13065                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t
13066                 c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced
13067                 [11]- (Trace Port Databus)
13068                 PSU_IOU_SLCR_MIO_PIN_33_L3_SEL                                                  0
13069
13070                 Configures MIO Pin 33 peripheral interface mapping
13071                 (OFFSET, MASK, VALUE)      (0XFF180084, 0x000000FEU ,0x00000008U)
13072                 RegMask = (IOU_SLCR_MIO_PIN_33_L0_SEL_MASK | IOU_SLCR_MIO_PIN_33_L1_SEL_MASK | IOU_SLCR_MIO_PIN_33_L2_SEL_MASK | IOU_SLCR_MIO_PIN_33_L3_SEL_MASK |  0 );
13073
13074                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT
13075                         | 0x00000000U << IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT
13076                         | 0x00000001U << IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT
13077                         | 0x00000000U << IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT
13078                         |  0 ) & RegMask); */
13079                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_33_OFFSET ,0x000000FEU ,0x00000008U);
13080         /*############################################################################################################################ */
13081
13082                 /*Register : MIO_PIN_34 @ 0XFF180088</p>
13083
13084                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)
13085                 PSU_IOU_SLCR_MIO_PIN_34_L0_SEL                                                  0
13086
13087                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
13088                 PSU_IOU_SLCR_MIO_PIN_34_L1_SEL                                                  0
13089
13090                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S
13091                 an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
13092                 ut, dp_aux_data_out- (Dp Aux Data)
13093                 PSU_IOU_SLCR_MIO_PIN_34_L2_SEL                                                  1
13094
13095                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can
13096                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
13097                  3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2
13098                  Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P
13099                 rt Databus)
13100                 PSU_IOU_SLCR_MIO_PIN_34_L3_SEL                                                  0
13101
13102                 Configures MIO Pin 34 peripheral interface mapping
13103                 (OFFSET, MASK, VALUE)      (0XFF180088, 0x000000FEU ,0x00000008U)
13104                 RegMask = (IOU_SLCR_MIO_PIN_34_L0_SEL_MASK | IOU_SLCR_MIO_PIN_34_L1_SEL_MASK | IOU_SLCR_MIO_PIN_34_L2_SEL_MASK | IOU_SLCR_MIO_PIN_34_L3_SEL_MASK |  0 );
13105
13106                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT
13107                         | 0x00000000U << IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT
13108                         | 0x00000001U << IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT
13109                         | 0x00000000U << IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT
13110                         |  0 ) & RegMask); */
13111                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_34_OFFSET ,0x000000FEU ,0x00000008U);
13112         /*############################################################################################################################ */
13113
13114                 /*Register : MIO_PIN_35 @ 0XFF18008C</p>
13115
13116                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)
13117                 PSU_IOU_SLCR_MIO_PIN_35_L0_SEL                                                  0
13118
13119                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
13120                 PSU_IOU_SLCR_MIO_PIN_35_L1_SEL                                                  0
13121
13122                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S
13123                 an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
13124                 PSU_IOU_SLCR_MIO_PIN_35_L2_SEL                                                  1
13125
13126                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can
13127                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
13128                 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
13129                 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd-
13130                 UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
13131                 PSU_IOU_SLCR_MIO_PIN_35_L3_SEL                                                  0
13132
13133                 Configures MIO Pin 35 peripheral interface mapping
13134                 (OFFSET, MASK, VALUE)      (0XFF18008C, 0x000000FEU ,0x00000008U)
13135                 RegMask = (IOU_SLCR_MIO_PIN_35_L0_SEL_MASK | IOU_SLCR_MIO_PIN_35_L1_SEL_MASK | IOU_SLCR_MIO_PIN_35_L2_SEL_MASK | IOU_SLCR_MIO_PIN_35_L3_SEL_MASK |  0 );
13136
13137                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT
13138                         | 0x00000000U << IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT
13139                         | 0x00000001U << IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT
13140                         | 0x00000000U << IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT
13141                         |  0 ) & RegMask); */
13142                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_35_OFFSET ,0x000000FEU ,0x00000008U);
13143         /*############################################################################################################################ */
13144
13145                 /*Register : MIO_PIN_36 @ 0XFF180090</p>
13146
13147                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)
13148                 PSU_IOU_SLCR_MIO_PIN_36_L0_SEL                                                  0
13149
13150                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
13151                 PSU_IOU_SLCR_MIO_PIN_36_L1_SEL                                                  0
13152
13153                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S
13154                 an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
13155                 ut, dp_aux_data_out- (Dp Aux Data)
13156                 PSU_IOU_SLCR_MIO_PIN_36_L2_SEL                                                  1
13157
13158                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c
13159                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
13160                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
13161                 so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
13162                  Output, tracedq[14]- (Trace Port Databus)
13163                 PSU_IOU_SLCR_MIO_PIN_36_L3_SEL                                                  0
13164
13165                 Configures MIO Pin 36 peripheral interface mapping
13166                 (OFFSET, MASK, VALUE)      (0XFF180090, 0x000000FEU ,0x00000008U)
13167                 RegMask = (IOU_SLCR_MIO_PIN_36_L0_SEL_MASK | IOU_SLCR_MIO_PIN_36_L1_SEL_MASK | IOU_SLCR_MIO_PIN_36_L2_SEL_MASK | IOU_SLCR_MIO_PIN_36_L3_SEL_MASK |  0 );
13168
13169                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT
13170                         | 0x00000000U << IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT
13171                         | 0x00000001U << IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT
13172                         | 0x00000000U << IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT
13173                         |  0 ) & RegMask); */
13174                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_36_OFFSET ,0x000000FEU ,0x00000008U);
13175         /*############################################################################################################################ */
13176
13177                 /*Register : MIO_PIN_37 @ 0XFF180094</p>
13178
13179                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )
13180                 PSU_IOU_SLCR_MIO_PIN_37_L0_SEL                                                  0
13181
13182                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
13183                 PSU_IOU_SLCR_MIO_PIN_37_L1_SEL                                                  0
13184
13185                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S
13186                 an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
13187                 PSU_IOU_SLCR_MIO_PIN_37_L2_SEL                                                  1
13188
13189                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c
13190                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
13191                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
13192                 1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
13193                 7= trace, Output, tracedq[15]- (Trace Port Databus)
13194                 PSU_IOU_SLCR_MIO_PIN_37_L3_SEL                                                  0
13195
13196                 Configures MIO Pin 37 peripheral interface mapping
13197                 (OFFSET, MASK, VALUE)      (0XFF180094, 0x000000FEU ,0x00000008U)
13198                 RegMask = (IOU_SLCR_MIO_PIN_37_L0_SEL_MASK | IOU_SLCR_MIO_PIN_37_L1_SEL_MASK | IOU_SLCR_MIO_PIN_37_L2_SEL_MASK | IOU_SLCR_MIO_PIN_37_L3_SEL_MASK |  0 );
13199
13200                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT
13201                         | 0x00000000U << IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT
13202                         | 0x00000001U << IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT
13203                         | 0x00000000U << IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT
13204                         |  0 ) & RegMask); */
13205                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_37_OFFSET ,0x000000FEU ,0x00000008U);
13206         /*############################################################################################################################ */
13207
13208                 /*Register : MIO_PIN_38 @ 0XFF180098</p>
13209
13210                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)
13211                 PSU_IOU_SLCR_MIO_PIN_38_L0_SEL                                                  0
13212
13213                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13214                 PSU_IOU_SLCR_MIO_PIN_38_L1_SEL                                                  0
13215
13216                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
13217                 PSU_IOU_SLCR_MIO_PIN_38_L2_SEL                                                  0
13218
13219                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c
13220                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
13221                 l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo
13222                 k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
13223                 (Trace Port Clock)
13224                 PSU_IOU_SLCR_MIO_PIN_38_L3_SEL                                                  0
13225
13226                 Configures MIO Pin 38 peripheral interface mapping
13227                 (OFFSET, MASK, VALUE)      (0XFF180098, 0x000000FEU ,0x00000000U)
13228                 RegMask = (IOU_SLCR_MIO_PIN_38_L0_SEL_MASK | IOU_SLCR_MIO_PIN_38_L1_SEL_MASK | IOU_SLCR_MIO_PIN_38_L2_SEL_MASK | IOU_SLCR_MIO_PIN_38_L3_SEL_MASK |  0 );
13229
13230                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT
13231                         | 0x00000000U << IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT
13232                         | 0x00000000U << IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT
13233                         | 0x00000000U << IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT
13234                         |  0 ) & RegMask); */
13235                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_38_OFFSET ,0x000000FEU ,0x00000000U);
13236         /*############################################################################################################################ */
13237
13238                 /*Register : MIO_PIN_39 @ 0XFF18009C</p>
13239
13240                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)
13241                 PSU_IOU_SLCR_MIO_PIN_39_L0_SEL                                                  0
13242
13243                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13244                 PSU_IOU_SLCR_MIO_PIN_39_L1_SEL                                                  0
13245
13246                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i
13247                 [4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used
13248                 PSU_IOU_SLCR_MIO_PIN_39_L2_SEL                                                  0
13249
13250                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c
13251                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
13252                 al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav
13253                 _out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
13254                 Control Signal)
13255                 PSU_IOU_SLCR_MIO_PIN_39_L3_SEL                                                  0
13256
13257                 Configures MIO Pin 39 peripheral interface mapping
13258                 (OFFSET, MASK, VALUE)      (0XFF18009C, 0x000000FEU ,0x00000000U)
13259                 RegMask = (IOU_SLCR_MIO_PIN_39_L0_SEL_MASK | IOU_SLCR_MIO_PIN_39_L1_SEL_MASK | IOU_SLCR_MIO_PIN_39_L2_SEL_MASK | IOU_SLCR_MIO_PIN_39_L3_SEL_MASK |  0 );
13260
13261                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT
13262                         | 0x00000000U << IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT
13263                         | 0x00000000U << IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT
13264                         | 0x00000000U << IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT
13265                         |  0 ) & RegMask); */
13266                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_39_OFFSET ,0x000000FEU ,0x00000000U);
13267         /*############################################################################################################################ */
13268
13269                 /*Register : MIO_PIN_40 @ 0XFF1800A0</p>
13270
13271                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)
13272                 PSU_IOU_SLCR_MIO_PIN_40_L0_SEL                                                  0
13273
13274                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13275                 PSU_IOU_SLCR_MIO_PIN_40_L1_SEL                                                  0
13276
13277                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
13278                  Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used
13279                 PSU_IOU_SLCR_MIO_PIN_40_L2_SEL                                                  0
13280
13281                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c
13282                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
13283                 al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk
13284                 in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)
13285                 PSU_IOU_SLCR_MIO_PIN_40_L3_SEL                                                  0
13286
13287                 Configures MIO Pin 40 peripheral interface mapping
13288                 (OFFSET, MASK, VALUE)      (0XFF1800A0, 0x000000FEU ,0x00000000U)
13289                 RegMask = (IOU_SLCR_MIO_PIN_40_L0_SEL_MASK | IOU_SLCR_MIO_PIN_40_L1_SEL_MASK | IOU_SLCR_MIO_PIN_40_L2_SEL_MASK | IOU_SLCR_MIO_PIN_40_L3_SEL_MASK |  0 );
13290
13291                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT
13292                         | 0x00000000U << IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT
13293                         | 0x00000000U << IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT
13294                         | 0x00000000U << IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT
13295                         |  0 ) & RegMask); */
13296                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_40_OFFSET ,0x000000FEU ,0x00000000U);
13297         /*############################################################################################################################ */
13298
13299                 /*Register : MIO_PIN_41 @ 0XFF1800A4</p>
13300
13301                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)
13302                 PSU_IOU_SLCR_MIO_PIN_41_L0_SEL                                                  0
13303
13304                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13305                 PSU_IOU_SLCR_MIO_PIN_41_L1_SEL                                                  0
13306
13307                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
13308                 bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used
13309                 PSU_IOU_SLCR_MIO_PIN_41_L2_SEL                                                  0
13310
13311                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c
13312                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
13313                 l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[
13314                 ]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
13315                 ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)
13316                 PSU_IOU_SLCR_MIO_PIN_41_L3_SEL                                                  0
13317
13318                 Configures MIO Pin 41 peripheral interface mapping
13319                 (OFFSET, MASK, VALUE)      (0XFF1800A4, 0x000000FEU ,0x00000000U)
13320                 RegMask = (IOU_SLCR_MIO_PIN_41_L0_SEL_MASK | IOU_SLCR_MIO_PIN_41_L1_SEL_MASK | IOU_SLCR_MIO_PIN_41_L2_SEL_MASK | IOU_SLCR_MIO_PIN_41_L3_SEL_MASK |  0 );
13321
13322                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT
13323                         | 0x00000000U << IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT
13324                         | 0x00000000U << IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT
13325                         | 0x00000000U << IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT
13326                         |  0 ) & RegMask); */
13327                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_41_OFFSET ,0x000000FEU ,0x00000000U);
13328         /*############################################################################################################################ */
13329
13330                 /*Register : MIO_PIN_42 @ 0XFF1800A8</p>
13331
13332                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)
13333                 PSU_IOU_SLCR_MIO_PIN_42_L0_SEL                                                  0
13334
13335                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13336                 PSU_IOU_SLCR_MIO_PIN_42_L1_SEL                                                  0
13337
13338                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
13339                 bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used
13340                 PSU_IOU_SLCR_MIO_PIN_42_L2_SEL                                                  0
13341
13342                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c
13343                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
13344                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_
13345                 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
13346                 t, tracedq[2]- (Trace Port Databus)
13347                 PSU_IOU_SLCR_MIO_PIN_42_L3_SEL                                                  0
13348
13349                 Configures MIO Pin 42 peripheral interface mapping
13350                 (OFFSET, MASK, VALUE)      (0XFF1800A8, 0x000000FEU ,0x00000000U)
13351                 RegMask = (IOU_SLCR_MIO_PIN_42_L0_SEL_MASK | IOU_SLCR_MIO_PIN_42_L1_SEL_MASK | IOU_SLCR_MIO_PIN_42_L2_SEL_MASK | IOU_SLCR_MIO_PIN_42_L3_SEL_MASK |  0 );
13352
13353                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT
13354                         | 0x00000000U << IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT
13355                         | 0x00000000U << IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT
13356                         | 0x00000000U << IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT
13357                         |  0 ) & RegMask); */
13358                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_42_OFFSET ,0x000000FEU ,0x00000000U);
13359         /*############################################################################################################################ */
13360
13361                 /*Register : MIO_PIN_43 @ 0XFF1800AC</p>
13362
13363                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)
13364                 PSU_IOU_SLCR_MIO_PIN_43_L0_SEL                                                  0
13365
13366                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13367                 PSU_IOU_SLCR_MIO_PIN_43_L1_SEL                                                  0
13368
13369                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
13370                 bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
13371                 PSU_IOU_SLCR_MIO_PIN_43_L2_SEL                                                  2
13372
13373                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c
13374                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
13375                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s
13376                 i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
13377                 tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)
13378                 PSU_IOU_SLCR_MIO_PIN_43_L3_SEL                                                  0
13379
13380                 Configures MIO Pin 43 peripheral interface mapping
13381                 (OFFSET, MASK, VALUE)      (0XFF1800AC, 0x000000FEU ,0x00000010U)
13382                 RegMask = (IOU_SLCR_MIO_PIN_43_L0_SEL_MASK | IOU_SLCR_MIO_PIN_43_L1_SEL_MASK | IOU_SLCR_MIO_PIN_43_L2_SEL_MASK | IOU_SLCR_MIO_PIN_43_L3_SEL_MASK |  0 );
13383
13384                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT
13385                         | 0x00000000U << IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT
13386                         | 0x00000002U << IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT
13387                         | 0x00000000U << IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT
13388                         |  0 ) & RegMask); */
13389                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_43_OFFSET ,0x000000FEU ,0x00000010U);
13390         /*############################################################################################################################ */
13391
13392                 /*Register : MIO_PIN_44 @ 0XFF1800B0</p>
13393
13394                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)
13395                 PSU_IOU_SLCR_MIO_PIN_44_L0_SEL                                                  0
13396
13397                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13398                 PSU_IOU_SLCR_MIO_PIN_44_L1_SEL                                                  0
13399
13400                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
13401                 bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
13402                 PSU_IOU_SLCR_MIO_PIN_44_L2_SEL                                                  2
13403
13404                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c
13405                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
13406                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s
13407                 i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
13408                  Not Used
13409                 PSU_IOU_SLCR_MIO_PIN_44_L3_SEL                                                  0
13410
13411                 Configures MIO Pin 44 peripheral interface mapping
13412                 (OFFSET, MASK, VALUE)      (0XFF1800B0, 0x000000FEU ,0x00000010U)
13413                 RegMask = (IOU_SLCR_MIO_PIN_44_L0_SEL_MASK | IOU_SLCR_MIO_PIN_44_L1_SEL_MASK | IOU_SLCR_MIO_PIN_44_L2_SEL_MASK | IOU_SLCR_MIO_PIN_44_L3_SEL_MASK |  0 );
13414
13415                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT
13416                         | 0x00000000U << IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT
13417                         | 0x00000002U << IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT
13418                         | 0x00000000U << IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT
13419                         |  0 ) & RegMask); */
13420                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_44_OFFSET ,0x000000FEU ,0x00000010U);
13421         /*############################################################################################################################ */
13422
13423                 /*Register : MIO_PIN_45 @ 0XFF1800B4</p>
13424
13425                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)
13426                 PSU_IOU_SLCR_MIO_PIN_45_L0_SEL                                                  0
13427
13428                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13429                 PSU_IOU_SLCR_MIO_PIN_45_L1_SEL                                                  0
13430
13431                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
13432                 bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
13433                 PSU_IOU_SLCR_MIO_PIN_45_L2_SEL                                                  2
13434
13435                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c
13436                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
13437                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
13438                 ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
13439                 PSU_IOU_SLCR_MIO_PIN_45_L3_SEL                                                  0
13440
13441                 Configures MIO Pin 45 peripheral interface mapping
13442                 (OFFSET, MASK, VALUE)      (0XFF1800B4, 0x000000FEU ,0x00000010U)
13443                 RegMask = (IOU_SLCR_MIO_PIN_45_L0_SEL_MASK | IOU_SLCR_MIO_PIN_45_L1_SEL_MASK | IOU_SLCR_MIO_PIN_45_L2_SEL_MASK | IOU_SLCR_MIO_PIN_45_L3_SEL_MASK |  0 );
13444
13445                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT
13446                         | 0x00000000U << IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT
13447                         | 0x00000002U << IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT
13448                         | 0x00000000U << IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT
13449                         |  0 ) & RegMask); */
13450                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_45_OFFSET ,0x000000FEU ,0x00000010U);
13451         /*############################################################################################################################ */
13452
13453                 /*Register : MIO_PIN_46 @ 0XFF1800B8</p>
13454
13455                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)
13456                 PSU_IOU_SLCR_MIO_PIN_46_L0_SEL                                                  0
13457
13458                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13459                 PSU_IOU_SLCR_MIO_PIN_46_L1_SEL                                                  0
13460
13461                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
13462                 bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
13463                 PSU_IOU_SLCR_MIO_PIN_46_L2_SEL                                                  2
13464
13465                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c
13466                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
13467                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt
13468                 0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
13469                 PSU_IOU_SLCR_MIO_PIN_46_L3_SEL                                                  0
13470
13471                 Configures MIO Pin 46 peripheral interface mapping
13472                 (OFFSET, MASK, VALUE)      (0XFF1800B8, 0x000000FEU ,0x00000010U)
13473                 RegMask = (IOU_SLCR_MIO_PIN_46_L0_SEL_MASK | IOU_SLCR_MIO_PIN_46_L1_SEL_MASK | IOU_SLCR_MIO_PIN_46_L2_SEL_MASK | IOU_SLCR_MIO_PIN_46_L3_SEL_MASK |  0 );
13474
13475                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT
13476                         | 0x00000000U << IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT
13477                         | 0x00000002U << IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT
13478                         | 0x00000000U << IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT
13479                         |  0 ) & RegMask); */
13480                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_46_OFFSET ,0x000000FEU ,0x00000010U);
13481         /*############################################################################################################################ */
13482
13483                 /*Register : MIO_PIN_47 @ 0XFF1800BC</p>
13484
13485                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)
13486                 PSU_IOU_SLCR_MIO_PIN_47_L0_SEL                                                  0
13487
13488                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13489                 PSU_IOU_SLCR_MIO_PIN_47_L1_SEL                                                  0
13490
13491                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
13492                 bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
13493                 PSU_IOU_SLCR_MIO_PIN_47_L2_SEL                                                  2
13494
13495                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c
13496                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
13497                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi
13498                 , Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
13499                  (UART transmitter serial output) 7= Not Used
13500                 PSU_IOU_SLCR_MIO_PIN_47_L3_SEL                                                  0
13501
13502                 Configures MIO Pin 47 peripheral interface mapping
13503                 (OFFSET, MASK, VALUE)      (0XFF1800BC, 0x000000FEU ,0x00000010U)
13504                 RegMask = (IOU_SLCR_MIO_PIN_47_L0_SEL_MASK | IOU_SLCR_MIO_PIN_47_L1_SEL_MASK | IOU_SLCR_MIO_PIN_47_L2_SEL_MASK | IOU_SLCR_MIO_PIN_47_L3_SEL_MASK |  0 );
13505
13506                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT
13507                         | 0x00000000U << IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT
13508                         | 0x00000002U << IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT
13509                         | 0x00000000U << IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT
13510                         |  0 ) & RegMask); */
13511                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_47_OFFSET ,0x000000FEU ,0x00000010U);
13512         /*############################################################################################################################ */
13513
13514                 /*Register : MIO_PIN_48 @ 0XFF1800C0</p>
13515
13516                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)
13517                 PSU_IOU_SLCR_MIO_PIN_48_L0_SEL                                                  0
13518
13519                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13520                 PSU_IOU_SLCR_MIO_PIN_48_L1_SEL                                                  0
13521
13522                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
13523                 bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
13524                 PSU_IOU_SLCR_MIO_PIN_48_L2_SEL                                                  2
13525
13526                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c
13527                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
13528                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
13529                 so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U
13530                 ed
13531                 PSU_IOU_SLCR_MIO_PIN_48_L3_SEL                                                  0
13532
13533                 Configures MIO Pin 48 peripheral interface mapping
13534                 (OFFSET, MASK, VALUE)      (0XFF1800C0, 0x000000FEU ,0x00000010U)
13535                 RegMask = (IOU_SLCR_MIO_PIN_48_L0_SEL_MASK | IOU_SLCR_MIO_PIN_48_L1_SEL_MASK | IOU_SLCR_MIO_PIN_48_L2_SEL_MASK | IOU_SLCR_MIO_PIN_48_L3_SEL_MASK |  0 );
13536
13537                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT
13538                         | 0x00000000U << IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT
13539                         | 0x00000002U << IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT
13540                         | 0x00000000U << IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT
13541                         |  0 ) & RegMask); */
13542                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_48_OFFSET ,0x000000FEU ,0x00000010U);
13543         /*############################################################################################################################ */
13544
13545                 /*Register : MIO_PIN_49 @ 0XFF1800C4</p>
13546
13547                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )
13548                 PSU_IOU_SLCR_MIO_PIN_49_L0_SEL                                                  0
13549
13550                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13551                 PSU_IOU_SLCR_MIO_PIN_49_L1_SEL                                                  0
13552
13553                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8
13554                 bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
13555                 PSU_IOU_SLCR_MIO_PIN_49_L2_SEL                                                  2
13556
13557                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c
13558                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
13559                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
13560                 1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
13561                 7= Not Used
13562                 PSU_IOU_SLCR_MIO_PIN_49_L3_SEL                                                  0
13563
13564                 Configures MIO Pin 49 peripheral interface mapping
13565                 (OFFSET, MASK, VALUE)      (0XFF1800C4, 0x000000FEU ,0x00000010U)
13566                 RegMask = (IOU_SLCR_MIO_PIN_49_L0_SEL_MASK | IOU_SLCR_MIO_PIN_49_L1_SEL_MASK | IOU_SLCR_MIO_PIN_49_L2_SEL_MASK | IOU_SLCR_MIO_PIN_49_L3_SEL_MASK |  0 );
13567
13568                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT
13569                         | 0x00000000U << IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT
13570                         | 0x00000002U << IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT
13571                         | 0x00000000U << IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT
13572                         |  0 ) & RegMask); */
13573                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_49_OFFSET ,0x000000FEU ,0x00000010U);
13574         /*############################################################################################################################ */
13575
13576                 /*Register : MIO_PIN_50 @ 0XFF1800C8</p>
13577
13578                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
13579                 PSU_IOU_SLCR_MIO_PIN_50_L0_SEL                                                  0
13580
13581                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13582                 PSU_IOU_SLCR_MIO_PIN_50_L1_SEL                                                  0
13583
13584                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c
13585                 d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
13586                 PSU_IOU_SLCR_MIO_PIN_50_L2_SEL                                                  2
13587
13588                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c
13589                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
13590                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2
13591                 clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
13592                 PSU_IOU_SLCR_MIO_PIN_50_L3_SEL                                                  0
13593
13594                 Configures MIO Pin 50 peripheral interface mapping
13595                 (OFFSET, MASK, VALUE)      (0XFF1800C8, 0x000000FEU ,0x00000010U)
13596                 RegMask = (IOU_SLCR_MIO_PIN_50_L0_SEL_MASK | IOU_SLCR_MIO_PIN_50_L1_SEL_MASK | IOU_SLCR_MIO_PIN_50_L2_SEL_MASK | IOU_SLCR_MIO_PIN_50_L3_SEL_MASK |  0 );
13597
13598                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT
13599                         | 0x00000000U << IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT
13600                         | 0x00000002U << IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT
13601                         | 0x00000000U << IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT
13602                         |  0 ) & RegMask); */
13603                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_50_OFFSET ,0x000000FEU ,0x00000010U);
13604         /*############################################################################################################################ */
13605
13606                 /*Register : MIO_PIN_51 @ 0XFF1800CC</p>
13607
13608                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
13609                 PSU_IOU_SLCR_MIO_PIN_51_L0_SEL                                                  0
13610
13611                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13612                 PSU_IOU_SLCR_MIO_PIN_51_L1_SEL                                                  0
13613
13614                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used
13615                 PSU_IOU_SLCR_MIO_PIN_51_L2_SEL                                                  2
13616
13617                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c
13618                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
13619                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp
13620                 t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
13621                 serial output) 7= Not Used
13622                 PSU_IOU_SLCR_MIO_PIN_51_L3_SEL                                                  0
13623
13624                 Configures MIO Pin 51 peripheral interface mapping
13625                 (OFFSET, MASK, VALUE)      (0XFF1800CC, 0x000000FEU ,0x00000010U)
13626                 RegMask = (IOU_SLCR_MIO_PIN_51_L0_SEL_MASK | IOU_SLCR_MIO_PIN_51_L1_SEL_MASK | IOU_SLCR_MIO_PIN_51_L2_SEL_MASK | IOU_SLCR_MIO_PIN_51_L3_SEL_MASK |  0 );
13627
13628                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT
13629                         | 0x00000000U << IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT
13630                         | 0x00000002U << IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT
13631                         | 0x00000000U << IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT
13632                         |  0 ) & RegMask); */
13633                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_51_OFFSET ,0x000000FEU ,0x00000010U);
13634         /*############################################################################################################################ */
13635
13636                 /*Register : MIO_PIN_52 @ 0XFF1800D0</p>
13637
13638                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)
13639                 PSU_IOU_SLCR_MIO_PIN_52_L0_SEL                                                  0
13640
13641                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)
13642                 PSU_IOU_SLCR_MIO_PIN_52_L1_SEL                                                  1
13643
13644                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13645                 PSU_IOU_SLCR_MIO_PIN_52_L2_SEL                                                  0
13646
13647                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can
13648                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
13649                 ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
13650                 ) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
13651                 lk- (Trace Port Clock)
13652                 PSU_IOU_SLCR_MIO_PIN_52_L3_SEL                                                  0
13653
13654                 Configures MIO Pin 52 peripheral interface mapping
13655                 (OFFSET, MASK, VALUE)      (0XFF1800D0, 0x000000FEU ,0x00000004U)
13656                 RegMask = (IOU_SLCR_MIO_PIN_52_L0_SEL_MASK | IOU_SLCR_MIO_PIN_52_L1_SEL_MASK | IOU_SLCR_MIO_PIN_52_L2_SEL_MASK | IOU_SLCR_MIO_PIN_52_L3_SEL_MASK |  0 );
13657
13658                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT
13659                         | 0x00000001U << IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT
13660                         | 0x00000000U << IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT
13661                         | 0x00000000U << IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT
13662                         |  0 ) & RegMask); */
13663                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_52_OFFSET ,0x000000FEU ,0x00000004U);
13664         /*############################################################################################################################ */
13665
13666                 /*Register : MIO_PIN_53 @ 0XFF1800D4</p>
13667
13668                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)
13669                 PSU_IOU_SLCR_MIO_PIN_53_L0_SEL                                                  0
13670
13671                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)
13672                 PSU_IOU_SLCR_MIO_PIN_53_L1_SEL                                                  1
13673
13674                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13675                 PSU_IOU_SLCR_MIO_PIN_53_L2_SEL                                                  0
13676
13677                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can
13678                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
13679                  3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o
13680                 t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
13681                 Signal)
13682                 PSU_IOU_SLCR_MIO_PIN_53_L3_SEL                                                  0
13683
13684                 Configures MIO Pin 53 peripheral interface mapping
13685                 (OFFSET, MASK, VALUE)      (0XFF1800D4, 0x000000FEU ,0x00000004U)
13686                 RegMask = (IOU_SLCR_MIO_PIN_53_L0_SEL_MASK | IOU_SLCR_MIO_PIN_53_L1_SEL_MASK | IOU_SLCR_MIO_PIN_53_L2_SEL_MASK | IOU_SLCR_MIO_PIN_53_L3_SEL_MASK |  0 );
13687
13688                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT
13689                         | 0x00000001U << IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT
13690                         | 0x00000000U << IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT
13691                         | 0x00000000U << IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT
13692                         |  0 ) & RegMask); */
13693                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_53_OFFSET ,0x000000FEU ,0x00000004U);
13694         /*############################################################################################################################ */
13695
13696                 /*Register : MIO_PIN_54 @ 0XFF1800D8</p>
13697
13698                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)
13699                 PSU_IOU_SLCR_MIO_PIN_54_L0_SEL                                                  0
13700
13701                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13702                 ata[2]- (ULPI data bus)
13703                 PSU_IOU_SLCR_MIO_PIN_54_L1_SEL                                                  1
13704
13705                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13706                 PSU_IOU_SLCR_MIO_PIN_54_L2_SEL                                                  0
13707
13708                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can
13709                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
13710                  3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in
13711                  (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
13712                 PSU_IOU_SLCR_MIO_PIN_54_L3_SEL                                                  0
13713
13714                 Configures MIO Pin 54 peripheral interface mapping
13715                 (OFFSET, MASK, VALUE)      (0XFF1800D8, 0x000000FEU ,0x00000004U)
13716                 RegMask = (IOU_SLCR_MIO_PIN_54_L0_SEL_MASK | IOU_SLCR_MIO_PIN_54_L1_SEL_MASK | IOU_SLCR_MIO_PIN_54_L2_SEL_MASK | IOU_SLCR_MIO_PIN_54_L3_SEL_MASK |  0 );
13717
13718                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT
13719                         | 0x00000001U << IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT
13720                         | 0x00000000U << IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT
13721                         | 0x00000000U << IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT
13722                         |  0 ) & RegMask); */
13723                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_54_OFFSET ,0x000000FEU ,0x00000004U);
13724         /*############################################################################################################################ */
13725
13726                 /*Register : MIO_PIN_55 @ 0XFF1800DC</p>
13727
13728                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)
13729                 PSU_IOU_SLCR_MIO_PIN_55_L0_SEL                                                  0
13730
13731                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)
13732                 PSU_IOU_SLCR_MIO_PIN_55_L1_SEL                                                  1
13733
13734                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13735                 PSU_IOU_SLCR_MIO_PIN_55_L2_SEL                                                  0
13736
13737                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can
13738                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
13739                 ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
13740                 - (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
13741                 output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
13742                 PSU_IOU_SLCR_MIO_PIN_55_L3_SEL                                                  0
13743
13744                 Configures MIO Pin 55 peripheral interface mapping
13745                 (OFFSET, MASK, VALUE)      (0XFF1800DC, 0x000000FEU ,0x00000004U)
13746                 RegMask = (IOU_SLCR_MIO_PIN_55_L0_SEL_MASK | IOU_SLCR_MIO_PIN_55_L1_SEL_MASK | IOU_SLCR_MIO_PIN_55_L2_SEL_MASK | IOU_SLCR_MIO_PIN_55_L3_SEL_MASK |  0 );
13747
13748                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT
13749                         | 0x00000001U << IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT
13750                         | 0x00000000U << IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT
13751                         | 0x00000000U << IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT
13752                         |  0 ) & RegMask); */
13753                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_55_OFFSET ,0x000000FEU ,0x00000004U);
13754         /*############################################################################################################################ */
13755
13756                 /*Register : MIO_PIN_56 @ 0XFF1800E0</p>
13757
13758                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)
13759                 PSU_IOU_SLCR_MIO_PIN_56_L0_SEL                                                  0
13760
13761                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13762                 ata[0]- (ULPI data bus)
13763                 PSU_IOU_SLCR_MIO_PIN_56_L1_SEL                                                  1
13764
13765                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13766                 PSU_IOU_SLCR_MIO_PIN_56_L2_SEL                                                  0
13767
13768                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can
13769                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
13770                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
13771                 - (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
13772                 utput, tracedq[2]- (Trace Port Databus)
13773                 PSU_IOU_SLCR_MIO_PIN_56_L3_SEL                                                  0
13774
13775                 Configures MIO Pin 56 peripheral interface mapping
13776                 (OFFSET, MASK, VALUE)      (0XFF1800E0, 0x000000FEU ,0x00000004U)
13777                 RegMask = (IOU_SLCR_MIO_PIN_56_L0_SEL_MASK | IOU_SLCR_MIO_PIN_56_L1_SEL_MASK | IOU_SLCR_MIO_PIN_56_L2_SEL_MASK | IOU_SLCR_MIO_PIN_56_L3_SEL_MASK |  0 );
13778
13779                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT
13780                         | 0x00000001U << IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT
13781                         | 0x00000000U << IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT
13782                         | 0x00000000U << IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT
13783                         |  0 ) & RegMask); */
13784                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_56_OFFSET ,0x000000FEU ,0x00000004U);
13785         /*############################################################################################################################ */
13786
13787                 /*Register : MIO_PIN_57 @ 0XFF1800E4</p>
13788
13789                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)
13790                 PSU_IOU_SLCR_MIO_PIN_57_L0_SEL                                                  0
13791
13792                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13793                 ata[1]- (ULPI data bus)
13794                 PSU_IOU_SLCR_MIO_PIN_57_L1_SEL                                                  1
13795
13796                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13797                 PSU_IOU_SLCR_MIO_PIN_57_L2_SEL                                                  0
13798
13799                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can
13800                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
13801                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
13802                 si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
13803                  trace, Output, tracedq[3]- (Trace Port Databus)
13804                 PSU_IOU_SLCR_MIO_PIN_57_L3_SEL                                                  0
13805
13806                 Configures MIO Pin 57 peripheral interface mapping
13807                 (OFFSET, MASK, VALUE)      (0XFF1800E4, 0x000000FEU ,0x00000004U)
13808                 RegMask = (IOU_SLCR_MIO_PIN_57_L0_SEL_MASK | IOU_SLCR_MIO_PIN_57_L1_SEL_MASK | IOU_SLCR_MIO_PIN_57_L2_SEL_MASK | IOU_SLCR_MIO_PIN_57_L3_SEL_MASK |  0 );
13809
13810                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT
13811                         | 0x00000001U << IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT
13812                         | 0x00000000U << IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT
13813                         | 0x00000000U << IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT
13814                         |  0 ) & RegMask); */
13815                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_57_OFFSET ,0x000000FEU ,0x00000004U);
13816         /*############################################################################################################################ */
13817
13818                 /*Register : MIO_PIN_58 @ 0XFF1800E8</p>
13819
13820                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)
13821                 PSU_IOU_SLCR_MIO_PIN_58_L0_SEL                                                  0
13822
13823                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)
13824                 PSU_IOU_SLCR_MIO_PIN_58_L1_SEL                                                  1
13825
13826                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13827                 PSU_IOU_SLCR_MIO_PIN_58_L2_SEL                                                  0
13828
13829                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can
13830                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
13831                  3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock
13832                  5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]-
13833                 Trace Port Databus)
13834                 PSU_IOU_SLCR_MIO_PIN_58_L3_SEL                                                  0
13835
13836                 Configures MIO Pin 58 peripheral interface mapping
13837                 (OFFSET, MASK, VALUE)      (0XFF1800E8, 0x000000FEU ,0x00000004U)
13838                 RegMask = (IOU_SLCR_MIO_PIN_58_L0_SEL_MASK | IOU_SLCR_MIO_PIN_58_L1_SEL_MASK | IOU_SLCR_MIO_PIN_58_L2_SEL_MASK | IOU_SLCR_MIO_PIN_58_L3_SEL_MASK |  0 );
13839
13840                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT
13841                         | 0x00000001U << IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT
13842                         | 0x00000000U << IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT
13843                         | 0x00000000U << IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT
13844                         |  0 ) & RegMask); */
13845                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_58_OFFSET ,0x000000FEU ,0x00000004U);
13846         /*############################################################################################################################ */
13847
13848                 /*Register : MIO_PIN_59 @ 0XFF1800EC</p>
13849
13850                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)
13851                 PSU_IOU_SLCR_MIO_PIN_59_L0_SEL                                                  0
13852
13853                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13854                 ata[3]- (ULPI data bus)
13855                 PSU_IOU_SLCR_MIO_PIN_59_L1_SEL                                                  1
13856
13857                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13858                 PSU_IOU_SLCR_MIO_PIN_59_L2_SEL                                                  0
13859
13860                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can
13861                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
13862                 ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
13863                 ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port
13864                 atabus)
13865                 PSU_IOU_SLCR_MIO_PIN_59_L3_SEL                                                  0
13866
13867                 Configures MIO Pin 59 peripheral interface mapping
13868                 (OFFSET, MASK, VALUE)      (0XFF1800EC, 0x000000FEU ,0x00000004U)
13869                 RegMask = (IOU_SLCR_MIO_PIN_59_L0_SEL_MASK | IOU_SLCR_MIO_PIN_59_L1_SEL_MASK | IOU_SLCR_MIO_PIN_59_L2_SEL_MASK | IOU_SLCR_MIO_PIN_59_L3_SEL_MASK |  0 );
13870
13871                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT
13872                         | 0x00000001U << IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT
13873                         | 0x00000000U << IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT
13874                         | 0x00000000U << IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT
13875                         |  0 ) & RegMask); */
13876                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_59_OFFSET ,0x000000FEU ,0x00000004U);
13877         /*############################################################################################################################ */
13878
13879                 /*Register : MIO_PIN_60 @ 0XFF1800F0</p>
13880
13881                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)
13882                 PSU_IOU_SLCR_MIO_PIN_60_L0_SEL                                                  0
13883
13884                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13885                 ata[4]- (ULPI data bus)
13886                 PSU_IOU_SLCR_MIO_PIN_60_L1_SEL                                                  1
13887
13888                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13889                 PSU_IOU_SLCR_MIO_PIN_60_L2_SEL                                                  0
13890
13891                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can
13892                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
13893                 ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
13894                 - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
13895                 PSU_IOU_SLCR_MIO_PIN_60_L3_SEL                                                  0
13896
13897                 Configures MIO Pin 60 peripheral interface mapping
13898                 (OFFSET, MASK, VALUE)      (0XFF1800F0, 0x000000FEU ,0x00000004U)
13899                 RegMask = (IOU_SLCR_MIO_PIN_60_L0_SEL_MASK | IOU_SLCR_MIO_PIN_60_L1_SEL_MASK | IOU_SLCR_MIO_PIN_60_L2_SEL_MASK | IOU_SLCR_MIO_PIN_60_L3_SEL_MASK |  0 );
13900
13901                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT
13902                         | 0x00000001U << IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT
13903                         | 0x00000000U << IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT
13904                         | 0x00000000U << IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT
13905                         |  0 ) & RegMask); */
13906                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_60_OFFSET ,0x000000FEU ,0x00000004U);
13907         /*############################################################################################################################ */
13908
13909                 /*Register : MIO_PIN_61 @ 0XFF1800F4</p>
13910
13911                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)
13912                 PSU_IOU_SLCR_MIO_PIN_61_L0_SEL                                                  0
13913
13914                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13915                 ata[5]- (ULPI data bus)
13916                 PSU_IOU_SLCR_MIO_PIN_61_L1_SEL                                                  1
13917
13918                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13919                 PSU_IOU_SLCR_MIO_PIN_61_L2_SEL                                                  0
13920
13921                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can
13922                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
13923                  3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]
13924                  (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
13925                 ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
13926                 PSU_IOU_SLCR_MIO_PIN_61_L3_SEL                                                  0
13927
13928                 Configures MIO Pin 61 peripheral interface mapping
13929                 (OFFSET, MASK, VALUE)      (0XFF1800F4, 0x000000FEU ,0x00000004U)
13930                 RegMask = (IOU_SLCR_MIO_PIN_61_L0_SEL_MASK | IOU_SLCR_MIO_PIN_61_L1_SEL_MASK | IOU_SLCR_MIO_PIN_61_L2_SEL_MASK | IOU_SLCR_MIO_PIN_61_L3_SEL_MASK |  0 );
13931
13932                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT
13933                         | 0x00000001U << IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT
13934                         | 0x00000000U << IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT
13935                         | 0x00000000U << IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT
13936                         |  0 ) & RegMask); */
13937                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_61_OFFSET ,0x000000FEU ,0x00000004U);
13938         /*############################################################################################################################ */
13939
13940                 /*Register : MIO_PIN_62 @ 0XFF1800F8</p>
13941
13942                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)
13943                 PSU_IOU_SLCR_MIO_PIN_62_L0_SEL                                                  0
13944
13945                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13946                 ata[6]- (ULPI data bus)
13947                 PSU_IOU_SLCR_MIO_PIN_62_L1_SEL                                                  1
13948
13949                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13950                 PSU_IOU_SLCR_MIO_PIN_62_L2_SEL                                                  0
13951
13952                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c
13953                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
13954                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
13955                 o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
13956                 t, tracedq[8]- (Trace Port Databus)
13957                 PSU_IOU_SLCR_MIO_PIN_62_L3_SEL                                                  0
13958
13959                 Configures MIO Pin 62 peripheral interface mapping
13960                 (OFFSET, MASK, VALUE)      (0XFF1800F8, 0x000000FEU ,0x00000004U)
13961                 RegMask = (IOU_SLCR_MIO_PIN_62_L0_SEL_MASK | IOU_SLCR_MIO_PIN_62_L1_SEL_MASK | IOU_SLCR_MIO_PIN_62_L2_SEL_MASK | IOU_SLCR_MIO_PIN_62_L3_SEL_MASK |  0 );
13962
13963                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT
13964                         | 0x00000001U << IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT
13965                         | 0x00000000U << IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT
13966                         | 0x00000000U << IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT
13967                         |  0 ) & RegMask); */
13968                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_62_OFFSET ,0x000000FEU ,0x00000004U);
13969         /*############################################################################################################################ */
13970
13971                 /*Register : MIO_PIN_63 @ 0XFF1800FC</p>
13972
13973                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )
13974                 PSU_IOU_SLCR_MIO_PIN_63_L0_SEL                                                  0
13975
13976                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13977                 ata[7]- (ULPI data bus)
13978                 PSU_IOU_SLCR_MIO_PIN_63_L1_SEL                                                  1
13979
13980                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13981                 PSU_IOU_SLCR_MIO_PIN_63_L2_SEL                                                  0
13982
13983                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c
13984                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
13985                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
13986                 i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
13987                 tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
13988                 PSU_IOU_SLCR_MIO_PIN_63_L3_SEL                                                  0
13989
13990                 Configures MIO Pin 63 peripheral interface mapping
13991                 (OFFSET, MASK, VALUE)      (0XFF1800FC, 0x000000FEU ,0x00000004U)
13992                 RegMask = (IOU_SLCR_MIO_PIN_63_L0_SEL_MASK | IOU_SLCR_MIO_PIN_63_L1_SEL_MASK | IOU_SLCR_MIO_PIN_63_L2_SEL_MASK | IOU_SLCR_MIO_PIN_63_L3_SEL_MASK |  0 );
13993
13994                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT
13995                         | 0x00000001U << IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT
13996                         | 0x00000000U << IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT
13997                         | 0x00000000U << IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT
13998                         |  0 ) & RegMask); */
13999                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_63_OFFSET ,0x000000FEU ,0x00000004U);
14000         /*############################################################################################################################ */
14001
14002                 /*Register : MIO_PIN_64 @ 0XFF180100</p>
14003
14004                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)
14005                 PSU_IOU_SLCR_MIO_PIN_64_L0_SEL                                                  1
14006
14007                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)
14008                 PSU_IOU_SLCR_MIO_PIN_64_L1_SEL                                                  0
14009
14010                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
14011                 PSU_IOU_SLCR_MIO_PIN_64_L2_SEL                                                  0
14012
14013                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c
14014                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
14015                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s
14016                 i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
14017                  trace, Output, tracedq[10]- (Trace Port Databus)
14018                 PSU_IOU_SLCR_MIO_PIN_64_L3_SEL                                                  0
14019
14020                 Configures MIO Pin 64 peripheral interface mapping
14021                 (OFFSET, MASK, VALUE)      (0XFF180100, 0x000000FEU ,0x00000002U)
14022                 RegMask = (IOU_SLCR_MIO_PIN_64_L0_SEL_MASK | IOU_SLCR_MIO_PIN_64_L1_SEL_MASK | IOU_SLCR_MIO_PIN_64_L2_SEL_MASK | IOU_SLCR_MIO_PIN_64_L3_SEL_MASK |  0 );
14023
14024                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT
14025                         | 0x00000000U << IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT
14026                         | 0x00000000U << IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT
14027                         | 0x00000000U << IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT
14028                         |  0 ) & RegMask); */
14029                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_64_OFFSET ,0x000000FEU ,0x00000002U);
14030         /*############################################################################################################################ */
14031
14032                 /*Register : MIO_PIN_65 @ 0XFF180104</p>
14033
14034                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)
14035                 PSU_IOU_SLCR_MIO_PIN_65_L0_SEL                                                  1
14036
14037                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)
14038                 PSU_IOU_SLCR_MIO_PIN_65_L1_SEL                                                  0
14039
14040                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used
14041                 PSU_IOU_SLCR_MIO_PIN_65_L2_SEL                                                  0
14042
14043                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c
14044                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
14045                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5=
14046                 ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac
14047                 dq[11]- (Trace Port Databus)
14048                 PSU_IOU_SLCR_MIO_PIN_65_L3_SEL                                                  0
14049
14050                 Configures MIO Pin 65 peripheral interface mapping
14051                 (OFFSET, MASK, VALUE)      (0XFF180104, 0x000000FEU ,0x00000002U)
14052                 RegMask = (IOU_SLCR_MIO_PIN_65_L0_SEL_MASK | IOU_SLCR_MIO_PIN_65_L1_SEL_MASK | IOU_SLCR_MIO_PIN_65_L2_SEL_MASK | IOU_SLCR_MIO_PIN_65_L3_SEL_MASK |  0 );
14053
14054                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT
14055                         | 0x00000000U << IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT
14056                         | 0x00000000U << IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT
14057                         | 0x00000000U << IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT
14058                         |  0 ) & RegMask); */
14059                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_65_OFFSET ,0x000000FEU ,0x00000002U);
14060         /*############################################################################################################################ */
14061
14062                 /*Register : MIO_PIN_66 @ 0XFF180108</p>
14063
14064                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)
14065                 PSU_IOU_SLCR_MIO_PIN_66_L0_SEL                                                  1
14066
14067                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
14068                 ata[2]- (ULPI data bus)
14069                 PSU_IOU_SLCR_MIO_PIN_66_L1_SEL                                                  0
14070
14071                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
14072                  Indicator) 2= Not Used 3= Not Used
14073                 PSU_IOU_SLCR_MIO_PIN_66_L2_SEL                                                  0
14074
14075                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c
14076                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
14077                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt
14078                 2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
14079                 Port Databus)
14080                 PSU_IOU_SLCR_MIO_PIN_66_L3_SEL                                                  0
14081
14082                 Configures MIO Pin 66 peripheral interface mapping
14083                 (OFFSET, MASK, VALUE)      (0XFF180108, 0x000000FEU ,0x00000002U)
14084                 RegMask = (IOU_SLCR_MIO_PIN_66_L0_SEL_MASK | IOU_SLCR_MIO_PIN_66_L1_SEL_MASK | IOU_SLCR_MIO_PIN_66_L2_SEL_MASK | IOU_SLCR_MIO_PIN_66_L3_SEL_MASK |  0 );
14085
14086                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT
14087                         | 0x00000000U << IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT
14088                         | 0x00000000U << IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT
14089                         | 0x00000000U << IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT
14090                         |  0 ) & RegMask); */
14091                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_66_OFFSET ,0x000000FEU ,0x00000002U);
14092         /*############################################################################################################################ */
14093
14094                 /*Register : MIO_PIN_67 @ 0XFF18010C</p>
14095
14096                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)
14097                 PSU_IOU_SLCR_MIO_PIN_67_L0_SEL                                                  1
14098
14099                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)
14100                 PSU_IOU_SLCR_MIO_PIN_67_L1_SEL                                                  0
14101
14102                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
14103                 bit Data bus) 2= Not Used 3= Not Used
14104                 PSU_IOU_SLCR_MIO_PIN_67_L2_SEL                                                  0
14105
14106                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c
14107                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
14108                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi
14109                 , Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
14110                  (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
14111                 PSU_IOU_SLCR_MIO_PIN_67_L3_SEL                                                  0
14112
14113                 Configures MIO Pin 67 peripheral interface mapping
14114                 (OFFSET, MASK, VALUE)      (0XFF18010C, 0x000000FEU ,0x00000002U)
14115                 RegMask = (IOU_SLCR_MIO_PIN_67_L0_SEL_MASK | IOU_SLCR_MIO_PIN_67_L1_SEL_MASK | IOU_SLCR_MIO_PIN_67_L2_SEL_MASK | IOU_SLCR_MIO_PIN_67_L3_SEL_MASK |  0 );
14116
14117                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT
14118                         | 0x00000000U << IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT
14119                         | 0x00000000U << IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT
14120                         | 0x00000000U << IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT
14121                         |  0 ) & RegMask); */
14122                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_67_OFFSET ,0x000000FEU ,0x00000002U);
14123         /*############################################################################################################################ */
14124
14125                 /*Register : MIO_PIN_68 @ 0XFF180110</p>
14126
14127                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)
14128                 PSU_IOU_SLCR_MIO_PIN_68_L0_SEL                                                  1
14129
14130                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
14131                 ata[0]- (ULPI data bus)
14132                 PSU_IOU_SLCR_MIO_PIN_68_L1_SEL                                                  0
14133
14134                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
14135                 bit Data bus) 2= Not Used 3= Not Used
14136                 PSU_IOU_SLCR_MIO_PIN_68_L2_SEL                                                  0
14137
14138                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c
14139                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
14140                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
14141                 so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
14142                  Output, tracedq[14]- (Trace Port Databus)
14143                 PSU_IOU_SLCR_MIO_PIN_68_L3_SEL                                                  0
14144
14145                 Configures MIO Pin 68 peripheral interface mapping
14146                 (OFFSET, MASK, VALUE)      (0XFF180110, 0x000000FEU ,0x00000002U)
14147                 RegMask = (IOU_SLCR_MIO_PIN_68_L0_SEL_MASK | IOU_SLCR_MIO_PIN_68_L1_SEL_MASK | IOU_SLCR_MIO_PIN_68_L2_SEL_MASK | IOU_SLCR_MIO_PIN_68_L3_SEL_MASK |  0 );
14148
14149                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT
14150                         | 0x00000000U << IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT
14151                         | 0x00000000U << IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT
14152                         | 0x00000000U << IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT
14153                         |  0 ) & RegMask); */
14154                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_68_OFFSET ,0x000000FEU ,0x00000002U);
14155         /*############################################################################################################################ */
14156
14157                 /*Register : MIO_PIN_69 @ 0XFF180114</p>
14158
14159                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)
14160                 PSU_IOU_SLCR_MIO_PIN_69_L0_SEL                                                  1
14161
14162                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
14163                 ata[1]- (ULPI data bus)
14164                 PSU_IOU_SLCR_MIO_PIN_69_L1_SEL                                                  0
14165
14166                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
14167                 bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
14168                 PSU_IOU_SLCR_MIO_PIN_69_L2_SEL                                                  0
14169
14170                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c
14171                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
14172                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
14173                 0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
14174                 7= trace, Output, tracedq[15]- (Trace Port Databus)
14175                 PSU_IOU_SLCR_MIO_PIN_69_L3_SEL                                                  0
14176
14177                 Configures MIO Pin 69 peripheral interface mapping
14178                 (OFFSET, MASK, VALUE)      (0XFF180114, 0x000000FEU ,0x00000002U)
14179                 RegMask = (IOU_SLCR_MIO_PIN_69_L0_SEL_MASK | IOU_SLCR_MIO_PIN_69_L1_SEL_MASK | IOU_SLCR_MIO_PIN_69_L2_SEL_MASK | IOU_SLCR_MIO_PIN_69_L3_SEL_MASK |  0 );
14180
14181                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT
14182                         | 0x00000000U << IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT
14183                         | 0x00000000U << IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT
14184                         | 0x00000000U << IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT
14185                         |  0 ) & RegMask); */
14186                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_69_OFFSET ,0x000000FEU ,0x00000002U);
14187         /*############################################################################################################################ */
14188
14189                 /*Register : MIO_PIN_70 @ 0XFF180118</p>
14190
14191                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)
14192                 PSU_IOU_SLCR_MIO_PIN_70_L0_SEL                                                  1
14193
14194                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)
14195                 PSU_IOU_SLCR_MIO_PIN_70_L1_SEL                                                  0
14196
14197                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
14198                 bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
14199                 PSU_IOU_SLCR_MIO_PIN_70_L2_SEL                                                  0
14200
14201                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c
14202                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
14203                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
14204                 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not
14205                 sed
14206                 PSU_IOU_SLCR_MIO_PIN_70_L3_SEL                                                  0
14207
14208                 Configures MIO Pin 70 peripheral interface mapping
14209                 (OFFSET, MASK, VALUE)      (0XFF180118, 0x000000FEU ,0x00000002U)
14210                 RegMask = (IOU_SLCR_MIO_PIN_70_L0_SEL_MASK | IOU_SLCR_MIO_PIN_70_L1_SEL_MASK | IOU_SLCR_MIO_PIN_70_L2_SEL_MASK | IOU_SLCR_MIO_PIN_70_L3_SEL_MASK |  0 );
14211
14212                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT
14213                         | 0x00000000U << IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT
14214                         | 0x00000000U << IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT
14215                         | 0x00000000U << IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT
14216                         |  0 ) & RegMask); */
14217                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_70_OFFSET ,0x000000FEU ,0x00000002U);
14218         /*############################################################################################################################ */
14219
14220                 /*Register : MIO_PIN_71 @ 0XFF18011C</p>
14221
14222                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)
14223                 PSU_IOU_SLCR_MIO_PIN_71_L0_SEL                                                  1
14224
14225                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
14226                 ata[3]- (ULPI data bus)
14227                 PSU_IOU_SLCR_MIO_PIN_71_L1_SEL                                                  0
14228
14229                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
14230                 bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
14231                 PSU_IOU_SLCR_MIO_PIN_71_L2_SEL                                                  0
14232
14233                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c
14234                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
14235                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
14236                  ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
14237                 PSU_IOU_SLCR_MIO_PIN_71_L3_SEL                                                  0
14238
14239                 Configures MIO Pin 71 peripheral interface mapping
14240                 (OFFSET, MASK, VALUE)      (0XFF18011C, 0x000000FEU ,0x00000002U)
14241                 RegMask = (IOU_SLCR_MIO_PIN_71_L0_SEL_MASK | IOU_SLCR_MIO_PIN_71_L1_SEL_MASK | IOU_SLCR_MIO_PIN_71_L2_SEL_MASK | IOU_SLCR_MIO_PIN_71_L3_SEL_MASK |  0 );
14242
14243                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT
14244                         | 0x00000000U << IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT
14245                         | 0x00000000U << IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT
14246                         | 0x00000000U << IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT
14247                         |  0 ) & RegMask); */
14248                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_71_OFFSET ,0x000000FEU ,0x00000002U);
14249         /*############################################################################################################################ */
14250
14251                 /*Register : MIO_PIN_72 @ 0XFF180120</p>
14252
14253                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)
14254                 PSU_IOU_SLCR_MIO_PIN_72_L0_SEL                                                  1
14255
14256                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
14257                 ata[4]- (ULPI data bus)
14258                 PSU_IOU_SLCR_MIO_PIN_72_L1_SEL                                                  0
14259
14260                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
14261                 bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
14262                 PSU_IOU_SLCR_MIO_PIN_72_L2_SEL                                                  0
14263
14264                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c
14265                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
14266                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N
14267                 t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
14268                 PSU_IOU_SLCR_MIO_PIN_72_L3_SEL                                                  0
14269
14270                 Configures MIO Pin 72 peripheral interface mapping
14271                 (OFFSET, MASK, VALUE)      (0XFF180120, 0x000000FEU ,0x00000002U)
14272                 RegMask = (IOU_SLCR_MIO_PIN_72_L0_SEL_MASK | IOU_SLCR_MIO_PIN_72_L1_SEL_MASK | IOU_SLCR_MIO_PIN_72_L2_SEL_MASK | IOU_SLCR_MIO_PIN_72_L3_SEL_MASK |  0 );
14273
14274                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT
14275                         | 0x00000000U << IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT
14276                         | 0x00000000U << IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT
14277                         | 0x00000000U << IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT
14278                         |  0 ) & RegMask); */
14279                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_72_OFFSET ,0x000000FEU ,0x00000002U);
14280         /*############################################################################################################################ */
14281
14282                 /*Register : MIO_PIN_73 @ 0XFF180124</p>
14283
14284                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)
14285                 PSU_IOU_SLCR_MIO_PIN_73_L0_SEL                                                  1
14286
14287                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
14288                 ata[5]- (ULPI data bus)
14289                 PSU_IOU_SLCR_MIO_PIN_73_L1_SEL                                                  0
14290
14291                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
14292                 bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
14293                 PSU_IOU_SLCR_MIO_PIN_73_L2_SEL                                                  0
14294
14295                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c
14296                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
14297                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
14298                  Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
14299                 PSU_IOU_SLCR_MIO_PIN_73_L3_SEL                                                  0
14300
14301                 Configures MIO Pin 73 peripheral interface mapping
14302                 (OFFSET, MASK, VALUE)      (0XFF180124, 0x000000FEU ,0x00000002U)
14303                 RegMask = (IOU_SLCR_MIO_PIN_73_L0_SEL_MASK | IOU_SLCR_MIO_PIN_73_L1_SEL_MASK | IOU_SLCR_MIO_PIN_73_L2_SEL_MASK | IOU_SLCR_MIO_PIN_73_L3_SEL_MASK |  0 );
14304
14305                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT
14306                         | 0x00000000U << IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT
14307                         | 0x00000000U << IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT
14308                         | 0x00000000U << IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT
14309                         |  0 ) & RegMask); */
14310                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_73_OFFSET ,0x000000FEU ,0x00000002U);
14311         /*############################################################################################################################ */
14312
14313                 /*Register : MIO_PIN_74 @ 0XFF180128</p>
14314
14315                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)
14316                 PSU_IOU_SLCR_MIO_PIN_74_L0_SEL                                                  1
14317
14318                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
14319                 ata[6]- (ULPI data bus)
14320                 PSU_IOU_SLCR_MIO_PIN_74_L1_SEL                                                  0
14321
14322                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
14323                 bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
14324                 PSU_IOU_SLCR_MIO_PIN_74_L2_SEL                                                  0
14325
14326                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c
14327                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
14328                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
14329                 o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
14330                 PSU_IOU_SLCR_MIO_PIN_74_L3_SEL                                                  0
14331
14332                 Configures MIO Pin 74 peripheral interface mapping
14333                 (OFFSET, MASK, VALUE)      (0XFF180128, 0x000000FEU ,0x00000002U)
14334                 RegMask = (IOU_SLCR_MIO_PIN_74_L0_SEL_MASK | IOU_SLCR_MIO_PIN_74_L1_SEL_MASK | IOU_SLCR_MIO_PIN_74_L2_SEL_MASK | IOU_SLCR_MIO_PIN_74_L3_SEL_MASK |  0 );
14335
14336                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT
14337                         | 0x00000000U << IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT
14338                         | 0x00000000U << IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT
14339                         | 0x00000000U << IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT
14340                         |  0 ) & RegMask); */
14341                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_74_OFFSET ,0x000000FEU ,0x00000002U);
14342         /*############################################################################################################################ */
14343
14344                 /*Register : MIO_PIN_75 @ 0XFF18012C</p>
14345
14346                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )
14347                 PSU_IOU_SLCR_MIO_PIN_75_L0_SEL                                                  1
14348
14349                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
14350                 ata[7]- (ULPI data bus)
14351                 PSU_IOU_SLCR_MIO_PIN_75_L1_SEL                                                  0
14352
14353                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma
14354                 d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
14355                 PSU_IOU_SLCR_MIO_PIN_75_L2_SEL                                                  0
14356
14357                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c
14358                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
14359                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
14360                 i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
14361                 PSU_IOU_SLCR_MIO_PIN_75_L3_SEL                                                  0
14362
14363                 Configures MIO Pin 75 peripheral interface mapping
14364                 (OFFSET, MASK, VALUE)      (0XFF18012C, 0x000000FEU ,0x00000002U)
14365                 RegMask = (IOU_SLCR_MIO_PIN_75_L0_SEL_MASK | IOU_SLCR_MIO_PIN_75_L1_SEL_MASK | IOU_SLCR_MIO_PIN_75_L2_SEL_MASK | IOU_SLCR_MIO_PIN_75_L3_SEL_MASK |  0 );
14366
14367                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT
14368                         | 0x00000000U << IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT
14369                         | 0x00000000U << IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT
14370                         | 0x00000000U << IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT
14371                         |  0 ) & RegMask); */
14372                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_75_OFFSET ,0x000000FEU ,0x00000002U);
14373         /*############################################################################################################################ */
14374
14375                 /*Register : MIO_PIN_76 @ 0XFF180130</p>
14376
14377                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
14378                 PSU_IOU_SLCR_MIO_PIN_76_L0_SEL                                                  0
14379
14380                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
14381                 PSU_IOU_SLCR_MIO_PIN_76_L1_SEL                                                  0
14382
14383                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio
14384                 _clk_out- (SDSDIO clock) 3= Not Used
14385                 PSU_IOU_SLCR_MIO_PIN_76_L2_SEL                                                  0
14386
14387                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c
14388                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
14389                 al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock
14390                  6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used
14391                 PSU_IOU_SLCR_MIO_PIN_76_L3_SEL                                                  6
14392
14393                 Configures MIO Pin 76 peripheral interface mapping
14394                 (OFFSET, MASK, VALUE)      (0XFF180130, 0x000000FEU ,0x000000C0U)
14395                 RegMask = (IOU_SLCR_MIO_PIN_76_L0_SEL_MASK | IOU_SLCR_MIO_PIN_76_L1_SEL_MASK | IOU_SLCR_MIO_PIN_76_L2_SEL_MASK | IOU_SLCR_MIO_PIN_76_L3_SEL_MASK |  0 );
14396
14397                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT
14398                         | 0x00000000U << IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT
14399                         | 0x00000000U << IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT
14400                         | 0x00000006U << IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT
14401                         |  0 ) & RegMask); */
14402                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_76_OFFSET ,0x000000FEU ,0x000000C0U);
14403         /*############################################################################################################################ */
14404
14405                 /*Register : MIO_PIN_77 @ 0XFF180134</p>
14406
14407                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
14408                 PSU_IOU_SLCR_MIO_PIN_77_L0_SEL                                                  0
14409
14410                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
14411                 PSU_IOU_SLCR_MIO_PIN_77_L1_SEL                                                  0
14412
14413                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
14414                 PSU_IOU_SLCR_MIO_PIN_77_L2_SEL                                                  0
14415
14416                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c
14417                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
14418                 l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD
14419                 O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o
14420                 t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used
14421                 PSU_IOU_SLCR_MIO_PIN_77_L3_SEL                                                  6
14422
14423                 Configures MIO Pin 77 peripheral interface mapping
14424                 (OFFSET, MASK, VALUE)      (0XFF180134, 0x000000FEU ,0x000000C0U)
14425                 RegMask = (IOU_SLCR_MIO_PIN_77_L0_SEL_MASK | IOU_SLCR_MIO_PIN_77_L1_SEL_MASK | IOU_SLCR_MIO_PIN_77_L2_SEL_MASK | IOU_SLCR_MIO_PIN_77_L3_SEL_MASK |  0 );
14426
14427                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT
14428                         | 0x00000000U << IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT
14429                         | 0x00000000U << IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT
14430                         | 0x00000006U << IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT
14431                         |  0 ) & RegMask); */
14432                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_77_OFFSET ,0x000000FEU ,0x000000C0U);
14433         /*############################################################################################################################ */
14434
14435                 /*Register : MIO_MST_TRI0 @ 0XFF180204</p>
14436
14437                 Master Tri-state Enable for pin 0, active high
14438                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI                                            0
14439
14440                 Master Tri-state Enable for pin 1, active high
14441                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI                                            0
14442
14443                 Master Tri-state Enable for pin 2, active high
14444                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI                                            0
14445
14446                 Master Tri-state Enable for pin 3, active high
14447                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI                                            0
14448
14449                 Master Tri-state Enable for pin 4, active high
14450                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI                                            0
14451
14452                 Master Tri-state Enable for pin 5, active high
14453                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI                                            0
14454
14455                 Master Tri-state Enable for pin 6, active high
14456                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI                                            0
14457
14458                 Master Tri-state Enable for pin 7, active high
14459                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI                                            0
14460
14461                 Master Tri-state Enable for pin 8, active high
14462                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI                                            0
14463
14464                 Master Tri-state Enable for pin 9, active high
14465                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI                                            0
14466
14467                 Master Tri-state Enable for pin 10, active high
14468                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI                                            0
14469
14470                 Master Tri-state Enable for pin 11, active high
14471                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI                                            0
14472
14473                 Master Tri-state Enable for pin 12, active high
14474                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI                                            0
14475
14476                 Master Tri-state Enable for pin 13, active high
14477                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI                                            0
14478
14479                 Master Tri-state Enable for pin 14, active high
14480                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI                                            0
14481
14482                 Master Tri-state Enable for pin 15, active high
14483                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI                                            0
14484
14485                 Master Tri-state Enable for pin 16, active high
14486                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI                                            0
14487
14488                 Master Tri-state Enable for pin 17, active high
14489                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI                                            0
14490
14491                 Master Tri-state Enable for pin 18, active high
14492                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI                                            1
14493
14494                 Master Tri-state Enable for pin 19, active high
14495                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI                                            0
14496
14497                 Master Tri-state Enable for pin 20, active high
14498                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI                                            0
14499
14500                 Master Tri-state Enable for pin 21, active high
14501                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI                                            1
14502
14503                 Master Tri-state Enable for pin 22, active high
14504                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI                                            0
14505
14506                 Master Tri-state Enable for pin 23, active high
14507                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI                                            0
14508
14509                 Master Tri-state Enable for pin 24, active high
14510                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI                                            0
14511
14512                 Master Tri-state Enable for pin 25, active high
14513                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI                                            1
14514
14515                 Master Tri-state Enable for pin 26, active high
14516                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI                                            0
14517
14518                 Master Tri-state Enable for pin 27, active high
14519                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI                                            0
14520
14521                 Master Tri-state Enable for pin 28, active high
14522                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI                                            1
14523
14524                 Master Tri-state Enable for pin 29, active high
14525                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI                                            0
14526
14527                 Master Tri-state Enable for pin 30, active high
14528                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI                                            1
14529
14530                 Master Tri-state Enable for pin 31, active high
14531                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI                                            0
14532
14533                 MIO pin Tri-state Enables, 31:0
14534                 (OFFSET, MASK, VALUE)      (0XFF180204, 0xFFFFFFFFU ,0x52240000U)
14535                 RegMask = (IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK |  0 );
14536
14537                 RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT
14538                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT
14539                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT
14540                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT
14541                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT
14542                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT
14543                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT
14544                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT
14545                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT
14546                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT
14547                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT
14548                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT
14549                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT
14550                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT
14551                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT
14552                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT
14553                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT
14554                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT
14555                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT
14556                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT
14557                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT
14558                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT
14559                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT
14560                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT
14561                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT
14562                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT
14563                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT
14564                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT
14565                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT
14566                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT
14567                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT
14568                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT
14569                         |  0 ) & RegMask); */
14570                 PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI0_OFFSET ,0xFFFFFFFFU ,0x52240000U);
14571         /*############################################################################################################################ */
14572
14573                 /*Register : MIO_MST_TRI1 @ 0XFF180208</p>
14574
14575                 Master Tri-state Enable for pin 32, active high
14576                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI                                            0
14577
14578                 Master Tri-state Enable for pin 33, active high
14579                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI                                            0
14580
14581                 Master Tri-state Enable for pin 34, active high
14582                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI                                            0
14583
14584                 Master Tri-state Enable for pin 35, active high
14585                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI                                            0
14586
14587                 Master Tri-state Enable for pin 36, active high
14588                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI                                            0
14589
14590                 Master Tri-state Enable for pin 37, active high
14591                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI                                            0
14592
14593                 Master Tri-state Enable for pin 38, active high
14594                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI                                            0
14595
14596                 Master Tri-state Enable for pin 39, active high
14597                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI                                            0
14598
14599                 Master Tri-state Enable for pin 40, active high
14600                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI                                            0
14601
14602                 Master Tri-state Enable for pin 41, active high
14603                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI                                            0
14604
14605                 Master Tri-state Enable for pin 42, active high
14606                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI                                            0
14607
14608                 Master Tri-state Enable for pin 43, active high
14609                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI                                            0
14610
14611                 Master Tri-state Enable for pin 44, active high
14612                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI                                            1
14613
14614                 Master Tri-state Enable for pin 45, active high
14615                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI                                            1
14616
14617                 Master Tri-state Enable for pin 46, active high
14618                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI                                            0
14619
14620                 Master Tri-state Enable for pin 47, active high
14621                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI                                            0
14622
14623                 Master Tri-state Enable for pin 48, active high
14624                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI                                            0
14625
14626                 Master Tri-state Enable for pin 49, active high
14627                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI                                            0
14628
14629                 Master Tri-state Enable for pin 50, active high
14630                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI                                            0
14631
14632                 Master Tri-state Enable for pin 51, active high
14633                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI                                            0
14634
14635                 Master Tri-state Enable for pin 52, active high
14636                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI                                            1
14637
14638                 Master Tri-state Enable for pin 53, active high
14639                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI                                            1
14640
14641                 Master Tri-state Enable for pin 54, active high
14642                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI                                            0
14643
14644                 Master Tri-state Enable for pin 55, active high
14645                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI                                            1
14646
14647                 Master Tri-state Enable for pin 56, active high
14648                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI                                            0
14649
14650                 Master Tri-state Enable for pin 57, active high
14651                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI                                            0
14652
14653                 Master Tri-state Enable for pin 58, active high
14654                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI                                            0
14655
14656                 Master Tri-state Enable for pin 59, active high
14657                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI                                            0
14658
14659                 Master Tri-state Enable for pin 60, active high
14660                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI                                            0
14661
14662                 Master Tri-state Enable for pin 61, active high
14663                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI                                            0
14664
14665                 Master Tri-state Enable for pin 62, active high
14666                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI                                            0
14667
14668                 Master Tri-state Enable for pin 63, active high
14669                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI                                            0
14670
14671                 MIO pin Tri-state Enables, 63:32
14672                 (OFFSET, MASK, VALUE)      (0XFF180208, 0xFFFFFFFFU ,0x00B03000U)
14673                 RegMask = (IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK |  0 );
14674
14675                 RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT
14676                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT
14677                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT
14678                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT
14679                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT
14680                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT
14681                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT
14682                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT
14683                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT
14684                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT
14685                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT
14686                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT
14687                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT
14688                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT
14689                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT
14690                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT
14691                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT
14692                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT
14693                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT
14694                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT
14695                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT
14696                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT
14697                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT
14698                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT
14699                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT
14700                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT
14701                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT
14702                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT
14703                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT
14704                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT
14705                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT
14706                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT
14707                         |  0 ) & RegMask); */
14708                 PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI1_OFFSET ,0xFFFFFFFFU ,0x00B03000U);
14709         /*############################################################################################################################ */
14710
14711                 /*Register : MIO_MST_TRI2 @ 0XFF18020C</p>
14712
14713                 Master Tri-state Enable for pin 64, active high
14714                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI                                            0
14715
14716                 Master Tri-state Enable for pin 65, active high
14717                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI                                            0
14718
14719                 Master Tri-state Enable for pin 66, active high
14720                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI                                            0
14721
14722                 Master Tri-state Enable for pin 67, active high
14723                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI                                            0
14724
14725                 Master Tri-state Enable for pin 68, active high
14726                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI                                            0
14727
14728                 Master Tri-state Enable for pin 69, active high
14729                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI                                            0
14730
14731                 Master Tri-state Enable for pin 70, active high
14732                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI                                            1
14733
14734                 Master Tri-state Enable for pin 71, active high
14735                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI                                            1
14736
14737                 Master Tri-state Enable for pin 72, active high
14738                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI                                            1
14739
14740                 Master Tri-state Enable for pin 73, active high
14741                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI                                            1
14742
14743                 Master Tri-state Enable for pin 74, active high
14744                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI                                            1
14745
14746                 Master Tri-state Enable for pin 75, active high
14747                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI                                            1
14748
14749                 Master Tri-state Enable for pin 76, active high
14750                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI                                            0
14751
14752                 Master Tri-state Enable for pin 77, active high
14753                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI                                            0
14754
14755                 MIO pin Tri-state Enables, 77:64
14756                 (OFFSET, MASK, VALUE)      (0XFF18020C, 0x00003FFFU ,0x00000FC0U)
14757                 RegMask = (IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK |  0 );
14758
14759                 RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT
14760                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT
14761                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT
14762                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT
14763                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT
14764                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT
14765                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT
14766                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT
14767                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT
14768                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT
14769                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT
14770                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT
14771                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT
14772                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT
14773                         |  0 ) & RegMask); */
14774                 PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI2_OFFSET ,0x00003FFFU ,0x00000FC0U);
14775         /*############################################################################################################################ */
14776
14777                 /*Register : bank0_ctrl0 @ 0XFF180138</p>
14778
14779                 Each bit applies to a single IO. Bit 0 for MIO[0].
14780                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0                                           1
14781
14782                 Each bit applies to a single IO. Bit 0 for MIO[0].
14783                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1                                           1
14784
14785                 Each bit applies to a single IO. Bit 0 for MIO[0].
14786                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2                                           1
14787
14788                 Each bit applies to a single IO. Bit 0 for MIO[0].
14789                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3                                           1
14790
14791                 Each bit applies to a single IO. Bit 0 for MIO[0].
14792                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4                                           1
14793
14794                 Each bit applies to a single IO. Bit 0 for MIO[0].
14795                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5                                           1
14796
14797                 Each bit applies to a single IO. Bit 0 for MIO[0].
14798                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6                                           1
14799
14800                 Each bit applies to a single IO. Bit 0 for MIO[0].
14801                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7                                           1
14802
14803                 Each bit applies to a single IO. Bit 0 for MIO[0].
14804                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8                                           1
14805
14806                 Each bit applies to a single IO. Bit 0 for MIO[0].
14807                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9                                           1
14808
14809                 Each bit applies to a single IO. Bit 0 for MIO[0].
14810                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10                                          1
14811
14812                 Each bit applies to a single IO. Bit 0 for MIO[0].
14813                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11                                          1
14814
14815                 Each bit applies to a single IO. Bit 0 for MIO[0].
14816                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12                                          1
14817
14818                 Each bit applies to a single IO. Bit 0 for MIO[0].
14819                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13                                          1
14820
14821                 Each bit applies to a single IO. Bit 0 for MIO[0].
14822                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14                                          1
14823
14824                 Each bit applies to a single IO. Bit 0 for MIO[0].
14825                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15                                          1
14826
14827                 Each bit applies to a single IO. Bit 0 for MIO[0].
14828                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16                                          1
14829
14830                 Each bit applies to a single IO. Bit 0 for MIO[0].
14831                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17                                          1
14832
14833                 Each bit applies to a single IO. Bit 0 for MIO[0].
14834                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18                                          1
14835
14836                 Each bit applies to a single IO. Bit 0 for MIO[0].
14837                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19                                          1
14838
14839                 Each bit applies to a single IO. Bit 0 for MIO[0].
14840                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20                                          1
14841
14842                 Each bit applies to a single IO. Bit 0 for MIO[0].
14843                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21                                          1
14844
14845                 Each bit applies to a single IO. Bit 0 for MIO[0].
14846                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22                                          1
14847
14848                 Each bit applies to a single IO. Bit 0 for MIO[0].
14849                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23                                          1
14850
14851                 Each bit applies to a single IO. Bit 0 for MIO[0].
14852                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24                                          1
14853
14854                 Each bit applies to a single IO. Bit 0 for MIO[0].
14855                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25                                          1
14856
14857                 Drive0 control to MIO Bank 0 - control MIO[25:0]
14858                 (OFFSET, MASK, VALUE)      (0XFF180138, 0x03FFFFFFU ,0x03FFFFFFU)
14859                 RegMask = (IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK |  0 );
14860
14861                 RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT
14862                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT
14863                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT
14864                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT
14865                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT
14866                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT
14867                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT
14868                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT
14869                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT
14870                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT
14871                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT
14872                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT
14873                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT
14874                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT
14875                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT
14876                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT
14877                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT
14878                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT
14879                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT
14880                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT
14881                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT
14882                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT
14883                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT
14884                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT
14885                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT
14886                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT
14887                         |  0 ) & RegMask); */
14888                 PSU_Mask_Write (IOU_SLCR_BANK0_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
14889         /*############################################################################################################################ */
14890
14891                 /*Register : bank0_ctrl1 @ 0XFF18013C</p>
14892
14893                 Each bit applies to a single IO. Bit 0 for MIO[0].
14894                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0                                           1
14895
14896                 Each bit applies to a single IO. Bit 0 for MIO[0].
14897                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1                                           1
14898
14899                 Each bit applies to a single IO. Bit 0 for MIO[0].
14900                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2                                           1
14901
14902                 Each bit applies to a single IO. Bit 0 for MIO[0].
14903                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3                                           1
14904
14905                 Each bit applies to a single IO. Bit 0 for MIO[0].
14906                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4                                           1
14907
14908                 Each bit applies to a single IO. Bit 0 for MIO[0].
14909                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5                                           1
14910
14911                 Each bit applies to a single IO. Bit 0 for MIO[0].
14912                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6                                           1
14913
14914                 Each bit applies to a single IO. Bit 0 for MIO[0].
14915                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7                                           1
14916
14917                 Each bit applies to a single IO. Bit 0 for MIO[0].
14918                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8                                           1
14919
14920                 Each bit applies to a single IO. Bit 0 for MIO[0].
14921                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9                                           1
14922
14923                 Each bit applies to a single IO. Bit 0 for MIO[0].
14924                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10                                          1
14925
14926                 Each bit applies to a single IO. Bit 0 for MIO[0].
14927                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11                                          1
14928
14929                 Each bit applies to a single IO. Bit 0 for MIO[0].
14930                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12                                          1
14931
14932                 Each bit applies to a single IO. Bit 0 for MIO[0].
14933                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13                                          1
14934
14935                 Each bit applies to a single IO. Bit 0 for MIO[0].
14936                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14                                          1
14937
14938                 Each bit applies to a single IO. Bit 0 for MIO[0].
14939                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15                                          1
14940
14941                 Each bit applies to a single IO. Bit 0 for MIO[0].
14942                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16                                          1
14943
14944                 Each bit applies to a single IO. Bit 0 for MIO[0].
14945                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17                                          1
14946
14947                 Each bit applies to a single IO. Bit 0 for MIO[0].
14948                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18                                          1
14949
14950                 Each bit applies to a single IO. Bit 0 for MIO[0].
14951                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19                                          1
14952
14953                 Each bit applies to a single IO. Bit 0 for MIO[0].
14954                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20                                          1
14955
14956                 Each bit applies to a single IO. Bit 0 for MIO[0].
14957                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21                                          1
14958
14959                 Each bit applies to a single IO. Bit 0 for MIO[0].
14960                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22                                          1
14961
14962                 Each bit applies to a single IO. Bit 0 for MIO[0].
14963                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23                                          1
14964
14965                 Each bit applies to a single IO. Bit 0 for MIO[0].
14966                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24                                          1
14967
14968                 Each bit applies to a single IO. Bit 0 for MIO[0].
14969                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25                                          1
14970
14971                 Drive1 control to MIO Bank 0 - control MIO[25:0]
14972                 (OFFSET, MASK, VALUE)      (0XFF18013C, 0x03FFFFFFU ,0x03FFFFFFU)
14973                 RegMask = (IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK |  0 );
14974
14975                 RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT
14976                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT
14977                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT
14978                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT
14979                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT
14980                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT
14981                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT
14982                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT
14983                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT
14984                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT
14985                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT
14986                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT
14987                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT
14988                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT
14989                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT
14990                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT
14991                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT
14992                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT
14993                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT
14994                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT
14995                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT
14996                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT
14997                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT
14998                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT
14999                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT
15000                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT
15001                         |  0 ) & RegMask); */
15002                 PSU_Mask_Write (IOU_SLCR_BANK0_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
15003         /*############################################################################################################################ */
15004
15005                 /*Register : bank0_ctrl3 @ 0XFF180140</p>
15006
15007                 Each bit applies to a single IO. Bit 0 for MIO[0].
15008                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0                                   0
15009
15010                 Each bit applies to a single IO. Bit 0 for MIO[0].
15011                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1                                   0
15012
15013                 Each bit applies to a single IO. Bit 0 for MIO[0].
15014                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2                                   0
15015
15016                 Each bit applies to a single IO. Bit 0 for MIO[0].
15017                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3                                   0
15018
15019                 Each bit applies to a single IO. Bit 0 for MIO[0].
15020                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4                                   0
15021
15022                 Each bit applies to a single IO. Bit 0 for MIO[0].
15023                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5                                   0
15024
15025                 Each bit applies to a single IO. Bit 0 for MIO[0].
15026                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6                                   0
15027
15028                 Each bit applies to a single IO. Bit 0 for MIO[0].
15029                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7                                   0
15030
15031                 Each bit applies to a single IO. Bit 0 for MIO[0].
15032                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8                                   0
15033
15034                 Each bit applies to a single IO. Bit 0 for MIO[0].
15035                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9                                   0
15036
15037                 Each bit applies to a single IO. Bit 0 for MIO[0].
15038                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10                                  0
15039
15040                 Each bit applies to a single IO. Bit 0 for MIO[0].
15041                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11                                  0
15042
15043                 Each bit applies to a single IO. Bit 0 for MIO[0].
15044                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12                                  0
15045
15046                 Each bit applies to a single IO. Bit 0 for MIO[0].
15047                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13                                  0
15048
15049                 Each bit applies to a single IO. Bit 0 for MIO[0].
15050                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14                                  0
15051
15052                 Each bit applies to a single IO. Bit 0 for MIO[0].
15053                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15                                  0
15054
15055                 Each bit applies to a single IO. Bit 0 for MIO[0].
15056                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16                                  0
15057
15058                 Each bit applies to a single IO. Bit 0 for MIO[0].
15059                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17                                  0
15060
15061                 Each bit applies to a single IO. Bit 0 for MIO[0].
15062                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18                                  0
15063
15064                 Each bit applies to a single IO. Bit 0 for MIO[0].
15065                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19                                  0
15066
15067                 Each bit applies to a single IO. Bit 0 for MIO[0].
15068                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20                                  0
15069
15070                 Each bit applies to a single IO. Bit 0 for MIO[0].
15071                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21                                  0
15072
15073                 Each bit applies to a single IO. Bit 0 for MIO[0].
15074                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22                                  0
15075
15076                 Each bit applies to a single IO. Bit 0 for MIO[0].
15077                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23                                  0
15078
15079                 Each bit applies to a single IO. Bit 0 for MIO[0].
15080                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24                                  0
15081
15082                 Each bit applies to a single IO. Bit 0 for MIO[0].
15083                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25                                  0
15084
15085                 Selects either Schmitt or CMOS input for MIO Bank 0 - control MIO[25:0]
15086                 (OFFSET, MASK, VALUE)      (0XFF180140, 0x03FFFFFFU ,0x00000000U)
15087                 RegMask = (IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK |  0 );
15088
15089                 RegVal = ((0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
15090                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
15091                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
15092                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
15093                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
15094                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
15095                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
15096                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
15097                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
15098                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
15099                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
15100                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
15101                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
15102                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
15103                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
15104                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
15105                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
15106                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
15107                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
15108                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
15109                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
15110                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
15111                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
15112                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
15113                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
15114                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
15115                         |  0 ) & RegMask); */
15116                 PSU_Mask_Write (IOU_SLCR_BANK0_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U);
15117         /*############################################################################################################################ */
15118
15119                 /*Register : bank0_ctrl4 @ 0XFF180144</p>
15120
15121                 Each bit applies to a single IO. Bit 0 for MIO[0].
15122                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0                                  1
15123
15124                 Each bit applies to a single IO. Bit 0 for MIO[0].
15125                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1                                  1
15126
15127                 Each bit applies to a single IO. Bit 0 for MIO[0].
15128                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2                                  1
15129
15130                 Each bit applies to a single IO. Bit 0 for MIO[0].
15131                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3                                  1
15132
15133                 Each bit applies to a single IO. Bit 0 for MIO[0].
15134                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4                                  1
15135
15136                 Each bit applies to a single IO. Bit 0 for MIO[0].
15137                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5                                  1
15138
15139                 Each bit applies to a single IO. Bit 0 for MIO[0].
15140                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6                                  1
15141
15142                 Each bit applies to a single IO. Bit 0 for MIO[0].
15143                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7                                  1
15144
15145                 Each bit applies to a single IO. Bit 0 for MIO[0].
15146                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8                                  1
15147
15148                 Each bit applies to a single IO. Bit 0 for MIO[0].
15149                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9                                  1
15150
15151                 Each bit applies to a single IO. Bit 0 for MIO[0].
15152                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10                                 1
15153
15154                 Each bit applies to a single IO. Bit 0 for MIO[0].
15155                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11                                 1
15156
15157                 Each bit applies to a single IO. Bit 0 for MIO[0].
15158                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12                                 1
15159
15160                 Each bit applies to a single IO. Bit 0 for MIO[0].
15161                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13                                 1
15162
15163                 Each bit applies to a single IO. Bit 0 for MIO[0].
15164                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14                                 1
15165
15166                 Each bit applies to a single IO. Bit 0 for MIO[0].
15167                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15                                 1
15168
15169                 Each bit applies to a single IO. Bit 0 for MIO[0].
15170                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16                                 1
15171
15172                 Each bit applies to a single IO. Bit 0 for MIO[0].
15173                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17                                 1
15174
15175                 Each bit applies to a single IO. Bit 0 for MIO[0].
15176                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18                                 1
15177
15178                 Each bit applies to a single IO. Bit 0 for MIO[0].
15179                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19                                 1
15180
15181                 Each bit applies to a single IO. Bit 0 for MIO[0].
15182                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20                                 1
15183
15184                 Each bit applies to a single IO. Bit 0 for MIO[0].
15185                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21                                 1
15186
15187                 Each bit applies to a single IO. Bit 0 for MIO[0].
15188                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22                                 1
15189
15190                 Each bit applies to a single IO. Bit 0 for MIO[0].
15191                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23                                 1
15192
15193                 Each bit applies to a single IO. Bit 0 for MIO[0].
15194                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24                                 1
15195
15196                 Each bit applies to a single IO. Bit 0 for MIO[0].
15197                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25                                 1
15198
15199                 When mio_bank0_pull_enable is set, this selects pull up or pull down for MIO Bank 0 - control MIO[25:0]
15200                 (OFFSET, MASK, VALUE)      (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU)
15201                 RegMask = (IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK |  0 );
15202
15203                 RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
15204                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
15205                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
15206                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
15207                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
15208                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
15209                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
15210                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
15211                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
15212                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
15213                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
15214                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
15215                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
15216                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
15217                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
15218                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
15219                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
15220                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
15221                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
15222                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
15223                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
15224                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
15225                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
15226                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
15227                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
15228                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
15229                         |  0 ) & RegMask); */
15230                 PSU_Mask_Write (IOU_SLCR_BANK0_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
15231         /*############################################################################################################################ */
15232
15233                 /*Register : bank0_ctrl5 @ 0XFF180148</p>
15234
15235                 Each bit applies to a single IO. Bit 0 for MIO[0].
15236                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0                                      1
15237
15238                 Each bit applies to a single IO. Bit 0 for MIO[0].
15239                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1                                      1
15240
15241                 Each bit applies to a single IO. Bit 0 for MIO[0].
15242                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2                                      1
15243
15244                 Each bit applies to a single IO. Bit 0 for MIO[0].
15245                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3                                      1
15246
15247                 Each bit applies to a single IO. Bit 0 for MIO[0].
15248                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4                                      1
15249
15250                 Each bit applies to a single IO. Bit 0 for MIO[0].
15251                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5                                      1
15252
15253                 Each bit applies to a single IO. Bit 0 for MIO[0].
15254                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6                                      1
15255
15256                 Each bit applies to a single IO. Bit 0 for MIO[0].
15257                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7                                      1
15258
15259                 Each bit applies to a single IO. Bit 0 for MIO[0].
15260                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8                                      1
15261
15262                 Each bit applies to a single IO. Bit 0 for MIO[0].
15263                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9                                      1
15264
15265                 Each bit applies to a single IO. Bit 0 for MIO[0].
15266                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10                                     1
15267
15268                 Each bit applies to a single IO. Bit 0 for MIO[0].
15269                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11                                     1
15270
15271                 Each bit applies to a single IO. Bit 0 for MIO[0].
15272                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12                                     1
15273
15274                 Each bit applies to a single IO. Bit 0 for MIO[0].
15275                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13                                     1
15276
15277                 Each bit applies to a single IO. Bit 0 for MIO[0].
15278                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14                                     1
15279
15280                 Each bit applies to a single IO. Bit 0 for MIO[0].
15281                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15                                     1
15282
15283                 Each bit applies to a single IO. Bit 0 for MIO[0].
15284                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16                                     1
15285
15286                 Each bit applies to a single IO. Bit 0 for MIO[0].
15287                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17                                     1
15288
15289                 Each bit applies to a single IO. Bit 0 for MIO[0].
15290                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18                                     1
15291
15292                 Each bit applies to a single IO. Bit 0 for MIO[0].
15293                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19                                     1
15294
15295                 Each bit applies to a single IO. Bit 0 for MIO[0].
15296                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20                                     1
15297
15298                 Each bit applies to a single IO. Bit 0 for MIO[0].
15299                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21                                     1
15300
15301                 Each bit applies to a single IO. Bit 0 for MIO[0].
15302                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22                                     1
15303
15304                 Each bit applies to a single IO. Bit 0 for MIO[0].
15305                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23                                     1
15306
15307                 Each bit applies to a single IO. Bit 0 for MIO[0].
15308                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24                                     1
15309
15310                 Each bit applies to a single IO. Bit 0 for MIO[0].
15311                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25                                     1
15312
15313                 When set, this enables mio_bank0_pullupdown to selects pull up or pull down for MIO Bank 0 - control MIO[25:0]
15314                 (OFFSET, MASK, VALUE)      (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU)
15315                 RegMask = (IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK |  0 );
15316
15317                 RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT
15318                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT
15319                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT
15320                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT
15321                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT
15322                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT
15323                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT
15324                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT
15325                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT
15326                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT
15327                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT
15328                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT
15329                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT
15330                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT
15331                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT
15332                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT
15333                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT
15334                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT
15335                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT
15336                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT
15337                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT
15338                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT
15339                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT
15340                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT
15341                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT
15342                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT
15343                         |  0 ) & RegMask); */
15344                 PSU_Mask_Write (IOU_SLCR_BANK0_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
15345         /*############################################################################################################################ */
15346
15347                 /*Register : bank0_ctrl6 @ 0XFF18014C</p>
15348
15349                 Each bit applies to a single IO. Bit 0 for MIO[0].
15350                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0                                 0
15351
15352                 Each bit applies to a single IO. Bit 0 for MIO[0].
15353                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1                                 0
15354
15355                 Each bit applies to a single IO. Bit 0 for MIO[0].
15356                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2                                 0
15357
15358                 Each bit applies to a single IO. Bit 0 for MIO[0].
15359                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3                                 0
15360
15361                 Each bit applies to a single IO. Bit 0 for MIO[0].
15362                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4                                 0
15363
15364                 Each bit applies to a single IO. Bit 0 for MIO[0].
15365                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5                                 0
15366
15367                 Each bit applies to a single IO. Bit 0 for MIO[0].
15368                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6                                 0
15369
15370                 Each bit applies to a single IO. Bit 0 for MIO[0].
15371                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7                                 0
15372
15373                 Each bit applies to a single IO. Bit 0 for MIO[0].
15374                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8                                 0
15375
15376                 Each bit applies to a single IO. Bit 0 for MIO[0].
15377                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9                                 0
15378
15379                 Each bit applies to a single IO. Bit 0 for MIO[0].
15380                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10                                0
15381
15382                 Each bit applies to a single IO. Bit 0 for MIO[0].
15383                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11                                0
15384
15385                 Each bit applies to a single IO. Bit 0 for MIO[0].
15386                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12                                0
15387
15388                 Each bit applies to a single IO. Bit 0 for MIO[0].
15389                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13                                0
15390
15391                 Each bit applies to a single IO. Bit 0 for MIO[0].
15392                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14                                0
15393
15394                 Each bit applies to a single IO. Bit 0 for MIO[0].
15395                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15                                0
15396
15397                 Each bit applies to a single IO. Bit 0 for MIO[0].
15398                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16                                0
15399
15400                 Each bit applies to a single IO. Bit 0 for MIO[0].
15401                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17                                0
15402
15403                 Each bit applies to a single IO. Bit 0 for MIO[0].
15404                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18                                0
15405
15406                 Each bit applies to a single IO. Bit 0 for MIO[0].
15407                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19                                0
15408
15409                 Each bit applies to a single IO. Bit 0 for MIO[0].
15410                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20                                0
15411
15412                 Each bit applies to a single IO. Bit 0 for MIO[0].
15413                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21                                0
15414
15415                 Each bit applies to a single IO. Bit 0 for MIO[0].
15416                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22                                0
15417
15418                 Each bit applies to a single IO. Bit 0 for MIO[0].
15419                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23                                0
15420
15421                 Each bit applies to a single IO. Bit 0 for MIO[0].
15422                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24                                0
15423
15424                 Each bit applies to a single IO. Bit 0 for MIO[0].
15425                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25                                0
15426
15427                 Slew rate control to MIO Bank 0 - control MIO[25:0]
15428                 (OFFSET, MASK, VALUE)      (0XFF18014C, 0x03FFFFFFU ,0x00000000U)
15429                 RegMask = (IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK |  0 );
15430
15431                 RegVal = ((0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
15432                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
15433                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
15434                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
15435                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
15436                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
15437                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
15438                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
15439                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
15440                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
15441                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
15442                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
15443                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
15444                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
15445                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
15446                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
15447                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
15448                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
15449                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
15450                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
15451                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
15452                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
15453                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
15454                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
15455                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
15456                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
15457                         |  0 ) & RegMask); */
15458                 PSU_Mask_Write (IOU_SLCR_BANK0_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U);
15459         /*############################################################################################################################ */
15460
15461                 /*Register : bank1_ctrl0 @ 0XFF180154</p>
15462
15463                 Each bit applies to a single IO. Bit 0 for MIO[26].
15464                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0                                           1
15465
15466                 Each bit applies to a single IO. Bit 0 for MIO[26].
15467                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1                                           1
15468
15469                 Each bit applies to a single IO. Bit 0 for MIO[26].
15470                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2                                           1
15471
15472                 Each bit applies to a single IO. Bit 0 for MIO[26].
15473                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3                                           1
15474
15475                 Each bit applies to a single IO. Bit 0 for MIO[26].
15476                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4                                           1
15477
15478                 Each bit applies to a single IO. Bit 0 for MIO[26].
15479                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5                                           1
15480
15481                 Each bit applies to a single IO. Bit 0 for MIO[26].
15482                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6                                           1
15483
15484                 Each bit applies to a single IO. Bit 0 for MIO[26].
15485                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7                                           1
15486
15487                 Each bit applies to a single IO. Bit 0 for MIO[26].
15488                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8                                           1
15489
15490                 Each bit applies to a single IO. Bit 0 for MIO[26].
15491                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9                                           1
15492
15493                 Each bit applies to a single IO. Bit 0 for MIO[26].
15494                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10                                          1
15495
15496                 Each bit applies to a single IO. Bit 0 for MIO[26].
15497                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11                                          1
15498
15499                 Each bit applies to a single IO. Bit 0 for MIO[26].
15500                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12                                          1
15501
15502                 Each bit applies to a single IO. Bit 0 for MIO[26].
15503                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13                                          1
15504
15505                 Each bit applies to a single IO. Bit 0 for MIO[26].
15506                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14                                          1
15507
15508                 Each bit applies to a single IO. Bit 0 for MIO[26].
15509                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15                                          1
15510
15511                 Each bit applies to a single IO. Bit 0 for MIO[26].
15512                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16                                          1
15513
15514                 Each bit applies to a single IO. Bit 0 for MIO[26].
15515                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17                                          1
15516
15517                 Each bit applies to a single IO. Bit 0 for MIO[26].
15518                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18                                          1
15519
15520                 Each bit applies to a single IO. Bit 0 for MIO[26].
15521                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19                                          1
15522
15523                 Each bit applies to a single IO. Bit 0 for MIO[26].
15524                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20                                          1
15525
15526                 Each bit applies to a single IO. Bit 0 for MIO[26].
15527                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21                                          1
15528
15529                 Each bit applies to a single IO. Bit 0 for MIO[26].
15530                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22                                          1
15531
15532                 Each bit applies to a single IO. Bit 0 for MIO[26].
15533                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23                                          1
15534
15535                 Each bit applies to a single IO. Bit 0 for MIO[26].
15536                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24                                          1
15537
15538                 Each bit applies to a single IO. Bit 0 for MIO[26].
15539                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25                                          1
15540
15541                 Drive0 control to MIO Bank 1 - control MIO[51:26]
15542                 (OFFSET, MASK, VALUE)      (0XFF180154, 0x03FFFFFFU ,0x03FFFFFFU)
15543                 RegMask = (IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK |  0 );
15544
15545                 RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT
15546                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT
15547                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT
15548                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT
15549                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT
15550                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT
15551                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT
15552                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT
15553                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT
15554                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT
15555                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT
15556                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT
15557                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT
15558                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT
15559                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT
15560                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT
15561                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT
15562                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT
15563                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT
15564                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT
15565                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT
15566                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT
15567                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT
15568                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT
15569                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT
15570                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT
15571                         |  0 ) & RegMask); */
15572                 PSU_Mask_Write (IOU_SLCR_BANK1_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
15573         /*############################################################################################################################ */
15574
15575                 /*Register : bank1_ctrl1 @ 0XFF180158</p>
15576
15577                 Each bit applies to a single IO. Bit 0 for MIO[26].
15578                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0                                           1
15579
15580                 Each bit applies to a single IO. Bit 0 for MIO[26].
15581                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1                                           1
15582
15583                 Each bit applies to a single IO. Bit 0 for MIO[26].
15584                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2                                           1
15585
15586                 Each bit applies to a single IO. Bit 0 for MIO[26].
15587                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3                                           1
15588
15589                 Each bit applies to a single IO. Bit 0 for MIO[26].
15590                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4                                           1
15591
15592                 Each bit applies to a single IO. Bit 0 for MIO[26].
15593                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5                                           1
15594
15595                 Each bit applies to a single IO. Bit 0 for MIO[26].
15596                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6                                           1
15597
15598                 Each bit applies to a single IO. Bit 0 for MIO[26].
15599                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7                                           1
15600
15601                 Each bit applies to a single IO. Bit 0 for MIO[26].
15602                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8                                           1
15603
15604                 Each bit applies to a single IO. Bit 0 for MIO[26].
15605                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9                                           1
15606
15607                 Each bit applies to a single IO. Bit 0 for MIO[26].
15608                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10                                          1
15609
15610                 Each bit applies to a single IO. Bit 0 for MIO[26].
15611                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11                                          1
15612
15613                 Each bit applies to a single IO. Bit 0 for MIO[26].
15614                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12                                          1
15615
15616                 Each bit applies to a single IO. Bit 0 for MIO[26].
15617                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13                                          1
15618
15619                 Each bit applies to a single IO. Bit 0 for MIO[26].
15620                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14                                          1
15621
15622                 Each bit applies to a single IO. Bit 0 for MIO[26].
15623                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15                                          1
15624
15625                 Each bit applies to a single IO. Bit 0 for MIO[26].
15626                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16                                          1
15627
15628                 Each bit applies to a single IO. Bit 0 for MIO[26].
15629                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17                                          1
15630
15631                 Each bit applies to a single IO. Bit 0 for MIO[26].
15632                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18                                          1
15633
15634                 Each bit applies to a single IO. Bit 0 for MIO[26].
15635                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19                                          1
15636
15637                 Each bit applies to a single IO. Bit 0 for MIO[26].
15638                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20                                          1
15639
15640                 Each bit applies to a single IO. Bit 0 for MIO[26].
15641                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21                                          1
15642
15643                 Each bit applies to a single IO. Bit 0 for MIO[26].
15644                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22                                          1
15645
15646                 Each bit applies to a single IO. Bit 0 for MIO[26].
15647                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23                                          1
15648
15649                 Each bit applies to a single IO. Bit 0 for MIO[26].
15650                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24                                          1
15651
15652                 Each bit applies to a single IO. Bit 0 for MIO[26].
15653                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25                                          1
15654
15655                 Drive1 control to MIO Bank 1 - control MIO[51:26]
15656                 (OFFSET, MASK, VALUE)      (0XFF180158, 0x03FFFFFFU ,0x03FFFFFFU)
15657                 RegMask = (IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK |  0 );
15658
15659                 RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT
15660                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT
15661                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT
15662                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT
15663                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT
15664                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT
15665                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT
15666                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT
15667                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT
15668                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT
15669                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT
15670                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT
15671                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT
15672                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT
15673                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT
15674                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT
15675                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT
15676                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT
15677                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT
15678                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT
15679                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT
15680                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT
15681                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT
15682                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT
15683                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT
15684                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT
15685                         |  0 ) & RegMask); */
15686                 PSU_Mask_Write (IOU_SLCR_BANK1_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
15687         /*############################################################################################################################ */
15688
15689                 /*Register : bank1_ctrl3 @ 0XFF18015C</p>
15690
15691                 Each bit applies to a single IO. Bit 0 for MIO[26].
15692                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0                                   0
15693
15694                 Each bit applies to a single IO. Bit 0 for MIO[26].
15695                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1                                   0
15696
15697                 Each bit applies to a single IO. Bit 0 for MIO[26].
15698                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2                                   0
15699
15700                 Each bit applies to a single IO. Bit 0 for MIO[26].
15701                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3                                   0
15702
15703                 Each bit applies to a single IO. Bit 0 for MIO[26].
15704                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4                                   0
15705
15706                 Each bit applies to a single IO. Bit 0 for MIO[26].
15707                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5                                   0
15708
15709                 Each bit applies to a single IO. Bit 0 for MIO[26].
15710                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6                                   0
15711
15712                 Each bit applies to a single IO. Bit 0 for MIO[26].
15713                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7                                   0
15714
15715                 Each bit applies to a single IO. Bit 0 for MIO[26].
15716                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8                                   0
15717
15718                 Each bit applies to a single IO. Bit 0 for MIO[26].
15719                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9                                   0
15720
15721                 Each bit applies to a single IO. Bit 0 for MIO[26].
15722                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10                                  0
15723
15724                 Each bit applies to a single IO. Bit 0 for MIO[26].
15725                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11                                  0
15726
15727                 Each bit applies to a single IO. Bit 0 for MIO[26].
15728                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12                                  0
15729
15730                 Each bit applies to a single IO. Bit 0 for MIO[26].
15731                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13                                  0
15732
15733                 Each bit applies to a single IO. Bit 0 for MIO[26].
15734                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14                                  0
15735
15736                 Each bit applies to a single IO. Bit 0 for MIO[26].
15737                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15                                  0
15738
15739                 Each bit applies to a single IO. Bit 0 for MIO[26].
15740                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16                                  0
15741
15742                 Each bit applies to a single IO. Bit 0 for MIO[26].
15743                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17                                  0
15744
15745                 Each bit applies to a single IO. Bit 0 for MIO[26].
15746                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18                                  0
15747
15748                 Each bit applies to a single IO. Bit 0 for MIO[26].
15749                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19                                  0
15750
15751                 Each bit applies to a single IO. Bit 0 for MIO[26].
15752                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20                                  0
15753
15754                 Each bit applies to a single IO. Bit 0 for MIO[26].
15755                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21                                  0
15756
15757                 Each bit applies to a single IO. Bit 0 for MIO[26].
15758                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22                                  0
15759
15760                 Each bit applies to a single IO. Bit 0 for MIO[26].
15761                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23                                  0
15762
15763                 Each bit applies to a single IO. Bit 0 for MIO[26].
15764                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24                                  0
15765
15766                 Each bit applies to a single IO. Bit 0 for MIO[26].
15767                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25                                  0
15768
15769                 Selects either Schmitt or CMOS input for MIO Bank 1 - control MIO[51:26]
15770                 (OFFSET, MASK, VALUE)      (0XFF18015C, 0x03FFFFFFU ,0x00000000U)
15771                 RegMask = (IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK |  0 );
15772
15773                 RegVal = ((0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
15774                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
15775                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
15776                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
15777                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
15778                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
15779                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
15780                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
15781                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
15782                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
15783                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
15784                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
15785                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
15786                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
15787                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
15788                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
15789                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
15790                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
15791                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
15792                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
15793                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
15794                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
15795                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
15796                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
15797                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
15798                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
15799                         |  0 ) & RegMask); */
15800                 PSU_Mask_Write (IOU_SLCR_BANK1_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U);
15801         /*############################################################################################################################ */
15802
15803                 /*Register : bank1_ctrl4 @ 0XFF180160</p>
15804
15805                 Each bit applies to a single IO. Bit 0 for MIO[26].
15806                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0                                  1
15807
15808                 Each bit applies to a single IO. Bit 0 for MIO[26].
15809                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1                                  1
15810
15811                 Each bit applies to a single IO. Bit 0 for MIO[26].
15812                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2                                  1
15813
15814                 Each bit applies to a single IO. Bit 0 for MIO[26].
15815                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3                                  1
15816
15817                 Each bit applies to a single IO. Bit 0 for MIO[26].
15818                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4                                  1
15819
15820                 Each bit applies to a single IO. Bit 0 for MIO[26].
15821                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5                                  1
15822
15823                 Each bit applies to a single IO. Bit 0 for MIO[26].
15824                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6                                  1
15825
15826                 Each bit applies to a single IO. Bit 0 for MIO[26].
15827                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7                                  1
15828
15829                 Each bit applies to a single IO. Bit 0 for MIO[26].
15830                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8                                  1
15831
15832                 Each bit applies to a single IO. Bit 0 for MIO[26].
15833                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9                                  1
15834
15835                 Each bit applies to a single IO. Bit 0 for MIO[26].
15836                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10                                 1
15837
15838                 Each bit applies to a single IO. Bit 0 for MIO[26].
15839                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11                                 1
15840
15841                 Each bit applies to a single IO. Bit 0 for MIO[26].
15842                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12                                 1
15843
15844                 Each bit applies to a single IO. Bit 0 for MIO[26].
15845                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13                                 1
15846
15847                 Each bit applies to a single IO. Bit 0 for MIO[26].
15848                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14                                 1
15849
15850                 Each bit applies to a single IO. Bit 0 for MIO[26].
15851                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15                                 1
15852
15853                 Each bit applies to a single IO. Bit 0 for MIO[26].
15854                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16                                 1
15855
15856                 Each bit applies to a single IO. Bit 0 for MIO[26].
15857                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17                                 1
15858
15859                 Each bit applies to a single IO. Bit 0 for MIO[26].
15860                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18                                 1
15861
15862                 Each bit applies to a single IO. Bit 0 for MIO[26].
15863                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19                                 1
15864
15865                 Each bit applies to a single IO. Bit 0 for MIO[26].
15866                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20                                 1
15867
15868                 Each bit applies to a single IO. Bit 0 for MIO[26].
15869                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21                                 1
15870
15871                 Each bit applies to a single IO. Bit 0 for MIO[26].
15872                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22                                 1
15873
15874                 Each bit applies to a single IO. Bit 0 for MIO[26].
15875                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23                                 1
15876
15877                 Each bit applies to a single IO. Bit 0 for MIO[26].
15878                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24                                 1
15879
15880                 Each bit applies to a single IO. Bit 0 for MIO[26].
15881                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25                                 1
15882
15883                 When mio_bank1_pull_enable is set, this selects pull up or pull down for MIO Bank 1 - control MIO[51:26]
15884                 (OFFSET, MASK, VALUE)      (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU)
15885                 RegMask = (IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK |  0 );
15886
15887                 RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
15888                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
15889                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
15890                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
15891                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
15892                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
15893                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
15894                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
15895                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
15896                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
15897                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
15898                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
15899                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
15900                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
15901                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
15902                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
15903                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
15904                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
15905                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
15906                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
15907                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
15908                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
15909                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
15910                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
15911                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
15912                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
15913                         |  0 ) & RegMask); */
15914                 PSU_Mask_Write (IOU_SLCR_BANK1_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
15915         /*############################################################################################################################ */
15916
15917                 /*Register : bank1_ctrl5 @ 0XFF180164</p>
15918
15919                 Each bit applies to a single IO. Bit 0 for MIO[26].
15920                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0                                      1
15921
15922                 Each bit applies to a single IO. Bit 0 for MIO[26].
15923                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1                                      1
15924
15925                 Each bit applies to a single IO. Bit 0 for MIO[26].
15926                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2                                      1
15927
15928                 Each bit applies to a single IO. Bit 0 for MIO[26].
15929                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3                                      1
15930
15931                 Each bit applies to a single IO. Bit 0 for MIO[26].
15932                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4                                      1
15933
15934                 Each bit applies to a single IO. Bit 0 for MIO[26].
15935                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5                                      1
15936
15937                 Each bit applies to a single IO. Bit 0 for MIO[26].
15938                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6                                      1
15939
15940                 Each bit applies to a single IO. Bit 0 for MIO[26].
15941                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7                                      1
15942
15943                 Each bit applies to a single IO. Bit 0 for MIO[26].
15944                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8                                      1
15945
15946                 Each bit applies to a single IO. Bit 0 for MIO[26].
15947                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9                                      1
15948
15949                 Each bit applies to a single IO. Bit 0 for MIO[26].
15950                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10                                     1
15951
15952                 Each bit applies to a single IO. Bit 0 for MIO[26].
15953                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11                                     1
15954
15955                 Each bit applies to a single IO. Bit 0 for MIO[26].
15956                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12                                     1
15957
15958                 Each bit applies to a single IO. Bit 0 for MIO[26].
15959                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13                                     1
15960
15961                 Each bit applies to a single IO. Bit 0 for MIO[26].
15962                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14                                     1
15963
15964                 Each bit applies to a single IO. Bit 0 for MIO[26].
15965                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15                                     1
15966
15967                 Each bit applies to a single IO. Bit 0 for MIO[26].
15968                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16                                     1
15969
15970                 Each bit applies to a single IO. Bit 0 for MIO[26].
15971                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17                                     1
15972
15973                 Each bit applies to a single IO. Bit 0 for MIO[26].
15974                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18                                     1
15975
15976                 Each bit applies to a single IO. Bit 0 for MIO[26].
15977                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19                                     1
15978
15979                 Each bit applies to a single IO. Bit 0 for MIO[26].
15980                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20                                     1
15981
15982                 Each bit applies to a single IO. Bit 0 for MIO[26].
15983                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21                                     1
15984
15985                 Each bit applies to a single IO. Bit 0 for MIO[26].
15986                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22                                     1
15987
15988                 Each bit applies to a single IO. Bit 0 for MIO[26].
15989                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23                                     1
15990
15991                 Each bit applies to a single IO. Bit 0 for MIO[26].
15992                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24                                     1
15993
15994                 Each bit applies to a single IO. Bit 0 for MIO[26].
15995                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25                                     1
15996
15997                 When set, this enables mio_bank1_pullupdown to selects pull up or pull down for MIO Bank 1 - control MIO[51:26]
15998                 (OFFSET, MASK, VALUE)      (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU)
15999                 RegMask = (IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK |  0 );
16000
16001                 RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT
16002                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT
16003                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT
16004                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT
16005                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT
16006                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT
16007                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT
16008                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT
16009                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT
16010                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT
16011                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT
16012                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT
16013                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT
16014                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT
16015                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT
16016                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT
16017                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT
16018                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT
16019                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT
16020                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT
16021                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT
16022                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT
16023                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT
16024                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT
16025                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT
16026                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT
16027                         |  0 ) & RegMask); */
16028                 PSU_Mask_Write (IOU_SLCR_BANK1_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
16029         /*############################################################################################################################ */
16030
16031                 /*Register : bank1_ctrl6 @ 0XFF180168</p>
16032
16033                 Each bit applies to a single IO. Bit 0 for MIO[26].
16034                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0                                 0
16035
16036                 Each bit applies to a single IO. Bit 0 for MIO[26].
16037                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1                                 0
16038
16039                 Each bit applies to a single IO. Bit 0 for MIO[26].
16040                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2                                 0
16041
16042                 Each bit applies to a single IO. Bit 0 for MIO[26].
16043                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3                                 0
16044
16045                 Each bit applies to a single IO. Bit 0 for MIO[26].
16046                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4                                 0
16047
16048                 Each bit applies to a single IO. Bit 0 for MIO[26].
16049                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5                                 0
16050
16051                 Each bit applies to a single IO. Bit 0 for MIO[26].
16052                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6                                 0
16053
16054                 Each bit applies to a single IO. Bit 0 for MIO[26].
16055                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7                                 0
16056
16057                 Each bit applies to a single IO. Bit 0 for MIO[26].
16058                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8                                 0
16059
16060                 Each bit applies to a single IO. Bit 0 for MIO[26].
16061                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9                                 0
16062
16063                 Each bit applies to a single IO. Bit 0 for MIO[26].
16064                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10                                0
16065
16066                 Each bit applies to a single IO. Bit 0 for MIO[26].
16067                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11                                0
16068
16069                 Each bit applies to a single IO. Bit 0 for MIO[26].
16070                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12                                0
16071
16072                 Each bit applies to a single IO. Bit 0 for MIO[26].
16073                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13                                0
16074
16075                 Each bit applies to a single IO. Bit 0 for MIO[26].
16076                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14                                0
16077
16078                 Each bit applies to a single IO. Bit 0 for MIO[26].
16079                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15                                0
16080
16081                 Each bit applies to a single IO. Bit 0 for MIO[26].
16082                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16                                0
16083
16084                 Each bit applies to a single IO. Bit 0 for MIO[26].
16085                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17                                0
16086
16087                 Each bit applies to a single IO. Bit 0 for MIO[26].
16088                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18                                0
16089
16090                 Each bit applies to a single IO. Bit 0 for MIO[26].
16091                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19                                0
16092
16093                 Each bit applies to a single IO. Bit 0 for MIO[26].
16094                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20                                0
16095
16096                 Each bit applies to a single IO. Bit 0 for MIO[26].
16097                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21                                0
16098
16099                 Each bit applies to a single IO. Bit 0 for MIO[26].
16100                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22                                0
16101
16102                 Each bit applies to a single IO. Bit 0 for MIO[26].
16103                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23                                0
16104
16105                 Each bit applies to a single IO. Bit 0 for MIO[26].
16106                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24                                0
16107
16108                 Each bit applies to a single IO. Bit 0 for MIO[26].
16109                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25                                0
16110
16111                 Slew rate control to MIO Bank 1 - control MIO[51:26]
16112                 (OFFSET, MASK, VALUE)      (0XFF180168, 0x03FFFFFFU ,0x00000000U)
16113                 RegMask = (IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK |  0 );
16114
16115                 RegVal = ((0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
16116                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
16117                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
16118                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
16119                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
16120                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
16121                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
16122                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
16123                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
16124                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
16125                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
16126                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
16127                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
16128                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
16129                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
16130                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
16131                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
16132                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
16133                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
16134                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
16135                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
16136                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
16137                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
16138                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
16139                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
16140                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
16141                         |  0 ) & RegMask); */
16142                 PSU_Mask_Write (IOU_SLCR_BANK1_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U);
16143         /*############################################################################################################################ */
16144
16145                 /*Register : bank2_ctrl0 @ 0XFF180170</p>
16146
16147                 Each bit applies to a single IO. Bit 0 for MIO[52].
16148                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0                                           1
16149
16150                 Each bit applies to a single IO. Bit 0 for MIO[52].
16151                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1                                           1
16152
16153                 Each bit applies to a single IO. Bit 0 for MIO[52].
16154                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2                                           1
16155
16156                 Each bit applies to a single IO. Bit 0 for MIO[52].
16157                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3                                           1
16158
16159                 Each bit applies to a single IO. Bit 0 for MIO[52].
16160                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4                                           1
16161
16162                 Each bit applies to a single IO. Bit 0 for MIO[52].
16163                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5                                           1
16164
16165                 Each bit applies to a single IO. Bit 0 for MIO[52].
16166                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6                                           1
16167
16168                 Each bit applies to a single IO. Bit 0 for MIO[52].
16169                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7                                           1
16170
16171                 Each bit applies to a single IO. Bit 0 for MIO[52].
16172                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8                                           1
16173
16174                 Each bit applies to a single IO. Bit 0 for MIO[52].
16175                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9                                           1
16176
16177                 Each bit applies to a single IO. Bit 0 for MIO[52].
16178                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10                                          1
16179
16180                 Each bit applies to a single IO. Bit 0 for MIO[52].
16181                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11                                          1
16182
16183                 Each bit applies to a single IO. Bit 0 for MIO[52].
16184                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12                                          1
16185
16186                 Each bit applies to a single IO. Bit 0 for MIO[52].
16187                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13                                          1
16188
16189                 Each bit applies to a single IO. Bit 0 for MIO[52].
16190                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14                                          1
16191
16192                 Each bit applies to a single IO. Bit 0 for MIO[52].
16193                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15                                          1
16194
16195                 Each bit applies to a single IO. Bit 0 for MIO[52].
16196                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16                                          1
16197
16198                 Each bit applies to a single IO. Bit 0 for MIO[52].
16199                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17                                          1
16200
16201                 Each bit applies to a single IO. Bit 0 for MIO[52].
16202                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18                                          1
16203
16204                 Each bit applies to a single IO. Bit 0 for MIO[52].
16205                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19                                          1
16206
16207                 Each bit applies to a single IO. Bit 0 for MIO[52].
16208                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20                                          1
16209
16210                 Each bit applies to a single IO. Bit 0 for MIO[52].
16211                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21                                          1
16212
16213                 Each bit applies to a single IO. Bit 0 for MIO[52].
16214                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22                                          1
16215
16216                 Each bit applies to a single IO. Bit 0 for MIO[52].
16217                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23                                          1
16218
16219                 Each bit applies to a single IO. Bit 0 for MIO[52].
16220                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24                                          1
16221
16222                 Each bit applies to a single IO. Bit 0 for MIO[52].
16223                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25                                          1
16224
16225                 Drive0 control to MIO Bank 2 - control MIO[77:52]
16226                 (OFFSET, MASK, VALUE)      (0XFF180170, 0x03FFFFFFU ,0x03FFFFFFU)
16227                 RegMask = (IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK |  0 );
16228
16229                 RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT
16230                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT
16231                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT
16232                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT
16233                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT
16234                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT
16235                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT
16236                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT
16237                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT
16238                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT
16239                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT
16240                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT
16241                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT
16242                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT
16243                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT
16244                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT
16245                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT
16246                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT
16247                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT
16248                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT
16249                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT
16250                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT
16251                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT
16252                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT
16253                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT
16254                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT
16255                         |  0 ) & RegMask); */
16256                 PSU_Mask_Write (IOU_SLCR_BANK2_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
16257         /*############################################################################################################################ */
16258
16259                 /*Register : bank2_ctrl1 @ 0XFF180174</p>
16260
16261                 Each bit applies to a single IO. Bit 0 for MIO[52].
16262                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0                                           1
16263
16264                 Each bit applies to a single IO. Bit 0 for MIO[52].
16265                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1                                           1
16266
16267                 Each bit applies to a single IO. Bit 0 for MIO[52].
16268                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2                                           1
16269
16270                 Each bit applies to a single IO. Bit 0 for MIO[52].
16271                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3                                           1
16272
16273                 Each bit applies to a single IO. Bit 0 for MIO[52].
16274                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4                                           1
16275
16276                 Each bit applies to a single IO. Bit 0 for MIO[52].
16277                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5                                           1
16278
16279                 Each bit applies to a single IO. Bit 0 for MIO[52].
16280                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6                                           1
16281
16282                 Each bit applies to a single IO. Bit 0 for MIO[52].
16283                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7                                           1
16284
16285                 Each bit applies to a single IO. Bit 0 for MIO[52].
16286                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8                                           1
16287
16288                 Each bit applies to a single IO. Bit 0 for MIO[52].
16289                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9                                           1
16290
16291                 Each bit applies to a single IO. Bit 0 for MIO[52].
16292                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10                                          1
16293
16294                 Each bit applies to a single IO. Bit 0 for MIO[52].
16295                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11                                          1
16296
16297                 Each bit applies to a single IO. Bit 0 for MIO[52].
16298                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12                                          1
16299
16300                 Each bit applies to a single IO. Bit 0 for MIO[52].
16301                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13                                          1
16302
16303                 Each bit applies to a single IO. Bit 0 for MIO[52].
16304                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14                                          1
16305
16306                 Each bit applies to a single IO. Bit 0 for MIO[52].
16307                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15                                          1
16308
16309                 Each bit applies to a single IO. Bit 0 for MIO[52].
16310                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16                                          1
16311
16312                 Each bit applies to a single IO. Bit 0 for MIO[52].
16313                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17                                          1
16314
16315                 Each bit applies to a single IO. Bit 0 for MIO[52].
16316                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18                                          1
16317
16318                 Each bit applies to a single IO. Bit 0 for MIO[52].
16319                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19                                          1
16320
16321                 Each bit applies to a single IO. Bit 0 for MIO[52].
16322                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20                                          1
16323
16324                 Each bit applies to a single IO. Bit 0 for MIO[52].
16325                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21                                          1
16326
16327                 Each bit applies to a single IO. Bit 0 for MIO[52].
16328                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22                                          1
16329
16330                 Each bit applies to a single IO. Bit 0 for MIO[52].
16331                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23                                          1
16332
16333                 Each bit applies to a single IO. Bit 0 for MIO[52].
16334                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24                                          1
16335
16336                 Each bit applies to a single IO. Bit 0 for MIO[52].
16337                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25                                          1
16338
16339                 Drive1 control to MIO Bank 2 - control MIO[77:52]
16340                 (OFFSET, MASK, VALUE)      (0XFF180174, 0x03FFFFFFU ,0x03FFFFFFU)
16341                 RegMask = (IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK |  0 );
16342
16343                 RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT
16344                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT
16345                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT
16346                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT
16347                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT
16348                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT
16349                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT
16350                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT
16351                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT
16352                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT
16353                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT
16354                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT
16355                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT
16356                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT
16357                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT
16358                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT
16359                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT
16360                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT
16361                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT
16362                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT
16363                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT
16364                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT
16365                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT
16366                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT
16367                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT
16368                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT
16369                         |  0 ) & RegMask); */
16370                 PSU_Mask_Write (IOU_SLCR_BANK2_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
16371         /*############################################################################################################################ */
16372
16373                 /*Register : bank2_ctrl3 @ 0XFF180178</p>
16374
16375                 Each bit applies to a single IO. Bit 0 for MIO[52].
16376                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0                                   0
16377
16378                 Each bit applies to a single IO. Bit 0 for MIO[52].
16379                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1                                   0
16380
16381                 Each bit applies to a single IO. Bit 0 for MIO[52].
16382                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2                                   0
16383
16384                 Each bit applies to a single IO. Bit 0 for MIO[52].
16385                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3                                   0
16386
16387                 Each bit applies to a single IO. Bit 0 for MIO[52].
16388                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4                                   0
16389
16390                 Each bit applies to a single IO. Bit 0 for MIO[52].
16391                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5                                   0
16392
16393                 Each bit applies to a single IO. Bit 0 for MIO[52].
16394                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6                                   0
16395
16396                 Each bit applies to a single IO. Bit 0 for MIO[52].
16397                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7                                   0
16398
16399                 Each bit applies to a single IO. Bit 0 for MIO[52].
16400                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8                                   0
16401
16402                 Each bit applies to a single IO. Bit 0 for MIO[52].
16403                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9                                   0
16404
16405                 Each bit applies to a single IO. Bit 0 for MIO[52].
16406                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10                                  0
16407
16408                 Each bit applies to a single IO. Bit 0 for MIO[52].
16409                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11                                  0
16410
16411                 Each bit applies to a single IO. Bit 0 for MIO[52].
16412                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12                                  0
16413
16414                 Each bit applies to a single IO. Bit 0 for MIO[52].
16415                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13                                  0
16416
16417                 Each bit applies to a single IO. Bit 0 for MIO[52].
16418                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14                                  0
16419
16420                 Each bit applies to a single IO. Bit 0 for MIO[52].
16421                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15                                  0
16422
16423                 Each bit applies to a single IO. Bit 0 for MIO[52].
16424                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16                                  0
16425
16426                 Each bit applies to a single IO. Bit 0 for MIO[52].
16427                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17                                  0
16428
16429                 Each bit applies to a single IO. Bit 0 for MIO[52].
16430                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18                                  0
16431
16432                 Each bit applies to a single IO. Bit 0 for MIO[52].
16433                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19                                  0
16434
16435                 Each bit applies to a single IO. Bit 0 for MIO[52].
16436                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20                                  0
16437
16438                 Each bit applies to a single IO. Bit 0 for MIO[52].
16439                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21                                  0
16440
16441                 Each bit applies to a single IO. Bit 0 for MIO[52].
16442                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22                                  0
16443
16444                 Each bit applies to a single IO. Bit 0 for MIO[52].
16445                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23                                  0
16446
16447                 Each bit applies to a single IO. Bit 0 for MIO[52].
16448                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24                                  0
16449
16450                 Each bit applies to a single IO. Bit 0 for MIO[52].
16451                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25                                  0
16452
16453                 Selects either Schmitt or CMOS input for MIO Bank 2 - control MIO[77:52]
16454                 (OFFSET, MASK, VALUE)      (0XFF180178, 0x03FFFFFFU ,0x00000000U)
16455                 RegMask = (IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK |  0 );
16456
16457                 RegVal = ((0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
16458                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
16459                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
16460                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
16461                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
16462                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
16463                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
16464                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
16465                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
16466                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
16467                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
16468                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
16469                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
16470                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
16471                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
16472                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
16473                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
16474                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
16475                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
16476                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
16477                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
16478                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
16479                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
16480                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
16481                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
16482                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
16483                         |  0 ) & RegMask); */
16484                 PSU_Mask_Write (IOU_SLCR_BANK2_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U);
16485         /*############################################################################################################################ */
16486
16487                 /*Register : bank2_ctrl4 @ 0XFF18017C</p>
16488
16489                 Each bit applies to a single IO. Bit 0 for MIO[52].
16490                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0                                  1
16491
16492                 Each bit applies to a single IO. Bit 0 for MIO[52].
16493                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1                                  1
16494
16495                 Each bit applies to a single IO. Bit 0 for MIO[52].
16496                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2                                  1
16497
16498                 Each bit applies to a single IO. Bit 0 for MIO[52].
16499                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3                                  1
16500
16501                 Each bit applies to a single IO. Bit 0 for MIO[52].
16502                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4                                  1
16503
16504                 Each bit applies to a single IO. Bit 0 for MIO[52].
16505                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5                                  1
16506
16507                 Each bit applies to a single IO. Bit 0 for MIO[52].
16508                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6                                  1
16509
16510                 Each bit applies to a single IO. Bit 0 for MIO[52].
16511                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7                                  1
16512
16513                 Each bit applies to a single IO. Bit 0 for MIO[52].
16514                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8                                  1
16515
16516                 Each bit applies to a single IO. Bit 0 for MIO[52].
16517                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9                                  1
16518
16519                 Each bit applies to a single IO. Bit 0 for MIO[52].
16520                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10                                 1
16521
16522                 Each bit applies to a single IO. Bit 0 for MIO[52].
16523                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11                                 1
16524
16525                 Each bit applies to a single IO. Bit 0 for MIO[52].
16526                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12                                 1
16527
16528                 Each bit applies to a single IO. Bit 0 for MIO[52].
16529                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13                                 1
16530
16531                 Each bit applies to a single IO. Bit 0 for MIO[52].
16532                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14                                 1
16533
16534                 Each bit applies to a single IO. Bit 0 for MIO[52].
16535                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15                                 1
16536
16537                 Each bit applies to a single IO. Bit 0 for MIO[52].
16538                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16                                 1
16539
16540                 Each bit applies to a single IO. Bit 0 for MIO[52].
16541                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17                                 1
16542
16543                 Each bit applies to a single IO. Bit 0 for MIO[52].
16544                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18                                 1
16545
16546                 Each bit applies to a single IO. Bit 0 for MIO[52].
16547                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19                                 1
16548
16549                 Each bit applies to a single IO. Bit 0 for MIO[52].
16550                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20                                 1
16551
16552                 Each bit applies to a single IO. Bit 0 for MIO[52].
16553                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21                                 1
16554
16555                 Each bit applies to a single IO. Bit 0 for MIO[52].
16556                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22                                 1
16557
16558                 Each bit applies to a single IO. Bit 0 for MIO[52].
16559                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23                                 1
16560
16561                 Each bit applies to a single IO. Bit 0 for MIO[52].
16562                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24                                 1
16563
16564                 Each bit applies to a single IO. Bit 0 for MIO[52].
16565                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25                                 1
16566
16567                 When mio_bank2_pull_enable is set, this selects pull up or pull down for MIO Bank 2 - control MIO[77:52]
16568                 (OFFSET, MASK, VALUE)      (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU)
16569                 RegMask = (IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK |  0 );
16570
16571                 RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
16572                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
16573                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
16574                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
16575                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
16576                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
16577                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
16578                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
16579                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
16580                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
16581                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
16582                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
16583                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
16584                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
16585                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
16586                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
16587                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
16588                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
16589                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
16590                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
16591                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
16592                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
16593                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
16594                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
16595                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
16596                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
16597                         |  0 ) & RegMask); */
16598                 PSU_Mask_Write (IOU_SLCR_BANK2_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
16599         /*############################################################################################################################ */
16600
16601                 /*Register : bank2_ctrl5 @ 0XFF180180</p>
16602
16603                 Each bit applies to a single IO. Bit 0 for MIO[52].
16604                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0                                      1
16605
16606                 Each bit applies to a single IO. Bit 0 for MIO[52].
16607                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1                                      1
16608
16609                 Each bit applies to a single IO. Bit 0 for MIO[52].
16610                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2                                      1
16611
16612                 Each bit applies to a single IO. Bit 0 for MIO[52].
16613                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3                                      1
16614
16615                 Each bit applies to a single IO. Bit 0 for MIO[52].
16616                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4                                      1
16617
16618                 Each bit applies to a single IO. Bit 0 for MIO[52].
16619                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5                                      1
16620
16621                 Each bit applies to a single IO. Bit 0 for MIO[52].
16622                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6                                      1
16623
16624                 Each bit applies to a single IO. Bit 0 for MIO[52].
16625                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7                                      1
16626
16627                 Each bit applies to a single IO. Bit 0 for MIO[52].
16628                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8                                      1
16629
16630                 Each bit applies to a single IO. Bit 0 for MIO[52].
16631                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9                                      1
16632
16633                 Each bit applies to a single IO. Bit 0 for MIO[52].
16634                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10                                     1
16635
16636                 Each bit applies to a single IO. Bit 0 for MIO[52].
16637                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11                                     1
16638
16639                 Each bit applies to a single IO. Bit 0 for MIO[52].
16640                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12                                     1
16641
16642                 Each bit applies to a single IO. Bit 0 for MIO[52].
16643                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13                                     1
16644
16645                 Each bit applies to a single IO. Bit 0 for MIO[52].
16646                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14                                     1
16647
16648                 Each bit applies to a single IO. Bit 0 for MIO[52].
16649                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15                                     1
16650
16651                 Each bit applies to a single IO. Bit 0 for MIO[52].
16652                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16                                     1
16653
16654                 Each bit applies to a single IO. Bit 0 for MIO[52].
16655                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17                                     1
16656
16657                 Each bit applies to a single IO. Bit 0 for MIO[52].
16658                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18                                     1
16659
16660                 Each bit applies to a single IO. Bit 0 for MIO[52].
16661                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19                                     1
16662
16663                 Each bit applies to a single IO. Bit 0 for MIO[52].
16664                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20                                     1
16665
16666                 Each bit applies to a single IO. Bit 0 for MIO[52].
16667                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21                                     1
16668
16669                 Each bit applies to a single IO. Bit 0 for MIO[52].
16670                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22                                     1
16671
16672                 Each bit applies to a single IO. Bit 0 for MIO[52].
16673                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23                                     1
16674
16675                 Each bit applies to a single IO. Bit 0 for MIO[52].
16676                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24                                     1
16677
16678                 Each bit applies to a single IO. Bit 0 for MIO[52].
16679                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25                                     1
16680
16681                 When set, this enables mio_bank2_pullupdown to selects pull up or pull down for MIO Bank 2 - control MIO[77:52]
16682                 (OFFSET, MASK, VALUE)      (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU)
16683                 RegMask = (IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK |  0 );
16684
16685                 RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT
16686                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT
16687                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT
16688                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT
16689                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT
16690                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT
16691                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT
16692                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT
16693                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT
16694                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT
16695                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT
16696                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT
16697                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT
16698                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT
16699                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT
16700                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT
16701                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT
16702                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT
16703                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT
16704                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT
16705                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT
16706                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT
16707                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT
16708                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT
16709                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT
16710                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT
16711                         |  0 ) & RegMask); */
16712                 PSU_Mask_Write (IOU_SLCR_BANK2_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
16713         /*############################################################################################################################ */
16714
16715                 /*Register : bank2_ctrl6 @ 0XFF180184</p>
16716
16717                 Each bit applies to a single IO. Bit 0 for MIO[52].
16718                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0                                 0
16719
16720                 Each bit applies to a single IO. Bit 0 for MIO[52].
16721                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1                                 0
16722
16723                 Each bit applies to a single IO. Bit 0 for MIO[52].
16724                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2                                 0
16725
16726                 Each bit applies to a single IO. Bit 0 for MIO[52].
16727                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3                                 0
16728
16729                 Each bit applies to a single IO. Bit 0 for MIO[52].
16730                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4                                 0
16731
16732                 Each bit applies to a single IO. Bit 0 for MIO[52].
16733                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5                                 0
16734
16735                 Each bit applies to a single IO. Bit 0 for MIO[52].
16736                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6                                 0
16737
16738                 Each bit applies to a single IO. Bit 0 for MIO[52].
16739                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7                                 0
16740
16741                 Each bit applies to a single IO. Bit 0 for MIO[52].
16742                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8                                 0
16743
16744                 Each bit applies to a single IO. Bit 0 for MIO[52].
16745                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9                                 0
16746
16747                 Each bit applies to a single IO. Bit 0 for MIO[52].
16748                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10                                0
16749
16750                 Each bit applies to a single IO. Bit 0 for MIO[52].
16751                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11                                0
16752
16753                 Each bit applies to a single IO. Bit 0 for MIO[52].
16754                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12                                0
16755
16756                 Each bit applies to a single IO. Bit 0 for MIO[52].
16757                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13                                0
16758
16759                 Each bit applies to a single IO. Bit 0 for MIO[52].
16760                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14                                0
16761
16762                 Each bit applies to a single IO. Bit 0 for MIO[52].
16763                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15                                0
16764
16765                 Each bit applies to a single IO. Bit 0 for MIO[52].
16766                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16                                0
16767
16768                 Each bit applies to a single IO. Bit 0 for MIO[52].
16769                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17                                0
16770
16771                 Each bit applies to a single IO. Bit 0 for MIO[52].
16772                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18                                0
16773
16774                 Each bit applies to a single IO. Bit 0 for MIO[52].
16775                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19                                0
16776
16777                 Each bit applies to a single IO. Bit 0 for MIO[52].
16778                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20                                0
16779
16780                 Each bit applies to a single IO. Bit 0 for MIO[52].
16781                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21                                0
16782
16783                 Each bit applies to a single IO. Bit 0 for MIO[52].
16784                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22                                0
16785
16786                 Each bit applies to a single IO. Bit 0 for MIO[52].
16787                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23                                0
16788
16789                 Each bit applies to a single IO. Bit 0 for MIO[52].
16790                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24                                0
16791
16792                 Each bit applies to a single IO. Bit 0 for MIO[52].
16793                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25                                0
16794
16795                 Slew rate control to MIO Bank 2 - control MIO[77:52]
16796                 (OFFSET, MASK, VALUE)      (0XFF180184, 0x03FFFFFFU ,0x00000000U)
16797                 RegMask = (IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK |  0 );
16798
16799                 RegVal = ((0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
16800                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
16801                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
16802                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
16803                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
16804                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
16805                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
16806                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
16807                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
16808                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
16809                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
16810                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
16811                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
16812                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
16813                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
16814                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
16815                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
16816                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
16817                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
16818                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
16819                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
16820                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
16821                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
16822                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
16823                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
16824                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
16825                         |  0 ) & RegMask); */
16826                 PSU_Mask_Write (IOU_SLCR_BANK2_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U);
16827         /*############################################################################################################################ */
16828
16829                 // : LOOPBACK
16830                 /*Register : MIO_LOOPBACK @ 0XFF180200</p>
16831
16832                 I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp
16833                 ts to I2C 0 inputs.
16834                 PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1                                        0
16835
16836                 CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R
16837                 .
16838                 PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1                                        0
16839
16840                 UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1
16841                 outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.
16842                 PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1                                          0
16843
16844                 SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp
16845                 ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.
16846                 PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1                                        0
16847
16848                 Loopback function within MIO
16849                 (OFFSET, MASK, VALUE)      (0XFF180200, 0x0000000FU ,0x00000000U)
16850                 RegMask = (IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK | IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK | IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK | IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK |  0 );
16851
16852                 RegVal = ((0x00000000U << IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT
16853                         | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT
16854                         | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT
16855                         | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT
16856                         |  0 ) & RegMask); */
16857                 PSU_Mask_Write (IOU_SLCR_MIO_LOOPBACK_OFFSET ,0x0000000FU ,0x00000000U);
16858         /*############################################################################################################################ */
16859
16860
16861   return 1;
16862 }
16863 unsigned long psu_peripherals_init_data() {
16864                 // : RESET BLOCKS
16865                 // : TIMESTAMP
16866                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
16867
16868                 Block level reset
16869                 PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET                                        0
16870
16871                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
16872                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00100000U ,0x00000000U)
16873                 RegMask = (CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK |  0 );
16874
16875                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT
16876                         |  0 ) & RegMask); */
16877                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00100000U ,0x00000000U);
16878         /*############################################################################################################################ */
16879
16880                 // : ENET
16881                 /*Register : RST_LPD_IOU0 @ 0XFF5E0230</p>
16882
16883                 GEM 3 reset
16884                 PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET                                             0
16885
16886                 Software controlled reset for the GEMs
16887                 (OFFSET, MASK, VALUE)      (0XFF5E0230, 0x00000008U ,0x00000000U)
16888                 RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK |  0 );
16889
16890                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
16891                         |  0 ) & RegMask); */
16892                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000000U);
16893         /*############################################################################################################################ */
16894
16895                 // : QSPI
16896                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
16897
16898                 Block level reset
16899                 PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET                                             0
16900
16901                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
16902                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000001U ,0x00000000U)
16903                 RegMask = (CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK |  0 );
16904
16905                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT
16906                         |  0 ) & RegMask); */
16907                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000001U ,0x00000000U);
16908         /*############################################################################################################################ */
16909
16910                 // : QSPI TAP DELAY
16911                 /*Register : IOU_TAPDLY_BYPASS @ 0XFF180390</p>
16912
16913                 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypass the Tap delay on the Rx clock signal of LQSPI
16914                 PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX                                         1
16915
16916                 IOU tap delay bypass for the LQSPI and NAND controllers
16917                 (OFFSET, MASK, VALUE)      (0XFF180390, 0x00000004U ,0x00000004U)
16918                 RegMask = (IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK |  0 );
16919
16920                 RegVal = ((0x00000001U << IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT
16921                         |  0 ) & RegMask); */
16922                 PSU_Mask_Write (IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET ,0x00000004U ,0x00000004U);
16923         /*############################################################################################################################ */
16924
16925                 // : NAND
16926                 // : USB
16927                 /*Register : RST_LPD_TOP @ 0XFF5E023C</p>
16928
16929                 USB 0 reset for control registers
16930                 PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET                                          0
16931
16932                 USB 0 sleep circuit reset
16933                 PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET                                         0
16934
16935                 USB 0 reset
16936                 PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET                                          0
16937
16938                 Software control register for the LPD block.
16939                 (OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000540U ,0x00000000U)
16940                 RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK |  0 );
16941
16942                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
16943                         | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
16944                         | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
16945                         |  0 ) & RegMask); */
16946                 PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000540U ,0x00000000U);
16947         /*############################################################################################################################ */
16948
16949                 // : FPD RESET
16950                 /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
16951
16952                 PCIE config reset
16953                 PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET                                          0
16954
16955                 PCIE control block level reset
16956                 PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET                                         0
16957
16958                 PCIE bridge block level reset (AXI interface)
16959                 PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET                                       0
16960
16961                 Display Port block level reset (includes DPDMA)
16962                 PSU_CRF_APB_RST_FPD_TOP_DP_RESET                                                0
16963
16964                 FPD WDT reset
16965                 PSU_CRF_APB_RST_FPD_TOP_SWDT_RESET                                              0
16966
16967                 GDMA block level reset
16968                 PSU_CRF_APB_RST_FPD_TOP_GDMA_RESET                                              0
16969
16970                 Pixel Processor (submodule of GPU) block level reset
16971                 PSU_CRF_APB_RST_FPD_TOP_GPU_PP0_RESET                                           0
16972
16973                 Pixel Processor (submodule of GPU) block level reset
16974                 PSU_CRF_APB_RST_FPD_TOP_GPU_PP1_RESET                                           0
16975
16976                 GPU block level reset
16977                 PSU_CRF_APB_RST_FPD_TOP_GPU_RESET                                               0
16978
16979                 GT block level reset
16980                 PSU_CRF_APB_RST_FPD_TOP_GT_RESET                                                0
16981
16982                 Sata block level reset
16983                 PSU_CRF_APB_RST_FPD_TOP_SATA_RESET                                              0
16984
16985                 FPD Block level software controlled reset
16986                 (OFFSET, MASK, VALUE)      (0XFD1A0100, 0x000F807EU ,0x00000000U)
16987                 RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | CRF_APB_RST_FPD_TOP_DP_RESET_MASK | CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK | CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_RESET_MASK | CRF_APB_RST_FPD_TOP_GT_RESET_MASK | CRF_APB_RST_FPD_TOP_SATA_RESET_MASK |  0 );
16988
16989                 RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
16990                         | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
16991                         | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
16992                         | 0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
16993                         | 0x00000000U << CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT
16994                         | 0x00000000U << CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT
16995                         | 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT
16996                         | 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT
16997                         | 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT
16998                         | 0x00000000U << CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT
16999                         | 0x00000000U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
17000                         |  0 ) & RegMask); */
17001                 PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000F807EU ,0x00000000U);
17002         /*############################################################################################################################ */
17003
17004                 // : SD
17005                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
17006
17007                 Block level reset
17008                 PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET                                            0
17009
17010                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
17011                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000040U ,0x00000000U)
17012                 RegMask = (CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK |  0 );
17013
17014                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT
17015                         |  0 ) & RegMask); */
17016                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000040U ,0x00000000U);
17017         /*############################################################################################################################ */
17018
17019                 /*Register : CTRL_REG_SD @ 0XFF180310</p>
17020
17021                 SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled
17022                 PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL                                           0
17023
17024                 SD eMMC selection
17025                 (OFFSET, MASK, VALUE)      (0XFF180310, 0x00008000U ,0x00000000U)
17026                 RegMask = (IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK |  0 );
17027
17028                 RegVal = ((0x00000000U << IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT
17029                         |  0 ) & RegMask); */
17030                 PSU_Mask_Write (IOU_SLCR_CTRL_REG_SD_OFFSET ,0x00008000U ,0x00000000U);
17031         /*############################################################################################################################ */
17032
17033                 /*Register : SD_CONFIG_REG2 @ 0XFF180320</p>
17034
17035                 Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
17036                 t 11 - Reserved
17037                 PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE                                        0
17038
17039                 1.8V Support 1: 1.8V supported 0: 1.8V not supported support
17040                 PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V                                            0
17041
17042                 3.0V Support 1: 3.0V supported 0: 3.0V not supported support
17043                 PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V                                            0
17044
17045                 3.3V Support 1: 3.3V supported 0: 3.3V not supported support
17046                 PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V                                            1
17047
17048                 SD Config Register 2
17049                 (OFFSET, MASK, VALUE)      (0XFF180320, 0x33800000U ,0x00800000U)
17050                 RegMask = (IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK |  0 );
17051
17052                 RegVal = ((0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT
17053                         | 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT
17054                         | 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT
17055                         | 0x00000001U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT
17056                         |  0 ) & RegMask); */
17057                 PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG2_OFFSET ,0x33800000U ,0x00800000U);
17058         /*############################################################################################################################ */
17059
17060                 // : SD1 BASE CLOCK
17061                 /*Register : SD_CONFIG_REG1 @ 0XFF18031C</p>
17062
17063                 Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.
17064                 PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK                                         0xc7
17065
17066                 SD Config Register 1
17067                 (OFFSET, MASK, VALUE)      (0XFF18031C, 0x7F800000U ,0x63800000U)
17068                 RegMask = (IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK |  0 );
17069
17070                 RegVal = ((0x000000C7U << IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT
17071                         |  0 ) & RegMask); */
17072                 PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG1_OFFSET ,0x7F800000U ,0x63800000U);
17073         /*############################################################################################################################ */
17074
17075                 // : SD1 RETUNER
17076                 /*Register : SD_CONFIG_REG3 @ 0XFF180324</p>
17077
17078                 This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. 0h - Get inf
17079                 rmation via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 secon
17080                 s Fh - Ch = Reserved
17081                 PSU_IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR                                       0X0
17082
17083                 SD Config Register 3
17084                 (OFFSET, MASK, VALUE)      (0XFF180324, 0x03C00000U ,0x00000000U)
17085                 RegMask = (IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK |  0 );
17086
17087                 RegVal = ((0x00000000U << IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT
17088                         |  0 ) & RegMask); */
17089                 PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG3_OFFSET ,0x03C00000U ,0x00000000U);
17090         /*############################################################################################################################ */
17091
17092                 // : CAN
17093                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
17094
17095                 Block level reset
17096                 PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET                                             0
17097
17098                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
17099                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000100U ,0x00000000U)
17100                 RegMask = (CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK |  0 );
17101
17102                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT
17103                         |  0 ) & RegMask); */
17104                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000100U ,0x00000000U);
17105         /*############################################################################################################################ */
17106
17107                 // : I2C
17108                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
17109
17110                 Block level reset
17111                 PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET                                             0
17112
17113                 Block level reset
17114                 PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET                                             0
17115
17116                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
17117                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000600U ,0x00000000U)
17118                 RegMask = (CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK | CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK |  0 );
17119
17120                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT
17121                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT
17122                         |  0 ) & RegMask); */
17123                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000600U ,0x00000000U);
17124         /*############################################################################################################################ */
17125
17126                 // : SWDT
17127                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
17128
17129                 Block level reset
17130                 PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET                                             0
17131
17132                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
17133                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00008000U ,0x00000000U)
17134                 RegMask = (CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK |  0 );
17135
17136                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT
17137                         |  0 ) & RegMask); */
17138                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00008000U ,0x00000000U);
17139         /*############################################################################################################################ */
17140
17141                 // : SPI
17142                 // : TTC
17143                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
17144
17145                 Block level reset
17146                 PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET                                             0
17147
17148                 Block level reset
17149                 PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET                                             0
17150
17151                 Block level reset
17152                 PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET                                             0
17153
17154                 Block level reset
17155                 PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET                                             0
17156
17157                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
17158                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00007800U ,0x00000000U)
17159                 RegMask = (CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK |  0 );
17160
17161                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT
17162                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT
17163                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT
17164                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT
17165                         |  0 ) & RegMask); */
17166                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00007800U ,0x00000000U);
17167         /*############################################################################################################################ */
17168
17169                 // : UART
17170                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
17171
17172                 Block level reset
17173                 PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET                                            0
17174
17175                 Block level reset
17176                 PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET                                            0
17177
17178                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
17179                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000006U ,0x00000000U)
17180                 RegMask = (CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK | CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK |  0 );
17181
17182                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT
17183                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT
17184                         |  0 ) & RegMask); */
17185                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000006U ,0x00000000U);
17186         /*############################################################################################################################ */
17187
17188                 // : UART BAUD RATE
17189                 /*Register : Baud_rate_divider_reg0 @ 0XFF000034</p>
17190
17191                 Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
17192                 PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV                                           0x5
17193
17194                 Baud Rate Divider Register
17195                 (OFFSET, MASK, VALUE)      (0XFF000034, 0x000000FFU ,0x00000005U)
17196                 RegMask = (UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK |  0 );
17197
17198                 RegVal = ((0x00000005U << UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
17199                         |  0 ) & RegMask); */
17200                 PSU_Mask_Write (UART0_BAUD_RATE_DIVIDER_REG0_OFFSET ,0x000000FFU ,0x00000005U);
17201         /*############################################################################################################################ */
17202
17203                 /*Register : Baud_rate_gen_reg0 @ 0XFF000018</p>
17204
17205                 Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
17206                 PSU_UART0_BAUD_RATE_GEN_REG0_CD                                                 0x8f
17207
17208                 Baud Rate Generator Register.
17209                 (OFFSET, MASK, VALUE)      (0XFF000018, 0x0000FFFFU ,0x0000008FU)
17210                 RegMask = (UART0_BAUD_RATE_GEN_REG0_CD_MASK |  0 );
17211
17212                 RegVal = ((0x0000008FU << UART0_BAUD_RATE_GEN_REG0_CD_SHIFT
17213                         |  0 ) & RegMask); */
17214                 PSU_Mask_Write (UART0_BAUD_RATE_GEN_REG0_OFFSET ,0x0000FFFFU ,0x0000008FU);
17215         /*############################################################################################################################ */
17216
17217                 /*Register : Control_reg0 @ 0XFF000000</p>
17218
17219                 Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
17220                 high level during 12 bit periods. It can be set regardless of the value of STTBRK.
17221                 PSU_UART0_CONTROL_REG0_STPBRK                                                   0x0
17222
17223                 Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
17224                 transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
17225                 PSU_UART0_CONTROL_REG0_STTBRK                                                   0x0
17226
17227                 Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
17228                 pleted.
17229                 PSU_UART0_CONTROL_REG0_RSTTO                                                    0x0
17230
17231                 Transmit disable: 0: enable transmitter 1: disable transmitter
17232                 PSU_UART0_CONTROL_REG0_TXDIS                                                    0x0
17233
17234                 Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
17235                 PSU_UART0_CONTROL_REG0_TXEN                                                     0x1
17236
17237                 Receive disable: 0: enable 1: disable, regardless of the value of RXEN
17238                 PSU_UART0_CONTROL_REG0_RXDIS                                                    0x0
17239
17240                 Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
17241                 PSU_UART0_CONTROL_REG0_RXEN                                                     0x1
17242
17243                 Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
17244                  bit is self clearing once the reset has completed.
17245                 PSU_UART0_CONTROL_REG0_TXRES                                                    0x1
17246
17247                 Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
17248                 is self clearing once the reset has completed.
17249                 PSU_UART0_CONTROL_REG0_RXRES                                                    0x1
17250
17251                 UART Control Register
17252                 (OFFSET, MASK, VALUE)      (0XFF000000, 0x000001FFU ,0x00000017U)
17253                 RegMask = (UART0_CONTROL_REG0_STPBRK_MASK | UART0_CONTROL_REG0_STTBRK_MASK | UART0_CONTROL_REG0_RSTTO_MASK | UART0_CONTROL_REG0_TXDIS_MASK | UART0_CONTROL_REG0_TXEN_MASK | UART0_CONTROL_REG0_RXDIS_MASK | UART0_CONTROL_REG0_RXEN_MASK | UART0_CONTROL_REG0_TXRES_MASK | UART0_CONTROL_REG0_RXRES_MASK |  0 );
17254
17255                 RegVal = ((0x00000000U << UART0_CONTROL_REG0_STPBRK_SHIFT
17256                         | 0x00000000U << UART0_CONTROL_REG0_STTBRK_SHIFT
17257                         | 0x00000000U << UART0_CONTROL_REG0_RSTTO_SHIFT
17258                         | 0x00000000U << UART0_CONTROL_REG0_TXDIS_SHIFT
17259                         | 0x00000001U << UART0_CONTROL_REG0_TXEN_SHIFT
17260                         | 0x00000000U << UART0_CONTROL_REG0_RXDIS_SHIFT
17261                         | 0x00000001U << UART0_CONTROL_REG0_RXEN_SHIFT
17262                         | 0x00000001U << UART0_CONTROL_REG0_TXRES_SHIFT
17263                         | 0x00000001U << UART0_CONTROL_REG0_RXRES_SHIFT
17264                         |  0 ) & RegMask); */
17265                 PSU_Mask_Write (UART0_CONTROL_REG0_OFFSET ,0x000001FFU ,0x00000017U);
17266         /*############################################################################################################################ */
17267
17268                 /*Register : mode_reg0 @ 0XFF000004</p>
17269
17270                 Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
17271                 PSU_UART0_MODE_REG0_CHMODE                                                      0x0
17272
17273                 Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
17274                 stop bits 10: 2 stop bits 11: reserved
17275                 PSU_UART0_MODE_REG0_NBSTOP                                                      0x0
17276
17277                 Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity
17278                 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
17279                 PSU_UART0_MODE_REG0_PAR                                                         0x4
17280
17281                 Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
17282                 PSU_UART0_MODE_REG0_CHRL                                                        0x0
17283
17284                 Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
17285                 source is uart_ref_clk 1: clock source is uart_ref_clk/8
17286                 PSU_UART0_MODE_REG0_CLKS                                                        0x0
17287
17288                 UART Mode Register
17289                 (OFFSET, MASK, VALUE)      (0XFF000004, 0x000003FFU ,0x00000020U)
17290                 RegMask = (UART0_MODE_REG0_CHMODE_MASK | UART0_MODE_REG0_NBSTOP_MASK | UART0_MODE_REG0_PAR_MASK | UART0_MODE_REG0_CHRL_MASK | UART0_MODE_REG0_CLKS_MASK |  0 );
17291
17292                 RegVal = ((0x00000000U << UART0_MODE_REG0_CHMODE_SHIFT
17293                         | 0x00000000U << UART0_MODE_REG0_NBSTOP_SHIFT
17294                         | 0x00000004U << UART0_MODE_REG0_PAR_SHIFT
17295                         | 0x00000000U << UART0_MODE_REG0_CHRL_SHIFT
17296                         | 0x00000000U << UART0_MODE_REG0_CLKS_SHIFT
17297                         |  0 ) & RegMask); */
17298                 PSU_Mask_Write (UART0_MODE_REG0_OFFSET ,0x000003FFU ,0x00000020U);
17299         /*############################################################################################################################ */
17300
17301                 /*Register : Baud_rate_divider_reg0 @ 0XFF010034</p>
17302
17303                 Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
17304                 PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV                                           0x5
17305
17306                 Baud Rate Divider Register
17307                 (OFFSET, MASK, VALUE)      (0XFF010034, 0x000000FFU ,0x00000005U)
17308                 RegMask = (UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK |  0 );
17309
17310                 RegVal = ((0x00000005U << UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
17311                         |  0 ) & RegMask); */
17312                 PSU_Mask_Write (UART1_BAUD_RATE_DIVIDER_REG0_OFFSET ,0x000000FFU ,0x00000005U);
17313         /*############################################################################################################################ */
17314
17315                 /*Register : Baud_rate_gen_reg0 @ 0XFF010018</p>
17316
17317                 Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
17318                 PSU_UART1_BAUD_RATE_GEN_REG0_CD                                                 0x8f
17319
17320                 Baud Rate Generator Register.
17321                 (OFFSET, MASK, VALUE)      (0XFF010018, 0x0000FFFFU ,0x0000008FU)
17322                 RegMask = (UART1_BAUD_RATE_GEN_REG0_CD_MASK |  0 );
17323
17324                 RegVal = ((0x0000008FU << UART1_BAUD_RATE_GEN_REG0_CD_SHIFT
17325                         |  0 ) & RegMask); */
17326                 PSU_Mask_Write (UART1_BAUD_RATE_GEN_REG0_OFFSET ,0x0000FFFFU ,0x0000008FU);
17327         /*############################################################################################################################ */
17328
17329                 /*Register : Control_reg0 @ 0XFF010000</p>
17330
17331                 Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
17332                 high level during 12 bit periods. It can be set regardless of the value of STTBRK.
17333                 PSU_UART1_CONTROL_REG0_STPBRK                                                   0x0
17334
17335                 Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
17336                 transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
17337                 PSU_UART1_CONTROL_REG0_STTBRK                                                   0x0
17338
17339                 Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
17340                 pleted.
17341                 PSU_UART1_CONTROL_REG0_RSTTO                                                    0x0
17342
17343                 Transmit disable: 0: enable transmitter 1: disable transmitter
17344                 PSU_UART1_CONTROL_REG0_TXDIS                                                    0x0
17345
17346                 Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
17347                 PSU_UART1_CONTROL_REG0_TXEN                                                     0x1
17348
17349                 Receive disable: 0: enable 1: disable, regardless of the value of RXEN
17350                 PSU_UART1_CONTROL_REG0_RXDIS                                                    0x0
17351
17352                 Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
17353                 PSU_UART1_CONTROL_REG0_RXEN                                                     0x1
17354
17355                 Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
17356                  bit is self clearing once the reset has completed.
17357                 PSU_UART1_CONTROL_REG0_TXRES                                                    0x1
17358
17359                 Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
17360                 is self clearing once the reset has completed.
17361                 PSU_UART1_CONTROL_REG0_RXRES                                                    0x1
17362
17363                 UART Control Register
17364                 (OFFSET, MASK, VALUE)      (0XFF010000, 0x000001FFU ,0x00000017U)
17365                 RegMask = (UART1_CONTROL_REG0_STPBRK_MASK | UART1_CONTROL_REG0_STTBRK_MASK | UART1_CONTROL_REG0_RSTTO_MASK | UART1_CONTROL_REG0_TXDIS_MASK | UART1_CONTROL_REG0_TXEN_MASK | UART1_CONTROL_REG0_RXDIS_MASK | UART1_CONTROL_REG0_RXEN_MASK | UART1_CONTROL_REG0_TXRES_MASK | UART1_CONTROL_REG0_RXRES_MASK |  0 );
17366
17367                 RegVal = ((0x00000000U << UART1_CONTROL_REG0_STPBRK_SHIFT
17368                         | 0x00000000U << UART1_CONTROL_REG0_STTBRK_SHIFT
17369                         | 0x00000000U << UART1_CONTROL_REG0_RSTTO_SHIFT
17370                         | 0x00000000U << UART1_CONTROL_REG0_TXDIS_SHIFT
17371                         | 0x00000001U << UART1_CONTROL_REG0_TXEN_SHIFT
17372                         | 0x00000000U << UART1_CONTROL_REG0_RXDIS_SHIFT
17373                         | 0x00000001U << UART1_CONTROL_REG0_RXEN_SHIFT
17374                         | 0x00000001U << UART1_CONTROL_REG0_TXRES_SHIFT
17375                         | 0x00000001U << UART1_CONTROL_REG0_RXRES_SHIFT
17376                         |  0 ) & RegMask); */
17377                 PSU_Mask_Write (UART1_CONTROL_REG0_OFFSET ,0x000001FFU ,0x00000017U);
17378         /*############################################################################################################################ */
17379
17380                 /*Register : mode_reg0 @ 0XFF010004</p>
17381
17382                 Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
17383                 PSU_UART1_MODE_REG0_CHMODE                                                      0x0
17384
17385                 Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
17386                 stop bits 10: 2 stop bits 11: reserved
17387                 PSU_UART1_MODE_REG0_NBSTOP                                                      0x0
17388
17389                 Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity
17390                 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
17391                 PSU_UART1_MODE_REG0_PAR                                                         0x4
17392
17393                 Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
17394                 PSU_UART1_MODE_REG0_CHRL                                                        0x0
17395
17396                 Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
17397                 source is uart_ref_clk 1: clock source is uart_ref_clk/8
17398                 PSU_UART1_MODE_REG0_CLKS                                                        0x0
17399
17400                 UART Mode Register
17401                 (OFFSET, MASK, VALUE)      (0XFF010004, 0x000003FFU ,0x00000020U)
17402                 RegMask = (UART1_MODE_REG0_CHMODE_MASK | UART1_MODE_REG0_NBSTOP_MASK | UART1_MODE_REG0_PAR_MASK | UART1_MODE_REG0_CHRL_MASK | UART1_MODE_REG0_CLKS_MASK |  0 );
17403
17404                 RegVal = ((0x00000000U << UART1_MODE_REG0_CHMODE_SHIFT
17405                         | 0x00000000U << UART1_MODE_REG0_NBSTOP_SHIFT
17406                         | 0x00000004U << UART1_MODE_REG0_PAR_SHIFT
17407                         | 0x00000000U << UART1_MODE_REG0_CHRL_SHIFT
17408                         | 0x00000000U << UART1_MODE_REG0_CLKS_SHIFT
17409                         |  0 ) & RegMask); */
17410                 PSU_Mask_Write (UART1_MODE_REG0_OFFSET ,0x000003FFU ,0x00000020U);
17411         /*############################################################################################################################ */
17412
17413                 // : GPIO
17414                 // : ADMA TZ
17415                 /*Register : slcr_adma @ 0XFF4B0024</p>
17416
17417                 TrustZone Classification for ADMA
17418                 PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ                                                0XFF
17419
17420                 RPU TrustZone settings
17421                 (OFFSET, MASK, VALUE)      (0XFF4B0024, 0x000000FFU ,0x000000FFU)
17422                 RegMask = (LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK |  0 );
17423
17424                 RegVal = ((0x000000FFU << LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT
17425                         |  0 ) & RegMask); */
17426                 PSU_Mask_Write (LPD_SLCR_SECURE_SLCR_ADMA_OFFSET ,0x000000FFU ,0x000000FFU);
17427         /*############################################################################################################################ */
17428
17429                 // : CSU TAMPERING
17430                 // : CSU TAMPER STATUS
17431                 /*Register : tamper_status @ 0XFFCA5000</p>
17432
17433                 CSU regsiter
17434                 PSU_CSU_TAMPER_STATUS_TAMPER_0                                                  0
17435
17436                 External MIO
17437                 PSU_CSU_TAMPER_STATUS_TAMPER_1                                                  0
17438
17439                 JTAG toggle detect
17440                 PSU_CSU_TAMPER_STATUS_TAMPER_2                                                  0
17441
17442                 PL SEU error
17443                 PSU_CSU_TAMPER_STATUS_TAMPER_3                                                  0
17444
17445                 AMS over temperature alarm for LPD
17446                 PSU_CSU_TAMPER_STATUS_TAMPER_4                                                  0
17447
17448                 AMS over temperature alarm for APU
17449                 PSU_CSU_TAMPER_STATUS_TAMPER_5                                                  0
17450
17451                 AMS voltage alarm for VCCPINT_FPD
17452                 PSU_CSU_TAMPER_STATUS_TAMPER_6                                                  0
17453
17454                 AMS voltage alarm for VCCPINT_LPD
17455                 PSU_CSU_TAMPER_STATUS_TAMPER_7                                                  0
17456
17457                 AMS voltage alarm for VCCPAUX
17458                 PSU_CSU_TAMPER_STATUS_TAMPER_8                                                  0
17459
17460                 AMS voltage alarm for DDRPHY
17461                 PSU_CSU_TAMPER_STATUS_TAMPER_9                                                  0
17462
17463                 AMS voltage alarm for PSIO bank 0/1/2
17464                 PSU_CSU_TAMPER_STATUS_TAMPER_10                                                 0
17465
17466                 AMS voltage alarm for PSIO bank 3 (dedicated pins)
17467                 PSU_CSU_TAMPER_STATUS_TAMPER_11                                                 0
17468
17469                 AMS voltaage alarm for GT
17470                 PSU_CSU_TAMPER_STATUS_TAMPER_12                                                 0
17471
17472                 Tamper Response Status
17473                 (OFFSET, MASK, VALUE)      (0XFFCA5000, 0x00001FFFU ,0x00000000U)
17474                 RegMask = (CSU_TAMPER_STATUS_TAMPER_0_MASK | CSU_TAMPER_STATUS_TAMPER_1_MASK | CSU_TAMPER_STATUS_TAMPER_2_MASK | CSU_TAMPER_STATUS_TAMPER_3_MASK | CSU_TAMPER_STATUS_TAMPER_4_MASK | CSU_TAMPER_STATUS_TAMPER_5_MASK | CSU_TAMPER_STATUS_TAMPER_6_MASK | CSU_TAMPER_STATUS_TAMPER_7_MASK | CSU_TAMPER_STATUS_TAMPER_8_MASK | CSU_TAMPER_STATUS_TAMPER_9_MASK | CSU_TAMPER_STATUS_TAMPER_10_MASK | CSU_TAMPER_STATUS_TAMPER_11_MASK | CSU_TAMPER_STATUS_TAMPER_12_MASK |  0 );
17475
17476                 RegVal = ((0x00000000U << CSU_TAMPER_STATUS_TAMPER_0_SHIFT
17477                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_1_SHIFT
17478                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_2_SHIFT
17479                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_3_SHIFT
17480                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_4_SHIFT
17481                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_5_SHIFT
17482                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_6_SHIFT
17483                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_7_SHIFT
17484                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_8_SHIFT
17485                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_9_SHIFT
17486                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_10_SHIFT
17487                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_11_SHIFT
17488                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_12_SHIFT
17489                         |  0 ) & RegMask); */
17490                 PSU_Mask_Write (CSU_TAMPER_STATUS_OFFSET ,0x00001FFFU ,0x00000000U);
17491         /*############################################################################################################################ */
17492
17493                 // : CSU TAMPER RESPONSE
17494                 // : AFIFM INTERFACE WIDTH
17495                 // : CPU QOS DEFAULT
17496                 /*Register : ACE_CTRL @ 0XFD5C0060</p>
17497
17498                 Set ACE outgoing AWQOS value
17499                 PSU_APU_ACE_CTRL_AWQOS                                                          0X0
17500
17501                 Set ACE outgoing ARQOS value
17502                 PSU_APU_ACE_CTRL_ARQOS                                                          0X0
17503
17504                 ACE Control Register
17505                 (OFFSET, MASK, VALUE)      (0XFD5C0060, 0x000F000FU ,0x00000000U)
17506                 RegMask = (APU_ACE_CTRL_AWQOS_MASK | APU_ACE_CTRL_ARQOS_MASK |  0 );
17507
17508                 RegVal = ((0x00000000U << APU_ACE_CTRL_AWQOS_SHIFT
17509                         | 0x00000000U << APU_ACE_CTRL_ARQOS_SHIFT
17510                         |  0 ) & RegMask); */
17511                 PSU_Mask_Write (APU_ACE_CTRL_OFFSET ,0x000F000FU ,0x00000000U);
17512         /*############################################################################################################################ */
17513
17514                 // : ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE
17515                 /*Register : CONTROL @ 0XFFA60040</p>
17516
17517                 Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from
17518                 he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e
17519                 pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi
17520                 g a 0 to this bit.
17521                 PSU_RTC_CONTROL_BATTERY_DISABLE                                                 0X1
17522
17523                 This register controls various functionalities within the RTC
17524                 (OFFSET, MASK, VALUE)      (0XFFA60040, 0x80000000U ,0x80000000U)
17525                 RegMask = (RTC_CONTROL_BATTERY_DISABLE_MASK |  0 );
17526
17527                 RegVal = ((0x00000001U << RTC_CONTROL_BATTERY_DISABLE_SHIFT
17528                         |  0 ) & RegMask); */
17529                 PSU_Mask_Write (RTC_CONTROL_OFFSET ,0x80000000U ,0x80000000U);
17530         /*############################################################################################################################ */
17531
17532                 // : TIMESTAMP COUNTER
17533                 /*Register : base_frequency_ID_register @ 0XFF260020</p>
17534
17535                 Frequency in number of ticks per second. Valid range from 10 MHz to 100 MHz.
17536                 PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ                                  0x5f5e100
17537
17538                 Program this register to match the clock frequency of the timestamp generator, in ticks per second. For example, for a 50 MHz
17539                 clock, program 0x02FAF080. This register is not accessible to the read-only programming interface.
17540                 (OFFSET, MASK, VALUE)      (0XFF260020, 0xFFFFFFFFU ,0x05F5E100U)
17541                 RegMask = (IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK |  0 );
17542
17543                 RegVal = ((0x05F5E100U << IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT
17544                         |  0 ) & RegMask); */
17545                 PSU_Mask_Write (IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET ,0xFFFFFFFFU ,0x05F5E100U);
17546         /*############################################################################################################################ */
17547
17548                 /*Register : counter_control_register @ 0XFF260000</p>
17549
17550                 Enable 0: The counter is disabled and not incrementing. 1: The counter is enabled and is incrementing.
17551                 PSU_IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN                                      0x1
17552
17553                 Controls the counter increments. This register is not accessible to the read-only programming interface.
17554                 (OFFSET, MASK, VALUE)      (0XFF260000, 0x00000001U ,0x00000001U)
17555                 RegMask = (IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK |  0 );
17556
17557                 RegVal = ((0x00000001U << IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT
17558                         |  0 ) & RegMask); */
17559                 PSU_Mask_Write (IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET ,0x00000001U ,0x00000001U);
17560         /*############################################################################################################################ */
17561
17562                 // : TTC SRC SELECT
17563
17564   return 1;
17565 }
17566 unsigned long psu_post_config_data() {
17567                 // : POST_CONFIG
17568
17569   return 1;
17570 }
17571 unsigned long psu_peripherals_powerdwn_data() {
17572                 // : POWER DOWN REQUEST INTERRUPT ENABLE
17573                 // : POWER DOWN TRIGGER
17574
17575   return 1;
17576 }
17577 unsigned long psu_lpd_xppu_data() {
17578                 // : XPPU INTERRUPT ENABLE
17579                 /*Register : IEN @ 0XFF980018</p>
17580
17581                 See Interuppt Status Register for details
17582                 PSU_LPD_XPPU_CFG_IEN_APER_PARITY                                                0X1
17583
17584                 See Interuppt Status Register for details
17585                 PSU_LPD_XPPU_CFG_IEN_APER_TZ                                                    0X1
17586
17587                 See Interuppt Status Register for details
17588                 PSU_LPD_XPPU_CFG_IEN_APER_PERM                                                  0X1
17589
17590                 See Interuppt Status Register for details
17591                 PSU_LPD_XPPU_CFG_IEN_MID_PARITY                                                 0X1
17592
17593                 See Interuppt Status Register for details
17594                 PSU_LPD_XPPU_CFG_IEN_MID_RO                                                     0X1
17595
17596                 See Interuppt Status Register for details
17597                 PSU_LPD_XPPU_CFG_IEN_MID_MISS                                                   0X1
17598
17599                 See Interuppt Status Register for details
17600                 PSU_LPD_XPPU_CFG_IEN_INV_APB                                                    0X1
17601
17602                 Interrupt Enable Register
17603                 (OFFSET, MASK, VALUE)      (0XFF980018, 0x000000EFU ,0x000000EFU)
17604                 RegMask = (LPD_XPPU_CFG_IEN_APER_PARITY_MASK | LPD_XPPU_CFG_IEN_APER_TZ_MASK | LPD_XPPU_CFG_IEN_APER_PERM_MASK | LPD_XPPU_CFG_IEN_MID_PARITY_MASK | LPD_XPPU_CFG_IEN_MID_RO_MASK | LPD_XPPU_CFG_IEN_MID_MISS_MASK | LPD_XPPU_CFG_IEN_INV_APB_MASK |  0 );
17605
17606                 RegVal = ((0x00000001U << LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT
17607                         | 0x00000001U << LPD_XPPU_CFG_IEN_APER_TZ_SHIFT
17608                         | 0x00000001U << LPD_XPPU_CFG_IEN_APER_PERM_SHIFT
17609                         | 0x00000001U << LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT
17610                         | 0x00000001U << LPD_XPPU_CFG_IEN_MID_RO_SHIFT
17611                         | 0x00000001U << LPD_XPPU_CFG_IEN_MID_MISS_SHIFT
17612                         | 0x00000001U << LPD_XPPU_CFG_IEN_INV_APB_SHIFT
17613                         |  0 ) & RegMask); */
17614                 PSU_Mask_Write (LPD_XPPU_CFG_IEN_OFFSET ,0x000000EFU ,0x000000EFU);
17615         /*############################################################################################################################ */
17616
17617
17618   return 1;
17619 }
17620 unsigned long psu_ddr_xmpu0_data() {
17621
17622   return 1;
17623 }
17624 unsigned long psu_ddr_xmpu1_data() {
17625
17626   return 1;
17627 }
17628 unsigned long psu_ddr_xmpu2_data() {
17629
17630   return 1;
17631 }
17632 unsigned long psu_ddr_xmpu3_data() {
17633
17634   return 1;
17635 }
17636 unsigned long psu_ddr_xmpu4_data() {
17637
17638   return 1;
17639 }
17640 unsigned long psu_ddr_xmpu5_data() {
17641
17642   return 1;
17643 }
17644 unsigned long psu_ocm_xmpu_data() {
17645
17646   return 1;
17647 }
17648 unsigned long psu_fpd_xmpu_data() {
17649
17650   return 1;
17651 }
17652 unsigned long psu_protection_lock_data() {
17653
17654   return 1;
17655 }
17656 unsigned long psu_apply_master_tz() {
17657                 // : RPU
17658                 // : DP TZ
17659                 // : SATA TZ
17660                 // : PCIE TZ
17661                 // : USB TZ
17662                 // : SD TZ
17663                 // : GEM TZ
17664                 // : QSPI TZ
17665                 // : NAND TZ
17666
17667   return 1;
17668 }
17669 unsigned long psu_serdes_init_data() {
17670                 // : SERDES INITIALIZATION
17671                 // : GT REFERENCE CLOCK SOURCE SELECTION
17672                 /*Register : PLL_REF_SEL0 @ 0XFD410000</p>
17673
17674                 PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
17675                 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
17676                 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
17677                 PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0                                              0xD
17678
17679                 PLL0 Reference Selection Register
17680                 (OFFSET, MASK, VALUE)      (0XFD410000, 0x0000001FU ,0x0000000DU)
17681                 RegMask = (SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK |  0 );
17682
17683                 RegVal = ((0x0000000DU << SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT
17684                         |  0 ) & RegMask); */
17685                 PSU_Mask_Write (SERDES_PLL_REF_SEL0_OFFSET ,0x0000001FU ,0x0000000DU);
17686         /*############################################################################################################################ */
17687
17688                 /*Register : PLL_REF_SEL1 @ 0XFD410004</p>
17689
17690                 PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
17691                 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
17692                 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
17693                 PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1                                              0x9
17694
17695                 PLL1 Reference Selection Register
17696                 (OFFSET, MASK, VALUE)      (0XFD410004, 0x0000001FU ,0x00000009U)
17697                 RegMask = (SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK |  0 );
17698
17699                 RegVal = ((0x00000009U << SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT
17700                         |  0 ) & RegMask); */
17701                 PSU_Mask_Write (SERDES_PLL_REF_SEL1_OFFSET ,0x0000001FU ,0x00000009U);
17702         /*############################################################################################################################ */
17703
17704                 /*Register : PLL_REF_SEL2 @ 0XFD410008</p>
17705
17706                 PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
17707                 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
17708                 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
17709                 PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2                                              0x8
17710
17711                 PLL2 Reference Selection Register
17712                 (OFFSET, MASK, VALUE)      (0XFD410008, 0x0000001FU ,0x00000008U)
17713                 RegMask = (SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK |  0 );
17714
17715                 RegVal = ((0x00000008U << SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT
17716                         |  0 ) & RegMask); */
17717                 PSU_Mask_Write (SERDES_PLL_REF_SEL2_OFFSET ,0x0000001FU ,0x00000008U);
17718         /*############################################################################################################################ */
17719
17720                 /*Register : PLL_REF_SEL3 @ 0XFD41000C</p>
17721
17722                 PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
17723                 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
17724                 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
17725                 PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3                                              0xF
17726
17727                 PLL3 Reference Selection Register
17728                 (OFFSET, MASK, VALUE)      (0XFD41000C, 0x0000001FU ,0x0000000FU)
17729                 RegMask = (SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK |  0 );
17730
17731                 RegVal = ((0x0000000FU << SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT
17732                         |  0 ) & RegMask); */
17733                 PSU_Mask_Write (SERDES_PLL_REF_SEL3_OFFSET ,0x0000001FU ,0x0000000FU);
17734         /*############################################################################################################################ */
17735
17736                 // : GT REFERENCE CLOCK FREQUENCY SELECTION
17737                 /*Register : L0_L0_REF_CLK_SEL @ 0XFD402860</p>
17738
17739                 Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output.
17740                 PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL                                 0x1
17741
17742                 Lane0 Ref Clock Selection Register
17743                 (OFFSET, MASK, VALUE)      (0XFD402860, 0x00000080U ,0x00000080U)
17744                 RegMask = (SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK |  0 );
17745
17746                 RegVal = ((0x00000001U << SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT
17747                         |  0 ) & RegMask); */
17748                 PSU_Mask_Write (SERDES_L0_L0_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U);
17749         /*############################################################################################################################ */
17750
17751                 /*Register : L0_L1_REF_CLK_SEL @ 0XFD402864</p>
17752
17753                 Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output.
17754                 PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL                                 0x0
17755
17756                 Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network
17757                 PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3                                   0x1
17758
17759                 Lane1 Ref Clock Selection Register
17760                 (OFFSET, MASK, VALUE)      (0XFD402864, 0x00000088U ,0x00000008U)
17761                 RegMask = (SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK | SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK |  0 );
17762
17763                 RegVal = ((0x00000000U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT
17764                         | 0x00000001U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT
17765                         |  0 ) & RegMask); */
17766                 PSU_Mask_Write (SERDES_L0_L1_REF_CLK_SEL_OFFSET ,0x00000088U ,0x00000008U);
17767         /*############################################################################################################################ */
17768
17769                 /*Register : L0_L2_REF_CLK_SEL @ 0XFD402868</p>
17770
17771                 Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output.
17772                 PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL                                 0x1
17773
17774                 Lane2 Ref Clock Selection Register
17775                 (OFFSET, MASK, VALUE)      (0XFD402868, 0x00000080U ,0x00000080U)
17776                 RegMask = (SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK |  0 );
17777
17778                 RegVal = ((0x00000001U << SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT
17779                         |  0 ) & RegMask); */
17780                 PSU_Mask_Write (SERDES_L0_L2_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U);
17781         /*############################################################################################################################ */
17782
17783                 /*Register : L0_L3_REF_CLK_SEL @ 0XFD40286C</p>
17784
17785                 Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output.
17786                 PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL                                 0x0
17787
17788                 Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network
17789                 PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1                                   0x1
17790
17791                 Lane3 Ref Clock Selection Register
17792                 (OFFSET, MASK, VALUE)      (0XFD40286C, 0x00000082U ,0x00000002U)
17793                 RegMask = (SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK | SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK |  0 );
17794
17795                 RegVal = ((0x00000000U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT
17796                         | 0x00000001U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT
17797                         |  0 ) & RegMask); */
17798                 PSU_Mask_Write (SERDES_L0_L3_REF_CLK_SEL_OFFSET ,0x00000082U ,0x00000002U);
17799         /*############################################################################################################################ */
17800
17801                 // : ENABLE SPREAD SPECTRUM
17802                 /*Register : L2_TM_PLL_DIG_37 @ 0XFD40A094</p>
17803
17804                 Enable/Disable coarse code satureation limiting logic
17805                 PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION                         0x1
17806
17807                 Test mode register 37
17808                 (OFFSET, MASK, VALUE)      (0XFD40A094, 0x00000010U ,0x00000010U)
17809                 RegMask = (SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK |  0 );
17810
17811                 RegVal = ((0x00000001U << SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT
17812                         |  0 ) & RegMask); */
17813                 PSU_Mask_Write (SERDES_L2_TM_PLL_DIG_37_OFFSET ,0x00000010U ,0x00000010U);
17814         /*############################################################################################################################ */
17815
17816                 /*Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368</p>
17817
17818                 Spread Spectrum No of Steps [7:0]
17819                 PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB                          0x38
17820
17821                 Spread Spectrum No of Steps bits 7:0
17822                 (OFFSET, MASK, VALUE)      (0XFD40A368, 0x000000FFU ,0x00000038U)
17823                 RegMask = (SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK |  0 );
17824
17825                 RegVal = ((0x00000038U << SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
17826                         |  0 ) & RegMask); */
17827                 PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000038U);
17828         /*############################################################################################################################ */
17829
17830                 /*Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C</p>
17831
17832                 Spread Spectrum No of Steps [10:8]
17833                 PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB                          0x03
17834
17835                 Spread Spectrum No of Steps bits 10:8
17836                 (OFFSET, MASK, VALUE)      (0XFD40A36C, 0x00000007U ,0x00000003U)
17837                 RegMask = (SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK |  0 );
17838
17839                 RegVal = ((0x00000003U << SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
17840                         |  0 ) & RegMask); */
17841                 PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U);
17842         /*############################################################################################################################ */
17843
17844                 /*Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368</p>
17845
17846                 Spread Spectrum No of Steps [7:0]
17847                 PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB                          0xE0
17848
17849                 Spread Spectrum No of Steps bits 7:0
17850                 (OFFSET, MASK, VALUE)      (0XFD40E368, 0x000000FFU ,0x000000E0U)
17851                 RegMask = (SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK |  0 );
17852
17853                 RegVal = ((0x000000E0U << SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
17854                         |  0 ) & RegMask); */
17855                 PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x000000E0U);
17856         /*############################################################################################################################ */
17857
17858                 /*Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C</p>
17859
17860                 Spread Spectrum No of Steps [10:8]
17861                 PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB                          0x3
17862
17863                 Spread Spectrum No of Steps bits 10:8
17864                 (OFFSET, MASK, VALUE)      (0XFD40E36C, 0x00000007U ,0x00000003U)
17865                 RegMask = (SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK |  0 );
17866
17867                 RegVal = ((0x00000003U << SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
17868                         |  0 ) & RegMask); */
17869                 PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U);
17870         /*############################################################################################################################ */
17871
17872                 /*Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368</p>
17873
17874                 Spread Spectrum No of Steps [7:0]
17875                 PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB                          0x58
17876
17877                 Spread Spectrum No of Steps bits 7:0
17878                 (OFFSET, MASK, VALUE)      (0XFD406368, 0x000000FFU ,0x00000058U)
17879                 RegMask = (SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK |  0 );
17880
17881                 RegVal = ((0x00000058U << SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
17882                         |  0 ) & RegMask); */
17883                 PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000058U);
17884         /*############################################################################################################################ */
17885
17886                 /*Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C</p>
17887
17888                 Spread Spectrum No of Steps [10:8]
17889                 PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB                          0x3
17890
17891                 Spread Spectrum No of Steps bits 10:8
17892                 (OFFSET, MASK, VALUE)      (0XFD40636C, 0x00000007U ,0x00000003U)
17893                 RegMask = (SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK |  0 );
17894
17895                 RegVal = ((0x00000003U << SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
17896                         |  0 ) & RegMask); */
17897                 PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U);
17898         /*############################################################################################################################ */
17899
17900                 /*Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370</p>
17901
17902                 Step Size for Spread Spectrum [7:0]
17903                 PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB                         0x7C
17904
17905                 Step Size for Spread Spectrum LSB
17906                 (OFFSET, MASK, VALUE)      (0XFD406370, 0x000000FFU ,0x0000007CU)
17907                 RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK |  0 );
17908
17909                 RegVal = ((0x0000007CU << SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
17910                         |  0 ) & RegMask); */
17911                 PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x0000007CU);
17912         /*############################################################################################################################ */
17913
17914                 /*Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374</p>
17915
17916                 Step Size for Spread Spectrum [15:8]
17917                 PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1                                 0x33
17918
17919                 Step Size for Spread Spectrum 1
17920                 (OFFSET, MASK, VALUE)      (0XFD406374, 0x000000FFU ,0x00000033U)
17921                 RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK |  0 );
17922
17923                 RegVal = ((0x00000033U << SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
17924                         |  0 ) & RegMask); */
17925                 PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000033U);
17926         /*############################################################################################################################ */
17927
17928                 /*Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378</p>
17929
17930                 Step Size for Spread Spectrum [23:16]
17931                 PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2                                 0x2
17932
17933                 Step Size for Spread Spectrum 2
17934                 (OFFSET, MASK, VALUE)      (0XFD406378, 0x000000FFU ,0x00000002U)
17935                 RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK |  0 );
17936
17937                 RegVal = ((0x00000002U << SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
17938                         |  0 ) & RegMask); */
17939                 PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U);
17940         /*############################################################################################################################ */
17941
17942                 /*Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C</p>
17943
17944                 Step Size for Spread Spectrum [25:24]
17945                 PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB                         0x0
17946
17947                 Enable/Disable test mode force on SS step size
17948                 PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE                         0x1
17949
17950                 Enable/Disable test mode force on SS no of steps
17951                 PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS                      0x1
17952
17953                 Enable force on enable Spread Spectrum
17954                 (OFFSET, MASK, VALUE)      (0XFD40637C, 0x00000033U ,0x00000030U)
17955                 RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK |  0 );
17956
17957                 RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
17958                         | 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
17959                         | 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
17960                         |  0 ) & RegMask); */
17961                 PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U);
17962         /*############################################################################################################################ */
17963
17964                 /*Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370</p>
17965
17966                 Step Size for Spread Spectrum [7:0]
17967                 PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB                         0xF4
17968
17969                 Step Size for Spread Spectrum LSB
17970                 (OFFSET, MASK, VALUE)      (0XFD40A370, 0x000000FFU ,0x000000F4U)
17971                 RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK |  0 );
17972
17973                 RegVal = ((0x000000F4U << SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
17974                         |  0 ) & RegMask); */
17975                 PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x000000F4U);
17976         /*############################################################################################################################ */
17977
17978                 /*Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374</p>
17979
17980                 Step Size for Spread Spectrum [15:8]
17981                 PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1                                 0x31
17982
17983                 Step Size for Spread Spectrum 1
17984                 (OFFSET, MASK, VALUE)      (0XFD40A374, 0x000000FFU ,0x00000031U)
17985                 RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK |  0 );
17986
17987                 RegVal = ((0x00000031U << SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
17988                         |  0 ) & RegMask); */
17989                 PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000031U);
17990         /*############################################################################################################################ */
17991
17992                 /*Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378</p>
17993
17994                 Step Size for Spread Spectrum [23:16]
17995                 PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2                                 0x2
17996
17997                 Step Size for Spread Spectrum 2
17998                 (OFFSET, MASK, VALUE)      (0XFD40A378, 0x000000FFU ,0x00000002U)
17999                 RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK |  0 );
18000
18001                 RegVal = ((0x00000002U << SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
18002                         |  0 ) & RegMask); */
18003                 PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U);
18004         /*############################################################################################################################ */
18005
18006                 /*Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C</p>
18007
18008                 Step Size for Spread Spectrum [25:24]
18009                 PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB                         0x0
18010
18011                 Enable/Disable test mode force on SS step size
18012                 PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE                         0x1
18013
18014                 Enable/Disable test mode force on SS no of steps
18015                 PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS                      0x1
18016
18017                 Enable force on enable Spread Spectrum
18018                 (OFFSET, MASK, VALUE)      (0XFD40A37C, 0x00000033U ,0x00000030U)
18019                 RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK |  0 );
18020
18021                 RegVal = ((0x00000000U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
18022                         | 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
18023                         | 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
18024                         |  0 ) & RegMask); */
18025                 PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U);
18026         /*############################################################################################################################ */
18027
18028                 /*Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370</p>
18029
18030                 Step Size for Spread Spectrum [7:0]
18031                 PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB                         0xC9
18032
18033                 Step Size for Spread Spectrum LSB
18034                 (OFFSET, MASK, VALUE)      (0XFD40E370, 0x000000FFU ,0x000000C9U)
18035                 RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK |  0 );
18036
18037                 RegVal = ((0x000000C9U << SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
18038                         |  0 ) & RegMask); */
18039                 PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x000000C9U);
18040         /*############################################################################################################################ */
18041
18042                 /*Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374</p>
18043
18044                 Step Size for Spread Spectrum [15:8]
18045                 PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1                                 0xD2
18046
18047                 Step Size for Spread Spectrum 1
18048                 (OFFSET, MASK, VALUE)      (0XFD40E374, 0x000000FFU ,0x000000D2U)
18049                 RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK |  0 );
18050
18051                 RegVal = ((0x000000D2U << SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
18052                         |  0 ) & RegMask); */
18053                 PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x000000D2U);
18054         /*############################################################################################################################ */
18055
18056                 /*Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378</p>
18057
18058                 Step Size for Spread Spectrum [23:16]
18059                 PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2                                 0x1
18060
18061                 Step Size for Spread Spectrum 2
18062                 (OFFSET, MASK, VALUE)      (0XFD40E378, 0x000000FFU ,0x00000001U)
18063                 RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK |  0 );
18064
18065                 RegVal = ((0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
18066                         |  0 ) & RegMask); */
18067                 PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000001U);
18068         /*############################################################################################################################ */
18069
18070                 /*Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C</p>
18071
18072                 Step Size for Spread Spectrum [25:24]
18073                 PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB                         0x0
18074
18075                 Enable/Disable test mode force on SS step size
18076                 PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE                         0x1
18077
18078                 Enable/Disable test mode force on SS no of steps
18079                 PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS                      0x1
18080
18081                 Enable test mode forcing on enable Spread Spectrum
18082                 PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS                             0x1
18083
18084                 Enable force on enable Spread Spectrum
18085                 (OFFSET, MASK, VALUE)      (0XFD40E37C, 0x000000B3U ,0x000000B0U)
18086                 RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK |  0 );
18087
18088                 RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
18089                         | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
18090                         | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
18091                         | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT
18092                         |  0 ) & RegMask); */
18093                 PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x000000B3U ,0x000000B0U);
18094         /*############################################################################################################################ */
18095
18096                 /*Register : L2_TM_DIG_6 @ 0XFD40906C</p>
18097
18098                 Bypass Descrambler
18099                 PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM                                           0x1
18100
18101                 Enable Bypass for <1> TM_DIG_CTRL_6
18102                 PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM                                     0x1
18103
18104                 Data path test modes in decoder and descram
18105                 (OFFSET, MASK, VALUE)      (0XFD40906C, 0x00000003U ,0x00000003U)
18106                 RegMask = (SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK |  0 );
18107
18108                 RegVal = ((0x00000001U << SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT
18109                         | 0x00000001U << SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
18110                         |  0 ) & RegMask); */
18111                 PSU_Mask_Write (SERDES_L2_TM_DIG_6_OFFSET ,0x00000003U ,0x00000003U);
18112         /*############################################################################################################################ */
18113
18114                 /*Register : L2_TX_DIG_TM_61 @ 0XFD4080F4</p>
18115
18116                 Bypass scrambler signal
18117                 PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM                                         0x1
18118
18119                 Enable/disable scrambler bypass signal
18120                 PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM                                   0x1
18121
18122                 MPHY PLL Gear and bypass scrambler
18123                 (OFFSET, MASK, VALUE)      (0XFD4080F4, 0x00000003U ,0x00000003U)
18124                 RegMask = (SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK |  0 );
18125
18126                 RegVal = ((0x00000001U << SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
18127                         | 0x00000001U << SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
18128                         |  0 ) & RegMask); */
18129                 PSU_Mask_Write (SERDES_L2_TX_DIG_TM_61_OFFSET ,0x00000003U ,0x00000003U);
18130         /*############################################################################################################################ */
18131
18132                 /*Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360</p>
18133
18134                 Enable test mode force on fractional mode enable
18135                 PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC                             0x1
18136
18137                 Fractional feedback division control and fractional value for feedback division bits 26:24
18138                 (OFFSET, MASK, VALUE)      (0XFD40E360, 0x00000040U ,0x00000040U)
18139                 RegMask = (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK |  0 );
18140
18141                 RegVal = ((0x00000001U << SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT
18142                         |  0 ) & RegMask); */
18143                 PSU_Mask_Write (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET ,0x00000040U ,0x00000040U);
18144         /*############################################################################################################################ */
18145
18146                 /*Register : L3_TM_DIG_6 @ 0XFD40D06C</p>
18147
18148                 Bypass 8b10b decoder
18149                 PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER                                           0x1
18150
18151                 Enable Bypass for <3> TM_DIG_CTRL_6
18152                 PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC                                         0x1
18153
18154                 Bypass Descrambler
18155                 PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM                                           0x1
18156
18157                 Enable Bypass for <1> TM_DIG_CTRL_6
18158                 PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM                                     0x1
18159
18160                 Data path test modes in decoder and descram
18161                 (OFFSET, MASK, VALUE)      (0XFD40D06C, 0x0000000FU ,0x0000000FU)
18162                 RegMask = (SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK | SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK |  0 );
18163
18164                 RegVal = ((0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT
18165                         | 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT
18166                         | 0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT
18167                         | 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
18168                         |  0 ) & RegMask); */
18169                 PSU_Mask_Write (SERDES_L3_TM_DIG_6_OFFSET ,0x0000000FU ,0x0000000FU);
18170         /*############################################################################################################################ */
18171
18172                 /*Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4</p>
18173
18174                 Enable/disable encoder bypass signal
18175                 PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC                                           0x1
18176
18177                 Bypass scrambler signal
18178                 PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM                                         0x1
18179
18180                 Enable/disable scrambler bypass signal
18181                 PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM                                   0x1
18182
18183                 MPHY PLL Gear and bypass scrambler
18184                 (OFFSET, MASK, VALUE)      (0XFD40C0F4, 0x0000000BU ,0x0000000BU)
18185                 RegMask = (SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK | SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK |  0 );
18186
18187                 RegVal = ((0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT
18188                         | 0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
18189                         | 0x00000001U << SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
18190                         |  0 ) & RegMask); */
18191                 PSU_Mask_Write (SERDES_L3_TX_DIG_TM_61_OFFSET ,0x0000000BU ,0x0000000BU);
18192         /*############################################################################################################################ */
18193
18194                 /*Register : L3_TXPMA_ST_0 @ 0XFD40CB00</p>
18195
18196                 PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY
18197                 PSU_SERDES_L3_TXPMA_ST_0_TX_PHY_MODE                                            0x21
18198
18199                 Opmode Info
18200                 (OFFSET, MASK, VALUE)      (0XFD40CB00, 0x000000F0U ,0x000000F0U)
18201                 RegMask = (SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK |  0 );
18202
18203                 RegVal = ((0x00000021U << SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT
18204                         |  0 ) & RegMask); */
18205                 PSU_Mask_Write (SERDES_L3_TXPMA_ST_0_OFFSET ,0x000000F0U ,0x000000F0U);
18206         /*############################################################################################################################ */
18207
18208                 // : ENABLE CHICKEN BIT FOR PCIE AND USB
18209                 /*Register : L0_TM_AUX_0 @ 0XFD4010CC</p>
18210
18211                 Spare- not used
18212                 PSU_SERDES_L0_TM_AUX_0_BIT_2                                                    1
18213
18214                 Spare registers
18215                 (OFFSET, MASK, VALUE)      (0XFD4010CC, 0x00000020U ,0x00000020U)
18216                 RegMask = (SERDES_L0_TM_AUX_0_BIT_2_MASK |  0 );
18217
18218                 RegVal = ((0x00000001U << SERDES_L0_TM_AUX_0_BIT_2_SHIFT
18219                         |  0 ) & RegMask); */
18220                 PSU_Mask_Write (SERDES_L0_TM_AUX_0_OFFSET ,0x00000020U ,0x00000020U);
18221         /*############################################################################################################################ */
18222
18223                 /*Register : L2_TM_AUX_0 @ 0XFD4090CC</p>
18224
18225                 Spare- not used
18226                 PSU_SERDES_L2_TM_AUX_0_BIT_2                                                    1
18227
18228                 Spare registers
18229                 (OFFSET, MASK, VALUE)      (0XFD4090CC, 0x00000020U ,0x00000020U)
18230                 RegMask = (SERDES_L2_TM_AUX_0_BIT_2_MASK |  0 );
18231
18232                 RegVal = ((0x00000001U << SERDES_L2_TM_AUX_0_BIT_2_SHIFT
18233                         |  0 ) & RegMask); */
18234                 PSU_Mask_Write (SERDES_L2_TM_AUX_0_OFFSET ,0x00000020U ,0x00000020U);
18235         /*############################################################################################################################ */
18236
18237                 // : ENABLING EYE SURF
18238                 /*Register : L0_TM_DIG_8 @ 0XFD401074</p>
18239
18240                 Enable Eye Surf
18241                 PSU_SERDES_L0_TM_DIG_8_EYESURF_ENABLE                                           0x1
18242
18243                 Test modes for Elastic buffer and enabling Eye Surf
18244                 (OFFSET, MASK, VALUE)      (0XFD401074, 0x00000010U ,0x00000010U)
18245                 RegMask = (SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK |  0 );
18246
18247                 RegVal = ((0x00000001U << SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT
18248                         |  0 ) & RegMask); */
18249                 PSU_Mask_Write (SERDES_L0_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
18250         /*############################################################################################################################ */
18251
18252                 /*Register : L1_TM_DIG_8 @ 0XFD405074</p>
18253
18254                 Enable Eye Surf
18255                 PSU_SERDES_L1_TM_DIG_8_EYESURF_ENABLE                                           0x1
18256
18257                 Test modes for Elastic buffer and enabling Eye Surf
18258                 (OFFSET, MASK, VALUE)      (0XFD405074, 0x00000010U ,0x00000010U)
18259                 RegMask = (SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK |  0 );
18260
18261                 RegVal = ((0x00000001U << SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT
18262                         |  0 ) & RegMask); */
18263                 PSU_Mask_Write (SERDES_L1_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
18264         /*############################################################################################################################ */
18265
18266                 /*Register : L2_TM_DIG_8 @ 0XFD409074</p>
18267
18268                 Enable Eye Surf
18269                 PSU_SERDES_L2_TM_DIG_8_EYESURF_ENABLE                                           0x1
18270
18271                 Test modes for Elastic buffer and enabling Eye Surf
18272                 (OFFSET, MASK, VALUE)      (0XFD409074, 0x00000010U ,0x00000010U)
18273                 RegMask = (SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK |  0 );
18274
18275                 RegVal = ((0x00000001U << SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT
18276                         |  0 ) & RegMask); */
18277                 PSU_Mask_Write (SERDES_L2_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
18278         /*############################################################################################################################ */
18279
18280                 /*Register : L3_TM_DIG_8 @ 0XFD40D074</p>
18281
18282                 Enable Eye Surf
18283                 PSU_SERDES_L3_TM_DIG_8_EYESURF_ENABLE                                           0x1
18284
18285                 Test modes for Elastic buffer and enabling Eye Surf
18286                 (OFFSET, MASK, VALUE)      (0XFD40D074, 0x00000010U ,0x00000010U)
18287                 RegMask = (SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK |  0 );
18288
18289                 RegVal = ((0x00000001U << SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT
18290                         |  0 ) & RegMask); */
18291                 PSU_Mask_Write (SERDES_L3_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
18292         /*############################################################################################################################ */
18293
18294                 // : ILL SETTINGS FOR GAIN AND LOCK SETTINGS
18295                 /*Register : L0_TM_MISC2 @ 0XFD40189C</p>
18296
18297                 ILL calib counts BYPASSED with calcode bits
18298                 PSU_SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS                                    0x1
18299
18300                 sampler cal
18301                 (OFFSET, MASK, VALUE)      (0XFD40189C, 0x00000080U ,0x00000080U)
18302                 RegMask = (SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK |  0 );
18303
18304                 RegVal = ((0x00000001U << SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
18305                         |  0 ) & RegMask); */
18306                 PSU_Mask_Write (SERDES_L0_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U);
18307         /*############################################################################################################################ */
18308
18309                 /*Register : L0_TM_IQ_ILL1 @ 0XFD4018F8</p>
18310
18311                 IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
18312                 PSU_SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0                               0x64
18313
18314                 iqpi cal code
18315                 (OFFSET, MASK, VALUE)      (0XFD4018F8, 0x000000FFU ,0x00000064U)
18316                 RegMask = (SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK |  0 );
18317
18318                 RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
18319                         |  0 ) & RegMask); */
18320                 PSU_Mask_Write (SERDES_L0_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x00000064U);
18321         /*############################################################################################################################ */
18322
18323                 /*Register : L0_TM_IQ_ILL2 @ 0XFD4018FC</p>
18324
18325                 IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
18326                 PSU_SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1                               0x64
18327
18328                 iqpi cal code
18329                 (OFFSET, MASK, VALUE)      (0XFD4018FC, 0x000000FFU ,0x00000064U)
18330                 RegMask = (SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK |  0 );
18331
18332                 RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
18333                         |  0 ) & RegMask); */
18334                 PSU_Mask_Write (SERDES_L0_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x00000064U);
18335         /*############################################################################################################################ */
18336
18337                 /*Register : L0_TM_ILL12 @ 0XFD401990</p>
18338
18339                 G1A pll ctr bypass value
18340                 PSU_SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL                                      0x11
18341
18342                 ill pll counter values
18343                 (OFFSET, MASK, VALUE)      (0XFD401990, 0x000000FFU ,0x00000011U)
18344                 RegMask = (SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK |  0 );
18345
18346                 RegVal = ((0x00000011U << SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
18347                         |  0 ) & RegMask); */
18348                 PSU_Mask_Write (SERDES_L0_TM_ILL12_OFFSET ,0x000000FFU ,0x00000011U);
18349         /*############################################################################################################################ */
18350
18351                 /*Register : L0_TM_E_ILL1 @ 0XFD401924</p>
18352
18353                 E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
18354                 PSU_SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0                                 0x4
18355
18356                 epi cal code
18357                 (OFFSET, MASK, VALUE)      (0XFD401924, 0x000000FFU ,0x00000004U)
18358                 RegMask = (SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK |  0 );
18359
18360                 RegVal = ((0x00000004U << SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
18361                         |  0 ) & RegMask); */
18362                 PSU_Mask_Write (SERDES_L0_TM_E_ILL1_OFFSET ,0x000000FFU ,0x00000004U);
18363         /*############################################################################################################################ */
18364
18365                 /*Register : L0_TM_E_ILL2 @ 0XFD401928</p>
18366
18367                 E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
18368                 PSU_SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1                                 0xFE
18369
18370                 epi cal code
18371                 (OFFSET, MASK, VALUE)      (0XFD401928, 0x000000FFU ,0x000000FEU)
18372                 RegMask = (SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK |  0 );
18373
18374                 RegVal = ((0x000000FEU << SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
18375                         |  0 ) & RegMask); */
18376                 PSU_Mask_Write (SERDES_L0_TM_E_ILL2_OFFSET ,0x000000FFU ,0x000000FEU);
18377         /*############################################################################################################################ */
18378
18379                 /*Register : L0_TM_IQ_ILL3 @ 0XFD401900</p>
18380
18381                 IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
18382                 PSU_SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2                               0x64
18383
18384                 iqpi cal code
18385                 (OFFSET, MASK, VALUE)      (0XFD401900, 0x000000FFU ,0x00000064U)
18386                 RegMask = (SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK |  0 );
18387
18388                 RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
18389                         |  0 ) & RegMask); */
18390                 PSU_Mask_Write (SERDES_L0_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x00000064U);
18391         /*############################################################################################################################ */
18392
18393                 /*Register : L0_TM_E_ILL3 @ 0XFD40192C</p>
18394
18395                 E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
18396                 PSU_SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2                                 0x0
18397
18398                 epi cal code
18399                 (OFFSET, MASK, VALUE)      (0XFD40192C, 0x000000FFU ,0x00000000U)
18400                 RegMask = (SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK |  0 );
18401
18402                 RegVal = ((0x00000000U << SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
18403                         |  0 ) & RegMask); */
18404                 PSU_Mask_Write (SERDES_L0_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000000U);
18405         /*############################################################################################################################ */
18406
18407                 /*Register : L0_TM_ILL8 @ 0XFD401980</p>
18408
18409                 ILL calibration code change wait time
18410                 PSU_SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT                                         0xFF
18411
18412                 ILL cal routine control
18413                 (OFFSET, MASK, VALUE)      (0XFD401980, 0x000000FFU ,0x000000FFU)
18414                 RegMask = (SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK |  0 );
18415
18416                 RegVal = ((0x000000FFU << SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
18417                         |  0 ) & RegMask); */
18418                 PSU_Mask_Write (SERDES_L0_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU);
18419         /*############################################################################################################################ */
18420
18421                 /*Register : L0_TM_IQ_ILL8 @ 0XFD401914</p>
18422
18423                 IQ ILL polytrim bypass value
18424                 PSU_SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL                             0xF7
18425
18426                 iqpi polytrim
18427                 (OFFSET, MASK, VALUE)      (0XFD401914, 0x000000FFU ,0x000000F7U)
18428                 RegMask = (SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK |  0 );
18429
18430                 RegVal = ((0x000000F7U << SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
18431                         |  0 ) & RegMask); */
18432                 PSU_Mask_Write (SERDES_L0_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
18433         /*############################################################################################################################ */
18434
18435                 /*Register : L0_TM_IQ_ILL9 @ 0XFD401918</p>
18436
18437                 bypass IQ polytrim
18438                 PSU_SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM                                  0x1
18439
18440                 enables for lf,constant gm trim and polytirm
18441                 (OFFSET, MASK, VALUE)      (0XFD401918, 0x00000001U ,0x00000001U)
18442                 RegMask = (SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK |  0 );
18443
18444                 RegVal = ((0x00000001U << SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
18445                         |  0 ) & RegMask); */
18446                 PSU_Mask_Write (SERDES_L0_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U);
18447         /*############################################################################################################################ */
18448
18449                 /*Register : L0_TM_E_ILL8 @ 0XFD401940</p>
18450
18451                 E ILL polytrim bypass value
18452                 PSU_SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL                               0xF7
18453
18454                 epi polytrim
18455                 (OFFSET, MASK, VALUE)      (0XFD401940, 0x000000FFU ,0x000000F7U)
18456                 RegMask = (SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK |  0 );
18457
18458                 RegVal = ((0x000000F7U << SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
18459                         |  0 ) & RegMask); */
18460                 PSU_Mask_Write (SERDES_L0_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
18461         /*############################################################################################################################ */
18462
18463                 /*Register : L0_TM_E_ILL9 @ 0XFD401944</p>
18464
18465                 bypass E polytrim
18466                 PSU_SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM                                    0x1
18467
18468                 enables for lf,constant gm trim and polytirm
18469                 (OFFSET, MASK, VALUE)      (0XFD401944, 0x00000001U ,0x00000001U)
18470                 RegMask = (SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK |  0 );
18471
18472                 RegVal = ((0x00000001U << SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
18473                         |  0 ) & RegMask); */
18474                 PSU_Mask_Write (SERDES_L0_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U);
18475         /*############################################################################################################################ */
18476
18477                 /*Register : L2_TM_MISC2 @ 0XFD40989C</p>
18478
18479                 ILL calib counts BYPASSED with calcode bits
18480                 PSU_SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS                                    0x1
18481
18482                 sampler cal
18483                 (OFFSET, MASK, VALUE)      (0XFD40989C, 0x00000080U ,0x00000080U)
18484                 RegMask = (SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK |  0 );
18485
18486                 RegVal = ((0x00000001U << SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
18487                         |  0 ) & RegMask); */
18488                 PSU_Mask_Write (SERDES_L2_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U);
18489         /*############################################################################################################################ */
18490
18491                 /*Register : L2_TM_IQ_ILL1 @ 0XFD4098F8</p>
18492
18493                 IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
18494                 PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0                               0x1A
18495
18496                 iqpi cal code
18497                 (OFFSET, MASK, VALUE)      (0XFD4098F8, 0x000000FFU ,0x0000001AU)
18498                 RegMask = (SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK |  0 );
18499
18500                 RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
18501                         |  0 ) & RegMask); */
18502                 PSU_Mask_Write (SERDES_L2_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x0000001AU);
18503         /*############################################################################################################################ */
18504
18505                 /*Register : L2_TM_IQ_ILL2 @ 0XFD4098FC</p>
18506
18507                 IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
18508                 PSU_SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1                               0x1A
18509
18510                 iqpi cal code
18511                 (OFFSET, MASK, VALUE)      (0XFD4098FC, 0x000000FFU ,0x0000001AU)
18512                 RegMask = (SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK |  0 );
18513
18514                 RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
18515                         |  0 ) & RegMask); */
18516                 PSU_Mask_Write (SERDES_L2_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x0000001AU);
18517         /*############################################################################################################################ */
18518
18519                 /*Register : L2_TM_ILL12 @ 0XFD409990</p>
18520
18521                 G1A pll ctr bypass value
18522                 PSU_SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL                                      0x10
18523
18524                 ill pll counter values
18525                 (OFFSET, MASK, VALUE)      (0XFD409990, 0x000000FFU ,0x00000010U)
18526                 RegMask = (SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK |  0 );
18527
18528                 RegVal = ((0x00000010U << SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
18529                         |  0 ) & RegMask); */
18530                 PSU_Mask_Write (SERDES_L2_TM_ILL12_OFFSET ,0x000000FFU ,0x00000010U);
18531         /*############################################################################################################################ */
18532
18533                 /*Register : L2_TM_E_ILL1 @ 0XFD409924</p>
18534
18535                 E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
18536                 PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0                                 0xFE
18537
18538                 epi cal code
18539                 (OFFSET, MASK, VALUE)      (0XFD409924, 0x000000FFU ,0x000000FEU)
18540                 RegMask = (SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK |  0 );
18541
18542                 RegVal = ((0x000000FEU << SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
18543                         |  0 ) & RegMask); */
18544                 PSU_Mask_Write (SERDES_L2_TM_E_ILL1_OFFSET ,0x000000FFU ,0x000000FEU);
18545         /*############################################################################################################################ */
18546
18547                 /*Register : L2_TM_E_ILL2 @ 0XFD409928</p>
18548
18549                 E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
18550                 PSU_SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1                                 0x0
18551
18552                 epi cal code
18553                 (OFFSET, MASK, VALUE)      (0XFD409928, 0x000000FFU ,0x00000000U)
18554                 RegMask = (SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK |  0 );
18555
18556                 RegVal = ((0x00000000U << SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
18557                         |  0 ) & RegMask); */
18558                 PSU_Mask_Write (SERDES_L2_TM_E_ILL2_OFFSET ,0x000000FFU ,0x00000000U);
18559         /*############################################################################################################################ */
18560
18561                 /*Register : L2_TM_IQ_ILL3 @ 0XFD409900</p>
18562
18563                 IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
18564                 PSU_SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2                               0x1A
18565
18566                 iqpi cal code
18567                 (OFFSET, MASK, VALUE)      (0XFD409900, 0x000000FFU ,0x0000001AU)
18568                 RegMask = (SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK |  0 );
18569
18570                 RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
18571                         |  0 ) & RegMask); */
18572                 PSU_Mask_Write (SERDES_L2_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x0000001AU);
18573         /*############################################################################################################################ */
18574
18575                 /*Register : L2_TM_E_ILL3 @ 0XFD40992C</p>
18576
18577                 E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
18578                 PSU_SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2                                 0x0
18579
18580                 epi cal code
18581                 (OFFSET, MASK, VALUE)      (0XFD40992C, 0x000000FFU ,0x00000000U)
18582                 RegMask = (SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK |  0 );
18583
18584                 RegVal = ((0x00000000U << SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
18585                         |  0 ) & RegMask); */
18586                 PSU_Mask_Write (SERDES_L2_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000000U);
18587         /*############################################################################################################################ */
18588
18589                 /*Register : L2_TM_ILL8 @ 0XFD409980</p>
18590
18591                 ILL calibration code change wait time
18592                 PSU_SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT                                         0xFF
18593
18594                 ILL cal routine control
18595                 (OFFSET, MASK, VALUE)      (0XFD409980, 0x000000FFU ,0x000000FFU)
18596                 RegMask = (SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK |  0 );
18597
18598                 RegVal = ((0x000000FFU << SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
18599                         |  0 ) & RegMask); */
18600                 PSU_Mask_Write (SERDES_L2_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU);
18601         /*############################################################################################################################ */
18602
18603                 /*Register : L2_TM_IQ_ILL8 @ 0XFD409914</p>
18604
18605                 IQ ILL polytrim bypass value
18606                 PSU_SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL                             0xF7
18607
18608                 iqpi polytrim
18609                 (OFFSET, MASK, VALUE)      (0XFD409914, 0x000000FFU ,0x000000F7U)
18610                 RegMask = (SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK |  0 );
18611
18612                 RegVal = ((0x000000F7U << SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
18613                         |  0 ) & RegMask); */
18614                 PSU_Mask_Write (SERDES_L2_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
18615         /*############################################################################################################################ */
18616
18617                 /*Register : L2_TM_IQ_ILL9 @ 0XFD409918</p>
18618
18619                 bypass IQ polytrim
18620                 PSU_SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM                                  0x1
18621
18622                 enables for lf,constant gm trim and polytirm
18623                 (OFFSET, MASK, VALUE)      (0XFD409918, 0x00000001U ,0x00000001U)
18624                 RegMask = (SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK |  0 );
18625
18626                 RegVal = ((0x00000001U << SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
18627                         |  0 ) & RegMask); */
18628                 PSU_Mask_Write (SERDES_L2_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U);
18629         /*############################################################################################################################ */
18630
18631                 /*Register : L2_TM_E_ILL8 @ 0XFD409940</p>
18632
18633                 E ILL polytrim bypass value
18634                 PSU_SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL                               0xF7
18635
18636                 epi polytrim
18637                 (OFFSET, MASK, VALUE)      (0XFD409940, 0x000000FFU ,0x000000F7U)
18638                 RegMask = (SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK |  0 );
18639
18640                 RegVal = ((0x000000F7U << SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
18641                         |  0 ) & RegMask); */
18642                 PSU_Mask_Write (SERDES_L2_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
18643         /*############################################################################################################################ */
18644
18645                 /*Register : L2_TM_E_ILL9 @ 0XFD409944</p>
18646
18647                 bypass E polytrim
18648                 PSU_SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM                                    0x1
18649
18650                 enables for lf,constant gm trim and polytirm
18651                 (OFFSET, MASK, VALUE)      (0XFD409944, 0x00000001U ,0x00000001U)
18652                 RegMask = (SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK |  0 );
18653
18654                 RegVal = ((0x00000001U << SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
18655                         |  0 ) & RegMask); */
18656                 PSU_Mask_Write (SERDES_L2_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U);
18657         /*############################################################################################################################ */
18658
18659                 /*Register : L3_TM_MISC2 @ 0XFD40D89C</p>
18660
18661                 ILL calib counts BYPASSED with calcode bits
18662                 PSU_SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS                                    0x1
18663
18664                 sampler cal
18665                 (OFFSET, MASK, VALUE)      (0XFD40D89C, 0x00000080U ,0x00000080U)
18666                 RegMask = (SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK |  0 );
18667
18668                 RegVal = ((0x00000001U << SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
18669                         |  0 ) & RegMask); */
18670                 PSU_Mask_Write (SERDES_L3_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U);
18671         /*############################################################################################################################ */
18672
18673                 /*Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8</p>
18674
18675                 IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
18676                 PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0                               0x7D
18677
18678                 iqpi cal code
18679                 (OFFSET, MASK, VALUE)      (0XFD40D8F8, 0x000000FFU ,0x0000007DU)
18680                 RegMask = (SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK |  0 );
18681
18682                 RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
18683                         |  0 ) & RegMask); */
18684                 PSU_Mask_Write (SERDES_L3_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x0000007DU);
18685         /*############################################################################################################################ */
18686
18687                 /*Register : L3_TM_IQ_ILL2 @ 0XFD40D8FC</p>
18688
18689                 IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
18690                 PSU_SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1                               0x7D
18691
18692                 iqpi cal code
18693                 (OFFSET, MASK, VALUE)      (0XFD40D8FC, 0x000000FFU ,0x0000007DU)
18694                 RegMask = (SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK |  0 );
18695
18696                 RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
18697                         |  0 ) & RegMask); */
18698                 PSU_Mask_Write (SERDES_L3_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x0000007DU);
18699         /*############################################################################################################################ */
18700
18701                 /*Register : L3_TM_ILL12 @ 0XFD40D990</p>
18702
18703                 G1A pll ctr bypass value
18704                 PSU_SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL                                      0x1
18705
18706                 ill pll counter values
18707                 (OFFSET, MASK, VALUE)      (0XFD40D990, 0x000000FFU ,0x00000001U)
18708                 RegMask = (SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK |  0 );
18709
18710                 RegVal = ((0x00000001U << SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
18711                         |  0 ) & RegMask); */
18712                 PSU_Mask_Write (SERDES_L3_TM_ILL12_OFFSET ,0x000000FFU ,0x00000001U);
18713         /*############################################################################################################################ */
18714
18715                 /*Register : L3_TM_E_ILL1 @ 0XFD40D924</p>
18716
18717                 E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
18718                 PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0                                 0x9C
18719
18720                 epi cal code
18721                 (OFFSET, MASK, VALUE)      (0XFD40D924, 0x000000FFU ,0x0000009CU)
18722                 RegMask = (SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK |  0 );
18723
18724                 RegVal = ((0x0000009CU << SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
18725                         |  0 ) & RegMask); */
18726                 PSU_Mask_Write (SERDES_L3_TM_E_ILL1_OFFSET ,0x000000FFU ,0x0000009CU);
18727         /*############################################################################################################################ */
18728
18729                 /*Register : L3_TM_E_ILL2 @ 0XFD40D928</p>
18730
18731                 E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
18732                 PSU_SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1                                 0x39
18733
18734                 epi cal code
18735                 (OFFSET, MASK, VALUE)      (0XFD40D928, 0x000000FFU ,0x00000039U)
18736                 RegMask = (SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK |  0 );
18737
18738                 RegVal = ((0x00000039U << SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
18739                         |  0 ) & RegMask); */
18740                 PSU_Mask_Write (SERDES_L3_TM_E_ILL2_OFFSET ,0x000000FFU ,0x00000039U);
18741         /*############################################################################################################################ */
18742
18743                 /*Register : L3_TM_ILL11 @ 0XFD40D98C</p>
18744
18745                 G2A_PCIe1 PLL ctr bypass value
18746                 PSU_SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL                          0x2
18747
18748                 ill pll counter values
18749                 (OFFSET, MASK, VALUE)      (0XFD40D98C, 0x000000F0U ,0x00000020U)
18750                 RegMask = (SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK |  0 );
18751
18752                 RegVal = ((0x00000002U << SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT
18753                         |  0 ) & RegMask); */
18754                 PSU_Mask_Write (SERDES_L3_TM_ILL11_OFFSET ,0x000000F0U ,0x00000020U);
18755         /*############################################################################################################################ */
18756
18757                 /*Register : L3_TM_IQ_ILL3 @ 0XFD40D900</p>
18758
18759                 IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
18760                 PSU_SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2                               0x7D
18761
18762                 iqpi cal code
18763                 (OFFSET, MASK, VALUE)      (0XFD40D900, 0x000000FFU ,0x0000007DU)
18764                 RegMask = (SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK |  0 );
18765
18766                 RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
18767                         |  0 ) & RegMask); */
18768                 PSU_Mask_Write (SERDES_L3_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x0000007DU);
18769         /*############################################################################################################################ */
18770
18771                 /*Register : L3_TM_E_ILL3 @ 0XFD40D92C</p>
18772
18773                 E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
18774                 PSU_SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2                                 0x64
18775
18776                 epi cal code
18777                 (OFFSET, MASK, VALUE)      (0XFD40D92C, 0x000000FFU ,0x00000064U)
18778                 RegMask = (SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK |  0 );
18779
18780                 RegVal = ((0x00000064U << SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
18781                         |  0 ) & RegMask); */
18782                 PSU_Mask_Write (SERDES_L3_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000064U);
18783         /*############################################################################################################################ */
18784
18785                 /*Register : L3_TM_ILL8 @ 0XFD40D980</p>
18786
18787                 ILL calibration code change wait time
18788                 PSU_SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT                                         0xFF
18789
18790                 ILL cal routine control
18791                 (OFFSET, MASK, VALUE)      (0XFD40D980, 0x000000FFU ,0x000000FFU)
18792                 RegMask = (SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK |  0 );
18793
18794                 RegVal = ((0x000000FFU << SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
18795                         |  0 ) & RegMask); */
18796                 PSU_Mask_Write (SERDES_L3_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU);
18797         /*############################################################################################################################ */
18798
18799                 /*Register : L3_TM_IQ_ILL8 @ 0XFD40D914</p>
18800
18801                 IQ ILL polytrim bypass value
18802                 PSU_SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL                             0xF7
18803
18804                 iqpi polytrim
18805                 (OFFSET, MASK, VALUE)      (0XFD40D914, 0x000000FFU ,0x000000F7U)
18806                 RegMask = (SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK |  0 );
18807
18808                 RegVal = ((0x000000F7U << SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
18809                         |  0 ) & RegMask); */
18810                 PSU_Mask_Write (SERDES_L3_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
18811         /*############################################################################################################################ */
18812
18813                 /*Register : L3_TM_IQ_ILL9 @ 0XFD40D918</p>
18814
18815                 bypass IQ polytrim
18816                 PSU_SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM                                  0x1
18817
18818                 enables for lf,constant gm trim and polytirm
18819                 (OFFSET, MASK, VALUE)      (0XFD40D918, 0x00000001U ,0x00000001U)
18820                 RegMask = (SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK |  0 );
18821
18822                 RegVal = ((0x00000001U << SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
18823                         |  0 ) & RegMask); */
18824                 PSU_Mask_Write (SERDES_L3_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U);
18825         /*############################################################################################################################ */
18826
18827                 /*Register : L3_TM_E_ILL8 @ 0XFD40D940</p>
18828
18829                 E ILL polytrim bypass value
18830                 PSU_SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL                               0xF7
18831
18832                 epi polytrim
18833                 (OFFSET, MASK, VALUE)      (0XFD40D940, 0x000000FFU ,0x000000F7U)
18834                 RegMask = (SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK |  0 );
18835
18836                 RegVal = ((0x000000F7U << SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
18837                         |  0 ) & RegMask); */
18838                 PSU_Mask_Write (SERDES_L3_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
18839         /*############################################################################################################################ */
18840
18841                 /*Register : L3_TM_E_ILL9 @ 0XFD40D944</p>
18842
18843                 bypass E polytrim
18844                 PSU_SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM                                    0x1
18845
18846                 enables for lf,constant gm trim and polytirm
18847                 (OFFSET, MASK, VALUE)      (0XFD40D944, 0x00000001U ,0x00000001U)
18848                 RegMask = (SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK |  0 );
18849
18850                 RegVal = ((0x00000001U << SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
18851                         |  0 ) & RegMask); */
18852                 PSU_Mask_Write (SERDES_L3_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U);
18853         /*############################################################################################################################ */
18854
18855                 // : SYMBOL LOCK AND WAIT
18856                 /*Register : L0_TM_DIG_21 @ 0XFD4010A8</p>
18857
18858                 pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20
18859                 PSU_SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH                                   0x11
18860
18861                 Control symbol alignment locking - wait counts
18862                 (OFFSET, MASK, VALUE)      (0XFD4010A8, 0x00000003U ,0x00000003U)
18863                 RegMask = (SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK |  0 );
18864
18865                 RegVal = ((0x00000011U << SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT
18866                         |  0 ) & RegMask); */
18867                 PSU_Mask_Write (SERDES_L0_TM_DIG_21_OFFSET ,0x00000003U ,0x00000003U);
18868         /*############################################################################################################################ */
18869
18870                 /*Register : L0_TM_DIG_10 @ 0XFD40107C</p>
18871
18872                 CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
18873                 PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME                                       0xF
18874
18875                 test control for changing cdr lock wait time
18876                 (OFFSET, MASK, VALUE)      (0XFD40107C, 0x0000000FU ,0x0000000FU)
18877                 RegMask = (SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK |  0 );
18878
18879                 RegVal = ((0x0000000FU << SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
18880                         |  0 ) & RegMask); */
18881                 PSU_Mask_Write (SERDES_L0_TM_DIG_10_OFFSET ,0x0000000FU ,0x0000000FU);
18882         /*############################################################################################################################ */
18883
18884                 // : SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG
18885                 /*Register : L0_TM_RST_DLY @ 0XFD4019A4</p>
18886
18887                 Delay apb reset by specified amount
18888                 PSU_SERDES_L0_TM_RST_DLY_APB_RST_DLY                                            0xFF
18889
18890                 reset delay for apb reset w.r.t pso of hsrx
18891                 (OFFSET, MASK, VALUE)      (0XFD4019A4, 0x000000FFU ,0x000000FFU)
18892                 RegMask = (SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK |  0 );
18893
18894                 RegVal = ((0x000000FFU << SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT
18895                         |  0 ) & RegMask); */
18896                 PSU_Mask_Write (SERDES_L0_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
18897         /*############################################################################################################################ */
18898
18899                 /*Register : L0_TM_ANA_BYP_15 @ 0XFD401038</p>
18900
18901                 Enable Bypass for <7> of TM_ANA_BYPS_15
18902                 PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE                       0x1
18903
18904                 Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
18905                 (OFFSET, MASK, VALUE)      (0XFD401038, 0x00000040U ,0x00000040U)
18906                 RegMask = (SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK |  0 );
18907
18908                 RegVal = ((0x00000001U << SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
18909                         |  0 ) & RegMask); */
18910                 PSU_Mask_Write (SERDES_L0_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
18911         /*############################################################################################################################ */
18912
18913                 /*Register : L0_TM_ANA_BYP_12 @ 0XFD40102C</p>
18914
18915                 Enable Bypass for <7> of TM_ANA_BYPS_12
18916                 PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG                              0x1
18917
18918                 Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
18919                 (OFFSET, MASK, VALUE)      (0XFD40102C, 0x00000040U ,0x00000040U)
18920                 RegMask = (SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK |  0 );
18921
18922                 RegVal = ((0x00000001U << SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
18923                         |  0 ) & RegMask); */
18924                 PSU_Mask_Write (SERDES_L0_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U);
18925         /*############################################################################################################################ */
18926
18927                 /*Register : L1_TM_RST_DLY @ 0XFD4059A4</p>
18928
18929                 Delay apb reset by specified amount
18930                 PSU_SERDES_L1_TM_RST_DLY_APB_RST_DLY                                            0xFF
18931
18932                 reset delay for apb reset w.r.t pso of hsrx
18933                 (OFFSET, MASK, VALUE)      (0XFD4059A4, 0x000000FFU ,0x000000FFU)
18934                 RegMask = (SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK |  0 );
18935
18936                 RegVal = ((0x000000FFU << SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT
18937                         |  0 ) & RegMask); */
18938                 PSU_Mask_Write (SERDES_L1_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
18939         /*############################################################################################################################ */
18940
18941                 /*Register : L1_TM_ANA_BYP_15 @ 0XFD405038</p>
18942
18943                 Enable Bypass for <7> of TM_ANA_BYPS_15
18944                 PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE                       0x1
18945
18946                 Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
18947                 (OFFSET, MASK, VALUE)      (0XFD405038, 0x00000040U ,0x00000040U)
18948                 RegMask = (SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK |  0 );
18949
18950                 RegVal = ((0x00000001U << SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
18951                         |  0 ) & RegMask); */
18952                 PSU_Mask_Write (SERDES_L1_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
18953         /*############################################################################################################################ */
18954
18955                 /*Register : L1_TM_ANA_BYP_12 @ 0XFD40502C</p>
18956
18957                 Enable Bypass for <7> of TM_ANA_BYPS_12
18958                 PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG                              0x1
18959
18960                 Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
18961                 (OFFSET, MASK, VALUE)      (0XFD40502C, 0x00000040U ,0x00000040U)
18962                 RegMask = (SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK |  0 );
18963
18964                 RegVal = ((0x00000001U << SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
18965                         |  0 ) & RegMask); */
18966                 PSU_Mask_Write (SERDES_L1_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U);
18967         /*############################################################################################################################ */
18968
18969                 /*Register : L2_TM_RST_DLY @ 0XFD4099A4</p>
18970
18971                 Delay apb reset by specified amount
18972                 PSU_SERDES_L2_TM_RST_DLY_APB_RST_DLY                                            0xFF
18973
18974                 reset delay for apb reset w.r.t pso of hsrx
18975                 (OFFSET, MASK, VALUE)      (0XFD4099A4, 0x000000FFU ,0x000000FFU)
18976                 RegMask = (SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK |  0 );
18977
18978                 RegVal = ((0x000000FFU << SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT
18979                         |  0 ) & RegMask); */
18980                 PSU_Mask_Write (SERDES_L2_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
18981         /*############################################################################################################################ */
18982
18983                 /*Register : L2_TM_ANA_BYP_15 @ 0XFD409038</p>
18984
18985                 Enable Bypass for <7> of TM_ANA_BYPS_15
18986                 PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE                       0x1
18987
18988                 Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
18989                 (OFFSET, MASK, VALUE)      (0XFD409038, 0x00000040U ,0x00000040U)
18990                 RegMask = (SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK |  0 );
18991
18992                 RegVal = ((0x00000001U << SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
18993                         |  0 ) & RegMask); */
18994                 PSU_Mask_Write (SERDES_L2_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
18995         /*############################################################################################################################ */
18996
18997                 /*Register : L2_TM_ANA_BYP_12 @ 0XFD40902C</p>
18998
18999                 Enable Bypass for <7> of TM_ANA_BYPS_12
19000                 PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG                              0x1
19001
19002                 Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
19003                 (OFFSET, MASK, VALUE)      (0XFD40902C, 0x00000040U ,0x00000040U)
19004                 RegMask = (SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK |  0 );
19005
19006                 RegVal = ((0x00000001U << SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
19007                         |  0 ) & RegMask); */
19008                 PSU_Mask_Write (SERDES_L2_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U);
19009         /*############################################################################################################################ */
19010
19011                 /*Register : L3_TM_RST_DLY @ 0XFD40D9A4</p>
19012
19013                 Delay apb reset by specified amount
19014                 PSU_SERDES_L3_TM_RST_DLY_APB_RST_DLY                                            0xFF
19015
19016                 reset delay for apb reset w.r.t pso of hsrx
19017                 (OFFSET, MASK, VALUE)      (0XFD40D9A4, 0x000000FFU ,0x000000FFU)
19018                 RegMask = (SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK |  0 );
19019
19020                 RegVal = ((0x000000FFU << SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT
19021                         |  0 ) & RegMask); */
19022                 PSU_Mask_Write (SERDES_L3_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
19023         /*############################################################################################################################ */
19024
19025                 /*Register : L3_TM_ANA_BYP_15 @ 0XFD40D038</p>
19026
19027                 Enable Bypass for <7> of TM_ANA_BYPS_15
19028                 PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE                       0x1
19029
19030                 Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
19031                 (OFFSET, MASK, VALUE)      (0XFD40D038, 0x00000040U ,0x00000040U)
19032                 RegMask = (SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK |  0 );
19033
19034                 RegVal = ((0x00000001U << SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
19035                         |  0 ) & RegMask); */
19036                 PSU_Mask_Write (SERDES_L3_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
19037         /*############################################################################################################################ */
19038
19039                 /*Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C</p>
19040
19041                 Enable Bypass for <7> of TM_ANA_BYPS_12
19042                 PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG                              0x1
19043
19044                 Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
19045                 (OFFSET, MASK, VALUE)      (0XFD40D02C, 0x00000040U ,0x00000040U)
19046                 RegMask = (SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK |  0 );
19047
19048                 RegVal = ((0x00000001U << SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
19049                         |  0 ) & RegMask); */
19050                 PSU_Mask_Write (SERDES_L3_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U);
19051         /*############################################################################################################################ */
19052
19053                 // : GT LANE SETTINGS
19054                 /*Register : ICM_CFG0 @ 0XFD410010</p>
19055
19056                 Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse
19057                 , 7 - Unused
19058                 PSU_SERDES_ICM_CFG0_L0_ICM_CFG                                                  1
19059
19060                 Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused
19061                  7 - Unused
19062                 PSU_SERDES_ICM_CFG0_L1_ICM_CFG                                                  4
19063
19064                 ICM Configuration Register 0
19065                 (OFFSET, MASK, VALUE)      (0XFD410010, 0x00000077U ,0x00000041U)
19066                 RegMask = (SERDES_ICM_CFG0_L0_ICM_CFG_MASK | SERDES_ICM_CFG0_L1_ICM_CFG_MASK |  0 );
19067
19068                 RegVal = ((0x00000001U << SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT
19069                         | 0x00000004U << SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT
19070                         |  0 ) & RegMask); */
19071                 PSU_Mask_Write (SERDES_ICM_CFG0_OFFSET ,0x00000077U ,0x00000041U);
19072         /*############################################################################################################################ */
19073
19074                 /*Register : ICM_CFG1 @ 0XFD410014</p>
19075
19076                 Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused
19077                  7 - Unused
19078                 PSU_SERDES_ICM_CFG1_L2_ICM_CFG                                                  3
19079
19080                 Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused
19081                  7 - Unused
19082                 PSU_SERDES_ICM_CFG1_L3_ICM_CFG                                                  2
19083
19084                 ICM Configuration Register 1
19085                 (OFFSET, MASK, VALUE)      (0XFD410014, 0x00000077U ,0x00000023U)
19086                 RegMask = (SERDES_ICM_CFG1_L2_ICM_CFG_MASK | SERDES_ICM_CFG1_L3_ICM_CFG_MASK |  0 );
19087
19088                 RegVal = ((0x00000003U << SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT
19089                         | 0x00000002U << SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT
19090                         |  0 ) & RegMask); */
19091                 PSU_Mask_Write (SERDES_ICM_CFG1_OFFSET ,0x00000077U ,0x00000023U);
19092         /*############################################################################################################################ */
19093
19094                 // : CHECKING PLL LOCK
19095                 // : ENABLE SERIAL DATA MUX DEEMPH
19096                 /*Register : L1_TXPMD_TM_45 @ 0XFD404CB4</p>
19097
19098                 Enable/disable DP post2 path
19099                 PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH                         0x1
19100
19101                 Override enable/disable of DP post2 path
19102                 PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH                    0x1
19103
19104                 Override enable/disable of DP post1 path
19105                 PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH                    0x1
19106
19107                 Enable/disable DP main path
19108                 PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH                          0x1
19109
19110                 Override enable/disable of DP main path
19111                 PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH                     0x1
19112
19113                 Post or pre or main DP path selection
19114                 (OFFSET, MASK, VALUE)      (0XFD404CB4, 0x00000037U ,0x00000037U)
19115                 RegMask = (SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK |  0 );
19116
19117                 RegVal = ((0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
19118                         | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT
19119                         | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT
19120                         | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT
19121                         | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT
19122                         |  0 ) & RegMask); */
19123                 PSU_Mask_Write (SERDES_L1_TXPMD_TM_45_OFFSET ,0x00000037U ,0x00000037U);
19124         /*############################################################################################################################ */
19125
19126                 /*Register : L1_TX_ANA_TM_118 @ 0XFD4041D8</p>
19127
19128                 Test register force for enabling/disablign TX deemphasis bits <17:0>
19129                 PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0                                0x1
19130
19131                 Enable Override of TX deemphasis
19132                 (OFFSET, MASK, VALUE)      (0XFD4041D8, 0x00000001U ,0x00000001U)
19133                 RegMask = (SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK |  0 );
19134
19135                 RegVal = ((0x00000001U << SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
19136                         |  0 ) & RegMask); */
19137                 PSU_Mask_Write (SERDES_L1_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U);
19138         /*############################################################################################################################ */
19139
19140                 /*Register : L3_TX_ANA_TM_118 @ 0XFD40C1D8</p>
19141
19142                 Test register force for enabling/disablign TX deemphasis bits <17:0>
19143                 PSU_SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0                                0x1
19144
19145                 Enable Override of TX deemphasis
19146                 (OFFSET, MASK, VALUE)      (0XFD40C1D8, 0x00000001U ,0x00000001U)
19147                 RegMask = (SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK |  0 );
19148
19149                 RegVal = ((0x00000001U << SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
19150                         |  0 ) & RegMask); */
19151                 PSU_Mask_Write (SERDES_L3_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U);
19152         /*############################################################################################################################ */
19153
19154                 // : CDR AND RX EQUALIZATION SETTINGS
19155                 /*Register : L3_TM_CDR5 @ 0XFD40DC14</p>
19156
19157                 FPHL FSM accumulate cycles
19158                 PSU_SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES                                       0x7
19159
19160                 FFL Phase0 int gain aka 2ol SD update rate
19161                 PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN                                          0x6
19162
19163                 Fast phase lock controls -- FSM accumulator cycle control and phase 0 int gain control.
19164                 (OFFSET, MASK, VALUE)      (0XFD40DC14, 0x000000FFU ,0x000000E6U)
19165                 RegMask = (SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK | SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK |  0 );
19166
19167                 RegVal = ((0x00000007U << SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT
19168                         | 0x00000006U << SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT
19169                         |  0 ) & RegMask); */
19170                 PSU_Mask_Write (SERDES_L3_TM_CDR5_OFFSET ,0x000000FFU ,0x000000E6U);
19171         /*############################################################################################################################ */
19172
19173                 /*Register : L3_TM_CDR16 @ 0XFD40DC40</p>
19174
19175                 FFL Phase0 prop gain aka 1ol SD update rate
19176                 PSU_SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN                                        0xC
19177
19178                 Fast phase lock controls -- phase 0 prop gain
19179                 (OFFSET, MASK, VALUE)      (0XFD40DC40, 0x0000001FU ,0x0000000CU)
19180                 RegMask = (SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK |  0 );
19181
19182                 RegVal = ((0x0000000CU << SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT
19183                         |  0 ) & RegMask); */
19184                 PSU_Mask_Write (SERDES_L3_TM_CDR16_OFFSET ,0x0000001FU ,0x0000000CU);
19185         /*############################################################################################################################ */
19186
19187                 /*Register : L3_TM_EQ0 @ 0XFD40D94C</p>
19188
19189                 EQ stg 2 controls BYPASSED
19190                 PSU_SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP                                           1
19191
19192                 eq stg1 and stg2 controls
19193                 (OFFSET, MASK, VALUE)      (0XFD40D94C, 0x00000020U ,0x00000020U)
19194                 RegMask = (SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK |  0 );
19195
19196                 RegVal = ((0x00000001U << SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT
19197                         |  0 ) & RegMask); */
19198                 PSU_Mask_Write (SERDES_L3_TM_EQ0_OFFSET ,0x00000020U ,0x00000020U);
19199         /*############################################################################################################################ */
19200
19201                 /*Register : L3_TM_EQ1 @ 0XFD40D950</p>
19202
19203                 EQ STG2 RL PROG
19204                 PSU_SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG                                            0x2
19205
19206                 EQ stg 2 preamp mode val
19207                 PSU_SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL                                    0x1
19208
19209                 eq stg1 and stg2 controls
19210                 (OFFSET, MASK, VALUE)      (0XFD40D950, 0x00000007U ,0x00000006U)
19211                 RegMask = (SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK | SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK |  0 );
19212
19213                 RegVal = ((0x00000002U << SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT
19214                         | 0x00000001U << SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT
19215                         |  0 ) & RegMask); */
19216                 PSU_Mask_Write (SERDES_L3_TM_EQ1_OFFSET ,0x00000007U ,0x00000006U);
19217         /*############################################################################################################################ */
19218
19219                 // : GEM SERDES SETTINGS
19220                 // : ENABLE PRE EMPHAIS AND VOLTAGE SWING
19221                 /*Register : L1_TXPMD_TM_48 @ 0XFD404CC0</p>
19222
19223                 Margining factor value
19224                 PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR                         0
19225
19226                 Margining factor
19227                 (OFFSET, MASK, VALUE)      (0XFD404CC0, 0x0000001FU ,0x00000000U)
19228                 RegMask = (SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK |  0 );
19229
19230                 RegVal = ((0x00000000U << SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT
19231                         |  0 ) & RegMask); */
19232                 PSU_Mask_Write (SERDES_L1_TXPMD_TM_48_OFFSET ,0x0000001FU ,0x00000000U);
19233         /*############################################################################################################################ */
19234
19235                 /*Register : L1_TX_ANA_TM_18 @ 0XFD404048</p>
19236
19237                 pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved
19238                 PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0                                   0
19239
19240                 Override for PIPE TX de-emphasis
19241                 (OFFSET, MASK, VALUE)      (0XFD404048, 0x000000FFU ,0x00000000U)
19242                 RegMask = (SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK |  0 );
19243
19244                 RegVal = ((0x00000000U << SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
19245                         |  0 ) & RegMask); */
19246                 PSU_Mask_Write (SERDES_L1_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000000U);
19247         /*############################################################################################################################ */
19248
19249                 /*Register : L3_TX_ANA_TM_18 @ 0XFD40C048</p>
19250
19251                 pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved
19252                 PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0                                   0x1
19253
19254                 Override for PIPE TX de-emphasis
19255                 (OFFSET, MASK, VALUE)      (0XFD40C048, 0x000000FFU ,0x00000001U)
19256                 RegMask = (SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK |  0 );
19257
19258                 RegVal = ((0x00000001U << SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
19259                         |  0 ) & RegMask); */
19260                 PSU_Mask_Write (SERDES_L3_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000001U);
19261         /*############################################################################################################################ */
19262
19263
19264   return 1;
19265 }
19266 unsigned long psu_resetout_init_data() {
19267                 // : TAKING SERDES PERIPHERAL OUT OF RESET RESET
19268                 // : PUTTING USB0 IN RESET
19269                 /*Register : RST_LPD_TOP @ 0XFF5E023C</p>
19270
19271                 USB 0 reset for control registers
19272                 PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET                                          0X0
19273
19274                 Software control register for the LPD block.
19275                 (OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000400U ,0x00000000U)
19276                 RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK |  0 );
19277
19278                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
19279                         |  0 ) & RegMask); */
19280                 PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000400U ,0x00000000U);
19281         /*############################################################################################################################ */
19282
19283                 // : USB0 PIPE POWER PRESENT
19284                 /*Register : fpd_power_prsnt @ 0XFF9D0080</p>
19285
19286                 This bit is used to choose between PIPE power present and 1'b1
19287                 PSU_USB3_0_FPD_POWER_PRSNT_OPTION                                               0X1
19288
19289                 fpd_power_prsnt
19290                 (OFFSET, MASK, VALUE)      (0XFF9D0080, 0x00000001U ,0x00000001U)
19291                 RegMask = (USB3_0_FPD_POWER_PRSNT_OPTION_MASK |  0 );
19292
19293                 RegVal = ((0x00000001U << USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT
19294                         |  0 ) & RegMask); */
19295                 PSU_Mask_Write (USB3_0_FPD_POWER_PRSNT_OFFSET ,0x00000001U ,0x00000001U);
19296         /*############################################################################################################################ */
19297
19298                 /*Register : fpd_pipe_clk @ 0XFF9D007C</p>
19299
19300                 This bit is used to choose between PIPE clock coming from SerDes and the suspend clk
19301                 PSU_USB3_0_FPD_PIPE_CLK_OPTION                                                  0x0
19302
19303                 fpd_pipe_clk
19304                 (OFFSET, MASK, VALUE)      (0XFF9D007C, 0x00000001U ,0x00000000U)
19305                 RegMask = (USB3_0_FPD_PIPE_CLK_OPTION_MASK |  0 );
19306
19307                 RegVal = ((0x00000000U << USB3_0_FPD_PIPE_CLK_OPTION_SHIFT
19308                         |  0 ) & RegMask); */
19309                 PSU_Mask_Write (USB3_0_FPD_PIPE_CLK_OFFSET ,0x00000001U ,0x00000000U);
19310         /*############################################################################################################################ */
19311
19312                 // :
19313                 /*Register : RST_LPD_TOP @ 0XFF5E023C</p>
19314
19315                 USB 0 sleep circuit reset
19316                 PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET                                         0X0
19317
19318                 USB 0 reset
19319                 PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET                                          0X0
19320
19321                 Software control register for the LPD block.
19322                 (OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000140U ,0x00000000U)
19323                 RegMask = (CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK |  0 );
19324
19325                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
19326                         | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
19327                         |  0 ) & RegMask); */
19328                 PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000140U ,0x00000000U);
19329         /*############################################################################################################################ */
19330
19331                 // : PUTTING GEM0 IN RESET
19332                 /*Register : RST_LPD_IOU0 @ 0XFF5E0230</p>
19333
19334                 GEM 3 reset
19335                 PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET                                             0X0
19336
19337                 Software controlled reset for the GEMs
19338                 (OFFSET, MASK, VALUE)      (0XFF5E0230, 0x00000008U ,0x00000000U)
19339                 RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK |  0 );
19340
19341                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
19342                         |  0 ) & RegMask); */
19343                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000000U);
19344         /*############################################################################################################################ */
19345
19346                 // : PUTTING SATA IN RESET
19347                 /*Register : sata_misc_ctrl @ 0XFD3D0100</p>
19348
19349                 Sata PM clock control select
19350                 PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL                                         0x3
19351
19352                 Misc Contorls for SATA.This register may only be modified during bootup (while SATA block is disabled)
19353                 (OFFSET, MASK, VALUE)      (0XFD3D0100, 0x00000003U ,0x00000003U)
19354                 RegMask = (SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK |  0 );
19355
19356                 RegVal = ((0x00000003U << SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT
19357                         |  0 ) & RegMask); */
19358                 PSU_Mask_Write (SIOU_SATA_MISC_CTRL_OFFSET ,0x00000003U ,0x00000003U);
19359         /*############################################################################################################################ */
19360
19361                 /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
19362
19363                 Sata block level reset
19364                 PSU_CRF_APB_RST_FPD_TOP_SATA_RESET                                              0X0
19365
19366                 FPD Block level software controlled reset
19367                 (OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00000002U ,0x00000000U)
19368                 RegMask = (CRF_APB_RST_FPD_TOP_SATA_RESET_MASK |  0 );
19369
19370                 RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
19371                         |  0 ) & RegMask); */
19372                 PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000000U);
19373         /*############################################################################################################################ */
19374
19375                 // : PUTTING PCIE CFG AND BRIDGE IN RESET
19376                 /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
19377
19378                 PCIE config reset
19379                 PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET                                          0X0
19380
19381                 PCIE bridge block level reset (AXI interface)
19382                 PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET                                       0X0
19383
19384                 FPD Block level software controlled reset
19385                 (OFFSET, MASK, VALUE)      (0XFD1A0100, 0x000C0000U ,0x00000000U)
19386                 RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK |  0 );
19387
19388                 RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
19389                         | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
19390                         |  0 ) & RegMask); */
19391                 PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000C0000U ,0x00000000U);
19392         /*############################################################################################################################ */
19393
19394                 // : PUTTING DP IN RESET
19395                 /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
19396
19397                 Display Port block level reset (includes DPDMA)
19398                 PSU_CRF_APB_RST_FPD_TOP_DP_RESET                                                0X0
19399
19400                 FPD Block level software controlled reset
19401                 (OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00010000U ,0x00000000U)
19402                 RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK |  0 );
19403
19404                 RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
19405                         |  0 ) & RegMask); */
19406                 PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00010000U ,0x00000000U);
19407         /*############################################################################################################################ */
19408
19409                 /*Register : DP_PHY_RESET @ 0XFD4A0200</p>
19410
19411                 Set to '1' to hold the GT in reset. Clear to release.
19412                 PSU_DP_DP_PHY_RESET_GT_RESET                                                    0X0
19413
19414                 Reset the transmitter PHY.
19415                 (OFFSET, MASK, VALUE)      (0XFD4A0200, 0x00000002U ,0x00000000U)
19416                 RegMask = (DP_DP_PHY_RESET_GT_RESET_MASK |  0 );
19417
19418                 RegVal = ((0x00000000U << DP_DP_PHY_RESET_GT_RESET_SHIFT
19419                         |  0 ) & RegMask); */
19420                 PSU_Mask_Write (DP_DP_PHY_RESET_OFFSET ,0x00000002U ,0x00000000U);
19421         /*############################################################################################################################ */
19422
19423                 /*Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238</p>
19424
19425                 Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] -
19426                 ane0 Bits [3:2] - lane 1
19427                 PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN                                           0X0
19428
19429                 Control PHY Power down
19430                 (OFFSET, MASK, VALUE)      (0XFD4A0238, 0x0000000FU ,0x00000000U)
19431                 RegMask = (DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK |  0 );
19432
19433                 RegVal = ((0x00000000U << DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
19434                         |  0 ) & RegMask); */
19435                 PSU_Mask_Write (DP_DP_TX_PHY_POWER_DOWN_OFFSET ,0x0000000FU ,0x00000000U);
19436         /*############################################################################################################################ */
19437
19438                 // : USB0 GFLADJ
19439                 /*Register : GUSB2PHYCFG @ 0XFE20C200</p>
19440
19441                 USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to
19442                 he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S
19443                 C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level
19444                 . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
19445                 UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger
19446                 alue. Note: This field is valid only in device mode.
19447                 PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM                                           0x9
19448
19449                 Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio
19450                  of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the
19451                 time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de
19452                 ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power
19453                 off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur
19454                 ng hibernation. - This bit is valid only in device mode.
19455                 PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY                                             0x0
19456
19457                 Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen
19458                 _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre
19459                  to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY.
19460                 ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh
19461                 n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma
19462                 d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet
19463                 d.
19464                 PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM                                            0x0
19465
19466                 USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P
19467                 Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. -
19468                 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte
19469                  in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i
19470                  active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.
19471                 PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL                                              0x0
19472
19473                 Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
19474                 full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with
19475                 ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
19476                 B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.
19477                 PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF                                              0x0
19478
19479                 ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa
19480                 e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons
19481                 ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s
19482                 lected through DWC_USB3_HSPHY_INTERFACE.
19483                 PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL                                       0x1
19484
19485                 PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a
19486                  8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same
19487                 lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen
19488                  ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I
19489                  any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.
19490                 PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF                                               0x0
19491
19492                 HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by
19493                 a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for
19494                 dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta
19495                 e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times.
19496                 The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this
19497                 ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH
19498                  clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One
19499                 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times
19500                 PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL                                             0x7
19501
19502                 Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either
19503                 he SoC bus or the USB. In Device-only configurations, only one register is needed. In Host mode, per-port registers are imple
19504                 ented.
19505                 (OFFSET, MASK, VALUE)      (0XFE20C200, 0x00003FBFU ,0x00002417U)
19506                 RegMask = (USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK | USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK | USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK | USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK | USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK |  0 );
19507
19508                 RegVal = ((0x00000009U << USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT
19509                         | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT
19510                         | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT
19511                         | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT
19512                         | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT
19513                         | 0x00000001U << USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT
19514                         | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT
19515                         | 0x00000007U << USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT
19516                         |  0 ) & RegMask); */
19517                 PSU_Mask_Write (USB3_0_XHCI_GUSB2PHYCFG_OFFSET ,0x00003FBFU ,0x00002417U);
19518         /*############################################################################################################################ */
19519
19520                 /*Register : GFLADJ @ 0XFE20C630</p>
19521
19522                 This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register
19523                 alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP
19524                 _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF
19525                 TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p
19526                 riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d
19527                 cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc
19528                 uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ =
19529                 ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P
19530                 RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)
19531                 PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ                                      0x0
19532
19533                 Global Frame Length Adjustment Register This register provides options for the software to control the core behavior with res
19534                 ect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an optio
19535                  to override the fladj_30mhz_reg sideband signal. In addition, it enables running SOF or ITP frame timer counters completely
19536                 rom the ref_clk. This facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal.
19537                 (OFFSET, MASK, VALUE)      (0XFE20C630, 0x003FFF00U ,0x00000000U)
19538                 RegMask = (USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK |  0 );
19539
19540                 RegVal = ((0x00000000U << USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT
19541                         |  0 ) & RegMask); */
19542                 PSU_Mask_Write (USB3_0_XHCI_GFLADJ_OFFSET ,0x003FFF00U ,0x00000000U);
19543         /*############################################################################################################################ */
19544
19545                 // : UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCORRECT RESET VALUES IN SILICON.
19546                 /*Register : ATTR_25 @ 0XFD480064</p>
19547
19548                 If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root
19549                 ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001
19550                 PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED                      0X1
19551
19552                 ATTR_25
19553                 (OFFSET, MASK, VALUE)      (0XFD480064, 0x00000200U ,0x00000200U)
19554                 RegMask = (PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK |  0 );
19555
19556                 RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT
19557                         |  0 ) & RegMask); */
19558                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_25_OFFSET ,0x00000200U ,0x00000200U);
19559         /*############################################################################################################################ */
19560
19561                 // : PCIE SETTINGS
19562                 /*Register : ATTR_7 @ 0XFD48001C</p>
19563
19564                 Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
19565                 ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
19566                 Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
19567                 erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator
19568                 set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
19569                 re size in bytes.; EP=0x0004; RP=0x0000
19570                 PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0                                                0x0
19571
19572                 ATTR_7
19573                 (OFFSET, MASK, VALUE)      (0XFD48001C, 0x0000FFFFU ,0x00000000U)
19574                 RegMask = (PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK |  0 );
19575
19576                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT
19577                         |  0 ) & RegMask); */
19578                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_7_OFFSET ,0x0000FFFFU ,0x00000000U);
19579         /*############################################################################################################################ */
19580
19581                 /*Register : ATTR_8 @ 0XFD480020</p>
19582
19583                 Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
19584                 ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
19585                 Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
19586                 erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator
19587                 set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
19588                 re size in bytes.; EP=0xFFF0; RP=0x0000
19589                 PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0                                                0x0
19590
19591                 ATTR_8
19592                 (OFFSET, MASK, VALUE)      (0XFD480020, 0x0000FFFFU ,0x00000000U)
19593                 RegMask = (PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK |  0 );
19594
19595                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT
19596                         |  0 ) & RegMask); */
19597                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_8_OFFSET ,0x0000FFFFU ,0x00000000U);
19598         /*############################################################################################################################ */
19599
19600                 /*Register : ATTR_9 @ 0XFD480024</p>
19601
19602                 Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if
19603                 AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
19604                  bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set
19605                 o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
19606                 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of
19607                 '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
19608                 ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
19609                 PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1                                                0x0
19610
19611                 ATTR_9
19612                 (OFFSET, MASK, VALUE)      (0XFD480024, 0x0000FFFFU ,0x00000000U)
19613                 RegMask = (PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK |  0 );
19614
19615                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT
19616                         |  0 ) & RegMask); */
19617                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_9_OFFSET ,0x0000FFFFU ,0x00000000U);
19618         /*############################################################################################################################ */
19619
19620                 /*Register : ATTR_10 @ 0XFD480028</p>
19621
19622                 Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if
19623                 AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
19624                  bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set
19625                 o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
19626                 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of
19627                 '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
19628                 ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
19629                 PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1                                               0x0
19630
19631                 ATTR_10
19632                 (OFFSET, MASK, VALUE)      (0XFD480028, 0x0000FFFFU ,0x00000000U)
19633                 RegMask = (PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK |  0 );
19634
19635                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT
19636                         |  0 ) & RegMask); */
19637                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_10_OFFSET ,0x0000FFFFU ,0x00000000U);
19638         /*############################################################################################################################ */
19639
19640                 /*Register : ATTR_11 @ 0XFD48002C</p>
19641
19642                 For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
19643                 AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
19644                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
19645                 , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
19646                 ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
19647                 most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to
19648                 . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
19649                 ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF
19650                 PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2                                               0xFFFF
19651
19652                 ATTR_11
19653                 (OFFSET, MASK, VALUE)      (0XFD48002C, 0x0000FFFFU ,0x0000FFFFU)
19654                 RegMask = (PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK |  0 );
19655
19656                 RegVal = ((0x0000FFFFU << PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT
19657                         |  0 ) & RegMask); */
19658                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_11_OFFSET ,0x0000FFFFU ,0x0000FFFFU);
19659         /*############################################################################################################################ */
19660
19661                 /*Register : ATTR_12 @ 0XFD480030</p>
19662
19663                 For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
19664                 AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
19665                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
19666                 , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
19667                 ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
19668                 most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to
19669                 . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
19670                 ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF
19671                 PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2                                               0xFF
19672
19673                 ATTR_12
19674                 (OFFSET, MASK, VALUE)      (0XFD480030, 0x0000FFFFU ,0x000000FFU)
19675                 RegMask = (PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK |  0 );
19676
19677                 RegVal = ((0x000000FFU << PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT
19678                         |  0 ) & RegMask); */
19679                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_12_OFFSET ,0x0000FFFFU ,0x000000FFU);
19680         /*############################################################################################################################ */
19681
19682                 /*Register : ATTR_13 @ 0XFD480034</p>
19683
19684                 For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
19685                 AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
19686                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
19687                  Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
19688                 t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
19689                 t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
19690                 if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits
19691                 f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
19692                  bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
19693                 PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3                                               0x0
19694
19695                 ATTR_13
19696                 (OFFSET, MASK, VALUE)      (0XFD480034, 0x0000FFFFU ,0x00000000U)
19697                 RegMask = (PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK |  0 );
19698
19699                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT
19700                         |  0 ) & RegMask); */
19701                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_13_OFFSET ,0x0000FFFFU ,0x00000000U);
19702         /*############################################################################################################################ */
19703
19704                 /*Register : ATTR_14 @ 0XFD480038</p>
19705
19706                 For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
19707                 AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
19708                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
19709                  Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
19710                 t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
19711                 t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
19712                 if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits
19713                 f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
19714                  bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF
19715                 PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3                                               0xFFFF
19716
19717                 ATTR_14
19718                 (OFFSET, MASK, VALUE)      (0XFD480038, 0x0000FFFFU ,0x0000FFFFU)
19719                 RegMask = (PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK |  0 );
19720
19721                 RegVal = ((0x0000FFFFU << PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT
19722                         |  0 ) & RegMask); */
19723                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_14_OFFSET ,0x0000FFFFU ,0x0000FFFFU);
19724         /*############################################################################################################################ */
19725
19726                 /*Register : ATTR_15 @ 0XFD48003C</p>
19727
19728                 For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
19729                 AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
19730                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
19731                 , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
19732                 ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
19733                 most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to
19734                 . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
19735                 ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0
19736                 PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4                                               0xFFF0
19737
19738                 ATTR_15
19739                 (OFFSET, MASK, VALUE)      (0XFD48003C, 0x0000FFFFU ,0x0000FFF0U)
19740                 RegMask = (PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK |  0 );
19741
19742                 RegVal = ((0x0000FFF0U << PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT
19743                         |  0 ) & RegMask); */
19744                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_15_OFFSET ,0x0000FFFFU ,0x0000FFF0U);
19745         /*############################################################################################################################ */
19746
19747                 /*Register : ATTR_16 @ 0XFD480040</p>
19748
19749                 For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
19750                 AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
19751                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
19752                 , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
19753                 ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
19754                 most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to
19755                 . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
19756                 ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0
19757                 PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4                                               0xFFF0
19758
19759                 ATTR_16
19760                 (OFFSET, MASK, VALUE)      (0XFD480040, 0x0000FFFFU ,0x0000FFF0U)
19761                 RegMask = (PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK |  0 );
19762
19763                 RegVal = ((0x0000FFF0U << PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT
19764                         |  0 ) & RegMask); */
19765                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_16_OFFSET ,0x0000FFFFU ,0x0000FFF0U);
19766         /*############################################################################################################################ */
19767
19768                 /*Register : ATTR_17 @ 0XFD480044</p>
19769
19770                 For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
19771                 AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
19772                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
19773                 Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit
19774                 refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
19775                 R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] =
19776                 refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in
19777                 ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
19778                 permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1
19779                 PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5                                               0xFFF1
19780
19781                 ATTR_17
19782                 (OFFSET, MASK, VALUE)      (0XFD480044, 0x0000FFFFU ,0x0000FFF1U)
19783                 RegMask = (PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK |  0 );
19784
19785                 RegVal = ((0x0000FFF1U << PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT
19786                         |  0 ) & RegMask); */
19787                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_17_OFFSET ,0x0000FFFFU ,0x0000FFF1U);
19788         /*############################################################################################################################ */
19789
19790                 /*Register : ATTR_18 @ 0XFD480048</p>
19791
19792                 For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
19793                 AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
19794                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
19795                 Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit
19796                 refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
19797                 R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] =
19798                 refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in
19799                 ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
19800                 permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1
19801                 PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5                                               0xFFF1
19802
19803                 ATTR_18
19804                 (OFFSET, MASK, VALUE)      (0XFD480048, 0x0000FFFFU ,0x0000FFF1U)
19805                 RegMask = (PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK |  0 );
19806
19807                 RegVal = ((0x0000FFF1U << PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT
19808                         |  0 ) & RegMask); */
19809                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_18_OFFSET ,0x0000FFFFU ,0x0000FFF1U);
19810         /*############################################################################################################################ */
19811
19812                 /*Register : ATTR_27 @ 0XFD48006C</p>
19813
19814                 Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred
19815                 to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001
19816                 PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED                      1
19817
19818                 Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1
19819                 state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6
19820                  32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000
19821                 PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY                        0x0
19822
19823                 ATTR_27
19824                 (OFFSET, MASK, VALUE)      (0XFD48006C, 0x00000738U ,0x00000100U)
19825                 RegMask = (PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK | PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK |  0 );
19826
19827                 RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT
19828                         | 0x00000000U << PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT
19829                         |  0 ) & RegMask); */
19830                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_27_OFFSET ,0x00000738U ,0x00000100U);
19831         /*############################################################################################################################ */
19832
19833                 /*Register : ATTR_50 @ 0XFD4800C8</p>
19834
19835                 Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0
19836                 00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw
19837                 tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r
19838                 gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004
19839                 PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE                          4
19840
19841                 PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab
19842                 lity.; EP=0x009C; RP=0x0000
19843                 PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR                                   0
19844
19845                 ATTR_50
19846                 (OFFSET, MASK, VALUE)      (0XFD4800C8, 0x0000FFF0U ,0x00000040U)
19847                 RegMask = (PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK | PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK |  0 );
19848
19849                 RegVal = ((0x00000004U << PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT
19850                         | 0x00000000U << PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT
19851                         |  0 ) & RegMask); */
19852                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_50_OFFSET ,0x0000FFF0U ,0x00000040U);
19853         /*############################################################################################################################ */
19854
19855                 /*Register : ATTR_105 @ 0XFD4801A4</p>
19856
19857                 Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l
19858                 ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD
19859                 PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD                              0xCD
19860
19861                 ATTR_105
19862                 (OFFSET, MASK, VALUE)      (0XFD4801A4, 0x000007FFU ,0x000000CDU)
19863                 RegMask = (PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK |  0 );
19864
19865                 RegVal = ((0x000000CDU << PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT
19866                         |  0 ) & RegMask); */
19867                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_105_OFFSET ,0x000007FFU ,0x000000CDU);
19868         /*############################################################################################################################ */
19869
19870                 /*Register : ATTR_106 @ 0XFD4801A8</p>
19871
19872                 Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non
19873                 osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024
19874                 PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH                              0x24
19875
19876                 Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da
19877                 a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and
19878                 completion header credits must be <= 80; EP=0x0004; RP=0x000C
19879                 PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH                             0xC
19880
19881                 ATTR_106
19882                 (OFFSET, MASK, VALUE)      (0XFD4801A8, 0x00003FFFU ,0x00000624U)
19883                 RegMask = (PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK | PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK |  0 );
19884
19885                 RegVal = ((0x00000024U << PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT
19886                         | 0x0000000CU << PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT
19887                         |  0 ) & RegMask); */
19888                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_106_OFFSET ,0x00003FFFU ,0x00000624U);
19889         /*############################################################################################################################ */
19890
19891                 /*Register : ATTR_107 @ 0XFD4801AC</p>
19892
19893                 Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data
19894                 redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support
19895                 d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be
19896                 less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018
19897                 PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD                             0x18
19898
19899                 ATTR_107
19900                 (OFFSET, MASK, VALUE)      (0XFD4801AC, 0x000007FFU ,0x00000018U)
19901                 RegMask = (PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK |  0 );
19902
19903                 RegVal = ((0x00000018U << PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT
19904                         |  0 ) & RegMask); */
19905                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_107_OFFSET ,0x000007FFU ,0x00000018U);
19906         /*############################################################################################################################ */
19907
19908                 /*Register : ATTR_108 @ 0XFD4801B0</p>
19909
19910                 Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less
19911                 han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5
19912                 PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD                              0xB5
19913
19914                 ATTR_108
19915                 (OFFSET, MASK, VALUE)      (0XFD4801B0, 0x000007FFU ,0x000000B5U)
19916                 RegMask = (PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK |  0 );
19917
19918                 RegVal = ((0x000000B5U << PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT
19919                         |  0 ) & RegMask); */
19920                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_108_OFFSET ,0x000007FFU ,0x000000B5U);
19921         /*############################################################################################################################ */
19922
19923                 /*Register : ATTR_109 @ 0XFD4801B4</p>
19924
19925                 Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00
19926                 0
19927                 PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV                                      0x0
19928
19929                 Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001
19930                 PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM                                    0x1
19931
19932                 Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER
19933                 cap structure; EP=0x0003; RP=0x0003
19934                 PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK                                         0x3
19935
19936                 Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n
19937                 mber of brams configured for transmit; EP=0x001C; RP=0x001C
19938                 PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET                                 0x1c
19939
19940                 Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post
19941                 d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020
19942                 PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH                              0x20
19943
19944                 ATTR_109
19945                 (OFFSET, MASK, VALUE)      (0XFD4801B4, 0x0000FFFFU ,0x00007E20U)
19946                 RegMask = (PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK | PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK | PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK | PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK | PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK |  0 );
19947
19948                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT
19949                         | 0x00000001U << PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT
19950                         | 0x00000003U << PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT
19951                         | 0x0000001CU << PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT
19952                         | 0x00000020U << PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT
19953                         |  0 ) & RegMask); */
19954                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_109_OFFSET ,0x0000FFFFU ,0x00007E20U);
19955         /*############################################################################################################################ */
19956
19957                 /*Register : ATTR_34 @ 0XFD480088</p>
19958
19959                 Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit
19960                 0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001
19961                 PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE                                        0x1
19962
19963                 ATTR_34
19964                 (OFFSET, MASK, VALUE)      (0XFD480088, 0x000000FFU ,0x00000001U)
19965                 RegMask = (PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK |  0 );
19966
19967                 RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT
19968                         |  0 ) & RegMask); */
19969                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_34_OFFSET ,0x000000FFU ,0x00000001U);
19970         /*############################################################################################################################ */
19971
19972                 /*Register : ATTR_53 @ 0XFD4800D4</p>
19973
19974                 PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil
19975                 ty.; EP=0x0048; RP=0x0060
19976                 PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR                                     0x60
19977
19978                 ATTR_53
19979                 (OFFSET, MASK, VALUE)      (0XFD4800D4, 0x000000FFU ,0x00000060U)
19980                 RegMask = (PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK |  0 );
19981
19982                 RegVal = ((0x00000060U << PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT
19983                         |  0 ) & RegMask); */
19984                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_53_OFFSET ,0x000000FFU ,0x00000060U);
19985         /*############################################################################################################################ */
19986
19987                 /*Register : ATTR_41 @ 0XFD4800A4</p>
19988
19989                 MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor
19990                  to Cap structure; EP=0x0000; RP=0x0000
19991                 PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE                 0x0
19992
19993                 Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or
19994                 he management port.; EP=0x0001; RP=0x0000
19995                 PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON                                         0
19996
19997                 MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi
19998                 ity.; EP=0x0060; RP=0x0000
19999                 PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR                                    0x0
20000
20001                 Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or
20002                 he management port.; EP=0x0001; RP=0x0000
20003                 PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON                                         0
20004
20005                 ATTR_41
20006                 (OFFSET, MASK, VALUE)      (0XFD4800A4, 0x000003FFU ,0x00000000U)
20007                 RegMask = (PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK |  0 );
20008
20009                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT
20010                         | 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT
20011                         | 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT
20012                         | 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT
20013                         |  0 ) & RegMask); */
20014                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_41_OFFSET ,0x000003FFU ,0x00000000U);
20015         /*############################################################################################################################ */
20016
20017                 /*Register : ATTR_97 @ 0XFD480184</p>
20018
20019                 Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004
20020                 PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH                            0x1
20021
20022                 Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00
20023                 4; RP=0x0004
20024                 PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH                               0x1
20025
20026                 ATTR_97
20027                 (OFFSET, MASK, VALUE)      (0XFD480184, 0x00000FFFU ,0x00000041U)
20028                 RegMask = (PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK | PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK |  0 );
20029
20030                 RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT
20031                         | 0x00000001U << PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT
20032                         |  0 ) & RegMask); */
20033                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_97_OFFSET ,0x00000FFFU ,0x00000041U);
20034         /*############################################################################################################################ */
20035
20036                 /*Register : ATTR_100 @ 0XFD480190</p>
20037
20038                 TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000
20039                 PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING                                   0x0
20040
20041                 ATTR_100
20042                 (OFFSET, MASK, VALUE)      (0XFD480190, 0x00000040U ,0x00000000U)
20043                 RegMask = (PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK |  0 );
20044
20045                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT
20046                         |  0 ) & RegMask); */
20047                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_100_OFFSET ,0x00000040U ,0x00000000U);
20048         /*############################################################################################################################ */
20049
20050                 /*Register : ATTR_101 @ 0XFD480194</p>
20051
20052                 Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message
20053                 LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL,
20054                 Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off;
20055                 EP=0x0000; RP=0x07FF
20056                 PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE                                  0x7FF
20057
20058                 Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001
20059                 PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING                             0x1
20060
20061                 ATTR_101
20062                 (OFFSET, MASK, VALUE)      (0XFD480194, 0x0000FFE2U ,0x0000FFE2U)
20063                 RegMask = (PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK | PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK |  0 );
20064
20065                 RegVal = ((0x000007FFU << PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT
20066                         | 0x00000001U << PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT
20067                         |  0 ) & RegMask); */
20068                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_101_OFFSET ,0x0000FFE2U ,0x0000FFE2U);
20069         /*############################################################################################################################ */
20070
20071                 /*Register : ATTR_37 @ 0XFD480094</p>
20072
20073                 Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism.
20074                 Required for Root.; EP=0x0000; RP=0x0001
20075                 PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP           0x1
20076
20077                 Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
20078                 gister.; EP=0x0001; RP=0x0001
20079                 PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY                          0x1
20080
20081                 ATTR_37
20082                 (OFFSET, MASK, VALUE)      (0XFD480094, 0x00004200U ,0x00004200U)
20083                 RegMask = (PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK | PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK |  0 );
20084
20085                 RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT
20086                         | 0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT
20087                         |  0 ) & RegMask); */
20088                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_37_OFFSET ,0x00004200U ,0x00004200U);
20089         /*############################################################################################################################ */
20090
20091                 /*Register : ATTR_93 @ 0XFD480174</p>
20092
20093                 Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L
20094                 _REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000
20095                 PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN                               0x1
20096
20097                 Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY
20098                 TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is
20099                 4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000
20100                 PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT                                  0x1000
20101
20102                 ATTR_93
20103                 (OFFSET, MASK, VALUE)      (0XFD480174, 0x0000FFFFU ,0x00009000U)
20104                 RegMask = (PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK | PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK |  0 );
20105
20106                 RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT
20107                         | 0x00001000U << PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT
20108                         |  0 ) & RegMask); */
20109                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_93_OFFSET ,0x0000FFFFU ,0x00009000U);
20110         /*############################################################################################################################ */
20111
20112                 /*Register : ID @ 0XFD480200</p>
20113
20114                 Device ID for the the PCIe Cap Structure Device ID field
20115                 PSU_PCIE_ATTRIB_ID_CFG_DEV_ID                                                   0xd021
20116
20117                 Vendor ID for the PCIe Cap Structure Vendor ID field
20118                 PSU_PCIE_ATTRIB_ID_CFG_VEND_ID                                                  0x10ee
20119
20120                 ID
20121                 (OFFSET, MASK, VALUE)      (0XFD480200, 0xFFFFFFFFU ,0x10EED021U)
20122                 RegMask = (PCIE_ATTRIB_ID_CFG_DEV_ID_MASK | PCIE_ATTRIB_ID_CFG_VEND_ID_MASK |  0 );
20123
20124                 RegVal = ((0x0000D021U << PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT
20125                         | 0x000010EEU << PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT
20126                         |  0 ) & RegMask); */
20127                 PSU_Mask_Write (PCIE_ATTRIB_ID_OFFSET ,0xFFFFFFFFU ,0x10EED021U);
20128         /*############################################################################################################################ */
20129
20130                 /*Register : SUBSYS_ID @ 0XFD480204</p>
20131
20132                 Subsystem ID for the the PCIe Cap Structure Subsystem ID field
20133                 PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID                                         0x7
20134
20135                 Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field
20136                 PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID                                    0x10ee
20137
20138                 SUBSYS_ID
20139                 (OFFSET, MASK, VALUE)      (0XFD480204, 0xFFFFFFFFU ,0x10EE0007U)
20140                 RegMask = (PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK | PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK |  0 );
20141
20142                 RegVal = ((0x00000007U << PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT
20143                         | 0x000010EEU << PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT
20144                         |  0 ) & RegMask); */
20145                 PSU_Mask_Write (PCIE_ATTRIB_SUBSYS_ID_OFFSET ,0xFFFFFFFFU ,0x10EE0007U);
20146         /*############################################################################################################################ */
20147
20148                 /*Register : REV_ID @ 0XFD480208</p>
20149
20150                 Revision ID for the the PCIe Cap Structure
20151                 PSU_PCIE_ATTRIB_REV_ID_CFG_REV_ID                                               0x0
20152
20153                 REV_ID
20154                 (OFFSET, MASK, VALUE)      (0XFD480208, 0x000000FFU ,0x00000000U)
20155                 RegMask = (PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK |  0 );
20156
20157                 RegVal = ((0x00000000U << PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT
20158                         |  0 ) & RegMask); */
20159                 PSU_Mask_Write (PCIE_ATTRIB_REV_ID_OFFSET ,0x000000FFU ,0x00000000U);
20160         /*############################################################################################################################ */
20161
20162                 /*Register : ATTR_24 @ 0XFD480060</p>
20163
20164                 Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
20165                 8000; RP=0x8000
20166                 PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE                                         0x400
20167
20168                 ATTR_24
20169                 (OFFSET, MASK, VALUE)      (0XFD480060, 0x0000FFFFU ,0x00000400U)
20170                 RegMask = (PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK |  0 );
20171
20172                 RegVal = ((0x00000400U << PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT
20173                         |  0 ) & RegMask); */
20174                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_24_OFFSET ,0x0000FFFFU ,0x00000400U);
20175         /*############################################################################################################################ */
20176
20177                 /*Register : ATTR_25 @ 0XFD480064</p>
20178
20179                 Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
20180                 0005; RP=0x0006
20181                 PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE                                         0x6
20182
20183                 INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001
20184                 PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED                               0
20185
20186                 ATTR_25
20187                 (OFFSET, MASK, VALUE)      (0XFD480064, 0x000001FFU ,0x00000006U)
20188                 RegMask = (PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK | PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK |  0 );
20189
20190                 RegVal = ((0x00000006U << PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT
20191                         | 0x00000000U << PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT
20192                         |  0 ) & RegMask); */
20193                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_25_OFFSET ,0x000001FFU ,0x00000006U);
20194         /*############################################################################################################################ */
20195
20196                 /*Register : ATTR_4 @ 0XFD480010</p>
20197
20198                 Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or
20199                 he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
20200                 ges are sent if an error is detected).; EP=0x0001; RP=0x0001
20201                 PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON                                          0
20202
20203                 Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or
20204                 he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
20205                 ges are sent if an error is detected).; EP=0x0001; RP=0x0001
20206                 PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON                                          0
20207
20208                 ATTR_4
20209                 (OFFSET, MASK, VALUE)      (0XFD480010, 0x00001000U ,0x00000000U)
20210                 RegMask = (PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK | PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK |  0 );
20211
20212                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT
20213                         | 0x00000000U << PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT
20214                         |  0 ) & RegMask); */
20215                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_4_OFFSET ,0x00001000U ,0x00000000U);
20216         /*############################################################################################################################ */
20217
20218                 /*Register : ATTR_89 @ 0XFD480164</p>
20219
20220                 VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP
20221                 0x0140; RP=0x0140
20222                 PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR                                   0
20223
20224                 ATTR_89
20225                 (OFFSET, MASK, VALUE)      (0XFD480164, 0x00001FFEU ,0x00000000U)
20226                 RegMask = (PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK |  0 );
20227
20228                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT
20229                         |  0 ) & RegMask); */
20230                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_89_OFFSET ,0x00001FFEU ,0x00000000U);
20231         /*############################################################################################################################ */
20232
20233                 /*Register : ATTR_79 @ 0XFD48013C</p>
20234
20235                 CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000
20236                 PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY                         1
20237
20238                 ATTR_79
20239                 (OFFSET, MASK, VALUE)      (0XFD48013C, 0x00000020U ,0x00000020U)
20240                 RegMask = (PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK |  0 );
20241
20242                 RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT
20243                         |  0 ) & RegMask); */
20244                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_79_OFFSET ,0x00000020U ,0x00000020U);
20245         /*############################################################################################################################ */
20246
20247                 /*Register : ATTR_43 @ 0XFD4800AC</p>
20248
20249                 Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o
20250                  the management port.; EP=0x0001; RP=0x0000
20251                 PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON                                        0
20252
20253                 ATTR_43
20254                 (OFFSET, MASK, VALUE)      (0XFD4800AC, 0x00000100U ,0x00000000U)
20255                 RegMask = (PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK |  0 );
20256
20257                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT
20258                         |  0 ) & RegMask); */
20259                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_43_OFFSET ,0x00000100U ,0x00000000U);
20260         /*############################################################################################################################ */
20261
20262                 /*Register : ATTR_48 @ 0XFD4800C0</p>
20263
20264                 MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note
20265                 hat the core does not implement the table; that must be implemented in user logic.; EP=0x0003; RP=0x0000
20266                 PSU_PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE                                0
20267
20268                 ATTR_48
20269                 (OFFSET, MASK, VALUE)      (0XFD4800C0, 0x000007FFU ,0x00000000U)
20270                 RegMask = (PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK |  0 );
20271
20272                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT
20273                         |  0 ) & RegMask); */
20274                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_48_OFFSET ,0x000007FFU ,0x00000000U);
20275         /*############################################################################################################################ */
20276
20277                 /*Register : ATTR_46 @ 0XFD4800B8</p>
20278
20279                 MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001;
20280                 P=0x0000
20281                 PSU_PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET                              0
20282
20283                 ATTR_46
20284                 (OFFSET, MASK, VALUE)      (0XFD4800B8, 0x0000FFFFU ,0x00000000U)
20285                 RegMask = (PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK |  0 );
20286
20287                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT
20288                         |  0 ) & RegMask); */
20289                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_46_OFFSET ,0x0000FFFFU ,0x00000000U);
20290         /*############################################################################################################################ */
20291
20292                 /*Register : ATTR_47 @ 0XFD4800BC</p>
20293
20294                 MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0000;
20295                 P=0x0000
20296                 PSU_PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET                              0
20297
20298                 ATTR_47
20299                 (OFFSET, MASK, VALUE)      (0XFD4800BC, 0x00001FFFU ,0x00000000U)
20300                 RegMask = (PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK |  0 );
20301
20302                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT
20303                         |  0 ) & RegMask); */
20304                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_47_OFFSET ,0x00001FFFU ,0x00000000U);
20305         /*############################################################################################################################ */
20306
20307                 /*Register : ATTR_44 @ 0XFD4800B0</p>
20308
20309                 MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP
20310                 0x0001; RP=0x0000
20311                 PSU_PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET                                0
20312
20313                 ATTR_44
20314                 (OFFSET, MASK, VALUE)      (0XFD4800B0, 0x0000FFFFU ,0x00000000U)
20315                 RegMask = (PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK |  0 );
20316
20317                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT
20318                         |  0 ) & RegMask); */
20319                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_44_OFFSET ,0x0000FFFFU ,0x00000000U);
20320         /*############################################################################################################################ */
20321
20322                 /*Register : ATTR_45 @ 0XFD4800B4</p>
20323
20324                 MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP
20325                 0x1000; RP=0x0000
20326                 PSU_PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET                                0
20327
20328                 ATTR_45
20329                 (OFFSET, MASK, VALUE)      (0XFD4800B4, 0x0000FFF8U ,0x00000000U)
20330                 RegMask = (PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK |  0 );
20331
20332                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT
20333                         |  0 ) & RegMask); */
20334                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_45_OFFSET ,0x0000FFF8U ,0x00000000U);
20335         /*############################################################################################################################ */
20336
20337                 /*Register : CB @ 0XFD48031C</p>
20338
20339                 DT837748 Enable
20340                 PSU_PCIE_ATTRIB_CB_CB1                                                          0x0
20341
20342                 ECO Register 1
20343                 (OFFSET, MASK, VALUE)      (0XFD48031C, 0x00000002U ,0x00000000U)
20344                 RegMask = (PCIE_ATTRIB_CB_CB1_MASK |  0 );
20345
20346                 RegVal = ((0x00000000U << PCIE_ATTRIB_CB_CB1_SHIFT
20347                         |  0 ) & RegMask); */
20348                 PSU_Mask_Write (PCIE_ATTRIB_CB_OFFSET ,0x00000002U ,0x00000000U);
20349         /*############################################################################################################################ */
20350
20351                 /*Register : ATTR_35 @ 0XFD48008C</p>
20352
20353                 Active State PM Support. Indicates the level of active state power management supported by the selected PCI Express Link, enc
20354                 ded as follows: 0 Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported.; EP=0x0001; RP=0x0001
20355                 PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT                              0x0
20356
20357                 ATTR_35
20358                 (OFFSET, MASK, VALUE)      (0XFD48008C, 0x00003000U ,0x00000000U)
20359                 RegMask = (PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK |  0 );
20360
20361                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT
20362                         |  0 ) & RegMask); */
20363                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_35_OFFSET ,0x00003000U ,0x00000000U);
20364         /*############################################################################################################################ */
20365
20366                 // : PUTTING PCIE CONTROL IN RESET
20367                 /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
20368
20369                 PCIE control block level reset
20370                 PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET                                         0X0
20371
20372                 FPD Block level software controlled reset
20373                 (OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00020000U ,0x00000000U)
20374                 RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK |  0 );
20375
20376                 RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
20377                         |  0 ) & RegMask); */
20378                 PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00020000U ,0x00000000U);
20379         /*############################################################################################################################ */
20380
20381                 // : CHECK PLL LOCK FOR LANE0
20382                 /*Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4</p>
20383
20384                 Status Read value of PLL Lock
20385                 PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
20386                 (OFFSET, MASK, VALUE)      (0XFD4023E4, 0x00000010U ,0x00000010U)  */
20387                 mask_poll(SERDES_L0_PLL_STATUS_READ_1_OFFSET,0x00000010U);
20388
20389         /*############################################################################################################################ */
20390
20391                 // : CHECK PLL LOCK FOR LANE1
20392                 /*Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4</p>
20393
20394                 Status Read value of PLL Lock
20395                 PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
20396                 (OFFSET, MASK, VALUE)      (0XFD4063E4, 0x00000010U ,0x00000010U)  */
20397                 mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET,0x00000010U);
20398
20399         /*############################################################################################################################ */
20400
20401                 // : CHECK PLL LOCK FOR LANE2
20402                 /*Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4</p>
20403
20404                 Status Read value of PLL Lock
20405                 PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
20406                 (OFFSET, MASK, VALUE)      (0XFD40A3E4, 0x00000010U ,0x00000010U)  */
20407                 mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET,0x00000010U);
20408
20409         /*############################################################################################################################ */
20410
20411                 // : CHECK PLL LOCK FOR LANE3
20412                 /*Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4</p>
20413
20414                 Status Read value of PLL Lock
20415                 PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
20416                 (OFFSET, MASK, VALUE)      (0XFD40E3E4, 0x00000010U ,0x00000010U)  */
20417                 mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET,0x00000010U);
20418
20419         /*############################################################################################################################ */
20420
20421                 // : SATA AHCI VENDOR SETTING
20422                 /*Register : PP2C @ 0XFD0C00AC</p>
20423
20424                 CIBGMN: COMINIT Burst Gap Minimum.
20425                 PSU_SATA_AHCI_VENDOR_PP2C_CIBGMN                                                0x18
20426
20427                 CIBGMX: COMINIT Burst Gap Maximum.
20428                 PSU_SATA_AHCI_VENDOR_PP2C_CIBGMX                                                0x40
20429
20430                 CIBGN: COMINIT Burst Gap Nominal.
20431                 PSU_SATA_AHCI_VENDOR_PP2C_CIBGN                                                 0x18
20432
20433                 CINMP: COMINIT Negate Minimum Period.
20434                 PSU_SATA_AHCI_VENDOR_PP2C_CINMP                                                 0x28
20435
20436                 PP2C - Port Phy2Cfg Register. This register controls the configuration of the Phy Control OOB timing for the COMINIT paramete
20437                 s for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
20438                 (OFFSET, MASK, VALUE)      (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U)
20439                 RegMask = (SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK | SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK | SATA_AHCI_VENDOR_PP2C_CIBGN_MASK | SATA_AHCI_VENDOR_PP2C_CINMP_MASK |  0 );
20440
20441                 RegVal = ((0x00000018U << SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT
20442                         | 0x00000040U << SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT
20443                         | 0x00000018U << SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT
20444                         | 0x00000028U << SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT
20445                         |  0 ) & RegMask); */
20446                 PSU_Mask_Write (SATA_AHCI_VENDOR_PP2C_OFFSET ,0xFFFFFFFFU ,0x28184018U);
20447         /*############################################################################################################################ */
20448
20449                 /*Register : PP3C @ 0XFD0C00B0</p>
20450
20451                 CWBGMN: COMWAKE Burst Gap Minimum.
20452                 PSU_SATA_AHCI_VENDOR_PP3C_CWBGMN                                                0x06
20453
20454                 CWBGMX: COMWAKE Burst Gap Maximum.
20455                 PSU_SATA_AHCI_VENDOR_PP3C_CWBGMX                                                0x14
20456
20457                 CWBGN: COMWAKE Burst Gap Nominal.
20458                 PSU_SATA_AHCI_VENDOR_PP3C_CWBGN                                                 0x08
20459
20460                 CWNMP: COMWAKE Negate Minimum Period.
20461                 PSU_SATA_AHCI_VENDOR_PP3C_CWNMP                                                 0x0E
20462
20463                 PP3C - Port Phy3CfgRegister. This register controls the configuration of the Phy Control OOB timing for the COMWAKE parameter
20464                  for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
20465                 (OFFSET, MASK, VALUE)      (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U)
20466                 RegMask = (SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK | SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK | SATA_AHCI_VENDOR_PP3C_CWBGN_MASK | SATA_AHCI_VENDOR_PP3C_CWNMP_MASK |  0 );
20467
20468                 RegVal = ((0x00000006U << SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT
20469                         | 0x00000014U << SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT
20470                         | 0x00000008U << SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT
20471                         | 0x0000000EU << SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT
20472                         |  0 ) & RegMask); */
20473                 PSU_Mask_Write (SATA_AHCI_VENDOR_PP3C_OFFSET ,0xFFFFFFFFU ,0x0E081406U);
20474         /*############################################################################################################################ */
20475
20476                 /*Register : PP4C @ 0XFD0C00B4</p>
20477
20478                 BMX: COM Burst Maximum.
20479                 PSU_SATA_AHCI_VENDOR_PP4C_BMX                                                   0x13
20480
20481                 BNM: COM Burst Nominal.
20482                 PSU_SATA_AHCI_VENDOR_PP4C_BNM                                                   0x08
20483
20484                 SFD: Signal Failure Detection, if the signal detection de-asserts for a time greater than this then the OOB detector will det
20485                 rmine this is a line idle and cause the PhyInit state machine to exit the Phy Ready State. A value of zero disables the Signa
20486                  Failure Detector. The value is based on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving a nominal time of
20487                 500ns based on a 150MHz PMCLK.
20488                 PSU_SATA_AHCI_VENDOR_PP4C_SFD                                                   0x4A
20489
20490                 PTST: Partial to Slumber timer value, specific delay the controller should apply while in partial before entering slumber. Th
20491                  value is bases on the system clock divided by 128, total delay = (Sys Clock Period) * PTST * 128
20492                 PSU_SATA_AHCI_VENDOR_PP4C_PTST                                                  0x06
20493
20494                 PP4C - Port Phy4Cfg Register. This register controls the configuration of the Phy Control Burst timing for the COM parameters
20495                 for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
20496                 (OFFSET, MASK, VALUE)      (0XFD0C00B4, 0xFFFFFFFFU ,0x064A0813U)
20497                 RegMask = (SATA_AHCI_VENDOR_PP4C_BMX_MASK | SATA_AHCI_VENDOR_PP4C_BNM_MASK | SATA_AHCI_VENDOR_PP4C_SFD_MASK | SATA_AHCI_VENDOR_PP4C_PTST_MASK |  0 );
20498
20499                 RegVal = ((0x00000013U << SATA_AHCI_VENDOR_PP4C_BMX_SHIFT
20500                         | 0x00000008U << SATA_AHCI_VENDOR_PP4C_BNM_SHIFT
20501                         | 0x0000004AU << SATA_AHCI_VENDOR_PP4C_SFD_SHIFT
20502                         | 0x00000006U << SATA_AHCI_VENDOR_PP4C_PTST_SHIFT
20503                         |  0 ) & RegMask); */
20504                 PSU_Mask_Write (SATA_AHCI_VENDOR_PP4C_OFFSET ,0xFFFFFFFFU ,0x064A0813U);
20505         /*############################################################################################################################ */
20506
20507                 /*Register : PP5C @ 0XFD0C00B8</p>
20508
20509                 RIT: Retry Interval Timer. The calculated value divided by two, the lower digit of precision is not needed.
20510                 PSU_SATA_AHCI_VENDOR_PP5C_RIT                                                   0xC96A4
20511
20512                 RCT: Rate Change Timer, a value based on the 54.2us for which a SATA device will transmit at a fixed rate ALIGNp after OOB ha
20513                  completed, for a fast SERDES it is suggested that this value be 54.2us / 4
20514                 PSU_SATA_AHCI_VENDOR_PP5C_RCT                                                   0x3FF
20515
20516                 PP5C - Port Phy5Cfg Register. This register controls the configuration of the Phy Control Retry Interval timing for either Po
20517                 t 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
20518                 (OFFSET, MASK, VALUE)      (0XFD0C00B8, 0xFFFFFFFFU ,0x3FFC96A4U)
20519                 RegMask = (SATA_AHCI_VENDOR_PP5C_RIT_MASK | SATA_AHCI_VENDOR_PP5C_RCT_MASK |  0 );
20520
20521                 RegVal = ((0x000C96A4U << SATA_AHCI_VENDOR_PP5C_RIT_SHIFT
20522                         | 0x000003FFU << SATA_AHCI_VENDOR_PP5C_RCT_SHIFT
20523                         |  0 ) & RegMask); */
20524                 PSU_Mask_Write (SATA_AHCI_VENDOR_PP5C_OFFSET ,0xFFFFFFFFU ,0x3FFC96A4U);
20525         /*############################################################################################################################ */
20526
20527
20528   return 1;
20529 }
20530 unsigned long psu_resetin_init_data() {
20531                 // : PUTTING SERDES PERIPHERAL IN RESET
20532                 // : PUTTING USB0 IN RESET
20533                 /*Register : RST_LPD_TOP @ 0XFF5E023C</p>
20534
20535                 USB 0 reset for control registers
20536                 PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET                                          0X1
20537
20538                 USB 0 sleep circuit reset
20539                 PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET                                         0X1
20540
20541                 USB 0 reset
20542                 PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET                                          0X1
20543
20544                 Software control register for the LPD block.
20545                 (OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000540U ,0x00000540U)
20546                 RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK |  0 );
20547
20548                 RegVal = ((0x00000001U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
20549                         | 0x00000001U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
20550                         | 0x00000001U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
20551                         |  0 ) & RegMask); */
20552                 PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000540U ,0x00000540U);
20553         /*############################################################################################################################ */
20554
20555                 // : PUTTING GEM0 IN RESET
20556                 /*Register : RST_LPD_IOU0 @ 0XFF5E0230</p>
20557
20558                 GEM 3 reset
20559                 PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET                                             0X1
20560
20561                 Software controlled reset for the GEMs
20562                 (OFFSET, MASK, VALUE)      (0XFF5E0230, 0x00000008U ,0x00000008U)
20563                 RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK |  0 );
20564
20565                 RegVal = ((0x00000001U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
20566                         |  0 ) & RegMask); */
20567                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000008U);
20568         /*############################################################################################################################ */
20569
20570                 // : PUTTING SATA IN RESET
20571                 /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
20572
20573                 Sata block level reset
20574                 PSU_CRF_APB_RST_FPD_TOP_SATA_RESET                                              0X1
20575
20576                 FPD Block level software controlled reset
20577                 (OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00000002U ,0x00000002U)
20578                 RegMask = (CRF_APB_RST_FPD_TOP_SATA_RESET_MASK |  0 );
20579
20580                 RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
20581                         |  0 ) & RegMask); */
20582                 PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000002U);
20583         /*############################################################################################################################ */
20584
20585                 // : PUTTING PCIE IN RESET
20586                 /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
20587
20588                 PCIE config reset
20589                 PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET                                          0X1
20590
20591                 PCIE control block level reset
20592                 PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET                                         0X1
20593
20594                 PCIE bridge block level reset (AXI interface)
20595                 PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET                                       0X1
20596
20597                 FPD Block level software controlled reset
20598                 (OFFSET, MASK, VALUE)      (0XFD1A0100, 0x000E0000U ,0x000E0000U)
20599                 RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK |  0 );
20600
20601                 RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
20602                         | 0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
20603                         | 0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
20604                         |  0 ) & RegMask); */
20605                 PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000E0000U ,0x000E0000U);
20606         /*############################################################################################################################ */
20607
20608                 // : PUTTING DP IN RESET
20609                 /*Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238</p>
20610
20611                 Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] -
20612                 ane0 Bits [3:2] - lane 1
20613                 PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN                                           0XA
20614
20615                 Control PHY Power down
20616                 (OFFSET, MASK, VALUE)      (0XFD4A0238, 0x0000000FU ,0x0000000AU)
20617                 RegMask = (DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK |  0 );
20618
20619                 RegVal = ((0x0000000AU << DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
20620                         |  0 ) & RegMask); */
20621                 PSU_Mask_Write (DP_DP_TX_PHY_POWER_DOWN_OFFSET ,0x0000000FU ,0x0000000AU);
20622         /*############################################################################################################################ */
20623
20624                 /*Register : DP_PHY_RESET @ 0XFD4A0200</p>
20625
20626                 Set to '1' to hold the GT in reset. Clear to release.
20627                 PSU_DP_DP_PHY_RESET_GT_RESET                                                    0X1
20628
20629                 Reset the transmitter PHY.
20630                 (OFFSET, MASK, VALUE)      (0XFD4A0200, 0x00000002U ,0x00000002U)
20631                 RegMask = (DP_DP_PHY_RESET_GT_RESET_MASK |  0 );
20632
20633                 RegVal = ((0x00000001U << DP_DP_PHY_RESET_GT_RESET_SHIFT
20634                         |  0 ) & RegMask); */
20635                 PSU_Mask_Write (DP_DP_PHY_RESET_OFFSET ,0x00000002U ,0x00000002U);
20636         /*############################################################################################################################ */
20637
20638                 /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
20639
20640                 Display Port block level reset (includes DPDMA)
20641                 PSU_CRF_APB_RST_FPD_TOP_DP_RESET                                                0X1
20642
20643                 FPD Block level software controlled reset
20644                 (OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00010000U ,0x00010000U)
20645                 RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK |  0 );
20646
20647                 RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
20648                         |  0 ) & RegMask); */
20649                 PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00010000U ,0x00010000U);
20650         /*############################################################################################################################ */
20651
20652
20653   return 1;
20654 }
20655 unsigned long psu_ps_pl_isolation_removal_data() {
20656                 // : PS-PL POWER UP REQUEST
20657                 /*Register : REQ_PWRUP_INT_EN @ 0XFFD80118</p>
20658
20659                 Power-up Request Interrupt Enable for PL
20660                 PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL                                              1
20661
20662                 Power-up Request Interrupt Enable Register. Writing a 1 to this location will unmask the interrupt.
20663                 (OFFSET, MASK, VALUE)      (0XFFD80118, 0x00800000U ,0x00800000U)
20664                 RegMask = (PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK |  0 );
20665
20666                 RegVal = ((0x00000001U << PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT
20667                         |  0 ) & RegMask); */
20668                 PSU_Mask_Write (PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET ,0x00800000U ,0x00800000U);
20669         /*############################################################################################################################ */
20670
20671                 /*Register : REQ_PWRUP_TRIG @ 0XFFD80120</p>
20672
20673                 Power-up Request Trigger for PL
20674                 PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL                                                1
20675
20676                 Power-up Request Trigger Register. A write of one to this location will generate a power-up request to the PMU.
20677                 (OFFSET, MASK, VALUE)      (0XFFD80120, 0x00800000U ,0x00800000U)
20678                 RegMask = (PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK |  0 );
20679
20680                 RegVal = ((0x00000001U << PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT
20681                         |  0 ) & RegMask); */
20682                 PSU_Mask_Write (PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET ,0x00800000U ,0x00800000U);
20683         /*############################################################################################################################ */
20684
20685                 // : POLL ON PL POWER STATUS
20686                 /*Register : REQ_PWRUP_STATUS @ 0XFFD80110</p>
20687
20688                 Power-up Request Status for PL
20689                 PSU_PMU_GLOBAL_REQ_PWRUP_STATUS_PL                                              1
20690                 (OFFSET, MASK, VALUE)      (0XFFD80110, 0x00800000U ,0x00000000U)  */
20691                 mask_pollOnValue(PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET,0x00800000U,0x00000000U);
20692
20693         /*############################################################################################################################ */
20694
20695
20696   return 1;
20697 }
20698 unsigned long psu_ps_pl_reset_config_data() {
20699                 // : PS PL RESET SEQUENCE
20700                 // : FABRIC RESET USING EMIO
20701                 /*Register : MASK_DATA_5_MSW @ 0XFF0A002C</p>
20702
20703                 Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
20704                 PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW                                             0x8000
20705
20706                 Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits)
20707                 (OFFSET, MASK, VALUE)      (0XFF0A002C, 0xFFFF0000U ,0x80000000U)
20708                 RegMask = (GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK |  0 );
20709
20710                 RegVal = ((0x00008000U << GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT
20711                         |  0 ) & RegMask); */
20712                 PSU_Mask_Write (GPIO_MASK_DATA_5_MSW_OFFSET ,0xFFFF0000U ,0x80000000U);
20713         /*############################################################################################################################ */
20714
20715                 /*Register : DIRM_5 @ 0XFF0A0344</p>
20716
20717                 Operation is the same as DIRM_0[DIRECTION_0]
20718                 PSU_GPIO_DIRM_5_DIRECTION_5                                                     0x80000000
20719
20720                 Direction mode (GPIO Bank5, EMIO)
20721                 (OFFSET, MASK, VALUE)      (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U)
20722                 RegMask = (GPIO_DIRM_5_DIRECTION_5_MASK |  0 );
20723
20724                 RegVal = ((0x80000000U << GPIO_DIRM_5_DIRECTION_5_SHIFT
20725                         |  0 ) & RegMask); */
20726                 PSU_Mask_Write (GPIO_DIRM_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);
20727         /*############################################################################################################################ */
20728
20729                 /*Register : OEN_5 @ 0XFF0A0348</p>
20730
20731                 Operation is the same as OEN_0[OP_ENABLE_0]
20732                 PSU_GPIO_OEN_5_OP_ENABLE_5                                                      0x80000000
20733
20734                 Output enable (GPIO Bank5, EMIO)
20735                 (OFFSET, MASK, VALUE)      (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U)
20736                 RegMask = (GPIO_OEN_5_OP_ENABLE_5_MASK |  0 );
20737
20738                 RegVal = ((0x80000000U << GPIO_OEN_5_OP_ENABLE_5_SHIFT
20739                         |  0 ) & RegMask); */
20740                 PSU_Mask_Write (GPIO_OEN_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);
20741         /*############################################################################################################################ */
20742
20743                 /*Register : DATA_5 @ 0XFF0A0054</p>
20744
20745                 Output Data
20746                 PSU_GPIO_DATA_5_DATA_5                                                          0x80000000
20747
20748                 Output Data (GPIO Bank5, EMIO)
20749                 (OFFSET, MASK, VALUE)      (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U)
20750                 RegMask = (GPIO_DATA_5_DATA_5_MASK |  0 );
20751
20752                 RegVal = ((0x80000000U << GPIO_DATA_5_DATA_5_SHIFT
20753                         |  0 ) & RegMask); */
20754                 PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);
20755         /*############################################################################################################################ */
20756
20757                 mask_delay(1);
20758
20759         /*############################################################################################################################ */
20760
20761                 // : FABRIC RESET USING DATA_5 TOGGLE
20762                 /*Register : DATA_5 @ 0XFF0A0054</p>
20763
20764                 Output Data
20765                 PSU_GPIO_DATA_5_DATA_5                                                          0X00000000
20766
20767                 Output Data (GPIO Bank5, EMIO)
20768                 (OFFSET, MASK, VALUE)      (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U)
20769                 RegMask = (GPIO_DATA_5_DATA_5_MASK |  0 );
20770
20771                 RegVal = ((0x00000000U << GPIO_DATA_5_DATA_5_SHIFT
20772                         |  0 ) & RegMask); */
20773                 PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x00000000U);
20774         /*############################################################################################################################ */
20775
20776                 mask_delay(1);
20777
20778         /*############################################################################################################################ */
20779
20780                 // : FABRIC RESET USING DATA_5 TOGGLE
20781                 /*Register : DATA_5 @ 0XFF0A0054</p>
20782
20783                 Output Data
20784                 PSU_GPIO_DATA_5_DATA_5                                                          0x80000000
20785
20786                 Output Data (GPIO Bank5, EMIO)
20787                 (OFFSET, MASK, VALUE)      (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U)
20788                 RegMask = (GPIO_DATA_5_DATA_5_MASK |  0 );
20789
20790                 RegVal = ((0x80000000U << GPIO_DATA_5_DATA_5_SHIFT
20791                         |  0 ) & RegMask); */
20792                 PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);
20793         /*############################################################################################################################ */
20794
20795
20796   return 1;
20797 }
20798
20799 unsigned long psu_ddr_phybringup_data() {
20800
20801
20802                 unsigned int regval = 0;
20803         int dpll_divisor;
20804         dpll_divisor = (Xil_In32(0xFD1A0080U) & 0x00003F00U) >> 0x00000008U;
20805         prog_reg (0xFD1A0080U, 0x00003F00U, 0x00000008U, 0x00000005U);
20806         prog_reg (0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U);
20807         Xil_Out32(0xFD080004U, 0x00040003U);
20808         while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U);
20809         prog_reg (0xFD080684U, 0x06000000U, 0x00000019U, 0x00000001U);
20810         prog_reg (0xFD0806A4U, 0x06000000U, 0x00000019U, 0x00000001U);
20811         prog_reg (0xFD0806C4U, 0x06000000U, 0x00000019U, 0x00000001U);
20812         prog_reg (0xFD0806E4U, 0x06000000U, 0x00000019U, 0x00000001U);
20813         prog_reg (0xFD1A0080, 0x3F00, 0x8, dpll_divisor);
20814         Xil_Out32(0xFD080004U, 0x40040071U);
20815         while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U);
20816         Xil_Out32(0xFD080004U, 0x40040001U);
20817         while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U);
20818         // PHY BRINGUP SEQ
20819         while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU);
20820         prog_reg (0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
20821         //poll for PHY initialization to complete
20822         while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU);
20823
20824         Xil_Out32(0xFD0701B0U, 0x00000001U);
20825         Xil_Out32(0xFD070320U, 0x00000001U);
20826         while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U);
20827         prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
20828          Xil_Out32(0xFD080004, 0x0004FE01); //PUB_PIR
20829           regval = Xil_In32(0xFD080030); //PUB_PGSR0
20830           while(regval != 0x80000FFF){
20831              regval = Xil_In32(0xFD080030); //PUB_PGSR0
20832           }
20833
20834
20835  // Run Vref training in static read mode
20836         Xil_Out32(0xFD080200U, 0x100091C7U);
20837         Xil_Out32(0xFD080018U, 0x00F01EF2U);
20838         Xil_Out32(0xFD08001CU, 0x55AA5498U);
20839         Xil_Out32(0xFD08142CU, 0x00041830U);
20840         Xil_Out32(0xFD08146CU, 0x00041830U);
20841         Xil_Out32(0xFD0814ACU, 0x00041830U);
20842         Xil_Out32(0xFD0814ECU, 0x00041830U);
20843         Xil_Out32(0xFD08152CU, 0x00041830U);
20844
20845
20846          Xil_Out32(0xFD080004, 0x00060001); //PUB_PIR
20847           regval = Xil_In32(0xFD080030); //PUB_PGSR0
20848           while((regval & 0x80004001) != 0x80004001){
20849              regval = Xil_In32(0xFD080030); //PUB_PGSR0
20850           }
20851
20852          // Vref training is complete, disabling static read mode
20853         Xil_Out32(0xFD080200U, 0x800091C7U);
20854         Xil_Out32(0xFD080018U, 0x00F12302U);
20855         Xil_Out32(0xFD08001CU, 0x55AA5480U);
20856         Xil_Out32(0xFD08142CU, 0x00041800U);
20857         Xil_Out32(0xFD08146CU, 0x00041800U);
20858         Xil_Out32(0xFD0814ACU, 0x00041800U);
20859         Xil_Out32(0xFD0814ECU, 0x00041800U);
20860         Xil_Out32(0xFD08152CU, 0x00041800U);
20861
20862
20863          Xil_Out32(0xFD080004, 0x0000C001); //PUB_PIR
20864           regval = Xil_In32(0xFD080030); //PUB_PGSR0
20865           while((regval & 0x80000C01) != 0x80000C01){
20866              regval = Xil_In32(0xFD080030); //PUB_PGSR0
20867           }
20868
20869         Xil_Out32(0xFD070180U, 0x01000040U);
20870         Xil_Out32(0xFD070060U, 0x00000000U);
20871         prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
20872
20873 return 1;
20874 }
20875
20876 /**
20877  * CRL_APB Base Address
20878  */
20879 #define CRL_APB_BASEADDR      0XFF5E0000U
20880 #define CRL_APB_RST_LPD_IOU0    ( ( CRL_APB_BASEADDR ) + 0X00000230U )
20881 #define CRL_APB_RST_LPD_IOU1    ( ( CRL_APB_BASEADDR ) + 0X00000234U )
20882 #define CRL_APB_RST_LPD_IOU2    ( ( CRL_APB_BASEADDR ) + 0X00000238U )
20883 #define CRL_APB_RST_LPD_TOP    ( ( CRL_APB_BASEADDR ) + 0X0000023CU )
20884 #define CRL_APB_IOU_SWITCH_CTRL    ( ( CRL_APB_BASEADDR ) + 0X0000009CU )
20885
20886 /**
20887  * CRF_APB Base Address
20888  */
20889 #define CRF_APB_BASEADDR      0XFD1A0000U
20890
20891 #define CRF_APB_RST_FPD_TOP    ( ( CRF_APB_BASEADDR ) + 0X00000100U )
20892 #define CRF_APB_GPU_REF_CTRL    ( ( CRF_APB_BASEADDR ) + 0X00000084U )
20893 #define CRF_APB_RST_DDR_SS    ( ( CRF_APB_BASEADDR ) + 0X00000108U )
20894 #define PSU_MASK_POLL_TIME 1100000
20895
20896
20897 int mask_pollOnValue(u32 add , u32 mask, u32 value ) {
20898         volatile u32 *addr = (volatile u32*)(unsigned long) add;
20899         int i = 0;
20900         while ((*addr & mask)!= value) {
20901                 if (i == PSU_MASK_POLL_TIME) {
20902                         return 0;
20903                 }
20904                 i++;
20905         }
20906         return 1;
20907         //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
20908 }
20909
20910 int mask_poll(u32 add , u32 mask) {
20911         volatile u32 *addr = (volatile u32*)(unsigned long) add;
20912         int i = 0;
20913         while (!(*addr & mask)) {
20914                 if (i == PSU_MASK_POLL_TIME) {
20915                         return 0;
20916                 }
20917                 i++;
20918         }
20919         return 1;
20920         //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
20921 }
20922
20923 void mask_delay(u32 delay) {
20924     usleep (delay);
20925 }
20926
20927 u32 mask_read(u32 add , u32 mask ) {
20928         volatile u32 *addr = (volatile u32*)(unsigned long) add;
20929         u32 val = (*addr & mask);
20930         //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
20931         return val;
20932 }
20933
20934
20935 //Following SERDES programming sequences that a user need to follow to work around the known limitation with SERDES.
20936 //These sequences should done before STEP 1 and STEP 2 as described in previous section. These programming steps are
20937 //required for current silicon version and are likely to undergo further changes with subsequent silicon versions.
20938
20939
20940
20941 int serdes_fixcal_code() {
20942         int MaskStatus = 1;
20943
20944    // L3_TM_CALIB_DIG19
20945    Xil_Out32(0xFD40EC4C,0x00000020);
20946    //ICM_CFG0
20947    Xil_Out32(0xFD410010,0x00000001);
20948
20949    //is calibration done, polling on L3_CALIB_DONE_STATUS
20950    MaskStatus = mask_poll(0xFD40EF14, 0x2);
20951
20952    if (MaskStatus == 0)
20953    {
20954         xil_printf("SERDES initialization timed out\n\r");
20955    }
20956
20957    unsigned int tmp_0_1;
20958    tmp_0_1 = mask_read(0xFD400B0C, 0x3F);
20959
20960    unsigned int tmp_0_2 = tmp_0_1 & (0x7);
20961    unsigned int tmp_0_3 = tmp_0_1 & (0x38);
20962    //Configure ICM for de-asserting CMN_Resetn
20963    Xil_Out32(0xFD410010,0x00000000);
20964    Xil_Out32(0xFD410014,0x00000000);
20965
20966    unsigned int tmp_0_2_mod = (tmp_0_2 <<1) | (0x1);
20967    tmp_0_2_mod = (tmp_0_2_mod <<4);
20968
20969    tmp_0_3 = tmp_0_3 >>3;
20970    Xil_Out32(0xFD40EC4C,tmp_0_3);
20971
20972    //L3_TM_CALIB_DIG18
20973    Xil_Out32(0xFD40EC48,tmp_0_2_mod);
20974    return MaskStatus;
20975
20976
20977 }
20978
20979 int serdes_enb_coarse_saturation() {
20980   //Enable PLL Coarse Code saturation Logic
20981    Xil_Out32(0xFD402094,0x00000010);
20982    Xil_Out32(0xFD406094,0x00000010);
20983    Xil_Out32(0xFD40A094,0x00000010);
20984    Xil_Out32(0xFD40E094,0x00000010);
20985    return 1;
20986 }
20987
20988 int init_serdes() {
20989         int status = 1;
20990         status &=  psu_resetin_init_data();
20991
20992         status &= serdes_fixcal_code();
20993         status &= serdes_enb_coarse_saturation();
20994
20995     status &=  psu_serdes_init_data();
20996         status &=  psu_resetout_init_data();
20997
20998         return status;
20999 }
21000
21001
21002
21003
21004
21005
21006 void init_peripheral()
21007 {
21008         unsigned int RegValue;
21009
21010         /* Turn on IOU Clock */
21011         //Xil_Out32( CRL_APB_IOU_SWITCH_CTRL, 0x01001500);
21012
21013         /* Release all resets in the IOU */
21014         Xil_Out32( CRL_APB_RST_LPD_IOU0, 0x00000000);
21015         Xil_Out32( CRL_APB_RST_LPD_IOU1, 0x00000000);
21016         Xil_Out32( CRL_APB_RST_LPD_IOU2, 0x00000000);
21017
21018         /* Activate GPU clocks */
21019         //Xil_Out32(CRF_APB_GPU_REF_CTRL, 0x07001500);
21020
21021         /* Take LPD out of reset except R5 */
21022         RegValue = Xil_In32(CRL_APB_RST_LPD_TOP);
21023         RegValue &= 0x7;
21024         Xil_Out32( CRL_APB_RST_LPD_TOP, RegValue);
21025
21026         /* Take most of FPD out of reset */
21027         Xil_Out32( CRF_APB_RST_FPD_TOP, 0x00000000);
21028
21029         /* Making DPDMA as secure */
21030   unsigned int tmp_regval;
21031   tmp_regval = Xil_In32(0xFD690040);
21032   tmp_regval &= ~0x00000001;
21033   Xil_Out32(0xFD690040, tmp_regval);
21034
21035         /* Making PCIe as secure */
21036   tmp_regval = Xil_In32(0xFD690030);
21037   tmp_regval &= ~0x00000001;
21038   Xil_Out32(0xFD690030, tmp_regval);
21039 }
21040
21041 int psu_init_xppu_aper_ram() {
21042         unsigned long APER_OFFSET = 0xFF981000;
21043         int i = 0;
21044         for (; i <= 400; i++) {
21045                 PSU_Mask_Write (APER_OFFSET ,0xF80FFFFFU ,0x08080000U);
21046                 APER_OFFSET = APER_OFFSET + 0x4;
21047         }
21048
21049         return 0;
21050 }
21051
21052 int psu_lpd_protection() {
21053    psu_init_xppu_aper_ram();
21054    psu_lpd_xppu_data();
21055    return 0;
21056 }
21057
21058 int psu_ddr_protection() {
21059    psu_ddr_xmpu0_data();
21060    psu_ddr_xmpu1_data();
21061    psu_ddr_xmpu2_data();
21062    psu_ddr_xmpu3_data();
21063    psu_ddr_xmpu4_data();
21064    psu_ddr_xmpu5_data();
21065    return 0;
21066 }
21067 int psu_ocm_protection() {
21068    psu_ocm_xmpu_data();
21069    return 0;
21070 }
21071
21072 int psu_fpd_protection() {
21073    psu_fpd_xmpu_data();
21074    return 0;
21075 }
21076
21077 int psu_protection_lock() {
21078   psu_protection_lock_data();
21079   return 0;
21080 }
21081
21082 int psu_protection() {
21083   psu_ddr_protection();
21084   psu_ocm_protection();
21085   psu_fpd_protection();
21086   psu_lpd_protection();
21087   return 0;
21088 }
21089
21090
21091
21092 int
21093 psu_init()
21094 {
21095         int status = 1;
21096         status &= psu_mio_init_data ();
21097         status &=   psu_pll_init_data ();
21098         status &=   psu_clock_init_data ();
21099
21100         status &=  psu_ddr_init_data ();
21101         status &=  psu_ddr_phybringup_data ();
21102         status &=  psu_peripherals_init_data ();
21103
21104         status &=  init_serdes();
21105         init_peripheral ();
21106
21107         status &=  psu_peripherals_powerdwn_data ();
21108
21109         if (status == 0) {
21110                 return 1;
21111         }
21112         return 0;
21113 }