1 /******************************************************************************
3 * Copyright (C) 2015 Xilinx, Inc. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>
19 ******************************************************************************/
23 #include "psu_init_gpl.h"
24 #define DPLL_CFG_LOCK_DLY 63
25 #define DPLL_CFG_LOCK_CNT 625
26 #define DPLL_CFG_LFHF 3
28 #define DPLL_CFG_RES 2
30 static int mask_pollOnValue(u32 add, u32 mask, u32 value);
32 static int mask_poll(u32 add, u32 mask);
34 static void mask_delay(u32 delay);
36 static u32 mask_read(u32 add, u32 mask);
38 static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly,
39 int d_lock_cnt, int d_lfhf, int d_cp, int d_res);
42 void PSU_Mask_Write(unsigned long offset, unsigned long mask,
45 unsigned long RegVal = 0x0;
47 RegVal = Xil_In32(offset);
49 RegVal |= (val & mask);
50 Xil_Out32(offset, RegVal);
54 void prog_reg(unsigned long addr, unsigned long mask,
60 rdata = Xil_In32(addr);
61 rdata = rdata & (~mask);
62 rdata = rdata | (value << shift);
63 Xil_Out32(addr, rdata);
66 unsigned long psu_pll_init_data(void)
72 * Register : RPLL_CFG @ 0XFF5E0034
74 * PLL loop filter resistor control
75 * PSU_CRL_APB_RPLL_CFG_RES 0xc
77 * PLL charge pump control
78 * PSU_CRL_APB_RPLL_CFG_CP 0x3
80 * PLL loop filter high frequency capacitor control
81 * PSU_CRL_APB_RPLL_CFG_LFHF 0x3
83 * Lock circuit counter setting
84 * PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x339
86 * Lock circuit configuration settings for lock windowsize
87 * PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f
89 * Helper data. Values are to be looked up in a table from Data Sheet
90 * (OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E672C6CU)
92 PSU_Mask_Write(CRL_APB_RPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E672C6CU);
93 /*##################################################################### */
99 * Register : RPLL_CTRL @ 0XFF5E0030
101 * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
102 * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
103 * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
104 * PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0
106 * The integer portion of the feedback divider to the PLL
107 * PSU_CRL_APB_RPLL_CTRL_FBDIV 0x2d
109 * This turns on the divide by 2 that is inside of the PLL. This does not c
110 * hange the VCO frequency, just the output frequency
111 * PSU_CRL_APB_RPLL_CTRL_DIV2 0x1
114 * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00012D00U)
116 PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00717F00U, 0x00012D00U);
117 /*##################################################################### */
123 * Register : RPLL_CTRL @ 0XFF5E0030
125 * Bypasses the PLL clock. The usable clock will be determined from the POS
126 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
127 * clock and 4 cycles of the new clock. This is not usually an issue, but d
128 * esigners must be aware.)
129 * PSU_CRL_APB_RPLL_CTRL_BYPASS 1
132 * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000008U)
134 PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U);
135 /*##################################################################### */
141 * Register : RPLL_CTRL @ 0XFF5E0030
143 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
145 * PSU_CRL_APB_RPLL_CTRL_RESET 1
148 * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000001U)
150 PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U);
151 /*##################################################################### */
157 * Register : RPLL_CTRL @ 0XFF5E0030
159 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
161 * PSU_CRL_APB_RPLL_CTRL_RESET 0
164 * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000000U)
166 PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U);
167 /*##################################################################### */
173 * Register : PLL_STATUS @ 0XFF5E0040
176 * PSU_CRL_APB_PLL_STATUS_RPLL_LOCK 1
177 * (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000002U ,0x00000002U)
179 mask_poll(CRL_APB_PLL_STATUS_OFFSET, 0x00000002U);
181 /*##################################################################### */
187 * Register : RPLL_CTRL @ 0XFF5E0030
189 * Bypasses the PLL clock. The usable clock will be determined from the POS
190 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
191 * clock and 4 cycles of the new clock. This is not usually an issue, but d
192 * esigners must be aware.)
193 * PSU_CRL_APB_RPLL_CTRL_BYPASS 0
196 * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000000U)
198 PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U);
199 /*##################################################################### */
202 * Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048
204 * Divisor value for this clock.
205 * PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x2
207 * Control for a clock that will be generated in the LPD, but used in the F
208 * PD as a clock source for the peripheral clock muxes.
209 * (OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000200U)
211 PSU_Mask_Write(CRL_APB_RPLL_TO_FPD_CTRL_OFFSET,
212 0x00003F00U, 0x00000200U);
213 /*##################################################################### */
222 * Register : IOPLL_CFG @ 0XFF5E0024
224 * PLL loop filter resistor control
225 * PSU_CRL_APB_IOPLL_CFG_RES 0x2
227 * PLL charge pump control
228 * PSU_CRL_APB_IOPLL_CFG_CP 0x4
230 * PLL loop filter high frequency capacitor control
231 * PSU_CRL_APB_IOPLL_CFG_LFHF 0x3
233 * Lock circuit counter setting
234 * PSU_CRL_APB_IOPLL_CFG_LOCK_CNT 0x258
236 * Lock circuit configuration settings for lock windowsize
237 * PSU_CRL_APB_IOPLL_CFG_LOCK_DLY 0x3f
239 * Helper data. Values are to be looked up in a table from Data Sheet
240 * (OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E4B0C82U)
242 PSU_Mask_Write(CRL_APB_IOPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C82U);
243 /*##################################################################### */
249 * Register : IOPLL_CTRL @ 0XFF5E0020
251 * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
252 * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
253 * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
254 * PSU_CRL_APB_IOPLL_CTRL_PRE_SRC 0x0
256 * The integer portion of the feedback divider to the PLL
257 * PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x5a
259 * This turns on the divide by 2 that is inside of the PLL. This does not c
260 * hange the VCO frequency, just the output frequency
261 * PSU_CRL_APB_IOPLL_CTRL_DIV2 0x1
264 * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00015A00U)
266 PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00717F00U, 0x00015A00U);
267 /*##################################################################### */
273 * Register : IOPLL_CTRL @ 0XFF5E0020
275 * Bypasses the PLL clock. The usable clock will be determined from the POS
276 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
277 * clock and 4 cycles of the new clock. This is not usually an issue, but d
278 * esigners must be aware.)
279 * PSU_CRL_APB_IOPLL_CTRL_BYPASS 1
282 * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000008U)
284 PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U);
285 /*##################################################################### */
291 * Register : IOPLL_CTRL @ 0XFF5E0020
293 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
295 * PSU_CRL_APB_IOPLL_CTRL_RESET 1
298 * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000001U)
300 PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U);
301 /*##################################################################### */
307 * Register : IOPLL_CTRL @ 0XFF5E0020
309 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
311 * PSU_CRL_APB_IOPLL_CTRL_RESET 0
314 * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000000U)
316 PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U);
317 /*##################################################################### */
323 * Register : PLL_STATUS @ 0XFF5E0040
326 * PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK 1
327 * (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000001U ,0x00000001U)
329 mask_poll(CRL_APB_PLL_STATUS_OFFSET, 0x00000001U);
331 /*##################################################################### */
337 * Register : IOPLL_CTRL @ 0XFF5E0020
339 * Bypasses the PLL clock. The usable clock will be determined from the POS
340 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
341 * clock and 4 cycles of the new clock. This is not usually an issue, but d
342 * esigners must be aware.)
343 * PSU_CRL_APB_IOPLL_CTRL_BYPASS 0
346 * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000000U)
348 PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U);
349 /*##################################################################### */
352 * Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044
354 * Divisor value for this clock.
355 * PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 0x3
357 * Control for a clock that will be generated in the LPD, but used in the F
358 * PD as a clock source for the peripheral clock muxes.
359 * (OFFSET, MASK, VALUE) (0XFF5E0044, 0x00003F00U ,0x00000300U)
361 PSU_Mask_Write(CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET,
362 0x00003F00U, 0x00000300U);
363 /*##################################################################### */
372 * Register : APLL_CFG @ 0XFD1A0024
374 * PLL loop filter resistor control
375 * PSU_CRF_APB_APLL_CFG_RES 0x2
377 * PLL charge pump control
378 * PSU_CRF_APB_APLL_CFG_CP 0x3
380 * PLL loop filter high frequency capacitor control
381 * PSU_CRF_APB_APLL_CFG_LFHF 0x3
383 * Lock circuit counter setting
384 * PSU_CRF_APB_APLL_CFG_LOCK_CNT 0x258
386 * Lock circuit configuration settings for lock windowsize
387 * PSU_CRF_APB_APLL_CFG_LOCK_DLY 0x3f
389 * Helper data. Values are to be looked up in a table from Data Sheet
390 * (OFFSET, MASK, VALUE) (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U)
392 PSU_Mask_Write(CRF_APB_APLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U);
393 /*##################################################################### */
399 * Register : APLL_CTRL @ 0XFD1A0020
401 * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
402 * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
403 * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
404 * PSU_CRF_APB_APLL_CTRL_PRE_SRC 0x0
406 * The integer portion of the feedback divider to the PLL
407 * PSU_CRF_APB_APLL_CTRL_FBDIV 0x48
409 * This turns on the divide by 2 that is inside of the PLL. This does not c
410 * hange the VCO frequency, just the output frequency
411 * PSU_CRF_APB_APLL_CTRL_DIV2 0x1
414 * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00717F00U ,0x00014800U)
416 PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00717F00U, 0x00014800U);
417 /*##################################################################### */
423 * Register : APLL_CTRL @ 0XFD1A0020
425 * Bypasses the PLL clock. The usable clock will be determined from the POS
426 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
427 * clock and 4 cycles of the new clock. This is not usually an issue, but d
428 * esigners must be aware.)
429 * PSU_CRF_APB_APLL_CTRL_BYPASS 1
432 * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000008U)
434 PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000008U, 0x00000008U);
435 /*##################################################################### */
441 * Register : APLL_CTRL @ 0XFD1A0020
443 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
445 * PSU_CRF_APB_APLL_CTRL_RESET 1
448 * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000001U)
450 PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000001U, 0x00000001U);
451 /*##################################################################### */
457 * Register : APLL_CTRL @ 0XFD1A0020
459 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
461 * PSU_CRF_APB_APLL_CTRL_RESET 0
464 * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000000U)
466 PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000001U, 0x00000000U);
467 /*##################################################################### */
473 * Register : PLL_STATUS @ 0XFD1A0044
476 * PSU_CRF_APB_PLL_STATUS_APLL_LOCK 1
477 * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000001U ,0x00000001U)
479 mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000001U);
481 /*##################################################################### */
487 * Register : APLL_CTRL @ 0XFD1A0020
489 * Bypasses the PLL clock. The usable clock will be determined from the POS
490 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
491 * clock and 4 cycles of the new clock. This is not usually an issue, but d
492 * esigners must be aware.)
493 * PSU_CRF_APB_APLL_CTRL_BYPASS 0
496 * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000000U)
498 PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000008U, 0x00000000U);
499 /*##################################################################### */
502 * Register : APLL_TO_LPD_CTRL @ 0XFD1A0048
504 * Divisor value for this clock.
505 * PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0 0x3
507 * Control for a clock that will be generated in the FPD, but used in the L
508 * PD as a clock source for the peripheral clock muxes.
509 * (OFFSET, MASK, VALUE) (0XFD1A0048, 0x00003F00U ,0x00000300U)
511 PSU_Mask_Write(CRF_APB_APLL_TO_LPD_CTRL_OFFSET,
512 0x00003F00U, 0x00000300U);
513 /*##################################################################### */
522 * Register : DPLL_CFG @ 0XFD1A0030
524 * PLL loop filter resistor control
525 * PSU_CRF_APB_DPLL_CFG_RES 0x2
527 * PLL charge pump control
528 * PSU_CRF_APB_DPLL_CFG_CP 0x3
530 * PLL loop filter high frequency capacitor control
531 * PSU_CRF_APB_DPLL_CFG_LFHF 0x3
533 * Lock circuit counter setting
534 * PSU_CRF_APB_DPLL_CFG_LOCK_CNT 0x258
536 * Lock circuit configuration settings for lock windowsize
537 * PSU_CRF_APB_DPLL_CFG_LOCK_DLY 0x3f
539 * Helper data. Values are to be looked up in a table from Data Sheet
540 * (OFFSET, MASK, VALUE) (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U)
542 PSU_Mask_Write(CRF_APB_DPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U);
543 /*##################################################################### */
549 * Register : DPLL_CTRL @ 0XFD1A002C
551 * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
552 * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
553 * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
554 * PSU_CRF_APB_DPLL_CTRL_PRE_SRC 0x0
556 * The integer portion of the feedback divider to the PLL
557 * PSU_CRF_APB_DPLL_CTRL_FBDIV 0x40
559 * This turns on the divide by 2 that is inside of the PLL. This does not c
560 * hange the VCO frequency, just the output frequency
561 * PSU_CRF_APB_DPLL_CTRL_DIV2 0x1
564 * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00717F00U ,0x00014000U)
566 PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00717F00U, 0x00014000U);
567 /*##################################################################### */
573 * Register : DPLL_CTRL @ 0XFD1A002C
575 * Bypasses the PLL clock. The usable clock will be determined from the POS
576 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
577 * clock and 4 cycles of the new clock. This is not usually an issue, but d
578 * esigners must be aware.)
579 * PSU_CRF_APB_DPLL_CTRL_BYPASS 1
582 * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000008U)
584 PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U);
585 /*##################################################################### */
591 * Register : DPLL_CTRL @ 0XFD1A002C
593 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
595 * PSU_CRF_APB_DPLL_CTRL_RESET 1
598 * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000001U)
600 PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U);
601 /*##################################################################### */
607 * Register : DPLL_CTRL @ 0XFD1A002C
609 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
611 * PSU_CRF_APB_DPLL_CTRL_RESET 0
614 * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000000U)
616 PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U);
617 /*##################################################################### */
623 * Register : PLL_STATUS @ 0XFD1A0044
626 * PSU_CRF_APB_PLL_STATUS_DPLL_LOCK 1
627 * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000002U ,0x00000002U)
629 mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000002U);
631 /*##################################################################### */
637 * Register : DPLL_CTRL @ 0XFD1A002C
639 * Bypasses the PLL clock. The usable clock will be determined from the POS
640 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
641 * clock and 4 cycles of the new clock. This is not usually an issue, but d
642 * esigners must be aware.)
643 * PSU_CRF_APB_DPLL_CTRL_BYPASS 0
646 * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000000U)
648 PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U);
649 /*##################################################################### */
652 * Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C
654 * Divisor value for this clock.
655 * PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 0x2
657 * Control for a clock that will be generated in the FPD, but used in the L
658 * PD as a clock source for the peripheral clock muxes.
659 * (OFFSET, MASK, VALUE) (0XFD1A004C, 0x00003F00U ,0x00000200U)
661 PSU_Mask_Write(CRF_APB_DPLL_TO_LPD_CTRL_OFFSET,
662 0x00003F00U, 0x00000200U);
663 /*##################################################################### */
672 * Register : VPLL_CFG @ 0XFD1A003C
674 * PLL loop filter resistor control
675 * PSU_CRF_APB_VPLL_CFG_RES 0x2
677 * PLL charge pump control
678 * PSU_CRF_APB_VPLL_CFG_CP 0x4
680 * PLL loop filter high frequency capacitor control
681 * PSU_CRF_APB_VPLL_CFG_LFHF 0x3
683 * Lock circuit counter setting
684 * PSU_CRF_APB_VPLL_CFG_LOCK_CNT 0x258
686 * Lock circuit configuration settings for lock windowsize
687 * PSU_CRF_APB_VPLL_CFG_LOCK_DLY 0x3f
689 * Helper data. Values are to be looked up in a table from Data Sheet
690 * (OFFSET, MASK, VALUE) (0XFD1A003C, 0xFE7FEDEFU ,0x7E4B0C82U)
692 PSU_Mask_Write(CRF_APB_VPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C82U);
693 /*##################################################################### */
699 * Register : VPLL_CTRL @ 0XFD1A0038
701 * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
702 * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
703 * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
704 * PSU_CRF_APB_VPLL_CTRL_PRE_SRC 0x0
706 * The integer portion of the feedback divider to the PLL
707 * PSU_CRF_APB_VPLL_CTRL_FBDIV 0x5a
709 * This turns on the divide by 2 that is inside of the PLL. This does not c
710 * hange the VCO frequency, just the output frequency
711 * PSU_CRF_APB_VPLL_CTRL_DIV2 0x1
714 * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00717F00U ,0x00015A00U)
716 PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00717F00U, 0x00015A00U);
717 /*##################################################################### */
723 * Register : VPLL_CTRL @ 0XFD1A0038
725 * Bypasses the PLL clock. The usable clock will be determined from the POS
726 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
727 * clock and 4 cycles of the new clock. This is not usually an issue, but d
728 * esigners must be aware.)
729 * PSU_CRF_APB_VPLL_CTRL_BYPASS 1
732 * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000008U)
734 PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U);
735 /*##################################################################### */
741 * Register : VPLL_CTRL @ 0XFD1A0038
743 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
745 * PSU_CRF_APB_VPLL_CTRL_RESET 1
748 * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000001U)
750 PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U);
751 /*##################################################################### */
757 * Register : VPLL_CTRL @ 0XFD1A0038
759 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
761 * PSU_CRF_APB_VPLL_CTRL_RESET 0
764 * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000000U)
766 PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U);
767 /*##################################################################### */
773 * Register : PLL_STATUS @ 0XFD1A0044
776 * PSU_CRF_APB_PLL_STATUS_VPLL_LOCK 1
777 * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000004U ,0x00000004U)
779 mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000004U);
781 /*##################################################################### */
787 * Register : VPLL_CTRL @ 0XFD1A0038
789 * Bypasses the PLL clock. The usable clock will be determined from the POS
790 * T_SRC field. (This signal may only be toggled after 4 cycles of the old
791 * clock and 4 cycles of the new clock. This is not usually an issue, but d
792 * esigners must be aware.)
793 * PSU_CRF_APB_VPLL_CTRL_BYPASS 0
796 * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000000U)
798 PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U);
799 /*##################################################################### */
802 * Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050
804 * Divisor value for this clock.
805 * PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0 0x3
807 * Control for a clock that will be generated in the FPD, but used in the L
808 * PD as a clock source for the peripheral clock muxes.
809 * (OFFSET, MASK, VALUE) (0XFD1A0050, 0x00003F00U ,0x00000300U)
811 PSU_Mask_Write(CRF_APB_VPLL_TO_LPD_CTRL_OFFSET,
812 0x00003F00U, 0x00000300U);
813 /*##################################################################### */
821 unsigned long psu_clock_init_data(void)
824 * CLOCK CONTROL SLCR REGISTER
827 * Register : GEM3_REF_CTRL @ 0XFF5E005C
829 * Clock active for the RX channel
830 * PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT 0x1
832 * Clock active signal. Switch to 0 to disable the clock
833 * PSU_CRL_APB_GEM3_REF_CTRL_CLKACT 0x1
836 * PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1 0x1
839 * PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0 0xc
841 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
842 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
843 * usually an issue, but designers must be aware.)
844 * PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL 0x0
846 * This register controls this reference clock
847 * (OFFSET, MASK, VALUE) (0XFF5E005C, 0x063F3F07U ,0x06010C00U)
849 PSU_Mask_Write(CRL_APB_GEM3_REF_CTRL_OFFSET,
850 0x063F3F07U, 0x06010C00U);
851 /*##################################################################### */
854 * Register : GEM_TSU_REF_CTRL @ 0XFF5E0100
857 * PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0 0x6
859 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
860 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
861 * usually an issue, but designers must be aware.)
862 * PSU_CRL_APB_GEM_TSU_REF_CTRL_SRCSEL 0x0
865 * PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1 0x1
867 * Clock active signal. Switch to 0 to disable the clock
868 * PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT 0x1
870 * This register controls this reference clock
871 * (OFFSET, MASK, VALUE) (0XFF5E0100, 0x013F3F07U ,0x01010600U)
873 PSU_Mask_Write(CRL_APB_GEM_TSU_REF_CTRL_OFFSET,
874 0x013F3F07U, 0x01010600U);
875 /*##################################################################### */
878 * Register : USB0_BUS_REF_CTRL @ 0XFF5E0060
880 * Clock active signal. Switch to 0 to disable the clock
881 * PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT 0x1
884 * PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1 0x1
887 * PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0 0x6
889 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
890 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
891 * usually an issue, but designers must be aware.)
892 * PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL 0x0
894 * This register controls this reference clock
895 * (OFFSET, MASK, VALUE) (0XFF5E0060, 0x023F3F07U ,0x02010600U)
897 PSU_Mask_Write(CRL_APB_USB0_BUS_REF_CTRL_OFFSET,
898 0x023F3F07U, 0x02010600U);
899 /*##################################################################### */
902 * Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C
904 * Clock active signal. Switch to 0 to disable the clock
905 * PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT 0x1
908 * PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 0x3
911 * PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 0x19
913 * 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af
914 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
915 * usually an issue, but designers must be aware.)
916 * PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL 0x0
918 * This register controls this reference clock
919 * (OFFSET, MASK, VALUE) (0XFF5E004C, 0x023F3F07U ,0x02031900U)
921 PSU_Mask_Write(CRL_APB_USB3_DUAL_REF_CTRL_OFFSET,
922 0x023F3F07U, 0x02031900U);
923 /*##################################################################### */
926 * Register : QSPI_REF_CTRL @ 0XFF5E0068
928 * Clock active signal. Switch to 0 to disable the clock
929 * PSU_CRL_APB_QSPI_REF_CTRL_CLKACT 0x1
932 * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1
935 * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0xc
937 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
938 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
939 * usually an issue, but designers must be aware.)
940 * PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0
942 * This register controls this reference clock
943 * (OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010C00U)
945 PSU_Mask_Write(CRL_APB_QSPI_REF_CTRL_OFFSET,
946 0x013F3F07U, 0x01010C00U);
947 /*##################################################################### */
950 * Register : SDIO1_REF_CTRL @ 0XFF5E0070
952 * Clock active signal. Switch to 0 to disable the clock
953 * PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT 0x1
956 * PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1 0x1
959 * PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x8
961 * 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af
962 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
963 * usually an issue, but designers must be aware.)
964 * PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x0
966 * This register controls this reference clock
967 * (OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010800U)
969 PSU_Mask_Write(CRL_APB_SDIO1_REF_CTRL_OFFSET,
970 0x013F3F07U, 0x01010800U);
971 /*##################################################################### */
974 * Register : SDIO_CLK_CTRL @ 0XFF18030C
976 * MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO
978 * PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL 0
980 * SoC Debug Clock Control
981 * (OFFSET, MASK, VALUE) (0XFF18030C, 0x00020000U ,0x00000000U)
983 PSU_Mask_Write(IOU_SLCR_SDIO_CLK_CTRL_OFFSET,
984 0x00020000U, 0x00000000U);
985 /*##################################################################### */
988 * Register : UART0_REF_CTRL @ 0XFF5E0074
990 * Clock active signal. Switch to 0 to disable the clock
991 * PSU_CRL_APB_UART0_REF_CTRL_CLKACT 0x1
994 * PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1 0x1
997 * PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 0xf
999 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1000 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1001 * usually an issue, but designers must be aware.)
1002 * PSU_CRL_APB_UART0_REF_CTRL_SRCSEL 0x0
1004 * This register controls this reference clock
1005 * (OFFSET, MASK, VALUE) (0XFF5E0074, 0x013F3F07U ,0x01010F00U)
1007 PSU_Mask_Write(CRL_APB_UART0_REF_CTRL_OFFSET,
1008 0x013F3F07U, 0x01010F00U);
1009 /*##################################################################### */
1012 * Register : UART1_REF_CTRL @ 0XFF5E0078
1014 * Clock active signal. Switch to 0 to disable the clock
1015 * PSU_CRL_APB_UART1_REF_CTRL_CLKACT 0x1
1018 * PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1 0x1
1021 * PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 0xf
1023 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1024 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1025 * usually an issue, but designers must be aware.)
1026 * PSU_CRL_APB_UART1_REF_CTRL_SRCSEL 0x0
1028 * This register controls this reference clock
1029 * (OFFSET, MASK, VALUE) (0XFF5E0078, 0x013F3F07U ,0x01010F00U)
1031 PSU_Mask_Write(CRL_APB_UART1_REF_CTRL_OFFSET,
1032 0x013F3F07U, 0x01010F00U);
1033 /*##################################################################### */
1036 * Register : I2C0_REF_CTRL @ 0XFF5E0120
1038 * Clock active signal. Switch to 0 to disable the clock
1039 * PSU_CRL_APB_I2C0_REF_CTRL_CLKACT 0x1
1042 * PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1 0x1
1045 * PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0 0xf
1047 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1048 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1049 * usually an issue, but designers must be aware.)
1050 * PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL 0x0
1052 * This register controls this reference clock
1053 * (OFFSET, MASK, VALUE) (0XFF5E0120, 0x013F3F07U ,0x01010F00U)
1055 PSU_Mask_Write(CRL_APB_I2C0_REF_CTRL_OFFSET,
1056 0x013F3F07U, 0x01010F00U);
1057 /*##################################################################### */
1060 * Register : I2C1_REF_CTRL @ 0XFF5E0124
1062 * Clock active signal. Switch to 0 to disable the clock
1063 * PSU_CRL_APB_I2C1_REF_CTRL_CLKACT 0x1
1066 * PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1 0x1
1069 * PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 0xf
1071 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1072 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1073 * usually an issue, but designers must be aware.)
1074 * PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL 0x0
1076 * This register controls this reference clock
1077 * (OFFSET, MASK, VALUE) (0XFF5E0124, 0x013F3F07U ,0x01010F00U)
1079 PSU_Mask_Write(CRL_APB_I2C1_REF_CTRL_OFFSET,
1080 0x013F3F07U, 0x01010F00U);
1081 /*##################################################################### */
1084 * Register : CAN1_REF_CTRL @ 0XFF5E0088
1086 * Clock active signal. Switch to 0 to disable the clock
1087 * PSU_CRL_APB_CAN1_REF_CTRL_CLKACT 0x1
1090 * PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1 0x1
1093 * PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0 0xf
1095 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1096 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1097 * usually an issue, but designers must be aware.)
1098 * PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL 0x0
1100 * This register controls this reference clock
1101 * (OFFSET, MASK, VALUE) (0XFF5E0088, 0x013F3F07U ,0x01010F00U)
1103 PSU_Mask_Write(CRL_APB_CAN1_REF_CTRL_OFFSET,
1104 0x013F3F07U, 0x01010F00U);
1105 /*##################################################################### */
1108 * Register : CPU_R5_CTRL @ 0XFF5E0090
1110 * Turing this off will shut down the OCM, some parts of the APM, and preve
1111 * nt transactions going from the FPD to the LPD and could lead to system h
1113 * PSU_CRL_APB_CPU_R5_CTRL_CLKACT 0x1
1116 * PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 0x3
1118 * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
1119 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1120 * usually an issue, but designers must be aware.)
1121 * PSU_CRL_APB_CPU_R5_CTRL_SRCSEL 0x2
1123 * This register controls this reference clock
1124 * (OFFSET, MASK, VALUE) (0XFF5E0090, 0x01003F07U ,0x01000302U)
1126 PSU_Mask_Write(CRL_APB_CPU_R5_CTRL_OFFSET, 0x01003F07U, 0x01000302U);
1127 /*##################################################################### */
1130 * Register : IOU_SWITCH_CTRL @ 0XFF5E009C
1132 * Clock active signal. Switch to 0 to disable the clock
1133 * PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT 0x1
1136 * PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 0x6
1138 * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
1139 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1140 * usually an issue, but designers must be aware.)
1141 * PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL 0x2
1143 * This register controls this reference clock
1144 * (OFFSET, MASK, VALUE) (0XFF5E009C, 0x01003F07U ,0x01000602U)
1146 PSU_Mask_Write(CRL_APB_IOU_SWITCH_CTRL_OFFSET,
1147 0x01003F07U, 0x01000602U);
1148 /*##################################################################### */
1151 * Register : PCAP_CTRL @ 0XFF5E00A4
1153 * Clock active signal. Switch to 0 to disable the clock
1154 * PSU_CRL_APB_PCAP_CTRL_CLKACT 0x1
1157 * PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x8
1159 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1160 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1161 * usually an issue, but designers must be aware.)
1162 * PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x0
1164 * This register controls this reference clock
1165 * (OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000800U)
1167 PSU_Mask_Write(CRL_APB_PCAP_CTRL_OFFSET, 0x01003F07U, 0x01000800U);
1168 /*##################################################################### */
1171 * Register : LPD_SWITCH_CTRL @ 0XFF5E00A8
1173 * Clock active signal. Switch to 0 to disable the clock
1174 * PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT 0x1
1177 * PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x3
1179 * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
1180 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1181 * usually an issue, but designers must be aware.)
1182 * PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL 0x2
1184 * This register controls this reference clock
1185 * (OFFSET, MASK, VALUE) (0XFF5E00A8, 0x01003F07U ,0x01000302U)
1187 PSU_Mask_Write(CRL_APB_LPD_SWITCH_CTRL_OFFSET,
1188 0x01003F07U, 0x01000302U);
1189 /*##################################################################### */
1192 * Register : LPD_LSBUS_CTRL @ 0XFF5E00AC
1194 * Clock active signal. Switch to 0 to disable the clock
1195 * PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT 0x1
1198 * PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 0xf
1200 * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
1201 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1202 * usually an issue, but designers must be aware.)
1203 * PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL 0x2
1205 * This register controls this reference clock
1206 * (OFFSET, MASK, VALUE) (0XFF5E00AC, 0x01003F07U ,0x01000F02U)
1208 PSU_Mask_Write(CRL_APB_LPD_LSBUS_CTRL_OFFSET,
1209 0x01003F07U, 0x01000F02U);
1210 /*##################################################################### */
1213 * Register : DBG_LPD_CTRL @ 0XFF5E00B0
1215 * Clock active signal. Switch to 0 to disable the clock
1216 * PSU_CRL_APB_DBG_LPD_CTRL_CLKACT 0x1
1219 * PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 0x6
1221 * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
1222 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1223 * usually an issue, but designers must be aware.)
1224 * PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL 0x2
1226 * This register controls this reference clock
1227 * (OFFSET, MASK, VALUE) (0XFF5E00B0, 0x01003F07U ,0x01000602U)
1229 PSU_Mask_Write(CRL_APB_DBG_LPD_CTRL_OFFSET,
1230 0x01003F07U, 0x01000602U);
1231 /*##################################################################### */
1234 * Register : ADMA_REF_CTRL @ 0XFF5E00B8
1236 * Clock active signal. Switch to 0 to disable the clock
1237 * PSU_CRL_APB_ADMA_REF_CTRL_CLKACT 0x1
1240 * PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 0x3
1242 * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
1243 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1244 * usually an issue, but designers must be aware.)
1245 * PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL 0x2
1247 * This register controls this reference clock
1248 * (OFFSET, MASK, VALUE) (0XFF5E00B8, 0x01003F07U ,0x01000302U)
1250 PSU_Mask_Write(CRL_APB_ADMA_REF_CTRL_OFFSET,
1251 0x01003F07U, 0x01000302U);
1252 /*##################################################################### */
1255 * Register : PL0_REF_CTRL @ 0XFF5E00C0
1257 * Clock active signal. Switch to 0 to disable the clock
1258 * PSU_CRL_APB_PL0_REF_CTRL_CLKACT 0x1
1261 * PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1 0x1
1264 * PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0 0xf
1266 * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
1267 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1268 * usually an issue, but designers must be aware.)
1269 * PSU_CRL_APB_PL0_REF_CTRL_SRCSEL 0x0
1271 * This register controls this reference clock
1272 * (OFFSET, MASK, VALUE) (0XFF5E00C0, 0x013F3F07U ,0x01010F00U)
1274 PSU_Mask_Write(CRL_APB_PL0_REF_CTRL_OFFSET,
1275 0x013F3F07U, 0x01010F00U);
1276 /*##################################################################### */
1279 * Register : AMS_REF_CTRL @ 0XFF5E0108
1282 * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 0x1
1285 * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1e
1287 * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
1288 * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
1289 * usually an issue, but designers must be aware.)
1290 * PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0x2
1292 * Clock active signal. Switch to 0 to disable the clock
1293 * PSU_CRL_APB_AMS_REF_CTRL_CLKACT 0x1
1295 * This register controls this reference clock
1296 * (OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011E02U)
1298 PSU_Mask_Write(CRL_APB_AMS_REF_CTRL_OFFSET,
1299 0x013F3F07U, 0x01011E02U);
1300 /*##################################################################### */
1303 * Register : DLL_REF_CTRL @ 0XFF5E0104
1305 * 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles
1306 * of the old clock and 4 cycles of the new clock. This is not usually an
1307 * issue, but designers must be aware.)
1308 * PSU_CRL_APB_DLL_REF_CTRL_SRCSEL 0
1310 * This register controls this reference clock
1311 * (OFFSET, MASK, VALUE) (0XFF5E0104, 0x00000007U ,0x00000000U)
1313 PSU_Mask_Write(CRL_APB_DLL_REF_CTRL_OFFSET,
1314 0x00000007U, 0x00000000U);
1315 /*##################################################################### */
1318 * Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128
1321 * PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 0xf
1323 * 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may
1324 * only be toggled after 4 cycles of the old clock and 4 cycles of the new
1325 * clock. This is not usually an issue, but designers must be aware.)
1326 * PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL 0x0
1328 * Clock active signal. Switch to 0 to disable the clock
1329 * PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1
1331 * This register controls this reference clock
1332 * (OFFSET, MASK, VALUE) (0XFF5E0128, 0x01003F07U ,0x01000F00U)
1334 PSU_Mask_Write(CRL_APB_TIMESTAMP_REF_CTRL_OFFSET,
1335 0x01003F07U, 0x01000F00U);
1336 /*##################################################################### */
1339 * Register : SATA_REF_CTRL @ 0XFD1A00A0
1341 * 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog
1342 * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
1343 * is not usually an issue, but designers must be aware.)
1344 * PSU_CRF_APB_SATA_REF_CTRL_SRCSEL 0x0
1346 * Clock active signal. Switch to 0 to disable the clock
1347 * PSU_CRF_APB_SATA_REF_CTRL_CLKACT 0x1
1350 * PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0 0x2
1352 * This register controls this reference clock
1353 * (OFFSET, MASK, VALUE) (0XFD1A00A0, 0x01003F07U ,0x01000200U)
1355 PSU_Mask_Write(CRF_APB_SATA_REF_CTRL_OFFSET,
1356 0x01003F07U, 0x01000200U);
1357 /*##################################################################### */
1360 * Register : PCIE_REF_CTRL @ 0XFD1A00B4
1362 * 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only
1363 * be toggled after 4 cycles of the old clock and 4 cycles of the new cloc
1364 * k. This is not usually an issue, but designers must be aware.)
1365 * PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL 0x0
1367 * Clock active signal. Switch to 0 to disable the clock
1368 * PSU_CRF_APB_PCIE_REF_CTRL_CLKACT 0x1
1371 * PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0 0x2
1373 * This register controls this reference clock
1374 * (OFFSET, MASK, VALUE) (0XFD1A00B4, 0x01003F07U ,0x01000200U)
1376 PSU_Mask_Write(CRF_APB_PCIE_REF_CTRL_OFFSET,
1377 0x01003F07U, 0x01000200U);
1378 /*##################################################################### */
1381 * Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070
1384 * PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1 0x1
1387 * PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 0x5
1389 * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T
1390 * his signal may only be toggled after 4 cycles of the old clock and 4 cyc
1391 * les of the new clock. This is not usually an issue, but designers must b
1393 * PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL 0x0
1395 * Clock active signal. Switch to 0 to disable the clock
1396 * PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT 0x1
1398 * This register controls this reference clock
1399 * (OFFSET, MASK, VALUE) (0XFD1A0070, 0x013F3F07U ,0x01010500U)
1401 PSU_Mask_Write(CRF_APB_DP_VIDEO_REF_CTRL_OFFSET,
1402 0x013F3F07U, 0x01010500U);
1403 /*##################################################################### */
1406 * Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074
1409 * PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1 0x1
1412 * PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0 0xf
1414 * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T
1415 * his signal may only be toggled after 4 cycles of the old clock and 4 cyc
1416 * les of the new clock. This is not usually an issue, but designers must b
1418 * PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL 0x3
1420 * Clock active signal. Switch to 0 to disable the clock
1421 * PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT 0x1
1423 * This register controls this reference clock
1424 * (OFFSET, MASK, VALUE) (0XFD1A0074, 0x013F3F07U ,0x01010F03U)
1426 PSU_Mask_Write(CRF_APB_DP_AUDIO_REF_CTRL_OFFSET,
1427 0x013F3F07U, 0x01010F03U);
1428 /*##################################################################### */
1431 * Register : DP_STC_REF_CTRL @ 0XFD1A007C
1434 * PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1 0x1
1437 * PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0 0xe
1439 * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg
1440 * led after 4 cycles of the old clock and 4 cycles of the new clock. This
1441 * is not usually an issue, but designers must be aware.)
1442 * PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL 0x3
1444 * Clock active signal. Switch to 0 to disable the clock
1445 * PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT 0x1
1447 * This register controls this reference clock
1448 * (OFFSET, MASK, VALUE) (0XFD1A007C, 0x013F3F07U ,0x01010E03U)
1450 PSU_Mask_Write(CRF_APB_DP_STC_REF_CTRL_OFFSET,
1451 0x013F3F07U, 0x01010E03U);
1452 /*##################################################################### */
1455 * Register : ACPU_CTRL @ 0XFD1A0060
1458 * PSU_CRF_APB_ACPU_CTRL_DIVISOR0 0x1
1460 * 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft
1461 * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
1462 * usually an issue, but designers must be aware.)
1463 * PSU_CRF_APB_ACPU_CTRL_SRCSEL 0x0
1465 * Clock active signal. Switch to 0 to disable the clock. For the half spee
1467 * PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF 0x1
1469 * Clock active signal. Switch to 0 to disable the clock. For the full spee
1470 * d ACPUX Clock. This will shut off the high speed clock to the entire APU
1471 * PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL 0x1
1473 * This register controls this reference clock
1474 * (OFFSET, MASK, VALUE) (0XFD1A0060, 0x03003F07U ,0x03000100U)
1476 PSU_Mask_Write(CRF_APB_ACPU_CTRL_OFFSET, 0x03003F07U, 0x03000100U);
1477 /*##################################################################### */
1480 * Register : DBG_FPD_CTRL @ 0XFD1A0068
1483 * PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0 0x2
1485 * 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog
1486 * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
1487 * is not usually an issue, but designers must be aware.)
1488 * PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL 0x0
1490 * Clock active signal. Switch to 0 to disable the clock
1491 * PSU_CRF_APB_DBG_FPD_CTRL_CLKACT 0x1
1493 * This register controls this reference clock
1494 * (OFFSET, MASK, VALUE) (0XFD1A0068, 0x01003F07U ,0x01000200U)
1496 PSU_Mask_Write(CRF_APB_DBG_FPD_CTRL_OFFSET,
1497 0x01003F07U, 0x01000200U);
1498 /*##################################################################### */
1501 * Register : DDR_CTRL @ 0XFD1A0080
1504 * PSU_CRF_APB_DDR_CTRL_DIVISOR0 0x2
1506 * 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles
1507 * of the old clock and 4 cycles of the new clock. This is not usually an i
1508 * ssue, but designers must be aware.)
1509 * PSU_CRF_APB_DDR_CTRL_SRCSEL 0x0
1511 * This register controls this reference clock
1512 * (OFFSET, MASK, VALUE) (0XFD1A0080, 0x00003F07U ,0x00000200U)
1514 PSU_Mask_Write(CRF_APB_DDR_CTRL_OFFSET, 0x00003F07U, 0x00000200U);
1515 /*##################################################################### */
1518 * Register : GPU_REF_CTRL @ 0XFD1A0084
1521 * PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0 0x1
1523 * 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog
1524 * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
1525 * is not usually an issue, but designers must be aware.)
1526 * PSU_CRF_APB_GPU_REF_CTRL_SRCSEL 0x0
1528 * Clock active signal. Switch to 0 to disable the clock, which will stop c
1529 * lock for GPU (and both Pixel Processors).
1530 * PSU_CRF_APB_GPU_REF_CTRL_CLKACT 0x1
1532 * Clock active signal for Pixel Processor. Switch to 0 to disable the cloc
1533 * k only to this Pixel Processor
1534 * PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT 0x1
1536 * Clock active signal for Pixel Processor. Switch to 0 to disable the cloc
1537 * k only to this Pixel Processor
1538 * PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT 0x1
1540 * This register controls this reference clock
1541 * (OFFSET, MASK, VALUE) (0XFD1A0084, 0x07003F07U ,0x07000100U)
1543 PSU_Mask_Write(CRF_APB_GPU_REF_CTRL_OFFSET,
1544 0x07003F07U, 0x07000100U);
1545 /*##################################################################### */
1548 * Register : GDMA_REF_CTRL @ 0XFD1A00B8
1551 * PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0 0x2
1553 * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
1554 * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
1555 * usually an issue, but designers must be aware.)
1556 * PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL 0x0
1558 * Clock active signal. Switch to 0 to disable the clock
1559 * PSU_CRF_APB_GDMA_REF_CTRL_CLKACT 0x1
1561 * This register controls this reference clock
1562 * (OFFSET, MASK, VALUE) (0XFD1A00B8, 0x01003F07U ,0x01000200U)
1564 PSU_Mask_Write(CRF_APB_GDMA_REF_CTRL_OFFSET,
1565 0x01003F07U, 0x01000200U);
1566 /*##################################################################### */
1569 * Register : DPDMA_REF_CTRL @ 0XFD1A00BC
1572 * PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0 0x2
1574 * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
1575 * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
1576 * usually an issue, but designers must be aware.)
1577 * PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL 0x0
1579 * Clock active signal. Switch to 0 to disable the clock
1580 * PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT 0x1
1582 * This register controls this reference clock
1583 * (OFFSET, MASK, VALUE) (0XFD1A00BC, 0x01003F07U ,0x01000200U)
1585 PSU_Mask_Write(CRF_APB_DPDMA_REF_CTRL_OFFSET,
1586 0x01003F07U, 0x01000200U);
1587 /*##################################################################### */
1590 * Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0
1593 * PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0 0x2
1595 * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
1596 * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
1597 * usually an issue, but designers must be aware.)
1598 * PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL 0x3
1600 * Clock active signal. Switch to 0 to disable the clock
1601 * PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT 0x1
1603 * This register controls this reference clock
1604 * (OFFSET, MASK, VALUE) (0XFD1A00C0, 0x01003F07U ,0x01000203U)
1606 PSU_Mask_Write(CRF_APB_TOPSW_MAIN_CTRL_OFFSET,
1607 0x01003F07U, 0x01000203U);
1608 /*##################################################################### */
1611 * Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4
1614 * PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0 0x5
1616 * 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog
1617 * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
1618 * is not usually an issue, but designers must be aware.)
1619 * PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL 0x2
1621 * Clock active signal. Switch to 0 to disable the clock
1622 * PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT 0x1
1624 * This register controls this reference clock
1625 * (OFFSET, MASK, VALUE) (0XFD1A00C4, 0x01003F07U ,0x01000502U)
1627 PSU_Mask_Write(CRF_APB_TOPSW_LSBUS_CTRL_OFFSET,
1628 0x01003F07U, 0x01000502U);
1629 /*##################################################################### */
1632 * Register : DBG_TSTMP_CTRL @ 0XFD1A00F8
1635 * PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0 0x2
1637 * 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog
1638 * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
1639 * is not usually an issue, but designers must be aware.)
1640 * PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL 0x0
1642 * This register controls this reference clock
1643 * (OFFSET, MASK, VALUE) (0XFD1A00F8, 0x00003F07U ,0x00000200U)
1645 PSU_Mask_Write(CRF_APB_DBG_TSTMP_CTRL_OFFSET,
1646 0x00003F07U, 0x00000200U);
1647 /*##################################################################### */
1650 * Register : IOU_TTC_APB_CLK @ 0XFF180380
1652 * 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se
1653 * lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5
1654 * clock for the APB interface of TTC0
1655 * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL 0
1657 * 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se
1658 * lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5
1659 * clock for the APB interface of TTC1
1660 * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL 0
1662 * 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se
1663 * lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5
1664 * clock for the APB interface of TTC2
1665 * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL 0
1667 * 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se
1668 * lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5
1669 * clock for the APB interface of TTC3
1670 * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL 0
1672 * TTC APB clock select
1673 * (OFFSET, MASK, VALUE) (0XFF180380, 0x000000FFU ,0x00000000U)
1675 PSU_Mask_Write(IOU_SLCR_IOU_TTC_APB_CLK_OFFSET,
1676 0x000000FFU, 0x00000000U);
1677 /*##################################################################### */
1680 * Register : WDT_CLK_SEL @ 0XFD610100
1682 * System watchdog timer clock source selection: 0: Internal APB clock 1: E
1683 * xternal (PL clock via EMIO or Pinout clock via MIO)
1684 * PSU_FPD_SLCR_WDT_CLK_SEL_SELECT 0
1686 * SWDT clock source select
1687 * (OFFSET, MASK, VALUE) (0XFD610100, 0x00000001U ,0x00000000U)
1689 PSU_Mask_Write(FPD_SLCR_WDT_CLK_SEL_OFFSET,
1690 0x00000001U, 0x00000000U);
1691 /*##################################################################### */
1694 * Register : WDT_CLK_SEL @ 0XFF180300
1696 * System watchdog timer clock source selection: 0: internal clock APB cloc
1697 * k 1: external clock from PL via EMIO, or from pinout via MIO
1698 * PSU_IOU_SLCR_WDT_CLK_SEL_SELECT 0
1700 * SWDT clock source select
1701 * (OFFSET, MASK, VALUE) (0XFF180300, 0x00000001U ,0x00000000U)
1703 PSU_Mask_Write(IOU_SLCR_WDT_CLK_SEL_OFFSET,
1704 0x00000001U, 0x00000000U);
1705 /*##################################################################### */
1708 * Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050
1710 * System watchdog timer clock source selection: 0: internal clock APB cloc
1711 * k 1: external clock pss_ref_clk
1712 * PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT 0
1714 * SWDT clock source select
1715 * (OFFSET, MASK, VALUE) (0XFF410050, 0x00000001U ,0x00000000U)
1717 PSU_Mask_Write(LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET,
1718 0x00000001U, 0x00000000U);
1719 /*##################################################################### */
1724 unsigned long psu_ddr_init_data(void)
1727 * DDR INITIALIZATION
1730 * DDR CONTROLLER RESET
1733 * Register : RST_DDR_SS @ 0XFD1A0108
1735 * DDR block level reset inside of the DDR Sub System
1736 * PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X1
1738 * DDR sub system block level reset
1739 * (OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000008U)
1741 PSU_Mask_Write(CRF_APB_RST_DDR_SS_OFFSET, 0x00000008U, 0x00000008U);
1742 /*##################################################################### */
1745 * Register : MSTR @ 0XFD070000
1747 * Indicates the configuration of the device used in the system. - 00 - x4
1748 * device - 01 - x8 device - 10 - x16 device - 11 - x32 device
1749 * PSU_DDRC_MSTR_DEVICE_CONFIG 0x1
1751 * Choose which registers are used. - 0 - Original registers - 1 - Shadow r
1753 * PSU_DDRC_MSTR_FREQUENCY_MODE 0x0
1755 * Only present for multi-rank configurations. Each bit represents one rank
1756 * . For two-rank configurations, only bits[25:24] are present. - 1 - popul
1757 * ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow
1758 * ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others -
1759 * Reserved. For 4 ranks following combinations are legal: - 0001 - One ran
1760 * k - 0011 - Two ranks - 1111 - Four ranks
1761 * PSU_DDRC_MSTR_ACTIVE_RANKS 0x1
1763 * SDRAM burst length used: - 0001 - Burst length of 2 (only supported for
1764 * mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur
1765 * st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other
1766 * values are reserved. This controls the burst size used to access the SDR
1767 * AM. This must match the burst length mode register setting in the SDRAM.
1768 * (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100)
1769 * Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH
1770 * is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1
1771 * PSU_DDRC_MSTR_BURST_RDWR 0x4
1773 * Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low
1774 * frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for
1775 * normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC
1776 * TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi
1777 * s bit must be set to '0'.
1778 * PSU_DDRC_MSTR_DLL_OFF_MODE 0x0
1780 * Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full
1781 * DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter
1782 * DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is
1783 * only supported when the SDRAM bus width is a multiple of 16, and quarter
1784 * bus width mode is only supported when the SDRAM bus width is a multiple
1785 * of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid
1786 * th refers to DQ bus width (excluding any ECC width).
1787 * PSU_DDRC_MSTR_DATA_BUS_WIDTH 0x0
1789 * 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D
1790 * RAM in normal mode (1N). This register can be changed, only when the Con
1791 * troller is in self-refresh mode. This signal must be set the same value
1792 * as MR3 bit A3. Note: Geardown mode is not supported if the configuration
1793 * parameter MEMC_CMD_RTN2IDLE is set
1794 * PSU_DDRC_MSTR_GEARDOWN_MODE 0x0
1796 * If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin
1797 * g, all command signals (except chip select) are held for 2 clocks on the
1798 * SDRAM bus. Chip select is asserted on the second cycle of the command N
1799 * ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti
1800 * ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i
1801 * s set Note: 2T timing is not supported in DDR4 geardown mode.
1802 * PSU_DDRC_MSTR_EN_2T_TIMING_MODE 0x0
1804 * When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci
1805 * sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full
1806 * bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer
1807 * cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is
1808 * disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl
1809 * ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported
1810 * , and this bit must be set to '0'
1811 * PSU_DDRC_MSTR_BURSTCHOP 0x0
1813 * Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d
1814 * evice in use Present only in designs configured to support LPDDR4.
1815 * PSU_DDRC_MSTR_LPDDR4 0x0
1817 * Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device
1818 * in use Present only in designs configured to support DDR4.
1819 * PSU_DDRC_MSTR_DDR4 0x1
1821 * Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d
1822 * evice in use Present only in designs configured to support LPDDR3.
1823 * PSU_DDRC_MSTR_LPDDR3 0x0
1825 * Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d
1826 * evice in use Present only in designs configured to support LPDDR2.
1827 * PSU_DDRC_MSTR_LPDDR2 0x0
1829 * Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de
1830 * vice in use Only present in designs that support DDR3.
1831 * PSU_DDRC_MSTR_DDR3 0x0
1834 * (OFFSET, MASK, VALUE) (0XFD070000, 0xE30FBE3DU ,0x41040010U)
1836 PSU_Mask_Write(DDRC_MSTR_OFFSET, 0xE30FBE3DU, 0x41040010U);
1837 /*##################################################################### */
1840 * Register : MRCTRL0 @ 0XFD070010
1842 * Setting this register bit to 1 triggers a mode register read or write op
1843 * eration. When the MR operation is complete, the uMCTL2 automatically cle
1844 * ars this bit. The other register fields of this register must be written
1845 * in a separate APB transaction, before setting this mr_wr bit. It is rec
1846 * ommended NOT to set this signal if in Init, Deep power-down or MPSM oper
1848 * PSU_DDRC_MRCTRL0_MR_WR 0x0
1850 * Address of the mode register that is to be written to. - 0000 - MR0 - 00
1851 * 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR
1852 * 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data
1853 * for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als
1854 * o used for writing to control words of RDIMMs. In that case, it correspo
1855 * nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[
1856 * 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a
1857 * s the bit[2:0] must be set to an appropriate value which is considered b
1858 * oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R
1860 * PSU_DDRC_MRCTRL0_MR_ADDR 0x0
1862 * Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire
1863 * d to access all ranks, so all bits should be set to 1. However, for mult
1864 * i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess
1865 * ary to access ranks individually. Examples (assume uMCTL2 is configured
1866 * for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x
1867 * 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran
1869 * PSU_DDRC_MRCTRL0_MR_RANK 0x3
1871 * Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b
1872 * efore automatic SDRAM initialization routine or not. For DDR4, this bit
1873 * can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init
1874 * ialization. For LPDDR4, this bit can be used to program additional mode
1875 * registers before automatic SDRAM initialization if necessary. Note: This
1876 * must be cleared to 0 after completing Software operation. Otherwise, SD
1877 * RAM initialization routine will not re-start. - 0 - Software interventio
1878 * n is not allowed - 1 - Software intervention is allowed
1879 * PSU_DDRC_MRCTRL0_SW_INIT_INT 0x0
1881 * Indicates whether the mode register operation is MRS in PDA mode or not
1882 * - 0 - MRS - 1 - MRS in Per DRAM Addressability mode
1883 * PSU_DDRC_MRCTRL0_PDA_EN 0x0
1885 * Indicates whether the mode register operation is MRS or WR/RD for MPR (o
1886 * nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR
1887 * PSU_DDRC_MRCTRL0_MPR_EN 0x0
1889 * Indicates whether the mode register operation is read or write. Only use
1890 * d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read
1891 * PSU_DDRC_MRCTRL0_MR_TYPE 0x0
1893 * Mode Register Read/Write Control Register 0. Note: Do not enable more th
1894 * an one of the following fields simultaneously: - sw_init_int - pda_en -
1896 * (OFFSET, MASK, VALUE) (0XFD070010, 0x8000F03FU ,0x00000030U)
1898 PSU_Mask_Write(DDRC_MRCTRL0_OFFSET, 0x8000F03FU, 0x00000030U);
1899 /*##################################################################### */
1902 * Register : DERATEEN @ 0XFD070020
1904 * Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us
1905 * es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d
1906 * esigns configured to support LPDDR4. The required number of cycles for d
1907 * erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p
1908 * eriod, and rounding up the next integer.
1909 * PSU_DDRC_DERATEEN_RC_DERATE_VALUE 0x2
1911 * Derate byte Present only in designs configured to support LPDDR2/LPDDR3/
1912 * LPDDR4 Indicates which byte of the MRR data is used for derating. The ma
1913 * ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.
1914 * PSU_DDRC_DERATEEN_DERATE_BYTE 0x0
1916 * Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl
1917 * y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all
1918 * LPDDR2 speed grades as derating value of +1.875 ns is less than a core_
1919 * ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8
1920 * 75 ns is less than a core_ddrc_core_clk period or not.
1921 * PSU_DDRC_DERATEEN_DERATE_VALUE 0x0
1923 * Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin
1924 * g parameter derating is enabled using MR4 read value. Present only in de
1925 * signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set
1926 * to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
1927 * PSU_DDRC_DERATEEN_DERATE_ENABLE 0x0
1929 * Temperature Derate Enable Register
1930 * (OFFSET, MASK, VALUE) (0XFD070020, 0x000003F3U ,0x00000200U)
1932 PSU_Mask_Write(DDRC_DERATEEN_OFFSET, 0x000003F3U, 0x00000200U);
1933 /*##################################################################### */
1936 * Register : DERATEINT @ 0XFD070024
1938 * Interval between two MR4 reads, used to derate the timing parameters. Pr
1939 * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r
1940 * egister must not be set to zero
1941 * PSU_DDRC_DERATEINT_MR4_READ_INTERVAL 0x800000
1943 * Temperature Derate Interval Register
1944 * (OFFSET, MASK, VALUE) (0XFD070024, 0xFFFFFFFFU ,0x00800000U)
1946 PSU_Mask_Write(DDRC_DERATEINT_OFFSET, 0xFFFFFFFFU, 0x00800000U);
1947 /*##################################################################### */
1950 * Register : PWRCTL @ 0XFD070030
1952 * Self refresh state is an intermediate state to enter to Self refresh pow
1953 * er down state or exit Self refresh power down state for LPDDR4. This reg
1954 * ister controls transition from the Self refresh state. - 1 - Prohibit tr
1955 * ansition from Self refresh state - 0 - Allow transition from Self refres
1957 * PSU_DDRC_PWRCTL_STAY_IN_SELFREF 0x0
1959 * A value of 1 to this register causes system to move to Self Refresh stat
1960 * e immediately, as long as it is not in INIT or DPD/MPSM operating_mode.
1961 * This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa
1962 * re Entry to Self Refresh - 0 - Software Exit from Self Refresh
1963 * PSU_DDRC_PWRCTL_SELFREF_SW 0x0
1965 * When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode
1966 * when the transaction store is empty. This register must be reset to '0'
1967 * to bring uMCTL2 out of maximum power saving mode. Present only in desig
1968 * ns configured to support DDR4. For non-DDR4, this register should not be
1969 * set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if
1970 * the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r
1971 * equires the chip-select signal to toggle. FOR PERFORMANCE ONLY.
1972 * PSU_DDRC_PWRCTL_MPSM_EN 0x0
1974 * Enable the assertion of dfi_dram_clk_disable whenever a clock is not req
1975 * uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted.
1976 * Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only
1977 * be asserted in Self Refresh. In DDR4, can be asserted in following: - i
1978 * n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca
1979 * n be asserted in following: - in Self Refresh - in Power Down - in Deep
1980 * Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse
1981 * rted in following: - in Self Refresh Power Down - in Power Down - during
1982 * Normal operation (Clock Stop)
1983 * PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE 0x0
1985 * When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the
1986 * transaction store is empty. This register must be reset to '0' to bring
1987 * uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM
1988 * initialization on deep power-down exit. Present only in designs configu
1989 * red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD
1990 * DR3, this register should not be set to 1. FOR PERFORMANCE ONLY.
1991 * PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN 0x0
1993 * If true then the uMCTL2 goes into power-down after a programmable number
1994 * of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_
1995 * x32). This register bit may be re-programmed during the course of normal
1997 * PSU_DDRC_PWRCTL_POWERDOWN_EN 0x0
1999 * If true then the uMCTL2 puts the SDRAM into Self Refresh after a program
2000 * mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG.
2001 * selfref_to_x32)'. This register bit may be re-programmed during the cour
2002 * se of normal operation.
2003 * PSU_DDRC_PWRCTL_SELFREF_EN 0x0
2005 * Low Power Control Register
2006 * (OFFSET, MASK, VALUE) (0XFD070030, 0x0000007FU ,0x00000000U)
2008 PSU_Mask_Write(DDRC_PWRCTL_OFFSET, 0x0000007FU, 0x00000000U);
2009 /*##################################################################### */
2012 * Register : PWRTMG @ 0XFD070034
2014 * After this many clocks of NOP or deselect the uMCTL2 automatically puts
2015 * the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_
2016 * en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
2017 * PSU_DDRC_PWRTMG_SELFREF_TO_X32 0x40
2019 * Minimum deep power-down time. For mDDR, value from the JEDEC specificati
2020 * on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL
2021 * .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE
2022 * C specification is 500us. Unit: Multiples of 4096 clocks. Present only i
2023 * n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE
2025 * PSU_DDRC_PWRTMG_T_DPD_X4096 0x84
2027 * After this many clocks of NOP or deselect the uMCTL2 automatically puts
2028 * the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_
2029 * en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.
2030 * PSU_DDRC_PWRTMG_POWERDOWN_TO_X32 0x10
2032 * Low Power Timing Register
2033 * (OFFSET, MASK, VALUE) (0XFD070034, 0x00FFFF1FU ,0x00408410U)
2035 PSU_Mask_Write(DDRC_PWRTMG_OFFSET, 0x00FFFF1FU, 0x00408410U);
2036 /*##################################################################### */
2039 * Register : RFSHCTL0 @ 0XFD070050
2041 * Threshold value in number of clock cycles before the critical refresh or
2042 * page timer expires. A critical refresh is to be issued before this thre
2043 * shold is reached. It is recommended that this not be changed from the de
2044 * fault value, currently shown as 0x2. It must always be less than interna
2045 * lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u
2046 * sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i
2047 * s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n
2048 * om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo
2050 * PSU_DDRC_RFSHCTL0_REFRESH_MARGIN 0x2
2052 * If the refresh timer (tRFCnom, also known as tREFI) has expired at least
2053 * once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then
2054 * a speculative refresh may be performed. A speculative refresh is a refr
2055 * esh performed at a time when refresh would be useful, but before it is a
2056 * bsolutely required. When the SDRAM bus is idle for a period of time dete
2057 * rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired
2058 * at least once since the last refresh, then a speculative refresh is per
2059 * formed. Speculative refreshes continues successively until there are no
2060 * refreshes pending or until new reads or writes are issued to the uMCTL2.
2061 * FOR PERFORMANCE ONLY.
2062 * PSU_DDRC_RFSHCTL0_REFRESH_TO_X32 0x10
2064 * The programmed value + 1 is the number of refresh timeouts that is allow
2065 * ed to accumulate before traffic is blocked and the refreshes are forced
2066 * to execute. Closing pages to perform a refresh is a one-time penalty tha
2067 * t must be paid for each group of refreshes. Therefore, performing refres
2068 * hes in a burst reduces the per-refresh penalty of these page closings. H
2069 * igher numbers for RFSHCTL.refresh_burst slightly increases utilization;
2070 * lower numbers decreases the worst-case latency associated with refreshes
2071 * . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh
2072 * For information on burst refresh feature refer to section 3.9 of DDR2 J
2073 * EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe
2074 * r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF
2075 * I cycles using the burst refresh feature. In DDR4 mode, according to Fin
2076 * e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre
2077 * shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda
2078 * tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens
2079 * ure that tRFCmax is not violated due to a PHY-initiated update occurring
2080 * shortly before a refresh burst was due. In this situation, the refresh
2081 * burst will be delayed until the PHY-initiated update is complete.
2082 * PSU_DDRC_RFSHCTL0_REFRESH_BURST 0x0
2084 * - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows
2085 * traffic to flow to other banks. Per bank refresh is not supported by all
2086 * LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr
2087 * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4
2088 * PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH 0x0
2090 * Refresh Control Register 0
2091 * (OFFSET, MASK, VALUE) (0XFD070050, 0x00F1F1F4U ,0x00210000U)
2093 PSU_Mask_Write(DDRC_RFSHCTL0_OFFSET, 0x00F1F1F4U, 0x00210000U);
2094 /*##################################################################### */
2097 * Register : RFSHCTL1 @ 0XFD070054
2099 * Refresh timer start for rank 1 (only present in multi-rank configuration
2100 * s). This is useful in staggering the refreshes to multiple ranks to help
2101 * traffic to proceed. This is explained in Refresh Controls section of ar
2102 * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
2103 * PSU_DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32 0x0
2105 * Refresh timer start for rank 0 (only present in multi-rank configuration
2106 * s). This is useful in staggering the refreshes to multiple ranks to help
2107 * traffic to proceed. This is explained in Refresh Controls section of ar
2108 * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
2109 * PSU_DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32 0x0
2111 * Refresh Control Register 1
2112 * (OFFSET, MASK, VALUE) (0XFD070054, 0x0FFF0FFFU ,0x00000000U)
2114 PSU_Mask_Write(DDRC_RFSHCTL1_OFFSET, 0x0FFF0FFFU, 0x00000000U);
2115 /*##################################################################### */
2118 * Register : RFSHCTL3 @ 0XFD070060
2120 * Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix
2121 * ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11
2122 * 0 - Enable on the fly 4x (not supported) - Everything else - reserved No
2123 * te: The on-the-fly modes is not supported in this version of the uMCTL2.
2124 * Note: This must be set up while the Controller is in reset or while the
2125 * Controller is in self-refresh mode. Changing this during normal operati
2126 * on is not allowed. Making this a dynamic register will be supported in f
2127 * uture version of the uMCTL2.
2128 * PSU_DDRC_RFSHCTL3_REFRESH_MODE 0x0
2130 * Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that
2131 * the refresh register(s) have been updated. The value is automatically up
2132 * dated when exiting reset, so it does not need to be toggled initially.
2133 * PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL 0x0
2135 * When '1', disable auto-refresh generated by the uMCTL2. When auto-refres
2136 * h is disabled, the SoC core must generate refreshes using the registers
2137 * reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a
2138 * nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1
2139 * , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4
2140 * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d
2141 * isable auto-refresh is not supported, and this bit must be set to '0'. T
2142 * his register field is changeable on the fly.
2143 * PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH 0x1
2145 * Refresh Control Register 3
2146 * (OFFSET, MASK, VALUE) (0XFD070060, 0x00000073U ,0x00000001U)
2148 PSU_Mask_Write(DDRC_RFSHCTL3_OFFSET, 0x00000073U, 0x00000001U);
2149 /*##################################################################### */
2152 * Register : RFSHTMG @ 0XFD070064
2154 * tREFI: Average time interval between refreshes per rank (Specification:
2155 * 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2,
2156 * LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre
2157 * shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE
2158 * FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this
2159 * register should be set to tREFIpb For configurations with MEMC_FREQ_RAT
2160 * IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val
2161 * ue is different depending on the refresh mode. The user should program t
2162 * he appropriate value from the spec based on the value programmed in the
2163 * refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea
2164 * ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th
2165 * an 0x1. Unit: Multiples of 32 clocks.
2166 * PSU_DDRC_RFSHTMG_T_RFC_NOM_X32 0x81
2168 * Used only when LPDDR3 memory type is connected. Should only be changed w
2169 * hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r
2170 * equired by some LPDDR3 devices which comply with earlier versions of the
2171 * LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1
2172 * - tREFBW parameter used
2173 * PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN 0x1
2175 * tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F
2176 * REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t
2177 * CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro
2178 * undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using
2179 * all-bank refreshes, the tRFCmin value in the above equations is equal to
2180 * tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq
2181 * uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above
2182 * equations is different depending on the refresh mode (fixed 1X,2X,4X) an
2183 * d the device density. The user should program the appropriate value from
2184 * the spec based on the 'refresh_mode' and the device density that is use
2186 * PSU_DDRC_RFSHTMG_T_RFC_MIN 0x8b
2188 * Refresh Timing Register
2189 * (OFFSET, MASK, VALUE) (0XFD070064, 0x0FFF83FFU ,0x0081808BU)
2191 PSU_Mask_Write(DDRC_RFSHTMG_OFFSET, 0x0FFF83FFU, 0x0081808BU);
2192 /*##################################################################### */
2195 * Register : ECCCFG0 @ 0XFD070070
2197 * Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U
2199 * PSU_DDRC_ECCCFG0_DIS_SCRUB 0x1
2201 * ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov
2202 * er 1 beat - all other settings are reserved for future use
2203 * PSU_DDRC_ECCCFG0_ECC_MODE 0x0
2205 * ECC Configuration Register 0
2206 * (OFFSET, MASK, VALUE) (0XFD070070, 0x00000017U ,0x00000010U)
2208 PSU_Mask_Write(DDRC_ECCCFG0_OFFSET, 0x00000017U, 0x00000010U);
2209 /*##################################################################### */
2212 * Register : ECCCFG1 @ 0XFD070074
2214 * Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da
2215 * ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat
2217 * PSU_DDRC_ECCCFG1_DATA_POISON_BIT 0x0
2219 * Enable ECC data poisoning - introduces ECC errors on writes to address s
2220 * pecified by the ECCPOISONADDR0/1 registers
2221 * PSU_DDRC_ECCCFG1_DATA_POISON_EN 0x0
2223 * ECC Configuration Register 1
2224 * (OFFSET, MASK, VALUE) (0XFD070074, 0x00000003U ,0x00000000U)
2226 PSU_Mask_Write(DDRC_ECCCFG1_OFFSET, 0x00000003U, 0x00000000U);
2227 /*##################################################################### */
2230 * Register : CRCPARCTL1 @ 0XFD0700C4
2232 * The maximum number of DFI PHY clock cycles allowed from the assertion of
2233 * the dfi_rddata_en signal to the assertion of each of the corresponding
2234 * bits of the dfi_rddata_valid signal. This corresponds to the DFI timing
2235 * parameter tphy_rdlat. Refer to PHY specification for correct value. This
2236 * value it only used for detecting read data timeout when DDR4 retry is e
2237 * nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value:
2238 * - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r
2239 * dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1
2240 * : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d
2241 * fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_
2242 * rdlat < 'd114 Unit: DFI Clocks
2243 * PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT 0x10
2245 * After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa
2246 * re has an option to read the mode registers in the DRAM before the hardw
2247 * are begins the retry process - 1: Wait for software to read/write the mo
2248 * de registers before hardware begins the retry. After software is done wi
2249 * th its operations, it will clear the alert interrupt register bit - 0: H
2250 * ardware can begin the retry right away after the dfi_alert_n pulse goes
2251 * away. The value on this register is valid only when retry is enabled (PA
2252 * RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t
2253 * he software doesn't clear the interrupt register after handling the pari
2254 * ty/CRC error, then the hardware will not begin the retry process and the
2255 * system will hang. In the case of Parity/CRC error, there are two possib
2256 * ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten
2257 * t parity' mode register bit is NOT set: the commands sent during retry a
2258 * nd normal operation are executed without parity checking. The value in t
2259 * he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent
2260 * parity' mode register bit is SET: Parity checking is done for commands s
2261 * ent during retry and normal operation. If multiple errors occur before M
2262 * R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don'
2264 * PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW 0x1
2266 * - 1: Enable command retry mechanism in case of C/A Parity or CRC error -
2267 * 0: Disable command retry mechanism when C/A Parity or CRC features are
2268 * enabled. Note that retry functionality is not supported if burst chop is
2269 * enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF
2270 * SHCTL3.dis_auto_refresh = 1)
2271 * PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE 0x0
2273 * CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no
2274 * t includes DM signal Present only in designs configured to support DDR4.
2275 * PSU_DDRC_CRCPARCTL1_CRC_INC_DM 0x0
2277 * CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio
2278 * n of CRC The setting of this register should match the CRC mode register
2279 * setting in the DRAM.
2280 * PSU_DDRC_CRCPARCTL1_CRC_ENABLE 0x0
2282 * C/A Parity enable register - 1: Enable generation of C/A parity and dete
2283 * ction of C/A parity error - 0: Disable generation of C/A parity and disa
2284 * ble detection of C/A parity error If RCD's parity error detection or SDR
2285 * AM's parity detection is enabled, this register should be 1.
2286 * PSU_DDRC_CRCPARCTL1_PARITY_ENABLE 0x0
2288 * CRC Parity Control Register1
2289 * (OFFSET, MASK, VALUE) (0XFD0700C4, 0x3F000391U ,0x10000200U)
2291 PSU_Mask_Write(DDRC_CRCPARCTL1_OFFSET, 0x3F000391U, 0x10000200U);
2292 /*##################################################################### */
2295 * Register : CRCPARCTL2 @ 0XFD0700C8
2297 * Value from the DRAM spec indicating the maximum width of the dfi_alert_n
2298 * pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M
2299 * AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT
2300 * _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i
2301 * llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.
2302 * PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX 0x40
2304 * Value from the DRAM spec indicating the maximum width of the dfi_alert_n
2305 * pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX
2306 * For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW
2307 * .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille
2308 * gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.
2309 * PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX 0x5
2311 * Indicates the maximum duration in number of DRAM clock cycles for which
2312 * a command should be held in the Command Retry FIFO before it is popped o
2313 * ut. Every location in the Command Retry FIFO has an associated down coun
2314 * ting timer that will use this register as the start value. The down coun
2315 * ting starts when a command is loaded into the FIFO. The timer counts dow
2316 * n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe
2317 * d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err
2318 * or occurs before the counter reaches zero. The counter is reset to 0, af
2319 * ter all the commands in the FIFO are retried. Recommended(minimum) value
2320 * s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK)
2321 * + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten
2322 * cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable
2323 * d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R
2324 * DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK)
2325 * + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be
2326 * in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n
2327 * ) should be considered. Note 3: Use the worst case(longer) value for PHY
2328 * Latencies/Board delay Note 4: The Recommended values are minimum value
2329 * to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max
2330 * value can be set to this register is defined below: - MEMC_BURST_LENGTH
2331 * == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2
2332 * Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b
2333 * us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod
2334 * e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C
2335 * RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC=
2336 * ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16
2337 * Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full
2338 * bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod
2339 * e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC
2340 * =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF
2341 * ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma
2342 * x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal
2344 * PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4 0x1f
2346 * CRC Parity Control Register2
2347 * (OFFSET, MASK, VALUE) (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU)
2349 PSU_Mask_Write(DDRC_CRCPARCTL2_OFFSET, 0x01FF1F3FU, 0x0040051FU);
2350 /*##################################################################### */
2353 * Register : INIT0 @ 0XFD0700D0
2355 * If lower bit is enabled the SDRAM initialization routine is skipped. The
2356 * upper bit decides what state the controller starts up in when reset is
2357 * removed - 00 - SDRAM Intialization routine is run after power-up - 01 -
2358 * SDRAM Intialization routine is skipped after power-up. Controller starts
2359 * up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p
2360 * ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ
2361 * ation routine is run after power-up. Note: The only 2'b00 is supported f
2362 * or LPDDR4 in this version of the uMCTL2.
2363 * PSU_DDRC_INIT0_SKIP_DRAM_INIT 0x0
2365 * Cycles to wait after driving CKE high to start the SDRAM initialization
2366 * sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req
2367 * uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD
2368 * R3 typically requires this to be programmed for a delay of 200 us. LPDDR
2369 * 4 typically requires this to be programmed for a delay of 2 us. For conf
2370 * igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi
2371 * ded by 2, and round it up to next integer value.
2372 * PSU_DDRC_INIT0_POST_CKE_X1024 0x2
2374 * Cycles to wait after reset before driving CKE high to start the SDRAM in
2375 * itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi
2376 * cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD
2377 * DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati
2378 * ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by
2379 * 2, and round it up to next integer value.
2380 * PSU_DDRC_INIT0_PRE_CKE_X1024 0x106
2382 * SDRAM Initialization Register 0
2383 * (OFFSET, MASK, VALUE) (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U)
2385 PSU_Mask_Write(DDRC_INIT0_OFFSET, 0xC3FF0FFFU, 0x00020106U);
2386 /*##################################################################### */
2389 * Register : INIT1 @ 0XFD0700D4
2391 * Number of cycles to assert SDRAM reset signal during init sequence. This
2392 * is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo
2393 * r use with a DDR PHY, this should be set to a minimum of 1
2394 * PSU_DDRC_INIT1_DRAM_RSTN_X1024 0x2
2396 * Cycles to wait after completing the SDRAM initialization sequence before
2397 * starting the dynamic scheduler. Unit: Counts of a global timer that pul
2398 * ses every 32 clock cycles. There is no known specific requirement for th
2399 * is; it may be set to zero.
2400 * PSU_DDRC_INIT1_FINAL_WAIT_X32 0x0
2402 * Wait period before driving the OCD complete command to SDRAM. Unit: Coun
2403 * ts of a global timer that pulses every 32 clock cycles. There is no know
2404 * n specific requirement for this; it may be set to zero.
2405 * PSU_DDRC_INIT1_PRE_OCD_X32 0x0
2407 * SDRAM Initialization Register 1
2408 * (OFFSET, MASK, VALUE) (0XFD0700D4, 0x01FF7F0FU ,0x00020000U)
2410 PSU_Mask_Write(DDRC_INIT1_OFFSET, 0x01FF7F0FU, 0x00020000U);
2411 /*##################################################################### */
2414 * Register : INIT2 @ 0XFD0700D8
2416 * Idle time after the reset command, tINIT4. Present only in designs confi
2417 * gured to support LPDDR2. Unit: 32 clock cycles.
2418 * PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32 0x23
2420 * Time to wait after the first CKE high, tINIT2. Present only in designs c
2421 * onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t
2422 * ypically requires 5 x tCK delay.
2423 * PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1 0x5
2425 * SDRAM Initialization Register 2
2426 * (OFFSET, MASK, VALUE) (0XFD0700D8, 0x0000FF0FU ,0x00002305U)
2428 PSU_Mask_Write(DDRC_INIT2_OFFSET, 0x0000FF0FU, 0x00002305U);
2429 /*##################################################################### */
2432 * Register : INIT3 @ 0XFD0700DC
2434 * DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he
2435 * re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value
2436 * loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP
2437 * DDR3/LPDDR4 - Value to write to MR1 register
2438 * PSU_DDRC_INIT3_MR 0x730
2440 * DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti
2441 * ng in this register is ignored. The uMCTL2 sets those bits appropriately
2442 * . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu
2443 * ation mode training is enabled, this bit is set appropriately by the uMC
2444 * TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/
2445 * LPDDR3/LPDDR4 - Value to write to MR2 register
2446 * PSU_DDRC_INIT3_EMR 0x301
2448 * SDRAM Initialization Register 3
2449 * (OFFSET, MASK, VALUE) (0XFD0700DC, 0xFFFFFFFFU ,0x07300301U)
2451 PSU_Mask_Write(DDRC_INIT3_OFFSET, 0xFFFFFFFFU, 0x07300301U);
2452 /*##################################################################### */
2455 * Register : INIT4 @ 0XFD0700E0
2457 * DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2
2458 * register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus
2460 * PSU_DDRC_INIT4_EMR2 0x20
2462 * DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3
2463 * register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis
2465 * PSU_DDRC_INIT4_EMR3 0x200
2467 * SDRAM Initialization Register 4
2468 * (OFFSET, MASK, VALUE) (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U)
2470 PSU_Mask_Write(DDRC_INIT4_OFFSET, 0xFFFFFFFFU, 0x00200200U);
2471 /*##################################################################### */
2474 * Register : INIT5 @ 0XFD0700E4
2476 * ZQ initial calibration, tZQINIT. Present only in designs configured to s
2477 * upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica
2478 * lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir
2480 * PSU_DDRC_INIT5_DEV_ZQINIT_X32 0x21
2482 * Maximum duration of the auto initialization, tINIT5. Present only in des
2483 * igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir
2485 * PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024 0x4
2487 * SDRAM Initialization Register 5
2488 * (OFFSET, MASK, VALUE) (0XFD0700E4, 0x00FF03FFU ,0x00210004U)
2490 PSU_Mask_Write(DDRC_INIT5_OFFSET, 0x00FF03FFU, 0x00210004U);
2491 /*##################################################################### */
2494 * Register : INIT6 @ 0XFD0700E8
2496 * DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs
2498 * PSU_DDRC_INIT6_MR4 0x0
2500 * DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs
2502 * PSU_DDRC_INIT6_MR5 0x6c0
2504 * SDRAM Initialization Register 6
2505 * (OFFSET, MASK, VALUE) (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U)
2507 PSU_Mask_Write(DDRC_INIT6_OFFSET, 0xFFFFFFFFU, 0x000006C0U);
2508 /*##################################################################### */
2511 * Register : INIT7 @ 0XFD0700EC
2513 * DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs
2515 * PSU_DDRC_INIT7_MR6 0x819
2517 * SDRAM Initialization Register 7
2518 * (OFFSET, MASK, VALUE) (0XFD0700EC, 0xFFFF0000U ,0x08190000U)
2520 PSU_Mask_Write(DDRC_INIT7_OFFSET, 0xFFFF0000U, 0x08190000U);
2521 /*##################################################################### */
2524 * Register : DIMMCTL @ 0XFD0700F0
2526 * Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and
2527 * BG1 are NOT swapped even if Address Mirroring is enabled. This will be r
2528 * equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp
2529 * ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled.
2530 * PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING 0x0
2532 * Enable for BG1 bit of MRS command. BG1 bit of the mode register address
2533 * is specified as RFU (Reserved for Future Use) and must be programmed to
2534 * 0 during MRS. In case where DRAMs which do not have BG1 are attached and
2535 * both the CA parity and the Output Inversion are enabled, this must be s
2536 * et to 0, so that the calculation of CA parity will not include BG1 bit.
2537 * Note: This has no effect on the address of any other memory accesses, or
2538 * of software-driven mode register accesses. If address mirroring is enab
2539 * led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En
2540 * abled - 0 - Disabled
2541 * PSU_DDRC_DIMMCTL_MRS_BG1_EN 0x1
2543 * Enable for A17 bit of MRS command. A17 bit of the mode register address
2544 * is specified as RFU (Reserved for Future Use) and must be programmed to
2545 * 0 during MRS. In case where DRAMs which do not have A17 are attached and
2546 * the Output Inversion are enabled, this must be set to 0, so that the ca
2547 * lculation of CA parity will not include A17 bit. Note: This has no effec
2548 * t on the address of any other memory accesses, or of software-driven mod
2549 * e register accesses. - 1 - Enabled - 0 - Disabled
2550 * PSU_DDRC_DIMMCTL_MRS_A17_EN 0x0
2552 * Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM
2553 * M implements the Output Inversion feature by default, which means that t
2554 * he following address, bank address and bank group bits of B-side DRAMs a
2555 * re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en
2556 * sures that, for mode register accesses generated by the uMCTL2 during th
2557 * e automatic initialization routine and enabling of a particular DDR4 fea
2558 * ture, separate A-side and B-side mode register accesses are generated. F
2559 * or B-side mode register accesses, these bits are inverted within the uMC
2560 * TL2 to compensate for this RDIMM inversion. Note: This has no effect on
2561 * the address of any other memory accesses, or of software-driven mode reg
2562 * ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 -
2563 * Do not implement output inversion for B-side DRAMs.
2564 * PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN 0x0
2566 * Address Mirroring Enable (for multi-rank UDIMM implementations and multi
2567 * -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement
2568 * address mirroring for odd ranks, which means that the following address
2569 * , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7,
2570 * A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t
2571 * his bit ensures that, for mode register accesses during the automatic in
2572 * itialization routine, these bits are swapped within the uMCTL2 to compen
2573 * sate for this UDIMM/RDIMM swapping. In addition to the automatic initial
2574 * ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th
2575 * e automatic MRS access to enable/disable of a particular DDR4 feature. N
2576 * ote: This has no effect on the address of any other memory accesses, or
2577 * of software-driven mode register accesses. This is not supported for mDD
2578 * R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1
2579 * output of MRS for the odd ranks is same as BG0 because BG1 is invalid,
2580 * hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran
2581 * ks, implement address mirroring for MRS commands to during initializatio
2582 * n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp
2583 * lements address mirroring) - 0 - Do not implement address mirroring
2584 * PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN 0x0
2586 * Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM
2587 * M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3
2588 * or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of
2589 * software driven MR commands (via MRCTRL0/MRCTRL1), where software is re
2590 * sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se
2591 * nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma
2592 * nds to even and odd ranks seperately - 0 - Do not stagger accesses
2593 * PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN 0x0
2595 * DIMM Control Register
2596 * (OFFSET, MASK, VALUE) (0XFD0700F0, 0x0000003FU ,0x00000010U)
2598 PSU_Mask_Write(DDRC_DIMMCTL_OFFSET, 0x0000003FU, 0x00000010U);
2599 /*##################################################################### */
2602 * Register : RANKCTL @ 0XFD0700F4
2604 * Only present for multi-rank configurations. Indicates the number of cloc
2605 * ks of gap in data responses when performing consecutive writes to differ
2606 * ent ranks. This is used to switch the delays in the PHY to match the ran
2607 * k requirements. This value should consider both PHY requirement and ODT
2608 * requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v
2609 * alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by
2610 * 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas
2611 * ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc
2612 * reased by 1. - ODT requirement: The value programmed in this register ta
2613 * kes care of the ODT switch off timing requirement when switching ranks d
2614 * uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1
2615 * For configurations with MEMC_FREQ_RATIO=1, program this to the larger o
2616 * f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_
2617 * RATIO=2, program this to the larger value divided by two and round it up
2618 * to the next integer.
2619 * PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP 0x6
2621 * Only present for multi-rank configurations. Indicates the number of cloc
2622 * ks of gap in data responses when performing consecutive reads to differe
2623 * nt ranks. This is used to switch the delays in the PHY to match the rank
2624 * requirements. This value should consider both PHY requirement and ODT r
2625 * equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va
2626 * lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only),
2627 * should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only
2628 * ), should be increased by 1. - ODT requirement: The value programmed in
2629 * this register takes care of the ODT switch off timing requirement when s
2630 * witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1,
2631 * program this to the larger of PHY requirement or ODT requirement. For co
2632 * nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di
2633 * vided by two and round it up to the next integer.
2634 * PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP 0x6
2636 * Only present for multi-rank configurations. Background: Reads to the sam
2637 * e rank can be performed back-to-back. Reads to different ranks require a
2638 * dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is
2639 * to avoid possible data bus contention as well as to give PHY enough tim
2640 * e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus
2641 * access on a cycle-by-cycle basis; therefore after a read is scheduled,
2642 * there are few clock cycles (determined by the value on RANKCTL.diff_rank
2643 * _rd_gap register) in which only reads from the same rank are eligible to
2644 * be scheduled. This prevents reads from other ranks from having fair acc
2645 * ess to the data bus. This parameter represents the maximum number of rea
2646 * ds that can be scheduled consecutively to the same rank. After this numb
2647 * er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by
2648 * the scheduler to allow all ranks a fair opportunity to be scheduled. Hig
2649 * her numbers increase bandwidth utilization, lower numbers increase fairn
2650 * ess. This feature can be DISABLED by setting this register to 0. When se
2651 * t to 0, the Controller will stay on the same rank as long as commands ar
2652 * e available for it. Minimum programmable value is 0 (feature disabled) a
2653 * nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY.
2654 * PSU_DDRC_RANKCTL_MAX_RANK_RD 0xf
2656 * Rank Control Register
2657 * (OFFSET, MASK, VALUE) (0XFD0700F4, 0x00000FFFU ,0x0000066FU)
2659 PSU_Mask_Write(DDRC_RANKCTL_OFFSET, 0x00000FFFU, 0x0000066FU);
2660 /*##################################################################### */
2663 * Register : DRAMTMG0 @ 0XFD070100
2665 * Minimum time between write and precharge to same bank. Unit: Clocks Spec
2666 * ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks
2667 * @400MHz and less for lower frequencies where: - WL = write latency - BL
2668 * = burst length. This must match the value programmed in the BL bit of t
2669 * he mode register to the SDRAM. BST (burst terminate) is not supported at
2670 * present. - tWR = Write recovery time. This comes directly from the SDRA
2671 * M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p
2672 * arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the
2673 * above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT
2674 * IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u
2675 * p to the next integer value.
2676 * PSU_DDRC_DRAMTMG0_WR2PRE 0x11
2678 * tFAW Valid only when 8 or more banks(or banks x bank groups) are present
2679 * . In 8-bank design, at most 4 banks must be activated in a rolling windo
2680 * w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi
2681 * s to (tFAW/2) and round up to next integer value. In a 4-bank design, se
2682 * t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration.
2684 * PSU_DDRC_DRAMTMG0_T_FAW 0x10
2686 * tRAS(max): Maximum time between activate and precharge to same bank. Thi
2687 * s is the maximum time that a page can be kept open Minimum value of this
2688 * register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO
2689 * =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of
2691 * PSU_DDRC_DRAMTMG0_T_RAS_MAX 0x24
2693 * tRAS(min): Minimum time between activate and precharge to the same bank.
2694 * For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA
2695 * S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T
2696 * mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th
2697 * e next integer value. Unit: Clocks
2698 * PSU_DDRC_DRAMTMG0_T_RAS_MIN 0x12
2700 * SDRAM Timing Register 0
2701 * (OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x11102412U)
2703 PSU_Mask_Write(DDRC_DRAMTMG0_OFFSET, 0x7F3F7F3FU, 0x11102412U);
2704 /*##################################################################### */
2707 * Register : DRAMTMG1 @ 0XFD070104
2709 * tXP: Minimum time after power-down exit to any operation. For DDR3, this
2710 * should be programmed to tXPDLL if slow powerdown exit is selected in MR
2711 * 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf
2712 * igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it
2713 * up to the next integer value. Units: Clocks
2714 * PSU_DDRC_DRAMTMG1_T_XP 0x4
2716 * tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL
2717 * /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi
2718 * ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2
2719 * - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t
2720 * RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4)
2721 * - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_
2722 * RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi
2723 * gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo
2724 * ve value by 2 and round it up to the next integer value. Unit: Clocks.
2725 * PSU_DDRC_DRAMTMG1_RD2PRE 0x4
2727 * tRC: Minimum time between activates to same bank. For configurations wit
2728 * h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege
2729 * r value. Unit: Clocks.
2730 * PSU_DDRC_DRAMTMG1_T_RC 0x1a
2732 * SDRAM Timing Register 1
2733 * (OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x0004041AU)
2735 PSU_Mask_Write(DDRC_DRAMTMG1_OFFSET, 0x001F1F7FU, 0x0004041AU);
2736 /*##################################################################### */
2739 * Register : DRAMTMG2 @ 0XFD070108
2741 * Set to WL Time from write command to write data on SDRAM interface. This
2742 * must be set to WL. For mDDR, it should normally be set to 1. Note that,
2743 * depending on the PHY, if using RDIMM, it may be necessary to use a valu
2744 * e of WL + 1 to compensate for the extra cycle of latency through the RDI
2745 * MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate
2746 * d using the above equation by 2, and round it up to next integer. This r
2747 * egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING
2748 * is set), as the DFI read and write latencies defined in DFITMG0 and DFI
2749 * TMG1 are sufficient for those protocols Unit: clocks
2750 * PSU_DDRC_DRAMTMG2_WRITE_LATENCY 0x7
2752 * Set to RL Time from read command to read data on SDRAM interface. This m
2753 * ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma
2754 * t be necessary to use a value of RL + 1 to compensate for the extra cycl
2755 * e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2
2756 * , divide the value calculated using the above equation by 2, and round i
2757 * t up to next integer. This register field is not required for DDR2 and D
2758 * DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie
2759 * s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit
2761 * PSU_DDRC_DRAMTMG2_READ_LATENCY 0x8
2763 * DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L
2764 * PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di
2765 * sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL
2766 * LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL
2767 * E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write
2768 * command. Include time for bus turnaround and all per-bank, per-rank, an
2769 * d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b
2770 * urst length. This must match the value programmed in the BL bit of the m
2771 * ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL
2772 * E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE =
2773 * read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d
2774 * erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should
2775 * be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal
2776 * culated using the above equation by 2, and round it up to next integer.
2777 * PSU_DDRC_DRAMTMG2_RD2WR 0x6
2779 * DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu
2780 * m time from write command to read command for same bank group. In others
2781 * , minimum time from write command to read command. Includes time for bus
2782 * turnaround, recovery times, and all per-bank, per-rank, and global cons
2783 * traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la
2784 * tency - BL = burst length. This must match the value programmed in the B
2785 * L bit of the mode register to the SDRAM - tWTR_L = internal write to rea
2786 * d command delay for same bank group. This comes directly from the SDRAM
2787 * specification. - tWTR = internal write to read command delay. This comes
2788 * directly from the SDRAM specification. Add one extra cycle for LPDDR2/L
2789 * PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid
2790 * e the value calculated using the above equation by 2, and round it up to
2792 * PSU_DDRC_DRAMTMG2_WR2RD 0xd
2794 * SDRAM Timing Register 2
2795 * (OFFSET, MASK, VALUE) (0XFD070108, 0x3F3F3F3FU ,0x0708060DU)
2797 PSU_Mask_Write(DDRC_DRAMTMG2_OFFSET, 0x3F3F3F3FU, 0x0708060DU);
2798 /*##################################################################### */
2801 * Register : DRAMTMG3 @ 0XFD07010C
2803 * Time to wait after a mode register write or read (MRW or MRR). Present o
2804 * nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty
2805 * pically requires value of 5. LPDDR3 typically requires value of 10. LPDD
2806 * R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist
2807 * er is used for the time from a MRW/MRR to all other commands. For LDPDR3
2808 * , this register is used for the time from a MRW/MRR to a MRW/MRR.
2809 * PSU_DDRC_DRAMTMG3_T_MRW 0x5
2811 * tMRD: Cycles to wait after a mode register write or read. Depending on t
2812 * he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com
2813 * mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim
2814 * e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2,
2815 * program this to (tMRD/2) and round it up to the next integer value. If
2816 * C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead.
2817 * PSU_DDRC_DRAMTMG3_T_MRD 0x4
2819 * tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com
2820 * mand and following non-load mode command. If C/A parity for DDR4 is used
2821 * , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or
2822 * tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if
2823 * using RDIMM, depending on the PHY, it may be necessary to use a value of
2824 * tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a
2825 * pplied to mode register writes by the RDIMM chip.
2826 * PSU_DDRC_DRAMTMG3_T_MOD 0xc
2828 * SDRAM Timing Register 3
2829 * (OFFSET, MASK, VALUE) (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU)
2831 PSU_Mask_Write(DDRC_DRAMTMG3_OFFSET, 0x3FF3F3FFU, 0x0050400CU);
2832 /*##################################################################### */
2835 * Register : DRAMTMG4 @ 0XFD070110
2837 * tRCD - tAL: Minimum time from activate to read or write command to same
2838 * bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD
2839 * - tAL)/2) and round it up to the next integer value. Minimum value allow
2840 * ed for this register is 1, which implies minimum (tRCD - tAL) value to b
2841 * e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.
2842 * PSU_DDRC_DRAMTMG4_T_RCD 0x8
2844 * DDR4: tCCD_L: This is the minimum time between two reads or two writes f
2845 * or same bank group. Others: tCCD: This is the minimum time between two r
2846 * eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t
2847 * his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U
2849 * PSU_DDRC_DRAMTMG4_T_CCD 0x3
2851 * DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f
2852 * or same bank group. Others: tRRD: Minimum time between activates from ba
2853 * nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi
2854 * s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni
2856 * PSU_DDRC_DRAMTMG4_T_RRD 0x3
2858 * tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ
2859 * _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM
2860 * C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t
2861 * RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho
2862 * uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
2863 * PSU_DDRC_DRAMTMG4_T_RP 0x9
2865 * SDRAM Timing Register 4
2866 * (OFFSET, MASK, VALUE) (0XFD070110, 0x1F0F0F1FU ,0x08030309U)
2868 PSU_Mask_Write(DDRC_DRAMTMG4_OFFSET, 0x1F0F0F1FU, 0x08030309U);
2869 /*##################################################################### */
2872 * Register : DRAMTMG5 @ 0XFD070114
2874 * This is the time before Self Refresh Exit that CK is maintained as a val
2875 * id clock before issuing SRX. Specifies the clock stable time before SRX.
2876 * Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK
2877 * EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_
2878 * FREQ_RATIO=2, program this to recommended value divided by two and round
2879 * it up to next integer.
2880 * PSU_DDRC_DRAMTMG5_T_CKSRX 0x6
2882 * This is the time after Self Refresh Down Entry that CK is maintained as
2883 * a valid clock. Specifies the clock disable delay after SRE. Recommended
2884 * settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1
2885 * - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations
2886 * with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw
2887 * o and round it up to next integer.
2888 * PSU_DDRC_DRAMTMG5_T_CKSRE 0x6
2890 * Minimum CKE low width for Self refresh or Self refresh power down entry
2891 * to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF
2892 * C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2:
2893 * tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ
2894 * _RATIO=2, program this to recommended value divided by two and round it
2895 * up to next integer.
2896 * PSU_DDRC_DRAMTMG5_T_CKESR 0x4
2898 * Minimum number of cycles of CKE HIGH/LOW during power-down and self refr
2899 * esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP
2900 * DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/
2901 * non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration
2902 * s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and
2903 * round it up to the next integer value. Unit: Clocks.
2904 * PSU_DDRC_DRAMTMG5_T_CKE 0x3
2906 * SDRAM Timing Register 5
2907 * (OFFSET, MASK, VALUE) (0XFD070114, 0x0F0F3F1FU ,0x06060403U)
2909 PSU_Mask_Write(DDRC_DRAMTMG5_OFFSET, 0x0F0F3F1FU, 0x06060403U);
2910 /*##################################################################### */
2913 * Register : DRAMTMG6 @ 0XFD070118
2915 * This is the time after Deep Power Down Entry that CK is maintained as a
2916 * valid clock. Specifies the clock disable delay after DPDE. Recommended s
2917 * ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_
2918 * FREQ_RATIO=2, program this to recommended value divided by two and round
2919 * it up to next integer. This is only present for designs supporting mDDR
2920 * or LPDDR2/LPDDR3 devices.
2921 * PSU_DDRC_DRAMTMG6_T_CKDPDE 0x1
2923 * This is the time before Deep Power Down Exit that CK is maintained as a
2924 * valid clock before issuing DPDX. Specifies the clock stable time before
2925 * DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config
2926 * urations with MEMC_FREQ_RATIO=2, program this to recommended value divid
2927 * ed by two and round it up to next integer. This is only present for desi
2928 * gns supporting mDDR or LPDDR2 devices.
2929 * PSU_DDRC_DRAMTMG6_T_CKDPDX 0x1
2931 * This is the time before Clock Stop Exit that CK is maintained as a valid
2932 * clock before issuing Clock Stop Exit. Specifies the clock stable time b
2933 * efore next command after Clock Stop Exit. Recommended settings: - mDDR:
2934 * 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio
2935 * ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by
2936 * two and round it up to next integer. This is only present for designs su
2937 * pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
2938 * PSU_DDRC_DRAMTMG6_T_CKCSX 0x4
2940 * SDRAM Timing Register 6
2941 * (OFFSET, MASK, VALUE) (0XFD070118, 0x0F0F000FU ,0x01010004U)
2943 PSU_Mask_Write(DDRC_DRAMTMG6_OFFSET, 0x0F0F000FU, 0x01010004U);
2944 /*##################################################################### */
2947 * Register : DRAMTMG7 @ 0XFD07011C
2949 * This is the time after Power Down Entry that CK is maintained as a valid
2950 * clock. Specifies the clock disable delay after PDE. Recommended setting
2951 * s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration
2952 * s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t
2953 * wo and round it up to next integer. This is only present for designs sup
2954 * porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
2955 * PSU_DDRC_DRAMTMG7_T_CKPDE 0x6
2957 * This is the time before Power Down Exit that CK is maintained as a valid
2958 * clock before issuing PDX. Specifies the clock stable time before PDX. R
2959 * ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c
2960 * onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value
2961 * divided by two and round it up to next integer. This is only present for
2962 * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
2963 * PSU_DDRC_DRAMTMG7_T_CKPDX 0x6
2965 * SDRAM Timing Register 7
2966 * (OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000606U)
2968 PSU_Mask_Write(DDRC_DRAMTMG7_OFFSET, 0x00000F0FU, 0x00000606U);
2969 /*##################################################################### */
2972 * Register : DRAMTMG8 @ 0XFD070120
2974 * tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and
2975 * Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this
2976 * to the above value divided by 2 and round up to next integer value. Unit
2977 * : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com
2978 * mands. Note: Ensure this is less than or equal to t_xs_x32.
2979 * PSU_DDRC_DRAMTMG8_T_XS_FAST_X32 0x3
2981 * tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S
2982 * elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th
2983 * is to the above value divided by 2 and round up to next integer value. U
2984 * nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to
2986 * PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32 0x3
2988 * tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config
2989 * urations with MEMC_FREQ_RATIO=2, program this to the above value divided
2990 * by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
2991 * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs.
2992 * PSU_DDRC_DRAMTMG8_T_XS_DLL_X32 0xd
2994 * tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi
2995 * gurations with MEMC_FREQ_RATIO=2, program this to the above value divide
2996 * d by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
2997 * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs.
2998 * PSU_DDRC_DRAMTMG8_T_XS_X32 0x6
3000 * SDRAM Timing Register 8
3001 * (OFFSET, MASK, VALUE) (0XFD070120, 0x7F7F7F7FU ,0x03030D06U)
3003 PSU_Mask_Write(DDRC_DRAMTMG8_OFFSET, 0x7F7F7F7FU, 0x03030D06U);
3004 /*##################################################################### */
3007 * Register : DRAMTMG9 @ 0XFD070124
3009 * DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o
3010 * nly with MEMC_FREQ_RATIO=2
3011 * PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE 0x0
3013 * tCCD_S: This is the minimum time between two reads or two writes for dif
3014 * ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m
3015 * inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2
3016 * , program this to (tCCD_S/2) and round it up to the next integer value.
3017 * Present only in designs configured to support DDR4. Unit: clocks.
3018 * PSU_DDRC_DRAMTMG9_T_CCD_S 0x2
3020 * tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif
3021 * ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th
3022 * is to (tRRD_S/2) and round it up to the next integer value. Present only
3023 * in designs configured to support DDR4. Unit: Clocks.
3024 * PSU_DDRC_DRAMTMG9_T_RRD_S 0x2
3026 * CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command
3027 * for different bank group. Includes time for bus turnaround, recovery ti
3028 * mes, and all per-bank, per-rank, and global constraints. Present only in
3029 * designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr
3030 * ite latency - PL = Parity latency - BL = burst length. This must match t
3031 * he value programmed in the BL bit of the mode register to the SDRAM - tW
3032 * TR_S = internal write to read command delay for different bank group. Th
3033 * is comes directly from the SDRAM specification. For configurations with
3034 * MEMC_FREQ_RATIO=2, divide the value calculated using the above equation
3035 * by 2, and round it up to next integer.
3036 * PSU_DDRC_DRAMTMG9_WR2RD_S 0xb
3038 * SDRAM Timing Register 9
3039 * (OFFSET, MASK, VALUE) (0XFD070124, 0x40070F3FU ,0x0002020BU)
3041 PSU_Mask_Write(DDRC_DRAMTMG9_OFFSET, 0x40070F3FU, 0x0002020BU);
3042 /*##################################################################### */
3045 * Register : DRAMTMG11 @ 0XFD07012C
3047 * tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL
3048 * L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2
3049 * ) and round it up to the next integer value. Present only in designs con
3050 * figured to support DDR4. Unit: Multiples of 32 clocks.
3051 * PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32 0x70
3053 * tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For
3054 * configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2
3055 * )+1. Present only in designs configured to support DDR4. Unit: clocks.
3056 * PSU_DDRC_DRAMTMG11_T_MPX_LH 0x7
3058 * tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_
3059 * FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int
3060 * eger value. Present only in designs configured to support DDR4. Unit: Cl
3062 * PSU_DDRC_DRAMTMG11_T_MPX_S 0x1
3064 * tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i
3065 * n designs configured to support DDR4. Unit: Clocks. For configurations w
3066 * ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat
3067 * ion by 2, and round it up to next integer.
3068 * PSU_DDRC_DRAMTMG11_T_CKMPE 0xe
3070 * SDRAM Timing Register 11
3071 * (OFFSET, MASK, VALUE) (0XFD07012C, 0x7F1F031FU ,0x7007010EU)
3073 PSU_Mask_Write(DDRC_DRAMTMG11_OFFSET, 0x7F1F031FU, 0x7007010EU);
3074 /*##################################################################### */
3077 * Register : DRAMTMG12 @ 0XFD070130
3079 * tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg
3080 * er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr
3081 * am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu
3083 * PSU_DDRC_DRAMTMG12_T_CMDCKE 0x2
3085 * tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat
3086 * ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u
3087 * p to next integer value.
3088 * PSU_DDRC_DRAMTMG12_T_CKEHCMD 0x6
3090 * tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode.
3091 * For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2)
3092 * and round it up to next integer value.
3093 * PSU_DDRC_DRAMTMG12_T_MRD_PDA 0x8
3095 * SDRAM Timing Register 12
3096 * (OFFSET, MASK, VALUE) (0XFD070130, 0x00030F1FU ,0x00020608U)
3098 PSU_Mask_Write(DDRC_DRAMTMG12_OFFSET, 0x00030F1FU, 0x00020608U);
3099 /*##################################################################### */
3102 * Register : ZQCTL0 @ 0XFD070180
3104 * - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg
3105 * ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration
3106 * request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati
3107 * on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre
3108 * sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
3109 * PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ 0x1
3111 * - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres
3112 * h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2
3113 * or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio
3114 * n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i
3115 * n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present
3116 * for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
3117 * PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL 0x0
3119 * - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC
3120 * L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with
3121 * tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co
3122 * mmands to different ranks do not overlap. - 0 - ZQ resistor is not share
3123 * d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR
3125 * PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED 0x0
3127 * - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit.
3128 * Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com
3129 * mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4
3130 * mode. This is only present for designs supporting DDR4 devices.
3131 * PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL 0x0
3133 * tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe
3134 * r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St
3135 * art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO
3136 * =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int
3137 * eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th
3138 * e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t
3139 * o the next integer value. Unit: Clock cycles. This is only present for d
3140 * esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
3141 * PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP 0x100
3143 * tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of
3144 * NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command
3145 * is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t
3146 * his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy
3147 * cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP
3148 * DDR3/LPDDR4 devices.
3149 * PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP 0x40
3151 * ZQ Control Register 0
3152 * (OFFSET, MASK, VALUE) (0XFD070180, 0xF7FF03FFU ,0x81000040U)
3154 PSU_Mask_Write(DDRC_ZQCTL0_OFFSET, 0xF7FF03FFU, 0x81000040U);
3155 /*##################################################################### */
3158 * Register : ZQCTL1 @ 0XFD070184
3160 * tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati
3161 * on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_
3162 * RATIO=2, program this to tZQReset/2 and round it up to the next integer
3163 * value. Unit: Clock cycles. This is only present for designs supporting L
3164 * PDDR2/LPDDR3/LPDDR4 devices.
3165 * PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP 0x20
3167 * Average interval to wait between automatically issuing ZQCS (ZQ calibrat
3168 * ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR
3169 * 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles
3170 * . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3
3172 * PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 0x196dc
3174 * ZQ Control Register 1
3175 * (OFFSET, MASK, VALUE) (0XFD070184, 0x3FFFFFFFU ,0x020196DCU)
3177 PSU_Mask_Write(DDRC_ZQCTL1_OFFSET, 0x3FFFFFFFU, 0x020196DCU);
3178 /*##################################################################### */
3181 * Register : DFITMG0 @ 0XFD070190
3183 * Specifies the number of DFI clock cycles after an assertion or de-assert
3184 * ion of the DFI control signals that the control signals at the PHY-DRAM
3185 * interface reflect the assertion or de-assertion. If the DFI clock and th
3186 * e memory clock are not phase-aligned, this timing parameter should be ro
3187 * unded up to the next integer value. Note that if using RDIMM, it is nece
3188 * ssary to increment this parameter by RDIMM's extra cycle of latency in t
3189 * erms of DFI clock.
3190 * PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY 0x4
3192 * Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u
3193 * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en
3194 * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles
3195 * - 1 in terms of SDR clock cycles Refer to PHY specification for correct
3197 * PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR 0x1
3199 * Time from the assertion of a read command on the DFI interface to the as
3200 * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr
3201 * ect value. This corresponds to the DFI parameter trddata_en. Note that,
3202 * depending on the PHY, if using RDIMM, it may be necessary to use the val
3203 * ue (CL + 1) in the calculation of trddata_en. This is to compensate for
3204 * the extra cycle of latency through the RDIMM. Unit: Clocks
3205 * PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN 0xb
3207 * Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us
3208 * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is
3209 * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df
3210 * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR
3211 * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio
3212 * n for correct value.
3213 * PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR 0x1
3215 * Specifies the number of clock cycles between when dfi_wrdata_en is asser
3216 * ted to when the associated write data is driven on the dfi_wrdata signal
3217 * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY
3218 * specification for correct value. Note, max supported value is 8. Unit:
3220 * PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA 0x2
3222 * Write latency Number of clocks from the write command to write data enab
3223 * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr
3224 * lat. Refer to PHY specification for correct value.Note that, depending o
3225 * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1)
3226 * in the calculation of tphy_wrlat. This is to compensate for the extra c
3227 * ycle of latency through the RDIMM.
3228 * PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT 0xb
3230 * DFI Timing Register 0
3231 * (OFFSET, MASK, VALUE) (0XFD070190, 0x1FBFBF3FU ,0x048B820BU)
3233 PSU_Mask_Write(DDRC_DFITMG0_OFFSET, 0x1FBFBF3FU, 0x048B820BU);
3234 /*##################################################################### */
3237 * Register : DFITMG1 @ 0XFD070194
3239 * Specifies the number of DFI PHY clocks between when the dfi_cs signal is
3240 * asserted and when the associated command is driven. This field is used
3241 * for CAL mode, should be set to '0' or the value which matches the CAL mo
3242 * de register setting in the DRAM. If the PHY can add the latency for CAL
3243 * mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
3244 * PSU_DDRC_DFITMG1_DFI_T_CMD_LAT 0x0
3246 * Specifies the number of DFI PHY clocks between when the dfi_cs signal is
3247 * asserted and when the associated dfi_parity_in signal is driven.
3248 * PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT 0x0
3250 * Specifies the number of DFI clocks between when the dfi_wrdata_en signal
3251 * is asserted and when the corresponding write data transfer is completed
3252 * on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d
3253 * elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set
3254 * to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI
3255 * 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va
3256 * lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_
3257 * RATIO=2, divide PHY's value by 2 and round up to next integer. If using
3258 * DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks
3259 * PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY 0x3
3261 * Specifies the number of DFI clock cycles from the assertion of the dfi_d
3262 * ram_clk_disable signal on the DFI until the clock to the DRAM memory dev
3263 * ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock
3264 * and the memory clock are not phase aligned, this timing parameter should
3265 * be rounded up to the next integer value.
3266 * PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE 0x3
3268 * Specifies the number of DFI clock cycles from the de-assertion of the df
3269 * i_dram_clk_disable signal on the DFI until the first valid rising edge o
3270 * f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the
3271 * DFI clock and the memory clock are not phase aligned, this timing param
3272 * eter should be rounded up to the next integer value.
3273 * PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE 0x4
3275 * DFI Timing Register 1
3276 * (OFFSET, MASK, VALUE) (0XFD070194, 0xF31F0F0FU ,0x00030304U)
3278 PSU_Mask_Write(DDRC_DFITMG1_OFFSET, 0xF31F0F0FU, 0x00030304U);
3279 /*##################################################################### */
3282 * Register : DFILPCFG0 @ 0XFD070198
3284 * Setting for DFI's tlp_resp time. Same value is used for both Power Down,
3285 * Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s
3286 * pecification onwards, recommends using a fixed value of 7 always.
3287 * PSU_DDRC_DFILPCFG0_DFI_TLP_RESP 0x7
3289 * Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente
3290 * red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32
3291 * cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5
3292 * 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles -
3293 * 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553
3294 * 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T
3295 * his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices
3297 * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD 0x0
3299 * Enables DFI Low Power interface handshaking during Deep Power Down Entry
3300 * /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup
3301 * porting mDDR or LPDDR2/LPDDR3 devices.
3302 * PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD 0x0
3304 * Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered
3305 * . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc
3306 * les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512
3307 * cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9
3308 * - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c
3309 * ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited
3310 * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR 0x0
3312 * Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex
3313 * it. - 0 - Disabled - 1 - Enabled
3314 * PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR 0x1
3316 * Value to drive on dfi_lp_wakeup signal when Power Down mode is entered.
3317 * Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle
3318 * s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy
3319 * cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 -
3320 * 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc
3321 * les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited
3322 * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x0
3324 * Enables DFI Low Power interface handshaking during Power Down Entry/Exit
3325 * . - 0 - Disabled - 1 - Enabled
3326 * PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD 0x1
3328 * DFI Low Power Configuration Register 0
3329 * (OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000101U)
3331 PSU_Mask_Write(DDRC_DFILPCFG0_OFFSET, 0x0FF1F1F1U, 0x07000101U);
3332 /*##################################################################### */
3335 * Register : DFILPCFG1 @ 0XFD07019C
3337 * Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is
3338 * entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1
3339 * - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x
3340 * 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl
3341 * es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC -
3342 * 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi
3343 * ted This is only present for designs supporting DDR4 devices.
3344 * PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM 0x2
3346 * Enables DFI Low Power interface handshaking during Maximum Power Saving
3347 * Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d
3348 * esigns supporting DDR4 devices.
3349 * PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM 0x1
3351 * DFI Low Power Configuration Register 1
3352 * (OFFSET, MASK, VALUE) (0XFD07019C, 0x000000F1U ,0x00000021U)
3354 PSU_Mask_Write(DDRC_DFILPCFG1_OFFSET, 0x000000F1U, 0x00000021U);
3355 /*##################################################################### */
3358 * Register : DFIUPD0 @ 0XFD0701A0
3360 * When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2
3361 * . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc
3362 * _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically.
3363 * PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD 0x0
3365 * When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2
3366 * following a self-refresh exit. The core must issue the dfi_ctrlupd_req
3367 * signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct
3368 * rlupd_req after exiting self-refresh.
3369 * PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX 0x0
3371 * Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si
3372 * gnal can assert. Lowest value to assign to this variable is 0x40. Unit:
3374 * PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MAX 0x40
3376 * Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si
3377 * gnal must be asserted. The uMCTL2 expects the PHY to respond within this
3378 * time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup
3379 * d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this
3380 * variable is 0x3. Unit: Clocks
3381 * PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MIN 0x3
3383 * DFI Update Register 0
3384 * (OFFSET, MASK, VALUE) (0XFD0701A0, 0xC3FF03FFU ,0x00400003U)
3386 PSU_Mask_Write(DDRC_DFIUPD0_OFFSET, 0xC3FF03FFU, 0x00400003U);
3387 /*##################################################################### */
3390 * Register : DFIUPD1 @ 0XFD0701A4
3392 * This is the minimum amount of time between uMCTL2 initiated DFI update r
3393 * equests (which is executed whenever the uMCTL2 is idle). Set this number
3394 * higher to reduce the frequency of update requests, which can have a sma
3395 * ll impact on the latency of the first read request when the uMCTL2 is id
3396 * le. Unit: 1024 clocks
3397 * PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 0x41
3399 * This is the maximum amount of time between uMCTL2 initiated DFI update r
3400 * equests. This timer resets with each update request; when the timer expi
3401 * res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd
3402 * _ackx is received. PHY can use this idle time to recalibrate the delay l
3403 * ines to the DLLs. The DFI controller update is also used to reset PHY FI
3404 * FO pointers in case of data capture errors. Updates are required to main
3405 * tain calibration over PVT, but frequent updates may impact performance.
3406 * Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must
3407 * be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl
3409 * PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0xe1
3411 * DFI Update Register 1
3412 * (OFFSET, MASK, VALUE) (0XFD0701A4, 0x00FF00FFU ,0x004100E1U)
3414 PSU_Mask_Write(DDRC_DFIUPD1_OFFSET, 0x00FF00FFU, 0x004100E1U);
3415 /*##################################################################### */
3418 * Register : DFIMISC @ 0XFD0701B0
3420 * Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal
3421 * s are active low - 1: Signals are active high
3422 * PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY 0x0
3424 * DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality.
3425 * - 1 - PHY implements DBI functionality. Present only in designs configu
3426 * red to support DDR4 and LPDDR4.
3427 * PSU_DDRC_DFIMISC_PHY_DBI_MODE 0x0
3429 * PHY initialization complete enable signal. When asserted the dfi_init_co
3430 * mplete signal can be used to trigger SDRAM initialisation
3431 * PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN 0x0
3433 * DFI Miscellaneous Control Register
3434 * (OFFSET, MASK, VALUE) (0XFD0701B0, 0x00000007U ,0x00000000U)
3436 PSU_Mask_Write(DDRC_DFIMISC_OFFSET, 0x00000007U, 0x00000000U);
3437 /*##################################################################### */
3440 * Register : DFITMG2 @ 0XFD0701B4
3442 * >Number of clocks between when a read command is sent on the DFI control
3443 * interface and when the associated dfi_rddata_cs signal is asserted. Thi
3444 * s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe
3445 * cification for correct value.
3446 * PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT 0x9
3448 * Number of clocks between when a write command is sent on the DFI control
3449 * interface and when the associated dfi_wrdata_cs signal is asserted. Thi
3450 * s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe
3451 * cification for correct value.
3452 * PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT 0x6
3454 * DFI Timing Register 2
3455 * (OFFSET, MASK, VALUE) (0XFD0701B4, 0x00003F3FU ,0x00000906U)
3457 PSU_Mask_Write(DDRC_DFITMG2_OFFSET, 0x00003F3FU, 0x00000906U);
3458 /*##################################################################### */
3461 * Register : DBICTL @ 0XFD0701C0
3463 * Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D
3464 * BI is enabled. This signal must be set the same value as DRAM's mode reg
3465 * ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b
3466 * e set to 0. - LPDDR4: MR3[6]
3467 * PSU_DDRC_DBICTL_RD_DBI_EN 0x0
3469 * Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ
3470 * e DBI is enabled. This signal must be set the same value as DRAM's mode
3471 * register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus
3472 * t be set to 0. - LPDDR4: MR3[7]
3473 * PSU_DDRC_DBICTL_WR_DBI_EN 0x0
3475 * DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi
3476 * s signal must be set the same logical value as DRAM's mode register. - D
3477 * DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th
3478 * is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13
3479 * [5] which is opposite polarity from this signal
3480 * PSU_DDRC_DBICTL_DM_EN 0x1
3482 * DM/DBI Control Register
3483 * (OFFSET, MASK, VALUE) (0XFD0701C0, 0x00000007U ,0x00000001U)
3485 PSU_Mask_Write(DDRC_DBICTL_OFFSET, 0x00000007U, 0x00000001U);
3486 /*##################################################################### */
3489 * Register : ADDRMAP0 @ 0XFD070200
3491 * Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t
3492 * o 27, and 31 Internal Base: 6 The selected HIF address bit is determined
3493 * by adding the internal base to the value of this field. If set to 31, r
3494 * ank address bit 0 is set to 0.
3495 * PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0 0x1f
3497 * Address Map Register 0
3498 * (OFFSET, MASK, VALUE) (0XFD070200, 0x0000001FU ,0x0000001FU)
3500 PSU_Mask_Write(DDRC_ADDRMAP0_OFFSET, 0x0000001FU, 0x0000001FU);
3501 /*##################################################################### */
3504 * Register : ADDRMAP1 @ 0XFD070204
3506 * Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t
3507 * o 29 and 31 Internal Base: 4 The selected HIF address bit is determined
3508 * by adding the internal base to the value of this field. If set to 31, ba
3509 * nk address bit 2 is set to 0.
3510 * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2 0x1f
3512 * Selects the HIF address bits used as bank address bit 1. Valid Range: 0
3513 * to 30 Internal Base: 3 The selected HIF address bit for each of the bank
3514 * address bits is determined by adding the internal base to the value of
3516 * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1 0xa
3518 * Selects the HIF address bits used as bank address bit 0. Valid Range: 0
3519 * to 30 Internal Base: 2 The selected HIF address bit for each of the bank
3520 * address bits is determined by adding the internal base to the value of
3522 * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0 0xa
3524 * Address Map Register 1
3525 * (OFFSET, MASK, VALUE) (0XFD070204, 0x001F1F1FU ,0x001F0A0AU)
3527 PSU_Mask_Write(DDRC_ADDRMAP1_OFFSET, 0x001F1F1FU, 0x001F0A0AU);
3528 /*##################################################################### */
3531 * Register : ADDRMAP2 @ 0XFD070208
3533 * - Full bus width mode: Selects the HIF address bit used as column addres
3534 * s bit 5. - Half bus width mode: Selects the HIF address bit used as colu
3535 * mn address bit 6. - Quarter bus width mode: Selects the HIF address bit
3536 * used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base
3537 * : 5 The selected HIF address bit is determined by adding the internal ba
3538 * se to the value of this field. If set to 15, this column address bit is
3540 * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5 0x0
3542 * - Full bus width mode: Selects the HIF address bit used as column addres
3543 * s bit 4. - Half bus width mode: Selects the HIF address bit used as colu
3544 * mn address bit 5. - Quarter bus width mode: Selects the HIF address bit
3545 * used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base:
3546 * 4 The selected HIF address bit is determined by adding the internal bas
3547 * e to the value of this field. If set to 15, this column address bit is s
3549 * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4 0x0
3551 * - Full bus width mode: Selects the HIF address bit used as column addres
3552 * s bit 3. - Half bus width mode: Selects the HIF address bit used as colu
3553 * mn address bit 4. - Quarter bus width mode: Selects the HIF address bit
3554 * used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s
3555 * elected HIF address bit is determined by adding the internal base to the
3556 * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1
3557 * 6, it is required to program this to 0, hence register does not exist in
3559 * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3 0x0
3561 * - Full bus width mode: Selects the HIF address bit used as column addres
3562 * s bit 2. - Half bus width mode: Selects the HIF address bit used as colu
3563 * mn address bit 3. - Quarter bus width mode: Selects the HIF address bit
3564 * used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s
3565 * elected HIF address bit is determined by adding the internal base to the
3566 * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8
3567 * or 16, it is required to program this to 0.
3568 * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2 0x0
3570 * Address Map Register 2
3571 * (OFFSET, MASK, VALUE) (0XFD070208, 0x0F0F0F0FU ,0x00000000U)
3573 PSU_Mask_Write(DDRC_ADDRMAP2_OFFSET, 0x0F0F0F0FU, 0x00000000U);
3574 /*##################################################################### */
3577 * Register : ADDRMAP3 @ 0XFD07020C
3579 * - Full bus width mode: Selects the HIF address bit used as column addres
3580 * s bit 9. - Half bus width mode: Selects the HIF address bit used as colu
3581 * mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode:
3582 * Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/
3583 * LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected
3584 * HIF address bit is determined by adding the internal base to the value o
3585 * f this field. If set to 15, this column address bit is set to 0. Note: P
3586 * er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo
3587 * r indicating auto-precharge, and hence no source address bit can be mapp
3588 * ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit
3589 * for auto-precharge in the CA bus and hence column bit 10 is used.
3590 * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9 0x0
3592 * - Full bus width mode: Selects the HIF address bit used as column addres
3593 * s bit 8. - Half bus width mode: Selects the HIF address bit used as colu
3594 * mn address bit 9. - Quarter bus width mode: Selects the HIF address bit
3595 * used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0
3596 * to 7, and 15 Internal Base: 8 The selected HIF address bit is determine
3597 * d by adding the internal base to the value of this field. If set to 15,
3598 * this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi
3599 * cation, column address bit 10 is reserved for indicating auto-precharge,
3600 * and hence no source address bit can be mapped to column address bit 10.
3601 * In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA
3602 * bus and hence column bit 10 is used.
3603 * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8 0x0
3605 * - Full bus width mode: Selects the HIF address bit used as column addres
3606 * s bit 7. - Half bus width mode: Selects the HIF address bit used as colu
3607 * mn address bit 8. - Quarter bus width mode: Selects the HIF address bit
3608 * used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base:
3609 * 7 The selected HIF address bit is determined by adding the internal bas
3610 * e to the value of this field. If set to 15, this column address bit is s
3612 * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7 0x0
3614 * - Full bus width mode: Selects the HIF address bit used as column addres
3615 * s bit 6. - Half bus width mode: Selects the HIF address bit used as colu
3616 * mn address bit 7. - Quarter bus width mode: Selects the HIF address bit
3617 * used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base:
3618 * 6 The selected HIF address bit is determined by adding the internal bas
3619 * e to the value of this field. If set to 15, this column address bit is s
3621 * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6 0x0
3623 * Address Map Register 3
3624 * (OFFSET, MASK, VALUE) (0XFD07020C, 0x0F0F0F0FU ,0x00000000U)
3626 PSU_Mask_Write(DDRC_ADDRMAP3_OFFSET, 0x0F0F0F0FU, 0x00000000U);
3627 /*##################################################################### */
3630 * Register : ADDRMAP4 @ 0XFD070210
3632 * - Full bus width mode: Selects the HIF address bit used as column addres
3633 * s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m
3634 * ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un
3635 * used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7,
3636 * and 15 Internal Base: 11 The selected HIF address bit is determined by
3637 * adding the internal base to the value of this field. If set to 15, this
3638 * column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio
3639 * n, column address bit 10 is reserved for indicating auto-precharge, and
3640 * hence no source address bit can be mapped to column address bit 10. In L
3641 * PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus
3642 * and hence column bit 10 is used.
3643 * PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11 0xf
3645 * - Full bus width mode: Selects the HIF address bit used as column addres
3646 * s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the
3647 * HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode)
3648 * . - Quarter bus width mode: UNUSED. To make it unused, this must be tied
3649 * to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF
3650 * address bit is determined by adding the internal base to the value of t
3651 * his field. If set to 15, this column address bit is set to 0. Note: Per
3652 * JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i
3653 * ndicating auto-precharge, and hence no source address bit can be mapped
3654 * to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for
3655 * auto-precharge in the CA bus and hence column bit 10 is used.
3656 * PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10 0xf
3658 * Address Map Register 4
3659 * (OFFSET, MASK, VALUE) (0XFD070210, 0x00000F0FU ,0x00000F0FU)
3661 PSU_Mask_Write(DDRC_ADDRMAP4_OFFSET, 0x00000F0FU, 0x00000F0FU);
3662 /*##################################################################### */
3665 * Register : ADDRMAP5 @ 0XFD070214
3667 * Selects the HIF address bit used as row address bit 11. Valid Range: 0 t
3668 * o 11, and 15 Internal Base: 17 The selected HIF address bit is determine
3669 * d by adding the internal base to the value of this field. If set to 15,
3670 * row address bit 11 is set to 0.
3671 * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11 0x8
3673 * Selects the HIF address bits used as row address bits 2 to 10. Valid Ran
3674 * ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row
3675 * address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro
3676 * w address bit 10) The selected HIF address bit for each of the row addre
3677 * ss bits is determined by adding the internal base to the value of this f
3678 * ield. When value 15 is used the values of row address bits 2 to 10 are d
3679 * efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.
3680 * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10 0xf
3682 * Selects the HIF address bits used as row address bit 1. Valid Range: 0 t
3683 * o 11 Internal Base: 7 The selected HIF address bit for each of the row a
3684 * ddress bits is determined by adding the internal base to the value of th
3686 * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1 0x8
3688 * Selects the HIF address bits used as row address bit 0. Valid Range: 0 t
3689 * o 11 Internal Base: 6 The selected HIF address bit for each of the row a
3690 * ddress bits is determined by adding the internal base to the value of th
3692 * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0 0x8
3694 * Address Map Register 5
3695 * (OFFSET, MASK, VALUE) (0XFD070214, 0x0F0F0F0FU ,0x080F0808U)
3697 PSU_Mask_Write(DDRC_ADDRMAP5_OFFSET, 0x0F0F0F0FU, 0x080F0808U);
3698 /*##################################################################### */
3701 * Register : ADDRMAP6 @ 0XFD070218
3703 * Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1
3704 * - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]=
3705 * =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use.
3706 * All addresses are valid Present only in designs configured to support L
3708 * PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB 0x0
3710 * Selects the HIF address bit used as row address bit 15. Valid Range: 0 t
3711 * o 11, and 15 Internal Base: 21 The selected HIF address bit is determine
3712 * d by adding the internal base to the value of this field. If set to 15,
3713 * row address bit 15 is set to 0.
3714 * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15 0xf
3716 * Selects the HIF address bit used as row address bit 14. Valid Range: 0 t
3717 * o 11, and 15 Internal Base: 20 The selected HIF address bit is determine
3718 * d by adding the internal base to the value of this field. If set to 15,
3719 * row address bit 14 is set to 0.
3720 * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14 0x8
3722 * Selects the HIF address bit used as row address bit 13. Valid Range: 0 t
3723 * o 11, and 15 Internal Base: 19 The selected HIF address bit is determine
3724 * d by adding the internal base to the value of this field. If set to 15,
3725 * row address bit 13 is set to 0.
3726 * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13 0x8
3728 * Selects the HIF address bit used as row address bit 12. Valid Range: 0 t
3729 * o 11, and 15 Internal Base: 18 The selected HIF address bit is determine
3730 * d by adding the internal base to the value of this field. If set to 15,
3731 * row address bit 12 is set to 0.
3732 * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12 0x8
3734 * Address Map Register 6
3735 * (OFFSET, MASK, VALUE) (0XFD070218, 0x8F0F0F0FU ,0x0F080808U)
3737 PSU_Mask_Write(DDRC_ADDRMAP6_OFFSET, 0x8F0F0F0FU, 0x0F080808U);
3738 /*##################################################################### */
3741 * Register : ADDRMAP7 @ 0XFD07021C
3743 * Selects the HIF address bit used as row address bit 17. Valid Range: 0 t
3744 * o 10, and 15 Internal Base: 23 The selected HIF address bit is determine
3745 * d by adding the internal base to the value of this field. If set to 15,
3746 * row address bit 17 is set to 0.
3747 * PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17 0xf
3749 * Selects the HIF address bit used as row address bit 16. Valid Range: 0 t
3750 * o 11, and 15 Internal Base: 22 The selected HIF address bit is determine
3751 * d by adding the internal base to the value of this field. If set to 15,
3752 * row address bit 16 is set to 0.
3753 * PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16 0xf
3755 * Address Map Register 7
3756 * (OFFSET, MASK, VALUE) (0XFD07021C, 0x00000F0FU ,0x00000F0FU)
3758 PSU_Mask_Write(DDRC_ADDRMAP7_OFFSET, 0x00000F0FU, 0x00000F0FU);
3759 /*##################################################################### */
3762 * Register : ADDRMAP8 @ 0XFD070220
3764 * Selects the HIF address bits used as bank group address bit 1. Valid Ran
3765 * ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea
3766 * ch of the bank group address bits is determined by adding the internal b
3767 * ase to the value of this field. If set to 31, bank group address bit 1 i
3769 * PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1 0x8
3771 * Selects the HIF address bits used as bank group address bit 0. Valid Ran
3772 * ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th
3773 * e bank group address bits is determined by adding the internal base to t
3774 * he value of this field.
3775 * PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0 0x8
3777 * Address Map Register 8
3778 * (OFFSET, MASK, VALUE) (0XFD070220, 0x00001F1FU ,0x00000808U)
3780 PSU_Mask_Write(DDRC_ADDRMAP8_OFFSET, 0x00001F1FU, 0x00000808U);
3781 /*##################################################################### */
3784 * Register : ADDRMAP9 @ 0XFD070224
3786 * Selects the HIF address bits used as row address bit 5. Valid Range: 0 t
3787 * o 11 Internal Base: 11 The selected HIF address bit for each of the row
3788 * address bits is determined by adding the internal base to the value of t
3789 * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
3790 * _10 is set to value 15.
3791 * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5 0x8
3793 * Selects the HIF address bits used as row address bit 4. Valid Range: 0 t
3794 * o 11 Internal Base: 10 The selected HIF address bit for each of the row
3795 * address bits is determined by adding the internal base to the value of t
3796 * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
3797 * _10 is set to value 15.
3798 * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4 0x8
3800 * Selects the HIF address bits used as row address bit 3. Valid Range: 0 t
3801 * o 11 Internal Base: 9 The selected HIF address bit for each of the row a
3802 * ddress bits is determined by adding the internal base to the value of th
3803 * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_
3804 * 10 is set to value 15.
3805 * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3 0x8
3807 * Selects the HIF address bits used as row address bit 2. Valid Range: 0 t
3808 * o 11 Internal Base: 8 The selected HIF address bit for each of the row a
3809 * ddress bits is determined by adding the internal base to the value of th
3810 * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_
3811 * 10 is set to value 15.
3812 * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2 0x8
3814 * Address Map Register 9
3815 * (OFFSET, MASK, VALUE) (0XFD070224, 0x0F0F0F0FU ,0x08080808U)
3817 PSU_Mask_Write(DDRC_ADDRMAP9_OFFSET, 0x0F0F0F0FU, 0x08080808U);
3818 /*##################################################################### */
3821 * Register : ADDRMAP10 @ 0XFD070228
3823 * Selects the HIF address bits used as row address bit 9. Valid Range: 0 t
3824 * o 11 Internal Base: 15 The selected HIF address bit for each of the row
3825 * address bits is determined by adding the internal base to the value of t
3826 * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
3827 * _10 is set to value 15.
3828 * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9 0x8
3830 * Selects the HIF address bits used as row address bit 8. Valid Range: 0 t
3831 * o 11 Internal Base: 14 The selected HIF address bit for each of the row
3832 * address bits is determined by adding the internal base to the value of t
3833 * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
3834 * _10 is set to value 15.
3835 * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8 0x8
3837 * Selects the HIF address bits used as row address bit 7. Valid Range: 0 t
3838 * o 11 Internal Base: 13 The selected HIF address bit for each of the row
3839 * address bits is determined by adding the internal base to the value of t
3840 * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
3841 * _10 is set to value 15.
3842 * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7 0x8
3844 * Selects the HIF address bits used as row address bit 6. Valid Range: 0 t
3845 * o 11 Internal Base: 12 The selected HIF address bit for each of the row
3846 * address bits is determined by adding the internal base to the value of t
3847 * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
3848 * _10 is set to value 15.
3849 * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6 0x8
3851 * Address Map Register 10
3852 * (OFFSET, MASK, VALUE) (0XFD070228, 0x0F0F0F0FU ,0x08080808U)
3854 PSU_Mask_Write(DDRC_ADDRMAP10_OFFSET, 0x0F0F0F0FU, 0x08080808U);
3855 /*##################################################################### */
3858 * Register : ADDRMAP11 @ 0XFD07022C
3860 * Selects the HIF address bits used as row address bit 10. Valid Range: 0
3861 * to 11 Internal Base: 16 The selected HIF address bit for each of the row
3862 * address bits is determined by adding the internal base to the value of
3863 * this field. This register field is used only when ADDRMAP5.addrmap_row_b
3864 * 2_10 is set to value 15.
3865 * PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10 0x8
3867 * Address Map Register 11
3868 * (OFFSET, MASK, VALUE) (0XFD07022C, 0x0000000FU ,0x00000008U)
3870 PSU_Mask_Write(DDRC_ADDRMAP11_OFFSET, 0x0000000FU, 0x00000008U);
3871 /*##################################################################### */
3874 * Register : ODTCFG @ 0XFD070240
3876 * Cycles to hold ODT for a write command. The minimum supported value is 2
3877 * . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800
3878 * ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D
3879 * DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR
3880 * EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (
3881 * not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
3882 * PSU_DDRC_ODTCFG_WR_ODT_HOLD 0x6
3884 * The delay, in clock cycles, from issuing a write command to setting ODT
3885 * values associated with that command. ODT setting must remain constant fo
3886 * r the entire time that DQS is driven by the uMCTL2. Recommended values:
3887 * DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL +
3888 * AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo
3889 * r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust
3890 * for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))
3891 * PSU_DDRC_ODTCFG_WR_ODT_DELAY 0x0
3893 * Cycles to hold ODT for a read command. The minimum supported value is 2.
3894 * Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) -
3895 * BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8
3896 * : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p
3897 * reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) +
3898 * RU(tODTon(max)/tCK)
3899 * PSU_DDRC_ODTCFG_RD_ODT_HOLD 0x6
3901 * The delay, in clock cycles, from issuing a read command to setting ODT v
3902 * alues associated with that command. ODT setting must remain constant for
3903 * the entire time that DQS is driven by the uMCTL2. Recommended values: D
3904 * DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL
3905 * - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C
3906 * WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat
3907 * (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK
3908 * write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre
3909 * amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su
3910 * pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R
3911 * U(tODTon(max)/tCK)
3912 * PSU_DDRC_ODTCFG_RD_ODT_DELAY 0x0
3914 * ODT Configuration Register
3915 * (OFFSET, MASK, VALUE) (0XFD070240, 0x0F1F0F7CU ,0x06000600U)
3917 PSU_Mask_Write(DDRC_ODTCFG_OFFSET, 0x0F1F0F7CU, 0x06000600U);
3918 /*##################################################################### */
3921 * Register : ODTMAP @ 0XFD070244
3923 * Indicates which remote ODTs must be turned on during a read from rank 1.
3924 * Each rank has a remote ODT (in the SDRAM) which can be turned on by set
3925 * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i
3926 * s controlled by bit next to the LSB, etc. For each rank, set its bit to
3927 * 1 to enable its ODT. Present only in configurations that have 2 or more
3929 * PSU_DDRC_ODTMAP_RANK1_RD_ODT 0x0
3931 * Indicates which remote ODTs must be turned on during a write to rank 1.
3932 * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett
3933 * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is
3934 * controlled by bit next to the LSB, etc. For each rank, set its bit to 1
3935 * to enable its ODT. Present only in configurations that have 2 or more r
3937 * PSU_DDRC_ODTMAP_RANK1_WR_ODT 0x0
3939 * Indicates which remote ODTs must be turned on during a read from rank 0.
3940 * Each rank has a remote ODT (in the SDRAM) which can be turned on by set
3941 * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i
3942 * s controlled by bit next to the LSB, etc. For each rank, set its bit to
3943 * 1 to enable its ODT.
3944 * PSU_DDRC_ODTMAP_RANK0_RD_ODT 0x0
3946 * Indicates which remote ODTs must be turned on during a write to rank 0.
3947 * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett
3948 * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is
3949 * controlled by bit next to the LSB, etc. For each rank, set its bit to 1
3950 * to enable its ODT.
3951 * PSU_DDRC_ODTMAP_RANK0_WR_ODT 0x1
3953 * ODT/Rank Map Register
3954 * (OFFSET, MASK, VALUE) (0XFD070244, 0x00003333U ,0x00000001U)
3956 PSU_Mask_Write(DDRC_ODTMAP_OFFSET, 0x00003333U, 0x00000001U);
3957 /*##################################################################### */
3960 * Register : SCHED @ 0XFD070250
3962 * When the preferred transaction store is empty for these many clock cycle
3963 * s, switch to the alternate transaction store if it is non-empty. The rea
3964 * d transaction store (both high and low priority) is the default preferre
3965 * d transaction store and the write transaction store is the alternative s
3966 * tore. When prefer write over read is set this is reversed. 0x0 is a lega
3967 * l value for this register. When set to 0x0, the transaction store switch
3968 * ing will happen immediately when the switching conditions become true. F
3969 * OR PERFORMANCE ONLY
3970 * PSU_DDRC_SCHED_RDWR_IDLE_GAP 0x1
3973 * PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS 0x0
3975 * Number of entries in the low priority transaction store is this value +
3976 * 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of ent
3977 * ries available for the high priority transaction store. Setting this to
3978 * maximum value allocates all entries to low priority transaction store. S
3979 * etting this to 0 allocates 1 entry to low priority transaction store and
3980 * the rest to high priority transaction store. Note: In ECC configuration
3981 * s, the numbers of write and low priority read credits issued is one less
3982 * than in the non-ECC case. One entry each is reserved in the write and l
3983 * ow-priority read CAMs for storing the RMW requests arising out of single
3984 * bit error correction RMW operation.
3985 * PSU_DDRC_SCHED_LPR_NUM_ENTRIES 0x20
3987 * If true, bank is kept open only while there are page hit transactions av
3988 * ailable in the CAM to that bank. The last read or write command in the C
3989 * AM with a bank and page hit will be executed with auto-precharge if SCHE
3990 * D1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclos
3991 * e_timer is set to 0, explicit precharge (and not auto-precharge) may be
3992 * issued in some cases where there is a mode switch between Write and Read
3993 * or between LPR and HPR. The Read and Write commands that are executed a
3994 * s part of the ECC scrub requests are also executed without auto-precharg
3995 * e. If false, the bank remains open until there is a need to close it (to
3996 * open a different page, or for page timeout or refresh timeout) - also k
3997 * nown as open page policy. The open page policy can be overridden by sett
3998 * ing the per-command-autopre bit on the HIF interface (hif_cmd_autopre).
3999 * The pageclose feature provids a midway between Open and Close page polic
4000 * ies. FOR PERFORMANCE ONLY.
4001 * PSU_DDRC_SCHED_PAGECLOSE 0x0
4003 * If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.
4004 * PSU_DDRC_SCHED_PREFER_WRITE 0x0
4006 * Active low signal. When asserted ('0'), all incoming transactions are fo
4007 * rced to low priority. This implies that all High Priority Read (HPR) and
4008 * Variable Priority Read commands (VPR) will be treated as Low Priority R
4009 * ead (LPR) commands. On the write side, all Variable Priority Write (VPW)
4010 * commands will be treated as Normal Priority Write (NPW) commands. Forci
4011 * ng the incoming transactions to low priority implicitly turns off Bypass
4012 * path for read commands. FOR PERFORMANCE ONLY.
4013 * PSU_DDRC_SCHED_FORCE_LOW_PRI_N 0x1
4015 * Scheduler Control Register
4016 * (OFFSET, MASK, VALUE) (0XFD070250, 0x7FFF3F07U ,0x01002001U)
4018 PSU_Mask_Write(DDRC_SCHED_OFFSET, 0x7FFF3F07U, 0x01002001U);
4019 /*##################################################################### */
4022 * Register : PERFLPR1 @ 0XFD070264
4024 * Number of transactions that are serviced once the LPR queue goes critica
4025 * l is the smaller of: - (a) This number - (b) Number of transactions avai
4026 * lable. Unit: Transaction. FOR PERFORMANCE ONLY.
4027 * PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH 0x8
4029 * Number of clocks that the LPR queue can be starved before it goes critic
4030 * al. The minimum valid functional value for this register is 0x1. Program
4031 * ming it to 0x0 will disable the starvation functionality; during normal
4032 * operation, this function should not be disabled as it will cause excessi
4033 * ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
4034 * PSU_DDRC_PERFLPR1_LPR_MAX_STARVE 0x40
4036 * Low Priority Read CAM Register 1
4037 * (OFFSET, MASK, VALUE) (0XFD070264, 0xFF00FFFFU ,0x08000040U)
4039 PSU_Mask_Write(DDRC_PERFLPR1_OFFSET, 0xFF00FFFFU, 0x08000040U);
4040 /*##################################################################### */
4043 * Register : PERFWR1 @ 0XFD07026C
4045 * Number of transactions that are serviced once the WR queue goes critical
4046 * is the smaller of: - (a) This number - (b) Number of transactions avail
4047 * able. Unit: Transaction. FOR PERFORMANCE ONLY.
4048 * PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH 0x8
4050 * Number of clocks that the WR queue can be starved before it goes critica
4051 * l. The minimum valid functional value for this register is 0x1. Programm
4052 * ing it to 0x0 will disable the starvation functionality; during normal o
4053 * peration, this function should not be disabled as it will cause excessiv
4054 * e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
4055 * PSU_DDRC_PERFWR1_W_MAX_STARVE 0x40
4057 * Write CAM Register 1
4058 * (OFFSET, MASK, VALUE) (0XFD07026C, 0xFF00FFFFU ,0x08000040U)
4060 PSU_Mask_Write(DDRC_PERFWR1_OFFSET, 0xFF00FFFFU, 0x08000040U);
4061 /*##################################################################### */
4064 * Register : DQMAP0 @ 0XFD070280
4066 * DQ nibble map for DQ bits [12-15] Present only in designs configured to
4068 * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15 0x0
4070 * DQ nibble map for DQ bits [8-11] Present only in designs configured to s
4072 * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11 0x0
4074 * DQ nibble map for DQ bits [4-7] Present only in designs configured to su
4076 * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7 0x0
4078 * DQ nibble map for DQ bits [0-3] Present only in designs configured to su
4080 * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3 0x0
4083 * (OFFSET, MASK, VALUE) (0XFD070280, 0xFFFFFFFFU ,0x00000000U)
4085 PSU_Mask_Write(DDRC_DQMAP0_OFFSET, 0xFFFFFFFFU, 0x00000000U);
4086 /*##################################################################### */
4089 * Register : DQMAP1 @ 0XFD070284
4091 * DQ nibble map for DQ bits [28-31] Present only in designs configured to
4093 * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31 0x0
4095 * DQ nibble map for DQ bits [24-27] Present only in designs configured to
4097 * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27 0x0
4099 * DQ nibble map for DQ bits [20-23] Present only in designs configured to
4101 * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23 0x0
4103 * DQ nibble map for DQ bits [16-19] Present only in designs configured to
4105 * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19 0x0
4108 * (OFFSET, MASK, VALUE) (0XFD070284, 0xFFFFFFFFU ,0x00000000U)
4110 PSU_Mask_Write(DDRC_DQMAP1_OFFSET, 0xFFFFFFFFU, 0x00000000U);
4111 /*##################################################################### */
4114 * Register : DQMAP2 @ 0XFD070288
4116 * DQ nibble map for DQ bits [44-47] Present only in designs configured to
4118 * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47 0x0
4120 * DQ nibble map for DQ bits [40-43] Present only in designs configured to
4122 * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43 0x0
4124 * DQ nibble map for DQ bits [36-39] Present only in designs configured to
4126 * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39 0x0
4128 * DQ nibble map for DQ bits [32-35] Present only in designs configured to
4130 * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35 0x0
4133 * (OFFSET, MASK, VALUE) (0XFD070288, 0xFFFFFFFFU ,0x00000000U)
4135 PSU_Mask_Write(DDRC_DQMAP2_OFFSET, 0xFFFFFFFFU, 0x00000000U);
4136 /*##################################################################### */
4139 * Register : DQMAP3 @ 0XFD07028C
4141 * DQ nibble map for DQ bits [60-63] Present only in designs configured to
4143 * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63 0x0
4145 * DQ nibble map for DQ bits [56-59] Present only in designs configured to
4147 * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59 0x0
4149 * DQ nibble map for DQ bits [52-55] Present only in designs configured to
4151 * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55 0x0
4153 * DQ nibble map for DQ bits [48-51] Present only in designs configured to
4155 * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51 0x0
4158 * (OFFSET, MASK, VALUE) (0XFD07028C, 0xFFFFFFFFU ,0x00000000U)
4160 PSU_Mask_Write(DDRC_DQMAP3_OFFSET, 0xFFFFFFFFU, 0x00000000U);
4161 /*##################################################################### */
4164 * Register : DQMAP4 @ 0XFD070290
4166 * DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf
4167 * igured to support DDR4.
4168 * PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7 0x0
4170 * DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf
4171 * igured to support DDR4.
4172 * PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3 0x0
4175 * (OFFSET, MASK, VALUE) (0XFD070290, 0x0000FFFFU ,0x00000000U)
4177 PSU_Mask_Write(DDRC_DQMAP4_OFFSET, 0x0000FFFFU, 0x00000000U);
4178 /*##################################################################### */
4181 * Register : DQMAP5 @ 0XFD070294
4183 * All even ranks have the same DQ mapping controled by DQMAP0-4 register a
4184 * s rank 0. This register provides DQ swap function for all odd ranks to s
4185 * upport CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap b
4186 * it 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank ba
4187 * sed DQ swapping 0: Enable rank based DQ swapping Present only in designs
4188 * configured to support DDR4.
4189 * PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP 0x1
4192 * (OFFSET, MASK, VALUE) (0XFD070294, 0x00000001U ,0x00000001U)
4194 PSU_Mask_Write(DDRC_DQMAP5_OFFSET, 0x00000001U, 0x00000001U);
4195 /*##################################################################### */
4198 * Register : DBG0 @ 0XFD070300
4200 * When this is set to '0', auto-precharge is disabled for the flushed comm
4201 * and in a collision case. Collision cases are write followed by read to s
4202 * ame address, read followed by write to same address, or write followed b
4203 * y write to same address with DBG0.dis_wc bit = 1 (where same address com
4204 * parisons exclude the two address bits representing critical word). FOR D
4206 * PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT 0x0
4208 * When 1, disable write combine. FOR DEBUG ONLY
4209 * PSU_DDRC_DBG0_DIS_WC 0x0
4212 * (OFFSET, MASK, VALUE) (0XFD070300, 0x00000011U ,0x00000000U)
4214 PSU_Mask_Write(DDRC_DBG0_OFFSET, 0x00000011U, 0x00000000U);
4215 /*##################################################################### */
4218 * Register : DBGCMD @ 0XFD07030C
4220 * Setting this register bit to 1 allows refresh and ZQCS commands to be tr
4221 * iggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD.
4222 * zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignore
4223 * d by the uMCTL2 logic. Setting this register bit to 0 allows refresh and
4224 * ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_shor
4225 * t and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no
4226 * function, and are ignored by the uMCTL2 logic. This register is static,
4227 * and may only be changed when the DDRC reset signal, core_ddrc_rstn, is
4229 * PSU_DDRC_DBGCMD_HW_REF_ZQ_EN 0x0
4231 * Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ct
4232 * rlupd_req to the PHY. When this request is stored in the uMCTL2, the bit
4233 * is automatically cleared. This operation must only be performed when DF
4234 * IUPD0.dis_auto_ctrlupd=1.
4235 * PSU_DDRC_DBGCMD_CTRLUPD 0x0
4237 * Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (
4238 * ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When thi
4239 * s request is stored in the uMCTL2, the bit is automatically cleared. Thi
4240 * s operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recom
4241 * mended NOT to set this register bit if in Init operating mode. This regi
4242 * ster bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown
4243 * (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo
4245 * PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT 0x0
4247 * Setting this register bit to 1 indicates to the uMCTL2 to issue a refres
4248 * h to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be
4249 * set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been s
4250 * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_
4251 * auto_refresh=1. It is recommended NOT to set this register bit if in Ini
4252 * t or Deep power-down operating modes or Maximum Power Saving Mode.
4253 * PSU_DDRC_DBGCMD_RANK1_REFRESH 0x0
4255 * Setting this register bit to 1 indicates to the uMCTL2 to issue a refres
4256 * h to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be
4257 * set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been s
4258 * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_
4259 * auto_refresh=1. It is recommended NOT to set this register bit if in Ini
4260 * t or Deep power-down operating modes or Maximum Power Saving Mode.
4261 * PSU_DDRC_DBGCMD_RANK0_REFRESH 0x0
4263 * Command Debug Register
4264 * (OFFSET, MASK, VALUE) (0XFD07030C, 0x80000033U ,0x00000000U)
4266 PSU_Mask_Write(DDRC_DBGCMD_OFFSET, 0x80000033U, 0x00000000U);
4267 /*##################################################################### */
4270 * Register : SWCTL @ 0XFD070320
4272 * Enable quasi-dynamic register programming outside reset. Program registe
4273 * r to 0 to enable quasi-dynamic programming. Set back register to 1 once
4274 * programming is done.
4275 * PSU_DDRC_SWCTL_SW_DONE 0x0
4277 * Software register programming control enable
4278 * (OFFSET, MASK, VALUE) (0XFD070320, 0x00000001U ,0x00000000U)
4280 PSU_Mask_Write(DDRC_SWCTL_OFFSET, 0x00000001U, 0x00000000U);
4281 /*##################################################################### */
4284 * Register : PCCFG @ 0XFD070400
4286 * Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expand
4287 * s every AXI burst into multiple HIF commands, using the memory burst len
4288 * gth as a unit. If set to 1, then XPI will use half of the memory burst l
4289 * ength as a unit. This applies to both reads and writes. When MSTR.data_b
4290 * us_width==00, setting bl_exp_mode to 1 has no effect. This can be used i
4291 * n cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.d
4292 * is_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd
4293 * _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionali
4294 * ty is not supported in the following cases: - UMCTL2_PARTIAL_WR=0 - UMCT
4295 * L2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 an
4296 * d MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only) - UMCTL2_PARTIAL_WR=1, MST
4297 * R.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burs
4298 * t_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPAR
4299 * CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared
4301 * PSU_DDRC_PCCFG_BL_EXP_MODE 0x0
4303 * Page match four limit. If set to 1, limits the number of consecutive sam
4304 * e page DDRC transactions that can be granted by the Port Arbiter to four
4305 * when Page Match feature is enabled. If set to 0, there is no limit impo
4306 * sed on number of consecutive same page DDRC transactions.
4307 * PSU_DDRC_PCCFG_PAGEMATCH_LIMIT 0x0
4309 * If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_l
4310 * pr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (aw
4311 * urgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_
4312 * go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a
4313 * t DDRC are driven to 1b'0.
4314 * PSU_DDRC_PCCFG_GO2CRITICAL_EN 0x1
4316 * Port Common Configuration Register
4317 * (OFFSET, MASK, VALUE) (0XFD070400, 0x00000111U ,0x00000001U)
4319 PSU_Mask_Write(DDRC_PCCFG_OFFSET, 0x00000111U, 0x00000001U);
4320 /*##################################################################### */
4323 * Register : PCFGR_0 @ 0XFD070404
4325 * If set to 1, enables the Page Match feature. If enabled, once a requesti
4326 * ng port is granted, the port is continued to be granted if the following
4327 * immediate commands are to the same memory page (same bank and same row)
4328 * . See also related PCCFG.pagematch_limit register.
4329 * PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN 0x0
4331 * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
4332 * bled and arurgent is asserted by the master, that port becomes the highe
4333 * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
4334 * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
4335 * urgent signal can be asserted anytime and as long as required which is i
4336 * ndependent of address handshaking (it is not associated with any particu
4338 * PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN 0x1
4340 * If set to 1, enables aging function for the read channel of the port.
4341 * PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN 0x0
4343 * Determines the initial load value of read aging counters. These counters
4344 * will be parallel loaded after reset, or after each grant to the corresp
4345 * onding port. The aging counters down-count every clock cycle where the p
4346 * ort is requesting but not granted. The higher significant 5-bits of the
4347 * read aging counter sets the priority of the read channel of a given port
4348 * . Port's priority will increase as the higher significant 5-bits of the
4349 * counter starts to decrease. When the aging counter becomes 0, the corres
4350 * ponding port channel will have the highest priority level (timeout condi
4351 * tion - Priority0). For multi-port configurations, the aging counters can
4352 * not be used to set port priorities when external dynamic priority inputs
4353 * (arqos) are enabled (timeout is still applicable). For single port conf
4354 * igurations, the aging counters are only used when they timeout (become 0
4355 * ) to force read-write direction switching. In this case, external dynami
4356 * c priority input, arqos (for reads only) can still be used to set the DD
4357 * RC read priority (2 priority levels: low priority read - LPR, high prior
4358 * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
4359 * s register field are tied internally to 2'b00.
4360 * PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY 0xf
4362 * Port n Configuration Read Register
4363 * (OFFSET, MASK, VALUE) (0XFD070404, 0x000073FFU ,0x0000200FU)
4365 PSU_Mask_Write(DDRC_PCFGR_0_OFFSET, 0x000073FFU, 0x0000200FU);
4366 /*##################################################################### */
4369 * Register : PCFGW_0 @ 0XFD070408
4371 * If set to 1, enables the Page Match feature. If enabled, once a requesti
4372 * ng port is granted, the port is continued to be granted if the following
4373 * immediate commands are to the same memory page (same bank and same row)
4374 * . See also related PCCFG.pagematch_limit register.
4375 * PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN 0x0
4377 * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
4378 * bled and awurgent is asserted by the master, that port becomes the highe
4379 * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
4380 * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
4381 * serted anytime and as long as required which is independent of address h
4382 * andshaking (it is not associated with any particular command).
4383 * PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN 0x1
4385 * If set to 1, enables aging function for the write channel of the port.
4386 * PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN 0x0
4388 * Determines the initial load value of write aging counters. These counter
4389 * s will be parallel loaded after reset, or after each grant to the corres
4390 * ponding port. The aging counters down-count every clock cycle where the
4391 * port is requesting but not granted. The higher significant 5-bits of the
4392 * write aging counter sets the initial priority of the write channel of a
4393 * given port. Port's priority will increase as the higher significant 5-b
4394 * its of the counter starts to decrease. When the aging counter becomes 0,
4395 * the corresponding port channel will have the highest priority level. Fo
4396 * r multi-port configurations, the aging counters cannot be used to set po
4397 * rt priorities when external dynamic priority inputs (awqos) are enabled
4398 * (timeout is still applicable). For single port configurations, the aging
4399 * counters are only used when they timeout (become 0) to force read-write
4400 * direction switching. Note: The two LSBs of this register field are tied
4401 * internally to 2'b00.
4402 * PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY 0xf
4404 * Port n Configuration Write Register
4405 * (OFFSET, MASK, VALUE) (0XFD070408, 0x000073FFU ,0x0000200FU)
4407 PSU_Mask_Write(DDRC_PCFGW_0_OFFSET, 0x000073FFU, 0x0000200FU);
4408 /*##################################################################### */
4411 * Register : PCTRL_0 @ 0XFD070490
4414 * PSU_DDRC_PCTRL_0_PORT_EN 0x1
4416 * Port n Control Register
4417 * (OFFSET, MASK, VALUE) (0XFD070490, 0x00000001U ,0x00000001U)
4419 PSU_Mask_Write(DDRC_PCTRL_0_OFFSET, 0x00000001U, 0x00000001U);
4420 /*##################################################################### */
4423 * Register : PCFGQOS0_0 @ 0XFD070494
4425 * This bitfield indicates the traffic class of region 1. Valid values are:
4426 * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
4427 * maps to the blue address queue. In this case, valid values are 0: LPR a
4428 * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
4429 * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
4431 * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1 0x2
4433 * This bitfield indicates the traffic class of region 0. Valid values are:
4434 * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
4435 * maps to the blue address queue. In this case, valid values are: 0: LPR
4436 * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
4437 * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
4439 * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0 0x0
4441 * Separation level1 indicating the end of region0 mapping; start of region
4442 * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
4443 * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
4444 * lues are used directly as port priorities, where the higher the value co
4445 * rresponds to higher port priority. All of the map_level* registers must
4446 * be set to distinct values.
4447 * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1 0xb
4449 * Port n Read QoS Configuration Register 0
4450 * (OFFSET, MASK, VALUE) (0XFD070494, 0x0033000FU ,0x0020000BU)
4452 PSU_Mask_Write(DDRC_PCFGQOS0_0_OFFSET, 0x0033000FU, 0x0020000BU);
4453 /*##################################################################### */
4456 * Register : PCFGQOS1_0 @ 0XFD070498
4458 * Specifies the timeout value for transactions mapped to the red address q
4460 * PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR 0x0
4462 * Specifies the timeout value for transactions mapped to the blue address
4464 * PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB 0x0
4466 * Port n Read QoS Configuration Register 1
4467 * (OFFSET, MASK, VALUE) (0XFD070498, 0x07FF07FFU ,0x00000000U)
4469 PSU_Mask_Write(DDRC_PCFGQOS1_0_OFFSET, 0x07FF07FFU, 0x00000000U);
4470 /*##################################################################### */
4473 * Register : PCFGR_1 @ 0XFD0704B4
4475 * If set to 1, enables the Page Match feature. If enabled, once a requesti
4476 * ng port is granted, the port is continued to be granted if the following
4477 * immediate commands are to the same memory page (same bank and same row)
4478 * . See also related PCCFG.pagematch_limit register.
4479 * PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN 0x0
4481 * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
4482 * bled and arurgent is asserted by the master, that port becomes the highe
4483 * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
4484 * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
4485 * urgent signal can be asserted anytime and as long as required which is i
4486 * ndependent of address handshaking (it is not associated with any particu
4488 * PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN 0x1
4490 * If set to 1, enables aging function for the read channel of the port.
4491 * PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN 0x0
4493 * Determines the initial load value of read aging counters. These counters
4494 * will be parallel loaded after reset, or after each grant to the corresp
4495 * onding port. The aging counters down-count every clock cycle where the p
4496 * ort is requesting but not granted. The higher significant 5-bits of the
4497 * read aging counter sets the priority of the read channel of a given port
4498 * . Port's priority will increase as the higher significant 5-bits of the
4499 * counter starts to decrease. When the aging counter becomes 0, the corres
4500 * ponding port channel will have the highest priority level (timeout condi
4501 * tion - Priority0). For multi-port configurations, the aging counters can
4502 * not be used to set port priorities when external dynamic priority inputs
4503 * (arqos) are enabled (timeout is still applicable). For single port conf
4504 * igurations, the aging counters are only used when they timeout (become 0
4505 * ) to force read-write direction switching. In this case, external dynami
4506 * c priority input, arqos (for reads only) can still be used to set the DD
4507 * RC read priority (2 priority levels: low priority read - LPR, high prior
4508 * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
4509 * s register field are tied internally to 2'b00.
4510 * PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY 0xf
4512 * Port n Configuration Read Register
4513 * (OFFSET, MASK, VALUE) (0XFD0704B4, 0x000073FFU ,0x0000200FU)
4515 PSU_Mask_Write(DDRC_PCFGR_1_OFFSET, 0x000073FFU, 0x0000200FU);
4516 /*##################################################################### */
4519 * Register : PCFGW_1 @ 0XFD0704B8
4521 * If set to 1, enables the Page Match feature. If enabled, once a requesti
4522 * ng port is granted, the port is continued to be granted if the following
4523 * immediate commands are to the same memory page (same bank and same row)
4524 * . See also related PCCFG.pagematch_limit register.
4525 * PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN 0x0
4527 * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
4528 * bled and awurgent is asserted by the master, that port becomes the highe
4529 * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
4530 * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
4531 * serted anytime and as long as required which is independent of address h
4532 * andshaking (it is not associated with any particular command).
4533 * PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN 0x1
4535 * If set to 1, enables aging function for the write channel of the port.
4536 * PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN 0x0
4538 * Determines the initial load value of write aging counters. These counter
4539 * s will be parallel loaded after reset, or after each grant to the corres
4540 * ponding port. The aging counters down-count every clock cycle where the
4541 * port is requesting but not granted. The higher significant 5-bits of the
4542 * write aging counter sets the initial priority of the write channel of a
4543 * given port. Port's priority will increase as the higher significant 5-b
4544 * its of the counter starts to decrease. When the aging counter becomes 0,
4545 * the corresponding port channel will have the highest priority level. Fo
4546 * r multi-port configurations, the aging counters cannot be used to set po
4547 * rt priorities when external dynamic priority inputs (awqos) are enabled
4548 * (timeout is still applicable). For single port configurations, the aging
4549 * counters are only used when they timeout (become 0) to force read-write
4550 * direction switching. Note: The two LSBs of this register field are tied
4551 * internally to 2'b00.
4552 * PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY 0xf
4554 * Port n Configuration Write Register
4555 * (OFFSET, MASK, VALUE) (0XFD0704B8, 0x000073FFU ,0x0000200FU)
4557 PSU_Mask_Write(DDRC_PCFGW_1_OFFSET, 0x000073FFU, 0x0000200FU);
4558 /*##################################################################### */
4561 * Register : PCTRL_1 @ 0XFD070540
4564 * PSU_DDRC_PCTRL_1_PORT_EN 0x1
4566 * Port n Control Register
4567 * (OFFSET, MASK, VALUE) (0XFD070540, 0x00000001U ,0x00000001U)
4569 PSU_Mask_Write(DDRC_PCTRL_1_OFFSET, 0x00000001U, 0x00000001U);
4570 /*##################################################################### */
4573 * Register : PCFGQOS0_1 @ 0XFD070544
4575 * This bitfield indicates the traffic class of region2. For dual address q
4576 * ueue configurations, region2 maps to the red address queue. Valid values
4577 * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN
4578 * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali
4579 * ased to LPR traffic.
4580 * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2 0x2
4582 * This bitfield indicates the traffic class of region 1. Valid values are:
4583 * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
4584 * maps to the blue address queue. In this case, valid values are 0: LPR a
4585 * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
4586 * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
4588 * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1 0x0
4590 * This bitfield indicates the traffic class of region 0. Valid values are:
4591 * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
4592 * maps to the blue address queue. In this case, valid values are: 0: LPR
4593 * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
4594 * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
4596 * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0 0x0
4598 * Separation level2 indicating the end of region1 mapping; start of region
4599 * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi
4600 * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note
4601 * that for PA, arqos values are used directly as port priorities, where t
4602 * he higher the value corresponds to higher port priority. All of the map_
4603 * level* registers must be set to distinct values.
4604 * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2 0xb
4606 * Separation level1 indicating the end of region0 mapping; start of region
4607 * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
4608 * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
4609 * lues are used directly as port priorities, where the higher the value co
4610 * rresponds to higher port priority. All of the map_level* registers must
4611 * be set to distinct values.
4612 * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1 0x3
4614 * Port n Read QoS Configuration Register 0
4615 * (OFFSET, MASK, VALUE) (0XFD070544, 0x03330F0FU ,0x02000B03U)
4617 PSU_Mask_Write(DDRC_PCFGQOS0_1_OFFSET, 0x03330F0FU, 0x02000B03U);
4618 /*##################################################################### */
4621 * Register : PCFGQOS1_1 @ 0XFD070548
4623 * Specifies the timeout value for transactions mapped to the red address q
4625 * PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR 0x0
4627 * Specifies the timeout value for transactions mapped to the blue address
4629 * PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB 0x0
4631 * Port n Read QoS Configuration Register 1
4632 * (OFFSET, MASK, VALUE) (0XFD070548, 0x07FF07FFU ,0x00000000U)
4634 PSU_Mask_Write(DDRC_PCFGQOS1_1_OFFSET, 0x07FF07FFU, 0x00000000U);
4635 /*##################################################################### */
4638 * Register : PCFGR_2 @ 0XFD070564
4640 * If set to 1, enables the Page Match feature. If enabled, once a requesti
4641 * ng port is granted, the port is continued to be granted if the following
4642 * immediate commands are to the same memory page (same bank and same row)
4643 * . See also related PCCFG.pagematch_limit register.
4644 * PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN 0x0
4646 * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
4647 * bled and arurgent is asserted by the master, that port becomes the highe
4648 * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
4649 * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
4650 * urgent signal can be asserted anytime and as long as required which is i
4651 * ndependent of address handshaking (it is not associated with any particu
4653 * PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN 0x1
4655 * If set to 1, enables aging function for the read channel of the port.
4656 * PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN 0x0
4658 * Determines the initial load value of read aging counters. These counters
4659 * will be parallel loaded after reset, or after each grant to the corresp
4660 * onding port. The aging counters down-count every clock cycle where the p
4661 * ort is requesting but not granted. The higher significant 5-bits of the
4662 * read aging counter sets the priority of the read channel of a given port
4663 * . Port's priority will increase as the higher significant 5-bits of the
4664 * counter starts to decrease. When the aging counter becomes 0, the corres
4665 * ponding port channel will have the highest priority level (timeout condi
4666 * tion - Priority0). For multi-port configurations, the aging counters can
4667 * not be used to set port priorities when external dynamic priority inputs
4668 * (arqos) are enabled (timeout is still applicable). For single port conf
4669 * igurations, the aging counters are only used when they timeout (become 0
4670 * ) to force read-write direction switching. In this case, external dynami
4671 * c priority input, arqos (for reads only) can still be used to set the DD
4672 * RC read priority (2 priority levels: low priority read - LPR, high prior
4673 * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
4674 * s register field are tied internally to 2'b00.
4675 * PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY 0xf
4677 * Port n Configuration Read Register
4678 * (OFFSET, MASK, VALUE) (0XFD070564, 0x000073FFU ,0x0000200FU)
4680 PSU_Mask_Write(DDRC_PCFGR_2_OFFSET, 0x000073FFU, 0x0000200FU);
4681 /*##################################################################### */
4684 * Register : PCFGW_2 @ 0XFD070568
4686 * If set to 1, enables the Page Match feature. If enabled, once a requesti
4687 * ng port is granted, the port is continued to be granted if the following
4688 * immediate commands are to the same memory page (same bank and same row)
4689 * . See also related PCCFG.pagematch_limit register.
4690 * PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN 0x0
4692 * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
4693 * bled and awurgent is asserted by the master, that port becomes the highe
4694 * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
4695 * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
4696 * serted anytime and as long as required which is independent of address h
4697 * andshaking (it is not associated with any particular command).
4698 * PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN 0x1
4700 * If set to 1, enables aging function for the write channel of the port.
4701 * PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN 0x0
4703 * Determines the initial load value of write aging counters. These counter
4704 * s will be parallel loaded after reset, or after each grant to the corres
4705 * ponding port. The aging counters down-count every clock cycle where the
4706 * port is requesting but not granted. The higher significant 5-bits of the
4707 * write aging counter sets the initial priority of the write channel of a
4708 * given port. Port's priority will increase as the higher significant 5-b
4709 * its of the counter starts to decrease. When the aging counter becomes 0,
4710 * the corresponding port channel will have the highest priority level. Fo
4711 * r multi-port configurations, the aging counters cannot be used to set po
4712 * rt priorities when external dynamic priority inputs (awqos) are enabled
4713 * (timeout is still applicable). For single port configurations, the aging
4714 * counters are only used when they timeout (become 0) to force read-write
4715 * direction switching. Note: The two LSBs of this register field are tied
4716 * internally to 2'b00.
4717 * PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY 0xf
4719 * Port n Configuration Write Register
4720 * (OFFSET, MASK, VALUE) (0XFD070568, 0x000073FFU ,0x0000200FU)
4722 PSU_Mask_Write(DDRC_PCFGW_2_OFFSET, 0x000073FFU, 0x0000200FU);
4723 /*##################################################################### */
4726 * Register : PCTRL_2 @ 0XFD0705F0
4729 * PSU_DDRC_PCTRL_2_PORT_EN 0x1
4731 * Port n Control Register
4732 * (OFFSET, MASK, VALUE) (0XFD0705F0, 0x00000001U ,0x00000001U)
4734 PSU_Mask_Write(DDRC_PCTRL_2_OFFSET, 0x00000001U, 0x00000001U);
4735 /*##################################################################### */
4738 * Register : PCFGQOS0_2 @ 0XFD0705F4
4740 * This bitfield indicates the traffic class of region2. For dual address q
4741 * ueue configurations, region2 maps to the red address queue. Valid values
4742 * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN
4743 * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali
4744 * ased to LPR traffic.
4745 * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2 0x2
4747 * This bitfield indicates the traffic class of region 1. Valid values are:
4748 * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
4749 * maps to the blue address queue. In this case, valid values are 0: LPR a
4750 * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
4751 * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
4753 * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1 0x0
4755 * This bitfield indicates the traffic class of region 0. Valid values are:
4756 * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
4757 * maps to the blue address queue. In this case, valid values are: 0: LPR
4758 * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
4759 * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
4761 * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0 0x0
4763 * Separation level2 indicating the end of region1 mapping; start of region
4764 * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi
4765 * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note
4766 * that for PA, arqos values are used directly as port priorities, where t
4767 * he higher the value corresponds to higher port priority. All of the map_
4768 * level* registers must be set to distinct values.
4769 * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2 0xb
4771 * Separation level1 indicating the end of region0 mapping; start of region
4772 * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
4773 * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
4774 * lues are used directly as port priorities, where the higher the value co
4775 * rresponds to higher port priority. All of the map_level* registers must
4776 * be set to distinct values.
4777 * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1 0x3
4779 * Port n Read QoS Configuration Register 0
4780 * (OFFSET, MASK, VALUE) (0XFD0705F4, 0x03330F0FU ,0x02000B03U)
4782 PSU_Mask_Write(DDRC_PCFGQOS0_2_OFFSET, 0x03330F0FU, 0x02000B03U);
4783 /*##################################################################### */
4786 * Register : PCFGQOS1_2 @ 0XFD0705F8
4788 * Specifies the timeout value for transactions mapped to the red address q
4790 * PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR 0x0
4792 * Specifies the timeout value for transactions mapped to the blue address
4794 * PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB 0x0
4796 * Port n Read QoS Configuration Register 1
4797 * (OFFSET, MASK, VALUE) (0XFD0705F8, 0x07FF07FFU ,0x00000000U)
4799 PSU_Mask_Write(DDRC_PCFGQOS1_2_OFFSET, 0x07FF07FFU, 0x00000000U);
4800 /*##################################################################### */
4803 * Register : PCFGR_3 @ 0XFD070614
4805 * If set to 1, enables the Page Match feature. If enabled, once a requesti
4806 * ng port is granted, the port is continued to be granted if the following
4807 * immediate commands are to the same memory page (same bank and same row)
4808 * . See also related PCCFG.pagematch_limit register.
4809 * PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN 0x0
4811 * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
4812 * bled and arurgent is asserted by the master, that port becomes the highe
4813 * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
4814 * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
4815 * urgent signal can be asserted anytime and as long as required which is i
4816 * ndependent of address handshaking (it is not associated with any particu
4818 * PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN 0x1
4820 * If set to 1, enables aging function for the read channel of the port.
4821 * PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN 0x0
4823 * Determines the initial load value of read aging counters. These counters
4824 * will be parallel loaded after reset, or after each grant to the corresp
4825 * onding port. The aging counters down-count every clock cycle where the p
4826 * ort is requesting but not granted. The higher significant 5-bits of the
4827 * read aging counter sets the priority of the read channel of a given port
4828 * . Port's priority will increase as the higher significant 5-bits of the
4829 * counter starts to decrease. When the aging counter becomes 0, the corres
4830 * ponding port channel will have the highest priority level (timeout condi
4831 * tion - Priority0). For multi-port configurations, the aging counters can
4832 * not be used to set port priorities when external dynamic priority inputs
4833 * (arqos) are enabled (timeout is still applicable). For single port conf
4834 * igurations, the aging counters are only used when they timeout (become 0
4835 * ) to force read-write direction switching. In this case, external dynami
4836 * c priority input, arqos (for reads only) can still be used to set the DD
4837 * RC read priority (2 priority levels: low priority read - LPR, high prior
4838 * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
4839 * s register field are tied internally to 2'b00.
4840 * PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY 0xf
4842 * Port n Configuration Read Register
4843 * (OFFSET, MASK, VALUE) (0XFD070614, 0x000073FFU ,0x0000200FU)
4845 PSU_Mask_Write(DDRC_PCFGR_3_OFFSET, 0x000073FFU, 0x0000200FU);
4846 /*##################################################################### */
4849 * Register : PCFGW_3 @ 0XFD070618
4851 * If set to 1, enables the Page Match feature. If enabled, once a requesti
4852 * ng port is granted, the port is continued to be granted if the following
4853 * immediate commands are to the same memory page (same bank and same row)
4854 * . See also related PCCFG.pagematch_limit register.
4855 * PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN 0x0
4857 * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
4858 * bled and awurgent is asserted by the master, that port becomes the highe
4859 * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
4860 * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
4861 * serted anytime and as long as required which is independent of address h
4862 * andshaking (it is not associated with any particular command).
4863 * PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN 0x1
4865 * If set to 1, enables aging function for the write channel of the port.
4866 * PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN 0x0
4868 * Determines the initial load value of write aging counters. These counter
4869 * s will be parallel loaded after reset, or after each grant to the corres
4870 * ponding port. The aging counters down-count every clock cycle where the
4871 * port is requesting but not granted. The higher significant 5-bits of the
4872 * write aging counter sets the initial priority of the write channel of a
4873 * given port. Port's priority will increase as the higher significant 5-b
4874 * its of the counter starts to decrease. When the aging counter becomes 0,
4875 * the corresponding port channel will have the highest priority level. Fo
4876 * r multi-port configurations, the aging counters cannot be used to set po
4877 * rt priorities when external dynamic priority inputs (awqos) are enabled
4878 * (timeout is still applicable). For single port configurations, the aging
4879 * counters are only used when they timeout (become 0) to force read-write
4880 * direction switching. Note: The two LSBs of this register field are tied
4881 * internally to 2'b00.
4882 * PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY 0xf
4884 * Port n Configuration Write Register
4885 * (OFFSET, MASK, VALUE) (0XFD070618, 0x000073FFU ,0x0000200FU)
4887 PSU_Mask_Write(DDRC_PCFGW_3_OFFSET, 0x000073FFU, 0x0000200FU);
4888 /*##################################################################### */
4891 * Register : PCTRL_3 @ 0XFD0706A0
4894 * PSU_DDRC_PCTRL_3_PORT_EN 0x1
4896 * Port n Control Register
4897 * (OFFSET, MASK, VALUE) (0XFD0706A0, 0x00000001U ,0x00000001U)
4899 PSU_Mask_Write(DDRC_PCTRL_3_OFFSET, 0x00000001U, 0x00000001U);
4900 /*##################################################################### */
4903 * Register : PCFGQOS0_3 @ 0XFD0706A4
4905 * This bitfield indicates the traffic class of region 1. Valid values are:
4906 * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
4907 * maps to the blue address queue. In this case, valid values are 0: LPR a
4908 * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
4909 * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
4911 * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1 0x1
4913 * This bitfield indicates the traffic class of region 0. Valid values are:
4914 * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
4915 * maps to the blue address queue. In this case, valid values are: 0: LPR
4916 * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
4917 * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
4919 * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0 0x0
4921 * Separation level1 indicating the end of region0 mapping; start of region
4922 * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
4923 * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
4924 * lues are used directly as port priorities, where the higher the value co
4925 * rresponds to higher port priority. All of the map_level* registers must
4926 * be set to distinct values.
4927 * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1 0x3
4929 * Port n Read QoS Configuration Register 0
4930 * (OFFSET, MASK, VALUE) (0XFD0706A4, 0x0033000FU ,0x00100003U)
4932 PSU_Mask_Write(DDRC_PCFGQOS0_3_OFFSET, 0x0033000FU, 0x00100003U);
4933 /*##################################################################### */
4936 * Register : PCFGQOS1_3 @ 0XFD0706A8
4938 * Specifies the timeout value for transactions mapped to the red address q
4940 * PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR 0x0
4942 * Specifies the timeout value for transactions mapped to the blue address
4944 * PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB 0x4f
4946 * Port n Read QoS Configuration Register 1
4947 * (OFFSET, MASK, VALUE) (0XFD0706A8, 0x07FF07FFU ,0x0000004FU)
4949 PSU_Mask_Write(DDRC_PCFGQOS1_3_OFFSET, 0x07FF07FFU, 0x0000004FU);
4950 /*##################################################################### */
4953 * Register : PCFGWQOS0_3 @ 0XFD0706AC
4955 * This bitfield indicates the traffic class of region 1. Valid values are:
4956 * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
4957 * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW
4959 * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1 0x1
4961 * This bitfield indicates the traffic class of region 0. Valid values are:
4962 * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
4963 * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW
4965 * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0 0x0
4967 * Separation level indicating the end of region0 mapping; start of region0
4968 * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos
4969 * . Note that for PA, awqos values are used directly as port priorities, w
4970 * here the higher the value corresponds to higher port priority.
4971 * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL 0x3
4973 * Port n Write QoS Configuration Register 0
4974 * (OFFSET, MASK, VALUE) (0XFD0706AC, 0x0033000FU ,0x00100003U)
4976 PSU_Mask_Write(DDRC_PCFGWQOS0_3_OFFSET, 0x0033000FU, 0x00100003U);
4977 /*##################################################################### */
4980 * Register : PCFGWQOS1_3 @ 0XFD0706B0
4982 * Specifies the timeout value for write transactions.
4983 * PSU_DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT 0x4f
4985 * Port n Write QoS Configuration Register 1
4986 * (OFFSET, MASK, VALUE) (0XFD0706B0, 0x000007FFU ,0x0000004FU)
4988 PSU_Mask_Write(DDRC_PCFGWQOS1_3_OFFSET, 0x000007FFU, 0x0000004FU);
4989 /*##################################################################### */
4992 * Register : PCFGR_4 @ 0XFD0706C4
4994 * If set to 1, enables the Page Match feature. If enabled, once a requesti
4995 * ng port is granted, the port is continued to be granted if the following
4996 * immediate commands are to the same memory page (same bank and same row)
4997 * . See also related PCCFG.pagematch_limit register.
4998 * PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN 0x0
5000 * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
5001 * bled and arurgent is asserted by the master, that port becomes the highe
5002 * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
5003 * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
5004 * urgent signal can be asserted anytime and as long as required which is i
5005 * ndependent of address handshaking (it is not associated with any particu
5007 * PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN 0x1
5009 * If set to 1, enables aging function for the read channel of the port.
5010 * PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN 0x0
5012 * Determines the initial load value of read aging counters. These counters
5013 * will be parallel loaded after reset, or after each grant to the corresp
5014 * onding port. The aging counters down-count every clock cycle where the p
5015 * ort is requesting but not granted. The higher significant 5-bits of the
5016 * read aging counter sets the priority of the read channel of a given port
5017 * . Port's priority will increase as the higher significant 5-bits of the
5018 * counter starts to decrease. When the aging counter becomes 0, the corres
5019 * ponding port channel will have the highest priority level (timeout condi
5020 * tion - Priority0). For multi-port configurations, the aging counters can
5021 * not be used to set port priorities when external dynamic priority inputs
5022 * (arqos) are enabled (timeout is still applicable). For single port conf
5023 * igurations, the aging counters are only used when they timeout (become 0
5024 * ) to force read-write direction switching. In this case, external dynami
5025 * c priority input, arqos (for reads only) can still be used to set the DD
5026 * RC read priority (2 priority levels: low priority read - LPR, high prior
5027 * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
5028 * s register field are tied internally to 2'b00.
5029 * PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY 0xf
5031 * Port n Configuration Read Register
5032 * (OFFSET, MASK, VALUE) (0XFD0706C4, 0x000073FFU ,0x0000200FU)
5034 PSU_Mask_Write(DDRC_PCFGR_4_OFFSET, 0x000073FFU, 0x0000200FU);
5035 /*##################################################################### */
5038 * Register : PCFGW_4 @ 0XFD0706C8
5040 * If set to 1, enables the Page Match feature. If enabled, once a requesti
5041 * ng port is granted, the port is continued to be granted if the following
5042 * immediate commands are to the same memory page (same bank and same row)
5043 * . See also related PCCFG.pagematch_limit register.
5044 * PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN 0x0
5046 * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
5047 * bled and awurgent is asserted by the master, that port becomes the highe
5048 * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
5049 * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
5050 * serted anytime and as long as required which is independent of address h
5051 * andshaking (it is not associated with any particular command).
5052 * PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN 0x1
5054 * If set to 1, enables aging function for the write channel of the port.
5055 * PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN 0x0
5057 * Determines the initial load value of write aging counters. These counter
5058 * s will be parallel loaded after reset, or after each grant to the corres
5059 * ponding port. The aging counters down-count every clock cycle where the
5060 * port is requesting but not granted. The higher significant 5-bits of the
5061 * write aging counter sets the initial priority of the write channel of a
5062 * given port. Port's priority will increase as the higher significant 5-b
5063 * its of the counter starts to decrease. When the aging counter becomes 0,
5064 * the corresponding port channel will have the highest priority level. Fo
5065 * r multi-port configurations, the aging counters cannot be used to set po
5066 * rt priorities when external dynamic priority inputs (awqos) are enabled
5067 * (timeout is still applicable). For single port configurations, the aging
5068 * counters are only used when they timeout (become 0) to force read-write
5069 * direction switching. Note: The two LSBs of this register field are tied
5070 * internally to 2'b00.
5071 * PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY 0xf
5073 * Port n Configuration Write Register
5074 * (OFFSET, MASK, VALUE) (0XFD0706C8, 0x000073FFU ,0x0000200FU)
5076 PSU_Mask_Write(DDRC_PCFGW_4_OFFSET, 0x000073FFU, 0x0000200FU);
5077 /*##################################################################### */
5080 * Register : PCTRL_4 @ 0XFD070750
5083 * PSU_DDRC_PCTRL_4_PORT_EN 0x1
5085 * Port n Control Register
5086 * (OFFSET, MASK, VALUE) (0XFD070750, 0x00000001U ,0x00000001U)
5088 PSU_Mask_Write(DDRC_PCTRL_4_OFFSET, 0x00000001U, 0x00000001U);
5089 /*##################################################################### */
5092 * Register : PCFGQOS0_4 @ 0XFD070754
5094 * This bitfield indicates the traffic class of region 1. Valid values are:
5095 * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
5096 * maps to the blue address queue. In this case, valid values are 0: LPR a
5097 * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
5098 * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
5100 * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1 0x1
5102 * This bitfield indicates the traffic class of region 0. Valid values are:
5103 * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
5104 * maps to the blue address queue. In this case, valid values are: 0: LPR
5105 * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
5106 * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
5108 * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0 0x0
5110 * Separation level1 indicating the end of region0 mapping; start of region
5111 * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
5112 * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
5113 * lues are used directly as port priorities, where the higher the value co
5114 * rresponds to higher port priority. All of the map_level* registers must
5115 * be set to distinct values.
5116 * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1 0x3
5118 * Port n Read QoS Configuration Register 0
5119 * (OFFSET, MASK, VALUE) (0XFD070754, 0x0033000FU ,0x00100003U)
5121 PSU_Mask_Write(DDRC_PCFGQOS0_4_OFFSET, 0x0033000FU, 0x00100003U);
5122 /*##################################################################### */
5125 * Register : PCFGQOS1_4 @ 0XFD070758
5127 * Specifies the timeout value for transactions mapped to the red address q
5129 * PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR 0x0
5131 * Specifies the timeout value for transactions mapped to the blue address
5133 * PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB 0x4f
5135 * Port n Read QoS Configuration Register 1
5136 * (OFFSET, MASK, VALUE) (0XFD070758, 0x07FF07FFU ,0x0000004FU)
5138 PSU_Mask_Write(DDRC_PCFGQOS1_4_OFFSET, 0x07FF07FFU, 0x0000004FU);
5139 /*##################################################################### */
5142 * Register : PCFGWQOS0_4 @ 0XFD07075C
5144 * This bitfield indicates the traffic class of region 1. Valid values are:
5145 * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
5146 * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW
5148 * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1 0x1
5150 * This bitfield indicates the traffic class of region 0. Valid values are:
5151 * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
5152 * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW
5154 * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0 0x0
5156 * Separation level indicating the end of region0 mapping; start of region0
5157 * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos
5158 * . Note that for PA, awqos values are used directly as port priorities, w
5159 * here the higher the value corresponds to higher port priority.
5160 * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL 0x3
5162 * Port n Write QoS Configuration Register 0
5163 * (OFFSET, MASK, VALUE) (0XFD07075C, 0x0033000FU ,0x00100003U)
5165 PSU_Mask_Write(DDRC_PCFGWQOS0_4_OFFSET, 0x0033000FU, 0x00100003U);
5166 /*##################################################################### */
5169 * Register : PCFGWQOS1_4 @ 0XFD070760
5171 * Specifies the timeout value for write transactions.
5172 * PSU_DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT 0x4f
5174 * Port n Write QoS Configuration Register 1
5175 * (OFFSET, MASK, VALUE) (0XFD070760, 0x000007FFU ,0x0000004FU)
5177 PSU_Mask_Write(DDRC_PCFGWQOS1_4_OFFSET, 0x000007FFU, 0x0000004FU);
5178 /*##################################################################### */
5181 * Register : PCFGR_5 @ 0XFD070774
5183 * If set to 1, enables the Page Match feature. If enabled, once a requesti
5184 * ng port is granted, the port is continued to be granted if the following
5185 * immediate commands are to the same memory page (same bank and same row)
5186 * . See also related PCCFG.pagematch_limit register.
5187 * PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN 0x0
5189 * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
5190 * bled and arurgent is asserted by the master, that port becomes the highe
5191 * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
5192 * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
5193 * urgent signal can be asserted anytime and as long as required which is i
5194 * ndependent of address handshaking (it is not associated with any particu
5196 * PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN 0x1
5198 * If set to 1, enables aging function for the read channel of the port.
5199 * PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN 0x0
5201 * Determines the initial load value of read aging counters. These counters
5202 * will be parallel loaded after reset, or after each grant to the corresp
5203 * onding port. The aging counters down-count every clock cycle where the p
5204 * ort is requesting but not granted. The higher significant 5-bits of the
5205 * read aging counter sets the priority of the read channel of a given port
5206 * . Port's priority will increase as the higher significant 5-bits of the
5207 * counter starts to decrease. When the aging counter becomes 0, the corres
5208 * ponding port channel will have the highest priority level (timeout condi
5209 * tion - Priority0). For multi-port configurations, the aging counters can
5210 * not be used to set port priorities when external dynamic priority inputs
5211 * (arqos) are enabled (timeout is still applicable). For single port conf
5212 * igurations, the aging counters are only used when they timeout (become 0
5213 * ) to force read-write direction switching. In this case, external dynami
5214 * c priority input, arqos (for reads only) can still be used to set the DD
5215 * RC read priority (2 priority levels: low priority read - LPR, high prior
5216 * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
5217 * s register field are tied internally to 2'b00.
5218 * PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY 0xf
5220 * Port n Configuration Read Register
5221 * (OFFSET, MASK, VALUE) (0XFD070774, 0x000073FFU ,0x0000200FU)
5223 PSU_Mask_Write(DDRC_PCFGR_5_OFFSET, 0x000073FFU, 0x0000200FU);
5224 /*##################################################################### */
5227 * Register : PCFGW_5 @ 0XFD070778
5229 * If set to 1, enables the Page Match feature. If enabled, once a requesti
5230 * ng port is granted, the port is continued to be granted if the following
5231 * immediate commands are to the same memory page (same bank and same row)
5232 * . See also related PCCFG.pagematch_limit register.
5233 * PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN 0x0
5235 * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
5236 * bled and awurgent is asserted by the master, that port becomes the highe
5237 * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
5238 * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
5239 * serted anytime and as long as required which is independent of address h
5240 * andshaking (it is not associated with any particular command).
5241 * PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN 0x1
5243 * If set to 1, enables aging function for the write channel of the port.
5244 * PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN 0x0
5246 * Determines the initial load value of write aging counters. These counter
5247 * s will be parallel loaded after reset, or after each grant to the corres
5248 * ponding port. The aging counters down-count every clock cycle where the
5249 * port is requesting but not granted. The higher significant 5-bits of the
5250 * write aging counter sets the initial priority of the write channel of a
5251 * given port. Port's priority will increase as the higher significant 5-b
5252 * its of the counter starts to decrease. When the aging counter becomes 0,
5253 * the corresponding port channel will have the highest priority level. Fo
5254 * r multi-port configurations, the aging counters cannot be used to set po
5255 * rt priorities when external dynamic priority inputs (awqos) are enabled
5256 * (timeout is still applicable). For single port configurations, the aging
5257 * counters are only used when they timeout (become 0) to force read-write
5258 * direction switching. Note: The two LSBs of this register field are tied
5259 * internally to 2'b00.
5260 * PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY 0xf
5262 * Port n Configuration Write Register
5263 * (OFFSET, MASK, VALUE) (0XFD070778, 0x000073FFU ,0x0000200FU)
5265 PSU_Mask_Write(DDRC_PCFGW_5_OFFSET, 0x000073FFU, 0x0000200FU);
5266 /*##################################################################### */
5269 * Register : PCTRL_5 @ 0XFD070800
5272 * PSU_DDRC_PCTRL_5_PORT_EN 0x1
5274 * Port n Control Register
5275 * (OFFSET, MASK, VALUE) (0XFD070800, 0x00000001U ,0x00000001U)
5277 PSU_Mask_Write(DDRC_PCTRL_5_OFFSET, 0x00000001U, 0x00000001U);
5278 /*##################################################################### */
5281 * Register : PCFGQOS0_5 @ 0XFD070804
5283 * This bitfield indicates the traffic class of region 1. Valid values are:
5284 * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
5285 * maps to the blue address queue. In this case, valid values are 0: LPR a
5286 * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
5287 * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
5289 * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1 0x1
5291 * This bitfield indicates the traffic class of region 0. Valid values are:
5292 * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
5293 * maps to the blue address queue. In this case, valid values are: 0: LPR
5294 * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
5295 * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
5297 * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0 0x0
5299 * Separation level1 indicating the end of region0 mapping; start of region
5300 * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
5301 * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
5302 * lues are used directly as port priorities, where the higher the value co
5303 * rresponds to higher port priority. All of the map_level* registers must
5304 * be set to distinct values.
5305 * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1 0x3
5307 * Port n Read QoS Configuration Register 0
5308 * (OFFSET, MASK, VALUE) (0XFD070804, 0x0033000FU ,0x00100003U)
5310 PSU_Mask_Write(DDRC_PCFGQOS0_5_OFFSET, 0x0033000FU, 0x00100003U);
5311 /*##################################################################### */
5314 * Register : PCFGQOS1_5 @ 0XFD070808
5316 * Specifies the timeout value for transactions mapped to the red address q
5318 * PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR 0x0
5320 * Specifies the timeout value for transactions mapped to the blue address
5322 * PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB 0x4f
5324 * Port n Read QoS Configuration Register 1
5325 * (OFFSET, MASK, VALUE) (0XFD070808, 0x07FF07FFU ,0x0000004FU)
5327 PSU_Mask_Write(DDRC_PCFGQOS1_5_OFFSET, 0x07FF07FFU, 0x0000004FU);
5328 /*##################################################################### */
5331 * Register : PCFGWQOS0_5 @ 0XFD07080C
5333 * This bitfield indicates the traffic class of region 1. Valid values are:
5334 * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
5335 * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW
5337 * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1 0x1
5339 * This bitfield indicates the traffic class of region 0. Valid values are:
5340 * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
5341 * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW
5343 * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0 0x0
5345 * Separation level indicating the end of region0 mapping; start of region0
5346 * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos
5347 * . Note that for PA, awqos values are used directly as port priorities, w
5348 * here the higher the value corresponds to higher port priority.
5349 * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL 0x3
5351 * Port n Write QoS Configuration Register 0
5352 * (OFFSET, MASK, VALUE) (0XFD07080C, 0x0033000FU ,0x00100003U)
5354 PSU_Mask_Write(DDRC_PCFGWQOS0_5_OFFSET, 0x0033000FU, 0x00100003U);
5355 /*##################################################################### */
5358 * Register : PCFGWQOS1_5 @ 0XFD070810
5360 * Specifies the timeout value for write transactions.
5361 * PSU_DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT 0x4f
5363 * Port n Write QoS Configuration Register 1
5364 * (OFFSET, MASK, VALUE) (0XFD070810, 0x000007FFU ,0x0000004FU)
5366 PSU_Mask_Write(DDRC_PCFGWQOS1_5_OFFSET, 0x000007FFU, 0x0000004FU);
5367 /*##################################################################### */
5370 * Register : SARBASE0 @ 0XFD070F04
5372 * Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x
5373 * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl
5374 * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
5375 * PSU_DDRC_SARBASE0_BASE_ADDR 0x0
5377 * SAR Base Address Register n
5378 * (OFFSET, MASK, VALUE) (0XFD070F04, 0x000001FFU ,0x00000000U)
5380 PSU_Mask_Write(DDRC_SARBASE0_OFFSET, 0x000001FFU, 0x00000000U);
5381 /*##################################################################### */
5384 * Register : SARSIZE0 @ 0XFD070F08
5386 * Number of blocks for address region n. This register determines the tota
5387 * l size of the region in multiples of minimum block size as specified by
5388 * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded
5389 * as number of blocks = nblocks + 1. For example, if register is programme
5390 * d to 0, region will have 1 block.
5391 * PSU_DDRC_SARSIZE0_NBLOCKS 0x0
5393 * SAR Size Register n
5394 * (OFFSET, MASK, VALUE) (0XFD070F08, 0x000000FFU ,0x00000000U)
5396 PSU_Mask_Write(DDRC_SARSIZE0_OFFSET, 0x000000FFU, 0x00000000U);
5397 /*##################################################################### */
5400 * Register : SARBASE1 @ 0XFD070F0C
5402 * Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x
5403 * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl
5404 * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
5405 * PSU_DDRC_SARBASE1_BASE_ADDR 0x10
5407 * SAR Base Address Register n
5408 * (OFFSET, MASK, VALUE) (0XFD070F0C, 0x000001FFU ,0x00000010U)
5410 PSU_Mask_Write(DDRC_SARBASE1_OFFSET, 0x000001FFU, 0x00000010U);
5411 /*##################################################################### */
5414 * Register : SARSIZE1 @ 0XFD070F10
5416 * Number of blocks for address region n. This register determines the tota
5417 * l size of the region in multiples of minimum block size as specified by
5418 * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded
5419 * as number of blocks = nblocks + 1. For example, if register is programme
5420 * d to 0, region will have 1 block.
5421 * PSU_DDRC_SARSIZE1_NBLOCKS 0xf
5423 * SAR Size Register n
5424 * (OFFSET, MASK, VALUE) (0XFD070F10, 0x000000FFU ,0x0000000FU)
5426 PSU_Mask_Write(DDRC_SARSIZE1_OFFSET, 0x000000FFU, 0x0000000FU);
5427 /*##################################################################### */
5430 * Register : DFITMG0_SHADOW @ 0XFD072190
5432 * Specifies the number of DFI clock cycles after an assertion or de-assert
5433 * ion of the DFI control signals that the control signals at the PHY-DRAM
5434 * interface reflect the assertion or de-assertion. If the DFI clock and th
5435 * e memory clock are not phase-aligned, this timing parameter should be ro
5436 * unded up to the next integer value. Note that if using RDIMM, it is nece
5437 * ssary to increment this parameter by RDIMM's extra cycle of latency in t
5438 * erms of DFI clock.
5439 * PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY 0x7
5441 * Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u
5442 * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en
5443 * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles
5444 * - 1 in terms of SDR clock cycles Refer to PHY specification for correct
5446 * PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR 0x1
5448 * Time from the assertion of a read command on the DFI interface to the as
5449 * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr
5450 * ect value. This corresponds to the DFI parameter trddata_en. Note that,
5451 * depending on the PHY, if using RDIMM, it may be necessary to use the val
5452 * ue (CL + 1) in the calculation of trddata_en. This is to compensate for
5453 * the extra cycle of latency through the RDIMM. Unit: Clocks
5454 * PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN 0x2
5456 * Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us
5457 * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is
5458 * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df
5459 * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR
5460 * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio
5461 * n for correct value.
5462 * PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR 0x1
5464 * Specifies the number of clock cycles between when dfi_wrdata_en is asser
5465 * ted to when the associated write data is driven on the dfi_wrdata signal
5466 * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY
5467 * specification for correct value. Note, max supported value is 8. Unit:
5469 * PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA 0x0
5471 * Write latency Number of clocks from the write command to write data enab
5472 * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr
5473 * lat. Refer to PHY specification for correct value.Note that, depending o
5474 * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1)
5475 * in the calculation of tphy_wrlat. This is to compensate for the extra c
5476 * ycle of latency through the RDIMM.
5477 * PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT 0x2
5479 * DFI Timing Shadow Register 0
5480 * (OFFSET, MASK, VALUE) (0XFD072190, 0x1FBFBF3FU ,0x07828002U)
5482 PSU_Mask_Write(DDRC_DFITMG0_SHADOW_OFFSET, 0x1FBFBF3FU, 0x07828002U);
5483 /*##################################################################### */
5486 * DDR CONTROLLER RESET
5489 * Register : RST_DDR_SS @ 0XFD1A0108
5491 * DDR block level reset inside of the DDR Sub System
5492 * PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X0
5494 * APM block level reset inside of the DDR Sub System
5495 * PSU_CRF_APB_RST_DDR_SS_APM_RESET 0X0
5497 * DDR sub system block level reset
5498 * (OFFSET, MASK, VALUE) (0XFD1A0108, 0x0000000CU ,0x00000000U)
5500 PSU_Mask_Write(CRF_APB_RST_DDR_SS_OFFSET, 0x0000000CU, 0x00000000U);
5501 /*##################################################################### */
5507 * Register : PGCR0 @ 0XFD080010
5510 * PSU_DDR_PHY_PGCR0_ADCP 0x0
5512 * Reserved. Returns zeroes on reads.
5513 * PSU_DDR_PHY_PGCR0_RESERVED_30_27 0x0
5516 * PSU_DDR_PHY_PGCR0_PHYFRST 0x1
5518 * Oscillator Mode Address/Command Delay Line Select
5519 * PSU_DDR_PHY_PGCR0_OSCACDL 0x3
5521 * Reserved. Returns zeroes on reads.
5522 * PSU_DDR_PHY_PGCR0_RESERVED_23_19 0x0
5524 * Digital Test Output Select
5525 * PSU_DDR_PHY_PGCR0_DTOSEL 0x0
5527 * Reserved. Returns zeroes on reads.
5528 * PSU_DDR_PHY_PGCR0_RESERVED_13 0x0
5530 * Oscillator Mode Division
5531 * PSU_DDR_PHY_PGCR0_OSCDIV 0xf
5534 * PSU_DDR_PHY_PGCR0_OSCEN 0x0
5536 * Reserved. Returns zeroes on reads.
5537 * PSU_DDR_PHY_PGCR0_RESERVED_7_0 0x0
5539 * PHY General Configuration Register 0
5540 * (OFFSET, MASK, VALUE) (0XFD080010, 0xFFFFFFFFU ,0x07001E00U)
5542 PSU_Mask_Write(DDR_PHY_PGCR0_OFFSET, 0xFFFFFFFFU, 0x07001E00U);
5543 /*##################################################################### */
5546 * Register : PGCR2 @ 0XFD080018
5548 * Clear Training Status Registers
5549 * PSU_DDR_PHY_PGCR2_CLRTSTAT 0x0
5551 * Clear Impedance Calibration
5552 * PSU_DDR_PHY_PGCR2_CLRZCAL 0x0
5554 * Clear Parity Error
5555 * PSU_DDR_PHY_PGCR2_CLRPERR 0x0
5557 * Initialization Complete Pin Configuration
5558 * PSU_DDR_PHY_PGCR2_ICPC 0x0
5560 * Data Training PUB Mode Exit Timer
5561 * PSU_DDR_PHY_PGCR2_DTPMXTMR 0xf
5563 * Initialization Bypass
5564 * PSU_DDR_PHY_PGCR2_INITFSMBYP 0x0
5567 * PSU_DDR_PHY_PGCR2_PLLFSMBYP 0x0
5570 * PSU_DDR_PHY_PGCR2_TREFPRD 0x10010
5572 * PHY General Configuration Register 2
5573 * (OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F10010U)
5575 PSU_Mask_Write(DDR_PHY_PGCR2_OFFSET, 0xFFFFFFFFU, 0x00F10010U);
5576 /*##################################################################### */
5579 * Register : PGCR3 @ 0XFD08001C
5582 * PSU_DDR_PHY_PGCR3_CKNEN 0x55
5585 * PSU_DDR_PHY_PGCR3_CKEN 0xaa
5587 * Reserved. Return zeroes on reads.
5588 * PSU_DDR_PHY_PGCR3_RESERVED_15 0x0
5590 * Enable Clock Gating for AC [0] ctl_rd_clk
5591 * PSU_DDR_PHY_PGCR3_GATEACRDCLK 0x2
5593 * Enable Clock Gating for AC [0] ddr_clk
5594 * PSU_DDR_PHY_PGCR3_GATEACDDRCLK 0x2
5596 * Enable Clock Gating for AC [0] ctl_clk
5597 * PSU_DDR_PHY_PGCR3_GATEACCTLCLK 0x2
5599 * Reserved. Return zeroes on reads.
5600 * PSU_DDR_PHY_PGCR3_RESERVED_8 0x0
5602 * Controls DDL Bypass Modes
5603 * PSU_DDR_PHY_PGCR3_DDLBYPMODE 0x2
5605 * IO Loop-Back Select
5606 * PSU_DDR_PHY_PGCR3_IOLB 0x0
5608 * AC Receive FIFO Read Mode
5609 * PSU_DDR_PHY_PGCR3_RDMODE 0x0
5611 * Read FIFO Reset Disable
5612 * PSU_DDR_PHY_PGCR3_DISRST 0x0
5614 * Clock Level when Clock Gating
5615 * PSU_DDR_PHY_PGCR3_CLKLEVEL 0x0
5617 * PHY General Configuration Register 3
5618 * (OFFSET, MASK, VALUE) (0XFD08001C, 0xFFFFFFFFU ,0x55AA5480U)
5620 PSU_Mask_Write(DDR_PHY_PGCR3_OFFSET, 0xFFFFFFFFU, 0x55AA5480U);
5621 /*##################################################################### */
5624 * Register : PGCR5 @ 0XFD080024
5626 * Frequency B Ratio Term
5627 * PSU_DDR_PHY_PGCR5_FRQBT 0x1
5629 * Frequency A Ratio Term
5630 * PSU_DDR_PHY_PGCR5_FRQAT 0x1
5632 * DFI Disconnect Time Period
5633 * PSU_DDR_PHY_PGCR5_DISCNPERIOD 0x0
5635 * Receiver bias core side control
5636 * PSU_DDR_PHY_PGCR5_VREF_RBCTRL 0xf
5638 * Reserved. Return zeroes on reads.
5639 * PSU_DDR_PHY_PGCR5_RESERVED_3 0x0
5641 * Internal VREF generator REFSEL ragne select
5642 * PSU_DDR_PHY_PGCR5_DXREFISELRANGE 0x1
5644 * DDL Page Read Write select
5645 * PSU_DDR_PHY_PGCR5_DDLPGACT 0x0
5647 * DDL Page Read Write select
5648 * PSU_DDR_PHY_PGCR5_DDLPGRW 0x0
5650 * PHY General Configuration Register 5
5651 * (OFFSET, MASK, VALUE) (0XFD080024, 0xFFFFFFFFU ,0x010100F4U)
5653 PSU_Mask_Write(DDR_PHY_PGCR5_OFFSET, 0xFFFFFFFFU, 0x010100F4U);
5654 /*##################################################################### */
5657 * Register : PTR0 @ 0XFD080040
5659 * PLL Power-Down Time
5660 * PSU_DDR_PHY_PTR0_TPLLPD 0x56
5662 * PLL Gear Shift Time
5663 * PSU_DDR_PHY_PTR0_TPLLGS 0x2155
5666 * PSU_DDR_PHY_PTR0_TPHYRST 0x10
5668 * PHY Timing Register 0
5669 * (OFFSET, MASK, VALUE) (0XFD080040, 0xFFFFFFFFU ,0x0AC85550U)
5671 PSU_Mask_Write(DDR_PHY_PTR0_OFFSET, 0xFFFFFFFFU, 0x0AC85550U);
5672 /*##################################################################### */
5675 * Register : PTR1 @ 0XFD080044
5678 * PSU_DDR_PHY_PTR1_TPLLLOCK 0x4141
5680 * Reserved. Returns zeroes on reads.
5681 * PSU_DDR_PHY_PTR1_RESERVED_15_13 0x0
5684 * PSU_DDR_PHY_PTR1_TPLLRST 0xaff
5686 * PHY Timing Register 1
5687 * (OFFSET, MASK, VALUE) (0XFD080044, 0xFFFFFFFFU ,0x41410AFFU)
5689 PSU_Mask_Write(DDR_PHY_PTR1_OFFSET, 0xFFFFFFFFU, 0x41410AFFU);
5690 /*##################################################################### */
5693 * Register : PLLCR0 @ 0XFD080068
5696 * PSU_DDR_PHY_PLLCR0_PLLBYP 0x0
5699 * PSU_DDR_PHY_PLLCR0_PLLRST 0x0
5702 * PSU_DDR_PHY_PLLCR0_PLLPD 0x0
5704 * Reference Stop Mode
5705 * PSU_DDR_PHY_PLLCR0_RSTOPM 0x0
5707 * PLL Frequency Select
5708 * PSU_DDR_PHY_PLLCR0_FRQSEL 0x1
5711 * PSU_DDR_PHY_PLLCR0_RLOCKM 0x0
5713 * Charge Pump Proportional Current Control
5714 * PSU_DDR_PHY_PLLCR0_CPPC 0x8
5716 * Charge Pump Integrating Current Control
5717 * PSU_DDR_PHY_PLLCR0_CPIC 0x0
5720 * PSU_DDR_PHY_PLLCR0_GSHIFT 0x0
5722 * Reserved. Return zeroes on reads.
5723 * PSU_DDR_PHY_PLLCR0_RESERVED_11_9 0x0
5725 * Analog Test Enable
5726 * PSU_DDR_PHY_PLLCR0_ATOEN 0x0
5728 * Analog Test Control
5729 * PSU_DDR_PHY_PLLCR0_ATC 0x0
5731 * Digital Test Control
5732 * PSU_DDR_PHY_PLLCR0_DTC 0x0
5734 * PLL Control Register 0 (Type B PLL Only)
5735 * (OFFSET, MASK, VALUE) (0XFD080068, 0xFFFFFFFFU ,0x01100000U)
5737 PSU_Mask_Write(DDR_PHY_PLLCR0_OFFSET, 0xFFFFFFFFU, 0x01100000U);
5738 /*##################################################################### */
5741 * Register : DSGCR @ 0XFD080090
5743 * Reserved. Return zeroes on reads.
5744 * PSU_DDR_PHY_DSGCR_RESERVED_31_28 0x0
5746 * When RDBI enabled, this bit is used to select RDBI CL calculation, if it
5747 * is 1b1, calculation will use RDBICL, otherwise use default calculation.
5748 * PSU_DDR_PHY_DSGCR_RDBICLSEL 0x0
5750 * When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v
5752 * PSU_DDR_PHY_DSGCR_RDBICL 0x2
5754 * PHY Impedance Update Enable
5755 * PSU_DDR_PHY_DSGCR_PHYZUEN 0x1
5757 * Reserved. Return zeroes on reads.
5758 * PSU_DDR_PHY_DSGCR_RESERVED_22 0x0
5760 * SDRAM Reset Output Enable
5761 * PSU_DDR_PHY_DSGCR_RSTOE 0x1
5763 * Single Data Rate Mode
5764 * PSU_DDR_PHY_DSGCR_SDRMODE 0x0
5766 * Reserved. Return zeroes on reads.
5767 * PSU_DDR_PHY_DSGCR_RESERVED_18 0x0
5769 * ATO Analog Test Enable
5770 * PSU_DDR_PHY_DSGCR_ATOAE 0x0
5773 * PSU_DDR_PHY_DSGCR_DTOOE 0x0
5776 * PSU_DDR_PHY_DSGCR_DTOIOM 0x0
5778 * DTO Power Down Receiver
5779 * PSU_DDR_PHY_DSGCR_DTOPDR 0x1
5781 * Reserved. Return zeroes on reads
5782 * PSU_DDR_PHY_DSGCR_RESERVED_13 0x0
5784 * DTO On-Die Termination
5785 * PSU_DDR_PHY_DSGCR_DTOODT 0x0
5787 * PHY Update Acknowledge Delay
5788 * PSU_DDR_PHY_DSGCR_PUAD 0x5
5790 * Controller Update Acknowledge Enable
5791 * PSU_DDR_PHY_DSGCR_CUAEN 0x1
5793 * Reserved. Return zeroes on reads
5794 * PSU_DDR_PHY_DSGCR_RESERVED_4_3 0x0
5796 * Controller Impedance Update Enable
5797 * PSU_DDR_PHY_DSGCR_CTLZUEN 0x0
5799 * Reserved. Return zeroes on reads
5800 * PSU_DDR_PHY_DSGCR_RESERVED_1 0x0
5802 * PHY Update Request Enable
5803 * PSU_DDR_PHY_DSGCR_PUREN 0x1
5805 * DDR System General Configuration Register
5806 * (OFFSET, MASK, VALUE) (0XFD080090, 0xFFFFFFFFU ,0x02A04161U)
5808 PSU_Mask_Write(DDR_PHY_DSGCR_OFFSET, 0xFFFFFFFFU, 0x02A04161U);
5809 /*##################################################################### */
5812 * Register : GPR0 @ 0XFD0800C0
5814 * General Purpose Register 0
5815 * PSU_DDR_PHY_GPR0_GPR0 0xd3
5817 * General Purpose Register 0
5818 * (OFFSET, MASK, VALUE) (0XFD0800C0, 0xFFFFFFFFU ,0x000000D3U)
5820 PSU_Mask_Write(DDR_PHY_GPR0_OFFSET, 0xFFFFFFFFU, 0x000000D3U);
5821 /*##################################################################### */
5824 * Register : DCR @ 0XFD080100
5826 * DDR4 Gear Down Timing.
5827 * PSU_DDR_PHY_DCR_GEARDN 0x0
5829 * Un-used Bank Group
5830 * PSU_DDR_PHY_DCR_UBG 0x0
5832 * Un-buffered DIMM Address Mirroring
5833 * PSU_DDR_PHY_DCR_UDIMM 0x0
5836 * PSU_DDR_PHY_DCR_DDR2T 0x0
5838 * No Simultaneous Rank Access
5839 * PSU_DDR_PHY_DCR_NOSRA 0x1
5841 * Reserved. Return zeroes on reads.
5842 * PSU_DDR_PHY_DCR_RESERVED_26_18 0x0
5845 * PSU_DDR_PHY_DCR_BYTEMASK 0x1
5848 * PSU_DDR_PHY_DCR_DDRTYPE 0x0
5850 * Multi-Purpose Register (MPR) DQ (DDR3 Only)
5851 * PSU_DDR_PHY_DCR_MPRDQ 0x0
5853 * Primary DQ (DDR3 Only)
5854 * PSU_DDR_PHY_DCR_PDQ 0x0
5857 * PSU_DDR_PHY_DCR_DDR8BNK 0x1
5860 * PSU_DDR_PHY_DCR_DDRMD 0x4
5862 * DRAM Configuration Register
5863 * (OFFSET, MASK, VALUE) (0XFD080100, 0xFFFFFFFFU ,0x0800040CU)
5865 PSU_Mask_Write(DDR_PHY_DCR_OFFSET, 0xFFFFFFFFU, 0x0800040CU);
5866 /*##################################################################### */
5869 * Register : DTPR0 @ 0XFD080110
5871 * Reserved. Return zeroes on reads.
5872 * PSU_DDR_PHY_DTPR0_RESERVED_31_29 0x0
5874 * Activate to activate command delay (different banks)
5875 * PSU_DDR_PHY_DTPR0_TRRD 0x6
5877 * Reserved. Return zeroes on reads.
5878 * PSU_DDR_PHY_DTPR0_RESERVED_23 0x0
5880 * Activate to precharge command delay
5881 * PSU_DDR_PHY_DTPR0_TRAS 0x24
5883 * Reserved. Return zeroes on reads.
5884 * PSU_DDR_PHY_DTPR0_RESERVED_15 0x0
5886 * Precharge command period
5887 * PSU_DDR_PHY_DTPR0_TRP 0xf
5889 * Reserved. Return zeroes on reads.
5890 * PSU_DDR_PHY_DTPR0_RESERVED_7_5 0x0
5892 * Internal read to precharge command delay
5893 * PSU_DDR_PHY_DTPR0_TRTP 0x8
5895 * DRAM Timing Parameters Register 0
5896 * (OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06240F08U)
5898 PSU_Mask_Write(DDR_PHY_DTPR0_OFFSET, 0xFFFFFFFFU, 0x06240F08U);
5899 /*##################################################################### */
5902 * Register : DTPR1 @ 0XFD080114
5904 * Reserved. Return zeroes on reads.
5905 * PSU_DDR_PHY_DTPR1_RESERVED_31 0x0
5907 * Minimum delay from when write leveling mode is programmed to the first D
5908 * QS/DQS# rising edge.
5909 * PSU_DDR_PHY_DTPR1_TWLMRD 0x28
5911 * Reserved. Return zeroes on reads.
5912 * PSU_DDR_PHY_DTPR1_RESERVED_23 0x0
5914 * 4-bank activate period
5915 * PSU_DDR_PHY_DTPR1_TFAW 0x20
5917 * Reserved. Return zeroes on reads.
5918 * PSU_DDR_PHY_DTPR1_RESERVED_15_11 0x0
5920 * Load mode update delay (DDR4 and DDR3 only)
5921 * PSU_DDR_PHY_DTPR1_TMOD 0x0
5923 * Reserved. Return zeroes on reads.
5924 * PSU_DDR_PHY_DTPR1_RESERVED_7_5 0x0
5926 * Load mode cycle time
5927 * PSU_DDR_PHY_DTPR1_TMRD 0x8
5929 * DRAM Timing Parameters Register 1
5930 * (OFFSET, MASK, VALUE) (0XFD080114, 0xFFFFFFFFU ,0x28200008U)
5932 PSU_Mask_Write(DDR_PHY_DTPR1_OFFSET, 0xFFFFFFFFU, 0x28200008U);
5933 /*##################################################################### */
5936 * Register : DTPR2 @ 0XFD080118
5938 * Reserved. Return zeroes on reads.
5939 * PSU_DDR_PHY_DTPR2_RESERVED_31_29 0x0
5941 * Read to Write command delay. Valid values are
5942 * PSU_DDR_PHY_DTPR2_TRTW 0x0
5944 * Reserved. Return zeroes on reads.
5945 * PSU_DDR_PHY_DTPR2_RESERVED_27_25 0x0
5947 * Read to ODT delay (DDR3 only)
5948 * PSU_DDR_PHY_DTPR2_TRTODT 0x0
5950 * Reserved. Return zeroes on reads.
5951 * PSU_DDR_PHY_DTPR2_RESERVED_23_20 0x0
5953 * CKE minimum pulse width
5954 * PSU_DDR_PHY_DTPR2_TCKE 0x7
5956 * Reserved. Return zeroes on reads.
5957 * PSU_DDR_PHY_DTPR2_RESERVED_15_10 0x0
5959 * Self refresh exit delay
5960 * PSU_DDR_PHY_DTPR2_TXS 0x300
5962 * DRAM Timing Parameters Register 2
5963 * (OFFSET, MASK, VALUE) (0XFD080118, 0xFFFFFFFFU ,0x00070300U)
5965 PSU_Mask_Write(DDR_PHY_DTPR2_OFFSET, 0xFFFFFFFFU, 0x00070300U);
5966 /*##################################################################### */
5969 * Register : DTPR3 @ 0XFD08011C
5971 * ODT turn-off delay extension
5972 * PSU_DDR_PHY_DTPR3_TOFDX 0x4
5974 * Read to read and write to write command delay
5975 * PSU_DDR_PHY_DTPR3_TCCD 0x0
5978 * PSU_DDR_PHY_DTPR3_TDLLK 0x300
5980 * Reserved. Return zeroes on reads.
5981 * PSU_DDR_PHY_DTPR3_RESERVED_15_12 0x0
5983 * Maximum DQS output access time from CK/CK# (LPDDR2/3 only)
5984 * PSU_DDR_PHY_DTPR3_TDQSCKMAX 0x8
5986 * Reserved. Return zeroes on reads.
5987 * PSU_DDR_PHY_DTPR3_RESERVED_7_3 0x0
5989 * DQS output access time from CK/CK# (LPDDR2/3 only)
5990 * PSU_DDR_PHY_DTPR3_TDQSCK 0x0
5992 * DRAM Timing Parameters Register 3
5993 * (OFFSET, MASK, VALUE) (0XFD08011C, 0xFFFFFFFFU ,0x83000800U)
5995 PSU_Mask_Write(DDR_PHY_DTPR3_OFFSET, 0xFFFFFFFFU, 0x83000800U);
5996 /*##################################################################### */
5999 * Register : DTPR4 @ 0XFD080120
6001 * Reserved. Return zeroes on reads.
6002 * PSU_DDR_PHY_DTPR4_RESERVED_31_30 0x0
6004 * ODT turn-on/turn-off delays (DDR2 only)
6005 * PSU_DDR_PHY_DTPR4_TAOND_TAOFD 0x0
6007 * Reserved. Return zeroes on reads.
6008 * PSU_DDR_PHY_DTPR4_RESERVED_27_26 0x0
6010 * Refresh-to-Refresh
6011 * PSU_DDR_PHY_DTPR4_TRFC 0x116
6013 * Reserved. Return zeroes on reads.
6014 * PSU_DDR_PHY_DTPR4_RESERVED_15_14 0x0
6016 * Write leveling output delay
6017 * PSU_DDR_PHY_DTPR4_TWLO 0x2b
6019 * Reserved. Return zeroes on reads.
6020 * PSU_DDR_PHY_DTPR4_RESERVED_7_5 0x0
6022 * Power down exit delay
6023 * PSU_DDR_PHY_DTPR4_TXP 0x7
6025 * DRAM Timing Parameters Register 4
6026 * (OFFSET, MASK, VALUE) (0XFD080120, 0xFFFFFFFFU ,0x01162B07U)
6028 PSU_Mask_Write(DDR_PHY_DTPR4_OFFSET, 0xFFFFFFFFU, 0x01162B07U);
6029 /*##################################################################### */
6032 * Register : DTPR5 @ 0XFD080124
6034 * Reserved. Return zeroes on reads.
6035 * PSU_DDR_PHY_DTPR5_RESERVED_31_24 0x0
6037 * Activate to activate command delay (same bank)
6038 * PSU_DDR_PHY_DTPR5_TRC 0x33
6040 * Reserved. Return zeroes on reads.
6041 * PSU_DDR_PHY_DTPR5_RESERVED_15 0x0
6043 * Activate to read or write delay
6044 * PSU_DDR_PHY_DTPR5_TRCD 0xf
6046 * Reserved. Return zeroes on reads.
6047 * PSU_DDR_PHY_DTPR5_RESERVED_7_5 0x0
6049 * Internal write to read command delay
6050 * PSU_DDR_PHY_DTPR5_TWTR 0x8
6052 * DRAM Timing Parameters Register 5
6053 * (OFFSET, MASK, VALUE) (0XFD080124, 0xFFFFFFFFU ,0x00330F08U)
6055 PSU_Mask_Write(DDR_PHY_DTPR5_OFFSET, 0xFFFFFFFFU, 0x00330F08U);
6056 /*##################################################################### */
6059 * Register : DTPR6 @ 0XFD080128
6061 * PUB Write Latency Enable
6062 * PSU_DDR_PHY_DTPR6_PUBWLEN 0x0
6064 * PUB Read Latency Enable
6065 * PSU_DDR_PHY_DTPR6_PUBRLEN 0x0
6067 * Reserved. Return zeroes on reads.
6068 * PSU_DDR_PHY_DTPR6_RESERVED_29_14 0x0
6071 * PSU_DDR_PHY_DTPR6_PUBWL 0xe
6073 * Reserved. Return zeroes on reads.
6074 * PSU_DDR_PHY_DTPR6_RESERVED_7_6 0x0
6077 * PSU_DDR_PHY_DTPR6_PUBRL 0xf
6079 * DRAM Timing Parameters Register 6
6080 * (OFFSET, MASK, VALUE) (0XFD080128, 0xFFFFFFFFU ,0x00000E0FU)
6082 PSU_Mask_Write(DDR_PHY_DTPR6_OFFSET, 0xFFFFFFFFU, 0x00000E0FU);
6083 /*##################################################################### */
6086 * Register : RDIMMGCR0 @ 0XFD080140
6088 * Reserved. Return zeroes on reads.
6089 * PSU_DDR_PHY_RDIMMGCR0_RESERVED_31 0x0
6091 * RDMIMM Quad CS Enable
6092 * PSU_DDR_PHY_RDIMMGCR0_QCSEN 0x0
6094 * Reserved. Return zeroes on reads.
6095 * PSU_DDR_PHY_RDIMMGCR0_RESERVED_29_28 0x0
6097 * RDIMM Outputs I/O Mode
6098 * PSU_DDR_PHY_RDIMMGCR0_RDIMMIOM 0x1
6100 * Reserved. Return zeroes on reads.
6101 * PSU_DDR_PHY_RDIMMGCR0_RESERVED_26_24 0x0
6103 * ERROUT# Output Enable
6104 * PSU_DDR_PHY_RDIMMGCR0_ERROUTOE 0x0
6107 * PSU_DDR_PHY_RDIMMGCR0_ERROUTIOM 0x1
6109 * ERROUT# Power Down Receiver
6110 * PSU_DDR_PHY_RDIMMGCR0_ERROUTPDR 0x0
6112 * Reserved. Return zeroes on reads.
6113 * PSU_DDR_PHY_RDIMMGCR0_RESERVED_20 0x0
6115 * ERROUT# On-Die Termination
6116 * PSU_DDR_PHY_RDIMMGCR0_ERROUTODT 0x0
6119 * PSU_DDR_PHY_RDIMMGCR0_LRDIMM 0x0
6122 * PSU_DDR_PHY_RDIMMGCR0_PARINIOM 0x0
6124 * Reserved. Return zeroes on reads.
6125 * PSU_DDR_PHY_RDIMMGCR0_RESERVED_16_8 0x0
6127 * Reserved. Return zeroes on reads.
6128 * PSU_DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD 0x0
6130 * Rank Mirror Enable.
6131 * PSU_DDR_PHY_RDIMMGCR0_RNKMRREN 0x2
6133 * Reserved. Return zeroes on reads.
6134 * PSU_DDR_PHY_RDIMMGCR0_RESERVED_3 0x0
6136 * Stop on Parity Error
6137 * PSU_DDR_PHY_RDIMMGCR0_SOPERR 0x0
6139 * Parity Error No Registering
6140 * PSU_DDR_PHY_RDIMMGCR0_ERRNOREG 0x0
6143 * PSU_DDR_PHY_RDIMMGCR0_RDIMM 0x0
6145 * RDIMM General Configuration Register 0
6146 * (OFFSET, MASK, VALUE) (0XFD080140, 0xFFFFFFFFU ,0x08400020U)
6148 PSU_Mask_Write(DDR_PHY_RDIMMGCR0_OFFSET, 0xFFFFFFFFU, 0x08400020U);
6149 /*##################################################################### */
6152 * Register : RDIMMGCR1 @ 0XFD080144
6154 * Reserved. Return zeroes on reads.
6155 * PSU_DDR_PHY_RDIMMGCR1_RESERVED_31_29 0x0
6157 * Address [17] B-side Inversion Disable
6158 * PSU_DDR_PHY_RDIMMGCR1_A17BID 0x0
6160 * Reserved. Return zeroes on reads.
6161 * PSU_DDR_PHY_RDIMMGCR1_RESERVED_27 0x0
6163 * Command word to command word programming delay
6164 * PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L2 0x0
6166 * Reserved. Return zeroes on reads.
6167 * PSU_DDR_PHY_RDIMMGCR1_RESERVED_23 0x0
6169 * Command word to command word programming delay
6170 * PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L 0x0
6172 * Reserved. Return zeroes on reads.
6173 * PSU_DDR_PHY_RDIMMGCR1_RESERVED_19 0x0
6175 * Command word to command word programming delay
6176 * PSU_DDR_PHY_RDIMMGCR1_TBCMRD 0x0
6178 * Reserved. Return zeroes on reads.
6179 * PSU_DDR_PHY_RDIMMGCR1_RESERVED_15_14 0x0
6181 * Stabilization time
6182 * PSU_DDR_PHY_RDIMMGCR1_TBCSTAB 0xc80
6184 * RDIMM General Configuration Register 1
6185 * (OFFSET, MASK, VALUE) (0XFD080144, 0xFFFFFFFFU ,0x00000C80U)
6187 PSU_Mask_Write(DDR_PHY_RDIMMGCR1_OFFSET, 0xFFFFFFFFU, 0x00000C80U);
6188 /*##################################################################### */
6191 * Register : RDIMMCR0 @ 0XFD080150
6193 * DDR4/DDR3 Control Word 7
6194 * PSU_DDR_PHY_RDIMMCR0_RC7 0x0
6196 * DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved
6197 * PSU_DDR_PHY_RDIMMCR0_RC6 0x0
6199 * DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)
6200 * PSU_DDR_PHY_RDIMMCR0_RC5 0x0
6202 * DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control
6203 * Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont
6205 * PSU_DDR_PHY_RDIMMCR0_RC4 0x0
6207 * DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Wo
6208 * rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri
6210 * PSU_DDR_PHY_RDIMMCR0_RC3 0x0
6212 * DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2
6213 * (Timing Control Word)
6214 * PSU_DDR_PHY_RDIMMCR0_RC2 0x0
6216 * DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)
6217 * PSU_DDR_PHY_RDIMMCR0_RC1 0x0
6219 * DDR4/DDR3 Control Word 0 (Global Features Control Word)
6220 * PSU_DDR_PHY_RDIMMCR0_RC0 0x0
6222 * RDIMM Control Register 0
6223 * (OFFSET, MASK, VALUE) (0XFD080150, 0xFFFFFFFFU ,0x00000000U)
6225 PSU_Mask_Write(DDR_PHY_RDIMMCR0_OFFSET, 0xFFFFFFFFU, 0x00000000U);
6226 /*##################################################################### */
6229 * Register : RDIMMCR1 @ 0XFD080154
6232 * PSU_DDR_PHY_RDIMMCR1_RC15 0x0
6234 * DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved
6235 * PSU_DDR_PHY_RDIMMCR1_RC14 0x0
6237 * DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved
6238 * PSU_DDR_PHY_RDIMMCR1_RC13 0x0
6240 * DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved
6241 * PSU_DDR_PHY_RDIMMCR1_RC12 0x0
6243 * DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo
6244 * rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word)
6245 * PSU_DDR_PHY_RDIMMCR1_RC11 0x0
6247 * DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)
6248 * PSU_DDR_PHY_RDIMMCR1_RC10 0x2
6250 * DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)
6251 * PSU_DDR_PHY_RDIMMCR1_RC9 0x0
6253 * DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con
6254 * trol Word 8 (Additional Input Bus Termination Setting Control Word)
6255 * PSU_DDR_PHY_RDIMMCR1_RC8 0x0
6257 * RDIMM Control Register 1
6258 * (OFFSET, MASK, VALUE) (0XFD080154, 0xFFFFFFFFU ,0x00000200U)
6260 PSU_Mask_Write(DDR_PHY_RDIMMCR1_OFFSET, 0xFFFFFFFFU, 0x00000200U);
6261 /*##################################################################### */
6264 * Register : MR0 @ 0XFD080180
6266 * Reserved. Return zeroes on reads.
6267 * PSU_DDR_PHY_MR0_RESERVED_31_8 0x6
6269 * CA Terminating Rank
6270 * PSU_DDR_PHY_MR0_CATR 0x0
6272 * Reserved. These are JEDEC reserved bits and are recommended by JEDEC to
6273 * be programmed to 0x0.
6274 * PSU_DDR_PHY_MR0_RSVD_6_5 0x1
6276 * Built-in Self-Test for RZQ
6277 * PSU_DDR_PHY_MR0_RZQI 0x2
6279 * Reserved. These are JEDEC reserved bits and are recommended by JEDEC to
6280 * be programmed to 0x0.
6281 * PSU_DDR_PHY_MR0_RSVD_2_0 0x0
6283 * LPDDR4 Mode Register 0
6284 * (OFFSET, MASK, VALUE) (0XFD080180, 0xFFFFFFFFU ,0x00000630U)
6286 PSU_Mask_Write(DDR_PHY_MR0_OFFSET, 0xFFFFFFFFU, 0x00000630U);
6287 /*##################################################################### */
6290 * Register : MR1 @ 0XFD080184
6292 * Reserved. Return zeroes on reads.
6293 * PSU_DDR_PHY_MR1_RESERVED_31_8 0x3
6295 * Read Postamble Length
6296 * PSU_DDR_PHY_MR1_RDPST 0x0
6298 * Write-recovery for auto-precharge command
6299 * PSU_DDR_PHY_MR1_NWR 0x0
6301 * Read Preamble Length
6302 * PSU_DDR_PHY_MR1_RDPRE 0x0
6304 * Write Preamble Length
6305 * PSU_DDR_PHY_MR1_WRPRE 0x0
6308 * PSU_DDR_PHY_MR1_BL 0x1
6310 * LPDDR4 Mode Register 1
6311 * (OFFSET, MASK, VALUE) (0XFD080184, 0xFFFFFFFFU ,0x00000301U)
6313 PSU_Mask_Write(DDR_PHY_MR1_OFFSET, 0xFFFFFFFFU, 0x00000301U);
6314 /*##################################################################### */
6317 * Register : MR2 @ 0XFD080188
6319 * Reserved. Return zeroes on reads.
6320 * PSU_DDR_PHY_MR2_RESERVED_31_8 0x0
6323 * PSU_DDR_PHY_MR2_WRL 0x0
6326 * PSU_DDR_PHY_MR2_WLS 0x0
6329 * PSU_DDR_PHY_MR2_WL 0x4
6332 * PSU_DDR_PHY_MR2_RL 0x0
6334 * LPDDR4 Mode Register 2
6335 * (OFFSET, MASK, VALUE) (0XFD080188, 0xFFFFFFFFU ,0x00000020U)
6337 PSU_Mask_Write(DDR_PHY_MR2_OFFSET, 0xFFFFFFFFU, 0x00000020U);
6338 /*##################################################################### */
6341 * Register : MR3 @ 0XFD08018C
6343 * Reserved. Return zeroes on reads.
6344 * PSU_DDR_PHY_MR3_RESERVED_31_8 0x2
6347 * PSU_DDR_PHY_MR3_DBIWR 0x0
6350 * PSU_DDR_PHY_MR3_DBIRD 0x0
6352 * Pull-down Drive Strength
6353 * PSU_DDR_PHY_MR3_PDDS 0x0
6355 * These are JEDEC reserved bits and are recommended by JEDEC to be program
6357 * PSU_DDR_PHY_MR3_RSVD 0x0
6359 * Write Postamble Length
6360 * PSU_DDR_PHY_MR3_WRPST 0x0
6362 * Pull-up Calibration Point
6363 * PSU_DDR_PHY_MR3_PUCAL 0x0
6365 * LPDDR4 Mode Register 3
6366 * (OFFSET, MASK, VALUE) (0XFD08018C, 0xFFFFFFFFU ,0x00000200U)
6368 PSU_Mask_Write(DDR_PHY_MR3_OFFSET, 0xFFFFFFFFU, 0x00000200U);
6369 /*##################################################################### */
6372 * Register : MR4 @ 0XFD080190
6374 * Reserved. Return zeroes on reads.
6375 * PSU_DDR_PHY_MR4_RESERVED_31_16 0x0
6377 * These are JEDEC reserved bits and are recommended by JEDEC to be program
6379 * PSU_DDR_PHY_MR4_RSVD_15_13 0x0
6382 * PSU_DDR_PHY_MR4_WRP 0x0
6385 * PSU_DDR_PHY_MR4_RDP 0x0
6387 * Read Preamble Training Mode
6388 * PSU_DDR_PHY_MR4_RPTM 0x0
6390 * Self Refresh Abort
6391 * PSU_DDR_PHY_MR4_SRA 0x0
6393 * CS to Command Latency Mode
6394 * PSU_DDR_PHY_MR4_CS2CMDL 0x0
6396 * These are JEDEC reserved bits and are recommended by JEDEC to be program
6398 * PSU_DDR_PHY_MR4_RSVD1 0x0
6400 * Internal VREF Monitor
6401 * PSU_DDR_PHY_MR4_IVM 0x0
6403 * Temperature Controlled Refresh Mode
6404 * PSU_DDR_PHY_MR4_TCRM 0x0
6406 * Temperature Controlled Refresh Range
6407 * PSU_DDR_PHY_MR4_TCRR 0x0
6409 * Maximum Power Down Mode
6410 * PSU_DDR_PHY_MR4_MPDM 0x0
6412 * This is a JEDEC reserved bit and is recommended by JEDEC to be programme
6414 * PSU_DDR_PHY_MR4_RSVD_0 0x0
6416 * DDR4 Mode Register 4
6417 * (OFFSET, MASK, VALUE) (0XFD080190, 0xFFFFFFFFU ,0x00000000U)
6419 PSU_Mask_Write(DDR_PHY_MR4_OFFSET, 0xFFFFFFFFU, 0x00000000U);
6420 /*##################################################################### */
6423 * Register : MR5 @ 0XFD080194
6425 * Reserved. Return zeroes on reads.
6426 * PSU_DDR_PHY_MR5_RESERVED_31_16 0x0
6428 * These are JEDEC reserved bits and are recommended by JEDEC to be program
6430 * PSU_DDR_PHY_MR5_RSVD 0x0
6433 * PSU_DDR_PHY_MR5_RDBI 0x0
6436 * PSU_DDR_PHY_MR5_WDBI 0x0
6439 * PSU_DDR_PHY_MR5_DM 0x1
6441 * CA Parity Persistent Error
6442 * PSU_DDR_PHY_MR5_CAPPE 0x1
6445 * PSU_DDR_PHY_MR5_RTTPARK 0x3
6447 * ODT Input Buffer during Power Down mode
6448 * PSU_DDR_PHY_MR5_ODTIBPD 0x0
6450 * C/A Parity Error Status
6451 * PSU_DDR_PHY_MR5_CAPES 0x0
6454 * PSU_DDR_PHY_MR5_CRCEC 0x0
6456 * C/A Parity Latency Mode
6457 * PSU_DDR_PHY_MR5_CAPM 0x0
6459 * DDR4 Mode Register 5
6460 * (OFFSET, MASK, VALUE) (0XFD080194, 0xFFFFFFFFU ,0x000006C0U)
6462 PSU_Mask_Write(DDR_PHY_MR5_OFFSET, 0xFFFFFFFFU, 0x000006C0U);
6463 /*##################################################################### */
6466 * Register : MR6 @ 0XFD080198
6468 * Reserved. Return zeroes on reads.
6469 * PSU_DDR_PHY_MR6_RESERVED_31_16 0x0
6471 * These are JEDEC reserved bits and are recommended by JEDEC to be program
6473 * PSU_DDR_PHY_MR6_RSVD_15_13 0x0
6475 * CAS_n to CAS_n command delay for same bank group (tCCD_L)
6476 * PSU_DDR_PHY_MR6_TCCDL 0x2
6478 * These are JEDEC reserved bits and are recommended by JEDEC to be program
6480 * PSU_DDR_PHY_MR6_RSVD_9_8 0x0
6482 * VrefDQ Training Enable
6483 * PSU_DDR_PHY_MR6_VDDQTEN 0x0
6485 * VrefDQ Training Range
6486 * PSU_DDR_PHY_MR6_VDQTRG 0x0
6488 * VrefDQ Training Values
6489 * PSU_DDR_PHY_MR6_VDQTVAL 0x19
6491 * DDR4 Mode Register 6
6492 * (OFFSET, MASK, VALUE) (0XFD080198, 0xFFFFFFFFU ,0x00000819U)
6494 PSU_Mask_Write(DDR_PHY_MR6_OFFSET, 0xFFFFFFFFU, 0x00000819U);
6495 /*##################################################################### */
6498 * Register : MR11 @ 0XFD0801AC
6500 * Reserved. Return zeroes on reads.
6501 * PSU_DDR_PHY_MR11_RESERVED_31_8 0x0
6503 * These are JEDEC reserved bits and are recommended by JEDEC to be program
6505 * PSU_DDR_PHY_MR11_RSVD 0x0
6507 * Power Down Control
6508 * PSU_DDR_PHY_MR11_PDCTL 0x0
6510 * DQ Bus Receiver On-Die-Termination
6511 * PSU_DDR_PHY_MR11_DQODT 0x0
6513 * LPDDR4 Mode Register 11
6514 * (OFFSET, MASK, VALUE) (0XFD0801AC, 0xFFFFFFFFU ,0x00000000U)
6516 PSU_Mask_Write(DDR_PHY_MR11_OFFSET, 0xFFFFFFFFU, 0x00000000U);
6517 /*##################################################################### */
6520 * Register : MR12 @ 0XFD0801B0
6522 * Reserved. Return zeroes on reads.
6523 * PSU_DDR_PHY_MR12_RESERVED_31_8 0x0
6525 * These are JEDEC reserved bits and are recommended by JEDEC to be program
6527 * PSU_DDR_PHY_MR12_RSVD 0x0
6529 * VREF_CA Range Select.
6530 * PSU_DDR_PHY_MR12_VR_CA 0x1
6532 * Controls the VREF(ca) levels for Frequency-Set-Point[1:0].
6533 * PSU_DDR_PHY_MR12_VREF_CA 0xd
6535 * LPDDR4 Mode Register 12
6536 * (OFFSET, MASK, VALUE) (0XFD0801B0, 0xFFFFFFFFU ,0x0000004DU)
6538 PSU_Mask_Write(DDR_PHY_MR12_OFFSET, 0xFFFFFFFFU, 0x0000004DU);
6539 /*##################################################################### */
6542 * Register : MR13 @ 0XFD0801B4
6544 * Reserved. Return zeroes on reads.
6545 * PSU_DDR_PHY_MR13_RESERVED_31_8 0x0
6547 * Frequency Set Point Operation Mode
6548 * PSU_DDR_PHY_MR13_FSPOP 0x0
6550 * Frequency Set Point Write Enable
6551 * PSU_DDR_PHY_MR13_FSPWR 0x0
6554 * PSU_DDR_PHY_MR13_DMD 0x0
6556 * Refresh Rate Option
6557 * PSU_DDR_PHY_MR13_RRO 0x0
6559 * VREF Current Generator
6560 * PSU_DDR_PHY_MR13_VRCG 0x1
6563 * PSU_DDR_PHY_MR13_VRO 0x0
6565 * Read Preamble Training Mode
6566 * PSU_DDR_PHY_MR13_RPT 0x0
6568 * Command Bus Training
6569 * PSU_DDR_PHY_MR13_CBT 0x0
6571 * LPDDR4 Mode Register 13
6572 * (OFFSET, MASK, VALUE) (0XFD0801B4, 0xFFFFFFFFU ,0x00000008U)
6574 PSU_Mask_Write(DDR_PHY_MR13_OFFSET, 0xFFFFFFFFU, 0x00000008U);
6575 /*##################################################################### */
6578 * Register : MR14 @ 0XFD0801B8
6580 * Reserved. Return zeroes on reads.
6581 * PSU_DDR_PHY_MR14_RESERVED_31_8 0x0
6583 * These are JEDEC reserved bits and are recommended by JEDEC to be program
6585 * PSU_DDR_PHY_MR14_RSVD 0x0
6587 * VREFDQ Range Selects.
6588 * PSU_DDR_PHY_MR14_VR_DQ 0x1
6590 * Reserved. Return zeroes on reads.
6591 * PSU_DDR_PHY_MR14_VREF_DQ 0xd
6593 * LPDDR4 Mode Register 14
6594 * (OFFSET, MASK, VALUE) (0XFD0801B8, 0xFFFFFFFFU ,0x0000004DU)
6596 PSU_Mask_Write(DDR_PHY_MR14_OFFSET, 0xFFFFFFFFU, 0x0000004DU);
6597 /*##################################################################### */
6600 * Register : MR22 @ 0XFD0801D8
6602 * Reserved. Return zeroes on reads.
6603 * PSU_DDR_PHY_MR22_RESERVED_31_8 0x0
6605 * These are JEDEC reserved bits and are recommended by JEDEC to be program
6607 * PSU_DDR_PHY_MR22_RSVD 0x0
6609 * CA ODT termination disable.
6610 * PSU_DDR_PHY_MR22_ODTD_CA 0x0
6613 * PSU_DDR_PHY_MR22_ODTE_CS 0x0
6616 * PSU_DDR_PHY_MR22_ODTE_CK 0x0
6618 * Controller ODT value for VOH calibration.
6619 * PSU_DDR_PHY_MR22_CODT 0x0
6621 * LPDDR4 Mode Register 22
6622 * (OFFSET, MASK, VALUE) (0XFD0801D8, 0xFFFFFFFFU ,0x00000000U)
6624 PSU_Mask_Write(DDR_PHY_MR22_OFFSET, 0xFFFFFFFFU, 0x00000000U);
6625 /*##################################################################### */
6628 * Register : DTCR0 @ 0XFD080200
6630 * Refresh During Training
6631 * PSU_DDR_PHY_DTCR0_RFSHDT 0x8
6633 * Reserved. Return zeroes on reads.
6634 * PSU_DDR_PHY_DTCR0_RESERVED_27_26 0x0
6636 * Data Training Debug Rank Select
6637 * PSU_DDR_PHY_DTCR0_DTDRS 0x0
6639 * Data Training with Early/Extended Gate
6640 * PSU_DDR_PHY_DTCR0_DTEXG 0x0
6642 * Data Training Extended Write DQS
6643 * PSU_DDR_PHY_DTCR0_DTEXD 0x0
6645 * Data Training Debug Step
6646 * PSU_DDR_PHY_DTCR0_DTDSTP 0x0
6648 * Data Training Debug Enable
6649 * PSU_DDR_PHY_DTCR0_DTDEN 0x0
6651 * Data Training Debug Byte Select
6652 * PSU_DDR_PHY_DTCR0_DTDBS 0x0
6654 * Data Training read DBI deskewing configuration
6655 * PSU_DDR_PHY_DTCR0_DTRDBITR 0x2
6657 * Reserved. Return zeroes on reads.
6658 * PSU_DDR_PHY_DTCR0_RESERVED_13 0x0
6660 * Data Training Write Bit Deskew Data Mask
6661 * PSU_DDR_PHY_DTCR0_DTWBDDM 0x1
6663 * Refreshes Issued During Entry to Training
6664 * PSU_DDR_PHY_DTCR0_RFSHEN 0x1
6666 * Data Training Compare Data
6667 * PSU_DDR_PHY_DTCR0_DTCMPD 0x1
6669 * Data Training Using MPR
6670 * PSU_DDR_PHY_DTCR0_DTMPR 0x1
6672 * Reserved. Return zeroes on reads.
6673 * PSU_DDR_PHY_DTCR0_RESERVED_5_4 0x0
6675 * Data Training Repeat Number
6676 * PSU_DDR_PHY_DTCR0_DTRPTN 0x7
6678 * Data Training Configuration Register 0
6679 * (OFFSET, MASK, VALUE) (0XFD080200, 0xFFFFFFFFU ,0x800091C7U)
6681 PSU_Mask_Write(DDR_PHY_DTCR0_OFFSET, 0xFFFFFFFFU, 0x800091C7U);
6682 /*##################################################################### */
6685 * Register : DTCR1 @ 0XFD080204
6688 * PSU_DDR_PHY_DTCR1_RANKEN_RSVD 0x0
6691 * PSU_DDR_PHY_DTCR1_RANKEN 0x1
6693 * Reserved. Return zeroes on reads.
6694 * PSU_DDR_PHY_DTCR1_RESERVED_15_14 0x0
6696 * Data Training Rank
6697 * PSU_DDR_PHY_DTCR1_DTRANK 0x0
6699 * Reserved. Return zeroes on reads.
6700 * PSU_DDR_PHY_DTCR1_RESERVED_11 0x0
6702 * Read Leveling Gate Sampling Difference
6703 * PSU_DDR_PHY_DTCR1_RDLVLGDIFF 0x2
6705 * Reserved. Return zeroes on reads.
6706 * PSU_DDR_PHY_DTCR1_RESERVED_7 0x0
6708 * Read Leveling Gate Shift
6709 * PSU_DDR_PHY_DTCR1_RDLVLGS 0x3
6711 * Reserved. Return zeroes on reads.
6712 * PSU_DDR_PHY_DTCR1_RESERVED_3 0x0
6714 * Read Preamble Training enable
6715 * PSU_DDR_PHY_DTCR1_RDPRMVL_TRN 0x1
6717 * Read Leveling Enable
6718 * PSU_DDR_PHY_DTCR1_RDLVLEN 0x1
6720 * Basic Gate Training Enable
6721 * PSU_DDR_PHY_DTCR1_BSTEN 0x0
6723 * Data Training Configuration Register 1
6724 * (OFFSET, MASK, VALUE) (0XFD080204, 0xFFFFFFFFU ,0x00010236U)
6726 PSU_Mask_Write(DDR_PHY_DTCR1_OFFSET, 0xFFFFFFFFU, 0x00010236U);
6727 /*##################################################################### */
6730 * Register : CATR0 @ 0XFD080240
6732 * Reserved. Return zeroes on reads.
6733 * PSU_DDR_PHY_CATR0_RESERVED_31_21 0x0
6735 * Minimum time (in terms of number of dram clocks) between two consectuve
6736 * CA calibration command
6737 * PSU_DDR_PHY_CATR0_CACD 0x14
6739 * Reserved. Return zeroes on reads.
6740 * PSU_DDR_PHY_CATR0_RESERVED_15_13 0x0
6742 * Minimum time (in terms of number of dram clocks) PUB should wait before
6743 * sampling the CA response after Calibration command has been sent to the
6745 * PSU_DDR_PHY_CATR0_CAADR 0x10
6747 * CA_1 Response Byte Lane 1
6748 * PSU_DDR_PHY_CATR0_CA1BYTE1 0x5
6750 * CA_1 Response Byte Lane 0
6751 * PSU_DDR_PHY_CATR0_CA1BYTE0 0x4
6753 * CA Training Register 0
6754 * (OFFSET, MASK, VALUE) (0XFD080240, 0xFFFFFFFFU ,0x00141054U)
6756 PSU_Mask_Write(DDR_PHY_CATR0_OFFSET, 0xFFFFFFFFU, 0x00141054U);
6757 /*##################################################################### */
6760 * Register : DQSDR0 @ 0XFD080250
6762 * Number of delay taps by which the DQS gate LCDL will be updated when DQS
6764 * PSU_DDR_PHY_DQSDR0_DFTDLY 0x0
6766 * Drift Impedance Update
6767 * PSU_DDR_PHY_DQSDR0_DFTZQUP 0x0
6770 * PSU_DDR_PHY_DQSDR0_DFTDDLUP 0x0
6772 * Reserved. Return zeroes on reads.
6773 * PSU_DDR_PHY_DQSDR0_RESERVED_25_22 0x0
6775 * Drift Read Spacing
6776 * PSU_DDR_PHY_DQSDR0_DFTRDSPC 0x0
6778 * Drift Back-to-Back Reads
6779 * PSU_DDR_PHY_DQSDR0_DFTB2BRD 0x8
6782 * PSU_DDR_PHY_DQSDR0_DFTIDLRD 0x8
6784 * Reserved. Return zeroes on reads.
6785 * PSU_DDR_PHY_DQSDR0_RESERVED_11_8 0x0
6788 * PSU_DDR_PHY_DQSDR0_DFTGPULSE 0x0
6790 * DQS Drift Update Mode
6791 * PSU_DDR_PHY_DQSDR0_DFTUPMODE 0x0
6793 * DQS Drift Detection Mode
6794 * PSU_DDR_PHY_DQSDR0_DFTDTMODE 0x0
6796 * DQS Drift Detection Enable
6797 * PSU_DDR_PHY_DQSDR0_DFTDTEN 0x0
6799 * DQS Drift Register 0
6800 * (OFFSET, MASK, VALUE) (0XFD080250, 0xFFFFFFFFU ,0x00088000U)
6802 PSU_Mask_Write(DDR_PHY_DQSDR0_OFFSET, 0xFFFFFFFFU, 0x00088000U);
6803 /*##################################################################### */
6806 * Register : BISTLSR @ 0XFD080414
6808 * LFSR seed for pseudo-random BIST patterns
6809 * PSU_DDR_PHY_BISTLSR_SEED 0x12341000
6811 * BIST LFSR Seed Register
6812 * (OFFSET, MASK, VALUE) (0XFD080414, 0xFFFFFFFFU ,0x12341000U)
6814 PSU_Mask_Write(DDR_PHY_BISTLSR_OFFSET, 0xFFFFFFFFU, 0x12341000U);
6815 /*##################################################################### */
6818 * Register : RIOCR5 @ 0XFD0804F4
6820 * Reserved. Return zeroes on reads.
6821 * PSU_DDR_PHY_RIOCR5_RESERVED_31_16 0x0
6823 * Reserved. Return zeros on reads.
6824 * PSU_DDR_PHY_RIOCR5_ODTOEMODE_RSVD 0x0
6826 * SDRAM On-die Termination Output Enable (OE) Mode Selection.
6827 * PSU_DDR_PHY_RIOCR5_ODTOEMODE 0x5
6829 * Rank I/O Configuration Register 5
6830 * (OFFSET, MASK, VALUE) (0XFD0804F4, 0xFFFFFFFFU ,0x00000005U)
6832 PSU_Mask_Write(DDR_PHY_RIOCR5_OFFSET, 0xFFFFFFFFU, 0x00000005U);
6833 /*##################################################################### */
6836 * Register : ACIOCR0 @ 0XFD080500
6838 * Address/Command Slew Rate (D3F I/O Only)
6839 * PSU_DDR_PHY_ACIOCR0_ACSR 0x0
6841 * SDRAM Reset I/O Mode
6842 * PSU_DDR_PHY_ACIOCR0_RSTIOM 0x1
6844 * SDRAM Reset Power Down Receiver
6845 * PSU_DDR_PHY_ACIOCR0_RSTPDR 0x1
6847 * Reserved. Return zeroes on reads.
6848 * PSU_DDR_PHY_ACIOCR0_RESERVED_27 0x0
6850 * SDRAM Reset On-Die Termination
6851 * PSU_DDR_PHY_ACIOCR0_RSTODT 0x0
6853 * Reserved. Return zeroes on reads.
6854 * PSU_DDR_PHY_ACIOCR0_RESERVED_25_10 0x0
6856 * CK Duty Cycle Correction
6857 * PSU_DDR_PHY_ACIOCR0_CKDCC 0x0
6859 * AC Power Down Receiver Mode
6860 * PSU_DDR_PHY_ACIOCR0_ACPDRMODE 0x2
6862 * AC On-die Termination Mode
6863 * PSU_DDR_PHY_ACIOCR0_ACODTMODE 0x2
6865 * Reserved. Return zeroes on reads.
6866 * PSU_DDR_PHY_ACIOCR0_RESERVED_1 0x0
6868 * Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.
6869 * PSU_DDR_PHY_ACIOCR0_ACRANKCLKSEL 0x0
6871 * AC I/O Configuration Register 0
6872 * (OFFSET, MASK, VALUE) (0XFD080500, 0xFFFFFFFFU ,0x30000028U)
6874 PSU_Mask_Write(DDR_PHY_ACIOCR0_OFFSET, 0xFFFFFFFFU, 0x30000028U);
6875 /*##################################################################### */
6878 * Register : ACIOCR2 @ 0XFD080508
6880 * Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL
6882 * PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE 0x0
6884 * Clock gating for Output Enable D slices [0]
6885 * PSU_DDR_PHY_ACIOCR2_ACOECLKGATE0 0x0
6887 * Clock gating for Power Down Receiver D slices [0]
6888 * PSU_DDR_PHY_ACIOCR2_ACPDRCLKGATE0 0x0
6890 * Clock gating for Termination Enable D slices [0]
6891 * PSU_DDR_PHY_ACIOCR2_ACTECLKGATE0 0x0
6893 * Clock gating for CK# D slices [1:0]
6894 * PSU_DDR_PHY_ACIOCR2_CKNCLKGATE0 0x2
6896 * Clock gating for CK D slices [1:0]
6897 * PSU_DDR_PHY_ACIOCR2_CKCLKGATE0 0x2
6899 * Clock gating for AC D slices [23:0]
6900 * PSU_DDR_PHY_ACIOCR2_ACCLKGATE0 0x0
6902 * AC I/O Configuration Register 2
6903 * (OFFSET, MASK, VALUE) (0XFD080508, 0xFFFFFFFFU ,0x0A000000U)
6905 PSU_Mask_Write(DDR_PHY_ACIOCR2_OFFSET, 0xFFFFFFFFU, 0x0A000000U);
6906 /*##################################################################### */
6909 * Register : ACIOCR3 @ 0XFD08050C
6911 * SDRAM Parity Output Enable (OE) Mode Selection
6912 * PSU_DDR_PHY_ACIOCR3_PAROEMODE 0x0
6914 * SDRAM Bank Group Output Enable (OE) Mode Selection
6915 * PSU_DDR_PHY_ACIOCR3_BGOEMODE 0x0
6917 * SDRAM Bank Address Output Enable (OE) Mode Selection
6918 * PSU_DDR_PHY_ACIOCR3_BAOEMODE 0x0
6920 * SDRAM A[17] Output Enable (OE) Mode Selection
6921 * PSU_DDR_PHY_ACIOCR3_A17OEMODE 0x0
6923 * SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection
6924 * PSU_DDR_PHY_ACIOCR3_A16OEMODE 0x0
6926 * SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)
6927 * PSU_DDR_PHY_ACIOCR3_ACTOEMODE 0x0
6929 * Reserved. Return zeroes on reads.
6930 * PSU_DDR_PHY_ACIOCR3_RESERVED_15_8 0x0
6932 * Reserved. Return zeros on reads.
6933 * PSU_DDR_PHY_ACIOCR3_CKOEMODE_RSVD 0x0
6935 * SDRAM CK Output Enable (OE) Mode Selection.
6936 * PSU_DDR_PHY_ACIOCR3_CKOEMODE 0x9
6938 * AC I/O Configuration Register 3
6939 * (OFFSET, MASK, VALUE) (0XFD08050C, 0xFFFFFFFFU ,0x00000009U)
6941 PSU_Mask_Write(DDR_PHY_ACIOCR3_OFFSET, 0xFFFFFFFFU, 0x00000009U);
6942 /*##################################################################### */
6945 * Register : ACIOCR4 @ 0XFD080510
6947 * Clock gating for AC LB slices and loopback read valid slices
6948 * PSU_DDR_PHY_ACIOCR4_LBCLKGATE 0x0
6950 * Clock gating for Output Enable D slices [1]
6951 * PSU_DDR_PHY_ACIOCR4_ACOECLKGATE1 0x0
6953 * Clock gating for Power Down Receiver D slices [1]
6954 * PSU_DDR_PHY_ACIOCR4_ACPDRCLKGATE1 0x0
6956 * Clock gating for Termination Enable D slices [1]
6957 * PSU_DDR_PHY_ACIOCR4_ACTECLKGATE1 0x0
6959 * Clock gating for CK# D slices [3:2]
6960 * PSU_DDR_PHY_ACIOCR4_CKNCLKGATE1 0x2
6962 * Clock gating for CK D slices [3:2]
6963 * PSU_DDR_PHY_ACIOCR4_CKCLKGATE1 0x2
6965 * Clock gating for AC D slices [47:24]
6966 * PSU_DDR_PHY_ACIOCR4_ACCLKGATE1 0x0
6968 * AC I/O Configuration Register 4
6969 * (OFFSET, MASK, VALUE) (0XFD080510, 0xFFFFFFFFU ,0x0A000000U)
6971 PSU_Mask_Write(DDR_PHY_ACIOCR4_OFFSET, 0xFFFFFFFFU, 0x0A000000U);
6972 /*##################################################################### */
6975 * Register : IOVCR0 @ 0XFD080520
6977 * Reserved. Return zeroes on reads.
6978 * PSU_DDR_PHY_IOVCR0_RESERVED_31_29 0x0
6980 * Address/command lane VREF Pad Enable
6981 * PSU_DDR_PHY_IOVCR0_ACREFPEN 0x0
6983 * Address/command lane Internal VREF Enable
6984 * PSU_DDR_PHY_IOVCR0_ACREFEEN 0x0
6986 * Address/command lane Single-End VREF Enable
6987 * PSU_DDR_PHY_IOVCR0_ACREFSEN 0x1
6989 * Address/command lane Internal VREF Enable
6990 * PSU_DDR_PHY_IOVCR0_ACREFIEN 0x1
6992 * External VREF generato REFSEL range select
6993 * PSU_DDR_PHY_IOVCR0_ACREFESELRANGE 0x0
6995 * Address/command lane External VREF Select
6996 * PSU_DDR_PHY_IOVCR0_ACREFESEL 0x0
6998 * Single ended VREF generator REFSEL range select
6999 * PSU_DDR_PHY_IOVCR0_ACREFSSELRANGE 0x1
7001 * Address/command lane Single-End VREF Select
7002 * PSU_DDR_PHY_IOVCR0_ACREFSSEL 0x30
7004 * Internal VREF generator REFSEL ragne select
7005 * PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE 0x1
7007 * REFSEL Control for internal AC IOs
7008 * PSU_DDR_PHY_IOVCR0_ACVREFISEL 0x4e
7010 * IO VREF Control Register 0
7011 * (OFFSET, MASK, VALUE) (0XFD080520, 0xFFFFFFFFU ,0x0300B0CEU)
7013 PSU_Mask_Write(DDR_PHY_IOVCR0_OFFSET, 0xFFFFFFFFU, 0x0300B0CEU);
7014 /*##################################################################### */
7017 * Register : VTCR0 @ 0XFD080528
7019 * Number of ctl_clk required to meet (> 150ns) timing requirements during
7020 * DRAM DQ VREF training
7021 * PSU_DDR_PHY_VTCR0_TVREF 0x7
7023 * DRM DQ VREF training Enable
7024 * PSU_DDR_PHY_VTCR0_DVEN 0x1
7026 * Per Device Addressability Enable
7027 * PSU_DDR_PHY_VTCR0_PDAEN 0x1
7029 * Reserved. Returns zeroes on reads.
7030 * PSU_DDR_PHY_VTCR0_RESERVED_26 0x0
7033 * PSU_DDR_PHY_VTCR0_VWCR 0x4
7035 * DRAM DQ VREF step size used during DRAM VREF training
7036 * PSU_DDR_PHY_VTCR0_DVSS 0x0
7038 * Maximum VREF limit value used during DRAM VREF training
7039 * PSU_DDR_PHY_VTCR0_DVMAX 0x32
7041 * Minimum VREF limit value used during DRAM VREF training
7042 * PSU_DDR_PHY_VTCR0_DVMIN 0x0
7044 * Initial DRAM DQ VREF value used during DRAM VREF training
7045 * PSU_DDR_PHY_VTCR0_DVINIT 0x19
7047 * VREF Training Control Register 0
7048 * (OFFSET, MASK, VALUE) (0XFD080528, 0xFFFFFFFFU ,0xF9032019U)
7050 PSU_Mask_Write(DDR_PHY_VTCR0_OFFSET, 0xFFFFFFFFU, 0xF9032019U);
7051 /*##################################################################### */
7054 * Register : VTCR1 @ 0XFD08052C
7056 * Host VREF step size used during VREF training. The register value of N i
7057 * ndicates step size of (N+1)
7058 * PSU_DDR_PHY_VTCR1_HVSS 0x0
7060 * Reserved. Returns zeroes on reads.
7061 * PSU_DDR_PHY_VTCR1_RESERVED_27 0x0
7063 * Maximum VREF limit value used during DRAM VREF training.
7064 * PSU_DDR_PHY_VTCR1_HVMAX 0x7f
7066 * Reserved. Returns zeroes on reads.
7067 * PSU_DDR_PHY_VTCR1_RESERVED_19 0x0
7069 * Minimum VREF limit value used during DRAM VREF training.
7070 * PSU_DDR_PHY_VTCR1_HVMIN 0x0
7072 * Reserved. Returns zeroes on reads.
7073 * PSU_DDR_PHY_VTCR1_RESERVED_11 0x0
7075 * Static Host Vref Rank Value
7076 * PSU_DDR_PHY_VTCR1_SHRNK 0x0
7078 * Static Host Vref Rank Enable
7079 * PSU_DDR_PHY_VTCR1_SHREN 0x1
7081 * Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir
7082 * ements during Host IO VREF training
7083 * PSU_DDR_PHY_VTCR1_TVREFIO 0x7
7085 * Eye LCDL Offset value for VREF training
7086 * PSU_DDR_PHY_VTCR1_EOFF 0x0
7088 * Number of LCDL Eye points for which VREF training is repeated
7089 * PSU_DDR_PHY_VTCR1_ENUM 0x0
7091 * HOST (IO) internal VREF training Enable
7092 * PSU_DDR_PHY_VTCR1_HVEN 0x1
7094 * Host IO Type Control
7095 * PSU_DDR_PHY_VTCR1_HVIO 0x1
7097 * VREF Training Control Register 1
7098 * (OFFSET, MASK, VALUE) (0XFD08052C, 0xFFFFFFFFU ,0x07F001E3U)
7100 PSU_Mask_Write(DDR_PHY_VTCR1_OFFSET, 0xFFFFFFFFU, 0x07F001E3U);
7101 /*##################################################################### */
7104 * Register : ACBDLR1 @ 0XFD080544
7106 * Reserved. Return zeroes on reads.
7107 * PSU_DDR_PHY_ACBDLR1_RESERVED_31_30 0x0
7109 * Delay select for the BDL on Parity.
7110 * PSU_DDR_PHY_ACBDLR1_PARBD 0x0
7112 * Reserved. Return zeroes on reads.
7113 * PSU_DDR_PHY_ACBDLR1_RESERVED_23_22 0x0
7115 * Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn
7117 * PSU_DDR_PHY_ACBDLR1_A16BD 0x0
7119 * Reserved. Return zeroes on reads.
7120 * PSU_DDR_PHY_ACBDLR1_RESERVED_15_14 0x0
7122 * Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi
7123 * s pin is connected to CAS.
7124 * PSU_DDR_PHY_ACBDLR1_A17BD 0x0
7126 * Reserved. Return zeroes on reads.
7127 * PSU_DDR_PHY_ACBDLR1_RESERVED_7_6 0x0
7129 * Delay select for the BDL on ACTN.
7130 * PSU_DDR_PHY_ACBDLR1_ACTBD 0x0
7132 * AC Bit Delay Line Register 1
7133 * (OFFSET, MASK, VALUE) (0XFD080544, 0xFFFFFFFFU ,0x00000000U)
7135 PSU_Mask_Write(DDR_PHY_ACBDLR1_OFFSET, 0xFFFFFFFFU, 0x00000000U);
7136 /*##################################################################### */
7139 * Register : ACBDLR2 @ 0XFD080548
7141 * Reserved. Return zeroes on reads.
7142 * PSU_DDR_PHY_ACBDLR2_RESERVED_31_30 0x0
7144 * Delay select for the BDL on BG[1].
7145 * PSU_DDR_PHY_ACBDLR2_BG1BD 0x0
7147 * Reserved. Return zeroes on reads.
7148 * PSU_DDR_PHY_ACBDLR2_RESERVED_23_22 0x0
7150 * Delay select for the BDL on BG[0].
7151 * PSU_DDR_PHY_ACBDLR2_BG0BD 0x0
7153 * Reser.ved Return zeroes on reads.
7154 * PSU_DDR_PHY_ACBDLR2_RESERVED_15_14 0x0
7156 * Delay select for the BDL on BA[1].
7157 * PSU_DDR_PHY_ACBDLR2_BA1BD 0x0
7159 * Reserved. Return zeroes on reads.
7160 * PSU_DDR_PHY_ACBDLR2_RESERVED_7_6 0x0
7162 * Delay select for the BDL on BA[0].
7163 * PSU_DDR_PHY_ACBDLR2_BA0BD 0x0
7165 * AC Bit Delay Line Register 2
7166 * (OFFSET, MASK, VALUE) (0XFD080548, 0xFFFFFFFFU ,0x00000000U)
7168 PSU_Mask_Write(DDR_PHY_ACBDLR2_OFFSET, 0xFFFFFFFFU, 0x00000000U);
7169 /*##################################################################### */
7172 * Register : ACBDLR6 @ 0XFD080558
7174 * Reserved. Return zeroes on reads.
7175 * PSU_DDR_PHY_ACBDLR6_RESERVED_31_30 0x0
7177 * Delay select for the BDL on Address A[3].
7178 * PSU_DDR_PHY_ACBDLR6_A03BD 0x0
7180 * Reserved. Return zeroes on reads.
7181 * PSU_DDR_PHY_ACBDLR6_RESERVED_23_22 0x0
7183 * Delay select for the BDL on Address A[2].
7184 * PSU_DDR_PHY_ACBDLR6_A02BD 0x0
7186 * Reserved. Return zeroes on reads.
7187 * PSU_DDR_PHY_ACBDLR6_RESERVED_15_14 0x0
7189 * Delay select for the BDL on Address A[1].
7190 * PSU_DDR_PHY_ACBDLR6_A01BD 0x0
7192 * Reserved. Return zeroes on reads.
7193 * PSU_DDR_PHY_ACBDLR6_RESERVED_7_6 0x0
7195 * Delay select for the BDL on Address A[0].
7196 * PSU_DDR_PHY_ACBDLR6_A00BD 0x0
7198 * AC Bit Delay Line Register 6
7199 * (OFFSET, MASK, VALUE) (0XFD080558, 0xFFFFFFFFU ,0x00000000U)
7201 PSU_Mask_Write(DDR_PHY_ACBDLR6_OFFSET, 0xFFFFFFFFU, 0x00000000U);
7202 /*##################################################################### */
7205 * Register : ACBDLR7 @ 0XFD08055C
7207 * Reserved. Return zeroes on reads.
7208 * PSU_DDR_PHY_ACBDLR7_RESERVED_31_30 0x0
7210 * Delay select for the BDL on Address A[7].
7211 * PSU_DDR_PHY_ACBDLR7_A07BD 0x0
7213 * Reserved. Return zeroes on reads.
7214 * PSU_DDR_PHY_ACBDLR7_RESERVED_23_22 0x0
7216 * Delay select for the BDL on Address A[6].
7217 * PSU_DDR_PHY_ACBDLR7_A06BD 0x0
7219 * Reserved. Return zeroes on reads.
7220 * PSU_DDR_PHY_ACBDLR7_RESERVED_15_14 0x0
7222 * Delay select for the BDL on Address A[5].
7223 * PSU_DDR_PHY_ACBDLR7_A05BD 0x0
7225 * Reserved. Return zeroes on reads.
7226 * PSU_DDR_PHY_ACBDLR7_RESERVED_7_6 0x0
7228 * Delay select for the BDL on Address A[4].
7229 * PSU_DDR_PHY_ACBDLR7_A04BD 0x0
7231 * AC Bit Delay Line Register 7
7232 * (OFFSET, MASK, VALUE) (0XFD08055C, 0xFFFFFFFFU ,0x00000000U)
7234 PSU_Mask_Write(DDR_PHY_ACBDLR7_OFFSET, 0xFFFFFFFFU, 0x00000000U);
7235 /*##################################################################### */
7238 * Register : ACBDLR8 @ 0XFD080560
7240 * Reserved. Return zeroes on reads.
7241 * PSU_DDR_PHY_ACBDLR8_RESERVED_31_30 0x0
7243 * Delay select for the BDL on Address A[11].
7244 * PSU_DDR_PHY_ACBDLR8_A11BD 0x0
7246 * Reserved. Return zeroes on reads.
7247 * PSU_DDR_PHY_ACBDLR8_RESERVED_23_22 0x0
7249 * Delay select for the BDL on Address A[10].
7250 * PSU_DDR_PHY_ACBDLR8_A10BD 0x0
7252 * Reserved. Return zeroes on reads.
7253 * PSU_DDR_PHY_ACBDLR8_RESERVED_15_14 0x0
7255 * Delay select for the BDL on Address A[9].
7256 * PSU_DDR_PHY_ACBDLR8_A09BD 0x0
7258 * Reserved. Return zeroes on reads.
7259 * PSU_DDR_PHY_ACBDLR8_RESERVED_7_6 0x0
7261 * Delay select for the BDL on Address A[8].
7262 * PSU_DDR_PHY_ACBDLR8_A08BD 0x0
7264 * AC Bit Delay Line Register 8
7265 * (OFFSET, MASK, VALUE) (0XFD080560, 0xFFFFFFFFU ,0x00000000U)
7267 PSU_Mask_Write(DDR_PHY_ACBDLR8_OFFSET, 0xFFFFFFFFU, 0x00000000U);
7268 /*##################################################################### */
7271 * Register : ACBDLR9 @ 0XFD080564
7273 * Reserved. Return zeroes on reads.
7274 * PSU_DDR_PHY_ACBDLR9_RESERVED_31_30 0x0
7276 * Delay select for the BDL on Address A[15].
7277 * PSU_DDR_PHY_ACBDLR9_A15BD 0x0
7279 * Reserved. Return zeroes on reads.
7280 * PSU_DDR_PHY_ACBDLR9_RESERVED_23_22 0x0
7282 * Delay select for the BDL on Address A[14].
7283 * PSU_DDR_PHY_ACBDLR9_A14BD 0x0
7285 * Reserved. Return zeroes on reads.
7286 * PSU_DDR_PHY_ACBDLR9_RESERVED_15_14 0x0
7288 * Delay select for the BDL on Address A[13].
7289 * PSU_DDR_PHY_ACBDLR9_A13BD 0x0
7291 * Reserved. Return zeroes on reads.
7292 * PSU_DDR_PHY_ACBDLR9_RESERVED_7_6 0x0
7294 * Delay select for the BDL on Address A[12].
7295 * PSU_DDR_PHY_ACBDLR9_A12BD 0x0
7297 * AC Bit Delay Line Register 9
7298 * (OFFSET, MASK, VALUE) (0XFD080564, 0xFFFFFFFFU ,0x00000000U)
7300 PSU_Mask_Write(DDR_PHY_ACBDLR9_OFFSET, 0xFFFFFFFFU, 0x00000000U);
7301 /*##################################################################### */
7304 * Register : ZQCR @ 0XFD080680
7306 * Reserved. Return zeroes on reads.
7307 * PSU_DDR_PHY_ZQCR_RESERVED_31_26 0x0
7310 * PSU_DDR_PHY_ZQCR_ZQREFISELRANGE 0x0
7312 * Programmable Wait for Frequency B
7313 * PSU_DDR_PHY_ZQCR_PGWAIT_FRQB 0x11
7315 * Programmable Wait for Frequency A
7316 * PSU_DDR_PHY_ZQCR_PGWAIT_FRQA 0x15
7318 * ZQ VREF Pad Enable
7319 * PSU_DDR_PHY_ZQCR_ZQREFPEN 0x0
7321 * ZQ Internal VREF Enable
7322 * PSU_DDR_PHY_ZQCR_ZQREFIEN 0x1
7324 * Choice of termination mode
7325 * PSU_DDR_PHY_ZQCR_ODT_MODE 0x1
7327 * Force ZCAL VT update
7328 * PSU_DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE 0x0
7331 * PSU_DDR_PHY_ZQCR_IODLMT 0x2
7333 * Averaging algorithm enable, if set, enables averaging algorithm
7334 * PSU_DDR_PHY_ZQCR_AVGEN 0x1
7336 * Maximum number of averaging rounds to be used by averaging algorithm
7337 * PSU_DDR_PHY_ZQCR_AVGMAX 0x2
7339 * ZQ Calibration Type
7340 * PSU_DDR_PHY_ZQCR_ZCALT 0x0
7343 * PSU_DDR_PHY_ZQCR_ZQPD 0x0
7345 * ZQ Impedance Control Register
7346 * (OFFSET, MASK, VALUE) (0XFD080680, 0xFFFFFFFFU ,0x008AAA58U)
7348 PSU_Mask_Write(DDR_PHY_ZQCR_OFFSET, 0xFFFFFFFFU, 0x008AAA58U);
7349 /*##################################################################### */
7352 * Register : ZQ0PR0 @ 0XFD080684
7354 * Pull-down drive strength ZCTRL over-ride enable
7355 * PSU_DDR_PHY_ZQ0PR0_PD_DRV_ZDEN 0x0
7357 * Pull-up drive strength ZCTRL over-ride enable
7358 * PSU_DDR_PHY_ZQ0PR0_PU_DRV_ZDEN 0x0
7360 * Pull-down termination ZCTRL over-ride enable
7361 * PSU_DDR_PHY_ZQ0PR0_PD_ODT_ZDEN 0x0
7363 * Pull-up termination ZCTRL over-ride enable
7364 * PSU_DDR_PHY_ZQ0PR0_PU_ODT_ZDEN 0x0
7366 * Calibration segment bypass
7367 * PSU_DDR_PHY_ZQ0PR0_ZSEGBYP 0x0
7369 * VREF latch mode controls the mode in which the ZLE pin of the PVREF cell
7370 * is driven by the PUB
7371 * PSU_DDR_PHY_ZQ0PR0_ZLE_MODE 0x0
7373 * Termination adjustment
7374 * PSU_DDR_PHY_ZQ0PR0_ODT_ADJUST 0x0
7376 * Pulldown drive strength adjustment
7377 * PSU_DDR_PHY_ZQ0PR0_PD_DRV_ADJUST 0x0
7379 * Pullup drive strength adjustment
7380 * PSU_DDR_PHY_ZQ0PR0_PU_DRV_ADJUST 0x0
7382 * DRAM Impedance Divide Ratio
7383 * PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT 0x7
7385 * HOST Impedance Divide Ratio
7386 * PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT 0x9
7388 * Impedance Divide Ratio (pulldown drive calibration during asymmetric dri
7389 * ve strength calibration)
7390 * PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD 0xd
7392 * Impedance Divide Ratio (pullup drive calibration during asymmetric drive
7393 * strength calibration)
7394 * PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU 0xd
7396 * ZQ n Impedance Control Program Register 0
7397 * (OFFSET, MASK, VALUE) (0XFD080684, 0xFFFFFFFFU ,0x000079DDU)
7399 PSU_Mask_Write(DDR_PHY_ZQ0PR0_OFFSET, 0xFFFFFFFFU, 0x000079DDU);
7400 /*##################################################################### */
7403 * Register : ZQ0OR0 @ 0XFD080694
7405 * Reserved. Return zeros on reads.
7406 * PSU_DDR_PHY_ZQ0OR0_RESERVED_31_26 0x0
7408 * Override value for the pull-up output impedance
7409 * PSU_DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD 0x1e1
7411 * Reserved. Return zeros on reads.
7412 * PSU_DDR_PHY_ZQ0OR0_RESERVED_15_10 0x0
7414 * Override value for the pull-down output impedance
7415 * PSU_DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD 0x210
7417 * ZQ n Impedance Control Override Data Register 0
7418 * (OFFSET, MASK, VALUE) (0XFD080694, 0xFFFFFFFFU ,0x01E10210U)
7420 PSU_Mask_Write(DDR_PHY_ZQ0OR0_OFFSET, 0xFFFFFFFFU, 0x01E10210U);
7421 /*##################################################################### */
7424 * Register : ZQ0OR1 @ 0XFD080698
7426 * Reserved. Return zeros on reads.
7427 * PSU_DDR_PHY_ZQ0OR1_RESERVED_31_26 0x0
7429 * Override value for the pull-up termination
7430 * PSU_DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD 0x1e1
7432 * Reserved. Return zeros on reads.
7433 * PSU_DDR_PHY_ZQ0OR1_RESERVED_15_10 0x0
7435 * Override value for the pull-down termination
7436 * PSU_DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD 0x0
7438 * ZQ n Impedance Control Override Data Register 1
7439 * (OFFSET, MASK, VALUE) (0XFD080698, 0xFFFFFFFFU ,0x01E10000U)
7441 PSU_Mask_Write(DDR_PHY_ZQ0OR1_OFFSET, 0xFFFFFFFFU, 0x01E10000U);
7442 /*##################################################################### */
7445 * Register : ZQ1PR0 @ 0XFD0806A4
7447 * Pull-down drive strength ZCTRL over-ride enable
7448 * PSU_DDR_PHY_ZQ1PR0_PD_DRV_ZDEN 0x0
7450 * Pull-up drive strength ZCTRL over-ride enable
7451 * PSU_DDR_PHY_ZQ1PR0_PU_DRV_ZDEN 0x0
7453 * Pull-down termination ZCTRL over-ride enable
7454 * PSU_DDR_PHY_ZQ1PR0_PD_ODT_ZDEN 0x0
7456 * Pull-up termination ZCTRL over-ride enable
7457 * PSU_DDR_PHY_ZQ1PR0_PU_ODT_ZDEN 0x0
7459 * Calibration segment bypass
7460 * PSU_DDR_PHY_ZQ1PR0_ZSEGBYP 0x0
7462 * VREF latch mode controls the mode in which the ZLE pin of the PVREF cell
7463 * is driven by the PUB
7464 * PSU_DDR_PHY_ZQ1PR0_ZLE_MODE 0x0
7466 * Termination adjustment
7467 * PSU_DDR_PHY_ZQ1PR0_ODT_ADJUST 0x0
7469 * Pulldown drive strength adjustment
7470 * PSU_DDR_PHY_ZQ1PR0_PD_DRV_ADJUST 0x1
7472 * Pullup drive strength adjustment
7473 * PSU_DDR_PHY_ZQ1PR0_PU_DRV_ADJUST 0x0
7475 * DRAM Impedance Divide Ratio
7476 * PSU_DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT 0x7
7478 * HOST Impedance Divide Ratio
7479 * PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT 0xb
7481 * Impedance Divide Ratio (pulldown drive calibration during asymmetric dri
7482 * ve strength calibration)
7483 * PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD 0xd
7485 * Impedance Divide Ratio (pullup drive calibration during asymmetric drive
7486 * strength calibration)
7487 * PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU 0xb
7489 * ZQ n Impedance Control Program Register 0
7490 * (OFFSET, MASK, VALUE) (0XFD0806A4, 0xFFFFFFFFU ,0x00087BDBU)
7492 PSU_Mask_Write(DDR_PHY_ZQ1PR0_OFFSET, 0xFFFFFFFFU, 0x00087BDBU);
7493 /*##################################################################### */
7496 * Register : DX0GCR0 @ 0XFD080700
7498 * Calibration Bypass
7499 * PSU_DDR_PHY_DX0GCR0_CALBYP 0x0
7501 * Master Delay Line Enable
7502 * PSU_DDR_PHY_DX0GCR0_MDLEN 0x1
7504 * Configurable ODT(TE) Phase Shift
7505 * PSU_DDR_PHY_DX0GCR0_CODTSHFT 0x0
7507 * DQS Duty Cycle Correction
7508 * PSU_DDR_PHY_DX0GCR0_DQSDCC 0x0
7510 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
7511 * input for the respective bypte lane of the PHY
7512 * PSU_DDR_PHY_DX0GCR0_RDDLY 0x8
7514 * Reserved. Return zeroes on reads.
7515 * PSU_DDR_PHY_DX0GCR0_RESERVED_19_14 0x0
7517 * DQSNSE Power Down Receiver
7518 * PSU_DDR_PHY_DX0GCR0_DQSNSEPDR 0x0
7520 * DQSSE Power Down Receiver
7521 * PSU_DDR_PHY_DX0GCR0_DQSSEPDR 0x0
7523 * RTT On Additive Latency
7524 * PSU_DDR_PHY_DX0GCR0_RTTOAL 0x0
7527 * PSU_DDR_PHY_DX0GCR0_RTTOH 0x3
7529 * Configurable PDR Phase Shift
7530 * PSU_DDR_PHY_DX0GCR0_CPDRSHFT 0x0
7533 * PSU_DDR_PHY_DX0GCR0_DQSRPD 0x0
7535 * DQSG Power Down Receiver
7536 * PSU_DDR_PHY_DX0GCR0_DQSGPDR 0x0
7538 * Reserved. Return zeroes on reads.
7539 * PSU_DDR_PHY_DX0GCR0_RESERVED_4 0x0
7541 * DQSG On-Die Termination
7542 * PSU_DDR_PHY_DX0GCR0_DQSGODT 0x0
7544 * DQSG Output Enable
7545 * PSU_DDR_PHY_DX0GCR0_DQSGOE 0x1
7547 * Reserved. Return zeroes on reads.
7548 * PSU_DDR_PHY_DX0GCR0_RESERVED_1_0 0x0
7550 * DATX8 n General Configuration Register 0
7551 * (OFFSET, MASK, VALUE) (0XFD080700, 0xFFFFFFFFU ,0x40800604U)
7553 PSU_Mask_Write(DDR_PHY_DX0GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U);
7554 /*##################################################################### */
7557 * Register : DX0GCR4 @ 0XFD080710
7559 * Byte lane VREF IOM (Used only by D4MU IOs)
7560 * PSU_DDR_PHY_DX0GCR4_RESERVED_31_29 0x0
7562 * Byte Lane VREF Pad Enable
7563 * PSU_DDR_PHY_DX0GCR4_DXREFPEN 0x0
7565 * Byte Lane Internal VREF Enable
7566 * PSU_DDR_PHY_DX0GCR4_DXREFEEN 0x3
7568 * Byte Lane Single-End VREF Enable
7569 * PSU_DDR_PHY_DX0GCR4_DXREFSEN 0x1
7571 * Reserved. Returns zeros on reads.
7572 * PSU_DDR_PHY_DX0GCR4_RESERVED_24 0x0
7574 * External VREF generator REFSEL range select
7575 * PSU_DDR_PHY_DX0GCR4_DXREFESELRANGE 0x0
7577 * Byte Lane External VREF Select
7578 * PSU_DDR_PHY_DX0GCR4_DXREFESEL 0x0
7580 * Single ended VREF generator REFSEL range select
7581 * PSU_DDR_PHY_DX0GCR4_DXREFSSELRANGE 0x1
7583 * Byte Lane Single-End VREF Select
7584 * PSU_DDR_PHY_DX0GCR4_DXREFSSEL 0x30
7586 * Reserved. Returns zeros on reads.
7587 * PSU_DDR_PHY_DX0GCR4_RESERVED_7_6 0x0
7589 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
7590 * PSU_DDR_PHY_DX0GCR4_DXREFIEN 0xf
7592 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
7593 * PSU_DDR_PHY_DX0GCR4_DXREFIMON 0x0
7595 * DATX8 n General Configuration Register 4
7596 * (OFFSET, MASK, VALUE) (0XFD080710, 0xFFFFFFFFU ,0x0E00B03CU)
7598 PSU_Mask_Write(DDR_PHY_DX0GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU);
7599 /*##################################################################### */
7602 * Register : DX0GCR5 @ 0XFD080714
7604 * Reserved. Returns zeros on reads.
7605 * PSU_DDR_PHY_DX0GCR5_RESERVED_31 0x0
7607 * Byte Lane internal VREF Select for Rank 3
7608 * PSU_DDR_PHY_DX0GCR5_DXREFISELR3 0x9
7610 * Reserved. Returns zeros on reads.
7611 * PSU_DDR_PHY_DX0GCR5_RESERVED_23 0x0
7613 * Byte Lane internal VREF Select for Rank 2
7614 * PSU_DDR_PHY_DX0GCR5_DXREFISELR2 0x9
7616 * Reserved. Returns zeros on reads.
7617 * PSU_DDR_PHY_DX0GCR5_RESERVED_15 0x0
7619 * Byte Lane internal VREF Select for Rank 1
7620 * PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x55
7622 * Reserved. Returns zeros on reads.
7623 * PSU_DDR_PHY_DX0GCR5_RESERVED_7 0x0
7625 * Byte Lane internal VREF Select for Rank 0
7626 * PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x55
7628 * DATX8 n General Configuration Register 5
7629 * (OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09095555U)
7631 PSU_Mask_Write(DDR_PHY_DX0GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U);
7632 /*##################################################################### */
7635 * Register : DX0GCR6 @ 0XFD080718
7637 * Reserved. Returns zeros on reads.
7638 * PSU_DDR_PHY_DX0GCR6_RESERVED_31_30 0x0
7640 * DRAM DQ VREF Select for Rank3
7641 * PSU_DDR_PHY_DX0GCR6_DXDQVREFR3 0x9
7643 * Reserved. Returns zeros on reads.
7644 * PSU_DDR_PHY_DX0GCR6_RESERVED_23_22 0x0
7646 * DRAM DQ VREF Select for Rank2
7647 * PSU_DDR_PHY_DX0GCR6_DXDQVREFR2 0x9
7649 * Reserved. Returns zeros on reads.
7650 * PSU_DDR_PHY_DX0GCR6_RESERVED_15_14 0x0
7652 * DRAM DQ VREF Select for Rank1
7653 * PSU_DDR_PHY_DX0GCR6_DXDQVREFR1 0x2b
7655 * Reserved. Returns zeros on reads.
7656 * PSU_DDR_PHY_DX0GCR6_RESERVED_7_6 0x0
7658 * DRAM DQ VREF Select for Rank0
7659 * PSU_DDR_PHY_DX0GCR6_DXDQVREFR0 0x2b
7661 * DATX8 n General Configuration Register 6
7662 * (OFFSET, MASK, VALUE) (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU)
7664 PSU_Mask_Write(DDR_PHY_DX0GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU);
7665 /*##################################################################### */
7668 * Register : DX1GCR0 @ 0XFD080800
7670 * Calibration Bypass
7671 * PSU_DDR_PHY_DX1GCR0_CALBYP 0x0
7673 * Master Delay Line Enable
7674 * PSU_DDR_PHY_DX1GCR0_MDLEN 0x1
7676 * Configurable ODT(TE) Phase Shift
7677 * PSU_DDR_PHY_DX1GCR0_CODTSHFT 0x0
7679 * DQS Duty Cycle Correction
7680 * PSU_DDR_PHY_DX1GCR0_DQSDCC 0x0
7682 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
7683 * input for the respective bypte lane of the PHY
7684 * PSU_DDR_PHY_DX1GCR0_RDDLY 0x8
7686 * Reserved. Return zeroes on reads.
7687 * PSU_DDR_PHY_DX1GCR0_RESERVED_19_14 0x0
7689 * DQSNSE Power Down Receiver
7690 * PSU_DDR_PHY_DX1GCR0_DQSNSEPDR 0x0
7692 * DQSSE Power Down Receiver
7693 * PSU_DDR_PHY_DX1GCR0_DQSSEPDR 0x0
7695 * RTT On Additive Latency
7696 * PSU_DDR_PHY_DX1GCR0_RTTOAL 0x0
7699 * PSU_DDR_PHY_DX1GCR0_RTTOH 0x3
7701 * Configurable PDR Phase Shift
7702 * PSU_DDR_PHY_DX1GCR0_CPDRSHFT 0x0
7705 * PSU_DDR_PHY_DX1GCR0_DQSRPD 0x0
7707 * DQSG Power Down Receiver
7708 * PSU_DDR_PHY_DX1GCR0_DQSGPDR 0x0
7710 * Reserved. Return zeroes on reads.
7711 * PSU_DDR_PHY_DX1GCR0_RESERVED_4 0x0
7713 * DQSG On-Die Termination
7714 * PSU_DDR_PHY_DX1GCR0_DQSGODT 0x0
7716 * DQSG Output Enable
7717 * PSU_DDR_PHY_DX1GCR0_DQSGOE 0x1
7719 * Reserved. Return zeroes on reads.
7720 * PSU_DDR_PHY_DX1GCR0_RESERVED_1_0 0x0
7722 * DATX8 n General Configuration Register 0
7723 * (OFFSET, MASK, VALUE) (0XFD080800, 0xFFFFFFFFU ,0x40800604U)
7725 PSU_Mask_Write(DDR_PHY_DX1GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U);
7726 /*##################################################################### */
7729 * Register : DX1GCR4 @ 0XFD080810
7731 * Byte lane VREF IOM (Used only by D4MU IOs)
7732 * PSU_DDR_PHY_DX1GCR4_RESERVED_31_29 0x0
7734 * Byte Lane VREF Pad Enable
7735 * PSU_DDR_PHY_DX1GCR4_DXREFPEN 0x0
7737 * Byte Lane Internal VREF Enable
7738 * PSU_DDR_PHY_DX1GCR4_DXREFEEN 0x3
7740 * Byte Lane Single-End VREF Enable
7741 * PSU_DDR_PHY_DX1GCR4_DXREFSEN 0x1
7743 * Reserved. Returns zeros on reads.
7744 * PSU_DDR_PHY_DX1GCR4_RESERVED_24 0x0
7746 * External VREF generator REFSEL range select
7747 * PSU_DDR_PHY_DX1GCR4_DXREFESELRANGE 0x0
7749 * Byte Lane External VREF Select
7750 * PSU_DDR_PHY_DX1GCR4_DXREFESEL 0x0
7752 * Single ended VREF generator REFSEL range select
7753 * PSU_DDR_PHY_DX1GCR4_DXREFSSELRANGE 0x1
7755 * Byte Lane Single-End VREF Select
7756 * PSU_DDR_PHY_DX1GCR4_DXREFSSEL 0x30
7758 * Reserved. Returns zeros on reads.
7759 * PSU_DDR_PHY_DX1GCR4_RESERVED_7_6 0x0
7761 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
7762 * PSU_DDR_PHY_DX1GCR4_DXREFIEN 0xf
7764 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
7765 * PSU_DDR_PHY_DX1GCR4_DXREFIMON 0x0
7767 * DATX8 n General Configuration Register 4
7768 * (OFFSET, MASK, VALUE) (0XFD080810, 0xFFFFFFFFU ,0x0E00B03CU)
7770 PSU_Mask_Write(DDR_PHY_DX1GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU);
7771 /*##################################################################### */
7774 * Register : DX1GCR5 @ 0XFD080814
7776 * Reserved. Returns zeros on reads.
7777 * PSU_DDR_PHY_DX1GCR5_RESERVED_31 0x0
7779 * Byte Lane internal VREF Select for Rank 3
7780 * PSU_DDR_PHY_DX1GCR5_DXREFISELR3 0x9
7782 * Reserved. Returns zeros on reads.
7783 * PSU_DDR_PHY_DX1GCR5_RESERVED_23 0x0
7785 * Byte Lane internal VREF Select for Rank 2
7786 * PSU_DDR_PHY_DX1GCR5_DXREFISELR2 0x9
7788 * Reserved. Returns zeros on reads.
7789 * PSU_DDR_PHY_DX1GCR5_RESERVED_15 0x0
7791 * Byte Lane internal VREF Select for Rank 1
7792 * PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x55
7794 * Reserved. Returns zeros on reads.
7795 * PSU_DDR_PHY_DX1GCR5_RESERVED_7 0x0
7797 * Byte Lane internal VREF Select for Rank 0
7798 * PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x55
7800 * DATX8 n General Configuration Register 5
7801 * (OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09095555U)
7803 PSU_Mask_Write(DDR_PHY_DX1GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U);
7804 /*##################################################################### */
7807 * Register : DX1GCR6 @ 0XFD080818
7809 * Reserved. Returns zeros on reads.
7810 * PSU_DDR_PHY_DX1GCR6_RESERVED_31_30 0x0
7812 * DRAM DQ VREF Select for Rank3
7813 * PSU_DDR_PHY_DX1GCR6_DXDQVREFR3 0x9
7815 * Reserved. Returns zeros on reads.
7816 * PSU_DDR_PHY_DX1GCR6_RESERVED_23_22 0x0
7818 * DRAM DQ VREF Select for Rank2
7819 * PSU_DDR_PHY_DX1GCR6_DXDQVREFR2 0x9
7821 * Reserved. Returns zeros on reads.
7822 * PSU_DDR_PHY_DX1GCR6_RESERVED_15_14 0x0
7824 * DRAM DQ VREF Select for Rank1
7825 * PSU_DDR_PHY_DX1GCR6_DXDQVREFR1 0x2b
7827 * Reserved. Returns zeros on reads.
7828 * PSU_DDR_PHY_DX1GCR6_RESERVED_7_6 0x0
7830 * DRAM DQ VREF Select for Rank0
7831 * PSU_DDR_PHY_DX1GCR6_DXDQVREFR0 0x2b
7833 * DATX8 n General Configuration Register 6
7834 * (OFFSET, MASK, VALUE) (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU)
7836 PSU_Mask_Write(DDR_PHY_DX1GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU);
7837 /*##################################################################### */
7840 * Register : DX2GCR0 @ 0XFD080900
7842 * Calibration Bypass
7843 * PSU_DDR_PHY_DX2GCR0_CALBYP 0x0
7845 * Master Delay Line Enable
7846 * PSU_DDR_PHY_DX2GCR0_MDLEN 0x1
7848 * Configurable ODT(TE) Phase Shift
7849 * PSU_DDR_PHY_DX2GCR0_CODTSHFT 0x0
7851 * DQS Duty Cycle Correction
7852 * PSU_DDR_PHY_DX2GCR0_DQSDCC 0x0
7854 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
7855 * input for the respective bypte lane of the PHY
7856 * PSU_DDR_PHY_DX2GCR0_RDDLY 0x8
7858 * Reserved. Return zeroes on reads.
7859 * PSU_DDR_PHY_DX2GCR0_RESERVED_19_14 0x0
7861 * DQSNSE Power Down Receiver
7862 * PSU_DDR_PHY_DX2GCR0_DQSNSEPDR 0x0
7864 * DQSSE Power Down Receiver
7865 * PSU_DDR_PHY_DX2GCR0_DQSSEPDR 0x0
7867 * RTT On Additive Latency
7868 * PSU_DDR_PHY_DX2GCR0_RTTOAL 0x0
7871 * PSU_DDR_PHY_DX2GCR0_RTTOH 0x3
7873 * Configurable PDR Phase Shift
7874 * PSU_DDR_PHY_DX2GCR0_CPDRSHFT 0x0
7877 * PSU_DDR_PHY_DX2GCR0_DQSRPD 0x0
7879 * DQSG Power Down Receiver
7880 * PSU_DDR_PHY_DX2GCR0_DQSGPDR 0x0
7882 * Reserved. Return zeroes on reads.
7883 * PSU_DDR_PHY_DX2GCR0_RESERVED_4 0x0
7885 * DQSG On-Die Termination
7886 * PSU_DDR_PHY_DX2GCR0_DQSGODT 0x0
7888 * DQSG Output Enable
7889 * PSU_DDR_PHY_DX2GCR0_DQSGOE 0x1
7891 * Reserved. Return zeroes on reads.
7892 * PSU_DDR_PHY_DX2GCR0_RESERVED_1_0 0x0
7894 * DATX8 n General Configuration Register 0
7895 * (OFFSET, MASK, VALUE) (0XFD080900, 0xFFFFFFFFU ,0x40800604U)
7897 PSU_Mask_Write(DDR_PHY_DX2GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U);
7898 /*##################################################################### */
7901 * Register : DX2GCR1 @ 0XFD080904
7903 * Enables the PDR mode for DQ[7:0]
7904 * PSU_DDR_PHY_DX2GCR1_DXPDRMODE 0x0
7906 * Reserved. Returns zeroes on reads.
7907 * PSU_DDR_PHY_DX2GCR1_RESERVED_15 0x0
7909 * Select the delayed or non-delayed read data strobe #
7910 * PSU_DDR_PHY_DX2GCR1_QSNSEL 0x1
7912 * Select the delayed or non-delayed read data strobe
7913 * PSU_DDR_PHY_DX2GCR1_QSSEL 0x1
7915 * Enables Read Data Strobe in a byte lane
7916 * PSU_DDR_PHY_DX2GCR1_OEEN 0x1
7918 * Enables PDR in a byte lane
7919 * PSU_DDR_PHY_DX2GCR1_PDREN 0x1
7921 * Enables ODT/TE in a byte lane
7922 * PSU_DDR_PHY_DX2GCR1_TEEN 0x1
7924 * Enables Write Data strobe in a byte lane
7925 * PSU_DDR_PHY_DX2GCR1_DSEN 0x1
7927 * Enables DM pin in a byte lane
7928 * PSU_DDR_PHY_DX2GCR1_DMEN 0x1
7930 * Enables DQ corresponding to each bit in a byte
7931 * PSU_DDR_PHY_DX2GCR1_DQEN 0xff
7933 * DATX8 n General Configuration Register 1
7934 * (OFFSET, MASK, VALUE) (0XFD080904, 0xFFFFFFFFU ,0x00007FFFU)
7936 PSU_Mask_Write(DDR_PHY_DX2GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU);
7937 /*##################################################################### */
7940 * Register : DX2GCR4 @ 0XFD080910
7942 * Byte lane VREF IOM (Used only by D4MU IOs)
7943 * PSU_DDR_PHY_DX2GCR4_RESERVED_31_29 0x0
7945 * Byte Lane VREF Pad Enable
7946 * PSU_DDR_PHY_DX2GCR4_DXREFPEN 0x0
7948 * Byte Lane Internal VREF Enable
7949 * PSU_DDR_PHY_DX2GCR4_DXREFEEN 0x3
7951 * Byte Lane Single-End VREF Enable
7952 * PSU_DDR_PHY_DX2GCR4_DXREFSEN 0x1
7954 * Reserved. Returns zeros on reads.
7955 * PSU_DDR_PHY_DX2GCR4_RESERVED_24 0x0
7957 * External VREF generator REFSEL range select
7958 * PSU_DDR_PHY_DX2GCR4_DXREFESELRANGE 0x0
7960 * Byte Lane External VREF Select
7961 * PSU_DDR_PHY_DX2GCR4_DXREFESEL 0x0
7963 * Single ended VREF generator REFSEL range select
7964 * PSU_DDR_PHY_DX2GCR4_DXREFSSELRANGE 0x1
7966 * Byte Lane Single-End VREF Select
7967 * PSU_DDR_PHY_DX2GCR4_DXREFSSEL 0x30
7969 * Reserved. Returns zeros on reads.
7970 * PSU_DDR_PHY_DX2GCR4_RESERVED_7_6 0x0
7972 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
7973 * PSU_DDR_PHY_DX2GCR4_DXREFIEN 0xf
7975 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
7976 * PSU_DDR_PHY_DX2GCR4_DXREFIMON 0x0
7978 * DATX8 n General Configuration Register 4
7979 * (OFFSET, MASK, VALUE) (0XFD080910, 0xFFFFFFFFU ,0x0E00B03CU)
7981 PSU_Mask_Write(DDR_PHY_DX2GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU);
7982 /*##################################################################### */
7985 * Register : DX2GCR5 @ 0XFD080914
7987 * Reserved. Returns zeros on reads.
7988 * PSU_DDR_PHY_DX2GCR5_RESERVED_31 0x0
7990 * Byte Lane internal VREF Select for Rank 3
7991 * PSU_DDR_PHY_DX2GCR5_DXREFISELR3 0x9
7993 * Reserved. Returns zeros on reads.
7994 * PSU_DDR_PHY_DX2GCR5_RESERVED_23 0x0
7996 * Byte Lane internal VREF Select for Rank 2
7997 * PSU_DDR_PHY_DX2GCR5_DXREFISELR2 0x9
7999 * Reserved. Returns zeros on reads.
8000 * PSU_DDR_PHY_DX2GCR5_RESERVED_15 0x0
8002 * Byte Lane internal VREF Select for Rank 1
8003 * PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x55
8005 * Reserved. Returns zeros on reads.
8006 * PSU_DDR_PHY_DX2GCR5_RESERVED_7 0x0
8008 * Byte Lane internal VREF Select for Rank 0
8009 * PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x55
8011 * DATX8 n General Configuration Register 5
8012 * (OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09095555U)
8014 PSU_Mask_Write(DDR_PHY_DX2GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U);
8015 /*##################################################################### */
8018 * Register : DX2GCR6 @ 0XFD080918
8020 * Reserved. Returns zeros on reads.
8021 * PSU_DDR_PHY_DX2GCR6_RESERVED_31_30 0x0
8023 * DRAM DQ VREF Select for Rank3
8024 * PSU_DDR_PHY_DX2GCR6_DXDQVREFR3 0x9
8026 * Reserved. Returns zeros on reads.
8027 * PSU_DDR_PHY_DX2GCR6_RESERVED_23_22 0x0
8029 * DRAM DQ VREF Select for Rank2
8030 * PSU_DDR_PHY_DX2GCR6_DXDQVREFR2 0x9
8032 * Reserved. Returns zeros on reads.
8033 * PSU_DDR_PHY_DX2GCR6_RESERVED_15_14 0x0
8035 * DRAM DQ VREF Select for Rank1
8036 * PSU_DDR_PHY_DX2GCR6_DXDQVREFR1 0x2b
8038 * Reserved. Returns zeros on reads.
8039 * PSU_DDR_PHY_DX2GCR6_RESERVED_7_6 0x0
8041 * DRAM DQ VREF Select for Rank0
8042 * PSU_DDR_PHY_DX2GCR6_DXDQVREFR0 0x2b
8044 * DATX8 n General Configuration Register 6
8045 * (OFFSET, MASK, VALUE) (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU)
8047 PSU_Mask_Write(DDR_PHY_DX2GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU);
8048 /*##################################################################### */
8051 * Register : DX3GCR0 @ 0XFD080A00
8053 * Calibration Bypass
8054 * PSU_DDR_PHY_DX3GCR0_CALBYP 0x0
8056 * Master Delay Line Enable
8057 * PSU_DDR_PHY_DX3GCR0_MDLEN 0x1
8059 * Configurable ODT(TE) Phase Shift
8060 * PSU_DDR_PHY_DX3GCR0_CODTSHFT 0x0
8062 * DQS Duty Cycle Correction
8063 * PSU_DDR_PHY_DX3GCR0_DQSDCC 0x0
8065 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
8066 * input for the respective bypte lane of the PHY
8067 * PSU_DDR_PHY_DX3GCR0_RDDLY 0x8
8069 * Reserved. Return zeroes on reads.
8070 * PSU_DDR_PHY_DX3GCR0_RESERVED_19_14 0x0
8072 * DQSNSE Power Down Receiver
8073 * PSU_DDR_PHY_DX3GCR0_DQSNSEPDR 0x0
8075 * DQSSE Power Down Receiver
8076 * PSU_DDR_PHY_DX3GCR0_DQSSEPDR 0x0
8078 * RTT On Additive Latency
8079 * PSU_DDR_PHY_DX3GCR0_RTTOAL 0x0
8082 * PSU_DDR_PHY_DX3GCR0_RTTOH 0x3
8084 * Configurable PDR Phase Shift
8085 * PSU_DDR_PHY_DX3GCR0_CPDRSHFT 0x0
8088 * PSU_DDR_PHY_DX3GCR0_DQSRPD 0x0
8090 * DQSG Power Down Receiver
8091 * PSU_DDR_PHY_DX3GCR0_DQSGPDR 0x0
8093 * Reserved. Return zeroes on reads.
8094 * PSU_DDR_PHY_DX3GCR0_RESERVED_4 0x0
8096 * DQSG On-Die Termination
8097 * PSU_DDR_PHY_DX3GCR0_DQSGODT 0x0
8099 * DQSG Output Enable
8100 * PSU_DDR_PHY_DX3GCR0_DQSGOE 0x1
8102 * Reserved. Return zeroes on reads.
8103 * PSU_DDR_PHY_DX3GCR0_RESERVED_1_0 0x0
8105 * DATX8 n General Configuration Register 0
8106 * (OFFSET, MASK, VALUE) (0XFD080A00, 0xFFFFFFFFU ,0x40800604U)
8108 PSU_Mask_Write(DDR_PHY_DX3GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U);
8109 /*##################################################################### */
8112 * Register : DX3GCR1 @ 0XFD080A04
8114 * Enables the PDR mode for DQ[7:0]
8115 * PSU_DDR_PHY_DX3GCR1_DXPDRMODE 0x0
8117 * Reserved. Returns zeroes on reads.
8118 * PSU_DDR_PHY_DX3GCR1_RESERVED_15 0x0
8120 * Select the delayed or non-delayed read data strobe #
8121 * PSU_DDR_PHY_DX3GCR1_QSNSEL 0x1
8123 * Select the delayed or non-delayed read data strobe
8124 * PSU_DDR_PHY_DX3GCR1_QSSEL 0x1
8126 * Enables Read Data Strobe in a byte lane
8127 * PSU_DDR_PHY_DX3GCR1_OEEN 0x1
8129 * Enables PDR in a byte lane
8130 * PSU_DDR_PHY_DX3GCR1_PDREN 0x1
8132 * Enables ODT/TE in a byte lane
8133 * PSU_DDR_PHY_DX3GCR1_TEEN 0x1
8135 * Enables Write Data strobe in a byte lane
8136 * PSU_DDR_PHY_DX3GCR1_DSEN 0x1
8138 * Enables DM pin in a byte lane
8139 * PSU_DDR_PHY_DX3GCR1_DMEN 0x1
8141 * Enables DQ corresponding to each bit in a byte
8142 * PSU_DDR_PHY_DX3GCR1_DQEN 0xff
8144 * DATX8 n General Configuration Register 1
8145 * (OFFSET, MASK, VALUE) (0XFD080A04, 0xFFFFFFFFU ,0x00007FFFU)
8147 PSU_Mask_Write(DDR_PHY_DX3GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU);
8148 /*##################################################################### */
8151 * Register : DX3GCR4 @ 0XFD080A10
8153 * Byte lane VREF IOM (Used only by D4MU IOs)
8154 * PSU_DDR_PHY_DX3GCR4_RESERVED_31_29 0x0
8156 * Byte Lane VREF Pad Enable
8157 * PSU_DDR_PHY_DX3GCR4_DXREFPEN 0x0
8159 * Byte Lane Internal VREF Enable
8160 * PSU_DDR_PHY_DX3GCR4_DXREFEEN 0x3
8162 * Byte Lane Single-End VREF Enable
8163 * PSU_DDR_PHY_DX3GCR4_DXREFSEN 0x1
8165 * Reserved. Returns zeros on reads.
8166 * PSU_DDR_PHY_DX3GCR4_RESERVED_24 0x0
8168 * External VREF generator REFSEL range select
8169 * PSU_DDR_PHY_DX3GCR4_DXREFESELRANGE 0x0
8171 * Byte Lane External VREF Select
8172 * PSU_DDR_PHY_DX3GCR4_DXREFESEL 0x0
8174 * Single ended VREF generator REFSEL range select
8175 * PSU_DDR_PHY_DX3GCR4_DXREFSSELRANGE 0x1
8177 * Byte Lane Single-End VREF Select
8178 * PSU_DDR_PHY_DX3GCR4_DXREFSSEL 0x30
8180 * Reserved. Returns zeros on reads.
8181 * PSU_DDR_PHY_DX3GCR4_RESERVED_7_6 0x0
8183 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
8184 * PSU_DDR_PHY_DX3GCR4_DXREFIEN 0xf
8186 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
8187 * PSU_DDR_PHY_DX3GCR4_DXREFIMON 0x0
8189 * DATX8 n General Configuration Register 4
8190 * (OFFSET, MASK, VALUE) (0XFD080A10, 0xFFFFFFFFU ,0x0E00B03CU)
8192 PSU_Mask_Write(DDR_PHY_DX3GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU);
8193 /*##################################################################### */
8196 * Register : DX3GCR5 @ 0XFD080A14
8198 * Reserved. Returns zeros on reads.
8199 * PSU_DDR_PHY_DX3GCR5_RESERVED_31 0x0
8201 * Byte Lane internal VREF Select for Rank 3
8202 * PSU_DDR_PHY_DX3GCR5_DXREFISELR3 0x9
8204 * Reserved. Returns zeros on reads.
8205 * PSU_DDR_PHY_DX3GCR5_RESERVED_23 0x0
8207 * Byte Lane internal VREF Select for Rank 2
8208 * PSU_DDR_PHY_DX3GCR5_DXREFISELR2 0x9
8210 * Reserved. Returns zeros on reads.
8211 * PSU_DDR_PHY_DX3GCR5_RESERVED_15 0x0
8213 * Byte Lane internal VREF Select for Rank 1
8214 * PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x55
8216 * Reserved. Returns zeros on reads.
8217 * PSU_DDR_PHY_DX3GCR5_RESERVED_7 0x0
8219 * Byte Lane internal VREF Select for Rank 0
8220 * PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x55
8222 * DATX8 n General Configuration Register 5
8223 * (OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09095555U)
8225 PSU_Mask_Write(DDR_PHY_DX3GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U);
8226 /*##################################################################### */
8229 * Register : DX3GCR6 @ 0XFD080A18
8231 * Reserved. Returns zeros on reads.
8232 * PSU_DDR_PHY_DX3GCR6_RESERVED_31_30 0x0
8234 * DRAM DQ VREF Select for Rank3
8235 * PSU_DDR_PHY_DX3GCR6_DXDQVREFR3 0x9
8237 * Reserved. Returns zeros on reads.
8238 * PSU_DDR_PHY_DX3GCR6_RESERVED_23_22 0x0
8240 * DRAM DQ VREF Select for Rank2
8241 * PSU_DDR_PHY_DX3GCR6_DXDQVREFR2 0x9
8243 * Reserved. Returns zeros on reads.
8244 * PSU_DDR_PHY_DX3GCR6_RESERVED_15_14 0x0
8246 * DRAM DQ VREF Select for Rank1
8247 * PSU_DDR_PHY_DX3GCR6_DXDQVREFR1 0x2b
8249 * Reserved. Returns zeros on reads.
8250 * PSU_DDR_PHY_DX3GCR6_RESERVED_7_6 0x0
8252 * DRAM DQ VREF Select for Rank0
8253 * PSU_DDR_PHY_DX3GCR6_DXDQVREFR0 0x2b
8255 * DATX8 n General Configuration Register 6
8256 * (OFFSET, MASK, VALUE) (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU)
8258 PSU_Mask_Write(DDR_PHY_DX3GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU);
8259 /*##################################################################### */
8262 * Register : DX4GCR0 @ 0XFD080B00
8264 * Calibration Bypass
8265 * PSU_DDR_PHY_DX4GCR0_CALBYP 0x0
8267 * Master Delay Line Enable
8268 * PSU_DDR_PHY_DX4GCR0_MDLEN 0x1
8270 * Configurable ODT(TE) Phase Shift
8271 * PSU_DDR_PHY_DX4GCR0_CODTSHFT 0x0
8273 * DQS Duty Cycle Correction
8274 * PSU_DDR_PHY_DX4GCR0_DQSDCC 0x0
8276 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
8277 * input for the respective bypte lane of the PHY
8278 * PSU_DDR_PHY_DX4GCR0_RDDLY 0x8
8280 * Reserved. Return zeroes on reads.
8281 * PSU_DDR_PHY_DX4GCR0_RESERVED_19_14 0x0
8283 * DQSNSE Power Down Receiver
8284 * PSU_DDR_PHY_DX4GCR0_DQSNSEPDR 0x0
8286 * DQSSE Power Down Receiver
8287 * PSU_DDR_PHY_DX4GCR0_DQSSEPDR 0x0
8289 * RTT On Additive Latency
8290 * PSU_DDR_PHY_DX4GCR0_RTTOAL 0x0
8293 * PSU_DDR_PHY_DX4GCR0_RTTOH 0x3
8295 * Configurable PDR Phase Shift
8296 * PSU_DDR_PHY_DX4GCR0_CPDRSHFT 0x0
8299 * PSU_DDR_PHY_DX4GCR0_DQSRPD 0x0
8301 * DQSG Power Down Receiver
8302 * PSU_DDR_PHY_DX4GCR0_DQSGPDR 0x0
8304 * Reserved. Return zeroes on reads.
8305 * PSU_DDR_PHY_DX4GCR0_RESERVED_4 0x0
8307 * DQSG On-Die Termination
8308 * PSU_DDR_PHY_DX4GCR0_DQSGODT 0x0
8310 * DQSG Output Enable
8311 * PSU_DDR_PHY_DX4GCR0_DQSGOE 0x1
8313 * Reserved. Return zeroes on reads.
8314 * PSU_DDR_PHY_DX4GCR0_RESERVED_1_0 0x0
8316 * DATX8 n General Configuration Register 0
8317 * (OFFSET, MASK, VALUE) (0XFD080B00, 0xFFFFFFFFU ,0x40800604U)
8319 PSU_Mask_Write(DDR_PHY_DX4GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U);
8320 /*##################################################################### */
8323 * Register : DX4GCR1 @ 0XFD080B04
8325 * Enables the PDR mode for DQ[7:0]
8326 * PSU_DDR_PHY_DX4GCR1_DXPDRMODE 0x0
8328 * Reserved. Returns zeroes on reads.
8329 * PSU_DDR_PHY_DX4GCR1_RESERVED_15 0x0
8331 * Select the delayed or non-delayed read data strobe #
8332 * PSU_DDR_PHY_DX4GCR1_QSNSEL 0x1
8334 * Select the delayed or non-delayed read data strobe
8335 * PSU_DDR_PHY_DX4GCR1_QSSEL 0x1
8337 * Enables Read Data Strobe in a byte lane
8338 * PSU_DDR_PHY_DX4GCR1_OEEN 0x1
8340 * Enables PDR in a byte lane
8341 * PSU_DDR_PHY_DX4GCR1_PDREN 0x1
8343 * Enables ODT/TE in a byte lane
8344 * PSU_DDR_PHY_DX4GCR1_TEEN 0x1
8346 * Enables Write Data strobe in a byte lane
8347 * PSU_DDR_PHY_DX4GCR1_DSEN 0x1
8349 * Enables DM pin in a byte lane
8350 * PSU_DDR_PHY_DX4GCR1_DMEN 0x1
8352 * Enables DQ corresponding to each bit in a byte
8353 * PSU_DDR_PHY_DX4GCR1_DQEN 0xff
8355 * DATX8 n General Configuration Register 1
8356 * (OFFSET, MASK, VALUE) (0XFD080B04, 0xFFFFFFFFU ,0x00007FFFU)
8358 PSU_Mask_Write(DDR_PHY_DX4GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU);
8359 /*##################################################################### */
8362 * Register : DX4GCR4 @ 0XFD080B10
8364 * Byte lane VREF IOM (Used only by D4MU IOs)
8365 * PSU_DDR_PHY_DX4GCR4_RESERVED_31_29 0x0
8367 * Byte Lane VREF Pad Enable
8368 * PSU_DDR_PHY_DX4GCR4_DXREFPEN 0x0
8370 * Byte Lane Internal VREF Enable
8371 * PSU_DDR_PHY_DX4GCR4_DXREFEEN 0x3
8373 * Byte Lane Single-End VREF Enable
8374 * PSU_DDR_PHY_DX4GCR4_DXREFSEN 0x1
8376 * Reserved. Returns zeros on reads.
8377 * PSU_DDR_PHY_DX4GCR4_RESERVED_24 0x0
8379 * External VREF generator REFSEL range select
8380 * PSU_DDR_PHY_DX4GCR4_DXREFESELRANGE 0x0
8382 * Byte Lane External VREF Select
8383 * PSU_DDR_PHY_DX4GCR4_DXREFESEL 0x0
8385 * Single ended VREF generator REFSEL range select
8386 * PSU_DDR_PHY_DX4GCR4_DXREFSSELRANGE 0x1
8388 * Byte Lane Single-End VREF Select
8389 * PSU_DDR_PHY_DX4GCR4_DXREFSSEL 0x30
8391 * Reserved. Returns zeros on reads.
8392 * PSU_DDR_PHY_DX4GCR4_RESERVED_7_6 0x0
8394 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
8395 * PSU_DDR_PHY_DX4GCR4_DXREFIEN 0xf
8397 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
8398 * PSU_DDR_PHY_DX4GCR4_DXREFIMON 0x0
8400 * DATX8 n General Configuration Register 4
8401 * (OFFSET, MASK, VALUE) (0XFD080B10, 0xFFFFFFFFU ,0x0E00B03CU)
8403 PSU_Mask_Write(DDR_PHY_DX4GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU);
8404 /*##################################################################### */
8407 * Register : DX4GCR5 @ 0XFD080B14
8409 * Reserved. Returns zeros on reads.
8410 * PSU_DDR_PHY_DX4GCR5_RESERVED_31 0x0
8412 * Byte Lane internal VREF Select for Rank 3
8413 * PSU_DDR_PHY_DX4GCR5_DXREFISELR3 0x9
8415 * Reserved. Returns zeros on reads.
8416 * PSU_DDR_PHY_DX4GCR5_RESERVED_23 0x0
8418 * Byte Lane internal VREF Select for Rank 2
8419 * PSU_DDR_PHY_DX4GCR5_DXREFISELR2 0x9
8421 * Reserved. Returns zeros on reads.
8422 * PSU_DDR_PHY_DX4GCR5_RESERVED_15 0x0
8424 * Byte Lane internal VREF Select for Rank 1
8425 * PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x55
8427 * Reserved. Returns zeros on reads.
8428 * PSU_DDR_PHY_DX4GCR5_RESERVED_7 0x0
8430 * Byte Lane internal VREF Select for Rank 0
8431 * PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x55
8433 * DATX8 n General Configuration Register 5
8434 * (OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09095555U)
8436 PSU_Mask_Write(DDR_PHY_DX4GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U);
8437 /*##################################################################### */
8440 * Register : DX4GCR6 @ 0XFD080B18
8442 * Reserved. Returns zeros on reads.
8443 * PSU_DDR_PHY_DX4GCR6_RESERVED_31_30 0x0
8445 * DRAM DQ VREF Select for Rank3
8446 * PSU_DDR_PHY_DX4GCR6_DXDQVREFR3 0x9
8448 * Reserved. Returns zeros on reads.
8449 * PSU_DDR_PHY_DX4GCR6_RESERVED_23_22 0x0
8451 * DRAM DQ VREF Select for Rank2
8452 * PSU_DDR_PHY_DX4GCR6_DXDQVREFR2 0x9
8454 * Reserved. Returns zeros on reads.
8455 * PSU_DDR_PHY_DX4GCR6_RESERVED_15_14 0x0
8457 * DRAM DQ VREF Select for Rank1
8458 * PSU_DDR_PHY_DX4GCR6_DXDQVREFR1 0x2b
8460 * Reserved. Returns zeros on reads.
8461 * PSU_DDR_PHY_DX4GCR6_RESERVED_7_6 0x0
8463 * DRAM DQ VREF Select for Rank0
8464 * PSU_DDR_PHY_DX4GCR6_DXDQVREFR0 0x2b
8466 * DATX8 n General Configuration Register 6
8467 * (OFFSET, MASK, VALUE) (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU)
8469 PSU_Mask_Write(DDR_PHY_DX4GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU);
8470 /*##################################################################### */
8473 * Register : DX5GCR0 @ 0XFD080C00
8475 * Calibration Bypass
8476 * PSU_DDR_PHY_DX5GCR0_CALBYP 0x0
8478 * Master Delay Line Enable
8479 * PSU_DDR_PHY_DX5GCR0_MDLEN 0x1
8481 * Configurable ODT(TE) Phase Shift
8482 * PSU_DDR_PHY_DX5GCR0_CODTSHFT 0x0
8484 * DQS Duty Cycle Correction
8485 * PSU_DDR_PHY_DX5GCR0_DQSDCC 0x0
8487 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
8488 * input for the respective bypte lane of the PHY
8489 * PSU_DDR_PHY_DX5GCR0_RDDLY 0x8
8491 * Reserved. Return zeroes on reads.
8492 * PSU_DDR_PHY_DX5GCR0_RESERVED_19_14 0x0
8494 * DQSNSE Power Down Receiver
8495 * PSU_DDR_PHY_DX5GCR0_DQSNSEPDR 0x0
8497 * DQSSE Power Down Receiver
8498 * PSU_DDR_PHY_DX5GCR0_DQSSEPDR 0x0
8500 * RTT On Additive Latency
8501 * PSU_DDR_PHY_DX5GCR0_RTTOAL 0x0
8504 * PSU_DDR_PHY_DX5GCR0_RTTOH 0x3
8506 * Configurable PDR Phase Shift
8507 * PSU_DDR_PHY_DX5GCR0_CPDRSHFT 0x0
8510 * PSU_DDR_PHY_DX5GCR0_DQSRPD 0x0
8512 * DQSG Power Down Receiver
8513 * PSU_DDR_PHY_DX5GCR0_DQSGPDR 0x0
8515 * Reserved. Return zeroes on reads.
8516 * PSU_DDR_PHY_DX5GCR0_RESERVED_4 0x0
8518 * DQSG On-Die Termination
8519 * PSU_DDR_PHY_DX5GCR0_DQSGODT 0x0
8521 * DQSG Output Enable
8522 * PSU_DDR_PHY_DX5GCR0_DQSGOE 0x1
8524 * Reserved. Return zeroes on reads.
8525 * PSU_DDR_PHY_DX5GCR0_RESERVED_1_0 0x0
8527 * DATX8 n General Configuration Register 0
8528 * (OFFSET, MASK, VALUE) (0XFD080C00, 0xFFFFFFFFU ,0x40800604U)
8530 PSU_Mask_Write(DDR_PHY_DX5GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U);
8531 /*##################################################################### */
8534 * Register : DX5GCR1 @ 0XFD080C04
8536 * Enables the PDR mode for DQ[7:0]
8537 * PSU_DDR_PHY_DX5GCR1_DXPDRMODE 0x0
8539 * Reserved. Returns zeroes on reads.
8540 * PSU_DDR_PHY_DX5GCR1_RESERVED_15 0x0
8542 * Select the delayed or non-delayed read data strobe #
8543 * PSU_DDR_PHY_DX5GCR1_QSNSEL 0x1
8545 * Select the delayed or non-delayed read data strobe
8546 * PSU_DDR_PHY_DX5GCR1_QSSEL 0x1
8548 * Enables Read Data Strobe in a byte lane
8549 * PSU_DDR_PHY_DX5GCR1_OEEN 0x1
8551 * Enables PDR in a byte lane
8552 * PSU_DDR_PHY_DX5GCR1_PDREN 0x1
8554 * Enables ODT/TE in a byte lane
8555 * PSU_DDR_PHY_DX5GCR1_TEEN 0x1
8557 * Enables Write Data strobe in a byte lane
8558 * PSU_DDR_PHY_DX5GCR1_DSEN 0x1
8560 * Enables DM pin in a byte lane
8561 * PSU_DDR_PHY_DX5GCR1_DMEN 0x1
8563 * Enables DQ corresponding to each bit in a byte
8564 * PSU_DDR_PHY_DX5GCR1_DQEN 0xff
8566 * DATX8 n General Configuration Register 1
8567 * (OFFSET, MASK, VALUE) (0XFD080C04, 0xFFFFFFFFU ,0x00007FFFU)
8569 PSU_Mask_Write(DDR_PHY_DX5GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU);
8570 /*##################################################################### */
8573 * Register : DX5GCR4 @ 0XFD080C10
8575 * Byte lane VREF IOM (Used only by D4MU IOs)
8576 * PSU_DDR_PHY_DX5GCR4_RESERVED_31_29 0x0
8578 * Byte Lane VREF Pad Enable
8579 * PSU_DDR_PHY_DX5GCR4_DXREFPEN 0x0
8581 * Byte Lane Internal VREF Enable
8582 * PSU_DDR_PHY_DX5GCR4_DXREFEEN 0x3
8584 * Byte Lane Single-End VREF Enable
8585 * PSU_DDR_PHY_DX5GCR4_DXREFSEN 0x1
8587 * Reserved. Returns zeros on reads.
8588 * PSU_DDR_PHY_DX5GCR4_RESERVED_24 0x0
8590 * External VREF generator REFSEL range select
8591 * PSU_DDR_PHY_DX5GCR4_DXREFESELRANGE 0x0
8593 * Byte Lane External VREF Select
8594 * PSU_DDR_PHY_DX5GCR4_DXREFESEL 0x0
8596 * Single ended VREF generator REFSEL range select
8597 * PSU_DDR_PHY_DX5GCR4_DXREFSSELRANGE 0x1
8599 * Byte Lane Single-End VREF Select
8600 * PSU_DDR_PHY_DX5GCR4_DXREFSSEL 0x30
8602 * Reserved. Returns zeros on reads.
8603 * PSU_DDR_PHY_DX5GCR4_RESERVED_7_6 0x0
8605 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
8606 * PSU_DDR_PHY_DX5GCR4_DXREFIEN 0xf
8608 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
8609 * PSU_DDR_PHY_DX5GCR4_DXREFIMON 0x0
8611 * DATX8 n General Configuration Register 4
8612 * (OFFSET, MASK, VALUE) (0XFD080C10, 0xFFFFFFFFU ,0x0E00B03CU)
8614 PSU_Mask_Write(DDR_PHY_DX5GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU);
8615 /*##################################################################### */
8618 * Register : DX5GCR5 @ 0XFD080C14
8620 * Reserved. Returns zeros on reads.
8621 * PSU_DDR_PHY_DX5GCR5_RESERVED_31 0x0
8623 * Byte Lane internal VREF Select for Rank 3
8624 * PSU_DDR_PHY_DX5GCR5_DXREFISELR3 0x9
8626 * Reserved. Returns zeros on reads.
8627 * PSU_DDR_PHY_DX5GCR5_RESERVED_23 0x0
8629 * Byte Lane internal VREF Select for Rank 2
8630 * PSU_DDR_PHY_DX5GCR5_DXREFISELR2 0x9
8632 * Reserved. Returns zeros on reads.
8633 * PSU_DDR_PHY_DX5GCR5_RESERVED_15 0x0
8635 * Byte Lane internal VREF Select for Rank 1
8636 * PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x55
8638 * Reserved. Returns zeros on reads.
8639 * PSU_DDR_PHY_DX5GCR5_RESERVED_7 0x0
8641 * Byte Lane internal VREF Select for Rank 0
8642 * PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x55
8644 * DATX8 n General Configuration Register 5
8645 * (OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09095555U)
8647 PSU_Mask_Write(DDR_PHY_DX5GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U);
8648 /*##################################################################### */
8651 * Register : DX5GCR6 @ 0XFD080C18
8653 * Reserved. Returns zeros on reads.
8654 * PSU_DDR_PHY_DX5GCR6_RESERVED_31_30 0x0
8656 * DRAM DQ VREF Select for Rank3
8657 * PSU_DDR_PHY_DX5GCR6_DXDQVREFR3 0x9
8659 * Reserved. Returns zeros on reads.
8660 * PSU_DDR_PHY_DX5GCR6_RESERVED_23_22 0x0
8662 * DRAM DQ VREF Select for Rank2
8663 * PSU_DDR_PHY_DX5GCR6_DXDQVREFR2 0x9
8665 * Reserved. Returns zeros on reads.
8666 * PSU_DDR_PHY_DX5GCR6_RESERVED_15_14 0x0
8668 * DRAM DQ VREF Select for Rank1
8669 * PSU_DDR_PHY_DX5GCR6_DXDQVREFR1 0x2b
8671 * Reserved. Returns zeros on reads.
8672 * PSU_DDR_PHY_DX5GCR6_RESERVED_7_6 0x0
8674 * DRAM DQ VREF Select for Rank0
8675 * PSU_DDR_PHY_DX5GCR6_DXDQVREFR0 0x2b
8677 * DATX8 n General Configuration Register 6
8678 * (OFFSET, MASK, VALUE) (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU)
8680 PSU_Mask_Write(DDR_PHY_DX5GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU);
8681 /*##################################################################### */
8684 * Register : DX6GCR0 @ 0XFD080D00
8686 * Calibration Bypass
8687 * PSU_DDR_PHY_DX6GCR0_CALBYP 0x0
8689 * Master Delay Line Enable
8690 * PSU_DDR_PHY_DX6GCR0_MDLEN 0x1
8692 * Configurable ODT(TE) Phase Shift
8693 * PSU_DDR_PHY_DX6GCR0_CODTSHFT 0x0
8695 * DQS Duty Cycle Correction
8696 * PSU_DDR_PHY_DX6GCR0_DQSDCC 0x0
8698 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
8699 * input for the respective bypte lane of the PHY
8700 * PSU_DDR_PHY_DX6GCR0_RDDLY 0x8
8702 * Reserved. Return zeroes on reads.
8703 * PSU_DDR_PHY_DX6GCR0_RESERVED_19_14 0x0
8705 * DQSNSE Power Down Receiver
8706 * PSU_DDR_PHY_DX6GCR0_DQSNSEPDR 0x0
8708 * DQSSE Power Down Receiver
8709 * PSU_DDR_PHY_DX6GCR0_DQSSEPDR 0x0
8711 * RTT On Additive Latency
8712 * PSU_DDR_PHY_DX6GCR0_RTTOAL 0x0
8715 * PSU_DDR_PHY_DX6GCR0_RTTOH 0x3
8717 * Configurable PDR Phase Shift
8718 * PSU_DDR_PHY_DX6GCR0_CPDRSHFT 0x0
8721 * PSU_DDR_PHY_DX6GCR0_DQSRPD 0x0
8723 * DQSG Power Down Receiver
8724 * PSU_DDR_PHY_DX6GCR0_DQSGPDR 0x0
8726 * Reserved. Return zeroes on reads.
8727 * PSU_DDR_PHY_DX6GCR0_RESERVED_4 0x0
8729 * DQSG On-Die Termination
8730 * PSU_DDR_PHY_DX6GCR0_DQSGODT 0x0
8732 * DQSG Output Enable
8733 * PSU_DDR_PHY_DX6GCR0_DQSGOE 0x1
8735 * Reserved. Return zeroes on reads.
8736 * PSU_DDR_PHY_DX6GCR0_RESERVED_1_0 0x0
8738 * DATX8 n General Configuration Register 0
8739 * (OFFSET, MASK, VALUE) (0XFD080D00, 0xFFFFFFFFU ,0x40800604U)
8741 PSU_Mask_Write(DDR_PHY_DX6GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U);
8742 /*##################################################################### */
8745 * Register : DX6GCR1 @ 0XFD080D04
8747 * Enables the PDR mode for DQ[7:0]
8748 * PSU_DDR_PHY_DX6GCR1_DXPDRMODE 0x0
8750 * Reserved. Returns zeroes on reads.
8751 * PSU_DDR_PHY_DX6GCR1_RESERVED_15 0x0
8753 * Select the delayed or non-delayed read data strobe #
8754 * PSU_DDR_PHY_DX6GCR1_QSNSEL 0x1
8756 * Select the delayed or non-delayed read data strobe
8757 * PSU_DDR_PHY_DX6GCR1_QSSEL 0x1
8759 * Enables Read Data Strobe in a byte lane
8760 * PSU_DDR_PHY_DX6GCR1_OEEN 0x1
8762 * Enables PDR in a byte lane
8763 * PSU_DDR_PHY_DX6GCR1_PDREN 0x1
8765 * Enables ODT/TE in a byte lane
8766 * PSU_DDR_PHY_DX6GCR1_TEEN 0x1
8768 * Enables Write Data strobe in a byte lane
8769 * PSU_DDR_PHY_DX6GCR1_DSEN 0x1
8771 * Enables DM pin in a byte lane
8772 * PSU_DDR_PHY_DX6GCR1_DMEN 0x1
8774 * Enables DQ corresponding to each bit in a byte
8775 * PSU_DDR_PHY_DX6GCR1_DQEN 0xff
8777 * DATX8 n General Configuration Register 1
8778 * (OFFSET, MASK, VALUE) (0XFD080D04, 0xFFFFFFFFU ,0x00007FFFU)
8780 PSU_Mask_Write(DDR_PHY_DX6GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU);
8781 /*##################################################################### */
8784 * Register : DX6GCR4 @ 0XFD080D10
8786 * Byte lane VREF IOM (Used only by D4MU IOs)
8787 * PSU_DDR_PHY_DX6GCR4_RESERVED_31_29 0x0
8789 * Byte Lane VREF Pad Enable
8790 * PSU_DDR_PHY_DX6GCR4_DXREFPEN 0x0
8792 * Byte Lane Internal VREF Enable
8793 * PSU_DDR_PHY_DX6GCR4_DXREFEEN 0x3
8795 * Byte Lane Single-End VREF Enable
8796 * PSU_DDR_PHY_DX6GCR4_DXREFSEN 0x1
8798 * Reserved. Returns zeros on reads.
8799 * PSU_DDR_PHY_DX6GCR4_RESERVED_24 0x0
8801 * External VREF generator REFSEL range select
8802 * PSU_DDR_PHY_DX6GCR4_DXREFESELRANGE 0x0
8804 * Byte Lane External VREF Select
8805 * PSU_DDR_PHY_DX6GCR4_DXREFESEL 0x0
8807 * Single ended VREF generator REFSEL range select
8808 * PSU_DDR_PHY_DX6GCR4_DXREFSSELRANGE 0x1
8810 * Byte Lane Single-End VREF Select
8811 * PSU_DDR_PHY_DX6GCR4_DXREFSSEL 0x30
8813 * Reserved. Returns zeros on reads.
8814 * PSU_DDR_PHY_DX6GCR4_RESERVED_7_6 0x0
8816 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
8817 * PSU_DDR_PHY_DX6GCR4_DXREFIEN 0xf
8819 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
8820 * PSU_DDR_PHY_DX6GCR4_DXREFIMON 0x0
8822 * DATX8 n General Configuration Register 4
8823 * (OFFSET, MASK, VALUE) (0XFD080D10, 0xFFFFFFFFU ,0x0E00B03CU)
8825 PSU_Mask_Write(DDR_PHY_DX6GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU);
8826 /*##################################################################### */
8829 * Register : DX6GCR5 @ 0XFD080D14
8831 * Reserved. Returns zeros on reads.
8832 * PSU_DDR_PHY_DX6GCR5_RESERVED_31 0x0
8834 * Byte Lane internal VREF Select for Rank 3
8835 * PSU_DDR_PHY_DX6GCR5_DXREFISELR3 0x9
8837 * Reserved. Returns zeros on reads.
8838 * PSU_DDR_PHY_DX6GCR5_RESERVED_23 0x0
8840 * Byte Lane internal VREF Select for Rank 2
8841 * PSU_DDR_PHY_DX6GCR5_DXREFISELR2 0x9
8843 * Reserved. Returns zeros on reads.
8844 * PSU_DDR_PHY_DX6GCR5_RESERVED_15 0x0
8846 * Byte Lane internal VREF Select for Rank 1
8847 * PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x55
8849 * Reserved. Returns zeros on reads.
8850 * PSU_DDR_PHY_DX6GCR5_RESERVED_7 0x0
8852 * Byte Lane internal VREF Select for Rank 0
8853 * PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x55
8855 * DATX8 n General Configuration Register 5
8856 * (OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09095555U)
8858 PSU_Mask_Write(DDR_PHY_DX6GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U);
8859 /*##################################################################### */
8862 * Register : DX6GCR6 @ 0XFD080D18
8864 * Reserved. Returns zeros on reads.
8865 * PSU_DDR_PHY_DX6GCR6_RESERVED_31_30 0x0
8867 * DRAM DQ VREF Select for Rank3
8868 * PSU_DDR_PHY_DX6GCR6_DXDQVREFR3 0x9
8870 * Reserved. Returns zeros on reads.
8871 * PSU_DDR_PHY_DX6GCR6_RESERVED_23_22 0x0
8873 * DRAM DQ VREF Select for Rank2
8874 * PSU_DDR_PHY_DX6GCR6_DXDQVREFR2 0x9
8876 * Reserved. Returns zeros on reads.
8877 * PSU_DDR_PHY_DX6GCR6_RESERVED_15_14 0x0
8879 * DRAM DQ VREF Select for Rank1
8880 * PSU_DDR_PHY_DX6GCR6_DXDQVREFR1 0x2b
8882 * Reserved. Returns zeros on reads.
8883 * PSU_DDR_PHY_DX6GCR6_RESERVED_7_6 0x0
8885 * DRAM DQ VREF Select for Rank0
8886 * PSU_DDR_PHY_DX6GCR6_DXDQVREFR0 0x2b
8888 * DATX8 n General Configuration Register 6
8889 * (OFFSET, MASK, VALUE) (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU)
8891 PSU_Mask_Write(DDR_PHY_DX6GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU);
8892 /*##################################################################### */
8895 * Register : DX7GCR0 @ 0XFD080E00
8897 * Calibration Bypass
8898 * PSU_DDR_PHY_DX7GCR0_CALBYP 0x0
8900 * Master Delay Line Enable
8901 * PSU_DDR_PHY_DX7GCR0_MDLEN 0x1
8903 * Configurable ODT(TE) Phase Shift
8904 * PSU_DDR_PHY_DX7GCR0_CODTSHFT 0x0
8906 * DQS Duty Cycle Correction
8907 * PSU_DDR_PHY_DX7GCR0_DQSDCC 0x0
8909 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
8910 * input for the respective bypte lane of the PHY
8911 * PSU_DDR_PHY_DX7GCR0_RDDLY 0x8
8913 * Reserved. Return zeroes on reads.
8914 * PSU_DDR_PHY_DX7GCR0_RESERVED_19_14 0x0
8916 * DQSNSE Power Down Receiver
8917 * PSU_DDR_PHY_DX7GCR0_DQSNSEPDR 0x0
8919 * DQSSE Power Down Receiver
8920 * PSU_DDR_PHY_DX7GCR0_DQSSEPDR 0x0
8922 * RTT On Additive Latency
8923 * PSU_DDR_PHY_DX7GCR0_RTTOAL 0x0
8926 * PSU_DDR_PHY_DX7GCR0_RTTOH 0x3
8928 * Configurable PDR Phase Shift
8929 * PSU_DDR_PHY_DX7GCR0_CPDRSHFT 0x0
8932 * PSU_DDR_PHY_DX7GCR0_DQSRPD 0x0
8934 * DQSG Power Down Receiver
8935 * PSU_DDR_PHY_DX7GCR0_DQSGPDR 0x0
8937 * Reserved. Return zeroes on reads.
8938 * PSU_DDR_PHY_DX7GCR0_RESERVED_4 0x0
8940 * DQSG On-Die Termination
8941 * PSU_DDR_PHY_DX7GCR0_DQSGODT 0x0
8943 * DQSG Output Enable
8944 * PSU_DDR_PHY_DX7GCR0_DQSGOE 0x1
8946 * Reserved. Return zeroes on reads.
8947 * PSU_DDR_PHY_DX7GCR0_RESERVED_1_0 0x0
8949 * DATX8 n General Configuration Register 0
8950 * (OFFSET, MASK, VALUE) (0XFD080E00, 0xFFFFFFFFU ,0x40800604U)
8952 PSU_Mask_Write(DDR_PHY_DX7GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U);
8953 /*##################################################################### */
8956 * Register : DX7GCR1 @ 0XFD080E04
8958 * Enables the PDR mode for DQ[7:0]
8959 * PSU_DDR_PHY_DX7GCR1_DXPDRMODE 0x0
8961 * Reserved. Returns zeroes on reads.
8962 * PSU_DDR_PHY_DX7GCR1_RESERVED_15 0x0
8964 * Select the delayed or non-delayed read data strobe #
8965 * PSU_DDR_PHY_DX7GCR1_QSNSEL 0x1
8967 * Select the delayed or non-delayed read data strobe
8968 * PSU_DDR_PHY_DX7GCR1_QSSEL 0x1
8970 * Enables Read Data Strobe in a byte lane
8971 * PSU_DDR_PHY_DX7GCR1_OEEN 0x1
8973 * Enables PDR in a byte lane
8974 * PSU_DDR_PHY_DX7GCR1_PDREN 0x1
8976 * Enables ODT/TE in a byte lane
8977 * PSU_DDR_PHY_DX7GCR1_TEEN 0x1
8979 * Enables Write Data strobe in a byte lane
8980 * PSU_DDR_PHY_DX7GCR1_DSEN 0x1
8982 * Enables DM pin in a byte lane
8983 * PSU_DDR_PHY_DX7GCR1_DMEN 0x1
8985 * Enables DQ corresponding to each bit in a byte
8986 * PSU_DDR_PHY_DX7GCR1_DQEN 0xff
8988 * DATX8 n General Configuration Register 1
8989 * (OFFSET, MASK, VALUE) (0XFD080E04, 0xFFFFFFFFU ,0x00007FFFU)
8991 PSU_Mask_Write(DDR_PHY_DX7GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU);
8992 /*##################################################################### */
8995 * Register : DX7GCR4 @ 0XFD080E10
8997 * Byte lane VREF IOM (Used only by D4MU IOs)
8998 * PSU_DDR_PHY_DX7GCR4_RESERVED_31_29 0x0
9000 * Byte Lane VREF Pad Enable
9001 * PSU_DDR_PHY_DX7GCR4_DXREFPEN 0x0
9003 * Byte Lane Internal VREF Enable
9004 * PSU_DDR_PHY_DX7GCR4_DXREFEEN 0x3
9006 * Byte Lane Single-End VREF Enable
9007 * PSU_DDR_PHY_DX7GCR4_DXREFSEN 0x1
9009 * Reserved. Returns zeros on reads.
9010 * PSU_DDR_PHY_DX7GCR4_RESERVED_24 0x0
9012 * External VREF generator REFSEL range select
9013 * PSU_DDR_PHY_DX7GCR4_DXREFESELRANGE 0x0
9015 * Byte Lane External VREF Select
9016 * PSU_DDR_PHY_DX7GCR4_DXREFESEL 0x0
9018 * Single ended VREF generator REFSEL range select
9019 * PSU_DDR_PHY_DX7GCR4_DXREFSSELRANGE 0x1
9021 * Byte Lane Single-End VREF Select
9022 * PSU_DDR_PHY_DX7GCR4_DXREFSSEL 0x30
9024 * Reserved. Returns zeros on reads.
9025 * PSU_DDR_PHY_DX7GCR4_RESERVED_7_6 0x0
9027 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
9028 * PSU_DDR_PHY_DX7GCR4_DXREFIEN 0xf
9030 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
9031 * PSU_DDR_PHY_DX7GCR4_DXREFIMON 0x0
9033 * DATX8 n General Configuration Register 4
9034 * (OFFSET, MASK, VALUE) (0XFD080E10, 0xFFFFFFFFU ,0x0E00B03CU)
9036 PSU_Mask_Write(DDR_PHY_DX7GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU);
9037 /*##################################################################### */
9040 * Register : DX7GCR5 @ 0XFD080E14
9042 * Reserved. Returns zeros on reads.
9043 * PSU_DDR_PHY_DX7GCR5_RESERVED_31 0x0
9045 * Byte Lane internal VREF Select for Rank 3
9046 * PSU_DDR_PHY_DX7GCR5_DXREFISELR3 0x9
9048 * Reserved. Returns zeros on reads.
9049 * PSU_DDR_PHY_DX7GCR5_RESERVED_23 0x0
9051 * Byte Lane internal VREF Select for Rank 2
9052 * PSU_DDR_PHY_DX7GCR5_DXREFISELR2 0x9
9054 * Reserved. Returns zeros on reads.
9055 * PSU_DDR_PHY_DX7GCR5_RESERVED_15 0x0
9057 * Byte Lane internal VREF Select for Rank 1
9058 * PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x55
9060 * Reserved. Returns zeros on reads.
9061 * PSU_DDR_PHY_DX7GCR5_RESERVED_7 0x0
9063 * Byte Lane internal VREF Select for Rank 0
9064 * PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x55
9066 * DATX8 n General Configuration Register 5
9067 * (OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09095555U)
9069 PSU_Mask_Write(DDR_PHY_DX7GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U);
9070 /*##################################################################### */
9073 * Register : DX7GCR6 @ 0XFD080E18
9075 * Reserved. Returns zeros on reads.
9076 * PSU_DDR_PHY_DX7GCR6_RESERVED_31_30 0x0
9078 * DRAM DQ VREF Select for Rank3
9079 * PSU_DDR_PHY_DX7GCR6_DXDQVREFR3 0x9
9081 * Reserved. Returns zeros on reads.
9082 * PSU_DDR_PHY_DX7GCR6_RESERVED_23_22 0x0
9084 * DRAM DQ VREF Select for Rank2
9085 * PSU_DDR_PHY_DX7GCR6_DXDQVREFR2 0x9
9087 * Reserved. Returns zeros on reads.
9088 * PSU_DDR_PHY_DX7GCR6_RESERVED_15_14 0x0
9090 * DRAM DQ VREF Select for Rank1
9091 * PSU_DDR_PHY_DX7GCR6_DXDQVREFR1 0x2b
9093 * Reserved. Returns zeros on reads.
9094 * PSU_DDR_PHY_DX7GCR6_RESERVED_7_6 0x0
9096 * DRAM DQ VREF Select for Rank0
9097 * PSU_DDR_PHY_DX7GCR6_DXDQVREFR0 0x2b
9099 * DATX8 n General Configuration Register 6
9100 * (OFFSET, MASK, VALUE) (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU)
9102 PSU_Mask_Write(DDR_PHY_DX7GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU);
9103 /*##################################################################### */
9106 * Register : DX8GCR0 @ 0XFD080F00
9108 * Calibration Bypass
9109 * PSU_DDR_PHY_DX8GCR0_CALBYP 0x0
9111 * Master Delay Line Enable
9112 * PSU_DDR_PHY_DX8GCR0_MDLEN 0x1
9114 * Configurable ODT(TE) Phase Shift
9115 * PSU_DDR_PHY_DX8GCR0_CODTSHFT 0x0
9117 * DQS Duty Cycle Correction
9118 * PSU_DDR_PHY_DX8GCR0_DQSDCC 0x0
9120 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
9121 * input for the respective bypte lane of the PHY
9122 * PSU_DDR_PHY_DX8GCR0_RDDLY 0x8
9124 * Reserved. Return zeroes on reads.
9125 * PSU_DDR_PHY_DX8GCR0_RESERVED_19_14 0x0
9127 * DQSNSE Power Down Receiver
9128 * PSU_DDR_PHY_DX8GCR0_DQSNSEPDR 0x0
9130 * DQSSE Power Down Receiver
9131 * PSU_DDR_PHY_DX8GCR0_DQSSEPDR 0x0
9133 * RTT On Additive Latency
9134 * PSU_DDR_PHY_DX8GCR0_RTTOAL 0x0
9137 * PSU_DDR_PHY_DX8GCR0_RTTOH 0x3
9139 * Configurable PDR Phase Shift
9140 * PSU_DDR_PHY_DX8GCR0_CPDRSHFT 0x0
9143 * PSU_DDR_PHY_DX8GCR0_DQSRPD 0x0
9145 * DQSG Power Down Receiver
9146 * PSU_DDR_PHY_DX8GCR0_DQSGPDR 0x1
9148 * Reserved. Return zeroes on reads.
9149 * PSU_DDR_PHY_DX8GCR0_RESERVED_4 0x0
9151 * DQSG On-Die Termination
9152 * PSU_DDR_PHY_DX8GCR0_DQSGODT 0x0
9154 * DQSG Output Enable
9155 * PSU_DDR_PHY_DX8GCR0_DQSGOE 0x1
9157 * Reserved. Return zeroes on reads.
9158 * PSU_DDR_PHY_DX8GCR0_RESERVED_1_0 0x0
9160 * DATX8 n General Configuration Register 0
9161 * (OFFSET, MASK, VALUE) (0XFD080F00, 0xFFFFFFFFU ,0x40800624U)
9163 PSU_Mask_Write(DDR_PHY_DX8GCR0_OFFSET, 0xFFFFFFFFU, 0x40800624U);
9164 /*##################################################################### */
9167 * Register : DX8GCR1 @ 0XFD080F04
9169 * Enables the PDR mode for DQ[7:0]
9170 * PSU_DDR_PHY_DX8GCR1_DXPDRMODE 0x0
9172 * Reserved. Returns zeroes on reads.
9173 * PSU_DDR_PHY_DX8GCR1_RESERVED_15 0x0
9175 * Select the delayed or non-delayed read data strobe #
9176 * PSU_DDR_PHY_DX8GCR1_QSNSEL 0x1
9178 * Select the delayed or non-delayed read data strobe
9179 * PSU_DDR_PHY_DX8GCR1_QSSEL 0x1
9181 * Enables Read Data Strobe in a byte lane
9182 * PSU_DDR_PHY_DX8GCR1_OEEN 0x1
9184 * Enables PDR in a byte lane
9185 * PSU_DDR_PHY_DX8GCR1_PDREN 0x1
9187 * Enables ODT/TE in a byte lane
9188 * PSU_DDR_PHY_DX8GCR1_TEEN 0x1
9190 * Enables Write Data strobe in a byte lane
9191 * PSU_DDR_PHY_DX8GCR1_DSEN 0x1
9193 * Enables DM pin in a byte lane
9194 * PSU_DDR_PHY_DX8GCR1_DMEN 0x1
9196 * Enables DQ corresponding to each bit in a byte
9197 * PSU_DDR_PHY_DX8GCR1_DQEN 0x0
9199 * DATX8 n General Configuration Register 1
9200 * (OFFSET, MASK, VALUE) (0XFD080F04, 0xFFFFFFFFU ,0x00007F00U)
9202 PSU_Mask_Write(DDR_PHY_DX8GCR1_OFFSET, 0xFFFFFFFFU, 0x00007F00U);
9203 /*##################################################################### */
9206 * Register : DX8GCR4 @ 0XFD080F10
9208 * Byte lane VREF IOM (Used only by D4MU IOs)
9209 * PSU_DDR_PHY_DX8GCR4_RESERVED_31_29 0x0
9211 * Byte Lane VREF Pad Enable
9212 * PSU_DDR_PHY_DX8GCR4_DXREFPEN 0x0
9214 * Byte Lane Internal VREF Enable
9215 * PSU_DDR_PHY_DX8GCR4_DXREFEEN 0x3
9217 * Byte Lane Single-End VREF Enable
9218 * PSU_DDR_PHY_DX8GCR4_DXREFSEN 0x1
9220 * Reserved. Returns zeros on reads.
9221 * PSU_DDR_PHY_DX8GCR4_RESERVED_24 0x0
9223 * External VREF generator REFSEL range select
9224 * PSU_DDR_PHY_DX8GCR4_DXREFESELRANGE 0x0
9226 * Byte Lane External VREF Select
9227 * PSU_DDR_PHY_DX8GCR4_DXREFESEL 0x0
9229 * Single ended VREF generator REFSEL range select
9230 * PSU_DDR_PHY_DX8GCR4_DXREFSSELRANGE 0x1
9232 * Byte Lane Single-End VREF Select
9233 * PSU_DDR_PHY_DX8GCR4_DXREFSSEL 0x30
9235 * Reserved. Returns zeros on reads.
9236 * PSU_DDR_PHY_DX8GCR4_RESERVED_7_6 0x0
9238 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
9239 * PSU_DDR_PHY_DX8GCR4_DXREFIEN 0xf
9241 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
9242 * PSU_DDR_PHY_DX8GCR4_DXREFIMON 0x0
9244 * DATX8 n General Configuration Register 4
9245 * (OFFSET, MASK, VALUE) (0XFD080F10, 0xFFFFFFFFU ,0x0E00B03CU)
9247 PSU_Mask_Write(DDR_PHY_DX8GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU);
9248 /*##################################################################### */
9251 * Register : DX8GCR5 @ 0XFD080F14
9253 * Reserved. Returns zeros on reads.
9254 * PSU_DDR_PHY_DX8GCR5_RESERVED_31 0x0
9256 * Byte Lane internal VREF Select for Rank 3
9257 * PSU_DDR_PHY_DX8GCR5_DXREFISELR3 0x9
9259 * Reserved. Returns zeros on reads.
9260 * PSU_DDR_PHY_DX8GCR5_RESERVED_23 0x0
9262 * Byte Lane internal VREF Select for Rank 2
9263 * PSU_DDR_PHY_DX8GCR5_DXREFISELR2 0x9
9265 * Reserved. Returns zeros on reads.
9266 * PSU_DDR_PHY_DX8GCR5_RESERVED_15 0x0
9268 * Byte Lane internal VREF Select for Rank 1
9269 * PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x55
9271 * Reserved. Returns zeros on reads.
9272 * PSU_DDR_PHY_DX8GCR5_RESERVED_7 0x0
9274 * Byte Lane internal VREF Select for Rank 0
9275 * PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x55
9277 * DATX8 n General Configuration Register 5
9278 * (OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09095555U)
9280 PSU_Mask_Write(DDR_PHY_DX8GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U);
9281 /*##################################################################### */
9284 * Register : DX8GCR6 @ 0XFD080F18
9286 * Reserved. Returns zeros on reads.
9287 * PSU_DDR_PHY_DX8GCR6_RESERVED_31_30 0x0
9289 * DRAM DQ VREF Select for Rank3
9290 * PSU_DDR_PHY_DX8GCR6_DXDQVREFR3 0x9
9292 * Reserved. Returns zeros on reads.
9293 * PSU_DDR_PHY_DX8GCR6_RESERVED_23_22 0x0
9295 * DRAM DQ VREF Select for Rank2
9296 * PSU_DDR_PHY_DX8GCR6_DXDQVREFR2 0x9
9298 * Reserved. Returns zeros on reads.
9299 * PSU_DDR_PHY_DX8GCR6_RESERVED_15_14 0x0
9301 * DRAM DQ VREF Select for Rank1
9302 * PSU_DDR_PHY_DX8GCR6_DXDQVREFR1 0x2b
9304 * Reserved. Returns zeros on reads.
9305 * PSU_DDR_PHY_DX8GCR6_RESERVED_7_6 0x0
9307 * DRAM DQ VREF Select for Rank0
9308 * PSU_DDR_PHY_DX8GCR6_DXDQVREFR0 0x2b
9310 * DATX8 n General Configuration Register 6
9311 * (OFFSET, MASK, VALUE) (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU)
9313 PSU_Mask_Write(DDR_PHY_DX8GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU);
9314 /*##################################################################### */
9317 * Register : DX8SL0OSC @ 0XFD081400
9319 * Reserved. Return zeroes on reads.
9320 * PSU_DDR_PHY_DX8SL0OSC_RESERVED_31_30 0x0
9322 * Enable Clock Gating for DX ddr_clk
9323 * PSU_DDR_PHY_DX8SL0OSC_GATEDXRDCLK 0x2
9325 * Enable Clock Gating for DX ctl_rd_clk
9326 * PSU_DDR_PHY_DX8SL0OSC_GATEDXDDRCLK 0x2
9328 * Enable Clock Gating for DX ctl_clk
9329 * PSU_DDR_PHY_DX8SL0OSC_GATEDXCTLCLK 0x2
9331 * Selects the level to which clocks will be stalled when clock gating is e
9333 * PSU_DDR_PHY_DX8SL0OSC_CLKLEVEL 0x0
9336 * PSU_DDR_PHY_DX8SL0OSC_LBMODE 0x0
9338 * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
9339 * PSU_DDR_PHY_DX8SL0OSC_LBGSDQS 0x0
9341 * Loopback DQS Gating
9342 * PSU_DDR_PHY_DX8SL0OSC_LBGDQS 0x0
9344 * Loopback DQS Shift
9345 * PSU_DDR_PHY_DX8SL0OSC_LBDQSS 0x0
9347 * PHY High-Speed Reset
9348 * PSU_DDR_PHY_DX8SL0OSC_PHYHRST 0x1
9351 * PSU_DDR_PHY_DX8SL0OSC_PHYFRST 0x1
9353 * Delay Line Test Start
9354 * PSU_DDR_PHY_DX8SL0OSC_DLTST 0x0
9356 * Delay Line Test Mode
9357 * PSU_DDR_PHY_DX8SL0OSC_DLTMODE 0x0
9359 * Reserved. Caution, do not write to this register field.
9360 * PSU_DDR_PHY_DX8SL0OSC_RESERVED_12_11 0x3
9362 * Oscillator Mode Write-Data Delay Line Select
9363 * PSU_DDR_PHY_DX8SL0OSC_OSCWDDL 0x3
9365 * Reserved. Caution, do not write to this register field.
9366 * PSU_DDR_PHY_DX8SL0OSC_RESERVED_8_7 0x3
9368 * Oscillator Mode Write-Leveling Delay Line Select
9369 * PSU_DDR_PHY_DX8SL0OSC_OSCWDL 0x3
9371 * Oscillator Mode Division
9372 * PSU_DDR_PHY_DX8SL0OSC_OSCDIV 0xf
9375 * PSU_DDR_PHY_DX8SL0OSC_OSCEN 0x0
9377 * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo
9378 * opback, and Gated Clock Control Register
9379 * (OFFSET, MASK, VALUE) (0XFD081400, 0xFFFFFFFFU ,0x2A019FFEU)
9381 PSU_Mask_Write(DDR_PHY_DX8SL0OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU);
9382 /*##################################################################### */
9385 * Register : DX8SL0PLLCR0 @ 0XFD081404
9388 * PSU_DDR_PHY_DX8SL0PLLCR0_PLLBYP 0x0
9391 * PSU_DDR_PHY_DX8SL0PLLCR0_PLLRST 0x0
9394 * PSU_DDR_PHY_DX8SL0PLLCR0_PLLPD 0x0
9396 * Reference Stop Mode
9397 * PSU_DDR_PHY_DX8SL0PLLCR0_RSTOPM 0x0
9399 * PLL Frequency Select
9400 * PSU_DDR_PHY_DX8SL0PLLCR0_FRQSEL 0x1
9403 * PSU_DDR_PHY_DX8SL0PLLCR0_RLOCKM 0x0
9405 * Charge Pump Proportional Current Control
9406 * PSU_DDR_PHY_DX8SL0PLLCR0_CPPC 0x8
9408 * Charge Pump Integrating Current Control
9409 * PSU_DDR_PHY_DX8SL0PLLCR0_CPIC 0x0
9412 * PSU_DDR_PHY_DX8SL0PLLCR0_GSHIFT 0x0
9414 * Reserved. Return zeroes on reads.
9415 * PSU_DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9 0x0
9417 * Analog Test Enable (ATOEN)
9418 * PSU_DDR_PHY_DX8SL0PLLCR0_ATOEN 0x0
9420 * Analog Test Control
9421 * PSU_DDR_PHY_DX8SL0PLLCR0_ATC 0x0
9423 * Digital Test Control
9424 * PSU_DDR_PHY_DX8SL0PLLCR0_DTC 0x0
9426 * DAXT8 0-1 PLL Control Register 0
9427 * (OFFSET, MASK, VALUE) (0XFD081404, 0xFFFFFFFFU ,0x01100000U)
9429 PSU_Mask_Write(DDR_PHY_DX8SL0PLLCR0_OFFSET,
9430 0xFFFFFFFFU, 0x01100000U);
9431 /*##################################################################### */
9434 * Register : DX8SL0DQSCTL @ 0XFD08141C
9436 * Reserved. Return zeroes on reads.
9437 * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25 0x0
9439 * Read Path Rise-to-Rise Mode
9440 * PSU_DDR_PHY_DX8SL0DQSCTL_RRRMODE 0x1
9442 * Reserved. Return zeroes on reads.
9443 * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22 0x0
9445 * Write Path Rise-to-Rise Mode
9446 * PSU_DDR_PHY_DX8SL0DQSCTL_WRRMODE 0x1
9448 * DQS Gate Extension
9449 * PSU_DDR_PHY_DX8SL0DQSCTL_DQSGX 0x0
9451 * Low Power PLL Power Down
9452 * PSU_DDR_PHY_DX8SL0DQSCTL_LPPLLPD 0x1
9454 * Low Power I/O Power Down
9455 * PSU_DDR_PHY_DX8SL0DQSCTL_LPIOPD 0x1
9457 * Reserved. Return zeroes on reads.
9458 * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15 0x0
9461 * PSU_DDR_PHY_DX8SL0DQSCTL_QSCNTEN 0x1
9463 * Unused DQ I/O Mode
9464 * PSU_DDR_PHY_DX8SL0DQSCTL_UDQIOM 0x0
9466 * Reserved. Return zeroes on reads.
9467 * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10 0x0
9470 * PSU_DDR_PHY_DX8SL0DQSCTL_DXSR 0x3
9473 * PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES 0x0
9476 * PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES 0x0
9478 * DATX8 0-1 DQS Control Register
9479 * (OFFSET, MASK, VALUE) (0XFD08141C, 0xFFFFFFFFU ,0x01264300U)
9481 PSU_Mask_Write(DDR_PHY_DX8SL0DQSCTL_OFFSET,
9482 0xFFFFFFFFU, 0x01264300U);
9483 /*##################################################################### */
9486 * Register : DX8SL0DXCTL2 @ 0XFD08142C
9488 * Reserved. Return zeroes on reads.
9489 * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24 0x0
9491 * Configurable Read Data Enable
9492 * PSU_DDR_PHY_DX8SL0DXCTL2_CRDEN 0x0
9494 * OX Extension during Post-amble
9495 * PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX 0x0
9497 * OE Extension during Pre-amble
9498 * PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX 0x1
9500 * Reserved. Return zeroes on reads.
9501 * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17 0x0
9503 * I/O Assisted Gate Select
9504 * PSU_DDR_PHY_DX8SL0DXCTL2_IOAG 0x0
9506 * I/O Loopback Select
9507 * PSU_DDR_PHY_DX8SL0DXCTL2_IOLB 0x0
9509 * Reserved. Return zeroes on reads.
9510 * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13 0x0
9512 * Low Power Wakeup Threshold
9513 * PSU_DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH 0xc
9515 * Read Data Bus Inversion Enable
9516 * PSU_DDR_PHY_DX8SL0DXCTL2_RDBI 0x0
9518 * Write Data Bus Inversion Enable
9519 * PSU_DDR_PHY_DX8SL0DXCTL2_WDBI 0x0
9521 * PUB Read FIFO Bypass
9522 * PSU_DDR_PHY_DX8SL0DXCTL2_PRFBYP 0x0
9524 * DATX8 Receive FIFO Read Mode
9525 * PSU_DDR_PHY_DX8SL0DXCTL2_RDMODE 0x0
9527 * Disables the Read FIFO Reset
9528 * PSU_DDR_PHY_DX8SL0DXCTL2_DISRST 0x0
9530 * Read DQS Gate I/O Loopback
9531 * PSU_DDR_PHY_DX8SL0DXCTL2_DQSGLB 0x0
9533 * Reserved. Return zeroes on reads.
9534 * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0 0x0
9536 * DATX8 0-1 DX Control Register 2
9537 * (OFFSET, MASK, VALUE) (0XFD08142C, 0xFFFFFFFFU ,0x00041800U)
9539 PSU_Mask_Write(DDR_PHY_DX8SL0DXCTL2_OFFSET,
9540 0xFFFFFFFFU, 0x00041800U);
9541 /*##################################################################### */
9544 * Register : DX8SL0IOCR @ 0XFD081430
9546 * Reserved. Return zeroes on reads.
9547 * PSU_DDR_PHY_DX8SL0IOCR_RESERVED_31 0x0
9549 * PVREF_DAC REFSEL range select
9550 * PSU_DDR_PHY_DX8SL0IOCR_DXDACRANGE 0x7
9552 * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
9553 * PSU_DDR_PHY_DX8SL0IOCR_DXVREFIOM 0x0
9556 * PSU_DDR_PHY_DX8SL0IOCR_DXIOM 0x2
9558 * DX IO Transmitter Mode
9559 * PSU_DDR_PHY_DX8SL0IOCR_DXTXM 0x0
9561 * DX IO Receiver Mode
9562 * PSU_DDR_PHY_DX8SL0IOCR_DXRXM 0x0
9564 * DATX8 0-1 I/O Configuration Register
9565 * (OFFSET, MASK, VALUE) (0XFD081430, 0xFFFFFFFFU ,0x70800000U)
9567 PSU_Mask_Write(DDR_PHY_DX8SL0IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U);
9568 /*##################################################################### */
9571 * Register : DX8SL1OSC @ 0XFD081440
9573 * Reserved. Return zeroes on reads.
9574 * PSU_DDR_PHY_DX8SL1OSC_RESERVED_31_30 0x0
9576 * Enable Clock Gating for DX ddr_clk
9577 * PSU_DDR_PHY_DX8SL1OSC_GATEDXRDCLK 0x2
9579 * Enable Clock Gating for DX ctl_rd_clk
9580 * PSU_DDR_PHY_DX8SL1OSC_GATEDXDDRCLK 0x2
9582 * Enable Clock Gating for DX ctl_clk
9583 * PSU_DDR_PHY_DX8SL1OSC_GATEDXCTLCLK 0x2
9585 * Selects the level to which clocks will be stalled when clock gating is e
9587 * PSU_DDR_PHY_DX8SL1OSC_CLKLEVEL 0x0
9590 * PSU_DDR_PHY_DX8SL1OSC_LBMODE 0x0
9592 * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
9593 * PSU_DDR_PHY_DX8SL1OSC_LBGSDQS 0x0
9595 * Loopback DQS Gating
9596 * PSU_DDR_PHY_DX8SL1OSC_LBGDQS 0x0
9598 * Loopback DQS Shift
9599 * PSU_DDR_PHY_DX8SL1OSC_LBDQSS 0x0
9601 * PHY High-Speed Reset
9602 * PSU_DDR_PHY_DX8SL1OSC_PHYHRST 0x1
9605 * PSU_DDR_PHY_DX8SL1OSC_PHYFRST 0x1
9607 * Delay Line Test Start
9608 * PSU_DDR_PHY_DX8SL1OSC_DLTST 0x0
9610 * Delay Line Test Mode
9611 * PSU_DDR_PHY_DX8SL1OSC_DLTMODE 0x0
9613 * Reserved. Caution, do not write to this register field.
9614 * PSU_DDR_PHY_DX8SL1OSC_RESERVED_12_11 0x3
9616 * Oscillator Mode Write-Data Delay Line Select
9617 * PSU_DDR_PHY_DX8SL1OSC_OSCWDDL 0x3
9619 * Reserved. Caution, do not write to this register field.
9620 * PSU_DDR_PHY_DX8SL1OSC_RESERVED_8_7 0x3
9622 * Oscillator Mode Write-Leveling Delay Line Select
9623 * PSU_DDR_PHY_DX8SL1OSC_OSCWDL 0x3
9625 * Oscillator Mode Division
9626 * PSU_DDR_PHY_DX8SL1OSC_OSCDIV 0xf
9629 * PSU_DDR_PHY_DX8SL1OSC_OSCEN 0x0
9631 * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo
9632 * opback, and Gated Clock Control Register
9633 * (OFFSET, MASK, VALUE) (0XFD081440, 0xFFFFFFFFU ,0x2A019FFEU)
9635 PSU_Mask_Write(DDR_PHY_DX8SL1OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU);
9636 /*##################################################################### */
9639 * Register : DX8SL1PLLCR0 @ 0XFD081444
9642 * PSU_DDR_PHY_DX8SL1PLLCR0_PLLBYP 0x0
9645 * PSU_DDR_PHY_DX8SL1PLLCR0_PLLRST 0x0
9648 * PSU_DDR_PHY_DX8SL1PLLCR0_PLLPD 0x0
9650 * Reference Stop Mode
9651 * PSU_DDR_PHY_DX8SL1PLLCR0_RSTOPM 0x0
9653 * PLL Frequency Select
9654 * PSU_DDR_PHY_DX8SL1PLLCR0_FRQSEL 0x1
9657 * PSU_DDR_PHY_DX8SL1PLLCR0_RLOCKM 0x0
9659 * Charge Pump Proportional Current Control
9660 * PSU_DDR_PHY_DX8SL1PLLCR0_CPPC 0x8
9662 * Charge Pump Integrating Current Control
9663 * PSU_DDR_PHY_DX8SL1PLLCR0_CPIC 0x0
9666 * PSU_DDR_PHY_DX8SL1PLLCR0_GSHIFT 0x0
9668 * Reserved. Return zeroes on reads.
9669 * PSU_DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9 0x0
9671 * Analog Test Enable (ATOEN)
9672 * PSU_DDR_PHY_DX8SL1PLLCR0_ATOEN 0x0
9674 * Analog Test Control
9675 * PSU_DDR_PHY_DX8SL1PLLCR0_ATC 0x0
9677 * Digital Test Control
9678 * PSU_DDR_PHY_DX8SL1PLLCR0_DTC 0x0
9680 * DAXT8 0-1 PLL Control Register 0
9681 * (OFFSET, MASK, VALUE) (0XFD081444, 0xFFFFFFFFU ,0x01100000U)
9683 PSU_Mask_Write(DDR_PHY_DX8SL1PLLCR0_OFFSET,
9684 0xFFFFFFFFU, 0x01100000U);
9685 /*##################################################################### */
9688 * Register : DX8SL1DQSCTL @ 0XFD08145C
9690 * Reserved. Return zeroes on reads.
9691 * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25 0x0
9693 * Read Path Rise-to-Rise Mode
9694 * PSU_DDR_PHY_DX8SL1DQSCTL_RRRMODE 0x1
9696 * Reserved. Return zeroes on reads.
9697 * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22 0x0
9699 * Write Path Rise-to-Rise Mode
9700 * PSU_DDR_PHY_DX8SL1DQSCTL_WRRMODE 0x1
9702 * DQS Gate Extension
9703 * PSU_DDR_PHY_DX8SL1DQSCTL_DQSGX 0x0
9705 * Low Power PLL Power Down
9706 * PSU_DDR_PHY_DX8SL1DQSCTL_LPPLLPD 0x1
9708 * Low Power I/O Power Down
9709 * PSU_DDR_PHY_DX8SL1DQSCTL_LPIOPD 0x1
9711 * Reserved. Return zeroes on reads.
9712 * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15 0x0
9715 * PSU_DDR_PHY_DX8SL1DQSCTL_QSCNTEN 0x1
9717 * Unused DQ I/O Mode
9718 * PSU_DDR_PHY_DX8SL1DQSCTL_UDQIOM 0x0
9720 * Reserved. Return zeroes on reads.
9721 * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10 0x0
9724 * PSU_DDR_PHY_DX8SL1DQSCTL_DXSR 0x3
9727 * PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES 0x0
9730 * PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES 0x0
9732 * DATX8 0-1 DQS Control Register
9733 * (OFFSET, MASK, VALUE) (0XFD08145C, 0xFFFFFFFFU ,0x01264300U)
9735 PSU_Mask_Write(DDR_PHY_DX8SL1DQSCTL_OFFSET,
9736 0xFFFFFFFFU, 0x01264300U);
9737 /*##################################################################### */
9740 * Register : DX8SL1DXCTL2 @ 0XFD08146C
9742 * Reserved. Return zeroes on reads.
9743 * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24 0x0
9745 * Configurable Read Data Enable
9746 * PSU_DDR_PHY_DX8SL1DXCTL2_CRDEN 0x0
9748 * OX Extension during Post-amble
9749 * PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX 0x0
9751 * OE Extension during Pre-amble
9752 * PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX 0x1
9754 * Reserved. Return zeroes on reads.
9755 * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17 0x0
9757 * I/O Assisted Gate Select
9758 * PSU_DDR_PHY_DX8SL1DXCTL2_IOAG 0x0
9760 * I/O Loopback Select
9761 * PSU_DDR_PHY_DX8SL1DXCTL2_IOLB 0x0
9763 * Reserved. Return zeroes on reads.
9764 * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13 0x0
9766 * Low Power Wakeup Threshold
9767 * PSU_DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH 0xc
9769 * Read Data Bus Inversion Enable
9770 * PSU_DDR_PHY_DX8SL1DXCTL2_RDBI 0x0
9772 * Write Data Bus Inversion Enable
9773 * PSU_DDR_PHY_DX8SL1DXCTL2_WDBI 0x0
9775 * PUB Read FIFO Bypass
9776 * PSU_DDR_PHY_DX8SL1DXCTL2_PRFBYP 0x0
9778 * DATX8 Receive FIFO Read Mode
9779 * PSU_DDR_PHY_DX8SL1DXCTL2_RDMODE 0x0
9781 * Disables the Read FIFO Reset
9782 * PSU_DDR_PHY_DX8SL1DXCTL2_DISRST 0x0
9784 * Read DQS Gate I/O Loopback
9785 * PSU_DDR_PHY_DX8SL1DXCTL2_DQSGLB 0x0
9787 * Reserved. Return zeroes on reads.
9788 * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0 0x0
9790 * DATX8 0-1 DX Control Register 2
9791 * (OFFSET, MASK, VALUE) (0XFD08146C, 0xFFFFFFFFU ,0x00041800U)
9793 PSU_Mask_Write(DDR_PHY_DX8SL1DXCTL2_OFFSET,
9794 0xFFFFFFFFU, 0x00041800U);
9795 /*##################################################################### */
9798 * Register : DX8SL1IOCR @ 0XFD081470
9800 * Reserved. Return zeroes on reads.
9801 * PSU_DDR_PHY_DX8SL1IOCR_RESERVED_31 0x0
9803 * PVREF_DAC REFSEL range select
9804 * PSU_DDR_PHY_DX8SL1IOCR_DXDACRANGE 0x7
9806 * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
9807 * PSU_DDR_PHY_DX8SL1IOCR_DXVREFIOM 0x0
9810 * PSU_DDR_PHY_DX8SL1IOCR_DXIOM 0x2
9812 * DX IO Transmitter Mode
9813 * PSU_DDR_PHY_DX8SL1IOCR_DXTXM 0x0
9815 * DX IO Receiver Mode
9816 * PSU_DDR_PHY_DX8SL1IOCR_DXRXM 0x0
9818 * DATX8 0-1 I/O Configuration Register
9819 * (OFFSET, MASK, VALUE) (0XFD081470, 0xFFFFFFFFU ,0x70800000U)
9821 PSU_Mask_Write(DDR_PHY_DX8SL1IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U);
9822 /*##################################################################### */
9825 * Register : DX8SL2OSC @ 0XFD081480
9827 * Reserved. Return zeroes on reads.
9828 * PSU_DDR_PHY_DX8SL2OSC_RESERVED_31_30 0x0
9830 * Enable Clock Gating for DX ddr_clk
9831 * PSU_DDR_PHY_DX8SL2OSC_GATEDXRDCLK 0x2
9833 * Enable Clock Gating for DX ctl_rd_clk
9834 * PSU_DDR_PHY_DX8SL2OSC_GATEDXDDRCLK 0x2
9836 * Enable Clock Gating for DX ctl_clk
9837 * PSU_DDR_PHY_DX8SL2OSC_GATEDXCTLCLK 0x2
9839 * Selects the level to which clocks will be stalled when clock gating is e
9841 * PSU_DDR_PHY_DX8SL2OSC_CLKLEVEL 0x0
9844 * PSU_DDR_PHY_DX8SL2OSC_LBMODE 0x0
9846 * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
9847 * PSU_DDR_PHY_DX8SL2OSC_LBGSDQS 0x0
9849 * Loopback DQS Gating
9850 * PSU_DDR_PHY_DX8SL2OSC_LBGDQS 0x0
9852 * Loopback DQS Shift
9853 * PSU_DDR_PHY_DX8SL2OSC_LBDQSS 0x0
9855 * PHY High-Speed Reset
9856 * PSU_DDR_PHY_DX8SL2OSC_PHYHRST 0x1
9859 * PSU_DDR_PHY_DX8SL2OSC_PHYFRST 0x1
9861 * Delay Line Test Start
9862 * PSU_DDR_PHY_DX8SL2OSC_DLTST 0x0
9864 * Delay Line Test Mode
9865 * PSU_DDR_PHY_DX8SL2OSC_DLTMODE 0x0
9867 * Reserved. Caution, do not write to this register field.
9868 * PSU_DDR_PHY_DX8SL2OSC_RESERVED_12_11 0x3
9870 * Oscillator Mode Write-Data Delay Line Select
9871 * PSU_DDR_PHY_DX8SL2OSC_OSCWDDL 0x3
9873 * Reserved. Caution, do not write to this register field.
9874 * PSU_DDR_PHY_DX8SL2OSC_RESERVED_8_7 0x3
9876 * Oscillator Mode Write-Leveling Delay Line Select
9877 * PSU_DDR_PHY_DX8SL2OSC_OSCWDL 0x3
9879 * Oscillator Mode Division
9880 * PSU_DDR_PHY_DX8SL2OSC_OSCDIV 0xf
9883 * PSU_DDR_PHY_DX8SL2OSC_OSCEN 0x0
9885 * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo
9886 * opback, and Gated Clock Control Register
9887 * (OFFSET, MASK, VALUE) (0XFD081480, 0xFFFFFFFFU ,0x2A019FFEU)
9889 PSU_Mask_Write(DDR_PHY_DX8SL2OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU);
9890 /*##################################################################### */
9893 * Register : DX8SL2PLLCR0 @ 0XFD081484
9896 * PSU_DDR_PHY_DX8SL2PLLCR0_PLLBYP 0x0
9899 * PSU_DDR_PHY_DX8SL2PLLCR0_PLLRST 0x0
9902 * PSU_DDR_PHY_DX8SL2PLLCR0_PLLPD 0x0
9904 * Reference Stop Mode
9905 * PSU_DDR_PHY_DX8SL2PLLCR0_RSTOPM 0x0
9907 * PLL Frequency Select
9908 * PSU_DDR_PHY_DX8SL2PLLCR0_FRQSEL 0x1
9911 * PSU_DDR_PHY_DX8SL2PLLCR0_RLOCKM 0x0
9913 * Charge Pump Proportional Current Control
9914 * PSU_DDR_PHY_DX8SL2PLLCR0_CPPC 0x8
9916 * Charge Pump Integrating Current Control
9917 * PSU_DDR_PHY_DX8SL2PLLCR0_CPIC 0x0
9920 * PSU_DDR_PHY_DX8SL2PLLCR0_GSHIFT 0x0
9922 * Reserved. Return zeroes on reads.
9923 * PSU_DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9 0x0
9925 * Analog Test Enable (ATOEN)
9926 * PSU_DDR_PHY_DX8SL2PLLCR0_ATOEN 0x0
9928 * Analog Test Control
9929 * PSU_DDR_PHY_DX8SL2PLLCR0_ATC 0x0
9931 * Digital Test Control
9932 * PSU_DDR_PHY_DX8SL2PLLCR0_DTC 0x0
9934 * DAXT8 0-1 PLL Control Register 0
9935 * (OFFSET, MASK, VALUE) (0XFD081484, 0xFFFFFFFFU ,0x01100000U)
9937 PSU_Mask_Write(DDR_PHY_DX8SL2PLLCR0_OFFSET,
9938 0xFFFFFFFFU, 0x01100000U);
9939 /*##################################################################### */
9942 * Register : DX8SL2DQSCTL @ 0XFD08149C
9944 * Reserved. Return zeroes on reads.
9945 * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25 0x0
9947 * Read Path Rise-to-Rise Mode
9948 * PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE 0x1
9950 * Reserved. Return zeroes on reads.
9951 * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22 0x0
9953 * Write Path Rise-to-Rise Mode
9954 * PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE 0x1
9956 * DQS Gate Extension
9957 * PSU_DDR_PHY_DX8SL2DQSCTL_DQSGX 0x0
9959 * Low Power PLL Power Down
9960 * PSU_DDR_PHY_DX8SL2DQSCTL_LPPLLPD 0x1
9962 * Low Power I/O Power Down
9963 * PSU_DDR_PHY_DX8SL2DQSCTL_LPIOPD 0x1
9965 * Reserved. Return zeroes on reads.
9966 * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15 0x0
9969 * PSU_DDR_PHY_DX8SL2DQSCTL_QSCNTEN 0x1
9971 * Unused DQ I/O Mode
9972 * PSU_DDR_PHY_DX8SL2DQSCTL_UDQIOM 0x0
9974 * Reserved. Return zeroes on reads.
9975 * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10 0x0
9978 * PSU_DDR_PHY_DX8SL2DQSCTL_DXSR 0x3
9981 * PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES 0x0
9984 * PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES 0x0
9986 * DATX8 0-1 DQS Control Register
9987 * (OFFSET, MASK, VALUE) (0XFD08149C, 0xFFFFFFFFU ,0x01264300U)
9989 PSU_Mask_Write(DDR_PHY_DX8SL2DQSCTL_OFFSET,
9990 0xFFFFFFFFU, 0x01264300U);
9991 /*##################################################################### */
9994 * Register : DX8SL2DXCTL2 @ 0XFD0814AC
9996 * Reserved. Return zeroes on reads.
9997 * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24 0x0
9999 * Configurable Read Data Enable
10000 * PSU_DDR_PHY_DX8SL2DXCTL2_CRDEN 0x0
10002 * OX Extension during Post-amble
10003 * PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX 0x0
10005 * OE Extension during Pre-amble
10006 * PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX 0x1
10008 * Reserved. Return zeroes on reads.
10009 * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17 0x0
10011 * I/O Assisted Gate Select
10012 * PSU_DDR_PHY_DX8SL2DXCTL2_IOAG 0x0
10014 * I/O Loopback Select
10015 * PSU_DDR_PHY_DX8SL2DXCTL2_IOLB 0x0
10017 * Reserved. Return zeroes on reads.
10018 * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13 0x0
10020 * Low Power Wakeup Threshold
10021 * PSU_DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH 0xc
10023 * Read Data Bus Inversion Enable
10024 * PSU_DDR_PHY_DX8SL2DXCTL2_RDBI 0x0
10026 * Write Data Bus Inversion Enable
10027 * PSU_DDR_PHY_DX8SL2DXCTL2_WDBI 0x0
10029 * PUB Read FIFO Bypass
10030 * PSU_DDR_PHY_DX8SL2DXCTL2_PRFBYP 0x0
10032 * DATX8 Receive FIFO Read Mode
10033 * PSU_DDR_PHY_DX8SL2DXCTL2_RDMODE 0x0
10035 * Disables the Read FIFO Reset
10036 * PSU_DDR_PHY_DX8SL2DXCTL2_DISRST 0x0
10038 * Read DQS Gate I/O Loopback
10039 * PSU_DDR_PHY_DX8SL2DXCTL2_DQSGLB 0x0
10041 * Reserved. Return zeroes on reads.
10042 * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0 0x0
10044 * DATX8 0-1 DX Control Register 2
10045 * (OFFSET, MASK, VALUE) (0XFD0814AC, 0xFFFFFFFFU ,0x00041800U)
10047 PSU_Mask_Write(DDR_PHY_DX8SL2DXCTL2_OFFSET,
10048 0xFFFFFFFFU, 0x00041800U);
10049 /*##################################################################### */
10052 * Register : DX8SL2IOCR @ 0XFD0814B0
10054 * Reserved. Return zeroes on reads.
10055 * PSU_DDR_PHY_DX8SL2IOCR_RESERVED_31 0x0
10057 * PVREF_DAC REFSEL range select
10058 * PSU_DDR_PHY_DX8SL2IOCR_DXDACRANGE 0x7
10060 * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
10061 * PSU_DDR_PHY_DX8SL2IOCR_DXVREFIOM 0x0
10064 * PSU_DDR_PHY_DX8SL2IOCR_DXIOM 0x2
10066 * DX IO Transmitter Mode
10067 * PSU_DDR_PHY_DX8SL2IOCR_DXTXM 0x0
10069 * DX IO Receiver Mode
10070 * PSU_DDR_PHY_DX8SL2IOCR_DXRXM 0x0
10072 * DATX8 0-1 I/O Configuration Register
10073 * (OFFSET, MASK, VALUE) (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U)
10075 PSU_Mask_Write(DDR_PHY_DX8SL2IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U);
10076 /*##################################################################### */
10079 * Register : DX8SL3OSC @ 0XFD0814C0
10081 * Reserved. Return zeroes on reads.
10082 * PSU_DDR_PHY_DX8SL3OSC_RESERVED_31_30 0x0
10084 * Enable Clock Gating for DX ddr_clk
10085 * PSU_DDR_PHY_DX8SL3OSC_GATEDXRDCLK 0x2
10087 * Enable Clock Gating for DX ctl_rd_clk
10088 * PSU_DDR_PHY_DX8SL3OSC_GATEDXDDRCLK 0x2
10090 * Enable Clock Gating for DX ctl_clk
10091 * PSU_DDR_PHY_DX8SL3OSC_GATEDXCTLCLK 0x2
10093 * Selects the level to which clocks will be stalled when clock gating is e
10095 * PSU_DDR_PHY_DX8SL3OSC_CLKLEVEL 0x0
10098 * PSU_DDR_PHY_DX8SL3OSC_LBMODE 0x0
10100 * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
10101 * PSU_DDR_PHY_DX8SL3OSC_LBGSDQS 0x0
10103 * Loopback DQS Gating
10104 * PSU_DDR_PHY_DX8SL3OSC_LBGDQS 0x0
10106 * Loopback DQS Shift
10107 * PSU_DDR_PHY_DX8SL3OSC_LBDQSS 0x0
10109 * PHY High-Speed Reset
10110 * PSU_DDR_PHY_DX8SL3OSC_PHYHRST 0x1
10113 * PSU_DDR_PHY_DX8SL3OSC_PHYFRST 0x1
10115 * Delay Line Test Start
10116 * PSU_DDR_PHY_DX8SL3OSC_DLTST 0x0
10118 * Delay Line Test Mode
10119 * PSU_DDR_PHY_DX8SL3OSC_DLTMODE 0x0
10121 * Reserved. Caution, do not write to this register field.
10122 * PSU_DDR_PHY_DX8SL3OSC_RESERVED_12_11 0x3
10124 * Oscillator Mode Write-Data Delay Line Select
10125 * PSU_DDR_PHY_DX8SL3OSC_OSCWDDL 0x3
10127 * Reserved. Caution, do not write to this register field.
10128 * PSU_DDR_PHY_DX8SL3OSC_RESERVED_8_7 0x3
10130 * Oscillator Mode Write-Leveling Delay Line Select
10131 * PSU_DDR_PHY_DX8SL3OSC_OSCWDL 0x3
10133 * Oscillator Mode Division
10134 * PSU_DDR_PHY_DX8SL3OSC_OSCDIV 0xf
10136 * Oscillator Enable
10137 * PSU_DDR_PHY_DX8SL3OSC_OSCEN 0x0
10139 * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo
10140 * opback, and Gated Clock Control Register
10141 * (OFFSET, MASK, VALUE) (0XFD0814C0, 0xFFFFFFFFU ,0x2A019FFEU)
10143 PSU_Mask_Write(DDR_PHY_DX8SL3OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU);
10144 /*##################################################################### */
10147 * Register : DX8SL3PLLCR0 @ 0XFD0814C4
10150 * PSU_DDR_PHY_DX8SL3PLLCR0_PLLBYP 0x0
10153 * PSU_DDR_PHY_DX8SL3PLLCR0_PLLRST 0x0
10156 * PSU_DDR_PHY_DX8SL3PLLCR0_PLLPD 0x0
10158 * Reference Stop Mode
10159 * PSU_DDR_PHY_DX8SL3PLLCR0_RSTOPM 0x0
10161 * PLL Frequency Select
10162 * PSU_DDR_PHY_DX8SL3PLLCR0_FRQSEL 0x1
10165 * PSU_DDR_PHY_DX8SL3PLLCR0_RLOCKM 0x0
10167 * Charge Pump Proportional Current Control
10168 * PSU_DDR_PHY_DX8SL3PLLCR0_CPPC 0x8
10170 * Charge Pump Integrating Current Control
10171 * PSU_DDR_PHY_DX8SL3PLLCR0_CPIC 0x0
10174 * PSU_DDR_PHY_DX8SL3PLLCR0_GSHIFT 0x0
10176 * Reserved. Return zeroes on reads.
10177 * PSU_DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9 0x0
10179 * Analog Test Enable (ATOEN)
10180 * PSU_DDR_PHY_DX8SL3PLLCR0_ATOEN 0x0
10182 * Analog Test Control
10183 * PSU_DDR_PHY_DX8SL3PLLCR0_ATC 0x0
10185 * Digital Test Control
10186 * PSU_DDR_PHY_DX8SL3PLLCR0_DTC 0x0
10188 * DAXT8 0-1 PLL Control Register 0
10189 * (OFFSET, MASK, VALUE) (0XFD0814C4, 0xFFFFFFFFU ,0x01100000U)
10191 PSU_Mask_Write(DDR_PHY_DX8SL3PLLCR0_OFFSET,
10192 0xFFFFFFFFU, 0x01100000U);
10193 /*##################################################################### */
10196 * Register : DX8SL3DQSCTL @ 0XFD0814DC
10198 * Reserved. Return zeroes on reads.
10199 * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25 0x0
10201 * Read Path Rise-to-Rise Mode
10202 * PSU_DDR_PHY_DX8SL3DQSCTL_RRRMODE 0x1
10204 * Reserved. Return zeroes on reads.
10205 * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22 0x0
10207 * Write Path Rise-to-Rise Mode
10208 * PSU_DDR_PHY_DX8SL3DQSCTL_WRRMODE 0x1
10210 * DQS Gate Extension
10211 * PSU_DDR_PHY_DX8SL3DQSCTL_DQSGX 0x0
10213 * Low Power PLL Power Down
10214 * PSU_DDR_PHY_DX8SL3DQSCTL_LPPLLPD 0x1
10216 * Low Power I/O Power Down
10217 * PSU_DDR_PHY_DX8SL3DQSCTL_LPIOPD 0x1
10219 * Reserved. Return zeroes on reads.
10220 * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15 0x0
10222 * QS Counter Enable
10223 * PSU_DDR_PHY_DX8SL3DQSCTL_QSCNTEN 0x1
10225 * Unused DQ I/O Mode
10226 * PSU_DDR_PHY_DX8SL3DQSCTL_UDQIOM 0x0
10228 * Reserved. Return zeroes on reads.
10229 * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10 0x0
10232 * PSU_DDR_PHY_DX8SL3DQSCTL_DXSR 0x3
10235 * PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES 0x0
10238 * PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES 0x0
10240 * DATX8 0-1 DQS Control Register
10241 * (OFFSET, MASK, VALUE) (0XFD0814DC, 0xFFFFFFFFU ,0x01264300U)
10243 PSU_Mask_Write(DDR_PHY_DX8SL3DQSCTL_OFFSET,
10244 0xFFFFFFFFU, 0x01264300U);
10245 /*##################################################################### */
10248 * Register : DX8SL3DXCTL2 @ 0XFD0814EC
10250 * Reserved. Return zeroes on reads.
10251 * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24 0x0
10253 * Configurable Read Data Enable
10254 * PSU_DDR_PHY_DX8SL3DXCTL2_CRDEN 0x0
10256 * OX Extension during Post-amble
10257 * PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX 0x0
10259 * OE Extension during Pre-amble
10260 * PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX 0x1
10262 * Reserved. Return zeroes on reads.
10263 * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17 0x0
10265 * I/O Assisted Gate Select
10266 * PSU_DDR_PHY_DX8SL3DXCTL2_IOAG 0x0
10268 * I/O Loopback Select
10269 * PSU_DDR_PHY_DX8SL3DXCTL2_IOLB 0x0
10271 * Reserved. Return zeroes on reads.
10272 * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13 0x0
10274 * Low Power Wakeup Threshold
10275 * PSU_DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH 0xc
10277 * Read Data Bus Inversion Enable
10278 * PSU_DDR_PHY_DX8SL3DXCTL2_RDBI 0x0
10280 * Write Data Bus Inversion Enable
10281 * PSU_DDR_PHY_DX8SL3DXCTL2_WDBI 0x0
10283 * PUB Read FIFO Bypass
10284 * PSU_DDR_PHY_DX8SL3DXCTL2_PRFBYP 0x0
10286 * DATX8 Receive FIFO Read Mode
10287 * PSU_DDR_PHY_DX8SL3DXCTL2_RDMODE 0x0
10289 * Disables the Read FIFO Reset
10290 * PSU_DDR_PHY_DX8SL3DXCTL2_DISRST 0x0
10292 * Read DQS Gate I/O Loopback
10293 * PSU_DDR_PHY_DX8SL3DXCTL2_DQSGLB 0x0
10295 * Reserved. Return zeroes on reads.
10296 * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0 0x0
10298 * DATX8 0-1 DX Control Register 2
10299 * (OFFSET, MASK, VALUE) (0XFD0814EC, 0xFFFFFFFFU ,0x00041800U)
10301 PSU_Mask_Write(DDR_PHY_DX8SL3DXCTL2_OFFSET,
10302 0xFFFFFFFFU, 0x00041800U);
10303 /*##################################################################### */
10306 * Register : DX8SL3IOCR @ 0XFD0814F0
10308 * Reserved. Return zeroes on reads.
10309 * PSU_DDR_PHY_DX8SL3IOCR_RESERVED_31 0x0
10311 * PVREF_DAC REFSEL range select
10312 * PSU_DDR_PHY_DX8SL3IOCR_DXDACRANGE 0x7
10314 * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
10315 * PSU_DDR_PHY_DX8SL3IOCR_DXVREFIOM 0x0
10318 * PSU_DDR_PHY_DX8SL3IOCR_DXIOM 0x2
10320 * DX IO Transmitter Mode
10321 * PSU_DDR_PHY_DX8SL3IOCR_DXTXM 0x0
10323 * DX IO Receiver Mode
10324 * PSU_DDR_PHY_DX8SL3IOCR_DXRXM 0x0
10326 * DATX8 0-1 I/O Configuration Register
10327 * (OFFSET, MASK, VALUE) (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U)
10329 PSU_Mask_Write(DDR_PHY_DX8SL3IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U);
10330 /*##################################################################### */
10333 * Register : DX8SL4OSC @ 0XFD081500
10335 * Reserved. Return zeroes on reads.
10336 * PSU_DDR_PHY_DX8SL4OSC_RESERVED_31_30 0x0
10338 * Enable Clock Gating for DX ddr_clk
10339 * PSU_DDR_PHY_DX8SL4OSC_GATEDXRDCLK 0x2
10341 * Enable Clock Gating for DX ctl_rd_clk
10342 * PSU_DDR_PHY_DX8SL4OSC_GATEDXDDRCLK 0x2
10344 * Enable Clock Gating for DX ctl_clk
10345 * PSU_DDR_PHY_DX8SL4OSC_GATEDXCTLCLK 0x2
10347 * Selects the level to which clocks will be stalled when clock gating is e
10349 * PSU_DDR_PHY_DX8SL4OSC_CLKLEVEL 0x0
10352 * PSU_DDR_PHY_DX8SL4OSC_LBMODE 0x0
10354 * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
10355 * PSU_DDR_PHY_DX8SL4OSC_LBGSDQS 0x0
10357 * Loopback DQS Gating
10358 * PSU_DDR_PHY_DX8SL4OSC_LBGDQS 0x0
10360 * Loopback DQS Shift
10361 * PSU_DDR_PHY_DX8SL4OSC_LBDQSS 0x0
10363 * PHY High-Speed Reset
10364 * PSU_DDR_PHY_DX8SL4OSC_PHYHRST 0x1
10367 * PSU_DDR_PHY_DX8SL4OSC_PHYFRST 0x1
10369 * Delay Line Test Start
10370 * PSU_DDR_PHY_DX8SL4OSC_DLTST 0x0
10372 * Delay Line Test Mode
10373 * PSU_DDR_PHY_DX8SL4OSC_DLTMODE 0x0
10375 * Reserved. Caution, do not write to this register field.
10376 * PSU_DDR_PHY_DX8SL4OSC_RESERVED_12_11 0x3
10378 * Oscillator Mode Write-Data Delay Line Select
10379 * PSU_DDR_PHY_DX8SL4OSC_OSCWDDL 0x3
10381 * Reserved. Caution, do not write to this register field.
10382 * PSU_DDR_PHY_DX8SL4OSC_RESERVED_8_7 0x3
10384 * Oscillator Mode Write-Leveling Delay Line Select
10385 * PSU_DDR_PHY_DX8SL4OSC_OSCWDL 0x3
10387 * Oscillator Mode Division
10388 * PSU_DDR_PHY_DX8SL4OSC_OSCDIV 0xf
10390 * Oscillator Enable
10391 * PSU_DDR_PHY_DX8SL4OSC_OSCEN 0x0
10393 * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo
10394 * opback, and Gated Clock Control Register
10395 * (OFFSET, MASK, VALUE) (0XFD081500, 0xFFFFFFFFU ,0x2A019FFEU)
10397 PSU_Mask_Write(DDR_PHY_DX8SL4OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU);
10398 /*##################################################################### */
10401 * Register : DX8SL4PLLCR0 @ 0XFD081504
10404 * PSU_DDR_PHY_DX8SL4PLLCR0_PLLBYP 0x0
10407 * PSU_DDR_PHY_DX8SL4PLLCR0_PLLRST 0x0
10410 * PSU_DDR_PHY_DX8SL4PLLCR0_PLLPD 0x0
10412 * Reference Stop Mode
10413 * PSU_DDR_PHY_DX8SL4PLLCR0_RSTOPM 0x0
10415 * PLL Frequency Select
10416 * PSU_DDR_PHY_DX8SL4PLLCR0_FRQSEL 0x1
10419 * PSU_DDR_PHY_DX8SL4PLLCR0_RLOCKM 0x0
10421 * Charge Pump Proportional Current Control
10422 * PSU_DDR_PHY_DX8SL4PLLCR0_CPPC 0x8
10424 * Charge Pump Integrating Current Control
10425 * PSU_DDR_PHY_DX8SL4PLLCR0_CPIC 0x0
10428 * PSU_DDR_PHY_DX8SL4PLLCR0_GSHIFT 0x0
10430 * Reserved. Return zeroes on reads.
10431 * PSU_DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9 0x0
10433 * Analog Test Enable (ATOEN)
10434 * PSU_DDR_PHY_DX8SL4PLLCR0_ATOEN 0x0
10436 * Analog Test Control
10437 * PSU_DDR_PHY_DX8SL4PLLCR0_ATC 0x0
10439 * Digital Test Control
10440 * PSU_DDR_PHY_DX8SL4PLLCR0_DTC 0x0
10442 * DAXT8 0-1 PLL Control Register 0
10443 * (OFFSET, MASK, VALUE) (0XFD081504, 0xFFFFFFFFU ,0x01100000U)
10445 PSU_Mask_Write(DDR_PHY_DX8SL4PLLCR0_OFFSET,
10446 0xFFFFFFFFU, 0x01100000U);
10447 /*##################################################################### */
10450 * Register : DX8SL4DQSCTL @ 0XFD08151C
10452 * Reserved. Return zeroes on reads.
10453 * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25 0x0
10455 * Read Path Rise-to-Rise Mode
10456 * PSU_DDR_PHY_DX8SL4DQSCTL_RRRMODE 0x1
10458 * Reserved. Return zeroes on reads.
10459 * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22 0x0
10461 * Write Path Rise-to-Rise Mode
10462 * PSU_DDR_PHY_DX8SL4DQSCTL_WRRMODE 0x1
10464 * DQS Gate Extension
10465 * PSU_DDR_PHY_DX8SL4DQSCTL_DQSGX 0x0
10467 * Low Power PLL Power Down
10468 * PSU_DDR_PHY_DX8SL4DQSCTL_LPPLLPD 0x1
10470 * Low Power I/O Power Down
10471 * PSU_DDR_PHY_DX8SL4DQSCTL_LPIOPD 0x1
10473 * Reserved. Return zeroes on reads.
10474 * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15 0x0
10476 * QS Counter Enable
10477 * PSU_DDR_PHY_DX8SL4DQSCTL_QSCNTEN 0x1
10479 * Unused DQ I/O Mode
10480 * PSU_DDR_PHY_DX8SL4DQSCTL_UDQIOM 0x0
10482 * Reserved. Return zeroes on reads.
10483 * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10 0x0
10486 * PSU_DDR_PHY_DX8SL4DQSCTL_DXSR 0x3
10489 * PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES 0x0
10492 * PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES 0x0
10494 * DATX8 0-1 DQS Control Register
10495 * (OFFSET, MASK, VALUE) (0XFD08151C, 0xFFFFFFFFU ,0x01264300U)
10497 PSU_Mask_Write(DDR_PHY_DX8SL4DQSCTL_OFFSET,
10498 0xFFFFFFFFU, 0x01264300U);
10499 /*##################################################################### */
10502 * Register : DX8SL4DXCTL2 @ 0XFD08152C
10504 * Reserved. Return zeroes on reads.
10505 * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24 0x0
10507 * Configurable Read Data Enable
10508 * PSU_DDR_PHY_DX8SL4DXCTL2_CRDEN 0x0
10510 * OX Extension during Post-amble
10511 * PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX 0x0
10513 * OE Extension during Pre-amble
10514 * PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX 0x1
10516 * Reserved. Return zeroes on reads.
10517 * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17 0x0
10519 * I/O Assisted Gate Select
10520 * PSU_DDR_PHY_DX8SL4DXCTL2_IOAG 0x0
10522 * I/O Loopback Select
10523 * PSU_DDR_PHY_DX8SL4DXCTL2_IOLB 0x0
10525 * Reserved. Return zeroes on reads.
10526 * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13 0x0
10528 * Low Power Wakeup Threshold
10529 * PSU_DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH 0xc
10531 * Read Data Bus Inversion Enable
10532 * PSU_DDR_PHY_DX8SL4DXCTL2_RDBI 0x0
10534 * Write Data Bus Inversion Enable
10535 * PSU_DDR_PHY_DX8SL4DXCTL2_WDBI 0x0
10537 * PUB Read FIFO Bypass
10538 * PSU_DDR_PHY_DX8SL4DXCTL2_PRFBYP 0x0
10540 * DATX8 Receive FIFO Read Mode
10541 * PSU_DDR_PHY_DX8SL4DXCTL2_RDMODE 0x0
10543 * Disables the Read FIFO Reset
10544 * PSU_DDR_PHY_DX8SL4DXCTL2_DISRST 0x0
10546 * Read DQS Gate I/O Loopback
10547 * PSU_DDR_PHY_DX8SL4DXCTL2_DQSGLB 0x0
10549 * Reserved. Return zeroes on reads.
10550 * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0 0x0
10552 * DATX8 0-1 DX Control Register 2
10553 * (OFFSET, MASK, VALUE) (0XFD08152C, 0xFFFFFFFFU ,0x00041800U)
10555 PSU_Mask_Write(DDR_PHY_DX8SL4DXCTL2_OFFSET,
10556 0xFFFFFFFFU, 0x00041800U);
10557 /*##################################################################### */
10560 * Register : DX8SL4IOCR @ 0XFD081530
10562 * Reserved. Return zeroes on reads.
10563 * PSU_DDR_PHY_DX8SL4IOCR_RESERVED_31 0x0
10565 * PVREF_DAC REFSEL range select
10566 * PSU_DDR_PHY_DX8SL4IOCR_DXDACRANGE 0x7
10568 * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
10569 * PSU_DDR_PHY_DX8SL4IOCR_DXVREFIOM 0x0
10572 * PSU_DDR_PHY_DX8SL4IOCR_DXIOM 0x2
10574 * DX IO Transmitter Mode
10575 * PSU_DDR_PHY_DX8SL4IOCR_DXTXM 0x0
10577 * DX IO Receiver Mode
10578 * PSU_DDR_PHY_DX8SL4IOCR_DXRXM 0x0
10580 * DATX8 0-1 I/O Configuration Register
10581 * (OFFSET, MASK, VALUE) (0XFD081530, 0xFFFFFFFFU ,0x70800000U)
10583 PSU_Mask_Write(DDR_PHY_DX8SL4IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U);
10584 /*##################################################################### */
10587 * Register : DX8SLbPLLCR0 @ 0XFD0817C4
10590 * PSU_DDR_PHY_DX8SLBPLLCR0_PLLBYP 0x0
10593 * PSU_DDR_PHY_DX8SLBPLLCR0_PLLRST 0x0
10596 * PSU_DDR_PHY_DX8SLBPLLCR0_PLLPD 0x0
10598 * Reference Stop Mode
10599 * PSU_DDR_PHY_DX8SLBPLLCR0_RSTOPM 0x0
10601 * PLL Frequency Select
10602 * PSU_DDR_PHY_DX8SLBPLLCR0_FRQSEL 0x1
10605 * PSU_DDR_PHY_DX8SLBPLLCR0_RLOCKM 0x0
10607 * Charge Pump Proportional Current Control
10608 * PSU_DDR_PHY_DX8SLBPLLCR0_CPPC 0x8
10610 * Charge Pump Integrating Current Control
10611 * PSU_DDR_PHY_DX8SLBPLLCR0_CPIC 0x0
10614 * PSU_DDR_PHY_DX8SLBPLLCR0_GSHIFT 0x0
10616 * Reserved. Return zeroes on reads.
10617 * PSU_DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9 0x0
10619 * Analog Test Enable (ATOEN)
10620 * PSU_DDR_PHY_DX8SLBPLLCR0_ATOEN 0x0
10622 * Analog Test Control
10623 * PSU_DDR_PHY_DX8SLBPLLCR0_ATC 0x0
10625 * Digital Test Control
10626 * PSU_DDR_PHY_DX8SLBPLLCR0_DTC 0x0
10628 * DAXT8 0-8 PLL Control Register 0
10629 * (OFFSET, MASK, VALUE) (0XFD0817C4, 0xFFFFFFFFU ,0x01100000U)
10631 PSU_Mask_Write(DDR_PHY_DX8SLBPLLCR0_OFFSET,
10632 0xFFFFFFFFU, 0x01100000U);
10633 /*##################################################################### */
10636 * Register : DX8SLbDQSCTL @ 0XFD0817DC
10638 * Reserved. Return zeroes on reads.
10639 * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25 0x0
10641 * Read Path Rise-to-Rise Mode
10642 * PSU_DDR_PHY_DX8SLBDQSCTL_RRRMODE 0x1
10644 * Reserved. Return zeroes on reads.
10645 * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22 0x0
10647 * Write Path Rise-to-Rise Mode
10648 * PSU_DDR_PHY_DX8SLBDQSCTL_WRRMODE 0x1
10650 * DQS Gate Extension
10651 * PSU_DDR_PHY_DX8SLBDQSCTL_DQSGX 0x0
10653 * Low Power PLL Power Down
10654 * PSU_DDR_PHY_DX8SLBDQSCTL_LPPLLPD 0x1
10656 * Low Power I/O Power Down
10657 * PSU_DDR_PHY_DX8SLBDQSCTL_LPIOPD 0x1
10659 * Reserved. Return zeroes on reads.
10660 * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15 0x0
10662 * QS Counter Enable
10663 * PSU_DDR_PHY_DX8SLBDQSCTL_QSCNTEN 0x1
10665 * Unused DQ I/O Mode
10666 * PSU_DDR_PHY_DX8SLBDQSCTL_UDQIOM 0x0
10668 * Reserved. Return zeroes on reads.
10669 * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10 0x0
10672 * PSU_DDR_PHY_DX8SLBDQSCTL_DXSR 0x3
10675 * PSU_DDR_PHY_DX8SLBDQSCTL_DQSNRES 0xc
10678 * PSU_DDR_PHY_DX8SLBDQSCTL_DQSRES 0x4
10680 * DATX8 0-8 DQS Control Register
10681 * (OFFSET, MASK, VALUE) (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U)
10683 PSU_Mask_Write(DDR_PHY_DX8SLBDQSCTL_OFFSET,
10684 0xFFFFFFFFU, 0x012643C4U);
10685 /*##################################################################### */
10690 unsigned long psu_ddr_qos_init_data(void)
10695 unsigned long psu_mio_init_data(void)
10701 * Register : MIO_PIN_0 @ 0XFF180000
10703 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out-
10705 * PSU_IOU_SLCR_MIO_PIN_0_L0_SEL 1
10707 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10708 * PSU_IOU_SLCR_MIO_PIN_0_L1_SEL 0
10710 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
10711 * , test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0
10712 * ]- (Test Scan Port) 3= Not Used
10713 * PSU_IOU_SLCR_MIO_PIN_0_L2_SEL 0
10715 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= g
10716 * pio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy
10717 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
10718 * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
10719 * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc
10720 * lk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Out
10721 * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c
10722 * lk- (Trace Port Clock)
10723 * PSU_IOU_SLCR_MIO_PIN_0_L3_SEL 0
10725 * Configures MIO Pin 0 peripheral interface mapping. S
10726 * (OFFSET, MASK, VALUE) (0XFF180000, 0x000000FEU ,0x00000002U)
10728 PSU_Mask_Write(IOU_SLCR_MIO_PIN_0_OFFSET, 0x000000FEU, 0x00000002U);
10729 /*##################################################################### */
10732 * Register : MIO_PIN_1 @ 0XFF180004
10734 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (Q
10735 * SPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus)
10736 * PSU_IOU_SLCR_MIO_PIN_1_L0_SEL 1
10738 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10739 * PSU_IOU_SLCR_MIO_PIN_1_L1_SEL 0
10741 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
10742 * , test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1
10743 * ]- (Test Scan Port) 3= Not Used
10744 * PSU_IOU_SLCR_MIO_PIN_1_L2_SEL 0
10746 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= g
10747 * pio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_
10748 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
10749 * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
10750 * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Ou
10751 * tput, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART
10752 * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
10754 * PSU_IOU_SLCR_MIO_PIN_1_L3_SEL 0
10756 * Configures MIO Pin 1 peripheral interface mapping
10757 * (OFFSET, MASK, VALUE) (0XFF180004, 0x000000FEU ,0x00000002U)
10759 PSU_Mask_Write(IOU_SLCR_MIO_PIN_1_OFFSET, 0x000000FEU, 0x00000002U);
10760 /*##################################################################### */
10763 * Register : MIO_PIN_2 @ 0XFF180008
10765 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI
10766 * Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)
10767 * PSU_IOU_SLCR_MIO_PIN_2_L0_SEL 1
10769 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10770 * PSU_IOU_SLCR_MIO_PIN_2_L1_SEL 0
10772 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
10773 * , test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2
10774 * ]- (Test Scan Port) 3= Not Used
10775 * PSU_IOU_SLCR_MIO_PIN_2_L2_SEL 0
10777 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= g
10778 * pio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_
10779 * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
10780 * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG
10781 * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, I
10782 * nput, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se
10783 * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
10784 * PSU_IOU_SLCR_MIO_PIN_2_L3_SEL 0
10786 * Configures MIO Pin 2 peripheral interface mapping
10787 * (OFFSET, MASK, VALUE) (0XFF180008, 0x000000FEU ,0x00000002U)
10789 PSU_Mask_Write(IOU_SLCR_MIO_PIN_2_OFFSET, 0x000000FEU, 0x00000002U);
10790 /*##################################################################### */
10793 * Register : MIO_PIN_3 @ 0XFF18000C
10795 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI
10796 * Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)
10797 * PSU_IOU_SLCR_MIO_PIN_3_L0_SEL 1
10799 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10800 * PSU_IOU_SLCR_MIO_PIN_3_L1_SEL 0
10802 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
10803 * , test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3
10804 * ]- (Test Scan Port) 3= Not Used
10805 * PSU_IOU_SLCR_MIO_PIN_3_L2_SEL 0
10807 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= g
10808 * pio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy
10809 * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
10810 * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
10811 * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output
10812 * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out-
10813 * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
10814 * output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
10815 * PSU_IOU_SLCR_MIO_PIN_3_L3_SEL 0
10817 * Configures MIO Pin 3 peripheral interface mapping
10818 * (OFFSET, MASK, VALUE) (0XFF18000C, 0x000000FEU ,0x00000002U)
10820 PSU_Mask_Write(IOU_SLCR_MIO_PIN_3_OFFSET, 0x000000FEU, 0x00000002U);
10821 /*##################################################################### */
10824 * Register : MIO_PIN_4 @ 0XFF180010
10826 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (
10827 * QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus)
10828 * PSU_IOU_SLCR_MIO_PIN_4_L0_SEL 1
10830 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10831 * PSU_IOU_SLCR_MIO_PIN_4_L1_SEL 0
10833 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
10834 * , test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4
10835 * ]- (Test Scan Port) 3= Not Used
10836 * PSU_IOU_SLCR_MIO_PIN_4_L2_SEL 0
10838 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= g
10839 * pio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy
10840 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
10841 * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa
10842 * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi
10843 * 0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cloc
10844 * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O
10845 * utput, tracedq[2]- (Trace Port Databus)
10846 * PSU_IOU_SLCR_MIO_PIN_4_L3_SEL 0
10848 * Configures MIO Pin 4 peripheral interface mapping
10849 * (OFFSET, MASK, VALUE) (0XFF180010, 0x000000FEU ,0x00000002U)
10851 PSU_Mask_Write(IOU_SLCR_MIO_PIN_4_OFFSET, 0x000000FEU, 0x00000002U);
10852 /*##################################################################### */
10855 * Register : MIO_PIN_5 @ 0XFF180014
10857 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out-
10858 * (QSPI Slave Select)
10859 * PSU_IOU_SLCR_MIO_PIN_5_L0_SEL 1
10861 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10862 * PSU_IOU_SLCR_MIO_PIN_5_L1_SEL 0
10864 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
10865 * , test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5
10866 * ]- (Test Scan Port) 3= Not Used
10867 * PSU_IOU_SLCR_MIO_PIN_5_L2_SEL 0
10869 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= g
10870 * pio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_
10871 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
10872 * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W
10873 * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4=
10874 * spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC
10875 * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7=
10876 * trace, Output, tracedq[3]- (Trace Port Databus)
10877 * PSU_IOU_SLCR_MIO_PIN_5_L3_SEL 0
10879 * Configures MIO Pin 5 peripheral interface mapping
10880 * (OFFSET, MASK, VALUE) (0XFF180014, 0x000000FEU ,0x00000002U)
10882 PSU_Mask_Write(IOU_SLCR_MIO_PIN_5_OFFSET, 0x000000FEU, 0x00000002U);
10883 /*##################################################################### */
10886 * Register : MIO_PIN_6 @ 0XFF180018
10888 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_l
10889 * pbk- (QSPI Clock to be fed-back)
10890 * PSU_IOU_SLCR_MIO_PIN_6_L0_SEL 1
10892 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10893 * PSU_IOU_SLCR_MIO_PIN_6_L1_SEL 0
10895 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
10896 * , test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6
10897 * ]- (Test Scan Port) 3= Not Used
10898 * PSU_IOU_SLCR_MIO_PIN_6_L2_SEL 0
10900 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= g
10901 * pio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_
10902 * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
10903 * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat
10904 * ch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= s
10905 * pi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TT
10906 * C Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
10907 * Output, tracedq[4]- (Trace Port Databus)
10908 * PSU_IOU_SLCR_MIO_PIN_6_L3_SEL 0
10910 * Configures MIO Pin 6 peripheral interface mapping
10911 * (OFFSET, MASK, VALUE) (0XFF180018, 0x000000FEU ,0x00000002U)
10913 PSU_Mask_Write(IOU_SLCR_MIO_PIN_6_OFFSET, 0x000000FEU, 0x00000002U);
10914 /*##################################################################### */
10917 * Register : MIO_PIN_7 @ 0XFF18001C
10919 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_
10920 * upper- (QSPI Slave Select upper)
10921 * PSU_IOU_SLCR_MIO_PIN_7_L0_SEL 1
10923 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10924 * PSU_IOU_SLCR_MIO_PIN_7_L1_SEL 0
10926 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
10927 * , test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7
10928 * ]- (Test Scan Port) 3= Not Used
10929 * PSU_IOU_SLCR_MIO_PIN_7_L2_SEL 0
10931 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= g
10932 * pio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy
10933 * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
10934 * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (
10935 * Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Ma
10936 * ster Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua
10937 * 0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, t
10938 * racedq[5]- (Trace Port Databus)
10939 * PSU_IOU_SLCR_MIO_PIN_7_L3_SEL 0
10941 * Configures MIO Pin 7 peripheral interface mapping
10942 * (OFFSET, MASK, VALUE) (0XFF18001C, 0x000000FEU ,0x00000002U)
10944 PSU_Mask_Write(IOU_SLCR_MIO_PIN_7_OFFSET, 0x000000FEU, 0x00000002U);
10945 /*##################################################################### */
10948 * Register : MIO_PIN_8 @ 0XFF180020
10950 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0
10951 * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper D
10953 * PSU_IOU_SLCR_MIO_PIN_8_L0_SEL 1
10955 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10956 * PSU_IOU_SLCR_MIO_PIN_8_L1_SEL 0
10958 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
10959 * , test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8
10960 * ]- (Test Scan Port) 3= Not Used
10961 * PSU_IOU_SLCR_MIO_PIN_8_L2_SEL 0
10963 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= g
10964 * pio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy
10965 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
10966 * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa
10967 * tch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Maste
10968 * r Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_
10969 * txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tra
10971 * PSU_IOU_SLCR_MIO_PIN_8_L3_SEL 0
10973 * Configures MIO Pin 8 peripheral interface mapping
10974 * (OFFSET, MASK, VALUE) (0XFF180020, 0x000000FEU ,0x00000002U)
10976 PSU_Mask_Write(IOU_SLCR_MIO_PIN_8_OFFSET, 0x000000FEU, 0x00000002U);
10977 /*##################################################################### */
10980 * Register : MIO_PIN_9 @ 0XFF180024
10982 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1
10983 * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper D
10985 * PSU_IOU_SLCR_MIO_PIN_9_L0_SEL 1
10987 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA
10989 * PSU_IOU_SLCR_MIO_PIN_9_L1_SEL 0
10991 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
10992 * , test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9
10993 * ]- (Test Scan Port) 3= Not Used
10994 * PSU_IOU_SLCR_MIO_PIN_9_L2_SEL 0
10996 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= g
10997 * pio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_
10998 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
10999 * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W
11000 * atch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master S
11001 * elects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3,
11002 * Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UA
11003 * RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Data
11005 * PSU_IOU_SLCR_MIO_PIN_9_L3_SEL 0
11007 * Configures MIO Pin 9 peripheral interface mapping
11008 * (OFFSET, MASK, VALUE) (0XFF180024, 0x000000FEU ,0x00000002U)
11010 PSU_Mask_Write(IOU_SLCR_MIO_PIN_9_OFFSET, 0x000000FEU, 0x00000002U);
11011 /*##################################################################### */
11014 * Register : MIO_PIN_10 @ 0XFF180028
11016 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2
11017 * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper D
11019 * PSU_IOU_SLCR_MIO_PIN_10_L0_SEL 1
11021 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N
11023 * PSU_IOU_SLCR_MIO_PIN_10_L1_SEL 0
11025 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
11026 * , test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[
11027 * 10]- (Test Scan Port) 3= Not Used
11028 * PSU_IOU_SLCR_MIO_PIN_10_L2_SEL 0
11030 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0=
11031 * gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_ph
11032 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
11033 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
11034 * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp
11035 * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo
11036 * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu
11037 * t, tracedq[8]- (Trace Port Databus)
11038 * PSU_IOU_SLCR_MIO_PIN_10_L3_SEL 0
11040 * Configures MIO Pin 10 peripheral interface mapping
11041 * (OFFSET, MASK, VALUE) (0XFF180028, 0x000000FEU ,0x00000002U)
11043 PSU_Mask_Write(IOU_SLCR_MIO_PIN_10_OFFSET, 0x000000FEU, 0x00000002U);
11044 /*##################################################################### */
11047 * Register : MIO_PIN_11 @ 0XFF18002C
11049 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3
11050 * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper D
11052 * PSU_IOU_SLCR_MIO_PIN_11_L0_SEL 1
11054 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N
11056 * PSU_IOU_SLCR_MIO_PIN_11_L1_SEL 0
11058 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
11059 * , test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[
11060 * 11]- (Test Scan Port) 3= Not Used
11061 * PSU_IOU_SLCR_MIO_PIN_11_L2_SEL 0
11063 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0=
11064 * gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_p
11065 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
11066 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
11067 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal)
11068 * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (
11069 * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
11070 * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
11071 * PSU_IOU_SLCR_MIO_PIN_11_L3_SEL 0
11073 * Configures MIO Pin 11 peripheral interface mapping
11074 * (OFFSET, MASK, VALUE) (0XFF18002C, 0x000000FEU ,0x00000002U)
11076 PSU_Mask_Write(IOU_SLCR_MIO_PIN_11_OFFSET, 0x000000FEU, 0x00000002U);
11077 /*##################################################################### */
11080 * Register : MIO_PIN_12 @ 0XFF180030
11082 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_
11083 * upper- (QSPI Upper Clock)
11084 * PSU_IOU_SLCR_MIO_PIN_12_L0_SEL 1
11086 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA
11087 * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe)
11088 * PSU_IOU_SLCR_MIO_PIN_12_L1_SEL 0
11090 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
11091 * , test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[
11092 * 12]- (Test Scan Port) 3= Not Used
11093 * PSU_IOU_SLCR_MIO_PIN_12_L2_SEL 0
11095 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0=
11096 * gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_p
11097 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
11098 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJT
11099 * AG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_
11100 * sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, O
11101 * utput, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace
11102 * dq[10]- (Trace Port Databus)
11103 * PSU_IOU_SLCR_MIO_PIN_12_L3_SEL 0
11105 * Configures MIO Pin 12 peripheral interface mapping
11106 * (OFFSET, MASK, VALUE) (0XFF180030, 0x000000FEU ,0x00000002U)
11108 PSU_Mask_Write(IOU_SLCR_MIO_PIN_12_OFFSET, 0x000000FEU, 0x00000002U);
11109 /*##################################################################### */
11112 * Register : MIO_PIN_13 @ 0XFF180034
11114 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11115 * PSU_IOU_SLCR_MIO_PIN_13_L0_SEL 0
11117 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NA
11119 * PSU_IOU_SLCR_MIO_PIN_13_L1_SEL 0
11121 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]-
11122 * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= t
11123 * est_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output,
11124 * test_scan_out[13]- (Test Scan Port) 3= Not Used
11125 * PSU_IOU_SLCR_MIO_PIN_13_L2_SEL 0
11127 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0=
11128 * gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_ph
11129 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
11130 * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTA
11131 * G TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1,
11132 * Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UAR
11133 * T receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Data
11135 * PSU_IOU_SLCR_MIO_PIN_13_L3_SEL 0
11137 * Configures MIO Pin 13 peripheral interface mapping
11138 * (OFFSET, MASK, VALUE) (0XFF180034, 0x000000FEU ,0x00000000U)
11140 PSU_Mask_Write(IOU_SLCR_MIO_PIN_13_OFFSET, 0x000000FEU, 0x00000000U);
11141 /*##################################################################### */
11144 * Register : MIO_PIN_14 @ 0XFF180038
11146 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11147 * PSU_IOU_SLCR_MIO_PIN_14_L0_SEL 0
11149 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND
11150 * Command Latch Enable)
11151 * PSU_IOU_SLCR_MIO_PIN_14_L1_SEL 0
11153 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]-
11154 * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= t
11155 * est_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output,
11156 * test_scan_out[14]- (Test Scan Port) 3= Not Used
11157 * PSU_IOU_SLCR_MIO_PIN_14_L2_SEL 0
11159 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0=
11160 * gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_ph
11161 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
11162 * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJT
11163 * AG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0,
11164 * Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver
11165 * serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)
11166 * PSU_IOU_SLCR_MIO_PIN_14_L3_SEL 2
11168 * Configures MIO Pin 14 peripheral interface mapping
11169 * (OFFSET, MASK, VALUE) (0XFF180038, 0x000000FEU ,0x00000040U)
11171 PSU_Mask_Write(IOU_SLCR_MIO_PIN_14_OFFSET, 0x000000FEU, 0x00000040U);
11172 /*##################################################################### */
11175 * Register : MIO_PIN_15 @ 0XFF18003C
11177 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11178 * PSU_IOU_SLCR_MIO_PIN_15_L0_SEL 0
11180 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND
11181 * Address Latch Enable)
11182 * PSU_IOU_SLCR_MIO_PIN_15_L1_SEL 0
11184 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]-
11185 * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= t
11186 * est_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output,
11187 * test_scan_out[15]- (Test Scan Port) 3= Not Used
11188 * PSU_IOU_SLCR_MIO_PIN_15_L2_SEL 0
11190 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0=
11191 * gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_p
11192 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
11193 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJT
11194 * AG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outp
11195 * ut, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_ou
11196 * t- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seria
11197 * l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
11198 * PSU_IOU_SLCR_MIO_PIN_15_L3_SEL 2
11200 * Configures MIO Pin 15 peripheral interface mapping
11201 * (OFFSET, MASK, VALUE) (0XFF18003C, 0x000000FEU ,0x00000040U)
11203 PSU_Mask_Write(IOU_SLCR_MIO_PIN_15_OFFSET, 0x000000FEU, 0x00000040U);
11204 /*##################################################################### */
11207 * Register : MIO_PIN_16 @ 0XFF180040
11209 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11210 * PSU_IOU_SLCR_MIO_PIN_16_L0_SEL 0
11212 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (
11213 * NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus)
11214 * PSU_IOU_SLCR_MIO_PIN_16_L1_SEL 0
11216 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]-
11217 * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= t
11218 * est_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output,
11219 * test_scan_out[16]- (Test Scan Port) 3= Not Used
11220 * PSU_IOU_SLCR_MIO_PIN_16_L2_SEL 0
11222 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0=
11223 * gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_p
11224 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
11225 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
11226 * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s
11227 * pi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl
11228 * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
11229 * Output, tracedq[14]- (Trace Port Databus)
11230 * PSU_IOU_SLCR_MIO_PIN_16_L3_SEL 2
11232 * Configures MIO Pin 16 peripheral interface mapping
11233 * (OFFSET, MASK, VALUE) (0XFF180040, 0x000000FEU ,0x00000040U)
11235 PSU_Mask_Write(IOU_SLCR_MIO_PIN_16_OFFSET, 0x000000FEU, 0x00000040U);
11236 /*##################################################################### */
11239 * Register : MIO_PIN_17 @ 0XFF180044
11241 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11242 * PSU_IOU_SLCR_MIO_PIN_17_L0_SEL 0
11244 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (
11245 * NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus)
11246 * PSU_IOU_SLCR_MIO_PIN_17_L1_SEL 0
11248 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]-
11249 * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= t
11250 * est_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output,
11251 * test_scan_out[17]- (Test Scan Port) 3= Not Used
11252 * PSU_IOU_SLCR_MIO_PIN_17_L2_SEL 0
11254 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0=
11255 * gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_ph
11256 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
11257 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
11258 * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4
11259 * = spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T
11260 * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
11261 * 7= trace, Output, tracedq[15]- (Trace Port Databus)
11262 * PSU_IOU_SLCR_MIO_PIN_17_L3_SEL 2
11264 * Configures MIO Pin 17 peripheral interface mapping
11265 * (OFFSET, MASK, VALUE) (0XFF180044, 0x000000FEU ,0x00000040U)
11267 PSU_Mask_Write(IOU_SLCR_MIO_PIN_17_OFFSET, 0x000000FEU, 0x00000040U);
11268 /*##################################################################### */
11271 * Register : MIO_PIN_18 @ 0XFF180048
11273 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11274 * PSU_IOU_SLCR_MIO_PIN_18_L0_SEL 0
11276 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (
11277 * NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus)
11278 * PSU_IOU_SLCR_MIO_PIN_18_L1_SEL 0
11280 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]-
11281 * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= t
11282 * est_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output,
11283 * test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU
11285 * PSU_IOU_SLCR_MIO_PIN_18_L2_SEL 0
11287 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0=
11288 * gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_ph
11289 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
11290 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
11291 * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp
11292 * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo
11293 * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
11294 * PSU_IOU_SLCR_MIO_PIN_18_L3_SEL 6
11296 * Configures MIO Pin 18 peripheral interface mapping
11297 * (OFFSET, MASK, VALUE) (0XFF180048, 0x000000FEU ,0x000000C0U)
11299 PSU_Mask_Write(IOU_SLCR_MIO_PIN_18_OFFSET, 0x000000FEU, 0x000000C0U);
11300 /*##################################################################### */
11303 * Register : MIO_PIN_19 @ 0XFF18004C
11305 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11306 * PSU_IOU_SLCR_MIO_PIN_19_L0_SEL 0
11308 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (
11309 * NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus)
11310 * PSU_IOU_SLCR_MIO_PIN_19_L1_SEL 0
11312 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]-
11313 * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= t
11314 * est_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output,
11315 * test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU
11317 * PSU_IOU_SLCR_MIO_PIN_19_L2_SEL 0
11319 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0=
11320 * gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_p
11321 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
11322 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
11323 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI
11324 * Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6=
11325 * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
11326 * PSU_IOU_SLCR_MIO_PIN_19_L3_SEL 6
11328 * Configures MIO Pin 19 peripheral interface mapping
11329 * (OFFSET, MASK, VALUE) (0XFF18004C, 0x000000FEU ,0x000000C0U)
11331 PSU_Mask_Write(IOU_SLCR_MIO_PIN_19_OFFSET, 0x000000FEU, 0x000000C0U);
11332 /*##################################################################### */
11335 * Register : MIO_PIN_20 @ 0XFF180050
11337 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11338 * PSU_IOU_SLCR_MIO_PIN_20_L0_SEL 0
11340 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (
11341 * NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus)
11342 * PSU_IOU_SLCR_MIO_PIN_20_L1_SEL 0
11344 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]-
11345 * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= t
11346 * est_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output,
11347 * test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU
11349 * PSU_IOU_SLCR_MIO_PIN_20_L2_SEL 0
11351 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0=
11352 * gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_p
11353 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
11354 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
11355 * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas
11356 * ter Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua
11357 * 1_txd- (UART transmitter serial output) 7= Not Used
11358 * PSU_IOU_SLCR_MIO_PIN_20_L3_SEL 6
11360 * Configures MIO Pin 20 peripheral interface mapping
11361 * (OFFSET, MASK, VALUE) (0XFF180050, 0x000000FEU ,0x000000C0U)
11363 PSU_Mask_Write(IOU_SLCR_MIO_PIN_20_OFFSET, 0x000000FEU, 0x000000C0U);
11364 /*##################################################################### */
11367 * Register : MIO_PIN_21 @ 0XFF180054
11369 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11370 * PSU_IOU_SLCR_MIO_PIN_21_L0_SEL 0
11372 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (
11373 * NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus)
11374 * PSU_IOU_SLCR_MIO_PIN_21_L1_SEL 0
11376 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com
11377 * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= tes
11378 * t_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, t
11379 * est_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU E
11381 * PSU_IOU_SLCR_MIO_PIN_21_L2_SEL 0
11383 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0=
11384 * gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_ph
11385 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
11386 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
11387 * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master
11388 * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc
11389 * 1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (
11390 * UART receiver serial input) 7= Not Used
11391 * PSU_IOU_SLCR_MIO_PIN_21_L3_SEL 6
11393 * Configures MIO Pin 21 peripheral interface mapping
11394 * (OFFSET, MASK, VALUE) (0XFF180054, 0x000000FEU ,0x000000C0U)
11396 PSU_Mask_Write(IOU_SLCR_MIO_PIN_21_OFFSET, 0x000000FEU, 0x000000C0U);
11397 /*##################################################################### */
11400 * Register : MIO_PIN_22 @ 0XFF180058
11402 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11403 * PSU_IOU_SLCR_MIO_PIN_22_L0_SEL 0
11405 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAN
11407 * PSU_IOU_SLCR_MIO_PIN_22_L1_SEL 0
11409 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out-
11410 * (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) =
11411 * test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, c
11412 * su_ext_tamper- (CSU Ext Tamper)
11413 * PSU_IOU_SLCR_MIO_PIN_22_L2_SEL 0
11415 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0=
11416 * gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_ph
11417 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
11418 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
11419 * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4=
11420 * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (
11421 * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U
11423 * PSU_IOU_SLCR_MIO_PIN_22_L3_SEL 0
11425 * Configures MIO Pin 22 peripheral interface mapping
11426 * (OFFSET, MASK, VALUE) (0XFF180058, 0x000000FEU ,0x00000000U)
11428 PSU_Mask_Write(IOU_SLCR_MIO_PIN_22_OFFSET, 0x000000FEU, 0x00000000U);
11429 /*##################################################################### */
11432 * Register : MIO_PIN_23 @ 0XFF18005C
11434 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11435 * PSU_IOU_SLCR_MIO_PIN_23_L0_SEL 0
11437 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (
11438 * NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus)
11439 * PSU_IOU_SLCR_MIO_PIN_23_L1_SEL 0
11441 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow-
11442 * (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Po
11443 * rt) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Inp
11444 * ut, csu_ext_tamper- (CSU Ext Tamper)
11445 * PSU_IOU_SLCR_MIO_PIN_23_L2_SEL 0
11447 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0=
11448 * gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_p
11449 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
11450 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
11451 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal)
11452 * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (
11453 * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
11454 * tput) 7= Not Used
11455 * PSU_IOU_SLCR_MIO_PIN_23_L3_SEL 0
11457 * Configures MIO Pin 23 peripheral interface mapping
11458 * (OFFSET, MASK, VALUE) (0XFF18005C, 0x000000FEU ,0x00000000U)
11460 PSU_Mask_Write(IOU_SLCR_MIO_PIN_23_OFFSET, 0x000000FEU, 0x00000000U);
11461 /*##################################################################### */
11464 * Register : MIO_PIN_24 @ 0XFF180060
11466 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11467 * PSU_IOU_SLCR_MIO_PIN_24_L0_SEL 0
11469 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (
11470 * NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus)
11471 * PSU_IOU_SLCR_MIO_PIN_24_L1_SEL 0
11473 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD
11474 * card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test
11475 * Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3=
11476 * csu, Input, csu_ext_tamper- (CSU Ext Tamper)
11477 * PSU_IOU_SLCR_MIO_PIN_24_L2_SEL 0
11479 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0=
11480 * gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_p
11481 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
11482 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
11483 * Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (T
11484 * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= N
11486 * PSU_IOU_SLCR_MIO_PIN_24_L3_SEL 1
11488 * Configures MIO Pin 24 peripheral interface mapping
11489 * (OFFSET, MASK, VALUE) (0XFF180060, 0x000000FEU ,0x00000020U)
11491 PSU_Mask_Write(IOU_SLCR_MIO_PIN_24_OFFSET, 0x000000FEU, 0x00000020U);
11492 /*##################################################################### */
11495 * Register : MIO_PIN_25 @ 0XFF180064
11497 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11498 * PSU_IOU_SLCR_MIO_PIN_25_L0_SEL 0
11500 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAN
11502 * PSU_IOU_SLCR_MIO_PIN_25_L1_SEL 0
11504 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca
11505 * rd write protect from connector) 2= test_scan, Input, test_scan_in[25]-
11506 * (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port
11507 * ) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
11508 * PSU_IOU_SLCR_MIO_PIN_25_L2_SEL 0
11510 * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0=
11511 * gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_ph
11512 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
11513 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
11514 * (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_ou
11515 * t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
11517 * PSU_IOU_SLCR_MIO_PIN_25_L3_SEL 1
11519 * Configures MIO Pin 25 peripheral interface mapping
11520 * (OFFSET, MASK, VALUE) (0XFF180064, 0x000000FEU ,0x00000020U)
11522 PSU_Mask_Write(IOU_SLCR_MIO_PIN_25_OFFSET, 0x000000FEU, 0x00000020U);
11523 /*##################################################################### */
11526 * Register : MIO_PIN_26 @ 0XFF180068
11528 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_
11529 * clk- (TX RGMII clock)
11530 * PSU_IOU_SLCR_MIO_PIN_26_L0_SEL 0
11532 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA
11534 * PSU_IOU_SLCR_MIO_PIN_26_L1_SEL 0
11536 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU
11537 * GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_sca
11538 * n, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_ta
11539 * mper- (CSU Ext Tamper)
11540 * PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 0
11542 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= g
11543 * pio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_
11544 * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
11545 * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
11546 * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_scl
11547 * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu
11548 * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (
11549 * Trace Port Databus)
11550 * PSU_IOU_SLCR_MIO_PIN_26_L3_SEL 0
11552 * Configures MIO Pin 26 peripheral interface mapping
11553 * (OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000000U)
11555 PSU_Mask_Write(IOU_SLCR_MIO_PIN_26_OFFSET, 0x000000FEU, 0x00000000U);
11556 /*##################################################################### */
11559 * Register : MIO_PIN_27 @ 0XFF18006C
11561 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
11562 * [0]- (TX RGMII data)
11563 * PSU_IOU_SLCR_MIO_PIN_27_L0_SEL 0
11565 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N
11567 * PSU_IOU_SLCR_MIO_PIN_27_L1_SEL 0
11569 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU
11570 * GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_sca
11571 * n, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_d
11572 * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
11573 * PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 3
11575 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= g
11576 * pio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy
11577 * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
11578 * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
11579 * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O
11580 * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR
11581 * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D
11583 * PSU_IOU_SLCR_MIO_PIN_27_L3_SEL 0
11585 * Configures MIO Pin 27 peripheral interface mapping
11586 * (OFFSET, MASK, VALUE) (0XFF18006C, 0x000000FEU ,0x00000018U)
11588 PSU_Mask_Write(IOU_SLCR_MIO_PIN_27_OFFSET, 0x000000FEU, 0x00000018U);
11589 /*##################################################################### */
11592 * Register : MIO_PIN_28 @ 0XFF180070
11594 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
11595 * [1]- (TX RGMII data)
11596 * PSU_IOU_SLCR_MIO_PIN_28_L0_SEL 0
11598 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N
11600 * PSU_IOU_SLCR_MIO_PIN_28_L1_SEL 0
11602 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU
11603 * GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_sca
11604 * n, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_p
11605 * lug_detect- (Dp Aux Hot Plug)
11606 * PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 3
11608 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= g
11609 * pio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy
11610 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
11611 * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA
11612 * G TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1,
11613 * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt
11614 * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
11615 * PSU_IOU_SLCR_MIO_PIN_28_L3_SEL 0
11617 * Configures MIO Pin 28 peripheral interface mapping
11618 * (OFFSET, MASK, VALUE) (0XFF180070, 0x000000FEU ,0x00000018U)
11620 PSU_Mask_Write(IOU_SLCR_MIO_PIN_28_OFFSET, 0x000000FEU, 0x00000018U);
11621 /*##################################################################### */
11624 * Register : MIO_PIN_29 @ 0XFF180074
11626 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
11627 * [2]- (TX RGMII data)
11628 * PSU_IOU_SLCR_MIO_PIN_29_L0_SEL 0
11630 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
11631 * PCIE Reset signal)
11632 * PSU_IOU_SLCR_MIO_PIN_29_L1_SEL 0
11634 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU
11635 * GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_sca
11636 * n, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_d
11637 * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
11638 * PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 3
11640 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= g
11641 * pio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_
11642 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
11643 * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
11644 * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output,
11645 * spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out-
11646 * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input
11647 * ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
11648 * PSU_IOU_SLCR_MIO_PIN_29_L3_SEL 0
11650 * Configures MIO Pin 29 peripheral interface mapping
11651 * (OFFSET, MASK, VALUE) (0XFF180074, 0x000000FEU ,0x00000018U)
11653 PSU_Mask_Write(IOU_SLCR_MIO_PIN_29_OFFSET, 0x000000FEU, 0x00000018U);
11654 /*##################################################################### */
11657 * Register : MIO_PIN_30 @ 0XFF180078
11659 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
11660 * [3]- (TX RGMII data)
11661 * PSU_IOU_SLCR_MIO_PIN_30_L0_SEL 0
11663 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
11664 * PCIE Reset signal)
11665 * PSU_IOU_SLCR_MIO_PIN_30_L1_SEL 0
11667 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU
11668 * GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_sca
11669 * n, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_p
11670 * lug_detect- (Dp Aux Hot Plug)
11671 * PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 3
11673 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= g
11674 * pio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_
11675 * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
11676 * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat
11677 * ch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0
11678 * , Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock
11679 * ) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output,
11680 * tracedq[8]- (Trace Port Databus)
11681 * PSU_IOU_SLCR_MIO_PIN_30_L3_SEL 0
11683 * Configures MIO Pin 30 peripheral interface mapping
11684 * (OFFSET, MASK, VALUE) (0XFF180078, 0x000000FEU ,0x00000018U)
11686 PSU_Mask_Write(IOU_SLCR_MIO_PIN_30_OFFSET, 0x000000FEU, 0x00000018U);
11687 /*##################################################################### */
11690 * Register : MIO_PIN_31 @ 0XFF18007C
11692 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_
11693 * ctl- (TX RGMII control)
11694 * PSU_IOU_SLCR_MIO_PIN_31_L0_SEL 0
11696 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
11697 * PCIE Reset signal)
11698 * PSU_IOU_SLCR_MIO_PIN_31_L1_SEL 0
11700 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU
11701 * GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_sca
11702 * n, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_ta
11703 * mper- (CSU Ext Tamper)
11704 * PSU_IOU_SLCR_MIO_PIN_31_L2_SEL 0
11706 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= g
11707 * pio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy
11708 * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
11709 * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (
11710 * Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4=
11711 * spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TT
11712 * C Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial outp
11713 * ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)
11714 * PSU_IOU_SLCR_MIO_PIN_31_L3_SEL 0
11716 * Configures MIO Pin 31 peripheral interface mapping
11717 * (OFFSET, MASK, VALUE) (0XFF18007C, 0x000000FEU ,0x00000000U)
11719 PSU_Mask_Write(IOU_SLCR_MIO_PIN_31_OFFSET, 0x000000FEU, 0x00000000U);
11720 /*##################################################################### */
11723 * Register : MIO_PIN_32 @ 0XFF180080
11725 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c
11726 * lk- (RX RGMII clock)
11727 * PSU_IOU_SLCR_MIO_PIN_32_L0_SEL 0
11729 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA
11730 * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe)
11731 * PSU_IOU_SLCR_MIO_PIN_32_L1_SEL 0
11733 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PM
11734 * U GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_sc
11735 * an, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_t
11736 * amper- (CSU Ext Tamper)
11737 * PSU_IOU_SLCR_MIO_PIN_32_L2_SEL 1
11739 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= g
11740 * pio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy
11741 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
11742 * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa
11743 * tch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4=
11744 * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (T
11745 * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= t
11746 * race, Output, tracedq[10]- (Trace Port Databus)
11747 * PSU_IOU_SLCR_MIO_PIN_32_L3_SEL 0
11749 * Configures MIO Pin 32 peripheral interface mapping
11750 * (OFFSET, MASK, VALUE) (0XFF180080, 0x000000FEU ,0x00000008U)
11752 PSU_Mask_Write(IOU_SLCR_MIO_PIN_32_OFFSET, 0x000000FEU, 0x00000008U);
11753 /*##################################################################### */
11756 * Register : MIO_PIN_33 @ 0XFF180084
11758 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[
11759 * 0]- (RX RGMII data)
11760 * PSU_IOU_SLCR_MIO_PIN_33_L0_SEL 0
11762 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
11763 * PCIE Reset signal)
11764 * PSU_IOU_SLCR_MIO_PIN_33_L1_SEL 0
11766 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PM
11767 * U GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_sc
11768 * an, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_t
11769 * amper- (CSU Ext Tamper)
11770 * PSU_IOU_SLCR_MIO_PIN_33_L2_SEL 1
11772 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= g
11773 * pio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_
11774 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
11775 * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W
11776 * atch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Mas
11777 * ter Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1
11778 * , Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq
11779 * [11]- (Trace Port Databus)
11780 * PSU_IOU_SLCR_MIO_PIN_33_L3_SEL 0
11782 * Configures MIO Pin 33 peripheral interface mapping
11783 * (OFFSET, MASK, VALUE) (0XFF180084, 0x000000FEU ,0x00000008U)
11785 PSU_Mask_Write(IOU_SLCR_MIO_PIN_33_OFFSET, 0x000000FEU, 0x00000008U);
11786 /*##################################################################### */
11789 * Register : MIO_PIN_34 @ 0XFF180088
11791 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[
11792 * 1]- (RX RGMII data)
11793 * PSU_IOU_SLCR_MIO_PIN_34_L0_SEL 0
11795 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
11796 * PCIE Reset signal)
11797 * PSU_IOU_SLCR_MIO_PIN_34_L1_SEL 0
11799 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PM
11800 * U GPI) 2= test_scan, Input, test_scan_in[34]- (Test Scan Port) = test_sc
11801 * an, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_
11802 * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
11803 * PSU_IOU_SLCR_MIO_PIN_34_L2_SEL 1
11805 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= g
11806 * pio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can0, Input, can0_phy_
11807 * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
11808 * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat
11809 * ch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master
11810 * Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rx
11811 * d- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Po
11813 * PSU_IOU_SLCR_MIO_PIN_34_L3_SEL 0
11815 * Configures MIO Pin 34 peripheral interface mapping
11816 * (OFFSET, MASK, VALUE) (0XFF180088, 0x000000FEU ,0x00000008U)
11818 PSU_Mask_Write(IOU_SLCR_MIO_PIN_34_OFFSET, 0x000000FEU, 0x00000008U);
11819 /*##################################################################### */
11822 * Register : MIO_PIN_35 @ 0XFF18008C
11824 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[
11825 * 2]- (RX RGMII data)
11826 * PSU_IOU_SLCR_MIO_PIN_35_L0_SEL 0
11828 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
11829 * PCIE Reset signal)
11830 * PSU_IOU_SLCR_MIO_PIN_35_L1_SEL 0
11832 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PM
11833 * U GPI) 2= test_scan, Input, test_scan_in[35]- (Test Scan Port) = test_sc
11834 * an, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_
11835 * plug_detect- (Dp Aux Hot Plug)
11836 * PSU_IOU_SLCR_MIO_PIN_35_L2_SEL 1
11838 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= g
11839 * pio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can0, Output, can0_phy
11840 * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
11841 * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (
11842 * Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master
11843 * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2
11844 * , Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (
11845 * UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Po
11847 * PSU_IOU_SLCR_MIO_PIN_35_L3_SEL 0
11849 * Configures MIO Pin 35 peripheral interface mapping
11850 * (OFFSET, MASK, VALUE) (0XFF18008C, 0x000000FEU ,0x00000008U)
11852 PSU_Mask_Write(IOU_SLCR_MIO_PIN_35_OFFSET, 0x000000FEU, 0x00000008U);
11853 /*##################################################################### */
11856 * Register : MIO_PIN_36 @ 0XFF180090
11858 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[
11859 * 3]- (RX RGMII data)
11860 * PSU_IOU_SLCR_MIO_PIN_36_L0_SEL 0
11862 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
11863 * PCIE Reset signal)
11864 * PSU_IOU_SLCR_MIO_PIN_36_L1_SEL 0
11866 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PM
11867 * U GPI) 2= test_scan, Input, test_scan_in[36]- (Test Scan Port) = test_sc
11868 * an, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_
11869 * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
11870 * PSU_IOU_SLCR_MIO_PIN_36_L2_SEL 1
11872 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0=
11873 * gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can1, Output, can1_p
11874 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
11875 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
11876 * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s
11877 * pi1, Output, spi1_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl
11878 * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
11879 * Output, tracedq[14]- (Trace Port Databus)
11880 * PSU_IOU_SLCR_MIO_PIN_36_L3_SEL 0
11882 * Configures MIO Pin 36 peripheral interface mapping
11883 * (OFFSET, MASK, VALUE) (0XFF180090, 0x000000FEU ,0x00000008U)
11885 PSU_Mask_Write(IOU_SLCR_MIO_PIN_36_OFFSET, 0x000000FEU, 0x00000008U);
11886 /*##################################################################### */
11889 * Register : MIO_PIN_37 @ 0XFF180094
11891 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c
11892 * tl- (RX RGMII control )
11893 * PSU_IOU_SLCR_MIO_PIN_37_L0_SEL 0
11895 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
11896 * PCIE Reset signal)
11897 * PSU_IOU_SLCR_MIO_PIN_37_L1_SEL 0
11899 * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PM
11900 * U GPI) 2= test_scan, Input, test_scan_in[37]- (Test Scan Port) = test_sc
11901 * an, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_
11902 * plug_detect- (Dp Aux Hot Plug)
11903 * PSU_IOU_SLCR_MIO_PIN_37_L2_SEL 1
11905 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0=
11906 * gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can1, Input, can1_ph
11907 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
11908 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
11909 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4
11910 * = spi1, Input, spi1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T
11911 * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
11912 * 7= trace, Output, tracedq[15]- (Trace Port Databus)
11913 * PSU_IOU_SLCR_MIO_PIN_37_L3_SEL 0
11915 * Configures MIO Pin 37 peripheral interface mapping
11916 * (OFFSET, MASK, VALUE) (0XFF180094, 0x000000FEU ,0x00000008U)
11918 PSU_Mask_Write(IOU_SLCR_MIO_PIN_37_OFFSET, 0x000000FEU, 0x00000008U);
11919 /*##################################################################### */
11922 * Register : MIO_PIN_38 @ 0XFF180098
11924 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_
11925 * clk- (TX RGMII clock)
11926 * PSU_IOU_SLCR_MIO_PIN_38_L0_SEL 0
11928 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
11929 * PSU_IOU_SLCR_MIO_PIN_38_L1_SEL 0
11931 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out-
11932 * (SDSDIO clock) 2= Not Used 3= Not Used
11933 * PSU_IOU_SLCR_MIO_PIN_38_L2_SEL 0
11935 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0=
11936 * gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_ph
11937 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
11938 * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTA
11939 * G TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_s
11940 * clk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, In
11941 * put, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
11942 * (Trace Port Clock)
11943 * PSU_IOU_SLCR_MIO_PIN_38_L3_SEL 0
11945 * Configures MIO Pin 38 peripheral interface mapping
11946 * (OFFSET, MASK, VALUE) (0XFF180098, 0x000000FEU ,0x00000000U)
11948 PSU_Mask_Write(IOU_SLCR_MIO_PIN_38_OFFSET, 0x000000FEU, 0x00000000U);
11949 /*##################################################################### */
11952 * Register : MIO_PIN_39 @ 0XFF18009C
11954 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd
11955 * [0]- (TX RGMII data)
11956 * PSU_IOU_SLCR_MIO_PIN_39_L0_SEL 0
11958 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
11959 * PSU_IOU_SLCR_MIO_PIN_39_L1_SEL 0
11961 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD
11962 * card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data b
11963 * us) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used
11964 * PSU_IOU_SLCR_MIO_PIN_39_L2_SEL 2
11966 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0=
11967 * gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_p
11968 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
11969 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJT
11970 * AG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0,
11971 * Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (U
11972 * ART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
11974 * PSU_IOU_SLCR_MIO_PIN_39_L3_SEL 0
11976 * Configures MIO Pin 39 peripheral interface mapping
11977 * (OFFSET, MASK, VALUE) (0XFF18009C, 0x000000FEU ,0x00000010U)
11979 PSU_Mask_Write(IOU_SLCR_MIO_PIN_39_OFFSET, 0x000000FEU, 0x00000010U);
11980 /*##################################################################### */
11983 * Register : MIO_PIN_40 @ 0XFF1800A0
11985 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd
11986 * [1]- (TX RGMII data)
11987 * PSU_IOU_SLCR_MIO_PIN_40_L0_SEL 0
11989 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
11990 * PSU_IOU_SLCR_MIO_PIN_40_L1_SEL 0
11992 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com
11993 * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1
11994 * , Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[
11995 * 5]- (8-bit Data bus) 3= Not Used
11996 * PSU_IOU_SLCR_MIO_PIN_40_L2_SEL 2
11998 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0=
11999 * gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_p
12000 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
12001 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJ
12002 * TAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3
12003 * , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmi
12004 * tter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)
12005 * PSU_IOU_SLCR_MIO_PIN_40_L3_SEL 0
12007 * Configures MIO Pin 40 peripheral interface mapping
12008 * (OFFSET, MASK, VALUE) (0XFF1800A0, 0x000000FEU ,0x00000010U)
12010 PSU_Mask_Write(IOU_SLCR_MIO_PIN_40_OFFSET, 0x000000FEU, 0x00000010U);
12011 /*##################################################################### */
12014 * Register : MIO_PIN_41 @ 0XFF1800A4
12016 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd
12017 * [2]- (TX RGMII data)
12018 * PSU_IOU_SLCR_MIO_PIN_41_L0_SEL 0
12020 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12021 * PSU_IOU_SLCR_MIO_PIN_41_L1_SEL 0
12023 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]-
12024 * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= s
12025 * d1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
12026 * t[6]- (8-bit Data bus) 3= Not Used
12027 * PSU_IOU_SLCR_MIO_PIN_41_L2_SEL 2
12029 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0=
12030 * gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_ph
12031 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
12032 * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTA
12033 * G TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outpu
12034 * t, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out
12035 * - (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inp
12036 * ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)
12037 * PSU_IOU_SLCR_MIO_PIN_41_L3_SEL 0
12039 * Configures MIO Pin 41 peripheral interface mapping
12040 * (OFFSET, MASK, VALUE) (0XFF1800A4, 0x000000FEU ,0x00000010U)
12042 PSU_Mask_Write(IOU_SLCR_MIO_PIN_41_OFFSET, 0x000000FEU, 0x00000010U);
12043 /*##################################################################### */
12046 * Register : MIO_PIN_42 @ 0XFF1800A8
12048 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd
12049 * [3]- (TX RGMII data)
12050 * PSU_IOU_SLCR_MIO_PIN_42_L0_SEL 0
12052 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12053 * PSU_IOU_SLCR_MIO_PIN_42_L1_SEL 0
12055 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]-
12056 * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= s
12057 * d1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
12058 * t[7]- (8-bit Data bus) 3= Not Used
12059 * PSU_IOU_SLCR_MIO_PIN_42_L2_SEL 2
12061 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0=
12062 * gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_ph
12063 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
12064 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
12065 * atch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= sp
12066 * i0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo
12067 * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu
12068 * t, tracedq[2]- (Trace Port Databus)
12069 * PSU_IOU_SLCR_MIO_PIN_42_L3_SEL 0
12071 * Configures MIO Pin 42 peripheral interface mapping
12072 * (OFFSET, MASK, VALUE) (0XFF1800A8, 0x000000FEU ,0x00000010U)
12074 PSU_Mask_Write(IOU_SLCR_MIO_PIN_42_OFFSET, 0x000000FEU, 0x00000010U);
12075 /*##################################################################### */
12078 * Register : MIO_PIN_43 @ 0XFF1800AC
12080 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_
12081 * ctl- (TX RGMII control)
12082 * PSU_IOU_SLCR_MIO_PIN_43_L0_SEL 0
12084 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12085 * PSU_IOU_SLCR_MIO_PIN_43_L1_SEL 0
12087 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]-
12088 * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s
12089 * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
12090 * PSU_IOU_SLCR_MIO_PIN_43_L2_SEL 0
12092 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0=
12093 * gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_p
12094 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
12095 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
12096 * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal)
12097 * 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (
12098 * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
12099 * tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)
12100 * PSU_IOU_SLCR_MIO_PIN_43_L3_SEL 0
12102 * Configures MIO Pin 43 peripheral interface mapping
12103 * (OFFSET, MASK, VALUE) (0XFF1800AC, 0x000000FEU ,0x00000000U)
12105 PSU_Mask_Write(IOU_SLCR_MIO_PIN_43_OFFSET, 0x000000FEU, 0x00000000U);
12106 /*##################################################################### */
12109 * Register : MIO_PIN_44 @ 0XFF1800B0
12111 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c
12112 * lk- (RX RGMII clock)
12113 * PSU_IOU_SLCR_MIO_PIN_44_L0_SEL 0
12115 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12116 * PSU_IOU_SLCR_MIO_PIN_44_L1_SEL 0
12118 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]-
12119 * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s
12120 * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
12121 * PSU_IOU_SLCR_MIO_PIN_44_L2_SEL 2
12123 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0=
12124 * gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_p
12125 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
12126 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
12127 * Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4
12128 * = spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in-
12129 * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7=
12131 * PSU_IOU_SLCR_MIO_PIN_44_L3_SEL 0
12133 * Configures MIO Pin 44 peripheral interface mapping
12134 * (OFFSET, MASK, VALUE) (0XFF1800B0, 0x000000FEU ,0x00000010U)
12136 PSU_Mask_Write(IOU_SLCR_MIO_PIN_44_OFFSET, 0x000000FEU, 0x00000010U);
12137 /*##################################################################### */
12140 * Register : MIO_PIN_45 @ 0XFF1800B4
12142 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
12143 * 0]- (RX RGMII data)
12144 * PSU_IOU_SLCR_MIO_PIN_45_L0_SEL 0
12146 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12147 * PSU_IOU_SLCR_MIO_PIN_45_L1_SEL 0
12149 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]-
12150 * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s
12151 * d1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
12152 * PSU_IOU_SLCR_MIO_PIN_45_L2_SEL 2
12154 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0=
12155 * gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_ph
12156 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
12157 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
12158 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI M
12159 * aster Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= u
12160 * a1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
12161 * PSU_IOU_SLCR_MIO_PIN_45_L3_SEL 0
12163 * Configures MIO Pin 45 peripheral interface mapping
12164 * (OFFSET, MASK, VALUE) (0XFF1800B4, 0x000000FEU ,0x00000010U)
12166 PSU_Mask_Write(IOU_SLCR_MIO_PIN_45_OFFSET, 0x000000FEU, 0x00000010U);
12167 /*##################################################################### */
12170 * Register : MIO_PIN_46 @ 0XFF1800B8
12172 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
12173 * 1]- (RX RGMII data)
12174 * PSU_IOU_SLCR_MIO_PIN_46_L0_SEL 0
12176 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12177 * PSU_IOU_SLCR_MIO_PIN_46_L1_SEL 0
12179 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]-
12180 * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s
12181 * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
12182 * t[0]- (8-bit Data bus) 3= Not Used
12183 * PSU_IOU_SLCR_MIO_PIN_46_L2_SEL 2
12185 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0=
12186 * gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_ph
12187 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
12188 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
12189 * atch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mast
12190 * er Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_
12191 * rxd- (UART receiver serial input) 7= Not Used
12192 * PSU_IOU_SLCR_MIO_PIN_46_L3_SEL 0
12194 * Configures MIO Pin 46 peripheral interface mapping
12195 * (OFFSET, MASK, VALUE) (0XFF1800B8, 0x000000FEU ,0x00000010U)
12197 PSU_Mask_Write(IOU_SLCR_MIO_PIN_46_OFFSET, 0x000000FEU, 0x00000010U);
12198 /*##################################################################### */
12201 * Register : MIO_PIN_47 @ 0XFF1800BC
12203 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
12204 * 2]- (RX RGMII data)
12205 * PSU_IOU_SLCR_MIO_PIN_47_L0_SEL 0
12207 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12208 * PSU_IOU_SLCR_MIO_PIN_47_L1_SEL 0
12210 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]-
12211 * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s
12212 * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
12213 * t[1]- (8-bit Data bus) 3= Not Used
12214 * PSU_IOU_SLCR_MIO_PIN_47_L2_SEL 2
12216 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0=
12217 * gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_p
12218 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
12219 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
12220 * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Maste
12221 * r Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= tt
12222 * c0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd-
12223 * (UART transmitter serial output) 7= Not Used
12224 * PSU_IOU_SLCR_MIO_PIN_47_L3_SEL 0
12226 * Configures MIO Pin 47 peripheral interface mapping
12227 * (OFFSET, MASK, VALUE) (0XFF1800BC, 0x000000FEU ,0x00000010U)
12229 PSU_Mask_Write(IOU_SLCR_MIO_PIN_47_OFFSET, 0x000000FEU, 0x00000010U);
12230 /*##################################################################### */
12233 * Register : MIO_PIN_48 @ 0XFF1800C0
12235 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
12236 * 3]- (RX RGMII data)
12237 * PSU_IOU_SLCR_MIO_PIN_48_L0_SEL 0
12239 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12240 * PSU_IOU_SLCR_MIO_PIN_48_L1_SEL 0
12242 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]-
12243 * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s
12244 * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
12245 * t[2]- (8-bit Data bus) 3= Not Used
12246 * PSU_IOU_SLCR_MIO_PIN_48_L2_SEL 2
12248 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0=
12249 * gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_p
12250 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
12251 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
12252 * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s
12253 * pi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl
12254 * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Us
12256 * PSU_IOU_SLCR_MIO_PIN_48_L3_SEL 0
12258 * Configures MIO Pin 48 peripheral interface mapping
12259 * (OFFSET, MASK, VALUE) (0XFF1800C0, 0x000000FEU ,0x00000010U)
12261 PSU_Mask_Write(IOU_SLCR_MIO_PIN_48_OFFSET, 0x000000FEU, 0x00000010U);
12262 /*##################################################################### */
12265 * Register : MIO_PIN_49 @ 0XFF1800C4
12267 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c
12268 * tl- (RX RGMII control )
12269 * PSU_IOU_SLCR_MIO_PIN_49_L0_SEL 0
12271 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12272 * PSU_IOU_SLCR_MIO_PIN_49_L1_SEL 0
12274 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow-
12275 * (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd
12276 * 1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
12277 * PSU_IOU_SLCR_MIO_PIN_49_L2_SEL 2
12279 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0=
12280 * gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_ph
12281 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
12282 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
12283 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4
12284 * = spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T
12285 * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
12287 * PSU_IOU_SLCR_MIO_PIN_49_L3_SEL 0
12289 * Configures MIO Pin 49 peripheral interface mapping
12290 * (OFFSET, MASK, VALUE) (0XFF1800C4, 0x000000FEU ,0x00000010U)
12292 PSU_Mask_Write(IOU_SLCR_MIO_PIN_49_OFFSET, 0x000000FEU, 0x00000010U);
12293 /*##################################################################### */
12296 * Register : MIO_PIN_50 @ 0XFF1800C8
12298 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk-
12300 * PSU_IOU_SLCR_MIO_PIN_50_L0_SEL 0
12302 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12303 * PSU_IOU_SLCR_MIO_PIN_50_L1_SEL 0
12305 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca
12306 * rd write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Ind
12307 * icator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
12308 * PSU_IOU_SLCR_MIO_PIN_50_L2_SEL 2
12310 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0=
12311 * gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_ph
12312 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
12313 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
12314 * atch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5=
12315 * ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART rece
12316 * iver serial input) 7= Not Used
12317 * PSU_IOU_SLCR_MIO_PIN_50_L3_SEL 0
12319 * Configures MIO Pin 50 peripheral interface mapping
12320 * (OFFSET, MASK, VALUE) (0XFF1800C8, 0x000000FEU ,0x00000010U)
12322 PSU_Mask_Write(IOU_SLCR_MIO_PIN_50_OFFSET, 0x000000FEU, 0x00000010U);
12323 /*##################################################################### */
12326 * Register : MIO_PIN_51 @ 0XFF1800CC
12328 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk-
12330 * PSU_IOU_SLCR_MIO_PIN_51_L0_SEL 0
12332 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12333 * PSU_IOU_SLCR_MIO_PIN_51_L1_SEL 0
12335 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdi
12336 * o1_clk_out- (SDSDIO clock) 3= Not Used
12337 * PSU_IOU_SLCR_MIO_PIN_51_L2_SEL 2
12339 * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0=
12340 * gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_p
12341 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
12342 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
12343 * (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Dat
12344 * a) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wa
12345 * ve_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
12346 * serial output) 7= Not Used
12347 * PSU_IOU_SLCR_MIO_PIN_51_L3_SEL 0
12349 * Configures MIO Pin 51 peripheral interface mapping
12350 * (OFFSET, MASK, VALUE) (0XFF1800CC, 0x000000FEU ,0x00000010U)
12352 PSU_Mask_Write(IOU_SLCR_MIO_PIN_51_OFFSET, 0x000000FEU, 0x00000010U);
12353 /*##################################################################### */
12356 * Register : MIO_PIN_52 @ 0XFF1800D0
12358 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_
12359 * clk- (TX RGMII clock)
12360 * PSU_IOU_SLCR_MIO_PIN_52_L0_SEL 0
12362 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i
12364 * PSU_IOU_SLCR_MIO_PIN_52_L1_SEL 1
12366 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12368 * PSU_IOU_SLCR_MIO_PIN_52_L2_SEL 0
12370 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g
12371 * pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy
12372 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
12373 * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
12374 * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc
12375 * lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out
12376 * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c
12377 * lk- (Trace Port Clock)
12378 * PSU_IOU_SLCR_MIO_PIN_52_L3_SEL 0
12380 * Configures MIO Pin 52 peripheral interface mapping
12381 * (OFFSET, MASK, VALUE) (0XFF1800D0, 0x000000FEU ,0x00000004U)
12383 PSU_Mask_Write(IOU_SLCR_MIO_PIN_52_OFFSET, 0x000000FEU, 0x00000004U);
12384 /*##################################################################### */
12387 * Register : MIO_PIN_53 @ 0XFF1800D4
12389 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
12390 * [0]- (TX RGMII data)
12391 * PSU_IOU_SLCR_MIO_PIN_53_L0_SEL 0
12393 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir-
12394 * (Data bus direction control)
12395 * PSU_IOU_SLCR_MIO_PIN_53_L1_SEL 1
12397 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12399 * PSU_IOU_SLCR_MIO_PIN_53_L2_SEL 0
12401 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g
12402 * pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_
12403 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
12404 * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
12405 * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou
12406 * tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART
12407 * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
12409 * PSU_IOU_SLCR_MIO_PIN_53_L3_SEL 0
12411 * Configures MIO Pin 53 peripheral interface mapping
12412 * (OFFSET, MASK, VALUE) (0XFF1800D4, 0x000000FEU ,0x00000004U)
12414 PSU_Mask_Write(IOU_SLCR_MIO_PIN_53_OFFSET, 0x000000FEU, 0x00000004U);
12415 /*##################################################################### */
12418 * Register : MIO_PIN_54 @ 0XFF1800D8
12420 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
12421 * [1]- (TX RGMII data)
12422 * PSU_IOU_SLCR_MIO_PIN_54_L0_SEL 0
12424 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
12425 * ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data
12427 * PSU_IOU_SLCR_MIO_PIN_54_L1_SEL 1
12429 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12431 * PSU_IOU_SLCR_MIO_PIN_54_L2_SEL 0
12433 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g
12434 * pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_
12435 * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
12436 * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG
12437 * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I
12438 * nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se
12439 * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
12440 * PSU_IOU_SLCR_MIO_PIN_54_L3_SEL 0
12442 * Configures MIO Pin 54 peripheral interface mapping
12443 * (OFFSET, MASK, VALUE) (0XFF1800D8, 0x000000FEU ,0x00000004U)
12445 PSU_Mask_Write(IOU_SLCR_MIO_PIN_54_OFFSET, 0x000000FEU, 0x00000004U);
12446 /*##################################################################### */
12449 * Register : MIO_PIN_55 @ 0XFF1800DC
12451 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
12452 * [2]- (TX RGMII data)
12453 * PSU_IOU_SLCR_MIO_PIN_55_L0_SEL 0
12455 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt-
12456 * (Data flow control signal from the PHY)
12457 * PSU_IOU_SLCR_MIO_PIN_55_L1_SEL 1
12459 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12461 * PSU_IOU_SLCR_MIO_PIN_55_L2_SEL 0
12463 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g
12464 * pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy
12465 * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
12466 * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
12467 * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output
12468 * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out-
12469 * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
12470 * output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
12471 * PSU_IOU_SLCR_MIO_PIN_55_L3_SEL 0
12473 * Configures MIO Pin 55 peripheral interface mapping
12474 * (OFFSET, MASK, VALUE) (0XFF1800DC, 0x000000FEU ,0x00000004U)
12476 PSU_Mask_Write(IOU_SLCR_MIO_PIN_55_OFFSET, 0x000000FEU, 0x00000004U);
12477 /*##################################################################### */
12480 * Register : MIO_PIN_56 @ 0XFF1800E0
12482 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
12483 * [3]- (TX RGMII data)
12484 * PSU_IOU_SLCR_MIO_PIN_56_L0_SEL 0
12486 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
12487 * ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data
12489 * PSU_IOU_SLCR_MIO_PIN_56_L1_SEL 1
12491 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12493 * PSU_IOU_SLCR_MIO_PIN_56_L2_SEL 0
12495 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= g
12496 * pio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy
12497 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
12498 * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa
12499 * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi
12500 * 0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cloc
12501 * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O
12502 * utput, tracedq[2]- (Trace Port Databus)
12503 * PSU_IOU_SLCR_MIO_PIN_56_L3_SEL 0
12505 * Configures MIO Pin 56 peripheral interface mapping
12506 * (OFFSET, MASK, VALUE) (0XFF1800E0, 0x000000FEU ,0x00000004U)
12508 PSU_Mask_Write(IOU_SLCR_MIO_PIN_56_OFFSET, 0x000000FEU, 0x00000004U);
12509 /*##################################################################### */
12512 * Register : MIO_PIN_57 @ 0XFF1800E4
12514 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_
12515 * ctl- (TX RGMII control)
12516 * PSU_IOU_SLCR_MIO_PIN_57_L0_SEL 0
12518 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
12519 * ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data
12521 * PSU_IOU_SLCR_MIO_PIN_57_L1_SEL 1
12523 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12525 * PSU_IOU_SLCR_MIO_PIN_57_L2_SEL 0
12527 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= g
12528 * pio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_
12529 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
12530 * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W
12531 * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4=
12532 * spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC
12533 * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7=
12534 * trace, Output, tracedq[3]- (Trace Port Databus)
12535 * PSU_IOU_SLCR_MIO_PIN_57_L3_SEL 0
12537 * Configures MIO Pin 57 peripheral interface mapping
12538 * (OFFSET, MASK, VALUE) (0XFF1800E4, 0x000000FEU ,0x00000004U)
12540 PSU_Mask_Write(IOU_SLCR_MIO_PIN_57_OFFSET, 0x000000FEU, 0x00000004U);
12541 /*##################################################################### */
12544 * Register : MIO_PIN_58 @ 0XFF1800E8
12546 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c
12547 * lk- (RX RGMII clock)
12548 * PSU_IOU_SLCR_MIO_PIN_58_L0_SEL 0
12550 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp-
12551 * (Asserted to end or interrupt transfers)
12552 * PSU_IOU_SLCR_MIO_PIN_58_L1_SEL 1
12554 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12556 * PSU_IOU_SLCR_MIO_PIN_58_L2_SEL 0
12558 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g
12559 * pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_
12560 * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
12561 * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
12562 * TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl
12563 * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu
12564 * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (
12565 * Trace Port Databus)
12566 * PSU_IOU_SLCR_MIO_PIN_58_L3_SEL 0
12568 * Configures MIO Pin 58 peripheral interface mapping
12569 * (OFFSET, MASK, VALUE) (0XFF1800E8, 0x000000FEU ,0x00000004U)
12571 PSU_Mask_Write(IOU_SLCR_MIO_PIN_58_OFFSET, 0x000000FEU, 0x00000004U);
12572 /*##################################################################### */
12575 * Register : MIO_PIN_59 @ 0XFF1800EC
12577 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
12578 * 0]- (RX RGMII data)
12579 * PSU_IOU_SLCR_MIO_PIN_59_L0_SEL 0
12581 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
12582 * ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data
12584 * PSU_IOU_SLCR_MIO_PIN_59_L1_SEL 1
12586 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12588 * PSU_IOU_SLCR_MIO_PIN_59_L2_SEL 0
12590 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g
12591 * pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy
12592 * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
12593 * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
12594 * TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O
12595 * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR
12596 * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D
12598 * PSU_IOU_SLCR_MIO_PIN_59_L3_SEL 0
12600 * Configures MIO Pin 59 peripheral interface mapping
12601 * (OFFSET, MASK, VALUE) (0XFF1800EC, 0x000000FEU ,0x00000004U)
12603 PSU_Mask_Write(IOU_SLCR_MIO_PIN_59_OFFSET, 0x000000FEU, 0x00000004U);
12604 /*##################################################################### */
12607 * Register : MIO_PIN_60 @ 0XFF1800F0
12609 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
12610 * 1]- (RX RGMII data)
12611 * PSU_IOU_SLCR_MIO_PIN_60_L0_SEL 0
12613 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
12614 * ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data
12616 * PSU_IOU_SLCR_MIO_PIN_60_L1_SEL 1
12618 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12620 * PSU_IOU_SLCR_MIO_PIN_60_L2_SEL 0
12622 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g
12623 * pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy
12624 * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
12625 * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA
12626 * G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1,
12627 * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt
12628 * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
12629 * PSU_IOU_SLCR_MIO_PIN_60_L3_SEL 0
12631 * Configures MIO Pin 60 peripheral interface mapping
12632 * (OFFSET, MASK, VALUE) (0XFF1800F0, 0x000000FEU ,0x00000004U)
12634 PSU_Mask_Write(IOU_SLCR_MIO_PIN_60_OFFSET, 0x000000FEU, 0x00000004U);
12635 /*##################################################################### */
12638 * Register : MIO_PIN_61 @ 0XFF1800F4
12640 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
12641 * 2]- (RX RGMII data)
12642 * PSU_IOU_SLCR_MIO_PIN_61_L0_SEL 0
12644 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
12645 * ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data
12647 * PSU_IOU_SLCR_MIO_PIN_61_L1_SEL 1
12649 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12651 * PSU_IOU_SLCR_MIO_PIN_61_L2_SEL 0
12653 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= g
12654 * pio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_
12655 * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
12656 * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
12657 * TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output,
12658 * spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out-
12659 * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input
12660 * ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
12661 * PSU_IOU_SLCR_MIO_PIN_61_L3_SEL 0
12663 * Configures MIO Pin 61 peripheral interface mapping
12664 * (OFFSET, MASK, VALUE) (0XFF1800F4, 0x000000FEU ,0x00000004U)
12666 PSU_Mask_Write(IOU_SLCR_MIO_PIN_61_OFFSET, 0x000000FEU, 0x00000004U);
12667 /*##################################################################### */
12670 * Register : MIO_PIN_62 @ 0XFF1800F8
12672 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
12673 * 3]- (RX RGMII data)
12674 * PSU_IOU_SLCR_MIO_PIN_62_L0_SEL 0
12676 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
12677 * ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data
12679 * PSU_IOU_SLCR_MIO_PIN_62_L1_SEL 1
12681 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12683 * PSU_IOU_SLCR_MIO_PIN_62_L2_SEL 0
12685 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0=
12686 * gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_ph
12687 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
12688 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
12689 * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp
12690 * i1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clo
12691 * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu
12692 * t, tracedq[8]- (Trace Port Databus)
12693 * PSU_IOU_SLCR_MIO_PIN_62_L3_SEL 0
12695 * Configures MIO Pin 62 peripheral interface mapping
12696 * (OFFSET, MASK, VALUE) (0XFF1800F8, 0x000000FEU ,0x00000004U)
12698 PSU_Mask_Write(IOU_SLCR_MIO_PIN_62_OFFSET, 0x000000FEU, 0x00000004U);
12699 /*##################################################################### */
12702 * Register : MIO_PIN_63 @ 0XFF1800FC
12704 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c
12705 * tl- (RX RGMII control )
12706 * PSU_IOU_SLCR_MIO_PIN_63_L0_SEL 0
12708 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
12709 * ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data
12711 * PSU_IOU_SLCR_MIO_PIN_63_L1_SEL 1
12713 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
12715 * PSU_IOU_SLCR_MIO_PIN_63_L2_SEL 0
12717 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0=
12718 * gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_p
12719 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
12720 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
12721 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal)
12722 * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (
12723 * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
12724 * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
12725 * PSU_IOU_SLCR_MIO_PIN_63_L3_SEL 0
12727 * Configures MIO Pin 63 peripheral interface mapping
12728 * (OFFSET, MASK, VALUE) (0XFF1800FC, 0x000000FEU ,0x00000004U)
12730 PSU_Mask_Write(IOU_SLCR_MIO_PIN_63_OFFSET, 0x000000FEU, 0x00000004U);
12731 /*##################################################################### */
12734 * Register : MIO_PIN_64 @ 0XFF180100
12736 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_
12737 * clk- (TX RGMII clock)
12738 * PSU_IOU_SLCR_MIO_PIN_64_L0_SEL 1
12740 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_i
12742 * PSU_IOU_SLCR_MIO_PIN_64_L1_SEL 0
12744 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out-
12745 * (SDSDIO clock) 2= Not Used 3= Not Used
12746 * PSU_IOU_SLCR_MIO_PIN_64_L2_SEL 0
12748 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0=
12749 * gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_p
12750 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
12751 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
12752 * Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4
12753 * = spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in-
12754 * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7=
12755 * trace, Output, tracedq[10]- (Trace Port Databus)
12756 * PSU_IOU_SLCR_MIO_PIN_64_L3_SEL 0
12758 * Configures MIO Pin 64 peripheral interface mapping
12759 * (OFFSET, MASK, VALUE) (0XFF180100, 0x000000FEU ,0x00000002U)
12761 PSU_Mask_Write(IOU_SLCR_MIO_PIN_64_OFFSET, 0x000000FEU, 0x00000002U);
12762 /*##################################################################### */
12765 * Register : MIO_PIN_65 @ 0XFF180104
12767 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
12768 * [0]- (TX RGMII data)
12769 * PSU_IOU_SLCR_MIO_PIN_65_L0_SEL 1
12771 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir-
12772 * (Data bus direction control)
12773 * PSU_IOU_SLCR_MIO_PIN_65_L1_SEL 0
12775 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD
12776 * card detect from connector) 2= Not Used 3= Not Used
12777 * PSU_IOU_SLCR_MIO_PIN_65_L2_SEL 0
12779 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0=
12780 * gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_ph
12781 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
12782 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
12783 * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI M
12784 * aster Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= u
12785 * a1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace
12786 * dq[11]- (Trace Port Databus)
12787 * PSU_IOU_SLCR_MIO_PIN_65_L3_SEL 0
12789 * Configures MIO Pin 65 peripheral interface mapping
12790 * (OFFSET, MASK, VALUE) (0XFF180104, 0x000000FEU ,0x00000002U)
12792 PSU_Mask_Write(IOU_SLCR_MIO_PIN_65_OFFSET, 0x000000FEU, 0x00000002U);
12793 /*##################################################################### */
12796 * Register : MIO_PIN_66 @ 0XFF180108
12798 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
12799 * [1]- (TX RGMII data)
12800 * PSU_IOU_SLCR_MIO_PIN_66_L0_SEL 1
12802 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
12803 * ta[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data
12805 * PSU_IOU_SLCR_MIO_PIN_66_L1_SEL 0
12807 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com
12808 * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not
12810 * PSU_IOU_SLCR_MIO_PIN_66_L2_SEL 0
12812 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0=
12813 * gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_ph
12814 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
12815 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
12816 * atch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Mast
12817 * er Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_
12818 * rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
12820 * PSU_IOU_SLCR_MIO_PIN_66_L3_SEL 0
12822 * Configures MIO Pin 66 peripheral interface mapping
12823 * (OFFSET, MASK, VALUE) (0XFF180108, 0x000000FEU ,0x00000002U)
12825 PSU_Mask_Write(IOU_SLCR_MIO_PIN_66_OFFSET, 0x000000FEU, 0x00000002U);
12826 /*##################################################################### */
12829 * Register : MIO_PIN_67 @ 0XFF18010C
12831 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
12832 * [2]- (TX RGMII data)
12833 * PSU_IOU_SLCR_MIO_PIN_67_L0_SEL 1
12835 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt-
12836 * (Data flow control signal from the PHY)
12837 * PSU_IOU_SLCR_MIO_PIN_67_L1_SEL 0
12839 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]-
12840 * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= N
12841 * ot Used 3= Not Used
12842 * PSU_IOU_SLCR_MIO_PIN_67_L2_SEL 0
12844 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0=
12845 * gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_p
12846 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
12847 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
12848 * (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Maste
12849 * r Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= tt
12850 * c2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd-
12851 * (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace
12853 * PSU_IOU_SLCR_MIO_PIN_67_L3_SEL 0
12855 * Configures MIO Pin 67 peripheral interface mapping
12856 * (OFFSET, MASK, VALUE) (0XFF18010C, 0x000000FEU ,0x00000002U)
12858 PSU_Mask_Write(IOU_SLCR_MIO_PIN_67_OFFSET, 0x000000FEU, 0x00000002U);
12859 /*##################################################################### */
12862 * Register : MIO_PIN_68 @ 0XFF180110
12864 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
12865 * [3]- (TX RGMII data)
12866 * PSU_IOU_SLCR_MIO_PIN_68_L0_SEL 1
12868 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
12869 * ta[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data
12871 * PSU_IOU_SLCR_MIO_PIN_68_L1_SEL 0
12873 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]-
12874 * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= N
12875 * ot Used 3= Not Used
12876 * PSU_IOU_SLCR_MIO_PIN_68_L2_SEL 0
12878 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0=
12879 * gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_p
12880 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
12881 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
12882 * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s
12883 * pi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl
12884 * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
12885 * Output, tracedq[14]- (Trace Port Databus)
12886 * PSU_IOU_SLCR_MIO_PIN_68_L3_SEL 0
12888 * Configures MIO Pin 68 peripheral interface mapping
12889 * (OFFSET, MASK, VALUE) (0XFF180110, 0x000000FEU ,0x00000002U)
12891 PSU_Mask_Write(IOU_SLCR_MIO_PIN_68_OFFSET, 0x000000FEU, 0x00000002U);
12892 /*##################################################################### */
12895 * Register : MIO_PIN_69 @ 0XFF180114
12897 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_
12898 * ctl- (TX RGMII control)
12899 * PSU_IOU_SLCR_MIO_PIN_69_L0_SEL 1
12901 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
12902 * ta[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data
12904 * PSU_IOU_SLCR_MIO_PIN_69_L1_SEL 0
12906 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]-
12907 * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s
12908 * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
12909 * PSU_IOU_SLCR_MIO_PIN_69_L2_SEL 0
12911 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0=
12912 * gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_ph
12913 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
12914 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
12915 * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4
12916 * = spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T
12917 * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
12918 * 7= trace, Output, tracedq[15]- (Trace Port Databus)
12919 * PSU_IOU_SLCR_MIO_PIN_69_L3_SEL 0
12921 * Configures MIO Pin 69 peripheral interface mapping
12922 * (OFFSET, MASK, VALUE) (0XFF180114, 0x000000FEU ,0x00000002U)
12924 PSU_Mask_Write(IOU_SLCR_MIO_PIN_69_OFFSET, 0x000000FEU, 0x00000002U);
12925 /*##################################################################### */
12928 * Register : MIO_PIN_70 @ 0XFF180118
12930 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c
12931 * lk- (RX RGMII clock)
12932 * PSU_IOU_SLCR_MIO_PIN_70_L0_SEL 1
12934 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp-
12935 * (Asserted to end or interrupt transfers)
12936 * PSU_IOU_SLCR_MIO_PIN_70_L1_SEL 0
12938 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]-
12939 * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s
12940 * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
12941 * PSU_IOU_SLCR_MIO_PIN_70_L2_SEL 0
12943 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0=
12944 * gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_ph
12945 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
12946 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
12947 * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4=
12948 * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (
12949 * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U
12951 * PSU_IOU_SLCR_MIO_PIN_70_L3_SEL 0
12953 * Configures MIO Pin 70 peripheral interface mapping
12954 * (OFFSET, MASK, VALUE) (0XFF180118, 0x000000FEU ,0x00000002U)
12956 PSU_Mask_Write(IOU_SLCR_MIO_PIN_70_OFFSET, 0x000000FEU, 0x00000002U);
12957 /*##################################################################### */
12960 * Register : MIO_PIN_71 @ 0XFF18011C
12962 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
12963 * 0]- (RX RGMII data)
12964 * PSU_IOU_SLCR_MIO_PIN_71_L0_SEL 1
12966 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
12967 * ta[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data
12969 * PSU_IOU_SLCR_MIO_PIN_71_L1_SEL 0
12971 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]-
12972 * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s
12973 * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
12974 * t[0]- (8-bit Data bus) 3= Not Used
12975 * PSU_IOU_SLCR_MIO_PIN_71_L2_SEL 0
12977 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0=
12978 * gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_p
12979 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
12980 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
12981 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI
12982 * Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6=
12983 * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
12984 * PSU_IOU_SLCR_MIO_PIN_71_L3_SEL 0
12986 * Configures MIO Pin 71 peripheral interface mapping
12987 * (OFFSET, MASK, VALUE) (0XFF18011C, 0x000000FEU ,0x00000002U)
12989 PSU_Mask_Write(IOU_SLCR_MIO_PIN_71_OFFSET, 0x000000FEU, 0x00000002U);
12990 /*##################################################################### */
12993 * Register : MIO_PIN_72 @ 0XFF180120
12995 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
12996 * 1]- (RX RGMII data)
12997 * PSU_IOU_SLCR_MIO_PIN_72_L0_SEL 1
12999 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
13000 * ta[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data
13002 * PSU_IOU_SLCR_MIO_PIN_72_L1_SEL 0
13004 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]-
13005 * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s
13006 * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
13007 * t[1]- (8-bit Data bus) 3= Not Used
13008 * PSU_IOU_SLCR_MIO_PIN_72_L2_SEL 0
13010 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0=
13011 * gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_p
13012 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
13013 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
13014 * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas
13015 * ter Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter seri
13016 * al output) 7= Not Used
13017 * PSU_IOU_SLCR_MIO_PIN_72_L3_SEL 0
13019 * Configures MIO Pin 72 peripheral interface mapping
13020 * (OFFSET, MASK, VALUE) (0XFF180120, 0x000000FEU ,0x00000002U)
13022 PSU_Mask_Write(IOU_SLCR_MIO_PIN_72_OFFSET, 0x000000FEU, 0x00000002U);
13023 /*##################################################################### */
13026 * Register : MIO_PIN_73 @ 0XFF180124
13028 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
13029 * 2]- (RX RGMII data)
13030 * PSU_IOU_SLCR_MIO_PIN_73_L0_SEL 1
13032 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
13033 * ta[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data
13035 * PSU_IOU_SLCR_MIO_PIN_73_L1_SEL 0
13037 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]-
13038 * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s
13039 * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
13040 * t[2]- (8-bit Data bus) 3= Not Used
13041 * PSU_IOU_SLCR_MIO_PIN_73_L2_SEL 0
13043 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0=
13044 * gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_ph
13045 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
13046 * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
13047 * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master
13048 * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not
13049 * Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
13050 * PSU_IOU_SLCR_MIO_PIN_73_L3_SEL 0
13052 * Configures MIO Pin 73 peripheral interface mapping
13053 * (OFFSET, MASK, VALUE) (0XFF180124, 0x000000FEU ,0x00000002U)
13055 PSU_Mask_Write(IOU_SLCR_MIO_PIN_73_OFFSET, 0x000000FEU, 0x00000002U);
13056 /*##################################################################### */
13059 * Register : MIO_PIN_74 @ 0XFF180128
13061 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
13062 * 3]- (RX RGMII data)
13063 * PSU_IOU_SLCR_MIO_PIN_74_L0_SEL 1
13065 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
13066 * ta[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data
13068 * PSU_IOU_SLCR_MIO_PIN_74_L1_SEL 0
13070 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]-
13071 * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s
13072 * d1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
13073 * t[3]- (8-bit Data bus) 3= Not Used
13074 * PSU_IOU_SLCR_MIO_PIN_74_L2_SEL 0
13076 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0=
13077 * gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_ph
13078 * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
13079 * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
13080 * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp
13081 * i1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (
13082 * UART receiver serial input) 7= Not Used
13083 * PSU_IOU_SLCR_MIO_PIN_74_L3_SEL 0
13085 * Configures MIO Pin 74 peripheral interface mapping
13086 * (OFFSET, MASK, VALUE) (0XFF180128, 0x000000FEU ,0x00000002U)
13088 PSU_Mask_Write(IOU_SLCR_MIO_PIN_74_OFFSET, 0x000000FEU, 0x00000002U);
13089 /*##################################################################### */
13092 * Register : MIO_PIN_75 @ 0XFF18012C
13094 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c
13095 * tl- (RX RGMII control )
13096 * PSU_IOU_SLCR_MIO_PIN_75_L0_SEL 1
13098 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
13099 * ta[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data
13101 * PSU_IOU_SLCR_MIO_PIN_75_L1_SEL 0
13103 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow-
13104 * (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1
13105 * , Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
13106 * PSU_IOU_SLCR_MIO_PIN_75_L2_SEL 0
13108 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0=
13109 * gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_p
13110 * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
13111 * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
13112 * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal)
13113 * 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_t
13114 * xd- (UART transmitter serial output) 7= Not Used
13115 * PSU_IOU_SLCR_MIO_PIN_75_L3_SEL 0
13117 * Configures MIO Pin 75 peripheral interface mapping
13118 * (OFFSET, MASK, VALUE) (0XFF18012C, 0x000000FEU ,0x00000002U)
13120 PSU_Mask_Write(IOU_SLCR_MIO_PIN_75_OFFSET, 0x000000FEU, 0x00000002U);
13121 /*##################################################################### */
13124 * Register : MIO_PIN_76 @ 0XFF180130
13126 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
13127 * PSU_IOU_SLCR_MIO_PIN_76_L0_SEL 0
13129 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13130 * PSU_IOU_SLCR_MIO_PIN_76_L1_SEL 0
13132 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca
13133 * rd write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO
13134 * clock) 3= Not Used
13135 * PSU_IOU_SLCR_MIO_PIN_76_L2_SEL 0
13137 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0=
13138 * gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_p
13139 * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
13140 * 2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDI
13141 * O Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2
13142 * _mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used
13143 * PSU_IOU_SLCR_MIO_PIN_76_L3_SEL 6
13145 * Configures MIO Pin 76 peripheral interface mapping
13146 * (OFFSET, MASK, VALUE) (0XFF180130, 0x000000FEU ,0x000000C0U)
13148 PSU_Mask_Write(IOU_SLCR_MIO_PIN_76_OFFSET, 0x000000FEU, 0x000000C0U);
13149 /*##################################################################### */
13152 * Register : MIO_PIN_77 @ 0XFF180134
13154 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
13155 * PSU_IOU_SLCR_MIO_PIN_77_L0_SEL 0
13157 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13158 * PSU_IOU_SLCR_MIO_PIN_77_L1_SEL 0
13160 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio
13161 * 1_cd_n- (SD card detect from connector) 3= Not Used
13162 * PSU_IOU_SLCR_MIO_PIN_77_L2_SEL 0
13164 * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0=
13165 * gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_ph
13166 * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
13167 * c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (M
13168 * DIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input,
13169 * gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5
13170 * = mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_ou
13171 * t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Outp
13172 * ut, gem3_mdio_out- (MDIO Data) 7= Not Used
13173 * PSU_IOU_SLCR_MIO_PIN_77_L3_SEL 6
13175 * Configures MIO Pin 77 peripheral interface mapping
13176 * (OFFSET, MASK, VALUE) (0XFF180134, 0x000000FEU ,0x000000C0U)
13178 PSU_Mask_Write(IOU_SLCR_MIO_PIN_77_OFFSET, 0x000000FEU, 0x000000C0U);
13179 /*##################################################################### */
13182 * Register : MIO_MST_TRI0 @ 0XFF180204
13184 * Master Tri-state Enable for pin 0, active high
13185 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI 0
13187 * Master Tri-state Enable for pin 1, active high
13188 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI 0
13190 * Master Tri-state Enable for pin 2, active high
13191 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI 0
13193 * Master Tri-state Enable for pin 3, active high
13194 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI 0
13196 * Master Tri-state Enable for pin 4, active high
13197 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI 0
13199 * Master Tri-state Enable for pin 5, active high
13200 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI 0
13202 * Master Tri-state Enable for pin 6, active high
13203 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI 0
13205 * Master Tri-state Enable for pin 7, active high
13206 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI 0
13208 * Master Tri-state Enable for pin 8, active high
13209 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI 0
13211 * Master Tri-state Enable for pin 9, active high
13212 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI 0
13214 * Master Tri-state Enable for pin 10, active high
13215 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI 0
13217 * Master Tri-state Enable for pin 11, active high
13218 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI 0
13220 * Master Tri-state Enable for pin 12, active high
13221 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI 0
13223 * Master Tri-state Enable for pin 13, active high
13224 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI 0
13226 * Master Tri-state Enable for pin 14, active high
13227 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI 0
13229 * Master Tri-state Enable for pin 15, active high
13230 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI 0
13232 * Master Tri-state Enable for pin 16, active high
13233 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI 0
13235 * Master Tri-state Enable for pin 17, active high
13236 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI 0
13238 * Master Tri-state Enable for pin 18, active high
13239 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI 1
13241 * Master Tri-state Enable for pin 19, active high
13242 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI 0
13244 * Master Tri-state Enable for pin 20, active high
13245 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI 0
13247 * Master Tri-state Enable for pin 21, active high
13248 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI 1
13250 * Master Tri-state Enable for pin 22, active high
13251 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI 0
13253 * Master Tri-state Enable for pin 23, active high
13254 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI 0
13256 * Master Tri-state Enable for pin 24, active high
13257 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI 0
13259 * Master Tri-state Enable for pin 25, active high
13260 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI 1
13262 * Master Tri-state Enable for pin 26, active high
13263 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 0
13265 * Master Tri-state Enable for pin 27, active high
13266 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI 0
13268 * Master Tri-state Enable for pin 28, active high
13269 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI 1
13271 * Master Tri-state Enable for pin 29, active high
13272 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI 0
13274 * Master Tri-state Enable for pin 30, active high
13275 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI 1
13277 * Master Tri-state Enable for pin 31, active high
13278 * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI 0
13280 * MIO pin Tri-state Enables, 31:0
13281 * (OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x52240000U)
13283 PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI0_OFFSET,
13284 0xFFFFFFFFU, 0x52240000U);
13285 /*##################################################################### */
13288 * Register : MIO_MST_TRI1 @ 0XFF180208
13290 * Master Tri-state Enable for pin 32, active high
13291 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI 0
13293 * Master Tri-state Enable for pin 33, active high
13294 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI 0
13296 * Master Tri-state Enable for pin 34, active high
13297 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI 0
13299 * Master Tri-state Enable for pin 35, active high
13300 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI 0
13302 * Master Tri-state Enable for pin 36, active high
13303 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI 0
13305 * Master Tri-state Enable for pin 37, active high
13306 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI 0
13308 * Master Tri-state Enable for pin 38, active high
13309 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI 0
13311 * Master Tri-state Enable for pin 39, active high
13312 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI 0
13314 * Master Tri-state Enable for pin 40, active high
13315 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI 0
13317 * Master Tri-state Enable for pin 41, active high
13318 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI 0
13320 * Master Tri-state Enable for pin 42, active high
13321 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI 0
13323 * Master Tri-state Enable for pin 43, active high
13324 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI 0
13326 * Master Tri-state Enable for pin 44, active high
13327 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI 1
13329 * Master Tri-state Enable for pin 45, active high
13330 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI 1
13332 * Master Tri-state Enable for pin 46, active high
13333 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI 0
13335 * Master Tri-state Enable for pin 47, active high
13336 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI 0
13338 * Master Tri-state Enable for pin 48, active high
13339 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI 0
13341 * Master Tri-state Enable for pin 49, active high
13342 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI 0
13344 * Master Tri-state Enable for pin 50, active high
13345 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI 0
13347 * Master Tri-state Enable for pin 51, active high
13348 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI 0
13350 * Master Tri-state Enable for pin 52, active high
13351 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI 1
13353 * Master Tri-state Enable for pin 53, active high
13354 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI 1
13356 * Master Tri-state Enable for pin 54, active high
13357 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI 0
13359 * Master Tri-state Enable for pin 55, active high
13360 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI 1
13362 * Master Tri-state Enable for pin 56, active high
13363 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI 0
13365 * Master Tri-state Enable for pin 57, active high
13366 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI 0
13368 * Master Tri-state Enable for pin 58, active high
13369 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI 0
13371 * Master Tri-state Enable for pin 59, active high
13372 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI 0
13374 * Master Tri-state Enable for pin 60, active high
13375 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI 0
13377 * Master Tri-state Enable for pin 61, active high
13378 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI 0
13380 * Master Tri-state Enable for pin 62, active high
13381 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI 0
13383 * Master Tri-state Enable for pin 63, active high
13384 * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI 0
13386 * MIO pin Tri-state Enables, 63:32
13387 * (OFFSET, MASK, VALUE) (0XFF180208, 0xFFFFFFFFU ,0x00B03000U)
13389 PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI1_OFFSET,
13390 0xFFFFFFFFU, 0x00B03000U);
13391 /*##################################################################### */
13394 * Register : MIO_MST_TRI2 @ 0XFF18020C
13396 * Master Tri-state Enable for pin 64, active high
13397 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI 0
13399 * Master Tri-state Enable for pin 65, active high
13400 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI 0
13402 * Master Tri-state Enable for pin 66, active high
13403 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI 0
13405 * Master Tri-state Enable for pin 67, active high
13406 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI 0
13408 * Master Tri-state Enable for pin 68, active high
13409 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI 0
13411 * Master Tri-state Enable for pin 69, active high
13412 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI 0
13414 * Master Tri-state Enable for pin 70, active high
13415 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI 1
13417 * Master Tri-state Enable for pin 71, active high
13418 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI 1
13420 * Master Tri-state Enable for pin 72, active high
13421 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI 1
13423 * Master Tri-state Enable for pin 73, active high
13424 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI 1
13426 * Master Tri-state Enable for pin 74, active high
13427 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI 1
13429 * Master Tri-state Enable for pin 75, active high
13430 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI 1
13432 * Master Tri-state Enable for pin 76, active high
13433 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI 0
13435 * Master Tri-state Enable for pin 77, active high
13436 * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI 0
13438 * MIO pin Tri-state Enables, 77:64
13439 * (OFFSET, MASK, VALUE) (0XFF18020C, 0x00003FFFU ,0x00000FC0U)
13441 PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI2_OFFSET,
13442 0x00003FFFU, 0x00000FC0U);
13443 /*##################################################################### */
13446 * Register : bank0_ctrl0 @ 0XFF180138
13448 * Each bit applies to a single IO. Bit 0 for MIO[0].
13449 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0 1
13451 * Each bit applies to a single IO. Bit 0 for MIO[0].
13452 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1 1
13454 * Each bit applies to a single IO. Bit 0 for MIO[0].
13455 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2 1
13457 * Each bit applies to a single IO. Bit 0 for MIO[0].
13458 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3 1
13460 * Each bit applies to a single IO. Bit 0 for MIO[0].
13461 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4 1
13463 * Each bit applies to a single IO. Bit 0 for MIO[0].
13464 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5 1
13466 * Each bit applies to a single IO. Bit 0 for MIO[0].
13467 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6 1
13469 * Each bit applies to a single IO. Bit 0 for MIO[0].
13470 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7 1
13472 * Each bit applies to a single IO. Bit 0 for MIO[0].
13473 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8 1
13475 * Each bit applies to a single IO. Bit 0 for MIO[0].
13476 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9 1
13478 * Each bit applies to a single IO. Bit 0 for MIO[0].
13479 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10 1
13481 * Each bit applies to a single IO. Bit 0 for MIO[0].
13482 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11 1
13484 * Each bit applies to a single IO. Bit 0 for MIO[0].
13485 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12 1
13487 * Each bit applies to a single IO. Bit 0 for MIO[0].
13488 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13 1
13490 * Each bit applies to a single IO. Bit 0 for MIO[0].
13491 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14 1
13493 * Each bit applies to a single IO. Bit 0 for MIO[0].
13494 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15 1
13496 * Each bit applies to a single IO. Bit 0 for MIO[0].
13497 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16 1
13499 * Each bit applies to a single IO. Bit 0 for MIO[0].
13500 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17 1
13502 * Each bit applies to a single IO. Bit 0 for MIO[0].
13503 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18 1
13505 * Each bit applies to a single IO. Bit 0 for MIO[0].
13506 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19 1
13508 * Each bit applies to a single IO. Bit 0 for MIO[0].
13509 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20 1
13511 * Each bit applies to a single IO. Bit 0 for MIO[0].
13512 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21 1
13514 * Each bit applies to a single IO. Bit 0 for MIO[0].
13515 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22 1
13517 * Each bit applies to a single IO. Bit 0 for MIO[0].
13518 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23 1
13520 * Each bit applies to a single IO. Bit 0 for MIO[0].
13521 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24 1
13523 * Each bit applies to a single IO. Bit 0 for MIO[0].
13524 * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25 1
13526 * Drive0 control to MIO Bank 0 - control MIO[25:0]
13527 * (OFFSET, MASK, VALUE) (0XFF180138, 0x03FFFFFFU ,0x03FFFFFFU)
13529 PSU_Mask_Write(IOU_SLCR_BANK0_CTRL0_OFFSET,
13530 0x03FFFFFFU, 0x03FFFFFFU);
13531 /*##################################################################### */
13534 * Register : bank0_ctrl1 @ 0XFF18013C
13536 * Each bit applies to a single IO. Bit 0 for MIO[0].
13537 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0 1
13539 * Each bit applies to a single IO. Bit 0 for MIO[0].
13540 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1 1
13542 * Each bit applies to a single IO. Bit 0 for MIO[0].
13543 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2 1
13545 * Each bit applies to a single IO. Bit 0 for MIO[0].
13546 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3 1
13548 * Each bit applies to a single IO. Bit 0 for MIO[0].
13549 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4 1
13551 * Each bit applies to a single IO. Bit 0 for MIO[0].
13552 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5 1
13554 * Each bit applies to a single IO. Bit 0 for MIO[0].
13555 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6 1
13557 * Each bit applies to a single IO. Bit 0 for MIO[0].
13558 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7 1
13560 * Each bit applies to a single IO. Bit 0 for MIO[0].
13561 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8 1
13563 * Each bit applies to a single IO. Bit 0 for MIO[0].
13564 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9 1
13566 * Each bit applies to a single IO. Bit 0 for MIO[0].
13567 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10 1
13569 * Each bit applies to a single IO. Bit 0 for MIO[0].
13570 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11 1
13572 * Each bit applies to a single IO. Bit 0 for MIO[0].
13573 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12 1
13575 * Each bit applies to a single IO. Bit 0 for MIO[0].
13576 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13 1
13578 * Each bit applies to a single IO. Bit 0 for MIO[0].
13579 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14 1
13581 * Each bit applies to a single IO. Bit 0 for MIO[0].
13582 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15 1
13584 * Each bit applies to a single IO. Bit 0 for MIO[0].
13585 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16 1
13587 * Each bit applies to a single IO. Bit 0 for MIO[0].
13588 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17 1
13590 * Each bit applies to a single IO. Bit 0 for MIO[0].
13591 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18 1
13593 * Each bit applies to a single IO. Bit 0 for MIO[0].
13594 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19 1
13596 * Each bit applies to a single IO. Bit 0 for MIO[0].
13597 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20 1
13599 * Each bit applies to a single IO. Bit 0 for MIO[0].
13600 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21 1
13602 * Each bit applies to a single IO. Bit 0 for MIO[0].
13603 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22 1
13605 * Each bit applies to a single IO. Bit 0 for MIO[0].
13606 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23 1
13608 * Each bit applies to a single IO. Bit 0 for MIO[0].
13609 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24 1
13611 * Each bit applies to a single IO. Bit 0 for MIO[0].
13612 * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25 1
13614 * Drive1 control to MIO Bank 0 - control MIO[25:0]
13615 * (OFFSET, MASK, VALUE) (0XFF18013C, 0x03FFFFFFU ,0x03FFFFFFU)
13617 PSU_Mask_Write(IOU_SLCR_BANK0_CTRL1_OFFSET,
13618 0x03FFFFFFU, 0x03FFFFFFU);
13619 /*##################################################################### */
13622 * Register : bank0_ctrl3 @ 0XFF180140
13624 * Each bit applies to a single IO. Bit 0 for MIO[0].
13625 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0 0
13627 * Each bit applies to a single IO. Bit 0 for MIO[0].
13628 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1 0
13630 * Each bit applies to a single IO. Bit 0 for MIO[0].
13631 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2 0
13633 * Each bit applies to a single IO. Bit 0 for MIO[0].
13634 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3 0
13636 * Each bit applies to a single IO. Bit 0 for MIO[0].
13637 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4 0
13639 * Each bit applies to a single IO. Bit 0 for MIO[0].
13640 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5 0
13642 * Each bit applies to a single IO. Bit 0 for MIO[0].
13643 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6 0
13645 * Each bit applies to a single IO. Bit 0 for MIO[0].
13646 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7 0
13648 * Each bit applies to a single IO. Bit 0 for MIO[0].
13649 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8 0
13651 * Each bit applies to a single IO. Bit 0 for MIO[0].
13652 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9 0
13654 * Each bit applies to a single IO. Bit 0 for MIO[0].
13655 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10 0
13657 * Each bit applies to a single IO. Bit 0 for MIO[0].
13658 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11 0
13660 * Each bit applies to a single IO. Bit 0 for MIO[0].
13661 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12 0
13663 * Each bit applies to a single IO. Bit 0 for MIO[0].
13664 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13 0
13666 * Each bit applies to a single IO. Bit 0 for MIO[0].
13667 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14 0
13669 * Each bit applies to a single IO. Bit 0 for MIO[0].
13670 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15 0
13672 * Each bit applies to a single IO. Bit 0 for MIO[0].
13673 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16 0
13675 * Each bit applies to a single IO. Bit 0 for MIO[0].
13676 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17 0
13678 * Each bit applies to a single IO. Bit 0 for MIO[0].
13679 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18 0
13681 * Each bit applies to a single IO. Bit 0 for MIO[0].
13682 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19 0
13684 * Each bit applies to a single IO. Bit 0 for MIO[0].
13685 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20 0
13687 * Each bit applies to a single IO. Bit 0 for MIO[0].
13688 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21 0
13690 * Each bit applies to a single IO. Bit 0 for MIO[0].
13691 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22 0
13693 * Each bit applies to a single IO. Bit 0 for MIO[0].
13694 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23 0
13696 * Each bit applies to a single IO. Bit 0 for MIO[0].
13697 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24 0
13699 * Each bit applies to a single IO. Bit 0 for MIO[0].
13700 * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25 0
13702 * Selects either Schmitt or CMOS input for MIO Bank 0 - control MIO[25:0]
13703 * (OFFSET, MASK, VALUE) (0XFF180140, 0x03FFFFFFU ,0x00000000U)
13705 PSU_Mask_Write(IOU_SLCR_BANK0_CTRL3_OFFSET,
13706 0x03FFFFFFU, 0x00000000U);
13707 /*##################################################################### */
13710 * Register : bank0_ctrl4 @ 0XFF180144
13712 * Each bit applies to a single IO. Bit 0 for MIO[0].
13713 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0 1
13715 * Each bit applies to a single IO. Bit 0 for MIO[0].
13716 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1 1
13718 * Each bit applies to a single IO. Bit 0 for MIO[0].
13719 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2 1
13721 * Each bit applies to a single IO. Bit 0 for MIO[0].
13722 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3 1
13724 * Each bit applies to a single IO. Bit 0 for MIO[0].
13725 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4 1
13727 * Each bit applies to a single IO. Bit 0 for MIO[0].
13728 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5 1
13730 * Each bit applies to a single IO. Bit 0 for MIO[0].
13731 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6 1
13733 * Each bit applies to a single IO. Bit 0 for MIO[0].
13734 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7 1
13736 * Each bit applies to a single IO. Bit 0 for MIO[0].
13737 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8 1
13739 * Each bit applies to a single IO. Bit 0 for MIO[0].
13740 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9 1
13742 * Each bit applies to a single IO. Bit 0 for MIO[0].
13743 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10 1
13745 * Each bit applies to a single IO. Bit 0 for MIO[0].
13746 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11 1
13748 * Each bit applies to a single IO. Bit 0 for MIO[0].
13749 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12 1
13751 * Each bit applies to a single IO. Bit 0 for MIO[0].
13752 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13 1
13754 * Each bit applies to a single IO. Bit 0 for MIO[0].
13755 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14 1
13757 * Each bit applies to a single IO. Bit 0 for MIO[0].
13758 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15 1
13760 * Each bit applies to a single IO. Bit 0 for MIO[0].
13761 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16 1
13763 * Each bit applies to a single IO. Bit 0 for MIO[0].
13764 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17 1
13766 * Each bit applies to a single IO. Bit 0 for MIO[0].
13767 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18 1
13769 * Each bit applies to a single IO. Bit 0 for MIO[0].
13770 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19 1
13772 * Each bit applies to a single IO. Bit 0 for MIO[0].
13773 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20 1
13775 * Each bit applies to a single IO. Bit 0 for MIO[0].
13776 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21 1
13778 * Each bit applies to a single IO. Bit 0 for MIO[0].
13779 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22 1
13781 * Each bit applies to a single IO. Bit 0 for MIO[0].
13782 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23 1
13784 * Each bit applies to a single IO. Bit 0 for MIO[0].
13785 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24 1
13787 * Each bit applies to a single IO. Bit 0 for MIO[0].
13788 * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25 1
13790 * When mio_bank0_pull_enable is set, this selects pull up or pull down for
13791 * MIO Bank 0 - control MIO[25:0]
13792 * (OFFSET, MASK, VALUE) (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU)
13794 PSU_Mask_Write(IOU_SLCR_BANK0_CTRL4_OFFSET,
13795 0x03FFFFFFU, 0x03FFFFFFU);
13796 /*##################################################################### */
13799 * Register : bank0_ctrl5 @ 0XFF180148
13801 * Each bit applies to a single IO. Bit 0 for MIO[0].
13802 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0 1
13804 * Each bit applies to a single IO. Bit 0 for MIO[0].
13805 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1 1
13807 * Each bit applies to a single IO. Bit 0 for MIO[0].
13808 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2 1
13810 * Each bit applies to a single IO. Bit 0 for MIO[0].
13811 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3 1
13813 * Each bit applies to a single IO. Bit 0 for MIO[0].
13814 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4 1
13816 * Each bit applies to a single IO. Bit 0 for MIO[0].
13817 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5 1
13819 * Each bit applies to a single IO. Bit 0 for MIO[0].
13820 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6 1
13822 * Each bit applies to a single IO. Bit 0 for MIO[0].
13823 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7 1
13825 * Each bit applies to a single IO. Bit 0 for MIO[0].
13826 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8 1
13828 * Each bit applies to a single IO. Bit 0 for MIO[0].
13829 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9 1
13831 * Each bit applies to a single IO. Bit 0 for MIO[0].
13832 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10 1
13834 * Each bit applies to a single IO. Bit 0 for MIO[0].
13835 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11 1
13837 * Each bit applies to a single IO. Bit 0 for MIO[0].
13838 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12 1
13840 * Each bit applies to a single IO. Bit 0 for MIO[0].
13841 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13 1
13843 * Each bit applies to a single IO. Bit 0 for MIO[0].
13844 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14 1
13846 * Each bit applies to a single IO. Bit 0 for MIO[0].
13847 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15 1
13849 * Each bit applies to a single IO. Bit 0 for MIO[0].
13850 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16 1
13852 * Each bit applies to a single IO. Bit 0 for MIO[0].
13853 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17 1
13855 * Each bit applies to a single IO. Bit 0 for MIO[0].
13856 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18 1
13858 * Each bit applies to a single IO. Bit 0 for MIO[0].
13859 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19 1
13861 * Each bit applies to a single IO. Bit 0 for MIO[0].
13862 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20 1
13864 * Each bit applies to a single IO. Bit 0 for MIO[0].
13865 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21 1
13867 * Each bit applies to a single IO. Bit 0 for MIO[0].
13868 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22 1
13870 * Each bit applies to a single IO. Bit 0 for MIO[0].
13871 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23 1
13873 * Each bit applies to a single IO. Bit 0 for MIO[0].
13874 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24 1
13876 * Each bit applies to a single IO. Bit 0 for MIO[0].
13877 * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25 1
13879 * When set, this enables mio_bank0_pullupdown to selects pull up or pull d
13880 * own for MIO Bank 0 - control MIO[25:0]
13881 * (OFFSET, MASK, VALUE) (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU)
13883 PSU_Mask_Write(IOU_SLCR_BANK0_CTRL5_OFFSET,
13884 0x03FFFFFFU, 0x03FFFFFFU);
13885 /*##################################################################### */
13888 * Register : bank0_ctrl6 @ 0XFF18014C
13890 * Each bit applies to a single IO. Bit 0 for MIO[0].
13891 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0
13893 * Each bit applies to a single IO. Bit 0 for MIO[0].
13894 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0
13896 * Each bit applies to a single IO. Bit 0 for MIO[0].
13897 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0
13899 * Each bit applies to a single IO. Bit 0 for MIO[0].
13900 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0
13902 * Each bit applies to a single IO. Bit 0 for MIO[0].
13903 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0
13905 * Each bit applies to a single IO. Bit 0 for MIO[0].
13906 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0
13908 * Each bit applies to a single IO. Bit 0 for MIO[0].
13909 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0
13911 * Each bit applies to a single IO. Bit 0 for MIO[0].
13912 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0
13914 * Each bit applies to a single IO. Bit 0 for MIO[0].
13915 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0
13917 * Each bit applies to a single IO. Bit 0 for MIO[0].
13918 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0
13920 * Each bit applies to a single IO. Bit 0 for MIO[0].
13921 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0
13923 * Each bit applies to a single IO. Bit 0 for MIO[0].
13924 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0
13926 * Each bit applies to a single IO. Bit 0 for MIO[0].
13927 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0
13929 * Each bit applies to a single IO. Bit 0 for MIO[0].
13930 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0
13932 * Each bit applies to a single IO. Bit 0 for MIO[0].
13933 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0
13935 * Each bit applies to a single IO. Bit 0 for MIO[0].
13936 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0
13938 * Each bit applies to a single IO. Bit 0 for MIO[0].
13939 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0
13941 * Each bit applies to a single IO. Bit 0 for MIO[0].
13942 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0
13944 * Each bit applies to a single IO. Bit 0 for MIO[0].
13945 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0
13947 * Each bit applies to a single IO. Bit 0 for MIO[0].
13948 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0
13950 * Each bit applies to a single IO. Bit 0 for MIO[0].
13951 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0
13953 * Each bit applies to a single IO. Bit 0 for MIO[0].
13954 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0
13956 * Each bit applies to a single IO. Bit 0 for MIO[0].
13957 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0
13959 * Each bit applies to a single IO. Bit 0 for MIO[0].
13960 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0
13962 * Each bit applies to a single IO. Bit 0 for MIO[0].
13963 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0
13965 * Each bit applies to a single IO. Bit 0 for MIO[0].
13966 * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0
13968 * Slew rate control to MIO Bank 0 - control MIO[25:0]
13969 * (OFFSET, MASK, VALUE) (0XFF18014C, 0x03FFFFFFU ,0x00000000U)
13971 PSU_Mask_Write(IOU_SLCR_BANK0_CTRL6_OFFSET,
13972 0x03FFFFFFU, 0x00000000U);
13973 /*##################################################################### */
13976 * Register : bank1_ctrl0 @ 0XFF180154
13978 * Each bit applies to a single IO. Bit 0 for MIO[26].
13979 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0 1
13981 * Each bit applies to a single IO. Bit 0 for MIO[26].
13982 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1 1
13984 * Each bit applies to a single IO. Bit 0 for MIO[26].
13985 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2 1
13987 * Each bit applies to a single IO. Bit 0 for MIO[26].
13988 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3 1
13990 * Each bit applies to a single IO. Bit 0 for MIO[26].
13991 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4 1
13993 * Each bit applies to a single IO. Bit 0 for MIO[26].
13994 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5 1
13996 * Each bit applies to a single IO. Bit 0 for MIO[26].
13997 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6 1
13999 * Each bit applies to a single IO. Bit 0 for MIO[26].
14000 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7 1
14002 * Each bit applies to a single IO. Bit 0 for MIO[26].
14003 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8 1
14005 * Each bit applies to a single IO. Bit 0 for MIO[26].
14006 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9 1
14008 * Each bit applies to a single IO. Bit 0 for MIO[26].
14009 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10 1
14011 * Each bit applies to a single IO. Bit 0 for MIO[26].
14012 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11 1
14014 * Each bit applies to a single IO. Bit 0 for MIO[26].
14015 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12 1
14017 * Each bit applies to a single IO. Bit 0 for MIO[26].
14018 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13 1
14020 * Each bit applies to a single IO. Bit 0 for MIO[26].
14021 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14 1
14023 * Each bit applies to a single IO. Bit 0 for MIO[26].
14024 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15 1
14026 * Each bit applies to a single IO. Bit 0 for MIO[26].
14027 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16 1
14029 * Each bit applies to a single IO. Bit 0 for MIO[26].
14030 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17 1
14032 * Each bit applies to a single IO. Bit 0 for MIO[26].
14033 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18 1
14035 * Each bit applies to a single IO. Bit 0 for MIO[26].
14036 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19 1
14038 * Each bit applies to a single IO. Bit 0 for MIO[26].
14039 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20 1
14041 * Each bit applies to a single IO. Bit 0 for MIO[26].
14042 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21 1
14044 * Each bit applies to a single IO. Bit 0 for MIO[26].
14045 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22 1
14047 * Each bit applies to a single IO. Bit 0 for MIO[26].
14048 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23 1
14050 * Each bit applies to a single IO. Bit 0 for MIO[26].
14051 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24 1
14053 * Each bit applies to a single IO. Bit 0 for MIO[26].
14054 * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25 1
14056 * Drive0 control to MIO Bank 1 - control MIO[51:26]
14057 * (OFFSET, MASK, VALUE) (0XFF180154, 0x03FFFFFFU ,0x03FFFFFFU)
14059 PSU_Mask_Write(IOU_SLCR_BANK1_CTRL0_OFFSET,
14060 0x03FFFFFFU, 0x03FFFFFFU);
14061 /*##################################################################### */
14064 * Register : bank1_ctrl1 @ 0XFF180158
14066 * Each bit applies to a single IO. Bit 0 for MIO[26].
14067 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0 1
14069 * Each bit applies to a single IO. Bit 0 for MIO[26].
14070 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1 1
14072 * Each bit applies to a single IO. Bit 0 for MIO[26].
14073 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2 1
14075 * Each bit applies to a single IO. Bit 0 for MIO[26].
14076 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3 1
14078 * Each bit applies to a single IO. Bit 0 for MIO[26].
14079 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4 1
14081 * Each bit applies to a single IO. Bit 0 for MIO[26].
14082 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5 1
14084 * Each bit applies to a single IO. Bit 0 for MIO[26].
14085 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6 1
14087 * Each bit applies to a single IO. Bit 0 for MIO[26].
14088 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7 1
14090 * Each bit applies to a single IO. Bit 0 for MIO[26].
14091 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8 1
14093 * Each bit applies to a single IO. Bit 0 for MIO[26].
14094 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9 1
14096 * Each bit applies to a single IO. Bit 0 for MIO[26].
14097 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10 1
14099 * Each bit applies to a single IO. Bit 0 for MIO[26].
14100 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11 1
14102 * Each bit applies to a single IO. Bit 0 for MIO[26].
14103 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12 1
14105 * Each bit applies to a single IO. Bit 0 for MIO[26].
14106 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13 1
14108 * Each bit applies to a single IO. Bit 0 for MIO[26].
14109 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14 1
14111 * Each bit applies to a single IO. Bit 0 for MIO[26].
14112 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15 1
14114 * Each bit applies to a single IO. Bit 0 for MIO[26].
14115 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16 1
14117 * Each bit applies to a single IO. Bit 0 for MIO[26].
14118 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17 1
14120 * Each bit applies to a single IO. Bit 0 for MIO[26].
14121 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18 1
14123 * Each bit applies to a single IO. Bit 0 for MIO[26].
14124 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19 1
14126 * Each bit applies to a single IO. Bit 0 for MIO[26].
14127 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20 1
14129 * Each bit applies to a single IO. Bit 0 for MIO[26].
14130 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21 1
14132 * Each bit applies to a single IO. Bit 0 for MIO[26].
14133 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22 1
14135 * Each bit applies to a single IO. Bit 0 for MIO[26].
14136 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23 1
14138 * Each bit applies to a single IO. Bit 0 for MIO[26].
14139 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24 1
14141 * Each bit applies to a single IO. Bit 0 for MIO[26].
14142 * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25 1
14144 * Drive1 control to MIO Bank 1 - control MIO[51:26]
14145 * (OFFSET, MASK, VALUE) (0XFF180158, 0x03FFFFFFU ,0x03FFFFFFU)
14147 PSU_Mask_Write(IOU_SLCR_BANK1_CTRL1_OFFSET,
14148 0x03FFFFFFU, 0x03FFFFFFU);
14149 /*##################################################################### */
14152 * Register : bank1_ctrl3 @ 0XFF18015C
14154 * Each bit applies to a single IO. Bit 0 for MIO[26].
14155 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0 0
14157 * Each bit applies to a single IO. Bit 0 for MIO[26].
14158 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1 0
14160 * Each bit applies to a single IO. Bit 0 for MIO[26].
14161 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2 0
14163 * Each bit applies to a single IO. Bit 0 for MIO[26].
14164 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3 0
14166 * Each bit applies to a single IO. Bit 0 for MIO[26].
14167 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4 0
14169 * Each bit applies to a single IO. Bit 0 for MIO[26].
14170 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5 0
14172 * Each bit applies to a single IO. Bit 0 for MIO[26].
14173 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6 0
14175 * Each bit applies to a single IO. Bit 0 for MIO[26].
14176 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7 0
14178 * Each bit applies to a single IO. Bit 0 for MIO[26].
14179 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8 0
14181 * Each bit applies to a single IO. Bit 0 for MIO[26].
14182 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9 0
14184 * Each bit applies to a single IO. Bit 0 for MIO[26].
14185 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10 0
14187 * Each bit applies to a single IO. Bit 0 for MIO[26].
14188 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11 0
14190 * Each bit applies to a single IO. Bit 0 for MIO[26].
14191 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12 0
14193 * Each bit applies to a single IO. Bit 0 for MIO[26].
14194 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13 0
14196 * Each bit applies to a single IO. Bit 0 for MIO[26].
14197 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14 0
14199 * Each bit applies to a single IO. Bit 0 for MIO[26].
14200 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15 0
14202 * Each bit applies to a single IO. Bit 0 for MIO[26].
14203 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16 0
14205 * Each bit applies to a single IO. Bit 0 for MIO[26].
14206 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17 0
14208 * Each bit applies to a single IO. Bit 0 for MIO[26].
14209 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18 0
14211 * Each bit applies to a single IO. Bit 0 for MIO[26].
14212 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19 0
14214 * Each bit applies to a single IO. Bit 0 for MIO[26].
14215 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20 0
14217 * Each bit applies to a single IO. Bit 0 for MIO[26].
14218 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21 0
14220 * Each bit applies to a single IO. Bit 0 for MIO[26].
14221 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22 0
14223 * Each bit applies to a single IO. Bit 0 for MIO[26].
14224 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23 0
14226 * Each bit applies to a single IO. Bit 0 for MIO[26].
14227 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24 0
14229 * Each bit applies to a single IO. Bit 0 for MIO[26].
14230 * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25 0
14232 * Selects either Schmitt or CMOS input for MIO Bank 1 - control MIO[51:26]
14233 * (OFFSET, MASK, VALUE) (0XFF18015C, 0x03FFFFFFU ,0x00000000U)
14235 PSU_Mask_Write(IOU_SLCR_BANK1_CTRL3_OFFSET,
14236 0x03FFFFFFU, 0x00000000U);
14237 /*##################################################################### */
14240 * Register : bank1_ctrl4 @ 0XFF180160
14242 * Each bit applies to a single IO. Bit 0 for MIO[26].
14243 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0 1
14245 * Each bit applies to a single IO. Bit 0 for MIO[26].
14246 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1 1
14248 * Each bit applies to a single IO. Bit 0 for MIO[26].
14249 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2 1
14251 * Each bit applies to a single IO. Bit 0 for MIO[26].
14252 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3 1
14254 * Each bit applies to a single IO. Bit 0 for MIO[26].
14255 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4 1
14257 * Each bit applies to a single IO. Bit 0 for MIO[26].
14258 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5 1
14260 * Each bit applies to a single IO. Bit 0 for MIO[26].
14261 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6 1
14263 * Each bit applies to a single IO. Bit 0 for MIO[26].
14264 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7 1
14266 * Each bit applies to a single IO. Bit 0 for MIO[26].
14267 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8 1
14269 * Each bit applies to a single IO. Bit 0 for MIO[26].
14270 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9 1
14272 * Each bit applies to a single IO. Bit 0 for MIO[26].
14273 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10 1
14275 * Each bit applies to a single IO. Bit 0 for MIO[26].
14276 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11 1
14278 * Each bit applies to a single IO. Bit 0 for MIO[26].
14279 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12 1
14281 * Each bit applies to a single IO. Bit 0 for MIO[26].
14282 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13 1
14284 * Each bit applies to a single IO. Bit 0 for MIO[26].
14285 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14 1
14287 * Each bit applies to a single IO. Bit 0 for MIO[26].
14288 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15 1
14290 * Each bit applies to a single IO. Bit 0 for MIO[26].
14291 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16 1
14293 * Each bit applies to a single IO. Bit 0 for MIO[26].
14294 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17 1
14296 * Each bit applies to a single IO. Bit 0 for MIO[26].
14297 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18 1
14299 * Each bit applies to a single IO. Bit 0 for MIO[26].
14300 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19 1
14302 * Each bit applies to a single IO. Bit 0 for MIO[26].
14303 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20 1
14305 * Each bit applies to a single IO. Bit 0 for MIO[26].
14306 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21 1
14308 * Each bit applies to a single IO. Bit 0 for MIO[26].
14309 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22 1
14311 * Each bit applies to a single IO. Bit 0 for MIO[26].
14312 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23 1
14314 * Each bit applies to a single IO. Bit 0 for MIO[26].
14315 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24 1
14317 * Each bit applies to a single IO. Bit 0 for MIO[26].
14318 * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25 1
14320 * When mio_bank1_pull_enable is set, this selects pull up or pull down for
14321 * MIO Bank 1 - control MIO[51:26]
14322 * (OFFSET, MASK, VALUE) (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU)
14324 PSU_Mask_Write(IOU_SLCR_BANK1_CTRL4_OFFSET,
14325 0x03FFFFFFU, 0x03FFFFFFU);
14326 /*##################################################################### */
14329 * Register : bank1_ctrl5 @ 0XFF180164
14331 * Each bit applies to a single IO. Bit 0 for MIO[26].
14332 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0 1
14334 * Each bit applies to a single IO. Bit 0 for MIO[26].
14335 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1 1
14337 * Each bit applies to a single IO. Bit 0 for MIO[26].
14338 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2 1
14340 * Each bit applies to a single IO. Bit 0 for MIO[26].
14341 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3 1
14343 * Each bit applies to a single IO. Bit 0 for MIO[26].
14344 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4 1
14346 * Each bit applies to a single IO. Bit 0 for MIO[26].
14347 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5 1
14349 * Each bit applies to a single IO. Bit 0 for MIO[26].
14350 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6 1
14352 * Each bit applies to a single IO. Bit 0 for MIO[26].
14353 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7 1
14355 * Each bit applies to a single IO. Bit 0 for MIO[26].
14356 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8 1
14358 * Each bit applies to a single IO. Bit 0 for MIO[26].
14359 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9 1
14361 * Each bit applies to a single IO. Bit 0 for MIO[26].
14362 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10 1
14364 * Each bit applies to a single IO. Bit 0 for MIO[26].
14365 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11 1
14367 * Each bit applies to a single IO. Bit 0 for MIO[26].
14368 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12 1
14370 * Each bit applies to a single IO. Bit 0 for MIO[26].
14371 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13 1
14373 * Each bit applies to a single IO. Bit 0 for MIO[26].
14374 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14 1
14376 * Each bit applies to a single IO. Bit 0 for MIO[26].
14377 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15 1
14379 * Each bit applies to a single IO. Bit 0 for MIO[26].
14380 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16 1
14382 * Each bit applies to a single IO. Bit 0 for MIO[26].
14383 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17 1
14385 * Each bit applies to a single IO. Bit 0 for MIO[26].
14386 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18 1
14388 * Each bit applies to a single IO. Bit 0 for MIO[26].
14389 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19 1
14391 * Each bit applies to a single IO. Bit 0 for MIO[26].
14392 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20 1
14394 * Each bit applies to a single IO. Bit 0 for MIO[26].
14395 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21 1
14397 * Each bit applies to a single IO. Bit 0 for MIO[26].
14398 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22 1
14400 * Each bit applies to a single IO. Bit 0 for MIO[26].
14401 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23 1
14403 * Each bit applies to a single IO. Bit 0 for MIO[26].
14404 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24 1
14406 * Each bit applies to a single IO. Bit 0 for MIO[26].
14407 * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25 1
14409 * When set, this enables mio_bank1_pullupdown to selects pull up or pull d
14410 * own for MIO Bank 1 - control MIO[51:26]
14411 * (OFFSET, MASK, VALUE) (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU)
14413 PSU_Mask_Write(IOU_SLCR_BANK1_CTRL5_OFFSET,
14414 0x03FFFFFFU, 0x03FFFFFFU);
14415 /*##################################################################### */
14418 * Register : bank1_ctrl6 @ 0XFF180168
14420 * Each bit applies to a single IO. Bit 0 for MIO[26].
14421 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0
14423 * Each bit applies to a single IO. Bit 0 for MIO[26].
14424 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0
14426 * Each bit applies to a single IO. Bit 0 for MIO[26].
14427 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0
14429 * Each bit applies to a single IO. Bit 0 for MIO[26].
14430 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0
14432 * Each bit applies to a single IO. Bit 0 for MIO[26].
14433 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0
14435 * Each bit applies to a single IO. Bit 0 for MIO[26].
14436 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0
14438 * Each bit applies to a single IO. Bit 0 for MIO[26].
14439 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0
14441 * Each bit applies to a single IO. Bit 0 for MIO[26].
14442 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0
14444 * Each bit applies to a single IO. Bit 0 for MIO[26].
14445 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0
14447 * Each bit applies to a single IO. Bit 0 for MIO[26].
14448 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0
14450 * Each bit applies to a single IO. Bit 0 for MIO[26].
14451 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0
14453 * Each bit applies to a single IO. Bit 0 for MIO[26].
14454 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0
14456 * Each bit applies to a single IO. Bit 0 for MIO[26].
14457 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0
14459 * Each bit applies to a single IO. Bit 0 for MIO[26].
14460 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0
14462 * Each bit applies to a single IO. Bit 0 for MIO[26].
14463 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0
14465 * Each bit applies to a single IO. Bit 0 for MIO[26].
14466 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0
14468 * Each bit applies to a single IO. Bit 0 for MIO[26].
14469 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0
14471 * Each bit applies to a single IO. Bit 0 for MIO[26].
14472 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0
14474 * Each bit applies to a single IO. Bit 0 for MIO[26].
14475 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0
14477 * Each bit applies to a single IO. Bit 0 for MIO[26].
14478 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0
14480 * Each bit applies to a single IO. Bit 0 for MIO[26].
14481 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0
14483 * Each bit applies to a single IO. Bit 0 for MIO[26].
14484 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0
14486 * Each bit applies to a single IO. Bit 0 for MIO[26].
14487 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0
14489 * Each bit applies to a single IO. Bit 0 for MIO[26].
14490 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0
14492 * Each bit applies to a single IO. Bit 0 for MIO[26].
14493 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0
14495 * Each bit applies to a single IO. Bit 0 for MIO[26].
14496 * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0
14498 * Slew rate control to MIO Bank 1 - control MIO[51:26]
14499 * (OFFSET, MASK, VALUE) (0XFF180168, 0x03FFFFFFU ,0x00000000U)
14501 PSU_Mask_Write(IOU_SLCR_BANK1_CTRL6_OFFSET,
14502 0x03FFFFFFU, 0x00000000U);
14503 /*##################################################################### */
14506 * Register : bank2_ctrl0 @ 0XFF180170
14508 * Each bit applies to a single IO. Bit 0 for MIO[52].
14509 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0 1
14511 * Each bit applies to a single IO. Bit 0 for MIO[52].
14512 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1 1
14514 * Each bit applies to a single IO. Bit 0 for MIO[52].
14515 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2 1
14517 * Each bit applies to a single IO. Bit 0 for MIO[52].
14518 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3 1
14520 * Each bit applies to a single IO. Bit 0 for MIO[52].
14521 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4 1
14523 * Each bit applies to a single IO. Bit 0 for MIO[52].
14524 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5 1
14526 * Each bit applies to a single IO. Bit 0 for MIO[52].
14527 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6 1
14529 * Each bit applies to a single IO. Bit 0 for MIO[52].
14530 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7 1
14532 * Each bit applies to a single IO. Bit 0 for MIO[52].
14533 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8 1
14535 * Each bit applies to a single IO. Bit 0 for MIO[52].
14536 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9 1
14538 * Each bit applies to a single IO. Bit 0 for MIO[52].
14539 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10 1
14541 * Each bit applies to a single IO. Bit 0 for MIO[52].
14542 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11 1
14544 * Each bit applies to a single IO. Bit 0 for MIO[52].
14545 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12 1
14547 * Each bit applies to a single IO. Bit 0 for MIO[52].
14548 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13 1
14550 * Each bit applies to a single IO. Bit 0 for MIO[52].
14551 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14 1
14553 * Each bit applies to a single IO. Bit 0 for MIO[52].
14554 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15 1
14556 * Each bit applies to a single IO. Bit 0 for MIO[52].
14557 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16 1
14559 * Each bit applies to a single IO. Bit 0 for MIO[52].
14560 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17 1
14562 * Each bit applies to a single IO. Bit 0 for MIO[52].
14563 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18 1
14565 * Each bit applies to a single IO. Bit 0 for MIO[52].
14566 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19 1
14568 * Each bit applies to a single IO. Bit 0 for MIO[52].
14569 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20 1
14571 * Each bit applies to a single IO. Bit 0 for MIO[52].
14572 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21 1
14574 * Each bit applies to a single IO. Bit 0 for MIO[52].
14575 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22 1
14577 * Each bit applies to a single IO. Bit 0 for MIO[52].
14578 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23 1
14580 * Each bit applies to a single IO. Bit 0 for MIO[52].
14581 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24 1
14583 * Each bit applies to a single IO. Bit 0 for MIO[52].
14584 * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25 1
14586 * Drive0 control to MIO Bank 2 - control MIO[77:52]
14587 * (OFFSET, MASK, VALUE) (0XFF180170, 0x03FFFFFFU ,0x03FFFFFFU)
14589 PSU_Mask_Write(IOU_SLCR_BANK2_CTRL0_OFFSET,
14590 0x03FFFFFFU, 0x03FFFFFFU);
14591 /*##################################################################### */
14594 * Register : bank2_ctrl1 @ 0XFF180174
14596 * Each bit applies to a single IO. Bit 0 for MIO[52].
14597 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0 1
14599 * Each bit applies to a single IO. Bit 0 for MIO[52].
14600 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1 1
14602 * Each bit applies to a single IO. Bit 0 for MIO[52].
14603 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2 1
14605 * Each bit applies to a single IO. Bit 0 for MIO[52].
14606 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3 1
14608 * Each bit applies to a single IO. Bit 0 for MIO[52].
14609 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4 1
14611 * Each bit applies to a single IO. Bit 0 for MIO[52].
14612 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5 1
14614 * Each bit applies to a single IO. Bit 0 for MIO[52].
14615 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6 1
14617 * Each bit applies to a single IO. Bit 0 for MIO[52].
14618 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7 1
14620 * Each bit applies to a single IO. Bit 0 for MIO[52].
14621 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8 1
14623 * Each bit applies to a single IO. Bit 0 for MIO[52].
14624 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9 1
14626 * Each bit applies to a single IO. Bit 0 for MIO[52].
14627 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10 1
14629 * Each bit applies to a single IO. Bit 0 for MIO[52].
14630 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11 1
14632 * Each bit applies to a single IO. Bit 0 for MIO[52].
14633 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12 1
14635 * Each bit applies to a single IO. Bit 0 for MIO[52].
14636 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13 1
14638 * Each bit applies to a single IO. Bit 0 for MIO[52].
14639 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14 1
14641 * Each bit applies to a single IO. Bit 0 for MIO[52].
14642 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15 1
14644 * Each bit applies to a single IO. Bit 0 for MIO[52].
14645 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16 1
14647 * Each bit applies to a single IO. Bit 0 for MIO[52].
14648 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17 1
14650 * Each bit applies to a single IO. Bit 0 for MIO[52].
14651 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18 1
14653 * Each bit applies to a single IO. Bit 0 for MIO[52].
14654 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19 1
14656 * Each bit applies to a single IO. Bit 0 for MIO[52].
14657 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20 1
14659 * Each bit applies to a single IO. Bit 0 for MIO[52].
14660 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21 1
14662 * Each bit applies to a single IO. Bit 0 for MIO[52].
14663 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22 1
14665 * Each bit applies to a single IO. Bit 0 for MIO[52].
14666 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23 1
14668 * Each bit applies to a single IO. Bit 0 for MIO[52].
14669 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24 1
14671 * Each bit applies to a single IO. Bit 0 for MIO[52].
14672 * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25 1
14674 * Drive1 control to MIO Bank 2 - control MIO[77:52]
14675 * (OFFSET, MASK, VALUE) (0XFF180174, 0x03FFFFFFU ,0x03FFFFFFU)
14677 PSU_Mask_Write(IOU_SLCR_BANK2_CTRL1_OFFSET,
14678 0x03FFFFFFU, 0x03FFFFFFU);
14679 /*##################################################################### */
14682 * Register : bank2_ctrl3 @ 0XFF180178
14684 * Each bit applies to a single IO. Bit 0 for MIO[52].
14685 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0 0
14687 * Each bit applies to a single IO. Bit 0 for MIO[52].
14688 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1 0
14690 * Each bit applies to a single IO. Bit 0 for MIO[52].
14691 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2 0
14693 * Each bit applies to a single IO. Bit 0 for MIO[52].
14694 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3 0
14696 * Each bit applies to a single IO. Bit 0 for MIO[52].
14697 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4 0
14699 * Each bit applies to a single IO. Bit 0 for MIO[52].
14700 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5 0
14702 * Each bit applies to a single IO. Bit 0 for MIO[52].
14703 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6 0
14705 * Each bit applies to a single IO. Bit 0 for MIO[52].
14706 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7 0
14708 * Each bit applies to a single IO. Bit 0 for MIO[52].
14709 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8 0
14711 * Each bit applies to a single IO. Bit 0 for MIO[52].
14712 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9 0
14714 * Each bit applies to a single IO. Bit 0 for MIO[52].
14715 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10 0
14717 * Each bit applies to a single IO. Bit 0 for MIO[52].
14718 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11 0
14720 * Each bit applies to a single IO. Bit 0 for MIO[52].
14721 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12 0
14723 * Each bit applies to a single IO. Bit 0 for MIO[52].
14724 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13 0
14726 * Each bit applies to a single IO. Bit 0 for MIO[52].
14727 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14 0
14729 * Each bit applies to a single IO. Bit 0 for MIO[52].
14730 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15 0
14732 * Each bit applies to a single IO. Bit 0 for MIO[52].
14733 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16 0
14735 * Each bit applies to a single IO. Bit 0 for MIO[52].
14736 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17 0
14738 * Each bit applies to a single IO. Bit 0 for MIO[52].
14739 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18 0
14741 * Each bit applies to a single IO. Bit 0 for MIO[52].
14742 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19 0
14744 * Each bit applies to a single IO. Bit 0 for MIO[52].
14745 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20 0
14747 * Each bit applies to a single IO. Bit 0 for MIO[52].
14748 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21 0
14750 * Each bit applies to a single IO. Bit 0 for MIO[52].
14751 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22 0
14753 * Each bit applies to a single IO. Bit 0 for MIO[52].
14754 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23 0
14756 * Each bit applies to a single IO. Bit 0 for MIO[52].
14757 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24 0
14759 * Each bit applies to a single IO. Bit 0 for MIO[52].
14760 * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25 0
14762 * Selects either Schmitt or CMOS input for MIO Bank 2 - control MIO[77:52]
14763 * (OFFSET, MASK, VALUE) (0XFF180178, 0x03FFFFFFU ,0x00000000U)
14765 PSU_Mask_Write(IOU_SLCR_BANK2_CTRL3_OFFSET,
14766 0x03FFFFFFU, 0x00000000U);
14767 /*##################################################################### */
14770 * Register : bank2_ctrl4 @ 0XFF18017C
14772 * Each bit applies to a single IO. Bit 0 for MIO[52].
14773 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0 1
14775 * Each bit applies to a single IO. Bit 0 for MIO[52].
14776 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1 1
14778 * Each bit applies to a single IO. Bit 0 for MIO[52].
14779 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2 1
14781 * Each bit applies to a single IO. Bit 0 for MIO[52].
14782 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3 1
14784 * Each bit applies to a single IO. Bit 0 for MIO[52].
14785 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4 1
14787 * Each bit applies to a single IO. Bit 0 for MIO[52].
14788 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5 1
14790 * Each bit applies to a single IO. Bit 0 for MIO[52].
14791 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6 1
14793 * Each bit applies to a single IO. Bit 0 for MIO[52].
14794 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7 1
14796 * Each bit applies to a single IO. Bit 0 for MIO[52].
14797 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8 1
14799 * Each bit applies to a single IO. Bit 0 for MIO[52].
14800 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9 1
14802 * Each bit applies to a single IO. Bit 0 for MIO[52].
14803 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10 1
14805 * Each bit applies to a single IO. Bit 0 for MIO[52].
14806 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11 1
14808 * Each bit applies to a single IO. Bit 0 for MIO[52].
14809 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12 1
14811 * Each bit applies to a single IO. Bit 0 for MIO[52].
14812 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13 1
14814 * Each bit applies to a single IO. Bit 0 for MIO[52].
14815 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14 1
14817 * Each bit applies to a single IO. Bit 0 for MIO[52].
14818 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15 1
14820 * Each bit applies to a single IO. Bit 0 for MIO[52].
14821 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16 1
14823 * Each bit applies to a single IO. Bit 0 for MIO[52].
14824 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17 1
14826 * Each bit applies to a single IO. Bit 0 for MIO[52].
14827 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18 1
14829 * Each bit applies to a single IO. Bit 0 for MIO[52].
14830 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19 1
14832 * Each bit applies to a single IO. Bit 0 for MIO[52].
14833 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20 1
14835 * Each bit applies to a single IO. Bit 0 for MIO[52].
14836 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21 1
14838 * Each bit applies to a single IO. Bit 0 for MIO[52].
14839 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22 1
14841 * Each bit applies to a single IO. Bit 0 for MIO[52].
14842 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23 1
14844 * Each bit applies to a single IO. Bit 0 for MIO[52].
14845 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24 1
14847 * Each bit applies to a single IO. Bit 0 for MIO[52].
14848 * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25 1
14850 * When mio_bank2_pull_enable is set, this selects pull up or pull down for
14851 * MIO Bank 2 - control MIO[77:52]
14852 * (OFFSET, MASK, VALUE) (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU)
14854 PSU_Mask_Write(IOU_SLCR_BANK2_CTRL4_OFFSET,
14855 0x03FFFFFFU, 0x03FFFFFFU);
14856 /*##################################################################### */
14859 * Register : bank2_ctrl5 @ 0XFF180180
14861 * Each bit applies to a single IO. Bit 0 for MIO[52].
14862 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0 1
14864 * Each bit applies to a single IO. Bit 0 for MIO[52].
14865 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1 1
14867 * Each bit applies to a single IO. Bit 0 for MIO[52].
14868 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2 1
14870 * Each bit applies to a single IO. Bit 0 for MIO[52].
14871 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3 1
14873 * Each bit applies to a single IO. Bit 0 for MIO[52].
14874 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4 1
14876 * Each bit applies to a single IO. Bit 0 for MIO[52].
14877 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5 1
14879 * Each bit applies to a single IO. Bit 0 for MIO[52].
14880 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6 1
14882 * Each bit applies to a single IO. Bit 0 for MIO[52].
14883 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7 1
14885 * Each bit applies to a single IO. Bit 0 for MIO[52].
14886 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8 1
14888 * Each bit applies to a single IO. Bit 0 for MIO[52].
14889 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9 1
14891 * Each bit applies to a single IO. Bit 0 for MIO[52].
14892 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10 1
14894 * Each bit applies to a single IO. Bit 0 for MIO[52].
14895 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11 1
14897 * Each bit applies to a single IO. Bit 0 for MIO[52].
14898 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12 1
14900 * Each bit applies to a single IO. Bit 0 for MIO[52].
14901 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13 1
14903 * Each bit applies to a single IO. Bit 0 for MIO[52].
14904 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14 1
14906 * Each bit applies to a single IO. Bit 0 for MIO[52].
14907 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15 1
14909 * Each bit applies to a single IO. Bit 0 for MIO[52].
14910 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16 1
14912 * Each bit applies to a single IO. Bit 0 for MIO[52].
14913 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17 1
14915 * Each bit applies to a single IO. Bit 0 for MIO[52].
14916 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18 1
14918 * Each bit applies to a single IO. Bit 0 for MIO[52].
14919 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19 1
14921 * Each bit applies to a single IO. Bit 0 for MIO[52].
14922 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20 1
14924 * Each bit applies to a single IO. Bit 0 for MIO[52].
14925 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21 1
14927 * Each bit applies to a single IO. Bit 0 for MIO[52].
14928 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22 1
14930 * Each bit applies to a single IO. Bit 0 for MIO[52].
14931 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23 1
14933 * Each bit applies to a single IO. Bit 0 for MIO[52].
14934 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24 1
14936 * Each bit applies to a single IO. Bit 0 for MIO[52].
14937 * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25 1
14939 * When set, this enables mio_bank2_pullupdown to selects pull up or pull d
14940 * own for MIO Bank 2 - control MIO[77:52]
14941 * (OFFSET, MASK, VALUE) (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU)
14943 PSU_Mask_Write(IOU_SLCR_BANK2_CTRL5_OFFSET,
14944 0x03FFFFFFU, 0x03FFFFFFU);
14945 /*##################################################################### */
14948 * Register : bank2_ctrl6 @ 0XFF180184
14950 * Each bit applies to a single IO. Bit 0 for MIO[52].
14951 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0
14953 * Each bit applies to a single IO. Bit 0 for MIO[52].
14954 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0
14956 * Each bit applies to a single IO. Bit 0 for MIO[52].
14957 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0
14959 * Each bit applies to a single IO. Bit 0 for MIO[52].
14960 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0
14962 * Each bit applies to a single IO. Bit 0 for MIO[52].
14963 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0
14965 * Each bit applies to a single IO. Bit 0 for MIO[52].
14966 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0
14968 * Each bit applies to a single IO. Bit 0 for MIO[52].
14969 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0
14971 * Each bit applies to a single IO. Bit 0 for MIO[52].
14972 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0
14974 * Each bit applies to a single IO. Bit 0 for MIO[52].
14975 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0
14977 * Each bit applies to a single IO. Bit 0 for MIO[52].
14978 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0
14980 * Each bit applies to a single IO. Bit 0 for MIO[52].
14981 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0
14983 * Each bit applies to a single IO. Bit 0 for MIO[52].
14984 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0
14986 * Each bit applies to a single IO. Bit 0 for MIO[52].
14987 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0
14989 * Each bit applies to a single IO. Bit 0 for MIO[52].
14990 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0
14992 * Each bit applies to a single IO. Bit 0 for MIO[52].
14993 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0
14995 * Each bit applies to a single IO. Bit 0 for MIO[52].
14996 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0
14998 * Each bit applies to a single IO. Bit 0 for MIO[52].
14999 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0
15001 * Each bit applies to a single IO. Bit 0 for MIO[52].
15002 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0
15004 * Each bit applies to a single IO. Bit 0 for MIO[52].
15005 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0
15007 * Each bit applies to a single IO. Bit 0 for MIO[52].
15008 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0
15010 * Each bit applies to a single IO. Bit 0 for MIO[52].
15011 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0
15013 * Each bit applies to a single IO. Bit 0 for MIO[52].
15014 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0
15016 * Each bit applies to a single IO. Bit 0 for MIO[52].
15017 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0
15019 * Each bit applies to a single IO. Bit 0 for MIO[52].
15020 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0
15022 * Each bit applies to a single IO. Bit 0 for MIO[52].
15023 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0
15025 * Each bit applies to a single IO. Bit 0 for MIO[52].
15026 * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0
15028 * Slew rate control to MIO Bank 2 - control MIO[77:52]
15029 * (OFFSET, MASK, VALUE) (0XFF180184, 0x03FFFFFFU ,0x00000000U)
15031 PSU_Mask_Write(IOU_SLCR_BANK2_CTRL6_OFFSET,
15032 0x03FFFFFFU, 0x00000000U);
15033 /*##################################################################### */
15039 * Register : MIO_LOOPBACK @ 0XFF180200
15041 * I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1
15042 * = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs
15044 * PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1 0
15046 * CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1
15047 * = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx.
15048 * PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1 0
15050 * UART Loopback Control. 0 = Connect UART inputs according to MIO mapping.
15051 * 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0
15052 * inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD
15054 * PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1 0
15056 * SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1
15057 * = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs
15058 * . The other SPI core will appear on the LS Slave Select.
15059 * PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1 0
15061 * Loopback function within MIO
15062 * (OFFSET, MASK, VALUE) (0XFF180200, 0x0000000FU ,0x00000000U)
15064 PSU_Mask_Write(IOU_SLCR_MIO_LOOPBACK_OFFSET,
15065 0x0000000FU, 0x00000000U);
15066 /*##################################################################### */
15071 unsigned long psu_peripherals_init_data(void)
15080 * Register : RST_FPD_TOP @ 0XFD1A0100
15082 * PCIE config reset
15083 * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0
15085 * PCIE control block level reset
15086 * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0
15088 * PCIE bridge block level reset (AXI interface)
15089 * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0
15091 * Display Port block level reset (includes DPDMA)
15092 * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0
15095 * PSU_CRF_APB_RST_FPD_TOP_SWDT_RESET 0
15097 * GDMA block level reset
15098 * PSU_CRF_APB_RST_FPD_TOP_GDMA_RESET 0
15100 * Pixel Processor (submodule of GPU) block level reset
15101 * PSU_CRF_APB_RST_FPD_TOP_GPU_PP0_RESET 0
15103 * Pixel Processor (submodule of GPU) block level reset
15104 * PSU_CRF_APB_RST_FPD_TOP_GPU_PP1_RESET 0
15106 * GPU block level reset
15107 * PSU_CRF_APB_RST_FPD_TOP_GPU_RESET 0
15109 * GT block level reset
15110 * PSU_CRF_APB_RST_FPD_TOP_GT_RESET 0
15112 * Sata block level reset
15113 * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0
15115 * FPD Block level software controlled reset
15116 * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000F807EU ,0x00000000U)
15118 PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000F807EU, 0x00000000U);
15119 /*##################################################################### */
15128 * Register : RST_LPD_IOU2 @ 0XFF5E0238
15130 * Block level reset
15131 * PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET 0
15133 * Block level reset
15134 * PSU_CRL_APB_RST_LPD_IOU2_IOU_CC_RESET 0
15136 * Block level reset
15137 * PSU_CRL_APB_RST_LPD_IOU2_ADMA_RESET 0
15139 * Software control register for the IOU block. Each bit will cause a singl
15140 * erperipheral or part of the peripheral to be reset.
15141 * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x001A0000U ,0x00000000U)
15143 PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET,
15144 0x001A0000U, 0x00000000U);
15145 /*##################################################################### */
15148 * Register : RST_LPD_TOP @ 0XFF5E023C
15150 * Reset entire full power domain.
15151 * PSU_CRL_APB_RST_LPD_TOP_FPD_RESET 0
15154 * PSU_CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET 0
15157 * PSU_CRL_APB_RST_LPD_TOP_SYSMON_RESET 0
15159 * Real Time Clock reset
15160 * PSU_CRL_APB_RST_LPD_TOP_RTC_RESET 0
15163 * PSU_CRL_APB_RST_LPD_TOP_APM_RESET 0
15166 * PSU_CRL_APB_RST_LPD_TOP_IPI_RESET 0
15168 * reset entire RPU power island
15169 * PSU_CRL_APB_RST_LPD_TOP_RPU_PGE_RESET 0
15172 * PSU_CRL_APB_RST_LPD_TOP_OCM_RESET 0
15174 * Software control register for the LPD block.
15175 * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x0093C018U ,0x00000000U)
15177 PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x0093C018U, 0x00000000U);
15178 /*##################################################################### */
15184 * Register : RST_LPD_IOU0 @ 0XFF5E0230
15187 * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0
15189 * Software controlled reset for the GEMs
15190 * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U)
15192 PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET,
15193 0x00000008U, 0x00000000U);
15194 /*##################################################################### */
15200 * Register : RST_LPD_IOU2 @ 0XFF5E0238
15202 * Block level reset
15203 * PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 0
15205 * Software control register for the IOU block. Each bit will cause a singl
15206 * erperipheral or part of the peripheral to be reset.
15207 * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000000U)
15209 PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET,
15210 0x00000001U, 0x00000000U);
15211 /*##################################################################### */
15217 * Register : IOU_TAPDLY_BYPASS @ 0XFF180390
15219 * 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa
15220 * ss the Tap delay on the Rx clock signal of LQSPI
15221 * PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 1
15223 * IOU tap delay bypass for the LQSPI and NAND controllers
15224 * (OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000004U)
15226 PSU_Mask_Write(IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET,
15227 0x00000004U, 0x00000004U);
15228 /*##################################################################### */
15237 * Register : RST_LPD_TOP @ 0XFF5E023C
15239 * USB 0 reset for control registers
15240 * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0
15242 * USB 0 sleep circuit reset
15243 * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0
15246 * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0
15248 * Software control register for the LPD block.
15249 * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000000U)
15251 PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000540U, 0x00000000U);
15252 /*##################################################################### */
15255 * USB0 PIPE POWER PRESENT
15258 * Register : fpd_power_prsnt @ 0XFF9D0080
15260 * This bit is used to choose between PIPE power present and 1'b1
15261 * PSU_USB3_0_FPD_POWER_PRSNT_OPTION 0X1
15264 * (OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U)
15266 PSU_Mask_Write(USB3_0_FPD_POWER_PRSNT_OFFSET,
15267 0x00000001U, 0x00000001U);
15268 /*##################################################################### */
15271 * Register : fpd_pipe_clk @ 0XFF9D007C
15273 * This bit is used to choose between PIPE clock coming from SerDes and the
15275 * PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0
15278 * (OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U)
15280 PSU_Mask_Write(USB3_0_FPD_PIPE_CLK_OFFSET, 0x00000001U, 0x00000000U);
15281 /*##################################################################### */
15287 * Register : RST_LPD_IOU2 @ 0XFF5E0238
15289 * Block level reset
15290 * PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET 0
15292 * Software control register for the IOU block. Each bit will cause a singl
15293 * erperipheral or part of the peripheral to be reset.
15294 * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000040U ,0x00000000U)
15296 PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET,
15297 0x00000040U, 0x00000000U);
15298 /*##################################################################### */
15301 * Register : CTRL_REG_SD @ 0XFF180310
15303 * SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled
15304 * PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL 0
15306 * SD eMMC selection
15307 * (OFFSET, MASK, VALUE) (0XFF180310, 0x00008000U ,0x00000000U)
15309 PSU_Mask_Write(IOU_SLCR_CTRL_REG_SD_OFFSET,
15310 0x00008000U, 0x00000000U);
15311 /*##################################################################### */
15314 * Register : SD_CONFIG_REG2 @ 0XFF180320
15316 * Should be set based on the final product usage 00 - Removable SCard Slot
15317 * 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved
15318 * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE 0
15320 * 1.8V Support 1: 1.8V supported 0: 1.8V not supported support
15321 * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V 1
15323 * 3.0V Support 1: 3.0V supported 0: 3.0V not supported support
15324 * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V 0
15326 * 3.3V Support 1: 3.3V supported 0: 3.3V not supported support
15327 * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V 1
15329 * SD Config Register 2
15330 * (OFFSET, MASK, VALUE) (0XFF180320, 0x33800000U ,0x02800000U)
15332 PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG2_OFFSET,
15333 0x33800000U, 0x02800000U);
15334 /*##################################################################### */
15340 * Register : SD_CONFIG_REG1 @ 0XFF18031C
15342 * Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.
15343 * PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK 0xc8
15345 * Configures the Number of Taps (Phases) of the rxclk_in that is supported
15347 * PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT 0x28
15349 * SD Config Register 1
15350 * (OFFSET, MASK, VALUE) (0XFF18031C, 0x7FFE0000U ,0x64500000U)
15352 PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG1_OFFSET,
15353 0x7FFE0000U, 0x64500000U);
15354 /*##################################################################### */
15357 * Register : SD_DLL_CTRL @ 0XFF180358
15360 * PSU_IOU_SLCR_SD_DLL_CTRL_RESERVED 1
15362 * SDIO status register
15363 * (OFFSET, MASK, VALUE) (0XFF180358, 0x00000008U ,0x00000008U)
15365 PSU_Mask_Write(IOU_SLCR_SD_DLL_CTRL_OFFSET,
15366 0x00000008U, 0x00000008U);
15367 /*##################################################################### */
15373 * Register : SD_CONFIG_REG3 @ 0XFF180324
15375 * This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. S
15376 * etting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other
15377 * source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n
15378 * = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved
15379 * PSU_IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR 0X0
15381 * SD Config Register 3
15382 * (OFFSET, MASK, VALUE) (0XFF180324, 0x03C00000U ,0x00000000U)
15384 PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG3_OFFSET,
15385 0x03C00000U, 0x00000000U);
15386 /*##################################################################### */
15392 * Register : RST_LPD_IOU2 @ 0XFF5E0238
15394 * Block level reset
15395 * PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET 0
15397 * Software control register for the IOU block. Each bit will cause a singl
15398 * erperipheral or part of the peripheral to be reset.
15399 * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000100U ,0x00000000U)
15401 PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET,
15402 0x00000100U, 0x00000000U);
15403 /*##################################################################### */
15409 * Register : RST_LPD_IOU2 @ 0XFF5E0238
15411 * Block level reset
15412 * PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET 0
15414 * Block level reset
15415 * PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET 0
15417 * Software control register for the IOU block. Each bit will cause a singl
15418 * erperipheral or part of the peripheral to be reset.
15419 * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000600U ,0x00000000U)
15421 PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET,
15422 0x00000600U, 0x00000000U);
15423 /*##################################################################### */
15429 * Register : RST_LPD_IOU2 @ 0XFF5E0238
15431 * Block level reset
15432 * PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET 0
15434 * Software control register for the IOU block. Each bit will cause a singl
15435 * erperipheral or part of the peripheral to be reset.
15436 * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00008000U ,0x00000000U)
15438 PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET,
15439 0x00008000U, 0x00000000U);
15440 /*##################################################################### */
15449 * Register : RST_LPD_IOU2 @ 0XFF5E0238
15451 * Block level reset
15452 * PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET 0
15454 * Block level reset
15455 * PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET 0
15457 * Block level reset
15458 * PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET 0
15460 * Block level reset
15461 * PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET 0
15463 * Software control register for the IOU block. Each bit will cause a singl
15464 * erperipheral or part of the peripheral to be reset.
15465 * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00007800U ,0x00000000U)
15467 PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET,
15468 0x00007800U, 0x00000000U);
15469 /*##################################################################### */
15475 * Register : RST_LPD_IOU2 @ 0XFF5E0238
15477 * Block level reset
15478 * PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET 0
15480 * Block level reset
15481 * PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET 0
15483 * Software control register for the IOU block. Each bit will cause a singl
15484 * erperipheral or part of the peripheral to be reset.
15485 * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000006U ,0x00000000U)
15487 PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET,
15488 0x00000006U, 0x00000000U);
15489 /*##################################################################### */
15495 * Register : Baud_rate_divider_reg0 @ 0XFF000034
15497 * Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
15498 * PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV 0x5
15500 * Baud Rate Divider Register
15501 * (OFFSET, MASK, VALUE) (0XFF000034, 0x000000FFU ,0x00000005U)
15503 PSU_Mask_Write(UART0_BAUD_RATE_DIVIDER_REG0_OFFSET,
15504 0x000000FFU, 0x00000005U);
15505 /*##################################################################### */
15508 * Register : Baud_rate_gen_reg0 @ 0XFF000018
15510 * Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor
15511 * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
15512 * PSU_UART0_BAUD_RATE_GEN_REG0_CD 0x8f
15514 * Baud Rate Generator Register.
15515 * (OFFSET, MASK, VALUE) (0XFF000018, 0x0000FFFFU ,0x0000008FU)
15517 PSU_Mask_Write(UART0_BAUD_RATE_GEN_REG0_OFFSET,
15518 0x0000FFFFU, 0x0000008FU);
15519 /*##################################################################### */
15522 * Register : Control_reg0 @ 0XFF000000
15524 * Stop transmitter break: 0: no affect 1: stop transmission of the break a
15525 * fter a minimum of one character length and transmit a high level during
15526 * 12 bit periods. It can be set regardless of the value of STTBRK.
15527 * PSU_UART0_CONTROL_REG0_STPBRK 0x0
15529 * Start transmitter break: 0: no affect 1: start to transmit a break after
15530 * the characters currently present in the FIFO and the transmit shift reg
15531 * ister have been transmitted. It can only be set if STPBRK (Stop transmit
15532 * ter break) is not high.
15533 * PSU_UART0_CONTROL_REG0_STTBRK 0x0
15535 * Restart receiver timeout counter: 1: receiver timeout counter is restart
15536 * ed. This bit is self clearing once the restart has completed.
15537 * PSU_UART0_CONTROL_REG0_RSTTO 0x0
15539 * Transmit disable: 0: enable transmitter 1: disable transmitter
15540 * PSU_UART0_CONTROL_REG0_TXDIS 0x0
15542 * Transmit enable: 0: disable transmitter 1: enable transmitter, provided
15543 * the TXDIS field is set to 0.
15544 * PSU_UART0_CONTROL_REG0_TXEN 0x1
15546 * Receive disable: 0: enable 1: disable, regardless of the value of RXEN
15547 * PSU_UART0_CONTROL_REG0_RXDIS 0x0
15549 * Receive enable: 0: disable 1: enable When set to one, the receiver logic
15550 * is enabled, provided the RXDIS field is set to zero.
15551 * PSU_UART0_CONTROL_REG0_RXEN 0x1
15553 * Software reset for Tx data path: 0: no affect 1: transmitter logic is re
15554 * set and all pending transmitter data is discarded This bit is self clear
15555 * ing once the reset has completed.
15556 * PSU_UART0_CONTROL_REG0_TXRES 0x1
15558 * Software reset for Rx data path: 0: no affect 1: receiver logic is reset
15559 * and all pending receiver data is discarded. This bit is self clearing o
15560 * nce the reset has completed.
15561 * PSU_UART0_CONTROL_REG0_RXRES 0x1
15563 * UART Control Register
15564 * (OFFSET, MASK, VALUE) (0XFF000000, 0x000001FFU ,0x00000017U)
15566 PSU_Mask_Write(UART0_CONTROL_REG0_OFFSET, 0x000001FFU, 0x00000017U);
15567 /*##################################################################### */
15570 * Register : mode_reg0 @ 0XFF000004
15572 * Channel mode: Defines the mode of operation of the UART. 00: normal 01:
15573 * automatic echo 10: local loopback 11: remote loopback
15574 * PSU_UART0_MODE_REG0_CHMODE 0x0
15576 * Number of stop bits: Defines the number of stop bits to detect on receiv
15577 * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st
15578 * op bits 11: reserved
15579 * PSU_UART0_MODE_REG0_NBSTOP 0x0
15581 * Parity type select: Defines the expected parity to check on receive and
15582 * the parity to generate on transmit. 000: even parity 001: odd parity 010
15583 * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari
15585 * PSU_UART0_MODE_REG0_PAR 0x4
15587 * Character length select: Defines the number of bits in each character. 1
15588 * 1: 6 bits 10: 7 bits 0x: 8 bits
15589 * PSU_UART0_MODE_REG0_CHRL 0x0
15591 * Clock source select: This field defines whether a pre-scalar of 8 is app
15592 * lied to the baud rate generator input clock. 0: clock source is uart_ref
15593 * _clk 1: clock source is uart_ref_clk/8
15594 * PSU_UART0_MODE_REG0_CLKS 0x0
15596 * UART Mode Register
15597 * (OFFSET, MASK, VALUE) (0XFF000004, 0x000003FFU ,0x00000020U)
15599 PSU_Mask_Write(UART0_MODE_REG0_OFFSET, 0x000003FFU, 0x00000020U);
15600 /*##################################################################### */
15603 * Register : Baud_rate_divider_reg0 @ 0XFF010034
15605 * Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
15606 * PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV 0x5
15608 * Baud Rate Divider Register
15609 * (OFFSET, MASK, VALUE) (0XFF010034, 0x000000FFU ,0x00000005U)
15611 PSU_Mask_Write(UART1_BAUD_RATE_DIVIDER_REG0_OFFSET,
15612 0x000000FFU, 0x00000005U);
15613 /*##################################################################### */
15616 * Register : Baud_rate_gen_reg0 @ 0XFF010018
15618 * Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor
15619 * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
15620 * PSU_UART1_BAUD_RATE_GEN_REG0_CD 0x8f
15622 * Baud Rate Generator Register.
15623 * (OFFSET, MASK, VALUE) (0XFF010018, 0x0000FFFFU ,0x0000008FU)
15625 PSU_Mask_Write(UART1_BAUD_RATE_GEN_REG0_OFFSET,
15626 0x0000FFFFU, 0x0000008FU);
15627 /*##################################################################### */
15630 * Register : Control_reg0 @ 0XFF010000
15632 * Stop transmitter break: 0: no affect 1: stop transmission of the break a
15633 * fter a minimum of one character length and transmit a high level during
15634 * 12 bit periods. It can be set regardless of the value of STTBRK.
15635 * PSU_UART1_CONTROL_REG0_STPBRK 0x0
15637 * Start transmitter break: 0: no affect 1: start to transmit a break after
15638 * the characters currently present in the FIFO and the transmit shift reg
15639 * ister have been transmitted. It can only be set if STPBRK (Stop transmit
15640 * ter break) is not high.
15641 * PSU_UART1_CONTROL_REG0_STTBRK 0x0
15643 * Restart receiver timeout counter: 1: receiver timeout counter is restart
15644 * ed. This bit is self clearing once the restart has completed.
15645 * PSU_UART1_CONTROL_REG0_RSTTO 0x0
15647 * Transmit disable: 0: enable transmitter 1: disable transmitter
15648 * PSU_UART1_CONTROL_REG0_TXDIS 0x0
15650 * Transmit enable: 0: disable transmitter 1: enable transmitter, provided
15651 * the TXDIS field is set to 0.
15652 * PSU_UART1_CONTROL_REG0_TXEN 0x1
15654 * Receive disable: 0: enable 1: disable, regardless of the value of RXEN
15655 * PSU_UART1_CONTROL_REG0_RXDIS 0x0
15657 * Receive enable: 0: disable 1: enable When set to one, the receiver logic
15658 * is enabled, provided the RXDIS field is set to zero.
15659 * PSU_UART1_CONTROL_REG0_RXEN 0x1
15661 * Software reset for Tx data path: 0: no affect 1: transmitter logic is re
15662 * set and all pending transmitter data is discarded This bit is self clear
15663 * ing once the reset has completed.
15664 * PSU_UART1_CONTROL_REG0_TXRES 0x1
15666 * Software reset for Rx data path: 0: no affect 1: receiver logic is reset
15667 * and all pending receiver data is discarded. This bit is self clearing o
15668 * nce the reset has completed.
15669 * PSU_UART1_CONTROL_REG0_RXRES 0x1
15671 * UART Control Register
15672 * (OFFSET, MASK, VALUE) (0XFF010000, 0x000001FFU ,0x00000017U)
15674 PSU_Mask_Write(UART1_CONTROL_REG0_OFFSET, 0x000001FFU, 0x00000017U);
15675 /*##################################################################### */
15678 * Register : mode_reg0 @ 0XFF010004
15680 * Channel mode: Defines the mode of operation of the UART. 00: normal 01:
15681 * automatic echo 10: local loopback 11: remote loopback
15682 * PSU_UART1_MODE_REG0_CHMODE 0x0
15684 * Number of stop bits: Defines the number of stop bits to detect on receiv
15685 * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st
15686 * op bits 11: reserved
15687 * PSU_UART1_MODE_REG0_NBSTOP 0x0
15689 * Parity type select: Defines the expected parity to check on receive and
15690 * the parity to generate on transmit. 000: even parity 001: odd parity 010
15691 * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari
15693 * PSU_UART1_MODE_REG0_PAR 0x4
15695 * Character length select: Defines the number of bits in each character. 1
15696 * 1: 6 bits 10: 7 bits 0x: 8 bits
15697 * PSU_UART1_MODE_REG0_CHRL 0x0
15699 * Clock source select: This field defines whether a pre-scalar of 8 is app
15700 * lied to the baud rate generator input clock. 0: clock source is uart_ref
15701 * _clk 1: clock source is uart_ref_clk/8
15702 * PSU_UART1_MODE_REG0_CLKS 0x0
15704 * UART Mode Register
15705 * (OFFSET, MASK, VALUE) (0XFF010004, 0x000003FFU ,0x00000020U)
15707 PSU_Mask_Write(UART1_MODE_REG0_OFFSET, 0x000003FFU, 0x00000020U);
15708 /*##################################################################### */
15714 * Register : RST_LPD_IOU2 @ 0XFF5E0238
15716 * Block level reset
15717 * PSU_CRL_APB_RST_LPD_IOU2_GPIO_RESET 0
15719 * Software control register for the IOU block. Each bit will cause a singl
15720 * erperipheral or part of the peripheral to be reset.
15721 * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00040000U ,0x00000000U)
15723 PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET,
15724 0x00040000U, 0x00000000U);
15725 /*##################################################################### */
15731 * Register : slcr_adma @ 0XFF4B0024
15733 * TrustZone Classification for ADMA
15734 * PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0XFF
15736 * RPU TrustZone settings
15737 * (OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU)
15739 PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_ADMA_OFFSET,
15740 0x000000FFU, 0x000000FFU);
15741 /*##################################################################### */
15747 * CSU TAMPER STATUS
15750 * Register : tamper_status @ 0XFFCA5000
15753 * PSU_CSU_TAMPER_STATUS_TAMPER_0 0
15756 * PSU_CSU_TAMPER_STATUS_TAMPER_1 0
15758 * JTAG toggle detect
15759 * PSU_CSU_TAMPER_STATUS_TAMPER_2 0
15762 * PSU_CSU_TAMPER_STATUS_TAMPER_3 0
15764 * AMS over temperature alarm for LPD
15765 * PSU_CSU_TAMPER_STATUS_TAMPER_4 0
15767 * AMS over temperature alarm for APU
15768 * PSU_CSU_TAMPER_STATUS_TAMPER_5 0
15770 * AMS voltage alarm for VCCPINT_FPD
15771 * PSU_CSU_TAMPER_STATUS_TAMPER_6 0
15773 * AMS voltage alarm for VCCPINT_LPD
15774 * PSU_CSU_TAMPER_STATUS_TAMPER_7 0
15776 * AMS voltage alarm for VCCPAUX
15777 * PSU_CSU_TAMPER_STATUS_TAMPER_8 0
15779 * AMS voltage alarm for DDRPHY
15780 * PSU_CSU_TAMPER_STATUS_TAMPER_9 0
15782 * AMS voltage alarm for PSIO bank 0/1/2
15783 * PSU_CSU_TAMPER_STATUS_TAMPER_10 0
15785 * AMS voltage alarm for PSIO bank 3 (dedicated pins)
15786 * PSU_CSU_TAMPER_STATUS_TAMPER_11 0
15788 * AMS voltaage alarm for GT
15789 * PSU_CSU_TAMPER_STATUS_TAMPER_12 0
15791 * Tamper Response Status
15792 * (OFFSET, MASK, VALUE) (0XFFCA5000, 0x00001FFFU ,0x00000000U)
15794 PSU_Mask_Write(CSU_TAMPER_STATUS_OFFSET, 0x00001FFFU, 0x00000000U);
15795 /*##################################################################### */
15798 * CSU TAMPER RESPONSE
15804 * Register : ACE_CTRL @ 0XFD5C0060
15806 * Set ACE outgoing AWQOS value
15807 * PSU_APU_ACE_CTRL_AWQOS 0X0
15809 * Set ACE outgoing ARQOS value
15810 * PSU_APU_ACE_CTRL_ARQOS 0X0
15812 * ACE Control Register
15813 * (OFFSET, MASK, VALUE) (0XFD5C0060, 0x000F000FU ,0x00000000U)
15815 PSU_Mask_Write(APU_ACE_CTRL_OFFSET, 0x000F000FU, 0x00000000U);
15816 /*##################################################################### */
15819 * ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE
15822 * Register : CONTROL @ 0XFFA60040
15824 * Enables the RTC. By writing a 0 to this bit, RTC will be powered off and
15825 * the only module that potentially draws current from the battery will be
15826 * BBRAM. The value read through this bit does not necessarily reflect whe
15827 * ther RTC is enabled or not. It is expected that RTC is enabled every tim
15828 * e it is being configured. If RTC is not used in the design, FSBL will di
15829 * sable it by writing a 0 to this bit.
15830 * PSU_RTC_CONTROL_BATTERY_DISABLE 0X1
15832 * This register controls various functionalities within the RTC
15833 * (OFFSET, MASK, VALUE) (0XFFA60040, 0x80000000U ,0x80000000U)
15835 PSU_Mask_Write(RTC_CONTROL_OFFSET, 0x80000000U, 0x80000000U);
15836 /*##################################################################### */
15839 * TIMESTAMP COUNTER
15842 * Register : base_frequency_ID_register @ 0XFF260020
15844 * Frequency in number of ticks per second. Valid range from 10 MHz to 100
15846 * PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ 0x5f5b9f0
15848 * Program this register to match the clock frequency of the timestamp gene
15849 * rator, in ticks per second. For example, for a 50 MHz clock, program 0x0
15850 * 2FAF080. This register is not accessible to the read-only programming in
15852 * (OFFSET, MASK, VALUE) (0XFF260020, 0xFFFFFFFFU ,0x05F5B9F0U)
15854 PSU_Mask_Write(IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET,
15855 0xFFFFFFFFU, 0x05F5B9F0U);
15856 /*##################################################################### */
15859 * Register : counter_control_register @ 0XFF260000
15861 * Enable 0: The counter is disabled and not incrementing. 1: The counter i
15862 * s enabled and is incrementing.
15863 * PSU_IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN 0x1
15865 * Controls the counter increments. This register is not accessible to the
15866 * read-only programming interface.
15867 * (OFFSET, MASK, VALUE) (0XFF260000, 0x00000001U ,0x00000001U)
15869 PSU_Mask_Write(IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET,
15870 0x00000001U, 0x00000001U);
15871 /*##################################################################### */
15889 * Register : DIRM_1 @ 0XFF0A0244
15891 * Operation is the same as DIRM_0[DIRECTION_0]
15892 * PSU_GPIO_DIRM_1_DIRECTION_1 0x20
15894 * Direction mode (GPIO Bank1, MIO)
15895 * (OFFSET, MASK, VALUE) (0XFF0A0244, 0x03FFFFFFU ,0x00000020U)
15897 PSU_Mask_Write(GPIO_DIRM_1_OFFSET, 0x03FFFFFFU, 0x00000020U);
15898 /*##################################################################### */
15904 * OUTPUT ENABLE BANK 0
15907 * OUTPUT ENABLE BANK 1
15910 * Register : OEN_1 @ 0XFF0A0248
15912 * Operation is the same as OEN_0[OP_ENABLE_0]
15913 * PSU_GPIO_OEN_1_OP_ENABLE_1 0x20
15915 * Output enable (GPIO Bank1, MIO)
15916 * (OFFSET, MASK, VALUE) (0XFF0A0248, 0x03FFFFFFU ,0x00000020U)
15918 PSU_Mask_Write(GPIO_OEN_1_OFFSET, 0x03FFFFFFU, 0x00000020U);
15919 /*##################################################################### */
15922 * OUTPUT ENABLE BANK 2
15925 * MASK_DATA_0_LSW LOW BANK [15:0]
15928 * MASK_DATA_0_MSW LOW BANK [25:16]
15931 * MASK_DATA_1_LSW LOW BANK [41:26]
15934 * Register : MASK_DATA_1_LSW @ 0XFF0A0008
15936 * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
15937 * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf
15939 * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]
15940 * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20
15942 * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)
15943 * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U)
15945 PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET,
15946 0xFFFFFFFFU, 0xFFDF0020U);
15947 /*##################################################################### */
15950 * MASK_DATA_1_MSW HIGH BANK [51:42]
15953 * MASK_DATA_1_LSW HIGH BANK [67:52]
15956 * MASK_DATA_1_LSW HIGH BANK [77:68]
15963 /*##################################################################### */
15966 * MASK_DATA_0_LSW LOW BANK [15:0]
15969 * MASK_DATA_0_MSW LOW BANK [25:16]
15972 * MASK_DATA_1_LSW LOW BANK [41:26]
15975 * Register : MASK_DATA_1_LSW @ 0XFF0A0008
15977 * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
15978 * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf
15980 * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]
15981 * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x0
15983 * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)
15984 * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0000U)
15986 PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET,
15987 0xFFFFFFFFU, 0xFFDF0000U);
15988 /*##################################################################### */
15991 * MASK_DATA_1_MSW HIGH BANK [51:42]
15994 * MASK_DATA_1_LSW HIGH BANK [67:52]
15997 * MASK_DATA_1_LSW HIGH BANK [77:68]
16004 /*##################################################################### */
16009 unsigned long psu_post_config_data(void)
16017 unsigned long psu_peripherals_powerdwn_data(void)
16020 * POWER DOWN REQUEST INTERRUPT ENABLE
16023 * POWER DOWN TRIGGER
16028 unsigned long psu_lpd_xppu_data(void)
16034 * APERTURE PERMISIION LIST
16037 * APERTURE NAME: UART0, START ADDRESS: FF000000, END ADDRESS: FF00FFFF
16040 * APERTURE NAME: UART1, START ADDRESS: FF010000, END ADDRESS: FF01FFFF
16043 * APERTURE NAME: I2C0, START ADDRESS: FF020000, END ADDRESS: FF02FFFF
16046 * APERTURE NAME: I2C1, START ADDRESS: FF030000, END ADDRESS: FF03FFFF
16049 * APERTURE NAME: SPI0, START ADDRESS: FF040000, END ADDRESS: FF04FFFF
16052 * APERTURE NAME: SPI1, START ADDRESS: FF050000, END ADDRESS: FF05FFFF
16055 * APERTURE NAME: CAN0, START ADDRESS: FF060000, END ADDRESS: FF06FFFF
16058 * APERTURE NAME: CAN1, START ADDRESS: FF070000, END ADDRESS: FF07FFFF
16061 * APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09
16065 * APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09
16069 * APERTURE NAME: GPIO, START ADDRESS: FF0A0000, END ADDRESS: FF0AFFFF
16072 * APERTURE NAME: GEM0, START ADDRESS: FF0B0000, END ADDRESS: FF0BFFFF
16075 * APERTURE NAME: GEM1, START ADDRESS: FF0C0000, END ADDRESS: FF0CFFFF
16078 * APERTURE NAME: GEM2, START ADDRESS: FF0D0000, END ADDRESS: FF0DFFFF
16081 * APERTURE NAME: GEM3, START ADDRESS: FF0E0000, END ADDRESS: FF0EFFFF
16084 * APERTURE NAME: QSPI, START ADDRESS: FF0F0000, END ADDRESS: FF0FFFFF
16087 * APERTURE NAME: NAND, START ADDRESS: FF100000, END ADDRESS: FF10FFFF
16090 * APERTURE NAME: TTC0, START ADDRESS: FF110000, END ADDRESS: FF11FFFF
16093 * APERTURE NAME: TTC1, START ADDRESS: FF120000, END ADDRESS: FF12FFFF
16096 * APERTURE NAME: TTC2, START ADDRESS: FF130000, END ADDRESS: FF13FFFF
16099 * APERTURE NAME: TTC3, START ADDRESS: FF140000, END ADDRESS: FF14FFFF
16102 * APERTURE NAME: SWDT, START ADDRESS: FF150000, END ADDRESS: FF15FFFF
16105 * APERTURE NAME: SD0, START ADDRESS: FF160000, END ADDRESS: FF16FFFF
16108 * APERTURE NAME: SD1, START ADDRESS: FF170000, END ADDRESS: FF17FFFF
16111 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16114 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16117 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16120 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16123 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16126 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16129 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16132 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16135 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16138 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16141 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16144 * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
16147 * APERTURE NAME: IOU_SECURE_SLCR, START ADDRESS: FF240000, END ADDRESS: FF
16151 * APERTURE NAME: IOU_SCNTR, START ADDRESS: FF250000, END ADDRESS: FF25FFFF
16154 * APERTURE NAME: IOU_SCNTRS, START ADDRESS: FF260000, END ADDRESS: FF26FFF
16158 * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A
16162 * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A
16166 * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A
16170 * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A
16174 * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F
16178 * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F
16182 * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F
16186 * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F
16190 * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F
16194 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
16197 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16200 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16203 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
16206 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
16209 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
16212 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
16215 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
16218 * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
16221 * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
16224 * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
16227 * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
16230 * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
16233 * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
16236 * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
16239 * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
16242 * APERTURE NAME: LPD_UNUSED_1, START ADDRESS: FF400000, END ADDRESS: FF40F
16246 * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
16249 * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
16252 * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
16255 * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
16258 * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
16261 * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
16264 * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
16267 * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
16270 * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
16273 * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
16276 * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF
16280 * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF
16284 * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF
16288 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16292 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16296 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16300 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16304 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16308 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16312 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16316 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16320 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16324 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16328 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16332 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16336 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16340 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16344 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16348 * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF
16352 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16355 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16358 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16361 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16364 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16367 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16370 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16373 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16376 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16379 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16382 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16385 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16388 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16391 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16394 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16397 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16400 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16403 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16406 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16409 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16412 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16415 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16418 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16421 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16424 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16427 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16430 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16433 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16436 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16439 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16442 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16445 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16448 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16451 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16454 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16457 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16460 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16463 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16466 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16469 * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
16472 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16476 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16480 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16484 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16488 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16492 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16496 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16500 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16504 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16508 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16512 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16516 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16520 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16524 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16528 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16532 * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F
16536 * APERTURE NAME: OCM_SLCR, START ADDRESS: FF960000, END ADDRESS: FF96FFFF
16539 * APERTURE NAME: LPD_UNUSED_4, START ADDRESS: FF970000, END ADDRESS: FF97F
16543 * APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF
16546 * APERTURE NAME: RPU, START ADDRESS: FF9A0000, END ADDRESS: FF9AFFFF
16549 * APERTURE NAME: AFIFM6, START ADDRESS: FF9B0000, END ADDRESS: FF9BFFFF
16552 * APERTURE NAME: LPD_XPPU_SINK, START ADDRESS: FF9C0000, END ADDRESS: FF9C
16556 * APERTURE NAME: USB3_0, START ADDRESS: FF9D0000, END ADDRESS: FF9DFFFF
16559 * APERTURE NAME: USB3_1, START ADDRESS: FF9E0000, END ADDRESS: FF9EFFFF
16562 * APERTURE NAME: LPD_UNUSED_5, START ADDRESS: FF9F0000, END ADDRESS: FF9FF
16566 * APERTURE NAME: APM0, START ADDRESS: FFA00000, END ADDRESS: FFA0FFFF
16569 * APERTURE NAME: APM1, START ADDRESS: FFA10000, END ADDRESS: FFA1FFFF
16572 * APERTURE NAME: APM_INTC_IOU, START ADDRESS: FFA20000, END ADDRESS: FFA2F
16576 * APERTURE NAME: APM_FPD_LPD, START ADDRESS: FFA30000, END ADDRESS: FFA3FF
16580 * APERTURE NAME: LPD_UNUSED_6, START ADDRESS: FFA40000, END ADDRESS: FFA4F
16584 * APERTURE NAME: AMS, START ADDRESS: FFA50000, END ADDRESS: FFA5FFFF
16587 * APERTURE NAME: RTC, START ADDRESS: FFA60000, END ADDRESS: FFA6FFFF
16590 * APERTURE NAME: OCM_XMPU_CFG, START ADDRESS: FFA70000, END ADDRESS: FFA7F
16594 * APERTURE NAME: ADMA_0, START ADDRESS: FFA80000, END ADDRESS: FFA8FFFF
16597 * APERTURE NAME: ADMA_1, START ADDRESS: FFA90000, END ADDRESS: FFA9FFFF
16600 * APERTURE NAME: ADMA_2, START ADDRESS: FFAA0000, END ADDRESS: FFAAFFFF
16603 * APERTURE NAME: ADMA_3, START ADDRESS: FFAB0000, END ADDRESS: FFABFFFF
16606 * APERTURE NAME: ADMA_4, START ADDRESS: FFAC0000, END ADDRESS: FFACFFFF
16609 * APERTURE NAME: ADMA_5, START ADDRESS: FFAD0000, END ADDRESS: FFADFFFF
16612 * APERTURE NAME: ADMA_6, START ADDRESS: FFAE0000, END ADDRESS: FFAEFFFF
16615 * APERTURE NAME: ADMA_7, START ADDRESS: FFAF0000, END ADDRESS: FFAFFFFF
16618 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16622 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16626 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16630 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16634 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16638 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16642 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16646 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16650 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16654 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16658 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16662 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16666 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16670 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16674 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16678 * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF
16682 * APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF
16685 * APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF
16688 * APERTURE NAME: CSU_LOCAL, START ADDRESS: FFC20000, END ADDRESS: FFC2FFFF
16691 * APERTURE NAME: PUF, START ADDRESS: FFC30000, END ADDRESS: FFC3FFFF
16694 * APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF
16697 * APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF
16700 * APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7F
16704 * APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7F
16708 * APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF
16711 * APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF
16714 * APERTURE NAME: CSU, START ADDRESS: FFCA0000, END ADDRESS: FFCAFFFF
16717 * APERTURE NAME: CSU_WDT, START ADDRESS: FFCB0000, END ADDRESS: FFCBFFFF
16720 * APERTURE NAME: EFUSE, START ADDRESS: FFCC0000, END ADDRESS: FFCCFFFF
16723 * APERTURE NAME: BBRAM, START ADDRESS: FFCD0000, END ADDRESS: FFCDFFFF
16726 * APERTURE NAME: RSA_CORE, START ADDRESS: FFCE0000, END ADDRESS: FFCEFFFF
16729 * APERTURE NAME: MBISTJTAG, START ADDRESS: FFCF0000, END ADDRESS: FFCFFFFF
16732 * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
16735 * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
16738 * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
16741 * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
16744 * APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5F
16748 * APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5F
16752 * APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF
16755 * APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF
16758 * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF
16762 * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF
16766 * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF
16770 * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF
16774 * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
16777 * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
16780 * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
16783 * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
16786 * APERTURE NAME: R5_0_ATCM, START ADDRESS: FFE00000, END ADDRESS: FFE0FFFF
16789 * APERTURE NAME: R5_0_ATCM_LOCKSTEP, START ADDRESS: FFE10000, END ADDRESS:
16793 * APERTURE NAME: R5_0_BTCM, START ADDRESS: FFE20000, END ADDRESS: FFE2FFFF
16796 * APERTURE NAME: R5_0_BTCM_LOCKSTEP, START ADDRESS: FFE30000, END ADDRESS:
16800 * APERTURE NAME: R5_0_INSTRUCTION_CACHE, START ADDRESS: FFE40000, END ADDR
16804 * APERTURE NAME: R5_0_DATA_CACHE, START ADDRESS: FFE50000, END ADDRESS: FF
16808 * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F
16812 * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F
16816 * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F
16820 * APERTURE NAME: R5_1_ATCM_, START ADDRESS: FFE90000, END ADDRESS: FFE9FFF
16824 * APERTURE NAME: RPU_UNUSED_10, START ADDRESS: FFEA0000, END ADDRESS: FFEA
16828 * APERTURE NAME: R5_1_BTCM_, START ADDRESS: FFEB0000, END ADDRESS: FFEBFFF
16832 * APERTURE NAME: R5_1_INSTRUCTION_CACHE, START ADDRESS: FFEC0000, END ADDR
16836 * APERTURE NAME: R5_1_DATA_CACHE, START ADDRESS: FFED0000, END ADDRESS: FF
16840 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16844 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16848 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16852 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16856 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16860 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16864 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16868 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16872 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16876 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16880 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16884 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16888 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16892 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16896 * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF
16900 * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF
16904 * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF
16908 * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF
16912 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16915 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16918 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16921 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16924 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16927 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16930 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16933 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16936 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16939 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16942 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16945 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16948 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16951 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16954 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16957 * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
16960 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16963 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16966 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16969 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16972 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16975 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16978 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16981 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16984 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16987 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16990 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16993 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16996 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
16999 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
17002 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
17005 * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
17008 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17011 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17014 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17017 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17020 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17023 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17026 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17029 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17032 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17035 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17038 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17041 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17044 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17047 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17050 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17053 * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
17056 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17059 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17062 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17065 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17068 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17071 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17074 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17077 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17080 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17083 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17086 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17089 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17092 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17095 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17098 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17101 * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
17104 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17107 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17110 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17113 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17116 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17119 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17122 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17125 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17128 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17131 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17134 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17137 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17140 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17143 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17146 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17149 * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
17152 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17155 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17158 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17161 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17164 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17167 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17170 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17173 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17176 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17179 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17182 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17185 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17188 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17191 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17194 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17197 * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
17200 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17203 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17206 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17209 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17212 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17215 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17218 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17221 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17224 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17227 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17230 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17233 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17236 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17239 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17242 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17245 * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
17248 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17251 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17254 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17257 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17260 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17263 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17266 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17269 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17272 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17275 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17278 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17281 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17284 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17287 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17290 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17293 * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
17296 * APERTURE NAME: IOU_GPV, START ADDRESS: FE000000, END ADDRESS: FE0FFFFF
17299 * APERTURE NAME: LPD_GPV, START ADDRESS: FE100000, END ADDRESS: FE1FFFFF
17302 * APERTURE NAME: USB3_0_XHCI, START ADDRESS: FE200000, END ADDRESS: FE2FFF
17306 * APERTURE NAME: USB3_1_XHCI, START ADDRESS: FE300000, END ADDRESS: FE3FFF
17310 * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F
17314 * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F
17318 * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F
17322 * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F
17326 * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
17329 * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
17332 * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
17335 * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
17338 * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
17341 * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
17344 * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
17347 * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
17350 * APERTURE NAME: QSPI_LINEAR_ADDRESS, START ADDRESS: C0000000, END ADDRESS
17359 unsigned long psu_ddr_xmpu0_data(void)
17367 unsigned long psu_ddr_xmpu1_data(void)
17375 unsigned long psu_ddr_xmpu2_data(void)
17383 unsigned long psu_ddr_xmpu3_data(void)
17391 unsigned long psu_ddr_xmpu4_data(void)
17399 unsigned long psu_ddr_xmpu5_data(void)
17407 unsigned long psu_ocm_xmpu_data(void)
17415 unsigned long psu_fpd_xmpu_data(void)
17423 unsigned long psu_protection_lock_data(void)
17426 * LOCKING PROTECTION MODULE
17432 * APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF
17438 * LOCK OCM XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
17441 * LOCK FPD XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
17444 * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
17447 * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
17450 * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
17453 * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
17456 * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
17459 * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
17464 unsigned long psu_apply_master_tz(void)
17473 * Register : slcr_dpdma @ 0XFD690040
17475 * TrustZone classification for DisplayPort DMA
17476 * PSU_FPD_SLCR_SECURE_SLCR_DPDMA_TZ 1
17478 * DPDMA TrustZone Settings
17479 * (OFFSET, MASK, VALUE) (0XFD690040, 0x00000001U ,0x00000001U)
17481 PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET,
17482 0x00000001U, 0x00000001U);
17483 /*##################################################################### */
17492 * Register : slcr_pcie @ 0XFD690030
17494 * TrustZone classification for DMA Channel 0
17495 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0 1
17497 * TrustZone classification for DMA Channel 1
17498 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1 1
17500 * TrustZone classification for DMA Channel 2
17501 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2 1
17503 * TrustZone classification for DMA Channel 3
17504 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3 1
17506 * TrustZone classification for Ingress Address Translation 0
17507 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0 1
17509 * TrustZone classification for Ingress Address Translation 1
17510 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1 1
17512 * TrustZone classification for Ingress Address Translation 2
17513 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2 1
17515 * TrustZone classification for Ingress Address Translation 3
17516 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3 1
17518 * TrustZone classification for Ingress Address Translation 4
17519 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4 1
17521 * TrustZone classification for Ingress Address Translation 5
17522 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5 1
17524 * TrustZone classification for Ingress Address Translation 6
17525 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6 1
17527 * TrustZone classification for Ingress Address Translation 7
17528 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7 1
17530 * TrustZone classification for Egress Address Translation 0
17531 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0 1
17533 * TrustZone classification for Egress Address Translation 1
17534 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1 1
17536 * TrustZone classification for Egress Address Translation 2
17537 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2 1
17539 * TrustZone classification for Egress Address Translation 3
17540 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3 1
17542 * TrustZone classification for Egress Address Translation 4
17543 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4 1
17545 * TrustZone classification for Egress Address Translation 5
17546 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5 1
17548 * TrustZone classification for Egress Address Translation 6
17549 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6 1
17551 * TrustZone classification for Egress Address Translation 7
17552 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7 1
17554 * TrustZone classification for DMA Registers
17555 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS 1
17557 * TrustZone classification for MSIx Table
17558 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE 1
17560 * TrustZone classification for MSIx PBA
17561 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA 1
17563 * TrustZone classification for ECAM
17564 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM 1
17566 * TrustZone classification for Bridge Common Registers
17567 * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS 1
17569 * PCIe TrustZone settings. This register may only be modified during bootu
17570 * p (while PCIe block is disabled)
17571 * (OFFSET, MASK, VALUE) (0XFD690030, 0x01FFFFFFU ,0x01FFFFFFU)
17573 PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_PCIE_OFFSET,
17574 0x01FFFFFFU, 0x01FFFFFFU);
17575 /*##################################################################### */
17581 * Register : slcr_usb @ 0XFF4B0034
17583 * TrustZone Classification for USB3_0
17584 * PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0 1
17586 * TrustZone Classification for USB3_1
17587 * PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1 1
17589 * USB3 TrustZone settings
17590 * (OFFSET, MASK, VALUE) (0XFF4B0034, 0x00000003U ,0x00000003U)
17592 PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_USB_OFFSET,
17593 0x00000003U, 0x00000003U);
17594 /*##################################################################### */
17600 * Register : IOU_AXI_RPRTCN @ 0XFF240004
17602 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17603 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17604 * ccess [2] = '1'' : Instruction access
17605 * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT 2
17607 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17608 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17609 * ccess [2] = '1'' : Instruction access
17610 * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT 2
17612 * AXI read protection type selection
17613 * (OFFSET, MASK, VALUE) (0XFF240004, 0x003F0000U ,0x00120000U)
17615 PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET,
17616 0x003F0000U, 0x00120000U);
17617 /*##################################################################### */
17620 * Register : IOU_AXI_WPRTCN @ 0XFF240000
17622 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17623 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17624 * ccess [2] = '1'' : Instruction access
17625 * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT 2
17627 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17628 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17629 * ccess [2] = '1'' : Instruction access
17630 * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT 2
17632 * AXI write protection type selection
17633 * (OFFSET, MASK, VALUE) (0XFF240000, 0x003F0000U ,0x00120000U)
17635 PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET,
17636 0x003F0000U, 0x00120000U);
17637 /*##################################################################### */
17643 * Register : IOU_AXI_RPRTCN @ 0XFF240004
17645 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17646 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17647 * ccess [2] = '1'' : Instruction access
17648 * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT 2
17650 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17651 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17652 * ccess [2] = '1'' : Instruction access
17653 * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT 2
17655 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17656 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17657 * ccess [2] = '1'' : Instruction access
17658 * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT 2
17660 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17661 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17662 * ccess [2] = '1'' : Instruction access
17663 * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT 2
17665 * AXI read protection type selection
17666 * (OFFSET, MASK, VALUE) (0XFF240004, 0x00000FFFU ,0x00000492U)
17668 PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET,
17669 0x00000FFFU, 0x00000492U);
17670 /*##################################################################### */
17673 * Register : IOU_AXI_WPRTCN @ 0XFF240000
17675 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17676 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17677 * ccess [2] = '1'' : Instruction access
17678 * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT 2
17680 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17681 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17682 * ccess [2] = '1'' : Instruction access
17683 * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT 2
17685 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17686 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17687 * ccess [2] = '1'' : Instruction access
17688 * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT 2
17690 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17691 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17692 * ccess [2] = '1'' : Instruction access
17693 * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT 2
17695 * AXI write protection type selection
17696 * (OFFSET, MASK, VALUE) (0XFF240000, 0x00000FFFU ,0x00000492U)
17698 PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET,
17699 0x00000FFFU, 0x00000492U);
17700 /*##################################################################### */
17706 * Register : IOU_AXI_WPRTCN @ 0XFF240000
17708 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17709 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17710 * ccess [2] = '1'' : Instruction access
17711 * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT 2
17713 * AXI write protection type selection
17714 * (OFFSET, MASK, VALUE) (0XFF240000, 0x0E000000U ,0x04000000U)
17716 PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET,
17717 0x0E000000U, 0x04000000U);
17718 /*##################################################################### */
17724 * Register : IOU_AXI_RPRTCN @ 0XFF240004
17726 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17727 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17728 * ccess [2] = '1'' : Instruction access
17729 * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT 2
17731 * AXI read protection type selection
17732 * (OFFSET, MASK, VALUE) (0XFF240004, 0x01C00000U ,0x00800000U)
17734 PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET,
17735 0x01C00000U, 0x00800000U);
17736 /*##################################################################### */
17739 * Register : IOU_AXI_WPRTCN @ 0XFF240000
17741 * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
17742 * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
17743 * ccess [2] = '1'' : Instruction access
17744 * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT 2
17746 * AXI write protection type selection
17747 * (OFFSET, MASK, VALUE) (0XFF240000, 0x01C00000U ,0x00800000U)
17749 PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET,
17750 0x01C00000U, 0x00800000U);
17751 /*##################################################################### */
17757 * Register : slcr_adma @ 0XFF4B0024
17759 * TrustZone Classification for ADMA
17760 * PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0xFF
17762 * RPU TrustZone settings
17763 * (OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU)
17765 PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_ADMA_OFFSET,
17766 0x000000FFU, 0x000000FFU);
17767 /*##################################################################### */
17770 * Register : slcr_gdma @ 0XFD690050
17772 * TrustZone Classification for GDMA
17773 * PSU_FPD_SLCR_SECURE_SLCR_GDMA_TZ 0xFF
17775 * GDMA Trustzone Settings
17776 * (OFFSET, MASK, VALUE) (0XFD690050, 0x000000FFU ,0x000000FFU)
17778 PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_GDMA_OFFSET,
17779 0x000000FFU, 0x000000FFU);
17780 /*##################################################################### */
17785 unsigned long psu_serdes_init_data(void)
17788 * SERDES INITIALIZATION
17791 * GT REFERENCE CLOCK SOURCE SELECTION
17794 * Register : PLL_REF_SEL0 @ 0XFD410000
17796 * PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1
17797 * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
17798 * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE
17799 * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
17801 * PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0 0xD
17803 * PLL0 Reference Selection Register
17804 * (OFFSET, MASK, VALUE) (0XFD410000, 0x0000001FU ,0x0000000DU)
17806 PSU_Mask_Write(SERDES_PLL_REF_SEL0_OFFSET, 0x0000001FU, 0x0000000DU);
17807 /*##################################################################### */
17810 * Register : PLL_REF_SEL1 @ 0XFD410004
17812 * PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1
17813 * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
17814 * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE
17815 * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
17817 * PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1 0x9
17819 * PLL1 Reference Selection Register
17820 * (OFFSET, MASK, VALUE) (0XFD410004, 0x0000001FU ,0x00000009U)
17822 PSU_Mask_Write(SERDES_PLL_REF_SEL1_OFFSET, 0x0000001FU, 0x00000009U);
17823 /*##################################################################### */
17826 * Register : PLL_REF_SEL2 @ 0XFD410008
17828 * PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1
17829 * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
17830 * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE
17831 * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
17833 * PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2 0x8
17835 * PLL2 Reference Selection Register
17836 * (OFFSET, MASK, VALUE) (0XFD410008, 0x0000001FU ,0x00000008U)
17838 PSU_Mask_Write(SERDES_PLL_REF_SEL2_OFFSET, 0x0000001FU, 0x00000008U);
17839 /*##################################################################### */
17842 * Register : PLL_REF_SEL3 @ 0XFD41000C
17844 * PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1
17845 * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
17846 * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE
17847 * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
17849 * PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3 0xF
17851 * PLL3 Reference Selection Register
17852 * (OFFSET, MASK, VALUE) (0XFD41000C, 0x0000001FU ,0x0000000FU)
17854 PSU_Mask_Write(SERDES_PLL_REF_SEL3_OFFSET, 0x0000001FU, 0x0000000FU);
17855 /*##################################################################### */
17858 * GT REFERENCE CLOCK FREQUENCY SELECTION
17861 * Register : L0_L0_REF_CLK_SEL @ 0XFD402860
17863 * Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer outp
17864 * ut. Set to 0 to select lane0 ref clock mux output.
17865 * PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL 0x1
17867 * Lane0 Ref Clock Selection Register
17868 * (OFFSET, MASK, VALUE) (0XFD402860, 0x00000080U ,0x00000080U)
17870 PSU_Mask_Write(SERDES_L0_L0_REF_CLK_SEL_OFFSET,
17871 0x00000080U, 0x00000080U);
17872 /*##################################################################### */
17875 * Register : L0_L1_REF_CLK_SEL @ 0XFD402864
17877 * Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer outp
17878 * ut. Set to 0 to select lane1 ref clock mux output.
17879 * PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL 0x0
17881 * Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 sli
17882 * cer output from ref clock network
17883 * PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3 0x1
17885 * Lane1 Ref Clock Selection Register
17886 * (OFFSET, MASK, VALUE) (0XFD402864, 0x00000088U ,0x00000008U)
17888 PSU_Mask_Write(SERDES_L0_L1_REF_CLK_SEL_OFFSET,
17889 0x00000088U, 0x00000008U);
17890 /*##################################################################### */
17893 * Register : L0_L2_REF_CLK_SEL @ 0XFD402868
17895 * Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer outp
17896 * ut. Set to 0 to select lane2 ref clock mux output.
17897 * PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL 0x1
17899 * Lane2 Ref Clock Selection Register
17900 * (OFFSET, MASK, VALUE) (0XFD402868, 0x00000080U ,0x00000080U)
17902 PSU_Mask_Write(SERDES_L0_L2_REF_CLK_SEL_OFFSET,
17903 0x00000080U, 0x00000080U);
17904 /*##################################################################### */
17907 * Register : L0_L3_REF_CLK_SEL @ 0XFD40286C
17909 * Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer outp
17910 * ut. Set to 0 to select lane3 ref clock mux output.
17911 * PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL 0x0
17913 * Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 sli
17914 * cer output from ref clock network
17915 * PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1 0x1
17917 * Lane3 Ref Clock Selection Register
17918 * (OFFSET, MASK, VALUE) (0XFD40286C, 0x00000082U ,0x00000002U)
17920 PSU_Mask_Write(SERDES_L0_L3_REF_CLK_SEL_OFFSET,
17921 0x00000082U, 0x00000002U);
17922 /*##################################################################### */
17925 * ENABLE SPREAD SPECTRUM
17928 * Register : L2_TM_PLL_DIG_37 @ 0XFD40A094
17930 * Enable/Disable coarse code satureation limiting logic
17931 * PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION 0x1
17933 * Test mode register 37
17934 * (OFFSET, MASK, VALUE) (0XFD40A094, 0x00000010U ,0x00000010U)
17936 PSU_Mask_Write(SERDES_L2_TM_PLL_DIG_37_OFFSET,
17937 0x00000010U, 0x00000010U);
17938 /*##################################################################### */
17941 * Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368
17943 * Spread Spectrum No of Steps [7:0]
17944 * PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x38
17946 * Spread Spectrum No of Steps bits 7:0
17947 * (OFFSET, MASK, VALUE) (0XFD40A368, 0x000000FFU ,0x00000038U)
17949 PSU_Mask_Write(SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET,
17950 0x000000FFU, 0x00000038U);
17951 /*##################################################################### */
17954 * Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C
17956 * Spread Spectrum No of Steps [10:8]
17957 * PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x03
17959 * Spread Spectrum No of Steps bits 10:8
17960 * (OFFSET, MASK, VALUE) (0XFD40A36C, 0x00000007U ,0x00000003U)
17962 PSU_Mask_Write(SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET,
17963 0x00000007U, 0x00000003U);
17964 /*##################################################################### */
17967 * Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368
17969 * Spread Spectrum No of Steps [7:0]
17970 * PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0xE0
17972 * Spread Spectrum No of Steps bits 7:0
17973 * (OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x000000E0U)
17975 PSU_Mask_Write(SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET,
17976 0x000000FFU, 0x000000E0U);
17977 /*##################################################################### */
17980 * Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C
17982 * Spread Spectrum No of Steps [10:8]
17983 * PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3
17985 * Spread Spectrum No of Steps bits 10:8
17986 * (OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000003U)
17988 PSU_Mask_Write(SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET,
17989 0x00000007U, 0x00000003U);
17990 /*##################################################################### */
17993 * Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368
17995 * Spread Spectrum No of Steps [7:0]
17996 * PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x58
17998 * Spread Spectrum No of Steps bits 7:0
17999 * (OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000058U)
18001 PSU_Mask_Write(SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET,
18002 0x000000FFU, 0x00000058U);
18003 /*##################################################################### */
18006 * Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C
18008 * Spread Spectrum No of Steps [10:8]
18009 * PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3
18011 * Spread Spectrum No of Steps bits 10:8
18012 * (OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000003U)
18014 PSU_Mask_Write(SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET,
18015 0x00000007U, 0x00000003U);
18016 /*##################################################################### */
18019 * Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370
18021 * Step Size for Spread Spectrum [7:0]
18022 * PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x7C
18024 * Step Size for Spread Spectrum LSB
18025 * (OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x0000007CU)
18027 PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET,
18028 0x000000FFU, 0x0000007CU);
18029 /*##################################################################### */
18032 * Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374
18034 * Step Size for Spread Spectrum [15:8]
18035 * PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x33
18037 * Step Size for Spread Spectrum 1
18038 * (OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000033U)
18040 PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET,
18041 0x000000FFU, 0x00000033U);
18042 /*##################################################################### */
18045 * Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378
18047 * Step Size for Spread Spectrum [23:16]
18048 * PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2
18050 * Step Size for Spread Spectrum 2
18051 * (OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000002U)
18053 PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET,
18054 0x000000FFU, 0x00000002U);
18055 /*##################################################################### */
18058 * Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C
18060 * Step Size for Spread Spectrum [25:24]
18061 * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0
18063 * Enable/Disable test mode force on SS step size
18064 * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1
18066 * Enable/Disable test mode force on SS no of steps
18067 * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1
18069 * Enable force on enable Spread Spectrum
18070 * (OFFSET, MASK, VALUE) (0XFD40637C, 0x00000033U ,0x00000030U)
18072 PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET,
18073 0x00000033U, 0x00000030U);
18074 /*##################################################################### */
18077 * Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370
18079 * Step Size for Spread Spectrum [7:0]
18080 * PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xF4
18082 * Step Size for Spread Spectrum LSB
18083 * (OFFSET, MASK, VALUE) (0XFD40A370, 0x000000FFU ,0x000000F4U)
18085 PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET,
18086 0x000000FFU, 0x000000F4U);
18087 /*##################################################################### */
18090 * Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374
18092 * Step Size for Spread Spectrum [15:8]
18093 * PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x31
18095 * Step Size for Spread Spectrum 1
18096 * (OFFSET, MASK, VALUE) (0XFD40A374, 0x000000FFU ,0x00000031U)
18098 PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET,
18099 0x000000FFU, 0x00000031U);
18100 /*##################################################################### */
18103 * Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378
18105 * Step Size for Spread Spectrum [23:16]
18106 * PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2
18108 * Step Size for Spread Spectrum 2
18109 * (OFFSET, MASK, VALUE) (0XFD40A378, 0x000000FFU ,0x00000002U)
18111 PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET,
18112 0x000000FFU, 0x00000002U);
18113 /*##################################################################### */
18116 * Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C
18118 * Step Size for Spread Spectrum [25:24]
18119 * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0
18121 * Enable/Disable test mode force on SS step size
18122 * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1
18124 * Enable/Disable test mode force on SS no of steps
18125 * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1
18127 * Enable force on enable Spread Spectrum
18128 * (OFFSET, MASK, VALUE) (0XFD40A37C, 0x00000033U ,0x00000030U)
18130 PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET,
18131 0x00000033U, 0x00000030U);
18132 /*##################################################################### */
18135 * Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370
18137 * Step Size for Spread Spectrum [7:0]
18138 * PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xC9
18140 * Step Size for Spread Spectrum LSB
18141 * (OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x000000C9U)
18143 PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET,
18144 0x000000FFU, 0x000000C9U);
18145 /*##################################################################### */
18148 * Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374
18150 * Step Size for Spread Spectrum [15:8]
18151 * PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0xD2
18153 * Step Size for Spread Spectrum 1
18154 * (OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x000000D2U)
18156 PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET,
18157 0x000000FFU, 0x000000D2U);
18158 /*##################################################################### */
18161 * Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378
18163 * Step Size for Spread Spectrum [23:16]
18164 * PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x1
18166 * Step Size for Spread Spectrum 2
18167 * (OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000001U)
18169 PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET,
18170 0x000000FFU, 0x00000001U);
18171 /*##################################################################### */
18174 * Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C
18176 * Step Size for Spread Spectrum [25:24]
18177 * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0
18179 * Enable/Disable test mode force on SS step size
18180 * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1
18182 * Enable/Disable test mode force on SS no of steps
18183 * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1
18185 * Enable test mode forcing on enable Spread Spectrum
18186 * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS 0x1
18188 * Enable force on enable Spread Spectrum
18189 * (OFFSET, MASK, VALUE) (0XFD40E37C, 0x000000B3U ,0x000000B0U)
18191 PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET,
18192 0x000000B3U, 0x000000B0U);
18193 /*##################################################################### */
18196 * Register : L2_TM_DIG_6 @ 0XFD40906C
18198 * Bypass Descrambler
18199 * PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM 0x1
18201 * Enable Bypass for <1> TM_DIG_CTRL_6
18202 * PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1
18204 * Data path test modes in decoder and descram
18205 * (OFFSET, MASK, VALUE) (0XFD40906C, 0x00000003U ,0x00000003U)
18207 PSU_Mask_Write(SERDES_L2_TM_DIG_6_OFFSET, 0x00000003U, 0x00000003U);
18208 /*##################################################################### */
18211 * Register : L2_TX_DIG_TM_61 @ 0XFD4080F4
18213 * Bypass scrambler signal
18214 * PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM 0x1
18216 * Enable/disable scrambler bypass signal
18217 * PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1
18219 * MPHY PLL Gear and bypass scrambler
18220 * (OFFSET, MASK, VALUE) (0XFD4080F4, 0x00000003U ,0x00000003U)
18222 PSU_Mask_Write(SERDES_L2_TX_DIG_TM_61_OFFSET,
18223 0x00000003U, 0x00000003U);
18224 /*##################################################################### */
18227 * Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360
18229 * Enable test mode force on fractional mode enable
18230 * PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC 0x1
18232 * Fractional feedback division control and fractional value for feedback d
18233 * ivision bits 26:24
18234 * (OFFSET, MASK, VALUE) (0XFD40E360, 0x00000040U ,0x00000040U)
18236 PSU_Mask_Write(SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET,
18237 0x00000040U, 0x00000040U);
18238 /*##################################################################### */
18241 * Register : L3_TM_DIG_6 @ 0XFD40D06C
18243 * Bypass 8b10b decoder
18244 * PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER 0x1
18246 * Enable Bypass for <3> TM_DIG_CTRL_6
18247 * PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC 0x1
18249 * Bypass Descrambler
18250 * PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM 0x1
18252 * Enable Bypass for <1> TM_DIG_CTRL_6
18253 * PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1
18255 * Data path test modes in decoder and descram
18256 * (OFFSET, MASK, VALUE) (0XFD40D06C, 0x0000000FU ,0x0000000FU)
18258 PSU_Mask_Write(SERDES_L3_TM_DIG_6_OFFSET, 0x0000000FU, 0x0000000FU);
18259 /*##################################################################### */
18262 * Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4
18264 * Enable/disable encoder bypass signal
18265 * PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC 0x1
18267 * Bypass scrambler signal
18268 * PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM 0x1
18270 * Enable/disable scrambler bypass signal
18271 * PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1
18273 * MPHY PLL Gear and bypass scrambler
18274 * (OFFSET, MASK, VALUE) (0XFD40C0F4, 0x0000000BU ,0x0000000BU)
18276 PSU_Mask_Write(SERDES_L3_TX_DIG_TM_61_OFFSET,
18277 0x0000000BU, 0x0000000BU);
18278 /*##################################################################### */
18281 * ENABLE CHICKEN BIT FOR PCIE AND USB
18284 * Register : L0_TM_AUX_0 @ 0XFD4010CC
18287 * PSU_SERDES_L0_TM_AUX_0_BIT_2 1
18290 * (OFFSET, MASK, VALUE) (0XFD4010CC, 0x00000020U ,0x00000020U)
18292 PSU_Mask_Write(SERDES_L0_TM_AUX_0_OFFSET, 0x00000020U, 0x00000020U);
18293 /*##################################################################### */
18296 * Register : L2_TM_AUX_0 @ 0XFD4090CC
18299 * PSU_SERDES_L2_TM_AUX_0_BIT_2 1
18302 * (OFFSET, MASK, VALUE) (0XFD4090CC, 0x00000020U ,0x00000020U)
18304 PSU_Mask_Write(SERDES_L2_TM_AUX_0_OFFSET, 0x00000020U, 0x00000020U);
18305 /*##################################################################### */
18308 * ENABLING EYE SURF
18311 * Register : L0_TM_DIG_8 @ 0XFD401074
18314 * PSU_SERDES_L0_TM_DIG_8_EYESURF_ENABLE 0x1
18316 * Test modes for Elastic buffer and enabling Eye Surf
18317 * (OFFSET, MASK, VALUE) (0XFD401074, 0x00000010U ,0x00000010U)
18319 PSU_Mask_Write(SERDES_L0_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U);
18320 /*##################################################################### */
18323 * Register : L1_TM_DIG_8 @ 0XFD405074
18326 * PSU_SERDES_L1_TM_DIG_8_EYESURF_ENABLE 0x1
18328 * Test modes for Elastic buffer and enabling Eye Surf
18329 * (OFFSET, MASK, VALUE) (0XFD405074, 0x00000010U ,0x00000010U)
18331 PSU_Mask_Write(SERDES_L1_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U);
18332 /*##################################################################### */
18335 * Register : L2_TM_DIG_8 @ 0XFD409074
18338 * PSU_SERDES_L2_TM_DIG_8_EYESURF_ENABLE 0x1
18340 * Test modes for Elastic buffer and enabling Eye Surf
18341 * (OFFSET, MASK, VALUE) (0XFD409074, 0x00000010U ,0x00000010U)
18343 PSU_Mask_Write(SERDES_L2_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U);
18344 /*##################################################################### */
18347 * Register : L3_TM_DIG_8 @ 0XFD40D074
18350 * PSU_SERDES_L3_TM_DIG_8_EYESURF_ENABLE 0x1
18352 * Test modes for Elastic buffer and enabling Eye Surf
18353 * (OFFSET, MASK, VALUE) (0XFD40D074, 0x00000010U ,0x00000010U)
18355 PSU_Mask_Write(SERDES_L3_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U);
18356 /*##################################################################### */
18359 * ILL SETTINGS FOR GAIN AND LOCK SETTINGS
18362 * Register : L0_TM_MISC2 @ 0XFD40189C
18364 * ILL calib counts BYPASSED with calcode bits
18365 * PSU_SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
18368 * (OFFSET, MASK, VALUE) (0XFD40189C, 0x00000080U ,0x00000080U)
18370 PSU_Mask_Write(SERDES_L0_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U);
18371 /*##################################################################### */
18374 * Register : L0_TM_IQ_ILL1 @ 0XFD4018F8
18376 * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 ,
18378 * PSU_SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x64
18381 * (OFFSET, MASK, VALUE) (0XFD4018F8, 0x000000FFU ,0x00000064U)
18383 PSU_Mask_Write(SERDES_L0_TM_IQ_ILL1_OFFSET,
18384 0x000000FFU, 0x00000064U);
18385 /*##################################################################### */
18388 * Register : L0_TM_IQ_ILL2 @ 0XFD4018FC
18390 * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
18391 * PSU_SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x64
18394 * (OFFSET, MASK, VALUE) (0XFD4018FC, 0x000000FFU ,0x00000064U)
18396 PSU_Mask_Write(SERDES_L0_TM_IQ_ILL2_OFFSET,
18397 0x000000FFU, 0x00000064U);
18398 /*##################################################################### */
18401 * Register : L0_TM_ILL12 @ 0XFD401990
18403 * G1A pll ctr bypass value
18404 * PSU_SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x11
18406 * ill pll counter values
18407 * (OFFSET, MASK, VALUE) (0XFD401990, 0x000000FFU ,0x00000011U)
18409 PSU_Mask_Write(SERDES_L0_TM_ILL12_OFFSET, 0x000000FFU, 0x00000011U);
18410 /*##################################################################### */
18413 * Register : L0_TM_E_ILL1 @ 0XFD401924
18415 * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U
18417 * PSU_SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x4
18420 * (OFFSET, MASK, VALUE) (0XFD401924, 0x000000FFU ,0x00000004U)
18422 PSU_Mask_Write(SERDES_L0_TM_E_ILL1_OFFSET, 0x000000FFU, 0x00000004U);
18423 /*##################################################################### */
18426 * Register : L0_TM_E_ILL2 @ 0XFD401928
18428 * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
18429 * PSU_SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0xFE
18432 * (OFFSET, MASK, VALUE) (0XFD401928, 0x000000FFU ,0x000000FEU)
18434 PSU_Mask_Write(SERDES_L0_TM_E_ILL2_OFFSET, 0x000000FFU, 0x000000FEU);
18435 /*##################################################################### */
18438 * Register : L0_TM_IQ_ILL3 @ 0XFD401900
18440 * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
18441 * PSU_SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x64
18444 * (OFFSET, MASK, VALUE) (0XFD401900, 0x000000FFU ,0x00000064U)
18446 PSU_Mask_Write(SERDES_L0_TM_IQ_ILL3_OFFSET,
18447 0x000000FFU, 0x00000064U);
18448 /*##################################################################### */
18451 * Register : L0_TM_E_ILL3 @ 0XFD40192C
18453 * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
18454 * PSU_SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0
18457 * (OFFSET, MASK, VALUE) (0XFD40192C, 0x000000FFU ,0x00000000U)
18459 PSU_Mask_Write(SERDES_L0_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000000U);
18460 /*##################################################################### */
18463 * Register : L0_TM_ILL8 @ 0XFD401980
18465 * ILL calibration code change wait time
18466 * PSU_SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
18468 * ILL cal routine control
18469 * (OFFSET, MASK, VALUE) (0XFD401980, 0x000000FFU ,0x000000FFU)
18471 PSU_Mask_Write(SERDES_L0_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU);
18472 /*##################################################################### */
18475 * Register : L0_TM_IQ_ILL8 @ 0XFD401914
18477 * IQ ILL polytrim bypass value
18478 * PSU_SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
18481 * (OFFSET, MASK, VALUE) (0XFD401914, 0x000000FFU ,0x000000F7U)
18483 PSU_Mask_Write(SERDES_L0_TM_IQ_ILL8_OFFSET,
18484 0x000000FFU, 0x000000F7U);
18485 /*##################################################################### */
18488 * Register : L0_TM_IQ_ILL9 @ 0XFD401918
18490 * bypass IQ polytrim
18491 * PSU_SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
18493 * enables for lf,constant gm trim and polytirm
18494 * (OFFSET, MASK, VALUE) (0XFD401918, 0x00000001U ,0x00000001U)
18496 PSU_Mask_Write(SERDES_L0_TM_IQ_ILL9_OFFSET,
18497 0x00000001U, 0x00000001U);
18498 /*##################################################################### */
18501 * Register : L0_TM_E_ILL8 @ 0XFD401940
18503 * E ILL polytrim bypass value
18504 * PSU_SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
18507 * (OFFSET, MASK, VALUE) (0XFD401940, 0x000000FFU ,0x000000F7U)
18509 PSU_Mask_Write(SERDES_L0_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U);
18510 /*##################################################################### */
18513 * Register : L0_TM_E_ILL9 @ 0XFD401944
18515 * bypass E polytrim
18516 * PSU_SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
18518 * enables for lf,constant gm trim and polytirm
18519 * (OFFSET, MASK, VALUE) (0XFD401944, 0x00000001U ,0x00000001U)
18521 PSU_Mask_Write(SERDES_L0_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U);
18522 /*##################################################################### */
18525 * Register : L0_TM_ILL13 @ 0XFD401994
18527 * ILL cal idle val refcnt
18528 * PSU_SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7
18530 * ill cal idle value count
18531 * (OFFSET, MASK, VALUE) (0XFD401994, 0x00000007U ,0x00000007U)
18533 PSU_Mask_Write(SERDES_L0_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U);
18534 /*##################################################################### */
18537 * Register : L1_TM_ILL13 @ 0XFD405994
18539 * ILL cal idle val refcnt
18540 * PSU_SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7
18542 * ill cal idle value count
18543 * (OFFSET, MASK, VALUE) (0XFD405994, 0x00000007U ,0x00000007U)
18545 PSU_Mask_Write(SERDES_L1_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U);
18546 /*##################################################################### */
18549 * Register : L2_TM_MISC2 @ 0XFD40989C
18551 * ILL calib counts BYPASSED with calcode bits
18552 * PSU_SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
18555 * (OFFSET, MASK, VALUE) (0XFD40989C, 0x00000080U ,0x00000080U)
18557 PSU_Mask_Write(SERDES_L2_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U);
18558 /*##################################################################### */
18561 * Register : L2_TM_IQ_ILL1 @ 0XFD4098F8
18563 * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 ,
18565 * PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x1A
18568 * (OFFSET, MASK, VALUE) (0XFD4098F8, 0x000000FFU ,0x0000001AU)
18570 PSU_Mask_Write(SERDES_L2_TM_IQ_ILL1_OFFSET,
18571 0x000000FFU, 0x0000001AU);
18572 /*##################################################################### */
18575 * Register : L2_TM_IQ_ILL2 @ 0XFD4098FC
18577 * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
18578 * PSU_SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x1A
18581 * (OFFSET, MASK, VALUE) (0XFD4098FC, 0x000000FFU ,0x0000001AU)
18583 PSU_Mask_Write(SERDES_L2_TM_IQ_ILL2_OFFSET,
18584 0x000000FFU, 0x0000001AU);
18585 /*##################################################################### */
18588 * Register : L2_TM_ILL12 @ 0XFD409990
18590 * G1A pll ctr bypass value
18591 * PSU_SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x10
18593 * ill pll counter values
18594 * (OFFSET, MASK, VALUE) (0XFD409990, 0x000000FFU ,0x00000010U)
18596 PSU_Mask_Write(SERDES_L2_TM_ILL12_OFFSET, 0x000000FFU, 0x00000010U);
18597 /*##################################################################### */
18600 * Register : L2_TM_E_ILL1 @ 0XFD409924
18602 * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U
18604 * PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0xFE
18607 * (OFFSET, MASK, VALUE) (0XFD409924, 0x000000FFU ,0x000000FEU)
18609 PSU_Mask_Write(SERDES_L2_TM_E_ILL1_OFFSET, 0x000000FFU, 0x000000FEU);
18610 /*##################################################################### */
18613 * Register : L2_TM_E_ILL2 @ 0XFD409928
18615 * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
18616 * PSU_SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x0
18619 * (OFFSET, MASK, VALUE) (0XFD409928, 0x000000FFU ,0x00000000U)
18621 PSU_Mask_Write(SERDES_L2_TM_E_ILL2_OFFSET, 0x000000FFU, 0x00000000U);
18622 /*##################################################################### */
18625 * Register : L2_TM_IQ_ILL3 @ 0XFD409900
18627 * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
18628 * PSU_SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x1A
18631 * (OFFSET, MASK, VALUE) (0XFD409900, 0x000000FFU ,0x0000001AU)
18633 PSU_Mask_Write(SERDES_L2_TM_IQ_ILL3_OFFSET,
18634 0x000000FFU, 0x0000001AU);
18635 /*##################################################################### */
18638 * Register : L2_TM_E_ILL3 @ 0XFD40992C
18640 * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
18641 * PSU_SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0
18644 * (OFFSET, MASK, VALUE) (0XFD40992C, 0x000000FFU ,0x00000000U)
18646 PSU_Mask_Write(SERDES_L2_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000000U);
18647 /*##################################################################### */
18650 * Register : L2_TM_ILL8 @ 0XFD409980
18652 * ILL calibration code change wait time
18653 * PSU_SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
18655 * ILL cal routine control
18656 * (OFFSET, MASK, VALUE) (0XFD409980, 0x000000FFU ,0x000000FFU)
18658 PSU_Mask_Write(SERDES_L2_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU);
18659 /*##################################################################### */
18662 * Register : L2_TM_IQ_ILL8 @ 0XFD409914
18664 * IQ ILL polytrim bypass value
18665 * PSU_SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
18668 * (OFFSET, MASK, VALUE) (0XFD409914, 0x000000FFU ,0x000000F7U)
18670 PSU_Mask_Write(SERDES_L2_TM_IQ_ILL8_OFFSET,
18671 0x000000FFU, 0x000000F7U);
18672 /*##################################################################### */
18675 * Register : L2_TM_IQ_ILL9 @ 0XFD409918
18677 * bypass IQ polytrim
18678 * PSU_SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
18680 * enables for lf,constant gm trim and polytirm
18681 * (OFFSET, MASK, VALUE) (0XFD409918, 0x00000001U ,0x00000001U)
18683 PSU_Mask_Write(SERDES_L2_TM_IQ_ILL9_OFFSET,
18684 0x00000001U, 0x00000001U);
18685 /*##################################################################### */
18688 * Register : L2_TM_E_ILL8 @ 0XFD409940
18690 * E ILL polytrim bypass value
18691 * PSU_SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
18694 * (OFFSET, MASK, VALUE) (0XFD409940, 0x000000FFU ,0x000000F7U)
18696 PSU_Mask_Write(SERDES_L2_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U);
18697 /*##################################################################### */
18700 * Register : L2_TM_E_ILL9 @ 0XFD409944
18702 * bypass E polytrim
18703 * PSU_SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
18705 * enables for lf,constant gm trim and polytirm
18706 * (OFFSET, MASK, VALUE) (0XFD409944, 0x00000001U ,0x00000001U)
18708 PSU_Mask_Write(SERDES_L2_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U);
18709 /*##################################################################### */
18712 * Register : L2_TM_ILL13 @ 0XFD409994
18714 * ILL cal idle val refcnt
18715 * PSU_SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7
18717 * ill cal idle value count
18718 * (OFFSET, MASK, VALUE) (0XFD409994, 0x00000007U ,0x00000007U)
18720 PSU_Mask_Write(SERDES_L2_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U);
18721 /*##################################################################### */
18724 * Register : L3_TM_MISC2 @ 0XFD40D89C
18726 * ILL calib counts BYPASSED with calcode bits
18727 * PSU_SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
18730 * (OFFSET, MASK, VALUE) (0XFD40D89C, 0x00000080U ,0x00000080U)
18732 PSU_Mask_Write(SERDES_L3_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U);
18733 /*##################################################################### */
18736 * Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8
18738 * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 ,
18740 * PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x7D
18743 * (OFFSET, MASK, VALUE) (0XFD40D8F8, 0x000000FFU ,0x0000007DU)
18745 PSU_Mask_Write(SERDES_L3_TM_IQ_ILL1_OFFSET,
18746 0x000000FFU, 0x0000007DU);
18747 /*##################################################################### */
18750 * Register : L3_TM_IQ_ILL2 @ 0XFD40D8FC
18752 * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
18753 * PSU_SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x7D
18756 * (OFFSET, MASK, VALUE) (0XFD40D8FC, 0x000000FFU ,0x0000007DU)
18758 PSU_Mask_Write(SERDES_L3_TM_IQ_ILL2_OFFSET,
18759 0x000000FFU, 0x0000007DU);
18760 /*##################################################################### */
18763 * Register : L3_TM_ILL12 @ 0XFD40D990
18765 * G1A pll ctr bypass value
18766 * PSU_SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x1
18768 * ill pll counter values
18769 * (OFFSET, MASK, VALUE) (0XFD40D990, 0x000000FFU ,0x00000001U)
18771 PSU_Mask_Write(SERDES_L3_TM_ILL12_OFFSET, 0x000000FFU, 0x00000001U);
18772 /*##################################################################### */
18775 * Register : L3_TM_E_ILL1 @ 0XFD40D924
18777 * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U
18779 * PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x9C
18782 * (OFFSET, MASK, VALUE) (0XFD40D924, 0x000000FFU ,0x0000009CU)
18784 PSU_Mask_Write(SERDES_L3_TM_E_ILL1_OFFSET, 0x000000FFU, 0x0000009CU);
18785 /*##################################################################### */
18788 * Register : L3_TM_E_ILL2 @ 0XFD40D928
18790 * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
18791 * PSU_SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x39
18794 * (OFFSET, MASK, VALUE) (0XFD40D928, 0x000000FFU ,0x00000039U)
18796 PSU_Mask_Write(SERDES_L3_TM_E_ILL2_OFFSET, 0x000000FFU, 0x00000039U);
18797 /*##################################################################### */
18800 * Register : L3_TM_ILL11 @ 0XFD40D98C
18802 * G2A_PCIe1 PLL ctr bypass value
18803 * PSU_SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL 0x2
18805 * ill pll counter values
18806 * (OFFSET, MASK, VALUE) (0XFD40D98C, 0x000000F0U ,0x00000020U)
18808 PSU_Mask_Write(SERDES_L3_TM_ILL11_OFFSET, 0x000000F0U, 0x00000020U);
18809 /*##################################################################### */
18812 * Register : L3_TM_IQ_ILL3 @ 0XFD40D900
18814 * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
18815 * PSU_SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x7D
18818 * (OFFSET, MASK, VALUE) (0XFD40D900, 0x000000FFU ,0x0000007DU)
18820 PSU_Mask_Write(SERDES_L3_TM_IQ_ILL3_OFFSET,
18821 0x000000FFU, 0x0000007DU);
18822 /*##################################################################### */
18825 * Register : L3_TM_E_ILL3 @ 0XFD40D92C
18827 * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
18828 * PSU_SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x64
18831 * (OFFSET, MASK, VALUE) (0XFD40D92C, 0x000000FFU ,0x00000064U)
18833 PSU_Mask_Write(SERDES_L3_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000064U);
18834 /*##################################################################### */
18837 * Register : L3_TM_ILL8 @ 0XFD40D980
18839 * ILL calibration code change wait time
18840 * PSU_SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
18842 * ILL cal routine control
18843 * (OFFSET, MASK, VALUE) (0XFD40D980, 0x000000FFU ,0x000000FFU)
18845 PSU_Mask_Write(SERDES_L3_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU);
18846 /*##################################################################### */
18849 * Register : L3_TM_IQ_ILL8 @ 0XFD40D914
18851 * IQ ILL polytrim bypass value
18852 * PSU_SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
18855 * (OFFSET, MASK, VALUE) (0XFD40D914, 0x000000FFU ,0x000000F7U)
18857 PSU_Mask_Write(SERDES_L3_TM_IQ_ILL8_OFFSET,
18858 0x000000FFU, 0x000000F7U);
18859 /*##################################################################### */
18862 * Register : L3_TM_IQ_ILL9 @ 0XFD40D918
18864 * bypass IQ polytrim
18865 * PSU_SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
18867 * enables for lf,constant gm trim and polytirm
18868 * (OFFSET, MASK, VALUE) (0XFD40D918, 0x00000001U ,0x00000001U)
18870 PSU_Mask_Write(SERDES_L3_TM_IQ_ILL9_OFFSET,
18871 0x00000001U, 0x00000001U);
18872 /*##################################################################### */
18875 * Register : L3_TM_E_ILL8 @ 0XFD40D940
18877 * E ILL polytrim bypass value
18878 * PSU_SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
18881 * (OFFSET, MASK, VALUE) (0XFD40D940, 0x000000FFU ,0x000000F7U)
18883 PSU_Mask_Write(SERDES_L3_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U);
18884 /*##################################################################### */
18887 * Register : L3_TM_E_ILL9 @ 0XFD40D944
18889 * bypass E polytrim
18890 * PSU_SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
18892 * enables for lf,constant gm trim and polytirm
18893 * (OFFSET, MASK, VALUE) (0XFD40D944, 0x00000001U ,0x00000001U)
18895 PSU_Mask_Write(SERDES_L3_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U);
18896 /*##################################################################### */
18899 * Register : L3_TM_ILL13 @ 0XFD40D994
18901 * ILL cal idle val refcnt
18902 * PSU_SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7
18904 * ill cal idle value count
18905 * (OFFSET, MASK, VALUE) (0XFD40D994, 0x00000007U ,0x00000007U)
18907 PSU_Mask_Write(SERDES_L3_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U);
18908 /*##################################################################### */
18911 * SYMBOL LOCK AND WAIT
18914 * Register : L0_TM_DIG_10 @ 0XFD40107C
18916 * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
18917 * PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1
18919 * test control for changing cdr lock wait time
18920 * (OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x00000001U)
18922 PSU_Mask_Write(SERDES_L0_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U);
18923 /*##################################################################### */
18926 * Register : L1_TM_DIG_10 @ 0XFD40507C
18928 * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
18929 * PSU_SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1
18931 * test control for changing cdr lock wait time
18932 * (OFFSET, MASK, VALUE) (0XFD40507C, 0x0000000FU ,0x00000001U)
18934 PSU_Mask_Write(SERDES_L1_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U);
18935 /*##################################################################### */
18938 * Register : L2_TM_DIG_10 @ 0XFD40907C
18940 * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
18941 * PSU_SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1
18943 * test control for changing cdr lock wait time
18944 * (OFFSET, MASK, VALUE) (0XFD40907C, 0x0000000FU ,0x00000001U)
18946 PSU_Mask_Write(SERDES_L2_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U);
18947 /*##################################################################### */
18950 * Register : L3_TM_DIG_10 @ 0XFD40D07C
18952 * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
18953 * PSU_SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1
18955 * test control for changing cdr lock wait time
18956 * (OFFSET, MASK, VALUE) (0XFD40D07C, 0x0000000FU ,0x00000001U)
18958 PSU_Mask_Write(SERDES_L3_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U);
18959 /*##################################################################### */
18962 * SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG
18965 * Register : L0_TM_RST_DLY @ 0XFD4019A4
18967 * Delay apb reset by specified amount
18968 * PSU_SERDES_L0_TM_RST_DLY_APB_RST_DLY 0xFF
18970 * reset delay for apb reset w.r.t pso of hsrx
18971 * (OFFSET, MASK, VALUE) (0XFD4019A4, 0x000000FFU ,0x000000FFU)
18973 PSU_Mask_Write(SERDES_L0_TM_RST_DLY_OFFSET,
18974 0x000000FFU, 0x000000FFU);
18975 /*##################################################################### */
18978 * Register : L0_TM_ANA_BYP_15 @ 0XFD401038
18980 * Enable Bypass for <7> of TM_ANA_BYPS_15
18981 * PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
18983 * Bypass control for pcs-pma interface. EQ supplies, main master supply an
18984 * d ps for samp c2c
18985 * (OFFSET, MASK, VALUE) (0XFD401038, 0x00000040U ,0x00000040U)
18987 PSU_Mask_Write(SERDES_L0_TM_ANA_BYP_15_OFFSET,
18988 0x00000040U, 0x00000040U);
18989 /*##################################################################### */
18992 * Register : L0_TM_ANA_BYP_12 @ 0XFD40102C
18994 * Enable Bypass for <7> of TM_ANA_BYPS_12
18995 * PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
18997 * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena
18999 * (OFFSET, MASK, VALUE) (0XFD40102C, 0x00000040U ,0x00000040U)
19001 PSU_Mask_Write(SERDES_L0_TM_ANA_BYP_12_OFFSET,
19002 0x00000040U, 0x00000040U);
19003 /*##################################################################### */
19006 * Register : L1_TM_RST_DLY @ 0XFD4059A4
19008 * Delay apb reset by specified amount
19009 * PSU_SERDES_L1_TM_RST_DLY_APB_RST_DLY 0xFF
19011 * reset delay for apb reset w.r.t pso of hsrx
19012 * (OFFSET, MASK, VALUE) (0XFD4059A4, 0x000000FFU ,0x000000FFU)
19014 PSU_Mask_Write(SERDES_L1_TM_RST_DLY_OFFSET,
19015 0x000000FFU, 0x000000FFU);
19016 /*##################################################################### */
19019 * Register : L1_TM_ANA_BYP_15 @ 0XFD405038
19021 * Enable Bypass for <7> of TM_ANA_BYPS_15
19022 * PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
19024 * Bypass control for pcs-pma interface. EQ supplies, main master supply an
19025 * d ps for samp c2c
19026 * (OFFSET, MASK, VALUE) (0XFD405038, 0x00000040U ,0x00000040U)
19028 PSU_Mask_Write(SERDES_L1_TM_ANA_BYP_15_OFFSET,
19029 0x00000040U, 0x00000040U);
19030 /*##################################################################### */
19033 * Register : L1_TM_ANA_BYP_12 @ 0XFD40502C
19035 * Enable Bypass for <7> of TM_ANA_BYPS_12
19036 * PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
19038 * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena
19040 * (OFFSET, MASK, VALUE) (0XFD40502C, 0x00000040U ,0x00000040U)
19042 PSU_Mask_Write(SERDES_L1_TM_ANA_BYP_12_OFFSET,
19043 0x00000040U, 0x00000040U);
19044 /*##################################################################### */
19047 * Register : L2_TM_RST_DLY @ 0XFD4099A4
19049 * Delay apb reset by specified amount
19050 * PSU_SERDES_L2_TM_RST_DLY_APB_RST_DLY 0xFF
19052 * reset delay for apb reset w.r.t pso of hsrx
19053 * (OFFSET, MASK, VALUE) (0XFD4099A4, 0x000000FFU ,0x000000FFU)
19055 PSU_Mask_Write(SERDES_L2_TM_RST_DLY_OFFSET,
19056 0x000000FFU, 0x000000FFU);
19057 /*##################################################################### */
19060 * Register : L2_TM_ANA_BYP_15 @ 0XFD409038
19062 * Enable Bypass for <7> of TM_ANA_BYPS_15
19063 * PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
19065 * Bypass control for pcs-pma interface. EQ supplies, main master supply an
19066 * d ps for samp c2c
19067 * (OFFSET, MASK, VALUE) (0XFD409038, 0x00000040U ,0x00000040U)
19069 PSU_Mask_Write(SERDES_L2_TM_ANA_BYP_15_OFFSET,
19070 0x00000040U, 0x00000040U);
19071 /*##################################################################### */
19074 * Register : L2_TM_ANA_BYP_12 @ 0XFD40902C
19076 * Enable Bypass for <7> of TM_ANA_BYPS_12
19077 * PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
19079 * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena
19081 * (OFFSET, MASK, VALUE) (0XFD40902C, 0x00000040U ,0x00000040U)
19083 PSU_Mask_Write(SERDES_L2_TM_ANA_BYP_12_OFFSET,
19084 0x00000040U, 0x00000040U);
19085 /*##################################################################### */
19088 * Register : L3_TM_RST_DLY @ 0XFD40D9A4
19090 * Delay apb reset by specified amount
19091 * PSU_SERDES_L3_TM_RST_DLY_APB_RST_DLY 0xFF
19093 * reset delay for apb reset w.r.t pso of hsrx
19094 * (OFFSET, MASK, VALUE) (0XFD40D9A4, 0x000000FFU ,0x000000FFU)
19096 PSU_Mask_Write(SERDES_L3_TM_RST_DLY_OFFSET,
19097 0x000000FFU, 0x000000FFU);
19098 /*##################################################################### */
19101 * Register : L3_TM_ANA_BYP_15 @ 0XFD40D038
19103 * Enable Bypass for <7> of TM_ANA_BYPS_15
19104 * PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
19106 * Bypass control for pcs-pma interface. EQ supplies, main master supply an
19107 * d ps for samp c2c
19108 * (OFFSET, MASK, VALUE) (0XFD40D038, 0x00000040U ,0x00000040U)
19110 PSU_Mask_Write(SERDES_L3_TM_ANA_BYP_15_OFFSET,
19111 0x00000040U, 0x00000040U);
19112 /*##################################################################### */
19115 * Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C
19117 * Enable Bypass for <7> of TM_ANA_BYPS_12
19118 * PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
19120 * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena
19122 * (OFFSET, MASK, VALUE) (0XFD40D02C, 0x00000040U ,0x00000040U)
19124 PSU_Mask_Write(SERDES_L3_TM_ANA_BYP_12_OFFSET,
19125 0x00000040U, 0x00000040U);
19126 /*##################################################################### */
19132 * Register : L0_TM_MISC3 @ 0XFD4019AC
19134 * CDR fast phase lock control
19135 * PSU_SERDES_L0_TM_MISC3_CDR_EN_FPL 0x0
19137 * CDR fast frequency lock control
19138 * PSU_SERDES_L0_TM_MISC3_CDR_EN_FFL 0x0
19140 * debug bus selection bit, cdr fast phase and freq controls
19141 * (OFFSET, MASK, VALUE) (0XFD4019AC, 0x00000003U ,0x00000000U)
19143 PSU_Mask_Write(SERDES_L0_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U);
19144 /*##################################################################### */
19147 * Register : L1_TM_MISC3 @ 0XFD4059AC
19149 * CDR fast phase lock control
19150 * PSU_SERDES_L1_TM_MISC3_CDR_EN_FPL 0x0
19152 * CDR fast frequency lock control
19153 * PSU_SERDES_L1_TM_MISC3_CDR_EN_FFL 0x0
19155 * debug bus selection bit, cdr fast phase and freq controls
19156 * (OFFSET, MASK, VALUE) (0XFD4059AC, 0x00000003U ,0x00000000U)
19158 PSU_Mask_Write(SERDES_L1_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U);
19159 /*##################################################################### */
19162 * Register : L2_TM_MISC3 @ 0XFD4099AC
19164 * CDR fast phase lock control
19165 * PSU_SERDES_L2_TM_MISC3_CDR_EN_FPL 0x0
19167 * CDR fast frequency lock control
19168 * PSU_SERDES_L2_TM_MISC3_CDR_EN_FFL 0x0
19170 * debug bus selection bit, cdr fast phase and freq controls
19171 * (OFFSET, MASK, VALUE) (0XFD4099AC, 0x00000003U ,0x00000000U)
19173 PSU_Mask_Write(SERDES_L2_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U);
19174 /*##################################################################### */
19177 * Register : L3_TM_MISC3 @ 0XFD40D9AC
19179 * CDR fast phase lock control
19180 * PSU_SERDES_L3_TM_MISC3_CDR_EN_FPL 0x0
19182 * CDR fast frequency lock control
19183 * PSU_SERDES_L3_TM_MISC3_CDR_EN_FFL 0x0
19185 * debug bus selection bit, cdr fast phase and freq controls
19186 * (OFFSET, MASK, VALUE) (0XFD40D9AC, 0x00000003U ,0x00000000U)
19188 PSU_Mask_Write(SERDES_L3_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U);
19189 /*##################################################################### */
19192 * DISABLE DYNAMIC OFFSET CALIBRATION
19195 * Register : L0_TM_EQ11 @ 0XFD401978
19197 * Force EQ offset correction algo off if not forced on
19198 * PSU_SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1
19200 * eq dynamic offset correction
19201 * (OFFSET, MASK, VALUE) (0XFD401978, 0x00000010U ,0x00000010U)
19203 PSU_Mask_Write(SERDES_L0_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U);
19204 /*##################################################################### */
19207 * Register : L1_TM_EQ11 @ 0XFD405978
19209 * Force EQ offset correction algo off if not forced on
19210 * PSU_SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1
19212 * eq dynamic offset correction
19213 * (OFFSET, MASK, VALUE) (0XFD405978, 0x00000010U ,0x00000010U)
19215 PSU_Mask_Write(SERDES_L1_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U);
19216 /*##################################################################### */
19219 * Register : L2_TM_EQ11 @ 0XFD409978
19221 * Force EQ offset correction algo off if not forced on
19222 * PSU_SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1
19224 * eq dynamic offset correction
19225 * (OFFSET, MASK, VALUE) (0XFD409978, 0x00000010U ,0x00000010U)
19227 PSU_Mask_Write(SERDES_L2_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U);
19228 /*##################################################################### */
19231 * Register : L3_TM_EQ11 @ 0XFD40D978
19233 * Force EQ offset correction algo off if not forced on
19234 * PSU_SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1
19236 * eq dynamic offset correction
19237 * (OFFSET, MASK, VALUE) (0XFD40D978, 0x00000010U ,0x00000010U)
19239 PSU_Mask_Write(SERDES_L3_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U);
19240 /*##################################################################### */
19243 * DISABLE ECO FOR PCIE
19246 * Register : eco_0 @ 0XFD3D001C
19249 * PSU_SIOU_ECO_0_FIELD 0x1
19251 * ECO Register for future use
19252 * (OFFSET, MASK, VALUE) (0XFD3D001C, 0xFFFFFFFFU ,0x00000001U)
19254 PSU_Mask_Write(SIOU_ECO_0_OFFSET, 0xFFFFFFFFU, 0x00000001U);
19255 /*##################################################################### */
19261 * Register : ICM_CFG0 @ 0XFD410010
19263 * Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0,
19264 * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unused, 7 - Unused
19265 * PSU_SERDES_ICM_CFG0_L0_ICM_CFG 1
19267 * Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1,
19268 * 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused, 7 - Unused
19269 * PSU_SERDES_ICM_CFG0_L1_ICM_CFG 4
19271 * ICM Configuration Register 0
19272 * (OFFSET, MASK, VALUE) (0XFD410010, 0x00000077U ,0x00000041U)
19274 PSU_Mask_Write(SERDES_ICM_CFG0_OFFSET, 0x00000077U, 0x00000041U);
19275 /*##################################################################### */
19278 * Register : ICM_CFG1 @ 0XFD410014
19280 * Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1,
19281 * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused, 7 - Unused
19282 * PSU_SERDES_ICM_CFG1_L2_ICM_CFG 3
19284 * Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3,
19285 * 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused, 7 - Unused
19286 * PSU_SERDES_ICM_CFG1_L3_ICM_CFG 2
19288 * ICM Configuration Register 1
19289 * (OFFSET, MASK, VALUE) (0XFD410014, 0x00000077U ,0x00000023U)
19291 PSU_Mask_Write(SERDES_ICM_CFG1_OFFSET, 0x00000077U, 0x00000023U);
19292 /*##################################################################### */
19295 * CHECKING PLL LOCK
19298 * ENABLE SERIAL DATA MUX DEEMPH
19301 * Register : L1_TXPMD_TM_45 @ 0XFD404CB4
19303 * Enable/disable DP post2 path
19304 * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1
19306 * Override enable/disable of DP post2 path
19307 * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1
19309 * Override enable/disable of DP post1 path
19310 * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1
19312 * Enable/disable DP main path
19313 * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1
19315 * Override enable/disable of DP main path
19316 * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1
19318 * Post or pre or main DP path selection
19319 * (OFFSET, MASK, VALUE) (0XFD404CB4, 0x00000037U ,0x00000037U)
19321 PSU_Mask_Write(SERDES_L1_TXPMD_TM_45_OFFSET,
19322 0x00000037U, 0x00000037U);
19323 /*##################################################################### */
19326 * Register : L1_TX_ANA_TM_118 @ 0XFD4041D8
19328 * Test register force for enabling/disablign TX deemphasis bits <17:0>
19329 * PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1
19331 * Enable Override of TX deemphasis
19332 * (OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U)
19334 PSU_Mask_Write(SERDES_L1_TX_ANA_TM_118_OFFSET,
19335 0x00000001U, 0x00000001U);
19336 /*##################################################################### */
19339 * Register : L3_TX_ANA_TM_118 @ 0XFD40C1D8
19341 * Test register force for enabling/disablign TX deemphasis bits <17:0>
19342 * PSU_SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1
19344 * Enable Override of TX deemphasis
19345 * (OFFSET, MASK, VALUE) (0XFD40C1D8, 0x00000001U ,0x00000001U)
19347 PSU_Mask_Write(SERDES_L3_TX_ANA_TM_118_OFFSET,
19348 0x00000001U, 0x00000001U);
19349 /*##################################################################### */
19352 * CDR AND RX EQUALIZATION SETTINGS
19355 * Register : L3_TM_CDR5 @ 0XFD40DC14
19357 * FPHL FSM accumulate cycles
19358 * PSU_SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES 0x7
19360 * FFL Phase0 int gain aka 2ol SD update rate
19361 * PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN 0x6
19363 * Fast phase lock controls -- FSM accumulator cycle control and phase 0 in
19365 * (OFFSET, MASK, VALUE) (0XFD40DC14, 0x000000FFU ,0x000000E6U)
19367 PSU_Mask_Write(SERDES_L3_TM_CDR5_OFFSET, 0x000000FFU, 0x000000E6U);
19368 /*##################################################################### */
19371 * Register : L3_TM_CDR16 @ 0XFD40DC40
19373 * FFL Phase0 prop gain aka 1ol SD update rate
19374 * PSU_SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN 0xC
19376 * Fast phase lock controls -- phase 0 prop gain
19377 * (OFFSET, MASK, VALUE) (0XFD40DC40, 0x0000001FU ,0x0000000CU)
19379 PSU_Mask_Write(SERDES_L3_TM_CDR16_OFFSET, 0x0000001FU, 0x0000000CU);
19380 /*##################################################################### */
19383 * Register : L3_TM_EQ0 @ 0XFD40D94C
19385 * EQ stg 2 controls BYPASSED
19386 * PSU_SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP 1
19388 * eq stg1 and stg2 controls
19389 * (OFFSET, MASK, VALUE) (0XFD40D94C, 0x00000020U ,0x00000020U)
19391 PSU_Mask_Write(SERDES_L3_TM_EQ0_OFFSET, 0x00000020U, 0x00000020U);
19392 /*##################################################################### */
19395 * Register : L3_TM_EQ1 @ 0XFD40D950
19398 * PSU_SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG 0x2
19400 * EQ stg 2 preamp mode val
19401 * PSU_SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL 0x1
19403 * eq stg1 and stg2 controls
19404 * (OFFSET, MASK, VALUE) (0XFD40D950, 0x00000007U ,0x00000006U)
19406 PSU_Mask_Write(SERDES_L3_TM_EQ1_OFFSET, 0x00000007U, 0x00000006U);
19407 /*##################################################################### */
19410 * GEM SERDES SETTINGS
19413 * ENABLE PRE EMPHAIS AND VOLTAGE SWING
19416 * Register : L1_TXPMD_TM_48 @ 0XFD404CC0
19418 * Margining factor value
19419 * PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR 0
19422 * (OFFSET, MASK, VALUE) (0XFD404CC0, 0x0000001FU ,0x00000000U)
19424 PSU_Mask_Write(SERDES_L1_TXPMD_TM_48_OFFSET,
19425 0x0000001FU, 0x00000000U);
19426 /*##################################################################### */
19429 * Register : L1_TX_ANA_TM_18 @ 0XFD404048
19431 * pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em
19432 * phasis, Others: reserved
19433 * PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0
19435 * Override for PIPE TX de-emphasis
19436 * (OFFSET, MASK, VALUE) (0XFD404048, 0x000000FFU ,0x00000000U)
19438 PSU_Mask_Write(SERDES_L1_TX_ANA_TM_18_OFFSET,
19439 0x000000FFU, 0x00000000U);
19440 /*##################################################################### */
19443 * Register : L3_TX_ANA_TM_18 @ 0XFD40C048
19445 * pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em
19446 * phasis, Others: reserved
19447 * PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0x1
19449 * Override for PIPE TX de-emphasis
19450 * (OFFSET, MASK, VALUE) (0XFD40C048, 0x000000FFU ,0x00000001U)
19452 PSU_Mask_Write(SERDES_L3_TX_ANA_TM_18_OFFSET,
19453 0x000000FFU, 0x00000001U);
19454 /*##################################################################### */
19459 unsigned long psu_resetout_init_data(void)
19462 * TAKING SERDES PERIPHERAL OUT OF RESET RESET
19465 * PUTTING USB0 IN RESET
19468 * Register : RST_LPD_TOP @ 0XFF5E023C
19470 * USB 0 reset for control registers
19471 * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X0
19473 * Software control register for the LPD block.
19474 * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U)
19476 PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000400U, 0x00000000U);
19477 /*##################################################################### */
19483 * Register : RST_LPD_TOP @ 0XFF5E023C
19485 * USB 0 sleep circuit reset
19486 * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X0
19489 * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X0
19491 * Software control register for the LPD block.
19492 * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000140U ,0x00000000U)
19494 PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000140U, 0x00000000U);
19495 /*##################################################################### */
19498 * PUTTING GEM0 IN RESET
19501 * Register : RST_LPD_IOU0 @ 0XFF5E0230
19504 * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X0
19506 * Software controlled reset for the GEMs
19507 * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U)
19509 PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET,
19510 0x00000008U, 0x00000000U);
19511 /*##################################################################### */
19514 * PUTTING SATA IN RESET
19517 * Register : sata_misc_ctrl @ 0XFD3D0100
19519 * Sata PM clock control select
19520 * PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL 0x3
19522 * Misc Contorls for SATA.This register may only be modified during bootup
19523 * (while SATA block is disabled)
19524 * (OFFSET, MASK, VALUE) (0XFD3D0100, 0x00000003U ,0x00000003U)
19526 PSU_Mask_Write(SIOU_SATA_MISC_CTRL_OFFSET, 0x00000003U, 0x00000003U);
19527 /*##################################################################### */
19530 * Register : RST_FPD_TOP @ 0XFD1A0100
19532 * Sata block level reset
19533 * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X0
19535 * FPD Block level software controlled reset
19536 * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000000U)
19538 PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00000002U, 0x00000000U);
19539 /*##################################################################### */
19542 * PUTTING PCIE CFG AND BRIDGE IN RESET
19545 * Register : RST_FPD_TOP @ 0XFD1A0100
19547 * PCIE config reset
19548 * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X0
19550 * PCIE bridge block level reset (AXI interface)
19551 * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X0
19553 * FPD Block level software controlled reset
19554 * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000C0000U ,0x00000000U)
19556 PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000C0000U, 0x00000000U);
19557 /*##################################################################### */
19560 * PUTTING DP IN RESET
19563 * Register : RST_FPD_TOP @ 0XFD1A0100
19565 * Display Port block level reset (includes DPDMA)
19566 * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X0
19568 * FPD Block level software controlled reset
19569 * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00000000U)
19571 PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00010000U, 0x00000000U);
19572 /*##################################################################### */
19575 * Register : DP_PHY_RESET @ 0XFD4A0200
19577 * Set to '1' to hold the GT in reset. Clear to release.
19578 * PSU_DP_DP_PHY_RESET_GT_RESET 0X0
19580 * Reset the transmitter PHY.
19581 * (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000000U)
19583 PSU_Mask_Write(DP_DP_PHY_RESET_OFFSET, 0x00000002U, 0x00000000U);
19584 /*##################################################################### */
19587 * Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238
19589 * Two bits per lane. When set to 11, moves the GT to power down mode. When
19590 * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] -
19592 * PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0X0
19594 * Control PHY Power down
19595 * (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x00000000U)
19597 PSU_Mask_Write(DP_DP_TX_PHY_POWER_DOWN_OFFSET,
19598 0x0000000FU, 0x00000000U);
19599 /*##################################################################### */
19605 * Register : GUSB2PHYCFG @ 0XFE20C200
19607 * USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY cloc
19608 * ks. Specifies the response time for a MAC request to the Packet FIFO Con
19609 * troller (PFC) to fetch data from the DFIFO (SPRAM). The following are th
19610 * e required values for the minimum SoC bus frequency of 60 MHz. USB turna
19611 * round time is a critical certification criteria when using long cables a
19612 * nd five hub levels. The required values for this field: - 4'h5: When the
19613 * MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
19614 * UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround tim
19615 * e is not critical, this field can be set to a larger value. Note: This f
19616 * ield is valid only in device mode.
19617 * PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0x9
19619 * Transceiver Delay: Enables a delay between the assertion of the UTMI/ULP
19620 * I Transceiver Select signal (for HS) and the assertion of the TxValid si
19621 * gnal during a HS Chirp. When this bit is set to 1, a delay (of approxima
19622 * tely 2.5 us) is introduced from the time when the Transceiver Select is
19623 * set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the
19624 * chirp-K. This delay is required for some UTMI/ULPI PHYs. Note: - If you
19625 * enable the hibernation feature when the device core comes out of power-
19626 * off, you must re-initialize this bit with the appropriate value because
19627 * the core does not save and restore this bit value during hibernation. -
19628 * This bit is valid only in device mode.
19629 * PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0x0
19631 * Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application use
19632 * s this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to th
19633 * e PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assert
19634 * ion from the core is not transferred to the external PHY. - 1'b1: utmi_s
19635 * leep_n and utmi_l1_suspend_n assertion from the core is transferred to t
19636 * he external PHY. Note: This bit must be set high for Port0 if PHY is use
19637 * d. Note: In Device mode - Before issuing any device endpoint command whe
19638 * n operating in 2.0 speeds, disable this bit and enable it after the comm
19639 * and completes. Without disabling this bit, if a command is issued when t
19640 * he device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated of
19641 * f, the command will not get completed.
19642 * PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0x0
19644 * USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select T
19645 * he application uses this bit to select a high-speed PHY or a full-speed
19646 * transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is a
19647 * lways 0, with Write Only access. - 1'b1: USB 1.1 full-speed serial trans
19648 * ceiver. This bit is always 1, with Write Only access. If both interface
19649 * types are selected in coreConsultant (that is, parameters' values are no
19650 * t zero), the application uses this bit to select the active interface is
19651 * active, with Read-Write bit access. Note: USB 1.1 full-serial transceiv
19652 * er is not supported. This bit always reads as 1'b0.
19653 * PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0x0
19655 * Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend
19656 * mode if Suspend conditions are valid. For DRD/OTG configurations, it is
19657 * recommended that this bit is set to 0 during coreConsultant configurati
19658 * on. If it is set to 1, then the application must clear this bit after po
19659 * wer-on reset. Application needs to set it to 1 after the core initializa
19660 * tion completes. For all other configurations, this bit can be set to 1 d
19661 * uring core configuration. Note: - In host mode, on reset, this bit is se
19662 * t to 1. Software can override this bit after reset. - In device mode, be
19663 * fore issuing any device endpoint command when operating in 2.0 speeds, d
19664 * isable this bit and enable it after the command completes. If you issue
19665 * a command without disabling this bit when the device is in L2 state and
19666 * if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get c
19668 * PSU_USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20 0x1
19670 * Full-Speed Serial Interface Select (FSIntf) The application uses this bi
19671 * t to select a unidirectional or bidirectional USB 1.1 full-speed serial
19672 * transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial in
19673 * terface. This bit is set to 0 with Read Only access. - 1'b1: 3-pin bidir
19674 * ectional full-speed serial interface. This bit is set to 0 with Read Onl
19675 * y access. Note: USB 1.1 full-speed serial interface is not supported. Th
19676 * is bit always reads as 1'b0.
19677 * PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0x0
19679 * ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to se
19680 * lect a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Int
19681 * erface This bit is writable only if UTMI+ and ULPI is specified for High
19682 * -Speed PHY Interface(s) in coreConsultant configuration (DWC_USB3_HSPHY_
19683 * INTERFACE = 3). Otherwise, this bit is read-only and the value depends o
19684 * n the interface selected through DWC_USB3_HSPHY_INTERFACE.
19685 * PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0x1
19687 * PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bi
19688 * t to configure the core to support a UTMI+ PHY with an 8- or 16-bit inte
19689 * rface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the en
19690 * abled 2.0 ports must have the same clock frequency as Port0 clock freque
19691 * ncy (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used toge
19692 * ther for different ports at the same time (that is, all the ports must b
19693 * e in 8-bit mode, or all of them must be in 16-bit mode, at a time). - If
19694 * any of the USB 2.0 ports is selected as ULPI port for operation, then a
19695 * ll the USB 2.0 ports must be operating at 60 MHz.
19696 * PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0x0
19698 * HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicat
19699 * ed by the application in this field, is multiplied by a bit-time factor;
19700 * this factor is added to the high-speed/full-speed interpacket timeout d
19701 * uration in the core to account for additional delays introduced by the P
19702 * HY. This may be required, since the delay introduced by the PHY in gener
19703 * ating the linestate condition may vary among PHYs. The USB standard time
19704 * out value for high-speed operation is 736 to 816 (inclusive) bit times.
19705 * The USB standard timeout value for full-speed operation is 16 to 18 (inc
19706 * lusive) bit times. The application must program this field based on the
19707 * speed of connection. The number of bit times added per PHY clock are: Hi
19708 * gh-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz P
19709 * HY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.
19710 * 4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY cloc
19711 * k = 0.25 bit times
19712 * PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0x7
19714 * ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive
19715 * 5V on VBUS, in the ULPI PHY. - 1'b0: PHY drives VBUS with internal char
19716 * ge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Onl
19717 * y when RTL parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3)
19718 * PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV 0x1
19720 * Global USB2 PHY Configuration Register The application must program this
19721 * register before starting any transactions on either the SoC bus or the
19722 * USB. In Device-only configurations, only one register is needed. In Host
19723 * mode, per-port registers are implemented.
19724 * (OFFSET, MASK, VALUE) (0XFE20C200, 0x00023FFFU ,0x00022457U)
19726 PSU_Mask_Write(USB3_0_XHCI_GUSB2PHYCFG_OFFSET,
19727 0x00023FFFU, 0x00022457U);
19728 /*##################################################################### */
19731 * Register : GFLADJ @ 0XFE20C630
19733 * This field indicates the frame length adjustment to be applied when SOF/
19734 * ITP counter is running on the ref_clk. This register value is used to ad
19735 * just the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP i
19736 * nterval when GLADJ.GFLADJ_REFCLK_LPM_SEL is set to '1'. This field must
19737 * be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set t
19738 * o '1' or GCTL.SOFITPSYNC is set to '1'. The value is derived as follows:
19739 * FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_pe
19740 * riod)) * ref_clk_period where - the ref_clk_period_integer is the intege
19741 * r value of the ref_clk period got by truncating the decimal (fractional)
19742 * value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_c
19743 * lk_period is the ref_clk period including the fractional value. Examples
19744 * : If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLA
19745 * DJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignorin
19746 * g the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_PE
19747 * RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*2
19748 * 0.8333 = 5208 (ignoring the fractional value)
19749 * PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0x0
19751 * Global Frame Length Adjustment Register This register provides options f
19752 * or the software to control the core behavior with respect to SOF (Start
19753 * of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer
19754 * functionality. It provides an option to override the fladj_30mhz_reg sid
19755 * eband signal. In addition, it enables running SOF or ITP frame timer cou
19756 * nters completely from the ref_clk. This facilitates hardware LPM in host
19757 * mode with the SOF or ITP counters being run from the ref_clk signal.
19758 * (OFFSET, MASK, VALUE) (0XFE20C630, 0x003FFF00U ,0x00000000U)
19760 PSU_Mask_Write(USB3_0_XHCI_GFLADJ_OFFSET, 0x003FFF00U, 0x00000000U);
19761 /*##################################################################### */
19764 * Register : GUCTL1 @ 0XFE20C11C
19766 * When this bit is set to '0', termsel, xcvrsel will become 0 during end o
19767 * f resume while the opmode will become 0 once controller completes end of
19768 * resume and enters U0 state (2 separate commandswill be issued). When th
19769 * is bit is set to '1', all the termsel, xcvrsel, opmode becomes 0 during
19770 * end of resume itself (only 1 command will be issued)
19771 * PSU_USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY 0x1
19774 * PSU_USB3_0_XHCI_GUCTL1_RESERVED_9 0x1
19776 * Global User Control Register 1
19777 * (OFFSET, MASK, VALUE) (0XFE20C11C, 0x00000600U ,0x00000600U)
19779 PSU_Mask_Write(USB3_0_XHCI_GUCTL1_OFFSET, 0x00000600U, 0x00000600U);
19780 /*##################################################################### */
19783 * Register : GUCTL @ 0XFE20C12C
19785 * Host IN Auto Retry (USBHstInAutoRetryEn) When set, this field enables th
19786 * e Auto Retry feature. For IN transfers (non-isochronous) that encounter
19787 * data packets with CRC errors or internal overrun scenarios, the auto ret
19788 * ry feature causes the Host core to reply to the device with a non-termin
19789 * ating retry ACK (that is, an ACK transaction packet with Retry = 1 and N
19790 * umP != 0). If the Auto Retry feature is disabled (default), the core wil
19791 * l respond with a terminating retry ACK (that is, an ACK transaction pack
19792 * et with Retry = 1 and NumP = 0). - 1'b0: Auto Retry Disabled - 1'b1: Aut
19793 * o Retry Enabled Note: This bit is also applicable to the device mode.
19794 * PSU_USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN 0x1
19796 * Global User Control Register: This register provides a few options for t
19797 * he software to control the core behavior in the Host mode. Most of the o
19798 * ptions are used to improve host inter-operability with different devices
19800 * (OFFSET, MASK, VALUE) (0XFE20C12C, 0x00004000U ,0x00004000U)
19802 PSU_Mask_Write(USB3_0_XHCI_GUCTL_OFFSET, 0x00004000U, 0x00004000U);
19803 /*##################################################################### */
19806 * UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCO
19807 * RRECT RESET VALUES IN SILICON.
19810 * Register : ATTR_25 @ 0XFD480064
19812 * If TRUE Completion Timeout Disable is supported. This is required to be
19813 * TRUE for Endpoint and either setting allowed for Root ports. Drives Devi
19814 * ce Capability 2 [4]; EP=0x0001; RP=0x0001
19815 * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED 0X1
19818 * (OFFSET, MASK, VALUE) (0XFD480064, 0x00000200U ,0x00000200U)
19820 PSU_Mask_Write(PCIE_ATTRIB_ATTR_25_OFFSET, 0x00000200U, 0x00000200U);
19821 /*##################################################################### */
19827 * Register : ATTR_7 @ 0XFD48001C
19829 * Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not
19830 * to be implemented, set to 32'h00000000. Bits are defined as follows: Me
19831 * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (
19832 * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask
19833 * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w
19834 * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:
19835 * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator (
19836 * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B
19837 * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.;
19838 * EP=0x0004; RP=0x0000
19839 * PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0 0x0
19842 * (OFFSET, MASK, VALUE) (0XFD48001C, 0x0000FFFFU ,0x00000000U)
19844 PSU_Mask_Write(PCIE_ATTRIB_ATTR_7_OFFSET, 0x0000FFFFU, 0x00000000U);
19845 /*##################################################################### */
19848 * Register : ATTR_8 @ 0XFD480020
19850 * Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not
19851 * to be implemented, set to 32'h00000000. Bits are defined as follows: Me
19852 * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (
19853 * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask
19854 * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w
19855 * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:
19856 * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator (
19857 * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B
19858 * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.;
19859 * EP=0xFFF0; RP=0x0000
19860 * PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0 0x0
19863 * (OFFSET, MASK, VALUE) (0XFD480020, 0x0000FFFFU ,0x00000000U)
19865 PSU_Mask_Write(PCIE_ATTRIB_ATTR_8_OFFSET, 0x0000FFFFU, 0x00000000U);
19866 /*##################################################################### */
19869 * Register : ATTR_9 @ 0XFD480024
19871 * Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3
19872 * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA
19873 * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri
19874 * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi
19875 * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac
19876 * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit)
19877 * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
19878 * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size
19879 * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t
19880 * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set
19881 * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t
19882 * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
19883 * PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1 0x0
19886 * (OFFSET, MASK, VALUE) (0XFD480024, 0x0000FFFFU ,0x00000000U)
19888 PSU_Mask_Write(PCIE_ATTRIB_ATTR_9_OFFSET, 0x0000FFFFU, 0x00000000U);
19889 /*##################################################################### */
19892 * Register : ATTR_10 @ 0XFD480028
19894 * Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3
19895 * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA
19896 * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri
19897 * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi
19898 * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac
19899 * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit)
19900 * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
19901 * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size
19902 * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t
19903 * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set
19904 * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t
19905 * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
19906 * PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1 0x0
19909 * (OFFSET, MASK, VALUE) (0XFD480028, 0x0000FFFFU ,0x00000000U)
19911 PSU_Mask_Write(PCIE_ATTRIB_ATTR_10_OFFSET, 0x0000FFFFU, 0x00000000U);
19912 /*##################################################################### */
19915 * Register : ATTR_11 @ 0XFD48002C
19917 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
19918 * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA
19919 * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
19920 * et to 32'h00000000. See BAR1 description if this functions as the upper
19921 * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF
19922 * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u
19923 * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie
19924 * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M
19925 * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to
19926 * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost
19927 * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat
19928 * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits
19929 * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt
19930 * es.; EP=0x0004; RP=0xFFFF
19931 * PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2 0xFFFF
19934 * (OFFSET, MASK, VALUE) (0XFD48002C, 0x0000FFFFU ,0x0000FFFFU)
19936 PSU_Mask_Write(PCIE_ATTRIB_ATTR_11_OFFSET, 0x0000FFFFU, 0x0000FFFFU);
19937 /*##################################################################### */
19940 * Register : ATTR_12 @ 0XFD480030
19942 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
19943 * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA
19944 * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
19945 * et to 32'h00000000. See BAR1 description if this functions as the upper
19946 * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF
19947 * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u
19948 * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie
19949 * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M
19950 * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to
19951 * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost
19952 * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat
19953 * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits
19954 * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt
19955 * es.; EP=0xFFF0; RP=0x00FF
19956 * PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2 0xFF
19959 * (OFFSET, MASK, VALUE) (0XFD480030, 0x0000FFFFU ,0x000000FFU)
19961 PSU_Mask_Write(PCIE_ATTRIB_ATTR_12_OFFSET, 0x0000FFFFU, 0x000000FFU);
19962 /*##################################################################### */
19965 * Register : ATTR_13 @ 0XFD480034
19967 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
19968 * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA
19969 * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
19970 * et to 32'h00000000. See BAR2 description if this functions as the upper
19971 * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00
19972 * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R
19973 * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi
19974 * t decode For an endpoint, bits are defined as follows: Memory Space BAR
19975 * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty
19976 * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:
19977 * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi
19978 * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp
19979 * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I
19980 * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable
19981 * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size
19982 * in bytes.; EP=0xFFFF; RP=0x0000
19983 * PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3 0x0
19986 * (OFFSET, MASK, VALUE) (0XFD480034, 0x0000FFFFU ,0x00000000U)
19988 PSU_Mask_Write(PCIE_ATTRIB_ATTR_13_OFFSET, 0x0000FFFFU, 0x00000000U);
19989 /*##################################################################### */
19992 * Register : ATTR_14 @ 0XFD480038
19994 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
19995 * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA
19996 * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
19997 * et to 32'h00000000. See BAR2 description if this functions as the upper
19998 * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00
19999 * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R
20000 * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi
20001 * t decode For an endpoint, bits are defined as follows: Memory Space BAR
20002 * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty
20003 * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:
20004 * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi
20005 * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp
20006 * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I
20007 * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable
20008 * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size
20009 * in bytes.; EP=0xFFFF; RP=0xFFFF
20010 * PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3 0xFFFF
20013 * (OFFSET, MASK, VALUE) (0XFD480038, 0x0000FFFFU ,0x0000FFFFU)
20015 PSU_Mask_Write(PCIE_ATTRIB_ATTR_14_OFFSET, 0x0000FFFFU, 0x0000FFFFU);
20016 /*##################################################################### */
20019 * Register : ATTR_15 @ 0XFD48003C
20021 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
20022 * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA
20023 * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
20024 * et to 32'h00000000. See BAR3 description if this functions as the upper
20025 * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF
20026 * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u
20027 * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie
20028 * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M
20029 * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to
20030 * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost
20031 * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat
20032 * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits
20033 * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt
20034 * es.; EP=0x0004; RP=0xFFF0
20035 * PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4 0xFFF0
20038 * (OFFSET, MASK, VALUE) (0XFD48003C, 0x0000FFFFU ,0x0000FFF0U)
20040 PSU_Mask_Write(PCIE_ATTRIB_ATTR_15_OFFSET, 0x0000FFFFU, 0x0000FFF0U);
20041 /*##################################################################### */
20044 * Register : ATTR_16 @ 0XFD480040
20046 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
20047 * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA
20048 * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
20049 * et to 32'h00000000. See BAR3 description if this functions as the upper
20050 * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF
20051 * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u
20052 * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie
20053 * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M
20054 * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to
20055 * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost
20056 * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat
20057 * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits
20058 * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt
20059 * es.; EP=0xFFF0; RP=0xFFF0
20060 * PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4 0xFFF0
20063 * (OFFSET, MASK, VALUE) (0XFD480040, 0x0000FFFFU ,0x0000FFF0U)
20065 PSU_Mask_Write(PCIE_ATTRIB_ATTR_16_OFFSET, 0x0000FFFFU, 0x0000FFF0U);
20066 /*##################################################################### */
20069 * Register : ATTR_17 @ 0XFD480044
20071 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
20072 * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA
20073 * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
20074 * et to 32'h00000000. See BAR4 description if this functions as the upper
20075 * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00
20076 * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0
20077 * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P
20078 * refetchable Memory Limit/Base implemented For an endpoint, bits are defi
20079 * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac
20080 * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be
20081 * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f
20082 * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory
20083 * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1)
20084 * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up
20085 * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF
20087 * PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5 0xFFF1
20090 * (OFFSET, MASK, VALUE) (0XFD480044, 0x0000FFFFU ,0x0000FFF1U)
20092 PSU_Mask_Write(PCIE_ATTRIB_ATTR_17_OFFSET, 0x0000FFFFU, 0x0000FFF1U);
20093 /*##################################################################### */
20096 * Register : ATTR_18 @ 0XFD480048
20098 * For an endpoint, specifies mask/settings for Base Address Register (BAR)
20099 * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA
20100 * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
20101 * et to 32'h00000000. See BAR4 description if this functions as the upper
20102 * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00
20103 * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0
20104 * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P
20105 * refetchable Memory Limit/Base implemented For an endpoint, bits are defi
20106 * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac
20107 * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be
20108 * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f
20109 * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory
20110 * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1)
20111 * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up
20112 * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF
20114 * PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5 0xFFF1
20117 * (OFFSET, MASK, VALUE) (0XFD480048, 0x0000FFFFU ,0x0000FFF1U)
20119 PSU_Mask_Write(PCIE_ATTRIB_ATTR_18_OFFSET, 0x0000FFFFU, 0x0000FFF1U);
20120 /*##################################################################### */
20123 * Register : ATTR_27 @ 0XFD48006C
20125 * Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1
20126 * - 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred to the Device Capa
20127 * bilities register. The values: 4-2048 bytes, 5- 4096 bytes are not suppo
20128 * rted; EP=0x0001; RP=0x0001
20129 * PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED 1
20131 * Endpoint L1 Acceptable Latency. Records the latency that the endpoint ca
20132 * n withstand on transitions from L1 state to L0 (if L1 state supported).
20133 * Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to
20134 * 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For
20135 * Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000
20136 * PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY 0x0
20139 * (OFFSET, MASK, VALUE) (0XFD48006C, 0x00000738U ,0x00000100U)
20141 PSU_Mask_Write(PCIE_ATTRIB_ATTR_27_OFFSET, 0x00000738U, 0x00000100U);
20142 /*##################################################################### */
20145 * Register : ATTR_50 @ 0XFD4800C8
20147 * Identifies the type of device/port as follows: 0000b PCI Express Endpoin
20148 * t device, 0001b Legacy PCI Express Endpoint device, 0100b Root Port of P
20149 * CI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110
20150 * b Downstream Port of PCI Express Switch, 0111b PCIE Express to PCI/PCI-X
20151 * Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Expre
20152 * ss Capabilities register. Must be consistent with IS_SWITCH and UPSTREAM
20153 * _FACING settings.; EP=0x0000; RP=0x0004
20154 * PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE 4
20156 * PCIe Capability's Next Capability Offset pointer to the next item in the
20157 * capabilities list, or 00h if this is the final capability.; EP=0x009C;
20159 * PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR 0
20162 * (OFFSET, MASK, VALUE) (0XFD4800C8, 0x0000FFF0U ,0x00000040U)
20164 PSU_Mask_Write(PCIE_ATTRIB_ATTR_50_OFFSET, 0x0000FFF0U, 0x00000040U);
20165 /*##################################################################### */
20168 * Register : ATTR_105 @ 0XFD4801A4
20170 * Number of credits that should be advertised for Completion data received
20171 * on Virtual Channel 0. The bytes advertised must be less than or equal t
20172 * o the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD
20173 * PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD 0xCD
20176 * (OFFSET, MASK, VALUE) (0XFD4801A4, 0x000007FFU ,0x000000CDU)
20178 PSU_Mask_Write(PCIE_ATTRIB_ATTR_105_OFFSET,
20179 0x000007FFU, 0x000000CDU);
20180 /*##################################################################### */
20183 * Register : ATTR_106 @ 0XFD4801A8
20185 * Number of credits that should be advertised for Completion headers recei
20186 * ved on Virtual Channel 0. The sum of the posted, non posted, and complet
20187 * ion header credits must be <= 80; EP=0x0048; RP=0x0024
20188 * PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH 0x24
20190 * Number of credits that should be advertised for Non-Posted headers recei
20191 * ved on Virtual Channel 0. The number of non posted data credits advertis
20192 * ed by the block is equal to the number of non posted header credits. The
20193 * sum of the posted, non posted, and completion header credits must be <=
20194 * 80; EP=0x0004; RP=0x000C
20195 * PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH 0xC
20198 * (OFFSET, MASK, VALUE) (0XFD4801A8, 0x00003FFFU ,0x00000624U)
20200 PSU_Mask_Write(PCIE_ATTRIB_ATTR_106_OFFSET,
20201 0x00003FFFU, 0x00000624U);
20202 /*##################################################################### */
20205 * Register : ATTR_107 @ 0XFD4801AC
20207 * Number of credits that should be advertised for Non-Posted data received
20208 * on Virtual Channel 0. The number of non posted data credits advertised
20209 * by the block is equal to two times the number of non posted header credi
20210 * ts if atomic operations are supported or is equal to the number of non p
20211 * osted header credits if atomic operations are not supported. The bytes a
20212 * dvertised must be less than or equal to the bram bytes available. See VC
20213 * 0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018
20214 * PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD 0x18
20217 * (OFFSET, MASK, VALUE) (0XFD4801AC, 0x000007FFU ,0x00000018U)
20219 PSU_Mask_Write(PCIE_ATTRIB_ATTR_107_OFFSET,
20220 0x000007FFU, 0x00000018U);
20221 /*##################################################################### */
20224 * Register : ATTR_108 @ 0XFD4801B0
20226 * Number of credits that should be advertised for Posted data received on
20227 * Virtual Channel 0. The bytes advertised must be less than or equal to th
20228 * e bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5
20229 * PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD 0xB5
20232 * (OFFSET, MASK, VALUE) (0XFD4801B0, 0x000007FFU ,0x000000B5U)
20234 PSU_Mask_Write(PCIE_ATTRIB_ATTR_108_OFFSET,
20235 0x000007FFU, 0x000000B5U);
20236 /*##################################################################### */
20239 * Register : ATTR_109 @ 0XFD4801B4
20241 * Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_
20242 * n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x0000
20243 * PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV 0x0
20245 * Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim
20246 * TRUE == trim.; EP=0x0001; RP=0x0001
20247 * PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM 0x1
20249 * Enables ECRC check on received TLP's 0 == don't check 1 == always check
20250 * 3 == check if enabled by ECRC check enable bit of AER cap structure; EP=
20251 * 0x0003; RP=0x0003
20252 * PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK 0x3
20254 * Index of last packet buffer used by TX TLM (i.e. number of buffers - 1).
20255 * Calculated from max payload size supported and the number of brams conf
20256 * igured for transmit; EP=0x001C; RP=0x001C
20257 * PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET 0x1c
20259 * Number of credits that should be advertised for Posted headers received
20260 * on Virtual Channel 0. The sum of the posted, non posted, and completion
20261 * header credits must be <= 80; EP=0x0004; RP=0x0020
20262 * PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH 0x20
20265 * (OFFSET, MASK, VALUE) (0XFD4801B4, 0x0000FFFFU ,0x00007E20U)
20267 PSU_Mask_Write(PCIE_ATTRIB_ATTR_109_OFFSET,
20268 0x0000FFFFU, 0x00007E20U);
20269 /*##################################################################### */
20272 * Register : ATTR_34 @ 0XFD480088
20274 * Specifies values to be transferred to Header Type register. Bit 7 should
20275 * be set to '0' indicating single-function device. Bit 0 identifies heade
20276 * r as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000;
20278 * PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE 0x1
20281 * (OFFSET, MASK, VALUE) (0XFD480088, 0x000000FFU ,0x00000001U)
20283 PSU_Mask_Write(PCIE_ATTRIB_ATTR_34_OFFSET, 0x000000FFU, 0x00000001U);
20284 /*##################################################################### */
20287 * Register : ATTR_53 @ 0XFD4800D4
20289 * PM Capability's Next Capability Offset pointer to the next item in the c
20290 * apabilities list, or 00h if this is the final capability.; EP=0x0048; RP
20292 * PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR 0x60
20295 * (OFFSET, MASK, VALUE) (0XFD4800D4, 0x000000FFU ,0x00000060U)
20297 PSU_Mask_Write(PCIE_ATTRIB_ATTR_53_OFFSET, 0x000000FFU, 0x00000060U);
20298 /*##################################################################### */
20301 * Register : ATTR_41 @ 0XFD4800A4
20303 * MSI Per-Vector Masking Capable. The value is transferred to the MSI Cont
20304 * rol Register[8]. When set, adds Mask and Pending Dword to Cap structure;
20305 * EP=0x0000; RP=0x0000
20306 * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE 0x0
20308 * Indicates that the MSI structures exists. If this is FALSE, then the MSI
20309 * structure cannot be accessed via either the link or the management port
20310 * .; EP=0x0001; RP=0x0000
20311 * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0
20313 * MSI Capability's Next Capability Offset pointer to the next item in the
20314 * capabilities list, or 00h if this is the final capability.; EP=0x0060; R
20316 * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR 0x0
20318 * Indicates that the MSI structures exists. If this is FALSE, then the MSI
20319 * structure cannot be accessed via either the link or the management port
20320 * .; EP=0x0001; RP=0x0000
20321 * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0
20324 * (OFFSET, MASK, VALUE) (0XFD4800A4, 0x000003FFU ,0x00000000U)
20326 PSU_Mask_Write(PCIE_ATTRIB_ATTR_41_OFFSET, 0x000003FFU, 0x00000000U);
20327 /*##################################################################### */
20330 * Register : ATTR_97 @ 0XFD480184
20332 * Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b
20333 * x4, 001000b x8.; EP=0x0004; RP=0x0004
20334 * PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH 0x1
20336 * Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1
20337 * ], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x0004; RP=0x0004
20338 * PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH 0x1
20341 * (OFFSET, MASK, VALUE) (0XFD480184, 0x00000FFFU ,0x00000041U)
20343 PSU_Mask_Write(PCIE_ATTRIB_ATTR_97_OFFSET, 0x00000FFFU, 0x00000041U);
20344 /*##################################################################### */
20347 * Register : ATTR_100 @ 0XFD480190
20349 * TRUE specifies upstream-facing port. FALSE specifies downstream-facing p
20350 * ort.; EP=0x0001; RP=0x0000
20351 * PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING 0x0
20354 * (OFFSET, MASK, VALUE) (0XFD480190, 0x00000040U ,0x00000000U)
20356 PSU_Mask_Write(PCIE_ATTRIB_ATTR_100_OFFSET,
20357 0x00000040U, 0x00000000U);
20358 /*##################################################################### */
20361 * Register : ATTR_101 @ 0XFD480194
20363 * Enable the routing of message TLPs to the user through the TRN RX interf
20364 * ace. A bit value of 1 enables routing of the message TLP to the user. Me
20365 * ssages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1
20366 * - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - I
20367 * NTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit
20368 * 10 PME_Turn_Off; EP=0x0000; RP=0x07FF
20369 * PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE 0x7FF
20371 * Disable BAR filtering. Does not change the behavior of the bar hit outpu
20372 * ts; EP=0x0000; RP=0x0001
20373 * PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING 0x1
20376 * (OFFSET, MASK, VALUE) (0XFD480194, 0x0000FFE2U ,0x0000FFE2U)
20378 PSU_Mask_Write(PCIE_ATTRIB_ATTR_101_OFFSET,
20379 0x0000FFE2U, 0x0000FFE2U);
20380 /*##################################################################### */
20383 * Register : ATTR_37 @ 0XFD480094
20385 * Link Bandwidth notification capability. Indicates support for the link b
20386 * andwidth notification status and interrupt mechanism. Required for Root.
20387 * ; EP=0x0000; RP=0x0001
20388 * PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 0x1
20390 * Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Op
20391 * tionality ECN. Transferred to the Link Capabilities register.; EP=0x0001
20393 * PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0x1
20396 * (OFFSET, MASK, VALUE) (0XFD480094, 0x00004200U ,0x00004200U)
20398 PSU_Mask_Write(PCIE_ATTRIB_ATTR_37_OFFSET, 0x00004200U, 0x00004200U);
20399 /*##################################################################### */
20402 * Register : ATTR_93 @ 0XFD480174
20404 * Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value
20405 * (or combined with the built-in value, depending on LL_REPLAY_TIMEOUT_FU
20406 * NC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000
20407 * PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN 0x1
20409 * Sets a user-defined timeout for the Replay Timer to force cause the retr
20410 * ansmission of unacknowledged TLPs; refer to LL_REPLAY_TIMEOUT_EN and LL_
20411 * REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this att
20412 * ribute is in symbol times, which is 4ns at GEN1 speeds and 2ns at GEN2.;
20413 * EP=0x0000; RP=0x0000
20414 * PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT 0x1000
20417 * (OFFSET, MASK, VALUE) (0XFD480174, 0x0000FFFFU ,0x00009000U)
20419 PSU_Mask_Write(PCIE_ATTRIB_ATTR_93_OFFSET, 0x0000FFFFU, 0x00009000U);
20420 /*##################################################################### */
20423 * Register : ID @ 0XFD480200
20425 * Device ID for the the PCIe Cap Structure Device ID field
20426 * PSU_PCIE_ATTRIB_ID_CFG_DEV_ID 0xd021
20428 * Vendor ID for the PCIe Cap Structure Vendor ID field
20429 * PSU_PCIE_ATTRIB_ID_CFG_VEND_ID 0x10ee
20432 * (OFFSET, MASK, VALUE) (0XFD480200, 0xFFFFFFFFU ,0x10EED021U)
20434 PSU_Mask_Write(PCIE_ATTRIB_ID_OFFSET, 0xFFFFFFFFU, 0x10EED021U);
20435 /*##################################################################### */
20438 * Register : SUBSYS_ID @ 0XFD480204
20440 * Subsystem ID for the the PCIe Cap Structure Subsystem ID field
20441 * PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID 0x7
20443 * Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field
20444 * PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID 0x10ee
20447 * (OFFSET, MASK, VALUE) (0XFD480204, 0xFFFFFFFFU ,0x10EE0007U)
20449 PSU_Mask_Write(PCIE_ATTRIB_SUBSYS_ID_OFFSET,
20450 0xFFFFFFFFU, 0x10EE0007U);
20451 /*##################################################################### */
20454 * Register : REV_ID @ 0XFD480208
20456 * Revision ID for the the PCIe Cap Structure
20457 * PSU_PCIE_ATTRIB_REV_ID_CFG_REV_ID 0x0
20460 * (OFFSET, MASK, VALUE) (0XFD480208, 0x000000FFU ,0x00000000U)
20462 PSU_Mask_Write(PCIE_ATTRIB_REV_ID_OFFSET, 0x000000FFU, 0x00000000U);
20463 /*##################################################################### */
20466 * Register : ATTR_24 @ 0XFD480060
20468 * Code identifying basic function, subclass and applicable programming int
20469 * erface. Transferred to the Class Code register.; EP=0x8000; RP=0x8000
20470 * PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE 0x400
20473 * (OFFSET, MASK, VALUE) (0XFD480060, 0x0000FFFFU ,0x00000400U)
20475 PSU_Mask_Write(PCIE_ATTRIB_ATTR_24_OFFSET, 0x0000FFFFU, 0x00000400U);
20476 /*##################################################################### */
20479 * Register : ATTR_25 @ 0XFD480064
20481 * Code identifying basic function, subclass and applicable programming int
20482 * erface. Transferred to the Class Code register.; EP=0x0005; RP=0x0006
20483 * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE 0x6
20485 * INTX Interrupt Generation Capable. If FALSE, this will cause Command[10]
20486 * to be hardwired to 0.; EP=0x0001; RP=0x0001
20487 * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED 0
20490 * (OFFSET, MASK, VALUE) (0XFD480064, 0x000001FFU ,0x00000006U)
20492 PSU_Mask_Write(PCIE_ATTRIB_ATTR_25_OFFSET, 0x000001FFU, 0x00000006U);
20493 /*##################################################################### */
20496 * Register : ATTR_4 @ 0XFD480010
20498 * Indicates that the AER structures exists. If this is FALSE, then the AER
20499 * structure cannot be accessed via either the link or the management port
20500 * , and AER will be considered to not be present for error management task
20501 * s (such as what types of error messages are sent if an error is detected
20502 * ).; EP=0x0001; RP=0x0001
20503 * PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0
20505 * Indicates that the AER structures exists. If this is FALSE, then the AER
20506 * structure cannot be accessed via either the link or the management port
20507 * , and AER will be considered to not be present for error management task
20508 * s (such as what types of error messages are sent if an error is detected
20509 * ).; EP=0x0001; RP=0x0001
20510 * PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0
20513 * (OFFSET, MASK, VALUE) (0XFD480010, 0x00001000U ,0x00000000U)
20515 PSU_Mask_Write(PCIE_ATTRIB_ATTR_4_OFFSET, 0x00001000U, 0x00000000U);
20516 /*##################################################################### */
20519 * Register : ATTR_89 @ 0XFD480164
20521 * VSEC's Next Capability Offset pointer to the next item in the capabiliti
20522 * es list, or 000h if this is the final capability.; EP=0x0140; RP=0x0140
20523 * PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR 0
20526 * (OFFSET, MASK, VALUE) (0XFD480164, 0x00001FFEU ,0x00000000U)
20528 PSU_Mask_Write(PCIE_ATTRIB_ATTR_89_OFFSET, 0x00001FFEU, 0x00000000U);
20529 /*##################################################################### */
20532 * Register : ATTR_79 @ 0XFD48013C
20534 * CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the
20535 * Root Capabilities register.; EP=0x0000; RP=0x0000
20536 * PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY 1
20539 * (OFFSET, MASK, VALUE) (0XFD48013C, 0x00000020U ,0x00000020U)
20541 PSU_Mask_Write(PCIE_ATTRIB_ATTR_79_OFFSET, 0x00000020U, 0x00000020U);
20542 /*##################################################################### */
20545 * Register : ATTR_43 @ 0XFD4800AC
20547 * Indicates that the MSIX structures exists. If this is FALSE, then the MS
20548 * IX structure cannot be accessed via either the link or the management po
20549 * rt.; EP=0x0001; RP=0x0000
20550 * PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON 0
20553 * (OFFSET, MASK, VALUE) (0XFD4800AC, 0x00000100U ,0x00000000U)
20555 PSU_Mask_Write(PCIE_ATTRIB_ATTR_43_OFFSET, 0x00000100U, 0x00000000U);
20556 /*##################################################################### */
20559 * Register : ATTR_48 @ 0XFD4800C0
20561 * MSI-X Table Size. This value is transferred to the MSI-X Message Control
20562 * [10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does
20563 * not implement the table; that must be implemented in user logic.; EP=0x0
20565 * PSU_PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE 0
20568 * (OFFSET, MASK, VALUE) (0XFD4800C0, 0x000007FFU ,0x00000000U)
20570 PSU_Mask_Write(PCIE_ATTRIB_ATTR_48_OFFSET, 0x000007FFU, 0x00000000U);
20571 /*##################################################################### */
20574 * Register : ATTR_46 @ 0XFD4800B8
20576 * MSI-X Table Offset. This value is transferred to the MSI-X Table Offset
20577 * field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000
20578 * PSU_PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET 0
20581 * (OFFSET, MASK, VALUE) (0XFD4800B8, 0x0000FFFFU ,0x00000000U)
20583 PSU_Mask_Write(PCIE_ATTRIB_ATTR_46_OFFSET, 0x0000FFFFU, 0x00000000U);
20584 /*##################################################################### */
20587 * Register : ATTR_47 @ 0XFD4800BC
20589 * MSI-X Table Offset. This value is transferred to the MSI-X Table Offset
20590 * field. Set to 0 if MSI-X is not enabled.; EP=0x0000; RP=0x0000
20591 * PSU_PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET 0
20594 * (OFFSET, MASK, VALUE) (0XFD4800BC, 0x00001FFFU ,0x00000000U)
20596 PSU_Mask_Write(PCIE_ATTRIB_ATTR_47_OFFSET, 0x00001FFFU, 0x00000000U);
20597 /*##################################################################### */
20600 * Register : ATTR_44 @ 0XFD4800B0
20602 * MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB
20603 * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000
20604 * PSU_PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET 0
20607 * (OFFSET, MASK, VALUE) (0XFD4800B0, 0x0000FFFFU ,0x00000000U)
20609 PSU_Mask_Write(PCIE_ATTRIB_ATTR_44_OFFSET, 0x0000FFFFU, 0x00000000U);
20610 /*##################################################################### */
20613 * Register : ATTR_45 @ 0XFD4800B4
20615 * MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB
20616 * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x1000; RP=0x0000
20617 * PSU_PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET 0
20620 * (OFFSET, MASK, VALUE) (0XFD4800B4, 0x0000FFF8U ,0x00000000U)
20622 PSU_Mask_Write(PCIE_ATTRIB_ATTR_45_OFFSET, 0x0000FFF8U, 0x00000000U);
20623 /*##################################################################### */
20626 * Register : CB @ 0XFD48031C
20629 * PSU_PCIE_ATTRIB_CB_CB1 0x0
20632 * (OFFSET, MASK, VALUE) (0XFD48031C, 0x00000002U ,0x00000000U)
20634 PSU_Mask_Write(PCIE_ATTRIB_CB_OFFSET, 0x00000002U, 0x00000000U);
20635 /*##################################################################### */
20638 * Register : ATTR_35 @ 0XFD48008C
20640 * Active State PM Support. Indicates the level of active state power manag
20641 * ement supported by the selected PCI Express Link, encoded as follows: 0
20642 * Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supporte
20643 * d.; EP=0x0001; RP=0x0001
20644 * PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT 0x0
20647 * (OFFSET, MASK, VALUE) (0XFD48008C, 0x00003000U ,0x00000000U)
20649 PSU_Mask_Write(PCIE_ATTRIB_ATTR_35_OFFSET, 0x00003000U, 0x00000000U);
20650 /*##################################################################### */
20653 * PUTTING PCIE CONTROL IN RESET
20656 * Register : RST_FPD_TOP @ 0XFD1A0100
20658 * PCIE control block level reset
20659 * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0
20661 * FPD Block level software controlled reset
20662 * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00020000U ,0x00000000U)
20664 PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00020000U, 0x00000000U);
20665 /*##################################################################### */
20671 * MASK_DATA_0_LSW LOW BANK [15:0]
20674 * MASK_DATA_0_MSW LOW BANK [25:16]
20677 * MASK_DATA_1_LSW LOW BANK [41:26]
20680 * Register : MASK_DATA_1_LSW @ 0XFF0A0008
20682 * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
20683 * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf
20685 * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]
20686 * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20
20688 * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)
20689 * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U)
20691 PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET,
20692 0xFFFFFFFFU, 0xFFDF0020U);
20693 /*##################################################################### */
20696 * MASK_DATA_1_MSW HIGH BANK [51:42]
20699 * MASK_DATA_1_LSW HIGH BANK [67:52]
20702 * MASK_DATA_1_LSW HIGH BANK [77:68]
20705 * CHECK PLL LOCK FOR LANE0
20708 * Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4
20710 * Status Read value of PLL Lock
20711 * PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
20712 * (OFFSET, MASK, VALUE) (0XFD4023E4, 0x00000010U ,0x00000010U)
20714 mask_poll(SERDES_L0_PLL_STATUS_READ_1_OFFSET, 0x00000010U);
20716 /*##################################################################### */
20719 * CHECK PLL LOCK FOR LANE1
20722 * Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4
20724 * Status Read value of PLL Lock
20725 * PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
20726 * (OFFSET, MASK, VALUE) (0XFD4063E4, 0x00000010U ,0x00000010U)
20728 mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET, 0x00000010U);
20730 /*##################################################################### */
20733 * CHECK PLL LOCK FOR LANE2
20736 * Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4
20738 * Status Read value of PLL Lock
20739 * PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
20740 * (OFFSET, MASK, VALUE) (0XFD40A3E4, 0x00000010U ,0x00000010U)
20742 mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET, 0x00000010U);
20744 /*##################################################################### */
20747 * CHECK PLL LOCK FOR LANE3
20750 * Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4
20752 * Status Read value of PLL Lock
20753 * PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
20754 * (OFFSET, MASK, VALUE) (0XFD40E3E4, 0x00000010U ,0x00000010U)
20756 mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET, 0x00000010U);
20758 /*##################################################################### */
20761 * SATA AHCI VENDOR SETTING
20764 * Register : PP2C @ 0XFD0C00AC
20766 * CIBGMN: COMINIT Burst Gap Minimum.
20767 * PSU_SATA_AHCI_VENDOR_PP2C_CIBGMN 0x18
20769 * CIBGMX: COMINIT Burst Gap Maximum.
20770 * PSU_SATA_AHCI_VENDOR_PP2C_CIBGMX 0x40
20772 * CIBGN: COMINIT Burst Gap Nominal.
20773 * PSU_SATA_AHCI_VENDOR_PP2C_CIBGN 0x18
20775 * CINMP: COMINIT Negate Minimum Period.
20776 * PSU_SATA_AHCI_VENDOR_PP2C_CINMP 0x28
20778 * PP2C - Port Phy2Cfg Register. This register controls the configuration o
20779 * f the Phy Control OOB timing for the COMINIT parameters for either Port
20780 * 0 or Port 1. The Port configured is controlled by the value programmed i
20781 * nto the Port Config Register.
20782 * (OFFSET, MASK, VALUE) (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U)
20784 PSU_Mask_Write(SATA_AHCI_VENDOR_PP2C_OFFSET,
20785 0xFFFFFFFFU, 0x28184018U);
20786 /*##################################################################### */
20789 * Register : PP3C @ 0XFD0C00B0
20791 * CWBGMN: COMWAKE Burst Gap Minimum.
20792 * PSU_SATA_AHCI_VENDOR_PP3C_CWBGMN 0x06
20794 * CWBGMX: COMWAKE Burst Gap Maximum.
20795 * PSU_SATA_AHCI_VENDOR_PP3C_CWBGMX 0x14
20797 * CWBGN: COMWAKE Burst Gap Nominal.
20798 * PSU_SATA_AHCI_VENDOR_PP3C_CWBGN 0x08
20800 * CWNMP: COMWAKE Negate Minimum Period.
20801 * PSU_SATA_AHCI_VENDOR_PP3C_CWNMP 0x0E
20803 * PP3C - Port Phy3CfgRegister. This register controls the configuration of
20804 * the Phy Control OOB timing for the COMWAKE parameters for either Port 0
20805 * or Port 1. The Port configured is controlled by the value programmed in
20806 * to the Port Config Register.
20807 * (OFFSET, MASK, VALUE) (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U)
20809 PSU_Mask_Write(SATA_AHCI_VENDOR_PP3C_OFFSET,
20810 0xFFFFFFFFU, 0x0E081406U);
20811 /*##################################################################### */
20814 * Register : PP4C @ 0XFD0C00B4
20816 * BMX: COM Burst Maximum.
20817 * PSU_SATA_AHCI_VENDOR_PP4C_BMX 0x13
20819 * BNM: COM Burst Nominal.
20820 * PSU_SATA_AHCI_VENDOR_PP4C_BNM 0x08
20822 * SFD: Signal Failure Detection, if the signal detection de-asserts for a
20823 * time greater than this then the OOB detector will determine this is a li
20824 * ne idle and cause the PhyInit state machine to exit the Phy Ready State.
20825 * A value of zero disables the Signal Failure Detector. The value is base
20826 * d on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving
20827 * a nominal time of 500ns based on a 150MHz PMCLK.
20828 * PSU_SATA_AHCI_VENDOR_PP4C_SFD 0x4A
20830 * PTST: Partial to Slumber timer value, specific delay the controller shou
20831 * ld apply while in partial before entering slumber. The value is bases on
20832 * the system clock divided by 128, total delay = (Sys Clock Period) * PTS
20834 * PSU_SATA_AHCI_VENDOR_PP4C_PTST 0x06
20836 * PP4C - Port Phy4Cfg Register. This register controls the configuration o
20837 * f the Phy Control Burst timing for the COM parameters for either Port 0
20838 * or Port 1. The Port configured is controlled by the value programmed int
20839 * o the Port Config Register.
20840 * (OFFSET, MASK, VALUE) (0XFD0C00B4, 0xFFFFFFFFU ,0x064A0813U)
20842 PSU_Mask_Write(SATA_AHCI_VENDOR_PP4C_OFFSET,
20843 0xFFFFFFFFU, 0x064A0813U);
20844 /*##################################################################### */
20847 * Register : PP5C @ 0XFD0C00B8
20849 * RIT: Retry Interval Timer. The calculated value divided by two, the lowe
20850 * r digit of precision is not needed.
20851 * PSU_SATA_AHCI_VENDOR_PP5C_RIT 0xC96A4
20853 * RCT: Rate Change Timer, a value based on the 54.2us for which a SATA dev
20854 * ice will transmit at a fixed rate ALIGNp after OOB has completed, for a
20855 * fast SERDES it is suggested that this value be 54.2us / 4
20856 * PSU_SATA_AHCI_VENDOR_PP5C_RCT 0x3FF
20858 * PP5C - Port Phy5Cfg Register. This register controls the configuration o
20859 * f the Phy Control Retry Interval timing for either Port 0 or Port 1. The
20860 * Port configured is controlled by the value programmed into the Port Con
20862 * (OFFSET, MASK, VALUE) (0XFD0C00B8, 0xFFFFFFFFU ,0x3FFC96A4U)
20864 PSU_Mask_Write(SATA_AHCI_VENDOR_PP5C_OFFSET,
20865 0xFFFFFFFFU, 0x3FFC96A4U);
20866 /*##################################################################### */
20871 unsigned long psu_resetin_init_data(void)
20874 * PUTTING SERDES PERIPHERAL IN RESET
20877 * PUTTING USB0 IN RESET
20880 * Register : RST_LPD_TOP @ 0XFF5E023C
20882 * USB 0 reset for control registers
20883 * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X1
20885 * USB 0 sleep circuit reset
20886 * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X1
20889 * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X1
20891 * Software control register for the LPD block.
20892 * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000540U)
20894 PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000540U, 0x00000540U);
20895 /*##################################################################### */
20898 * PUTTING GEM0 IN RESET
20901 * Register : RST_LPD_IOU0 @ 0XFF5E0230
20904 * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X1
20906 * Software controlled reset for the GEMs
20907 * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000008U)
20909 PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET,
20910 0x00000008U, 0x00000008U);
20911 /*##################################################################### */
20914 * PUTTING SATA IN RESET
20917 * Register : RST_FPD_TOP @ 0XFD1A0100
20919 * Sata block level reset
20920 * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X1
20922 * FPD Block level software controlled reset
20923 * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000002U)
20925 PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00000002U, 0x00000002U);
20926 /*##################################################################### */
20929 * PUTTING PCIE IN RESET
20932 * Register : RST_FPD_TOP @ 0XFD1A0100
20934 * PCIE config reset
20935 * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X1
20937 * PCIE control block level reset
20938 * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X1
20940 * PCIE bridge block level reset (AXI interface)
20941 * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X1
20943 * FPD Block level software controlled reset
20944 * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000E0000U ,0x000E0000U)
20946 PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000E0000U, 0x000E0000U);
20947 /*##################################################################### */
20950 * PUTTING DP IN RESET
20953 * Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238
20955 * Two bits per lane. When set to 11, moves the GT to power down mode. When
20956 * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] -
20958 * PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0XA
20960 * Control PHY Power down
20961 * (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x0000000AU)
20963 PSU_Mask_Write(DP_DP_TX_PHY_POWER_DOWN_OFFSET,
20964 0x0000000FU, 0x0000000AU);
20965 /*##################################################################### */
20968 * Register : DP_PHY_RESET @ 0XFD4A0200
20970 * Set to '1' to hold the GT in reset. Clear to release.
20971 * PSU_DP_DP_PHY_RESET_GT_RESET 0X1
20973 * Reset the transmitter PHY.
20974 * (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000002U)
20976 PSU_Mask_Write(DP_DP_PHY_RESET_OFFSET, 0x00000002U, 0x00000002U);
20977 /*##################################################################### */
20980 * Register : RST_FPD_TOP @ 0XFD1A0100
20982 * Display Port block level reset (includes DPDMA)
20983 * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X1
20985 * FPD Block level software controlled reset
20986 * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00010000U)
20988 PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00010000U, 0x00010000U);
20989 /*##################################################################### */
20994 unsigned long psu_ps_pl_isolation_removal_data(void)
20997 * PS-PL POWER UP REQUEST
21000 * Register : REQ_PWRUP_INT_EN @ 0XFFD80118
21002 * Power-up Request Interrupt Enable for PL
21003 * PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL 1
21005 * Power-up Request Interrupt Enable Register. Writing a 1 to this location
21006 * will unmask the interrupt.
21007 * (OFFSET, MASK, VALUE) (0XFFD80118, 0x00800000U ,0x00800000U)
21009 PSU_Mask_Write(PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET,
21010 0x00800000U, 0x00800000U);
21011 /*##################################################################### */
21014 * Register : REQ_PWRUP_TRIG @ 0XFFD80120
21016 * Power-up Request Trigger for PL
21017 * PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL 1
21019 * Power-up Request Trigger Register. A write of one to this location will
21020 * generate a power-up request to the PMU.
21021 * (OFFSET, MASK, VALUE) (0XFFD80120, 0x00800000U ,0x00800000U)
21023 PSU_Mask_Write(PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET,
21024 0x00800000U, 0x00800000U);
21025 /*##################################################################### */
21028 * POLL ON PL POWER STATUS
21031 * Register : REQ_PWRUP_STATUS @ 0XFFD80110
21033 * Power-up Request Status for PL
21034 * PSU_PMU_GLOBAL_REQ_PWRUP_STATUS_PL 1
21035 * (OFFSET, MASK, VALUE) (0XFFD80110, 0x00800000U ,0x00000000U)
21037 mask_pollOnValue(PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET,
21038 0x00800000U, 0x00000000U);
21040 /*##################################################################### */
21045 unsigned long psu_afi_config(void)
21051 * Register : RST_FPD_TOP @ 0XFD1A0100
21053 * AF_FM0 block level reset
21054 * PSU_CRF_APB_RST_FPD_TOP_AFI_FM0_RESET 0
21056 * AF_FM1 block level reset
21057 * PSU_CRF_APB_RST_FPD_TOP_AFI_FM1_RESET 0
21059 * AF_FM2 block level reset
21060 * PSU_CRF_APB_RST_FPD_TOP_AFI_FM2_RESET 0
21062 * AF_FM3 block level reset
21063 * PSU_CRF_APB_RST_FPD_TOP_AFI_FM3_RESET 0
21065 * AF_FM4 block level reset
21066 * PSU_CRF_APB_RST_FPD_TOP_AFI_FM4_RESET 0
21068 * AF_FM5 block level reset
21069 * PSU_CRF_APB_RST_FPD_TOP_AFI_FM5_RESET 0
21071 * FPD Block level software controlled reset
21072 * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00001F80U ,0x00000000U)
21074 PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00001F80U, 0x00000000U);
21075 /*##################################################################### */
21078 * Register : RST_LPD_TOP @ 0XFF5E023C
21081 * PSU_CRL_APB_RST_LPD_TOP_AFI_FM6_RESET 0
21083 * Software control register for the LPD block.
21084 * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00080000U ,0x00000000U)
21086 PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00080000U, 0x00000000U);
21087 /*##################################################################### */
21090 * AFIFM INTERFACE WIDTH
21093 * Register : afi_fs @ 0XFD615000
21095 * Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit
21096 * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data
21097 * width 11: reserved
21098 * PSU_FPD_SLCR_AFI_FS_DW_SS0_SEL 0x2
21100 * Select the 32/64/128-bit data width selection for the Slave 1 00: 32-bit
21101 * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data
21102 * width 11: reserved
21103 * PSU_FPD_SLCR_AFI_FS_DW_SS1_SEL 0x2
21105 * afi fs SLCR control register. This register is static and should not be
21106 * modified during operation.
21107 * (OFFSET, MASK, VALUE) (0XFD615000, 0x00000F00U ,0x00000A00U)
21109 PSU_Mask_Write(FPD_SLCR_AFI_FS_OFFSET, 0x00000F00U, 0x00000A00U);
21110 /*##################################################################### */
21115 unsigned long psu_ps_pl_reset_config_data(void)
21118 * PS PL RESET SEQUENCE
21121 * FABRIC RESET USING EMIO
21124 * Register : MASK_DATA_5_MSW @ 0XFF0A002C
21126 * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
21127 * PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW 0x8000
21129 * Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits)
21130 * (OFFSET, MASK, VALUE) (0XFF0A002C, 0xFFFF0000U ,0x80000000U)
21132 PSU_Mask_Write(GPIO_MASK_DATA_5_MSW_OFFSET,
21133 0xFFFF0000U, 0x80000000U);
21134 /*##################################################################### */
21137 * Register : DIRM_5 @ 0XFF0A0344
21139 * Operation is the same as DIRM_0[DIRECTION_0]
21140 * PSU_GPIO_DIRM_5_DIRECTION_5 0x80000000
21142 * Direction mode (GPIO Bank5, EMIO)
21143 * (OFFSET, MASK, VALUE) (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U)
21145 PSU_Mask_Write(GPIO_DIRM_5_OFFSET, 0xFFFFFFFFU, 0x80000000U);
21146 /*##################################################################### */
21149 * Register : OEN_5 @ 0XFF0A0348
21151 * Operation is the same as OEN_0[OP_ENABLE_0]
21152 * PSU_GPIO_OEN_5_OP_ENABLE_5 0x80000000
21154 * Output enable (GPIO Bank5, EMIO)
21155 * (OFFSET, MASK, VALUE) (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U)
21157 PSU_Mask_Write(GPIO_OEN_5_OFFSET, 0xFFFFFFFFU, 0x80000000U);
21158 /*##################################################################### */
21161 * Register : DATA_5 @ 0XFF0A0054
21164 * PSU_GPIO_DATA_5_DATA_5 0x80000000
21166 * Output Data (GPIO Bank5, EMIO)
21167 * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U)
21169 PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x80000000U);
21170 /*##################################################################### */
21174 /*##################################################################### */
21177 * FABRIC RESET USING DATA_5 TOGGLE
21180 * Register : DATA_5 @ 0XFF0A0054
21183 * PSU_GPIO_DATA_5_DATA_5 0X00000000
21185 * Output Data (GPIO Bank5, EMIO)
21186 * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U)
21188 PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x00000000U);
21189 /*##################################################################### */
21193 /*##################################################################### */
21196 * FABRIC RESET USING DATA_5 TOGGLE
21199 * Register : DATA_5 @ 0XFF0A0054
21202 * PSU_GPIO_DATA_5_DATA_5 0x80000000
21204 * Output Data (GPIO Bank5, EMIO)
21205 * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U)
21207 PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x80000000U);
21208 /*##################################################################### */
21214 unsigned long psu_ddr_phybringup_data(void)
21218 unsigned int regval = 0;
21220 unsigned int pll_retry = 10;
21222 unsigned int pll_locked = 0;
21225 while ((pll_retry > 0) && (!pll_locked)) {
21227 Xil_Out32(0xFD080004, 0x00040010);/*PIR*/
21228 Xil_Out32(0xFD080004, 0x00040011);/*PIR*/
21230 while ((Xil_In32(0xFD080030) & 0x1) != 1) {
21233 /*TIMEOUT poll mechanism need to be inserted in this block*/
21238 pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
21240 pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
21242 pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
21244 pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
21246 pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
21250 Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) |
21251 (pll_retry << 16));/*GPR0*/
21252 Xil_Out32(0xFD080004U, 0x00040063U);
21253 /* PHY BRINGUP SEQ */
21254 while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) {
21257 /*TIMEOUT poll mechanism need to be inserted in this block*/
21261 prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
21262 /* poll for PHY initialization to complete */
21263 while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) {
21266 /*TIMEOUT poll mechanism need to be inserted in this block*/
21271 Xil_Out32(0xFD0701B0U, 0x00000001U);
21272 Xil_Out32(0xFD070320U, 0x00000001U);
21273 while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) {
21276 /*TIMEOUT poll mechanism need to be inserted in this block*/
21280 prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
21281 Xil_Out32(0xFD080004, 0x0004FE01); /*PUB_PIR*/
21282 regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/
21283 while (regval != 0x80000FFF)
21284 regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/
21286 /* Run Vref training in static read mode*/
21287 Xil_Out32(0xFD080200U, 0x100091C7U);
21288 Xil_Out32(0xFD080018U, 0x00F01EEFU);
21289 prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
21290 prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
21291 prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
21292 prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
21293 prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
21294 prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
21297 Xil_Out32(0xFD080004, 0x00060001); /*PUB_PIR*/
21298 regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/
21299 while ((regval & 0x80004001) != 0x80004001) {
21301 regval = Xil_In32(0xFD080030);
21304 prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
21305 prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
21306 prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
21307 prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
21308 prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
21309 prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
21310 /*Vref training is complete, disabling static read mode*/
21311 Xil_Out32(0xFD080200U, 0x800091C7U);
21312 Xil_Out32(0xFD080018U, 0x00F122E7U);
21315 Xil_Out32(0xFD080004, 0x0000C001); /*PUB_PIR*/
21316 regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/
21317 while ((regval & 0x80000C01) != 0x80000C01) {
21319 regval = Xil_In32(0xFD080030);
21322 Xil_Out32(0xFD070180U, 0x01000040U);
21323 Xil_Out32(0xFD070060U, 0x00000000U);
21324 prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
21330 * CRL_APB Base Address
21332 #define CRL_APB_BASEADDR 0XFF5E0000U
21333 #define CRL_APB_RST_LPD_IOU0 ((CRL_APB_BASEADDR) + 0X00000230U)
21334 #define CRL_APB_RST_LPD_IOU1 ((CRL_APB_BASEADDR) + 0X00000234U)
21335 #define CRL_APB_RST_LPD_IOU2 ((CRL_APB_BASEADDR) + 0X00000238U)
21336 #define CRL_APB_RST_LPD_TOP ((CRL_APB_BASEADDR) + 0X0000023CU)
21337 #define CRL_APB_IOU_SWITCH_CTRL ((CRL_APB_BASEADDR) + 0X0000009CU)
21340 * CRF_APB Base Address
21342 #define CRF_APB_BASEADDR 0XFD1A0000U
21344 #define CRF_APB_RST_FPD_TOP ((CRF_APB_BASEADDR) + 0X00000100U)
21345 #define CRF_APB_GPU_REF_CTRL ((CRF_APB_BASEADDR) + 0X00000084U)
21346 #define CRF_APB_RST_DDR_SS ((CRF_APB_BASEADDR) + 0X00000108U)
21347 #define PSU_MASK_POLL_TIME 1100000
21350 * * Register: CRF_APB_DPLL_CTRL
21352 #define CRF_APB_DPLL_CTRL ((CRF_APB_BASEADDR) + 0X0000002C)
21355 #define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16
21356 #define CRF_APB_DPLL_CTRL_DIV2_WIDTH 1
21358 #define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8
21359 #define CRF_APB_DPLL_CTRL_FBDIV_WIDTH 7
21361 #define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3
21362 #define CRF_APB_DPLL_CTRL_BYPASS_WIDTH 1
21364 #define CRF_APB_DPLL_CTRL_RESET_SHIFT 0
21365 #define CRF_APB_DPLL_CTRL_RESET_WIDTH 1
21368 * * Register: CRF_APB_DPLL_CFG
21370 #define CRF_APB_DPLL_CFG ((CRF_APB_BASEADDR) + 0X00000030)
21372 #define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25
21373 #define CRF_APB_DPLL_CFG_LOCK_DLY_WIDTH 7
21375 #define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13
21376 #define CRF_APB_DPLL_CFG_LOCK_CNT_WIDTH 10
21378 #define CRF_APB_DPLL_CFG_LFHF_SHIFT 10
21379 #define CRF_APB_DPLL_CFG_LFHF_WIDTH 2
21381 #define CRF_APB_DPLL_CFG_CP_SHIFT 5
21382 #define CRF_APB_DPLL_CFG_CP_WIDTH 4
21384 #define CRF_APB_DPLL_CFG_RES_SHIFT 0
21385 #define CRF_APB_DPLL_CFG_RES_WIDTH 4
21388 * Register: CRF_APB_PLL_STATUS
21390 #define CRF_APB_PLL_STATUS ((CRF_APB_BASEADDR) + 0X00000044)
21393 static int mask_pollOnValue(u32 add, u32 mask, u32 value)
21395 volatile u32 *addr = (volatile u32 *)(unsigned long) add;
21398 while ((*addr & mask) != value) {
21399 if (i == PSU_MASK_POLL_TIME)
21406 static int mask_poll(u32 add, u32 mask)
21408 volatile u32 *addr = (volatile u32 *)(unsigned long) add;
21411 while (!(*addr & mask)) {
21412 if (i == PSU_MASK_POLL_TIME)
21419 static void mask_delay(u32 delay)
21424 static u32 mask_read(u32 add, u32 mask)
21426 volatile u32 *addr = (volatile u32 *)(unsigned long) add;
21427 u32 val = (*addr & mask);
21431 static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly, int d_lock_cnt,
21432 int d_lfhf, int d_cp, int d_res) {
21434 unsigned int pll_ctrl_regval;
21435 unsigned int pll_status_regval;
21437 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL);
21438 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_DIV2_MASK);
21439 pll_ctrl_regval = pll_ctrl_regval | (1 << CRF_APB_DPLL_CTRL_DIV2_SHIFT);
21440 Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval);
21442 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG);
21443 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_LOCK_DLY_MASK);
21444 pll_ctrl_regval = pll_ctrl_regval |
21445 (d_lock_dly << CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT);
21446 Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval);
21448 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG);
21449 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_LOCK_CNT_MASK);
21450 pll_ctrl_regval = pll_ctrl_regval |
21451 (d_lock_cnt << CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT);
21452 Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval);
21454 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG);
21455 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_LFHF_MASK);
21456 pll_ctrl_regval = pll_ctrl_regval |
21457 (d_lfhf << CRF_APB_DPLL_CFG_LFHF_SHIFT);
21458 Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval);
21460 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG);
21461 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_CP_MASK);
21462 pll_ctrl_regval = pll_ctrl_regval |
21463 (d_cp << CRF_APB_DPLL_CFG_CP_SHIFT);
21464 Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval);
21466 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG);
21467 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_RES_MASK);
21468 pll_ctrl_regval = pll_ctrl_regval |
21469 (d_res << CRF_APB_DPLL_CFG_RES_SHIFT);
21470 Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval);
21472 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL);
21473 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_FBDIV_MASK);
21474 pll_ctrl_regval = pll_ctrl_regval |
21475 (ddr_pll_fbdiv << CRF_APB_DPLL_CTRL_FBDIV_SHIFT);
21476 Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval);
21478 /*Setting PLL BYPASS*/
21479 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL);
21480 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_BYPASS_MASK);
21481 pll_ctrl_regval = pll_ctrl_regval |
21482 (1 << CRF_APB_DPLL_CTRL_BYPASS_SHIFT);
21483 Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval);
21485 /*Setting PLL RESET*/
21486 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL);
21487 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_RESET_MASK);
21488 pll_ctrl_regval = pll_ctrl_regval |
21489 (1 << CRF_APB_DPLL_CTRL_RESET_SHIFT);
21490 Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval);
21492 /*Clearing PLL RESET*/
21493 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL);
21494 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_RESET_MASK);
21495 pll_ctrl_regval = pll_ctrl_regval |
21496 (0 << CRF_APB_DPLL_CTRL_RESET_SHIFT);
21497 Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval);
21499 /*Checking PLL lock*/
21500 pll_status_regval = 0x00000000;
21501 while ((pll_status_regval & CRF_APB_PLL_STATUS_DPLL_LOCK_MASK) !=
21502 CRF_APB_PLL_STATUS_DPLL_LOCK_MASK)
21503 pll_status_regval = Xil_In32(CRF_APB_PLL_STATUS);
21508 /*Clearing PLL BYPASS*/
21509 pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL);
21510 pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_BYPASS_MASK);
21511 pll_ctrl_regval = pll_ctrl_regval |
21512 (0 << CRF_APB_DPLL_CTRL_BYPASS_SHIFT);
21513 Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval);
21517 /*Following SERDES programming sequences that a user need to follow to work
21518 * around the known limitation with SERDES. These sequences should done
21519 * before STEP 1 and STEP 2 as described in previous section. These
21520 * programming steps are *required for current silicon version and are
21521 * likely to undergo further changes with subsequent silicon versions.
21525 static int serdes_enb_coarse_saturation(void)
21527 /*Enable PLL Coarse Code saturation Logic*/
21528 Xil_Out32(0xFD402094, 0x00000010);
21529 Xil_Out32(0xFD406094, 0x00000010);
21530 Xil_Out32(0xFD40A094, 0x00000010);
21531 Xil_Out32(0xFD40E094, 0x00000010);
21535 int serdes_fixcal_code(void)
21537 int MaskStatus = 1;
21539 unsigned int rdata = 0;
21541 /*The valid codes are from 0x26 to 0x3C.
21542 *There are 23 valid codes in total.
21544 /*Each element of array stands for count of occurence of valid code.*/
21545 unsigned int match_pmos_code[23];
21546 /*Each element of array stands for count of occurence of valid code.*/
21547 /*The valid codes are from 0xC to 0x12.
21548 *There are 7 valid codes in total.
21550 unsigned int match_nmos_code[23];
21551 /*Each element of array stands for count of occurence of valid code.*/
21552 /*The valid codes are from 0x6 to 0xC.
21553 * There are 7 valid codes in total.
21555 unsigned int match_ical_code[7];
21556 /*Each element of array stands for count of occurence of valid code.*/
21557 unsigned int match_rcal_code[7];
21559 unsigned int p_code = 0;
21560 unsigned int n_code = 0;
21561 unsigned int i_code = 0;
21562 unsigned int r_code = 0;
21563 unsigned int repeat_count = 0;
21564 unsigned int L3_TM_CALIB_DIG20 = 0;
21565 unsigned int L3_TM_CALIB_DIG19 = 0;
21566 unsigned int L3_TM_CALIB_DIG18 = 0;
21567 unsigned int L3_TM_CALIB_DIG16 = 0;
21568 unsigned int L3_TM_CALIB_DIG15 = 0;
21569 unsigned int L3_TM_CALIB_DIG14 = 0;
21573 rdata = Xil_In32(0XFD40289C);
21574 rdata = rdata & ~0x03;
21575 rdata = rdata | 0x1;
21576 Xil_Out32(0XFD40289C, rdata);
21577 // check supply good status before starting AFE sequencing
21581 if (count == PSU_MASK_POLL_TIME)
21583 rdata = Xil_In32(0xFD402B1C);
21585 }while((rdata&0x0000000E) !=0x0000000E);
21587 for (i = 0; i < 23; i++) {
21588 match_pmos_code[i] = 0;
21589 match_nmos_code[i] = 0;
21591 for (i = 0; i < 7; i++) {
21592 match_ical_code[i] = 0;
21593 match_rcal_code[i] = 0;
21598 /*Clear ICM_CFG value*/
21599 Xil_Out32(0xFD410010, 0x00000000);
21600 Xil_Out32(0xFD410014, 0x00000000);
21602 /*Set ICM_CFG value*/
21603 /*This will trigger recalibration of all stages*/
21604 Xil_Out32(0xFD410010, 0x00000001);
21605 Xil_Out32(0xFD410014, 0x00000000);
21607 /*is calibration done? polling on L3_CALIB_DONE_STATUS*/
21608 MaskStatus = mask_poll(0xFD40EF14, 0x2);
21609 if (MaskStatus == 0) {
21610 /*failure here is because of calibration done timeout*/
21611 xil_printf("#SERDES initialization timed out\n\r");
21615 p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);/*PMOS code*/
21616 n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);/*NMOS code*/
21617 /*m_code = mask_read(0xFD40EF20, 0xFFFFFFFF)*/;/*MPHY code*/
21618 i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);/*ICAL code*/
21619 r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);/*RX code*/
21620 /*u_code = mask_read(0xFD40EF2C, 0xFFFFFFFF)*/;/*USB2 code*/
21622 /*PMOS code in acceptable range*/
21623 if ((p_code >= 0x26) && (p_code <= 0x3C))
21624 match_pmos_code[p_code - 0x26] += 1;
21626 /*NMOS code in acceptable range*/
21627 if ((n_code >= 0x26) && (n_code <= 0x3C))
21628 match_nmos_code[n_code - 0x26] += 1;
21630 /*PMOS code in acceptable range*/
21631 if ((i_code >= 0xC) && (i_code <= 0x12))
21632 match_ical_code[i_code - 0xC] += 1;
21634 /*NMOS code in acceptable range*/
21635 if ((r_code >= 0x6) && (r_code <= 0xC))
21636 match_rcal_code[r_code - 0x6] += 1;
21639 } while (repeat_count++ < 10);
21641 /*find the valid code which resulted in maximum times in 10 iterations*/
21642 for (i = 0; i < 23; i++) {
21643 if (match_pmos_code[i] >= match_pmos_code[0]) {
21644 match_pmos_code[0] = match_pmos_code[i];
21647 if (match_nmos_code[i] >= match_nmos_code[0]) {
21648 match_nmos_code[0] = match_nmos_code[i];
21653 for (i = 0; i < 7; i++) {
21654 if (match_ical_code[i] >= match_ical_code[0]) {
21655 match_ical_code[0] = match_ical_code[i];
21658 if (match_rcal_code[i] >= match_rcal_code[0]) {
21659 match_rcal_code[0] = match_rcal_code[i];
21663 /*L3_TM_CALIB_DIG20[3] PSW MSB Override*/
21664 /*L3_TM_CALIB_DIG20[2:0] PSW Code [4:2]*/
21665 L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);/*read DIG20*/
21666 L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
21669 /*L3_TM_CALIB_DIG19[7:6] PSW Code [1:0]*/
21670 /*L3_TM_CALIB_DIG19[5] PSW Override*/
21671 /*L3_TM_CALIB_DIG19[2] NSW MSB Override*/
21672 /*L3_TM_CALIB_DIG19[1:0] NSW Code [4:3]*/
21673 L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);/*read DIG19*/
21674 L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
21675 | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
21677 /*L3_TM_CALIB_DIG18[7:5] NSW Code [2:0]*/
21678 /*L3_TM_CALIB_DIG18[4] NSW Override*/
21679 L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);/*read DIG18*/
21680 L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
21683 /*L3_TM_CALIB_DIG16[2:0] RX Code [3:1]*/
21684 L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);/*read DIG16*/
21685 L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
21687 /*L3_TM_CALIB_DIG15[7] RX Code [0]*/
21688 /*L3_TM_CALIB_DIG15[6] RX CODE Override*/
21689 /*L3_TM_CALIB_DIG15[3] ICAL MSB Override*/
21690 /*L3_TM_CALIB_DIG15[2:0] ICAL Code [3:1]*/
21691 L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);/*read DIG15*/
21692 L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
21693 | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
21695 /*L3_TM_CALIB_DIG14[7] ICAL Code [0]*/
21696 /*L3_TM_CALIB_DIG14[6] ICAL Override*/
21697 L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);/*read DIG14*/
21698 L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
21700 /*Forces the calibration values*/
21701 Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
21702 Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
21703 Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
21704 Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
21705 Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
21706 Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
21710 static int init_serdes(void)
21714 status &= psu_resetin_init_data();
21716 status &= serdes_fixcal_code();
21717 status &= serdes_enb_coarse_saturation();
21719 status &= psu_serdes_init_data();
21720 status &= psu_resetout_init_data();
21726 static void init_peripheral(void)
21728 /*SMMU_REG Interrrupt Enable: Followig register need to be written all the time to properly catch SMMU messages.*/
21729 PSU_Mask_Write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
21732 static int psu_init_xppu_aper_ram(void)
21738 int psu_lpd_protection(void)
21740 psu_init_xppu_aper_ram();
21744 int psu_ddr_protection(void)
21746 psu_ddr_xmpu0_data();
21747 psu_ddr_xmpu1_data();
21748 psu_ddr_xmpu2_data();
21749 psu_ddr_xmpu3_data();
21750 psu_ddr_xmpu4_data();
21751 psu_ddr_xmpu5_data();
21754 int psu_ocm_protection(void)
21756 psu_ocm_xmpu_data();
21760 int psu_fpd_protection(void)
21762 psu_fpd_xmpu_data();
21766 int psu_protection_lock(void)
21768 psu_protection_lock_data();
21772 int psu_protection(void)
21774 psu_apply_master_tz();
21775 psu_ddr_protection();
21776 psu_ocm_protection();
21777 psu_fpd_protection();
21778 psu_lpd_protection();
21787 status &= psu_mio_init_data();
21788 status &= psu_pll_init_data();
21789 status &= psu_clock_init_data();
21790 status &= psu_ddr_init_data();
21791 status &= psu_ddr_phybringup_data();
21792 status &= psu_peripherals_init_data();
21793 status &= init_serdes();
21796 status &= psu_peripherals_powerdwn_data();
21797 status &= psu_afi_config();
21798 psu_ddr_qos_init_data();