1 /******************************************************************************
\r
3 * Copyright 2013 Altera Corporation. All Rights Reserved.
\r
5 * Redistribution and use in source and binary forms, with or without
\r
6 * modification, are permitted provided that the following conditions are met:
\r
8 * 1. Redistributions of source code must retain the above copyright notice,
\r
9 * this list of conditions and the following disclaimer.
\r
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
\r
12 * this list of conditions and the following disclaimer in the documentation
\r
13 * and/or other materials provided with the distribution.
\r
15 * 3. The name of the author may not be used to endorse or promote products
\r
16 * derived from this software without specific prior written permission.
\r
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
\r
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
\r
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
\r
21 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
\r
22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
\r
23 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
\r
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
\r
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
\r
26 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
\r
29 ******************************************************************************/
\r
31 #ifndef __ALT_DMA_H__
\r
32 #define __ALT_DMA_H__
\r
35 #include "alt_dma_common.h"
\r
36 #include "alt_dma_program.h"
\r
41 #endif /* __cplusplus */
\r
44 * \addtogroup ALT_DMA DMA Controller API
\r
46 * This module defines the API for configuration and use of the general purpose
\r
47 * DMA controller for the SoC. The DMA controller is an instance of the ARM
\r
48 * Corelink DMA Controller (DMA-330).
\r
51 * * ARM DDI 0424C, CoreLink DMA Controller DMA-330 Technical Reference
\r
53 * * ARM DAI 0239A, Application Note 239 Example Programs for the CoreLink
\r
54 * DMA Controller DMA-330.
\r
55 * * Altera, Cyclone V Device Handbook Volume 3: Hard Processor System
\r
56 * Technical Reference Manual, DMA Controller.
\r
62 * \addtogroup ALT_DMA_COMPILE DMA API Compile Options
\r
64 * This API provides control over the compile time inclusion of selected
\r
65 * modules. This can allow for a smaller resulting binary.
\r
70 #ifndef ALT_DMA_PERIPH_PROVISION_16550_SUPPORT
\r
71 #define ALT_DMA_PERIPH_PROVISION_16550_SUPPORT (1)
\r
74 #ifndef ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT
\r
75 #define ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT (1)
\r
83 * \addtogroup ALT_DMA_CSR DMA API for Configuration, Control, and Status
\r
85 * This API provides functions for configuration, control, and status queries
\r
86 * of the DMA controller.
\r
92 * This type definition enumerates the operational states that the DMA manager
\r
95 typedef enum ALT_DMA_MANAGER_STATE_e
\r
97 ALT_DMA_MANAGER_STATE_STOPPED = 0, /*!< Stopped */
\r
98 ALT_DMA_MANAGER_STATE_EXECUTING = 1, /*!< Executing */
\r
99 ALT_DMA_MANAGER_STATE_CACHE_MISS = 2, /*!< Cache Miss */
\r
100 ALT_DMA_MANAGER_STATE_UPDATING_PC = 3, /*!< Updating PC */
\r
101 ALT_DMA_MANAGER_STATE_WFE = 4, /*!< Waiting for Event */
\r
102 ALT_DMA_MANAGER_STATE_FAULTING = 15 /*!< Faulting */
\r
104 ALT_DMA_MANAGER_STATE_t;
\r
107 * This type definition enumerates the operational states that a DMA channel
\r
110 typedef enum ALT_DMA_CHANNEL_STATE_e
\r
112 ALT_DMA_CHANNEL_STATE_STOPPED = 0, /*!< Stopped */
\r
113 ALT_DMA_CHANNEL_STATE_EXECUTING = 1, /*!< Executing */
\r
114 ALT_DMA_CHANNEL_STATE_CACHE_MISS = 2, /*!< Cache Miss */
\r
115 ALT_DMA_CHANNEL_STATE_UPDATING_PC = 3, /*!< Updating PC */
\r
116 ALT_DMA_CHANNEL_STATE_WFE = 4, /*!< Waiting for Event */
\r
117 ALT_DMA_CHANNEL_STATE_AT_BARRIER = 5, /*!< At Barrier */
\r
118 ALT_DMA_CHANNEL_STATE_WFP = 7, /*!< Waiting for Peripheral */
\r
119 ALT_DMA_CHANNEL_STATE_KILLING = 8, /*!< Killing */
\r
120 ALT_DMA_CHANNEL_STATE_COMPLETING = 9, /*!< Completing */
\r
121 ALT_DMA_CHANNEL_STATE_FAULTING_COMPLETING = 14, /*!< Faulting Completing */
\r
122 ALT_DMA_CHANNEL_STATE_FAULTING = 15 /*!< Faulting */
\r
124 ALT_DMA_CHANNEL_STATE_t;
\r
127 * This type definition enumerates the possible fault status that the DMA
\r
128 * manager can have as a register mask.
\r
130 typedef enum ALT_DMA_MANAGER_FAULT_e
\r
133 * The DMA manager abort occured because of an instruction issued through
\r
134 * the debug interface.
\r
136 ALT_DMA_MANAGER_FAULT_DBG_INSTR = (int32_t)(1UL << 30),
\r
139 * The DMA manager instruction fetch AXI bus response was not OKAY.
\r
141 ALT_DMA_MANAGER_FAULT_INSTR_FETCH_ERR = (int32_t)(1UL << 16),
\r
144 * The DMA manager attempted to execute DMAWFE or DMASEV with
\r
145 * inappropriate security permissions.
\r
147 ALT_DMA_MANAGER_FAULT_MGR_EVNT_ERR = (int32_t)(1UL << 5),
\r
150 * The DMA manager attempted to execute DMAGO with inappropriate security
\r
153 ALT_DMA_MANAGER_FAULT_DMAGO_ERR = (int32_t)(1UL << 4),
\r
156 * The DMA manager attempted to execute an instruction operand that was
\r
157 * not valid for the DMA configuration.
\r
159 ALT_DMA_MANAGER_FAULT_OPERAND_INVALID = (int32_t)(1UL << 1),
\r
162 * The DMA manager attempted to execute an undefined instruction.
\r
164 ALT_DMA_MANAGER_FAULT_UNDEF_INSTR = (int32_t)(1UL << 0)
\r
166 ALT_DMA_MANAGER_FAULT_t;
\r
169 * This type definition enumerates the possible fault status that a channel
\r
170 * may have as a register mask.
\r
172 typedef enum ALT_DMA_CHANNEL_FAULT_e
\r
175 * The DMA channel has locked up due to resource starvation.
\r
177 ALT_DMA_CHANNEL_FAULT_LOCKUP_ERR = (int32_t)(1UL << 31),
\r
180 * The DMA channel abort occured because of an instruction issued through
\r
181 * the debug interface.
\r
183 ALT_DMA_CHANNEL_FAULT_DBG_INSTR = (int32_t)(1UL << 30),
\r
186 * The DMA channel data read AXI bus reponse was not OKAY.
\r
188 ALT_DMA_CHANNEL_FAULT_DATA_READ_ERR = (int32_t)(1UL << 18),
\r
191 * The DMA channel data write AXI bus response was not OKAY.
\r
193 ALT_DMA_CHANNEL_FAULT_DATA_WRITE_ERR = (int32_t)(1UL << 17),
\r
196 * The DMA channel instruction fetch AXI bus response was not OKAY.
\r
198 ALT_DMA_CHANNEL_FAULT_INSTR_FETCH_ERR = (int32_t)(1UL << 16),
\r
201 * The DMA channel MFIFO did not have the data for the DMAST instruction.
\r
203 ALT_DMA_CHANNEL_FAULT_ST_DATA_UNAVAILABLE = (int32_t)(1UL << 13),
\r
206 * The DMA channel MFIFO is too small to hold the DMALD instruction data,
\r
207 * or too small to servic the DMAST instruction request.
\r
209 ALT_DMA_CHANNEL_FAULT_MFIFO_ERR = (int32_t)(1UL << 12),
\r
212 * The DMA channel in non-secure state attempted to perform a secure read
\r
215 ALT_DMA_CHANNEL_FAULT_CH_RDWR_ERR = (int32_t)(1UL << 7),
\r
218 * The DMA channel in non-secure state attempted to execute the DMAWFP,
\r
219 * DMALDP, DMASTP, or DMAFLUSHP instruction involving a secure peripheral.
\r
221 ALT_DMA_CHANNEL_FAULT_CH_PERIPH_ERR = (int32_t)(1UL << 6),
\r
224 * The DMA channel in non-secure state attempted to execute the DMAWFE or
\r
225 * DMASEV instruction for a secure event or secure interrupt (if
\r
228 ALT_DMA_CHANNEL_FAULT_CH_EVNT_ERR = (int32_t)(1UL << 5),
\r
231 * The DMA channel attempted to execute an instruction operand that was
\r
232 * not valid for the DMA configuration.
\r
234 ALT_DMA_CHANNEL_FAULT_OPERAND_INVALID = (int32_t)(1UL << 1),
\r
237 * The DMA channel attempted to execute an undefined instruction.
\r
239 ALT_DMA_CHANNEL_FAULT_UNDEF_INSTR = (int32_t)(1UL << 0)
\r
241 ALT_DMA_CHANNEL_FAULT_t;
\r
244 * This type definition enumerates the possible DMA event-interrupt behavior
\r
245 * option selections when a DMASEV instruction is executed.
\r
247 typedef enum ALT_DMA_EVENT_SELECT_e
\r
250 * If the DMA controller executes DMASEV for the event-interrupt resource
\r
251 * then the DMA sends the event to all of the channel threads.
\r
253 ALT_DMA_EVENT_SELECT_SEND_EVT,
\r
256 * If the DMA controller executes DMASEV for the event-interrupt resource
\r
257 * then the DMA sets the \b irq[N] HIGH.
\r
259 ALT_DMA_EVENT_SELECT_SIG_IRQ
\r
261 ALT_DMA_EVENT_SELECT_t;
\r
264 * This type enumerates the DMA peripheral interface MUX selection options
\r
267 typedef enum ALT_DMA_PERIPH_MUX_e
\r
270 * Accept the reset default MUX selection
\r
272 ALT_DMA_PERIPH_MUX_DEFAULT = 0,
\r
275 * Select FPGA as the peripheral interface
\r
277 ALT_DMA_PERIPH_MUX_FPGA = 1,
\r
280 * Select CAN as the peripheral interface
\r
282 ALT_DMA_PERIPH_MUX_CAN = 2
\r
284 ALT_DMA_PERIPH_MUX_t;
\r
287 * This type defines the structure used to specify the configuration of the
\r
288 * security states and peripheral interface MUX selections for the DMA
\r
291 typedef struct ALT_DMA_CFG_s
\r
294 * DMA Manager security state configuration.
\r
296 ALT_DMA_SECURITY_t manager_sec;
\r
299 * DMA interrupt output security state configurations. Security state
\r
300 * configurations are 0-based index-aligned with the enumeration values
\r
301 * ALT_DMA_EVENT_0 through ALT_DMA_EVENT_7 of the ALT_DMA_EVENT_t type.
\r
303 ALT_DMA_SECURITY_t irq_sec[8];
\r
306 * Peripheral request interface security state configurations. Security
\r
307 * state configurations are 0-based index-aligned with the enumeration
\r
308 * values of the ALT_DMA_PERIPH_t type.
\r
310 ALT_DMA_SECURITY_t periph_sec[32];
\r
313 * DMA Peripheral Register Interface MUX Selections. MUX selections are
\r
314 * 0-based index-aligned with the enumeration values
\r
315 * ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 through
\r
316 * ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 of the ALT_DMA_PERIPH_t type.
\r
318 ALT_DMA_PERIPH_MUX_t periph_mux[4];
\r
323 * Initialize the DMA controller.
\r
325 * Initializes the DMA controller by setting the necessary control values to
\r
326 * establish the security state and MUXed peripheral request interface selection
\r
327 * configurations before taking the DMA controller out of reset.
\r
329 * After the DMA is initialized, the following conditions hold true:
\r
330 * * All DMA channel threads are in the Stopped state.
\r
331 * * All DMA channel threads are available for allocation.
\r
332 * * DMA Manager thread is waiting for an instruction from either APB
\r
334 * * The security state configurations of the DMA Manager, interrupt outputs,
\r
335 * and peripheral request interfaces are established and immutable until the
\r
337 * * The MUXed peripheral request interface selection configurations are
\r
338 * established and immutable until the DMA is reset.
\r
341 * A pointer to a ALT_DMA_CFG_t structure containing the desired
\r
342 * DMA controller security state and peripheral request interface
\r
345 * \retval ALT_E_SUCCESS The operation was successful.
\r
346 * \retval ALT_E_ERROR The operation failed.
\r
348 ALT_STATUS_CODE alt_dma_init(const ALT_DMA_CFG_t * dma_cfg);
\r
351 * Uninitializes the DMA controller.
\r
353 * Uninitializes the DMA controller by killing any running channel threads and
\r
354 * putting the DMA controller into reset.
\r
356 * \retval ALT_E_SUCCESS The operation was successful.
\r
357 * \retval ALT_E_ERROR The operation failed.
\r
359 ALT_STATUS_CODE alt_dma_uninit(void);
\r
362 * Allocate a DMA channel resource for use.
\r
365 * A DMA controller channel.
\r
367 * \retval ALT_E_SUCCESS The operation was successful.
\r
368 * \retval ALT_E_ERROR The operation failed.
\r
370 ALT_STATUS_CODE alt_dma_channel_alloc(ALT_DMA_CHANNEL_t channel);
\r
373 * Allocate a free DMA channel resource for use if there are any.
\r
376 * [out] A pointer to an output parameter that will contain the
\r
377 * channel allocated.
\r
379 * \retval ALT_E_SUCCESS The operation was successful.
\r
380 * \retval ALT_E_ERROR The operation failed. An unallocated channel
\r
381 * may not be available at the time of the API
\r
384 ALT_STATUS_CODE alt_dma_channel_alloc_any(ALT_DMA_CHANNEL_t * allocated);
\r
387 * Free a DMA channel resource for reuse.
\r
390 * The DMA controller channel resource to free.
\r
392 * \retval ALT_E_SUCCESS The operation was successful.
\r
393 * \retval ALT_E_ERROR The operation failed. The channel may not be in
\r
394 * the STOPPED state.
\r
396 ALT_STATUS_CODE alt_dma_channel_free(ALT_DMA_CHANNEL_t channel);
\r
399 * Start execution of a DMA microcode program on the specified DMA channel
\r
403 * The DMA channel thread used to execute the microcode program.
\r
406 * The DMA microcode program.
\r
408 * \retval ALT_E_SUCCESS The operation was successful.
\r
409 * \retval ALT_E_ERROR The operation failed.
\r
411 ALT_STATUS_CODE alt_dma_channel_exec(ALT_DMA_CHANNEL_t channel,
\r
412 ALT_DMA_PROGRAM_t * pgm);
\r
415 * Kill (abort) execution of any microcode program executing on the specified
\r
416 * DMA channel thread resource.
\r
418 * Terminates the channel thread of execution by issuing a DMAKILL instruction
\r
419 * using the DMA APB slave interface.
\r
422 * The DMA channel thread to abort any executing microcode program
\r
425 * \retval ALT_E_SUCCESS The operation was successful.
\r
426 * \retval ALT_E_ERROR The operation failed.
\r
427 * \retval ALT_E_TMO Timeout waiting for the channel to change into
\r
428 * KILLING or STOPPED state.
\r
430 ALT_STATUS_CODE alt_dma_channel_kill(ALT_DMA_CHANNEL_t channel);
\r
433 * Returns the current register value for the given DMA channel.
\r
436 * The DMA channel thread to abort any executing microcode program
\r
440 * Register to get the value for.
\r
443 * [out] The current value of the requested register.
\r
445 * \retval ALT_E_SUCCESS The operation was successful.
\r
446 * \retval ALT_E_ERROR The operation failed.
\r
447 * \retval ALT_E_BAD_ARG The specified channel or register is invalid.
\r
449 ALT_STATUS_CODE alt_dma_channel_reg_get(ALT_DMA_CHANNEL_t channel,
\r
450 ALT_DMA_PROGRAM_REG_t reg, uint32_t * val);
\r
453 * Signals the occurrence of an event or interrupt, using the specified event
\r
456 * Causes the CPU to issue a DMASEV instruction using the DMA APB slave
\r
459 * The Interrupt Enable Register (INTEN) register is used to control if each
\r
460 * event-interrupt resource is either an event or an interrupt. The INTEN
\r
461 * register sets the event-interrupt resource to function as an:
\r
462 * * Event - The DMAC generates an event for the specified event-interrupt
\r
463 * resource. When the DMAC executes a DMAWFE instruction for the
\r
464 * same event-interrupt resource then it clears the event.
\r
465 * * Interrupt - The DMAC sets the \b IRQ[N] signal high, where
\r
466 * \e evt_num is the number of the specified event
\r
467 * resource. The interrupt must be cleared after being handled.
\r
469 * When the configured to generate an event, this function may be used to
\r
470 * restart one or more waiting DMA channels (i.e. having executed a DMAWFE
\r
473 * See the following sections from the \e ARM DDI 0424C, CoreLink DMA Controller
\r
474 * DMA-330 Technical Reference Manual for implementation details and use cases:
\r
475 * * 2.5.1, Issuing Instructions to the DMAC using a Slave Interface
\r
476 * * 2.7, Using Events and Interrupts
\r
479 * A DMA event-interrupt resource. Allowable event values may be
\r
480 * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 but ALT_DMA_EVENT_ABORT is
\r
483 * \retval ALT_E_SUCCESS The operation was successful.
\r
484 * \retval ALT_E_ERROR The operation failed.
\r
485 * \retval ALT_E_BAD_ARG The given event number is invalid.
\r
487 ALT_STATUS_CODE alt_dma_send_event(ALT_DMA_EVENT_t evt_num);
\r
490 * Returns the current operational state of the DMA manager thread.
\r
493 * [out] Pointer to an output parameter to contain the DMA
\r
494 * channel thread state.
\r
496 * \retval ALT_E_SUCCESS The operation was successful.
\r
497 * \retval ALT_E_ERROR The operation failed.
\r
499 ALT_STATUS_CODE alt_dma_manager_state_get(ALT_DMA_MANAGER_STATE_t * state);
\r
502 * Returns the current operational state of the specified DMA channel thread.
\r
505 * The DMA channel thread to return the operational state of.
\r
508 * [out] Pointer to an output parameter to contain the DMA
\r
509 * channel thread state.
\r
511 * \retval ALT_E_SUCCESS The operation was successful.
\r
512 * \retval ALT_E_ERROR The operation failed.
\r
513 * \retval ALT_E_BAD_ARG The given channel identifier is invalid.
\r
515 ALT_STATUS_CODE alt_dma_channel_state_get(ALT_DMA_CHANNEL_t channel,
\r
516 ALT_DMA_CHANNEL_STATE_t * state);
\r
519 * Return the current fault status of the DMA manager thread.
\r
522 * [out] Pointer to an output parameter to contain the DMA
\r
523 * manager fault status.
\r
525 * \retval ALT_E_SUCCESS The operation was successful.
\r
526 * \retval ALT_E_ERROR The operation failed.
\r
528 ALT_STATUS_CODE alt_dma_manager_fault_status_get(ALT_DMA_MANAGER_FAULT_t * fault);
\r
531 * Return the current fault status of the specified DMA channel thread.
\r
534 * The DMA channel thread to return the fault status of.
\r
537 * [out] Pointer to an output parameter to contain the DMA
\r
538 * channel fault status.
\r
540 * \retval ALT_E_SUCCESS The operation was successful.
\r
541 * \retval ALT_E_ERROR The operation failed.
\r
542 * \retval ALT_E_BAD_ARG The given channel identifier is invalid.
\r
544 ALT_STATUS_CODE alt_dma_channel_fault_status_get(ALT_DMA_CHANNEL_t channel,
\r
545 ALT_DMA_CHANNEL_FAULT_t * fault);
\r
548 * Select whether the DMA controller sends the specific event to all channel
\r
549 * threads or signals an interrupt using the corressponding \b irq when a DMASEV
\r
550 * instruction is executed for the specified event-interrupt resource number.
\r
553 * The event-interrupt resource number. Valid values are
\r
554 * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT.
\r
557 * The desired behavior selection for \e evt_num when a DMASEV is
\r
560 * \retval ALT_E_SUCCESS The operation was successful.
\r
561 * \retval ALT_E_ERROR The operation failed.
\r
562 * \retval ALT_E_BAD_ARG The given selection identifier is invalid.
\r
564 ALT_STATUS_CODE alt_dma_event_int_select(ALT_DMA_EVENT_t evt_num,
\r
565 ALT_DMA_EVENT_SELECT_t opt);
\r
568 * Returns the status of the specified event-interrupt resource.
\r
570 * Returns ALT_E_TRUE if event is active or \b irq[N] is HIGH and returns
\r
571 * ALT_E_FALSE if event is inactive or \b irq[N] is LOW.
\r
574 * The event-interrupt resource number. Valid values are
\r
575 * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT.
\r
577 * \retval ALT_E_TRUE Event is active or \b irq[N] is HIGH.
\r
578 * \retval ALT_E_FALSE Event is inactive or \b irq[N] is LOW.
\r
579 * \retval ALT_E_ERROR The operation failed.
\r
580 * \retval ALT_E_BAD_ARG The given event identifier is invalid.
\r
582 ALT_STATUS_CODE alt_dma_event_int_status_get_raw(ALT_DMA_EVENT_t evt_num);
\r
585 * Returns the status of the specified interrupt resource.
\r
587 * Returns ALT_E_TRUE if interrupt is active and therfore \b irq[N] is HIGH and
\r
588 * returns ALT_E_FALSE if interrupt is inactive and therfore \b irq[N] is LOW.
\r
591 * The interrupt resource number. Valid values are
\r
592 * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT.
\r
594 * \retval ALT_E_TRUE Event is active or \b irq[N] is HIGH.
\r
595 * \retval ALT_E_FALSE Event is inactive or \b irq[N] is LOW.
\r
596 * \retval ALT_E_ERROR The operation failed.
\r
597 * \retval ALT_E_BAD_ARG The given event identifier is invalid.
\r
599 ALT_STATUS_CODE alt_dma_int_status_get(ALT_DMA_EVENT_t irq_num);
\r
602 * Clear the active (HIGH) status of the specified interrupt resource.
\r
604 * If the specified interrupt is HIGH, then sets \b irq[N] to LOW if the
\r
605 * event-interrupt resource is configured (see: alt_dma_event_int_enable())
\r
606 * to signal an interrupt. Otherwise, the status of \b irq[N] does not change.
\r
609 * The interrupt resource number. Valid values are
\r
610 * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT.
\r
612 * \retval ALT_E_SUCCESS The operation was successful.
\r
613 * \retval ALT_E_ERROR The operation failed.
\r
614 * \retval ALT_E_BAD_ARG The given event identifier is invalid.
\r
616 ALT_STATUS_CODE alt_dma_int_clear(ALT_DMA_EVENT_t irq_num);
\r
623 * \addtogroup ALT_DMA_STD_OPS DMA API for Standard Operations
\r
625 * The functions in this group provide common DMA operations for common bulk
\r
626 * data transfers between:
\r
627 * * Memory to Memory
\r
629 * * Memory to Peripheral
\r
630 * * Peripheral to Memory
\r
632 * All DMA operations are asynchronous. The following are the ways to receive
\r
633 * notification of a DMA transfer complete operation:
\r
634 * * Use alt_dma_channel_state_get() and poll for the
\r
635 * ALT_DMA_CHANNEL_STATE_STOPPED status.
\r
636 * * In conjunction with the interrupt API, use DMA events to signal an
\r
637 * interrupt. The event first must be configured to signal an interrupt
\r
638 * using alt_dma_event_int_select(). Configure the DMA program to send an
\r
640 * * Construct a custom program which waits for a particular event number by
\r
641 * assemblying a DMAWFE using alt_dma_program_DMAWFE(). Then run the custom
\r
642 * program on a different channel. The custom program will wait until the
\r
643 * DMA program sends the event. Configure the DMA program to send an event.
\r
645 * Cache related maintenance on the source and/or destinatino buffer are not
\r
646 * handled the DMA API and are the responsibility of the programmer. This is
\r
647 * because the DMA API does not have visibility into the current configuration
\r
648 * of the MMU or know about any special considerations regarding the source
\r
649 * and/or destination memory. The following are some example scenarios and
\r
650 * cache maintenance related precautions that may need to be taken:
\r
651 * * alt_dma_memory_to_memory(): Source buffer should be cleaned or purged,
\r
652 * destination buffer should be invalidated.
\r
653 * * alt_dma_zero_to_memory(): Destination buffer should be invalidated.
\r
654 * * alt_dma_memory_to_register(): Source buffer should be cleaned or purged.
\r
655 * * alt_dma_register_to_memory(): Destination buffer should be invalidated.
\r
656 * * alt_dma_memory_to_periph(): Source buffer should be cleaned or purged.
\r
657 * * alt_dma_periph_to_memory(): Destination buffer should be invalidated.
\r
663 * Uses the DMA engine to asynchronously copy the specified memory from the
\r
664 * given source address to the given destination address.
\r
666 * Overlapping memory regions are not supported.
\r
669 * The DMA channel thread to use for the transfer.
\r
672 * An allocated DMA program buffer to use for the life of the
\r
676 * The destination memory address to copy to.
\r
679 * The source memory address to copy from.
\r
682 * The size of the transfer in bytes.
\r
685 * If set to true, the DMA engine will be instructed to send an
\r
686 * event upon completion or fault.
\r
689 * If send_evt is true, the event specified will be sent.
\r
690 * Otherwise the parameter is ignored.
\r
692 * \retval ALT_E_SUCCESS The operation was successful.
\r
693 * \retval ALT_E_ERROR The operation failed.
\r
694 * \retval ALT_E_BAD_ARG The given channel or event identifier (if
\r
695 * used) is invalid, or the memory regions
\r
696 * specified are overlapping.
\r
698 ALT_STATUS_CODE alt_dma_memory_to_memory(ALT_DMA_CHANNEL_t channel,
\r
699 ALT_DMA_PROGRAM_t * program,
\r
704 ALT_DMA_EVENT_t evt);
\r
707 * Uses the DMA engine to asynchronously zero out the specified memory buffer.
\r
710 * The DMA channel thread to use for the transfer.
\r
713 * An allocated DMA program buffer to use for the life of the
\r
717 * The buffer memory address to zero out.
\r
720 * The size of the buffer in bytes.
\r
723 * If set to true, the DMA engine will be instructed to send an
\r
724 * event upon completion or fault.
\r
727 * If send_evt is true, the event specified will be sent.
\r
728 * Otherwise the parameter is ignored.
\r
730 * \retval ALT_E_SUCCESS The operation was successful.
\r
731 * \retval ALT_E_ERROR The operation failed.
\r
732 * \retval ALT_E_BAD_ARG The given channel or event identifier (if
\r
733 * used) is invalid.
\r
735 ALT_STATUS_CODE alt_dma_zero_to_memory(ALT_DMA_CHANNEL_t channel,
\r
736 ALT_DMA_PROGRAM_t * program,
\r
740 ALT_DMA_EVENT_t evt);
\r
743 * Uses the DMA engine to asynchronously transfer the contents of a memory
\r
744 * buffer to a keyhole register.
\r
747 * The DMA channel thread to use for the transfer.
\r
750 * An allocated DMA program buffer to use for the life of the
\r
754 * The address of the register to write buffer to.
\r
757 * The address of the memory buffer for the data.
\r
760 * The number of transfers to make.
\r
762 * \param register_width_bits
\r
763 * The width of the register to transfer to in bits. Valid values
\r
764 * are 8, 16, 32, and 64.
\r
767 * If set to true, the DMA engine will be instructed to send an
\r
768 * event upon completion or fault.
\r
771 * If send_evt is true, the event specified will be sent.
\r
772 * Otherwise the parameter is ignored.
\r
774 * \retval ALT_E_SUCCESS The operation was successful.
\r
775 * \retval ALT_E_ERROR The operation failed.
\r
776 * \retval ALT_E_BAD_ARG The given channel, event identifier (if used),
\r
777 * or register width are invalid, or if the
\r
778 * destination register or source buffer is
\r
779 * unaligned to the register width.
\r
781 ALT_STATUS_CODE alt_dma_memory_to_register(ALT_DMA_CHANNEL_t channel,
\r
782 ALT_DMA_PROGRAM_t * program,
\r
784 const void * src_buf,
\r
786 uint32_t register_width_bits,
\r
788 ALT_DMA_EVENT_t evt);
\r
791 * Uses the DMA engine to asynchronously transfer the contents of a keyhole
\r
792 * register to a memory buffer.
\r
795 * The DMA channel thread to use for the transfer.
\r
798 * An allocated DMA program buffer to use for the life of the
\r
802 * The address of the memory buffer to copy to.
\r
805 * The address of the keyhole register to read from.
\r
808 * The number of transfers to make.
\r
810 * \param register_width_bits
\r
811 * The width of the register to transfer to in bits. Valid values
\r
812 * are 8, 16, 32, and 64.
\r
815 * If set to true, the DMA engine will be instructed to send an
\r
816 * event upon completion or fault.
\r
819 * If send_evt is true, the event specified will be sent.
\r
820 * Otherwise the parameter is ignored.
\r
822 * \retval ALT_E_SUCCESS The operation was successful.
\r
823 * \retval ALT_E_ERROR The operation failed.
\r
824 * \retval ALT_E_BAD_ARG The given channel, event identifier (if used),
\r
825 * or register width are invalid, or if the
\r
826 * destination buffer or source register is
\r
827 * unaligned to the register width.
\r
829 ALT_STATUS_CODE alt_dma_register_to_memory(ALT_DMA_CHANNEL_t channel,
\r
830 ALT_DMA_PROGRAM_t * program,
\r
832 const void * src_reg,
\r
834 uint32_t register_width_bits,
\r
836 ALT_DMA_EVENT_t evt);
\r
839 * Uses the DMA engine to asynchronously copy memory from the given source
\r
840 * address to the specified peripheral. Because different peripheral has
\r
841 * different characteristics, individual peripherals need to be explicitly
\r
844 * The following lists the peripheral IDs supported by this API:
\r
845 * * ALT_DMA_PERIPH_QSPI_FLASH_TX
\r
846 * * ALT_DMA_PERIPH_UART0_TX
\r
847 * * ALT_DMA_PERIPH_UART1_TX
\r
850 * The DMA channel thread to use for the transfer.
\r
853 * An allocated DMA program buffer to use for the life of the
\r
857 * The destination peripheral to copy memory to.
\r
860 * The source memory address to copy from.
\r
863 * The size of the transfer in bytes.
\r
865 * \param periph_info
\r
866 * A pointer to a peripheral specific data structure. The
\r
867 * following list shows what data structure should be used for
\r
869 * * ALT_DMA_PERIPH_QSPI_FLASH_TX: This parameter is ignored.
\r
870 * * ALT_DMA_PERIPH_UART0_TX: Use a pointer to the
\r
871 * ALT_16550_HANDLE_t used to interact with that UART.
\r
872 * * ALT_DMA_PERIPH_UART1_TX: Use a pointer to the
\r
873 * ALT_16550_HANDLE_t used to interact with that UART.
\r
876 * If set to true, the DMA engine will be instructed to send an
\r
877 * event upon completion or fault.
\r
880 * If send_evt is true, the event specified will be sent.
\r
881 * Otherwise the parameter is ignored.
\r
883 * \retval ALT_E_SUCCESS The operation was successful.
\r
884 * \retval ALT_E_ERROR The operation failed.
\r
885 * \retval ALT_E_BAD_ARG The given channel, peripheral, or event
\r
886 * identifier (if used) is invalid.
\r
889 * Priority peripheral IDs to be supported:
\r
890 * * ALT_DMA_PERIPH_FPGA_0
\r
891 * * ALT_DMA_PERIPH_FPGA_1
\r
892 * * ALT_DMA_PERIPH_FPGA_2
\r
893 * * ALT_DMA_PERIPH_FPGA_3
\r
894 * * ALT_DMA_PERIPH_FPGA_4
\r
895 * * ALT_DMA_PERIPH_FPGA_5
\r
896 * * ALT_DMA_PERIPH_FPGA_6
\r
897 * * ALT_DMA_PERIPH_FPGA_7
\r
898 * * ALT_DMA_PERIPH_I2C0_TX
\r
899 * * ALT_DMA_PERIPH_I2C1_TX
\r
900 * * ALT_DMA_PERIPH_I2C2_TX
\r
901 * * ALT_DMA_PERIPH_I2C3_TX
\r
902 * * ALT_DMA_PERIPH_SPI0_MASTER_TX
\r
903 * * ALT_DMA_PERIPH_SPI0_SLAVE_TX
\r
904 * * ALT_DMA_PERIPH_SPI1_MASTER_TX
\r
905 * * ALT_DMA_PERIPH_SPI1_SLAVE_TX
\r
908 ALT_STATUS_CODE alt_dma_memory_to_periph(ALT_DMA_CHANNEL_t channel,
\r
909 ALT_DMA_PROGRAM_t * program,
\r
910 ALT_DMA_PERIPH_t dest,
\r
913 void * periph_info,
\r
915 ALT_DMA_EVENT_t evt);
\r
918 * Uses the DMA engine to copy memory from the specified peripheral to the
\r
919 * given destination address. Because different peripheral has different
\r
920 * characteristics, individual peripherals need to be explicitly supported.
\r
922 * The following lists the peripheral IDs supported by this API:
\r
923 * * ALT_DMA_PERIPH_QSPI_FLASH_RX
\r
924 * * ALT_DMA_PERIPH_UART0_RX
\r
925 * * ALT_DMA_PERIPH_UART1_RX
\r
928 * The DMA channel thread to use for the transfer.
\r
931 * An allocated DMA program buffer to use for the life of the
\r
935 * The destination memory address to copy to.
\r
938 * The source peripheral to copy memory from.
\r
941 * The size of the transfer in bytes.
\r
943 * \param periph_info
\r
944 * A pointer to a peripheral specific data structure. The
\r
945 * following list shows what data structure should be used for
\r
947 * * ALT_DMA_PERIPH_QSPI_FLASH_RX: This parameter is ignored.
\r
948 * * ALT_DMA_PERIPH_UART0_RX: Use a pointer to the
\r
949 * ALT_16550_HANDLE_t used to interact with that UART.
\r
950 * * ALT_DMA_PERIPH_UART1_RX: Use a pointer to the
\r
951 * ALT_16550_HANDLE_t used to interact with that UART.
\r
954 * If set to true, the DMA engine will be instructed to send an
\r
955 * event upon completion or fault.
\r
958 * If send_evt is true, the event specified will be sent.
\r
959 * Otherwise the parameter is ignored.
\r
961 * \retval ALT_E_SUCCESS The operation was successful.
\r
962 * \retval ALT_E_ERROR The operation failed.
\r
963 * \retval ALT_E_BAD_ARG The given channel, peripheral, or event
\r
964 * identifier (if used) is invalid.
\r
967 * Priority peripheral IDs to be supported:
\r
968 * * ALT_DMA_PERIPH_FPGA_0
\r
969 * * ALT_DMA_PERIPH_FPGA_1
\r
970 * * ALT_DMA_PERIPH_FPGA_2
\r
971 * * ALT_DMA_PERIPH_FPGA_3
\r
972 * * ALT_DMA_PERIPH_FPGA_4
\r
973 * * ALT_DMA_PERIPH_FPGA_5
\r
974 * * ALT_DMA_PERIPH_FPGA_6
\r
975 * * ALT_DMA_PERIPH_FPGA_7
\r
976 * * ALT_DMA_PERIPH_I2C0_RX
\r
977 * * ALT_DMA_PERIPH_I2C1_RX
\r
978 * * ALT_DMA_PERIPH_I2C2_RX
\r
979 * * ALT_DMA_PERIPH_I2C3_RX
\r
980 * * ALT_DMA_PERIPH_SPI0_MASTER_RX
\r
981 * * ALT_DMA_PERIPH_SPI0_SLAVE_RX
\r
982 * * ALT_DMA_PERIPH_SPI1_MASTER_RX
\r
983 * * ALT_DMA_PERIPH_SPI1_SLAVE_RX
\r
986 ALT_STATUS_CODE alt_dma_periph_to_memory(ALT_DMA_CHANNEL_t channel,
\r
987 ALT_DMA_PROGRAM_t * program,
\r
989 ALT_DMA_PERIPH_t src,
\r
991 void * periph_info,
\r
993 ALT_DMA_EVENT_t evt);
\r
1003 #ifdef __cplusplus
\r
1005 #endif /* __cplusplus */
\r
1007 #endif /* __ALT_DMA_H__ */
\r