]> git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Altera_Code/SoCSupport/mmu_support.c
Added project for Altera Cyclone V SoC, currently running from internal RAM.
[freertos] / FreeRTOS / Demo / CORTEX_A9_Cyclone_V_SoC_DK / Altera_Code / SoCSupport / mmu_support.c
1 /******************************************************************************
2 *
3 * Copyright 2013 Altera Corporation. All Rights Reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
21 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
23 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
26 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
27 * OF SUCH DAMAGE.
28 *
29 ******************************************************************************/
30
31 #include "alt_mmu.h"
32 #include "mmu_support.h"
33 //#include "boot_support.h"
34 #define ARRAY_COUNT(array) (sizeof(array) / sizeof(array[0]))
35
36
37 static uint32_t __attribute__ ((aligned (0x4000))) mmu_pt_storage[4096];
38
39 static void * mmu_pt_alloc(const size_t size, void * context) {
40
41         return context;
42 }
43
44 ALT_STATUS_CODE mmu_init(void) {
45
46         //
47         // Populate the page table with sections (1 MiB regions).
48         //
49         ALT_MMU_MEM_REGION_t regions[] =
50         {
51                 // Cacheable Memory area: 1 GiB
52                         {
53                                 .va                     = (void *)0x00000000,
54                                 .pa                     = (void *)0x00000000,
55                                 .size           = 0x40000000,
56                                 .access         = ALT_MMU_AP_FULL_ACCESS,
57                                 .attributes     = ALT_MMU_ATTR_WBA,
58                                 .shareable      = ALT_MMU_TTB_S_NON_SHAREABLE,
59                                 .execute        = ALT_MMU_TTB_XN_DISABLE,
60                                 .security       = ALT_MMU_TTB_NS_SECURE
61                         },
62
63                         // Non-cacheable Memory area: 1 GiB
64                         {
65                                 .va                     = (void *)0x40000000,
66                                 .pa                     = (void *)0x00000000,
67                                 .size           = 0x40000000,
68                                 .access         = ALT_MMU_AP_FULL_ACCESS,
69                                 .attributes     = ALT_MMU_ATTR_NC,
70                                 .shareable      = ALT_MMU_TTB_S_SHAREABLE,
71                                 .execute        = ALT_MMU_TTB_XN_DISABLE,
72                                 .security       = ALT_MMU_TTB_NS_SECURE
73                         },
74
75                         // Device area: Everything else
76                         {
77                                 .va         = (void *)0x80000000,
78                                 .pa         = (void *)0x40000000,
79                                 .size       = 0x40000000,
80                                 .access     = ALT_MMU_AP_NO_ACCESS,
81                                 .attributes = ALT_MMU_ATTR_FAULT,
82                                 .shareable  = ALT_MMU_TTB_S_SHAREABLE,
83                                 .execute    = ALT_MMU_TTB_XN_ENABLE,
84                                 .security   = ALT_MMU_TTB_NS_SECURE
85                         },
86
87                         // Device area: Everything else
88                         {
89                                 .va         = (void *)0xC0000000,
90                                 .pa         = (void *)0xC0000000,
91                                 .size       = 0x40000000,
92                                 .access     = ALT_MMU_AP_FULL_ACCESS,
93                                 .attributes = ALT_MMU_ATTR_DEVICE,
94                                 .shareable  = ALT_MMU_TTB_S_SHAREABLE,
95                                 .execute    = ALT_MMU_TTB_XN_ENABLE,
96                                 .security   = ALT_MMU_TTB_NS_SECURE
97                         }
98         };
99
100         ALT_STATUS_CODE status = ALT_E_SUCCESS;
101         uint32_t * ttb1 = NULL;
102
103         status |= alt_mmu_init();
104 //      BOOT_CHECK_STATUS;
105
106         size_t reqsize = alt_mmu_va_space_storage_required(regions,
107                         ARRAY_COUNT(regions));
108         if (reqsize > sizeof(mmu_pt_storage))
109                 status = ALT_E_ERROR;
110 //      BOOT_CHECK_STATUS;
111
112         status |= alt_mmu_va_space_create(&ttb1, regions, ARRAY_COUNT(regions), mmu_pt_alloc, mmu_pt_storage);
113 //      BOOT_CHECK_STATUS;
114
115         status |= alt_mmu_va_space_enable(ttb1);
116 //      BOOT_CHECK_STATUS;
117
118         return status;
119 }
120
121 ALT_STATUS_CODE mmu_uninit(void) {
122
123         return alt_mmu_disable();
124 }
125 /* md5sum:4fc6b96893e8e619490fad33b17c96d7 2013-09-28 20:48:16 */