git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/prr_iodefine.h

   1 /*******************************************************************************\r
   2 * DISCLAIMER\r
   3 * This software is supplied by Renesas Electronics Corporation and is only\r
   4 * intended for use with Renesas products. No other uses are authorized. This\r
   5 * software is owned by Renesas Electronics Corporation and is protected under\r
   6 * all applicable laws, including copyright laws.\r
   7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
   8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
   9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
  10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
  11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
  12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
  13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
  14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
  15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
  16 * Renesas reserves the right, without notice, to make changes to this software\r
  17 * and to discontinue the availability of this software. By using this software,\r
  18 * you agree to the additional terms and conditions found by accessing the\r
  19 * following link:\r
  20 * http://www.renesas.com/disclaimer\r
  21 *\r
  22 * Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
  23 *******************************************************************************/\r
  24 /*******************************************************************************\r
  25 * File Name     : prr_iodefine.h\r
  26 * Version       : 0.01\r
  27 * Device(s)     : Aragon\r
  28 * Tool-Chain    : DS-5 Ver 5.8\r
  29 *                 ARM Complier \r
  30 *               : \r
  31 * H/W Platform  : Aragon CPU Board\r
  32 * Description   : Aragon Sample Program vecotr.s\r
  33 *******************************************************************************/\r
  34 /*******************************************************************************\r
  35 * History : DD.MM.YYYY Version Description\r
  36 *         : 27.07.2012 0.01             \8eQ\8dl\8e\91\97¿\81FAragon_PRR120614.xls  !!!BSID\82Ì\93à\97e\82ª\8ed\97l\8f\91\82É\82È\82¢!!!\r
  37 *******************************************************************************/\r
  38 #ifndef __PRR_IODEFINE_H__\r
  39 #define __PRR_IODEFINE_H__\r
  40 \r
  41 #include "typedefine.h"\r
  42 \r
  43 struct st_prr {                                 /* struct PRR   */\r
  44        union {                                  /* MDR          */\r
  45        _UDWORD LONG;                            /*  Long Access */\r
  46              struct {                           /*  Bit Access  */\r
  47                     _UDWORD BTMD:3;             /*   BTMD       */\r
  48                     _UDWORD :1;                 /*              */\r
  49                     _UDWORD BTTEST:1;           /*   BTTEST     */\r
  50                     _UDWORD :1;                 /*              */\r
  51                     _UDWORD SEC:1;              /*   SEC        */\r
  52                     _UDWORD SELFEWP:1;          /*   SELFEWP    */\r
  53                     _UDWORD RAMBOOT:1;          /*   RAMBOOT    */\r
  54                     _UDWORD :23;                /*              */\r
  55                     } BIT;                      /*              */\r
  56              } MDR;                             /*              */\r
  57        union {                                  /* BSID         */\r
  58        _UDWORD LONG;                            /*  Long Access */\r
  59              struct {                           /*  Bit Access  */\r
  60                     _UDWORD dummy:32;                /*              */ /* !!!\83r\83b\83g\8c\88\92è\8e\9f\91æ\81A\92è\8b`\82·\82é!!! */\r
  61                     } BIT;                      /*              */\r
  62              } BSID;                            /*              */\r
  63        union {                                  /* ECCRR        */\r
  64        _UDWORD LONG;                            /*  Long Access */\r
  65              struct {                           /*  Bit Access  */\r
  66                     _UDWORD ECCEN:1;            /*   ECCEN      */\r
  67                     _UDWORD :31;                /*              */\r
  68                     } BIT;                      /*              */\r
  69              } ECCRR;                           /*              */\r
  70        _UBYTE wk0[276];                         /*              */\r
  71        union {                                  /* SEMRn        */\r
  72        _UDWORD LONG;                            /*  Long Access */\r
  73              struct {                           /*  Bit Access  */\r
  74                     _UDWORD SEMF:1;             /*   SEMF       */\r
  75                     _UDWORD :31;                /*              */\r
  76                     } BIT;                      /*              */\r
  77              } SEMRn[32];                       /*              */\r
  78        _UBYTE wk1[96];                          /*              */\r
  79        union {                                  /* RMPR         */\r
  80        _UDWORD LONG;                            /*  Long Access */\r
  81              struct {                           /*  Bit Access  */\r
  82                     _UDWORD AXI64:1;            /*   AXI64      */\r
  83                     _UDWORD AXI128:1;           /*   AXI128     */\r
  84                     _UDWORD :30;                /*              */\r
  85                     } BIT;                      /*              */\r
  86              } RMPR;                            /*              */\r
  87        union {                                  /* AXIBUSCTL0   */\r
  88        _UDWORD LONG;                            /*  Long Access */\r
  89              struct {                           /*  Bit Access  */\r
  90                     _UDWORD ETHAWCACHE:4;       /*   ETHAWCACHE */\r
  91                     _UDWORD :4;                 /*              */\r
  92                     _UDWORD ETHARCACHE:4;       /*   ETHARCACHE */\r
  93                     _UDWORD :4;                 /*              */\r
  94                     _UDWORD JCUAWCACHE:4;       /*   JCUAWCACHE */\r
  95                     _UDWORD :4;                 /*              */\r
  96                     _UDWORD JCUARCACHE:4;       /*   JCUARCACHE */\r
  97                     _UDWORD :4;                 /*              */\r
  98                     } BIT;                      /*              */\r
  99              } AXIBUSCTL0;                      /*              */\r
 100        union {                                  /* AXIBUSCTL1   */\r
 101        _UDWORD LONG;                            /*  Long Access */\r
 102              struct {                           /*  Bit Access  */\r
 103                     _UDWORD IMR21AWCACHE:4;     /*   IMR21AWCACHE */\r
 104                     _UDWORD :4;                 /*              */\r
 105                     _UDWORD IMR21ARCACHE:4;     /*   IMR21ARCACHE */\r
 106                     _UDWORD :4;                 /*              */\r
 107                     _UDWORD IMR20AWCACHE:4;     /*   IMR20AWCACHE */\r
 108                     _UDWORD :4;                 /*              */\r
 109                     _UDWORD IMR20ARCACHE:4;     /*   IMR20ARCACHE */\r
 110                     _UDWORD :4;                 /*              */\r
 111                     } BIT;                      /*              */\r
 112              } AXIBUSCTL1;                      /*              */\r
 113        union {                                  /* AXIBUSCTL2   */\r
 114        _UDWORD LONG;                            /*  Long Access */\r
 115              struct {                           /*  Bit Access  */\r
 116                     _UDWORD CEUAWCACHE:4;       /*   CEUAWCACHE */\r
 117                     _UDWORD :4;                 /*              */\r
 118                     _UDWORD CEUARCACHE:4;       /*   CEUARCACHE */\r
 119                     _UDWORD :4;                 /*              */\r
 120                     _UDWORD IMRDAWCACHE:4;      /*   IMRDAWCACHE */\r
 121                     _UDWORD :4;                 /*              */\r
 122                     _UDWORD IMRDARCACHE:4;      /*   IMRDARCACHE */\r
 123                     _UDWORD :4;                 /*              */\r
 124                     } BIT;                      /*              */\r
 125              } AXIBUSCTL2;                      /*              */\r
 126        union {                                  /* AXIBUSCTL3   */\r
 127        _UDWORD LONG;                            /*  Long Access */\r
 128              struct {                           /*  Bit Access  */\r
 129                     _UDWORD RGP641AWCACHE:4;    /*   RGP641AWCACHE */\r
 130                     _UDWORD :4;                 /*              */\r
 131                     _UDWORD RGP641ARCACHE:4;    /*   RGP641ARCACHE */\r
 132                     _UDWORD :4;                 /*              */\r
 133                     _UDWORD RGP640AWCACHE:4;    /*   RGP640AWCACHE */\r
 134                     _UDWORD :4;                 /*              */\r
 135                     _UDWORD RGP640ARCACHE:4;    /*   RGP640ARCACHE */\r
 136                     _UDWORD :4;                 /*              */\r
 137                     } BIT;                      /*              */\r
 138              } AXIBUSCTL3;                      /*              */\r
 139        union {                                  /* AXIBUSCTL4   */\r
 140        _UDWORD LONG;                            /*  Long Access */\r
 141              struct {                           /*  Bit Access  */\r
 142                     _UDWORD RGP1280AWCACHE:4;   /*   RGP1280AWCACHE */\r
 143                     _UDWORD :4;                 /*              */\r
 144                     _UDWORD RGP1280ARCACHE:4;   /*   RGP1280ARCACHE */\r
 145                     _UDWORD :4;                 /*              */\r
 146                     _UDWORD RGP642AWCACHE:4;    /*   RGP642AWCACHE */\r
 147                     _UDWORD :4;                 /*              */\r
 148                     _UDWORD RGP642ARCACHE:4;    /*   RGP642ARCACHE */\r
 149                     _UDWORD :4;                 /*              */\r
 150                     } BIT;                      /*              */\r
 151              } AXIBUSCTL4;                      /*              */\r
 152        union {                                  /* AXIBUSCTL5   */\r
 153        _UDWORD LONG;                            /*  Long Access */\r
 154              struct {                           /*  Bit Access  */\r
 155                     _UDWORD MLB_AxCACHE:2;      /*   MLB_AxCACHE */\r
 156                     _UDWORD :14;                /*              */\r
 157                     _UDWORD RGP1281AWCACHE:4;   /*   RGP1281AWCACHE */\r
 158                     _UDWORD :4;                 /*              */\r
 159                     _UDWORD RGP1281ARCACHE:4;   /*   RGP1281ARCACHE */\r
 160                     _UDWORD :4;                 /*              */\r
 161                     } BIT;                      /*              */\r
 162              } AXIBUSCTL5;                      /*              */\r
 163        union {                                  /* AXIBUSCTL6   */\r
 164        _UDWORD LONG;                            /*  Long Access */\r
 165              struct {                           /*  Bit Access  */\r
 166                     _UDWORD :8;                 /*              */\r
 167                     _UDWORD VDC502ARCACHE:4;    /*   VDC502ARCACHE */\r
 168                     _UDWORD :4;                 /*              */\r
 169                     _UDWORD VDC501AWCACHE:4;    /*   VDC501AWCACHE */\r
 170                     _UDWORD :4;                 /*              */\r
 171                     _UDWORD VDC501ARCACHE:4;    /*   VDC501ARCACHE */\r
 172                     _UDWORD :4;                 /*              */\r
 173                     } BIT;                      /*              */\r
 174              } AXIBUSCTL6;                      /*              */\r
 175        union {                                  /* AXIBUSCTL7   */\r
 176        _UDWORD LONG;                            /*  Long Access */\r
 177              struct {                           /*  Bit Access  */\r
 178                     _UDWORD :8;                 /*              */\r
 179                     _UDWORD VDC504ARCACHE:4;    /*   VDC504ARCACHE */\r
 180                     _UDWORD :4;                 /*              */\r
 181                     _UDWORD VDC503AWCACHE:4;    /*   VDC503AWCACHE */\r
 182                     _UDWORD :4;                 /*              */\r
 183                     _UDWORD VDC503ARCACHE:4;    /*   VDC503ARCACHE */\r
 184                     _UDWORD :4;                 /*              */\r
 185                     } BIT;                      /*              */\r
 186              } AXIBUSCTL7;                      /*              */\r
 187        union {                                  /* AXIBUSCTL8   */\r
 188        _UDWORD LONG;                            /*  Long Access */\r
 189              struct {                           /*  Bit Access  */\r
 190                     _UDWORD VDC511AWCACHE:4;    /*   VDC511AWCACHE */\r
 191                     _UDWORD :4;                 /*              */\r
 192                     _UDWORD VDC511ARCACHE:4;    /*   VDC511ARCACHE */\r
 193                     _UDWORD :4;                 /*              */\r
 194                     _UDWORD VDC505AWCACHE:4;    /*   VDC505AWCACHE */\r
 195                     _UDWORD :4;                 /*              */\r
 196                     _UDWORD VDC505ARCACHE:4;    /*   VDC505ARCACHE */\r
 197                     _UDWORD :4;                 /*              */\r
 198                     } BIT;                      /*              */\r
 199              } AXIBUSCTL8;                      /*              */\r
 200        union {                                  /* AXIBUSCTL9   */\r
 201        _UDWORD LONG;                            /*  Long Access */\r
 202              struct {                           /*  Bit Access  */\r
 203                     _UDWORD VDC513AWCACHE:4;    /*   VDC513AWCACHE */\r
 204                     _UDWORD :4;                 /*              */\r
 205                     _UDWORD VDC513ARCACHE:4;    /*   VDC513ARCACHE */\r
 206                     _UDWORD :12;                /*              */\r
 207                     _UDWORD VDC512ARCACHE:4;    /*   VDC512ARCACHE */\r
 208                     _UDWORD :4;                 /*              */\r
 209                     } BIT;                      /*              */\r
 210              } AXIBUSCTL9;                      /*              */\r
 211        union {                                  /* AXIBUSCTL10  */\r
 212        _UDWORD LONG;                            /*  Long Access */\r
 213              struct {                           /*  Bit Access  */\r
 214                     _UDWORD VDC515AWCACHE:4;    /*   VDC515AWCACHE */\r
 215                     _UDWORD :4;                 /*              */\r
 216                     _UDWORD VDC515ARCACHE:4;    /*   VDC515ARCACHE */\r
 217                     _UDWORD :12;                /*              */\r
 218                     _UDWORD VDC514ARCACHE:4;    /*   VDC514ARCACHE */\r
 219                     _UDWORD :4;                 /*              */\r
 220                     } BIT;                      /*              */\r
 221              } AXIBUSCTL10;                     /*              */\r
 222        union {                                  /* AXIRERRCTL0  */\r
 223        _UDWORD LONG;                            /*  Long Access */\r
 224              struct {                           /*  Bit Access  */\r
 225                     _UDWORD :8;                 /*              */\r
 226                     _UDWORD CEURERREN:1;        /*   CEURERREN  */\r
 227                     _UDWORD :3;                 /*              */\r
 228                     _UDWORD IMRDRERREN:1;       /*   IMRDRERREN */\r
 229                     _UDWORD :3;                 /*              */\r
 230                     _UDWORD IMR21RERREN:1;      /*   IMR21RERREN */\r
 231                     _UDWORD :3;                 /*              */\r
 232                     _UDWORD IMR20RERREN:1;      /*   IMR20RERREN */\r
 233                     _UDWORD :3;                 /*              */\r
 234                     _UDWORD ETHRERREN:1;        /*   ETHRERREN  */\r
 235                     _UDWORD :3;                 /*              */\r
 236                     _UDWORD JCURERREN:1;        /*   JCURERREN  */\r
 237                     _UDWORD :3;                 /*              */\r
 238                     } BIT;                      /*              */\r
 239              } AXIRERRCTL0;                     /*              */\r
 240        union {                                  /* AXIRERRCTL1  */\r
 241        _UDWORD LONG;                            /*  Long Access */\r
 242              struct {                           /*  Bit Access  */\r
 243                     _UDWORD :12;                /*              */\r
 244                     _UDWORD RGP1281RERREN:1;    /*   RGP1281RERREN */\r
 245                     _UDWORD :3;                 /*              */\r
 246                     _UDWORD RGP1280RERREN:1;    /*   RGP1280RERREN */\r
 247                     _UDWORD :3;                 /*              */\r
 248                     _UDWORD RGP642RERREN:1;     /*   RGP642RERREN */\r
 249                     _UDWORD :3;                 /*              */\r
 250                     _UDWORD RGP641RERREN:1;     /*   RGP641RERREN */\r
 251                     _UDWORD :3;                 /*              */\r
 252                     _UDWORD RGP640RERREN:1;     /*   RGP640RERREN */\r
 253                     _UDWORD :3;                 /*              */\r
 254                     } BIT;                      /*              */\r
 255              } AXIRERRCTL1;                     /*              */\r
 256        union {                                  /* AXIRERRCTL2  */\r
 257        _UDWORD LONG;                            /*  Long Access */\r
 258              struct {                           /*  Bit Access  */\r
 259                     _UDWORD :12;                /*              */\r
 260                     _UDWORD VDC505RERREN:1;     /*   VDC505RERREN */\r
 261                     _UDWORD :3;                 /*              */\r
 262                     _UDWORD VDC504RERREN:1;     /*   VDC504RERREN */\r
 263                     _UDWORD :3;                 /*              */\r
 264                     _UDWORD VDC503RERREN:1;     /*   VDC503RERREN */\r
 265                     _UDWORD :3;                 /*              */\r
 266                     _UDWORD VDC502RERREN:1;     /*   VDC502RERREN */\r
 267                     _UDWORD :3;                 /*              */\r
 268                     _UDWORD VDC501RERREN:1;     /*   VDC501RERREN */\r
 269                     _UDWORD :3;                 /*              */\r
 270                     } BIT;                      /*              */\r
 271              } AXIRERRCTL2;                     /*              */\r
 272        union {                                  /* AXIRERRCTL3  */\r
 273        _UDWORD LONG;                            /*  Long Access */\r
 274              struct {                           /*  Bit Access  */\r
 275                     _UDWORD :12;                /*              */\r
 276                     _UDWORD VDC515RERREN:1;     /*   VDC515RERREN */\r
 277                     _UDWORD :3;                 /*              */\r
 278                     _UDWORD VDC514RERREN:1;     /*   VDC514RERREN */\r
 279                     _UDWORD :3;                 /*              */\r
 280                     _UDWORD VDC513RERREN:1;     /*   VDC513RERREN */\r
 281                     _UDWORD :3;                 /*              */\r
 282                     _UDWORD VDC512RERREN:1;     /*   VDC512RERREN */\r
 283                     _UDWORD :3;                 /*              */\r
 284                     _UDWORD VDC511RERREN:1;     /*   VDC511RERREN */\r
 285                     _UDWORD :3;                 /*              */\r
 286                     } BIT;                      /*              */\r
 287              } AXIRERRCTL3;                     /*              */\r
 288        union {                                  /* AXIRERRST0   */\r
 289        _UDWORD LONG;                            /*  Long Access */\r
 290              struct {                           /*  Bit Access  */\r
 291                     _UDWORD :8;                 /*              */\r
 292                     _UDWORD CEUBRESP:2;         /*   CEUBRESP   */\r
 293                     _UDWORD CEURRESP:2;         /*   CEURRESP   */\r
 294                     _UDWORD IMRDBRESP:2;        /*   IMRDBRESP  */\r
 295                     _UDWORD IMRDRRESP:2;        /*   IMRDRRESP  */\r
 296                     _UDWORD IMR21BRESP:2;       /*   IMR21BRESP */\r
 297                     _UDWORD IMR21RRESP:2;       /*   IMR21RRESP */\r
 298                     _UDWORD IMR20BRESP:2;       /*   IMR20BRESP */\r
 299                     _UDWORD IMR20RRESP:2;       /*   IMR20RRESP */\r
 300                     _UDWORD ETHBRESP:2;         /*   ETHBRESP   */\r
 301                     _UDWORD ETHRRESP:2;         /*   ETHRRESP   */\r
 302                     _UDWORD JCUBRESP:2;         /*   JCUBRESP   */\r
 303                     _UDWORD JCURRESP:2;         /*   JCURRESP   */\r
 304                     } BIT;                      /*              */\r
 305              } AXIRERRST0;                      /*              */\r
 306        union {                                  /* AXIRERRST1   */\r
 307        _UDWORD LONG;                            /*  Long Access */\r
 308              struct {                           /*  Bit Access  */\r
 309                     _UDWORD :12;                /*              */\r
 310                     _UDWORD RGP1281BRESP:2;     /*   RGP1281BRESP */\r
 311                     _UDWORD RGP1281RRESP:2;     /*   RGP1281RRESP */\r
 312                     _UDWORD RGP1280BRESP:2;     /*   RGP1280BRESP */\r
 313                     _UDWORD RGP1280RRESP:2;     /*   RGP1280RRESP */\r
 314                     _UDWORD RGP642BRESP:2;      /*   RGP642BRESP */\r
 315                     _UDWORD RGP642RRESP:2;      /*   RGP642RRESP */\r
 316                     _UDWORD RGP641BRESP:2;      /*   RGP641BRESP */\r
 317                     _UDWORD RGP641RRESP:2;      /*   RGP641RRESP */\r
 318                     _UDWORD RGP640BRESP:2;      /*   RGP640BRESP */\r
 319                     _UDWORD RGP640RRESP:2;      /*   RGP640RRESP */\r
 320                     } BIT;                      /*              */\r
 321              } AXIRERRST1;                      /*              */\r
 322        union {                                  /* AXIRERRST2   */\r
 323        _UDWORD LONG;                            /*  Long Access */\r
 324              struct {                           /*  Bit Access  */\r
 325                     _UDWORD :12;                /*              */\r
 326                     _UDWORD VDC505BRESP:2;      /*   VDC505BRESP */\r
 327                     _UDWORD VDC505RRESP:2;      /*   VDC505RRESP */\r
 328                     _UDWORD VDC504BRESP:2;      /*   VDC504BRESP */\r
 329                     _UDWORD VDC504RRESP:2;      /*   VDC504RRESP */\r
 330                     _UDWORD VDC503BRESP:2;      /*   VDC503BRESP */\r
 331                     _UDWORD VDC503RRESP:2;      /*   VDC503RRESP */\r
 332                     _UDWORD VDC502BRESP:2;      /*   VDC502BRESP */\r
 333                     _UDWORD VDC502RRESP:2;      /*   VDC502RRESP */\r
 334                     _UDWORD VDC501BRESP:2;      /*   VDC501BRESP */\r
 335                     _UDWORD VDC501RRESP:2;      /*   VDC501RRESP */\r
 336                     } BIT;                      /*              */\r
 337              } AXIRERRST2;                      /*              */\r
 338        union {                                  /* AXIRERRST3   */\r
 339        _UDWORD LONG;                            /*  Long Access */\r
 340              struct {                           /*  Bit Access  */\r
 341                     _UDWORD :12;                /*              */\r
 342                     _UDWORD VDC515BRESP:2;      /*   VDC515BRESP */\r
 343                     _UDWORD VDC515RRESP:2;      /*   VDC515RRESP */\r
 344                     _UDWORD VDC514BRESP:2;      /*   VDC514BRESP */\r
 345                     _UDWORD VDC514RRESP:2;      /*   VDC514RRESP */\r
 346                     _UDWORD VDC513BRESP:2;      /*   VDC513BRESP */\r
 347                     _UDWORD VDC513RRESP:2;      /*   VDC513RRESP */\r
 348                     _UDWORD VDC512BRESP:2;      /*   VDC512BRESP */\r
 349                     _UDWORD VDC512RRESP:2;      /*   VDC512RRESP */\r
 350                     _UDWORD VDC511BRESP:2;      /*   VDC511BRESP */\r
 351                     _UDWORD VDC511RRESP:2;      /*   VDC511RRESP */\r
 352                     } BIT;                      /*              */\r
 353              } AXIRERRST3;                      /*              */\r
 354        union {                                  /* AXIRERRCLR0  */\r
 355        _UDWORD LONG;                            /*  Long Access */\r
 356              struct {                           /*  Bit Access  */\r
 357                     _UDWORD :8;                 /*              */\r
 358                     _UDWORD CEUBRESPCLR:1;      /*   CEUBRESPCLR */\r
 359                     _UDWORD :1;                 /*              */\r
 360                     _UDWORD CEURRESPCLR:1;      /*   CEURRESPCLR */\r
 361                     _UDWORD :1;                 /*              */\r
 362                     _UDWORD IMRDBRESPCLR:1;     /*   IMRDBRESPCLR */\r
 363                     _UDWORD :1;                 /*              */\r
 364                     _UDWORD IMRDRRESPCLR:1;     /*   IMRDRRESPCLR */\r
 365                     _UDWORD :1;                 /*              */\r
 366                     _UDWORD IMR21BRESPCLR:1;    /*   IMR21BRESPCLR */\r
 367                     _UDWORD :1;                 /*              */\r
 368                     _UDWORD IMR21RRESPCLR:1;    /*   IMR21RRESPCLR */\r
 369                     _UDWORD :1;                 /*              */\r
 370                     _UDWORD IMR20BRESPCLR:1;    /*   IMR20BRESPCLR */\r
 371                     _UDWORD :1;                 /*              */\r
 372                     _UDWORD IMR20RRESPCLR:1;    /*   IMR20RRESPCLR */\r
 373                     _UDWORD :1;                 /*              */\r
 374                     _UDWORD ETHBRESPCLR:1;      /*   ETHBRESPCLR */\r
 375                     _UDWORD :1;                 /*              */\r
 376                     _UDWORD ETHRRESPCLR:1;      /*   ETHRRESPCLR */\r
 377                     _UDWORD :1;                 /*              */\r
 378                     _UDWORD JCUBRESPCLR:1;      /*   JCUBRESPCLR */\r
 379                     _UDWORD :1;                 /*              */\r
 380                     _UDWORD JCURRESPCLR:1;      /*   JCURRESPCLR */\r
 381                     _UDWORD :1;                 /*              */\r
 382                     } BIT;                      /*              */\r
 383              } AXIRERRCLR0;                     /*              */\r
 384        union {                                  /* AXIRERRCLR1  */\r
 385        _UDWORD LONG;                            /*  Long Access */\r
 386              struct {                           /*  Bit Access  */\r
 387                     _UDWORD :12;                /*              */\r
 388                     _UDWORD RGP1281BRESPCLR:1;  /*   RGP1281BRESPCLR */\r
 389                     _UDWORD :1;                 /*              */\r
 390                     _UDWORD RGP1281RRESPCLR:1;  /*   RGP1281RRESPCLR */\r
 391                     _UDWORD :1;                 /*              */\r
 392                     _UDWORD RGP1280BRESPCLR:1;  /*   RGP1280BRESPCLR */\r
 393                     _UDWORD :1;                 /*              */\r
 394                     _UDWORD RGP1280RRESPCLR:1;  /*   RGP1280RRESPCLR */\r
 395                     _UDWORD :1;                 /*              */\r
 396                     _UDWORD RGP642BRESPCLR:1;   /*   RGP642BRESPCLR */\r
 397                     _UDWORD :1;                 /*              */\r
 398                     _UDWORD RGP642RRESPCLR:1;   /*   RGP642RRESPCLR */\r
 399                     _UDWORD :1;                 /*              */\r
 400                     _UDWORD RGP641BRESPCLR:1;   /*   RGP641BRESPCLR */\r
 401                     _UDWORD :1;                 /*              */\r
 402                     _UDWORD RGP641RRESPCLR:1;   /*   RGP641RRESPCLR */\r
 403                     _UDWORD :1;                 /*              */\r
 404                     _UDWORD RGP640BRESPCLR:1;   /*   RGP640BRESPCLR */\r
 405                     _UDWORD :1;                 /*              */\r
 406                     _UDWORD RGP640RRESPCLR:1;   /*   RGP640RRESPCLR */\r
 407                     _UDWORD :1;                 /*              */\r
 408                     } BIT;                      /*              */\r
 409              } AXIRERRCLR1;                     /*              */\r
 410        union {                                  /* AXIRERRCLR2  */\r
 411        _UDWORD LONG;                            /*  Long Access */\r
 412              struct {                           /*  Bit Access  */\r
 413                     _UDWORD :12;                /*              */\r
 414                     _UDWORD VDC505BRESPCLR:1;   /*   VDC505BRESPCLR */\r
 415                     _UDWORD :1;                 /*              */\r
 416                     _UDWORD VDC505RRESPCLR:1;   /*   VDC505RRESPCLR */\r
 417                     _UDWORD :1;                 /*              */\r
 418                     _UDWORD VDC504BRESPCLR:1;   /*   VDC504BRESPCLR */\r
 419                     _UDWORD :1;                 /*              */\r
 420                     _UDWORD VDC504RRESPCLR:1;   /*   VDC504RRESPCLR */\r
 421                     _UDWORD :1;                 /*              */\r
 422                     _UDWORD VDC503BRESPCLR:1;   /*   VDC503BRESPCLR */\r
 423                     _UDWORD :1;                 /*              */\r
 424                     _UDWORD VDC503RRESPCLR:1;   /*   VDC503RRESPCLR */\r
 425                     _UDWORD :1;                 /*              */\r
 426                     _UDWORD VDC502BRESPCLR:1;   /*   VDC502BRESPCLR */\r
 427                     _UDWORD :1;                 /*              */\r
 428                     _UDWORD VDC502RRESPCLR:1;   /*   VDC502RRESPCLR */\r
 429                     _UDWORD :1;                 /*              */\r
 430                     _UDWORD VDC501BRESPCLR:1;   /*   VDC501BRESPCLR */\r
 431                     _UDWORD :1;                 /*              */\r
 432                     _UDWORD VDC501RRESPCLR:1;   /*   VDC501RRESPCLR */\r
 433                     _UDWORD :1;                 /*              */\r
 434                     } BIT;                      /*              */\r
 435              } AXIRERRCLR2;                     /*              */\r
 436        union {                                  /* AXIRERRCLR3  */\r
 437        _UDWORD LONG;                            /*  Long Access */\r
 438              struct {                           /*  Bit Access  */\r
 439                     _UDWORD :12;                /*              */\r
 440                     _UDWORD VDC515BRESPCLR:1;   /*   VDC515BRESPCLR */\r
 441                     _UDWORD :1;                 /*              */\r
 442                     _UDWORD VDC515RRESPCLR:1;   /*   VDC515RRESPCLR */\r
 443                     _UDWORD :1;                 /*              */\r
 444                     _UDWORD VDC514BRESPCLR:1;   /*   VDC514BRESPCLR */\r
 445                     _UDWORD :1;                 /*              */\r
 446                     _UDWORD VDC514RRESPCLR:1;   /*   VDC514RRESPCLR */\r
 447                     _UDWORD :1;                 /*              */\r
 448                     _UDWORD VDC513BRESPCLR:1;   /*   VDC513BRESPCLR */\r
 449                     _UDWORD :1;                 /*              */\r
 450                     _UDWORD VDC513RRESPCLR:1;   /*   VDC513RRESPCLR */\r
 451                     _UDWORD :1;                 /*              */\r
 452                     _UDWORD VDC512BRESPCLR:1;   /*   VDC512BRESPCLR */\r
 453                     _UDWORD :1;                 /*              */\r
 454                     _UDWORD VDC512RRESPCLR:1;   /*   VDC512RRESPCLR */\r
 455                     _UDWORD :1;                 /*              */\r
 456                     _UDWORD VDC511BRESPCLR:1;   /*   VDC511BRESPCLR */\r
 457                     _UDWORD :1;                 /*              */\r
 458                     _UDWORD VDC511RRESPCLR:1;   /*   VDC511RRESPCLR */\r
 459                     _UDWORD :1;                 /*              */\r
 460                     } BIT;                      /*              */\r
 461              } AXIRERRCLR3;                     /*              */\r
 462 };                                              /*              */\r
 463 \r
 464 #define PRR             (*(volatile struct st_prr *)0xFCFE1800)   /* PRR Address */\r
 465 \r
 466 \r
 467 #endif /* __PRR_IODEFINE_H__ */\r
 468 \r
 469 /* End of File */\r