git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/IntQueueTimer.c

   1 /*\r
   2     FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     ***************************************************************************\r
   8      *                                                                       *\r
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  14      *    project by purchasing a FreeRTOS tutorial book, reference          *\r
  15      *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
  16      *                                                                       *\r
  17      *    Thank you!                                                         *\r
  18      *                                                                       *\r
  19     ***************************************************************************\r
  20 \r
  21     This file is part of the FreeRTOS distribution.\r
  22 \r
  23     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  24     the terms of the GNU General Public License (version 2) as published by the\r
  25     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  26 \r
  27     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
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  29     >>!   obliged to provide the source code for proprietary components     !<<\r
  30     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  31 \r
  32     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  33     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  34     FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
  35     link: http://www.freertos.org/a00114.html\r
  36 \r
  37     1 tab == 4 spaces!\r
  38 \r
  39     ***************************************************************************\r
  40      *                                                                       *\r
  41      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  42      *    not run, what could be wrong?"                                     *\r
  43      *                                                                       *\r
  44      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  45      *                                                                       *\r
  46     ***************************************************************************\r
  47 \r
  48     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  49     license and Real Time Engineers Ltd. contact details.\r
  50 \r
  51     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  52     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  53     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  54 \r
  55     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  56     Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  57     licenses offer ticketed support, indemnification and middleware.\r
  58 \r
  59     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  60     engineered and independently SIL3 certified version for use in safety and\r
  61     mission critical applications that require provable dependability.\r
  62 \r
  63     1 tab == 4 spaces!\r
  64 */\r
  65 \r
  66 /*\r
  67  * This file initialises three timers as follows:\r
  68  *\r
  69  * Timer 0 and Timer 1 provide the interrupts that are used with the IntQ\r
  70  * standard demo tasks, which test interrupt nesting and using queues from\r
  71  * interrupts.  Both these interrupts operate below the maximum syscall\r
  72  * interrupt priority.\r
  73  *\r
  74  * Timer 2 is a much higher frequency timer that tests the nesting of interrupts\r
  75  * that execute above the maximum syscall interrupt priority.\r
  76  *\r
  77  * All the timers can nest with the tick interrupt - creating a maximum\r
  78  * interrupt nesting depth of 4.\r
  79  *\r
  80  * For convenience, the high frequency timer is also used to provide the time\r
  81  * base for the run time stats.\r
  82  */\r
  83 \r
  84 /* Scheduler includes. */\r
  85 #include "FreeRTOS.h"\r
  86 \r
  87 /* Demo includes. */\r
  88 #include "IntQueueTimer.h"\r
  89 #include "IntQueue.h"\r
  90 \r
  91 /* Xilinx includes. */\r
  92 #include "xttcps.h"\r
  93 #include "xscugic.h"\r
  94 \r
  95 /* The frequencies at which the first two timers expire are slightly offset to\r
  96 ensure they don't remain synchronised.  The frequency of the interrupt that\r
  97 operates above the max syscall interrupt priority is 10 times faster so really\r
  98 hammers the interrupt entry and exit code. */\r
  99 #define tmrTIMERS_USED  3\r
 100 #define tmrTIMER_0_FREQUENCY    ( 2000UL )\r
 101 #define tmrTIMER_1_FREQUENCY    ( 2001UL )\r
 102 #define tmrTIMER_2_FREQUENCY    ( 20000UL )\r
 103 \r
 104 /*-----------------------------------------------------------*/\r
 105 \r
 106 /*\r
 107  * The single interrupt service routines that is used to service all three\r
 108  * timers.\r
 109  */\r
 110 static void prvTimerHandler( void *CallBackRef );\r
 111 \r
 112 /*-----------------------------------------------------------*/\r
 113 \r
 114 /* Hardware constants. */\r
 115 static const BaseType_t xDeviceIDs[ tmrTIMERS_USED ] = { XPAR_XTTCPS_0_DEVICE_ID, XPAR_XTTCPS_1_DEVICE_ID, XPAR_XTTCPS_2_DEVICE_ID };\r
 116 static const BaseType_t xInterruptIDs[ tmrTIMERS_USED ] = { XPAR_XTTCPS_0_INTR, XPAR_XTTCPS_1_INTR, XPAR_XTTCPS_2_INTR };\r
 117 \r
 118 /* Timer configuration settings. */\r
 119 typedef struct\r
 120 {\r
 121         uint32_t OutputHz;      /* Output frequency. */\r
 122         uint16_t Interval;      /* Interval value. */\r
 123         uint8_t Prescaler;      /* Prescaler value. */\r
 124         uint16_t Options;       /* Option settings. */\r
 125 } TmrCntrSetup;\r
 126 \r
 127 static TmrCntrSetup xTimerSettings[ tmrTIMERS_USED ] =\r
 128 {\r
 129         { tmrTIMER_0_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE },\r
 130         { tmrTIMER_1_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE },\r
 131         { tmrTIMER_2_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE }\r
 132 };\r
 133 \r
 134 /* Lower priority number means higher logical priority, so\r
 135 configMAX_API_CALL_INTERRUPT_PRIORITY - 1 is above the maximum system call\r
 136 interrupt priority. */\r
 137 static const UBaseType_t uxInterruptPriorities[ tmrTIMERS_USED ] =\r
 138 {\r
 139         configMAX_API_CALL_INTERRUPT_PRIORITY + 1,\r
 140         configMAX_API_CALL_INTERRUPT_PRIORITY,\r
 141         configMAX_API_CALL_INTERRUPT_PRIORITY - 1\r
 142 };\r
 143 \r
 144 static XTtcPs xTimerInstances[ tmrTIMERS_USED ];\r
 145 \r
 146 /* Used to provide a means of ensuring the intended interrupt nesting depth is\r
 147 actually being reached. */\r
 148 extern uint32_t ulPortInterruptNesting;\r
 149 static uint32_t ulMaxRecordedNesting = 0;\r
 150 \r
 151 /* Used to ensure the high frequency timer is running at the expected\r
 152 frequency. */\r
 153 static volatile uint32_t ulHighFrequencyTimerCounts = 0;\r
 154 \r
 155 /*-----------------------------------------------------------*/\r
 156 \r
 157 void vInitialiseTimerForIntQueueTest( void )\r
 158 {\r
 159 BaseType_t xStatus;\r
 160 TmrCntrSetup *pxTimerSettings;\r
 161 extern XScuGic xInterruptController;\r
 162 BaseType_t xTimer;\r
 163 XTtcPs *pxTimerInstance;\r
 164 XTtcPs_Config *pxTimerConfiguration;\r
 165 const uint8_t ucRisingEdge = 3;\r
 166 \r
 167         for( xTimer = 0; xTimer < tmrTIMERS_USED; xTimer++ )\r
 168         {\r
 169                 /* Look up the timer's configuration. */\r
 170                 pxTimerInstance = &( xTimerInstances[ xTimer ] );\r
 171                 pxTimerConfiguration = XTtcPs_LookupConfig( xDeviceIDs[ xTimer ] );\r
 172                 configASSERT( pxTimerConfiguration );\r
 173 \r
 174                 pxTimerSettings = &( xTimerSettings[ xTimer ] );\r
 175 \r
 176                 /* Initialise the device. */\r
 177                 xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );\r
 178                 if( xStatus != XST_SUCCESS )\r
 179                 {\r
 180                         /* Not sure how to do this before XTtcPs_CfgInitialize is called\r
 181                         as pxTimerInstance is set within XTtcPs_CfgInitialize(). */\r
 182                         XTtcPs_Stop( pxTimerInstance );\r
 183                         xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );\r
 184                         configASSERT( xStatus == XST_SUCCESS );\r
 185                 }\r
 186 \r
 187                 /* Set the options. */\r
 188                 XTtcPs_SetOptions( pxTimerInstance, pxTimerSettings->Options );\r
 189 \r
 190                 /* The timer frequency is preset in the pxTimerSettings structure.\r
 191                 Derive the values for the other structure members. */\r
 192                 XTtcPs_CalcIntervalFromFreq( pxTimerInstance, pxTimerSettings->OutputHz, &( pxTimerSettings->Interval ), &( pxTimerSettings->Prescaler ) );\r
 193 \r
 194                 /* Set the interval and prescale. */\r
 195                 XTtcPs_SetInterval( pxTimerInstance, pxTimerSettings->Interval );\r
 196                 XTtcPs_SetPrescaler( pxTimerInstance, pxTimerSettings->Prescaler );\r
 197 \r
 198                 /* The priority must be the lowest possible. */\r
 199                 XScuGic_SetPriorityTriggerType( &xInterruptController, xInterruptIDs[ xTimer ], uxInterruptPriorities[ xTimer ] << portPRIORITY_SHIFT, ucRisingEdge );\r
 200 \r
 201                 /* Connect to the interrupt controller. */\r
 202                 xStatus = XScuGic_Connect( &xInterruptController, xInterruptIDs[ xTimer ], ( Xil_InterruptHandler ) prvTimerHandler, ( void * ) pxTimerInstance );\r
 203                 configASSERT( xStatus == XST_SUCCESS);\r
 204 \r
 205                 /* Enable the interrupt in the GIC. */\r
 206                 XScuGic_Enable( &xInterruptController, xInterruptIDs[ xTimer ] );\r
 207 \r
 208                 /* Enable the interrupts in the timer. */\r
 209                 XTtcPs_EnableInterrupts( pxTimerInstance, XTTCPS_IXR_INTERVAL_MASK );\r
 210 \r
 211                 /* Start the timer. */\r
 212                 XTtcPs_Start( pxTimerInstance );\r
 213         }\r
 214 }\r
 215 /*-----------------------------------------------------------*/\r
 216 \r
 217 static void prvTimerHandler( void *pvCallBackRef )\r
 218 {\r
 219 uint32_t ulInterruptStatus;\r
 220 XTtcPs *pxTimer = ( XTtcPs * ) pvCallBackRef;\r
 221 BaseType_t xYieldRequired;\r
 222 \r
 223         /* Read the interrupt status, then write it back to clear the interrupt. */\r
 224         ulInterruptStatus = XTtcPs_GetInterruptStatus( pxTimer );\r
 225         XTtcPs_ClearInterruptStatus( pxTimer, ulInterruptStatus );\r
 226 \r
 227         /* Only one interrupt event type is expected. */\r
 228         configASSERT( ( XTTCPS_IXR_INTERVAL_MASK & ulInterruptStatus ) != 0 );\r
 229 \r
 230         /* Check the device ID to know which IntQueue demo to call. */\r
 231         if( pxTimer->Config.DeviceId == xDeviceIDs[ 0 ] )\r
 232         {\r
 233                 xYieldRequired = xFirstTimerHandler();\r
 234         }\r
 235         else if( pxTimer->Config.DeviceId == xDeviceIDs[ 1 ] )\r
 236         {\r
 237                 xYieldRequired = xSecondTimerHandler();\r
 238         }\r
 239         else\r
 240         {\r
 241                 /* Used to check the timer is running at the expected frequency. */\r
 242                 ulHighFrequencyTimerCounts++;\r
 243 \r
 244                 /* Latch the highest interrupt nesting count detected. */\r
 245                 if( ulPortInterruptNesting > ulMaxRecordedNesting )\r
 246                 {\r
 247                         ulMaxRecordedNesting = ulPortInterruptNesting;\r
 248                 }\r
 249 \r
 250                 xYieldRequired = pdFALSE;\r
 251         }\r
 252 \r
 253         /* If xYieldRequired is not pdFALSE then calling either xFirstTimerHandler()\r
 254         or xSecondTimerHandler() resulted in a task leaving the blocked state and\r
 255         the task that left the blocked state had a priority higher than the currently\r
 256         running task (the task this interrupt interrupted) - so a context switch\r
 257         should be performed so the interrupt returns directly to the higher priority\r
 258         task.  xYieldRequired is tested inside the following macro. */\r
 259         portYIELD_FROM_ISR( xYieldRequired );\r
 260 }\r
 261 \r