1 /*******************************************************************/
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3 /* This file is automatically generated by linker script generator.*/
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7 /* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */
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9 /* Description : Cortex-A9 Linker Script */
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11 /*******************************************************************/
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13 _STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
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14 _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
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16 _ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
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17 _SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
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18 _FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
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19 _UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
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21 /* Define Memories in the system */
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25 ps7_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x00100000, LENGTH = 0x1FF00000
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26 ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00030000
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27 ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00
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30 /* Specify the default entry point to the program */
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32 ENTRY(_freertos_vector_table)
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34 /* Define the sections, and where they are mapped in memory */
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39 *(.freertos_vectors)
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44 *(.gnu.linkonce.t.*)
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47 *(.gcc_execpt_table)
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52 *(.gnu.linkonce.armextab.*)
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53 } > ps7_ddr_0_S_AXI_BASEADDR
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57 } > ps7_ddr_0_S_AXI_BASEADDR
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61 } > ps7_ddr_0_S_AXI_BASEADDR
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67 *(.gnu.linkonce.r.*)
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69 } > ps7_ddr_0_S_AXI_BASEADDR
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72 __rodata1_start = .;
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76 } > ps7_ddr_0_S_AXI_BASEADDR
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82 *(.gnu.linkonce.s2.*)
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84 } > ps7_ddr_0_S_AXI_BASEADDR
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90 *(.gnu.linkonce.sb2.*)
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92 } > ps7_ddr_0_S_AXI_BASEADDR
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98 *(.gnu.linkonce.d.*)
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103 } > ps7_ddr_0_S_AXI_BASEADDR
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110 } > ps7_ddr_0_S_AXI_BASEADDR
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114 } > ps7_ddr_0_S_AXI_BASEADDR
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118 ___CTORS_LIST___ = .;
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119 KEEP (*crtbegin.o(.ctors))
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120 KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
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121 KEEP (*(SORT(.ctors.*)))
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124 ___CTORS_END___ = .;
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125 } > ps7_ddr_0_S_AXI_BASEADDR
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129 ___DTORS_LIST___ = .;
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130 KEEP (*crtbegin.o(.dtors))
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131 KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
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132 KEEP (*(SORT(.dtors.*)))
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135 ___DTORS_END___ = .;
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136 } > ps7_ddr_0_S_AXI_BASEADDR
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142 } > ps7_ddr_0_S_AXI_BASEADDR
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146 } > ps7_ddr_0_S_AXI_BASEADDR
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149 __eh_framehdr_start = .;
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151 __eh_framehdr_end = .;
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152 } > ps7_ddr_0_S_AXI_BASEADDR
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154 .gcc_except_table : {
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155 *(.gcc_except_table)
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156 } > ps7_ddr_0_S_AXI_BASEADDR
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158 .mmu_tbl (ALIGN(16384)) : {
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159 __mmu_tbl_start = .;
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162 } > ps7_ddr_0_S_AXI_BASEADDR
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167 *(.gnu.linkonce.armexidix.*.*)
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169 } > ps7_ddr_0_S_AXI_BASEADDR
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172 __preinit_array_start = .;
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173 KEEP (*(SORT(.preinit_array.*)))
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174 KEEP (*(.preinit_array))
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175 __preinit_array_end = .;
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176 } > ps7_ddr_0_S_AXI_BASEADDR
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179 __init_array_start = .;
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180 KEEP (*(SORT(.init_array.*)))
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181 KEEP (*(.init_array))
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182 __init_array_end = .;
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183 } > ps7_ddr_0_S_AXI_BASEADDR
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186 __fini_array_start = .;
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187 KEEP (*(SORT(.fini_array.*)))
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188 KEEP (*(.fini_array))
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189 __fini_array_end = .;
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190 } > ps7_ddr_0_S_AXI_BASEADDR
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192 .ARM.attributes : {
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193 __ARM.attributes_start = .;
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195 __ARM.attributes_end = .;
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196 } > ps7_ddr_0_S_AXI_BASEADDR
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202 *(.gnu.linkonce.s.*)
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204 } > ps7_ddr_0_S_AXI_BASEADDR
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210 *(.gnu.linkonce.sb.*)
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212 } > ps7_ddr_0_S_AXI_BASEADDR
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218 *(.gnu.linkonce.td.*)
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220 } > ps7_ddr_0_S_AXI_BASEADDR
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226 *(.gnu.linkonce.tb.*)
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228 } > ps7_ddr_0_S_AXI_BASEADDR
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234 *(.gnu.linkonce.b.*)
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237 } > ps7_ddr_0_S_AXI_BASEADDR
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239 _SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
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241 _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
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243 /* Generate Stack and Heap definitions */
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253 } > ps7_ddr_0_S_AXI_BASEADDR
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255 .stack (NOLOAD) : {
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262 _irq_stack_end = .;
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265 _supervisor_stack_end = .;
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266 . += _SUPERVISOR_STACK_SIZE;
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268 __supervisor_stack = .;
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269 _abort_stack_end = .;
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270 . += _ABORT_STACK_SIZE;
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273 _fiq_stack_end = .;
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274 . += _FIQ_STACK_SIZE;
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277 _undef_stack_end = .;
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278 . += _UNDEF_STACK_SIZE;
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281 } > ps7_ddr_0_S_AXI_BASEADDR
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