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40 ******************************************************************************/
41 /*****************************************************************************/
46 * MODIFICATION HISTORY:
48 * Ver Who Date Changes
49 * ----- ---- -------- ---------------------------------------------------
50 * 1.00a sdm 11/03/09 Initial release.
55 ******************************************************************************/
57 #ifndef SMC_H /* prevent circular inclusions */
58 #define SMC_H /* by using protection macros */
64 /***************************** Include Files *********************************/
66 #include "xparameters.h"
69 /***************** Macros (Inline Functions) Definitions *********************/
71 /**************************** Type Definitions *******************************/
73 /************************** Constant Definitions *****************************/
75 /* Memory controller configuration register offset */
76 #define XSMCPSS_MC_STATUS 0x000 /* Controller status reg, RO */
77 #define XSMCPSS_MC_INTERFACE_CONFIG 0x004 /* Interface config reg, RO */
78 #define XSMCPSS_MC_SET_CONFIG 0x008 /* Set configuration reg, WO */
79 #define XSMCPSS_MC_CLR_CONFIG 0x00C /* Clear config reg, WO */
80 #define XSMCPSS_MC_DIRECT_CMD 0x010 /* Direct command reg, WO */
81 #define XSMCPSS_MC_SET_CYCLES 0x014 /* Set cycles register, WO */
82 #define XSMCPSS_MC_SET_OPMODE 0x018 /* Set opmode register, WO */
83 #define XSMCPSS_MC_REFRESH_PERIOD_0 0x020 /* Refresh period_0 reg, RW */
84 #define XSMCPSS_MC_REFRESH_PERIOD_1 0x024 /* Refresh period_1 reg, RW */
86 /* Chip select configuration register offset */
87 #define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100 /* Interface 0 chip 0 config */
88 #define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120 /* Interface 0 chip 1 config */
89 #define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140 /* Interface 0 chip 2 config */
90 #define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160 /* Interface 0 chip 3 config */
91 #define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180 /* Interface 1 chip 0 config */
92 #define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0 /* Interface 1 chip 1 config */
93 #define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0 /* Interface 1 chip 2 config */
94 #define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0 /* Interface 1 chip 3 config */
96 /* User configuration register offset */
97 #define XSMCPSS_UC_STATUS_OFFSET 0x200 /* User status reg, RO */
98 #define XSMCPSS_UC_CONFIG_OFFSET 0x204 /* User config reg, WO */
100 /* Integration test register offset */
101 #define XSMCPSS_IT_OFFSET 0xE00
103 /* ID configuration register offset */
104 #define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0
105 #define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4
106 #define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8
107 #define XSMCPSS_ID_PERIP_3_OFFSET 0xFEC
108 #define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0
109 #define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4
110 #define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8
111 #define XSMCPSS_ID_PCELL_3_OFFSET 0xFFC
113 /************************** Variable Definitions *****************************/
115 /************************** Function Prototypes ******************************/
117 void XSmc_SramInit (void);
118 void XSmc_NorInit(void);
122 #endif /* __cplusplus */