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31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup gpiops_v2_1
40 * The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
43 * The GPIO Controller supports the following features:
45 * - Masked writes (There are no masked reads)
47 * - Configurable Interrupts (Level/Edge)
49 * This driver is intended to be RTOS and processor independent. Any needs for
50 * dynamic memory management, threads or thread mutual exclusion, virtual
51 * memory, or cache control must be satisfied by the layer above this driver.
53 * This driver supports all the features listed above, if applicable.
55 * <b>Driver Description</b>
57 * The device driver enables higher layer software (e.g., an application) to
58 * communicate to the GPIO.
62 * The driver provides interrupt management functions and an interrupt handler.
63 * Users of this driver need to provide callback functions. An interrupt handler
64 * example is available with the driver.
68 * This driver is not thread safe. Any needs for threads or thread mutual
69 * exclusion must be satisfied by the layer above this driver.
73 * Asserts are used within all Xilinx drivers to enforce constraints on argument
74 * values. Asserts can be turned off on a system-wide basis by defining, at
75 * compile time, the NDEBUG identifier. By default, asserts are turned on and it
76 * is recommended that users leave asserts on during development.
78 * <b>Building the driver</b>
80 * The XGpioPs driver is composed of several source files. This allows the user
81 * to build and link only those parts of the driver that are necessary.
85 * MODIFICATION HISTORY:
87 * Ver Who Date Changes
88 * ----- ---- -------- -----------------------------------------------
89 * 1.00a sv 01/15/10 First Release
90 * 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
91 * XGpioPs_GetMode, XGpioPs_GetModePin as they are not
92 * relevant to Zynq device.The interrupts are disabled
93 * for output pins on all banks during initialization.
94 * 1.02a hk 08/22/13 Added low level reset API
95 * 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
99 ******************************************************************************/
100 #ifndef XGPIOPS_H /* prevent circular inclusions */
101 #define XGPIOPS_H /* by using protection macros */
107 /***************************** Include Files *********************************/
110 #include "xgpiops_hw.h"
112 /************************** Constant Definitions *****************************/
114 /** @name Interrupt types
116 * The following constants define the interrupt types that can be set for each
119 #define XGPIOPS_IRQ_TYPE_EDGE_RISING 0 /**< Interrupt on Rising edge */
120 #define XGPIOPS_IRQ_TYPE_EDGE_FALLING 1 /**< Interrupt Falling edge */
121 #define XGPIOPS_IRQ_TYPE_EDGE_BOTH 2 /**< Interrupt on both edges */
122 #define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 3 /**< Interrupt on high level */
123 #define XGPIOPS_IRQ_TYPE_LEVEL_LOW 4 /**< Interrupt on low level */
126 #define XGPIOPS_BANK0 0 /**< GPIO Bank 0 */
127 #define XGPIOPS_BANK1 1 /**< GPIO Bank 1 */
128 #define XGPIOPS_BANK2 2 /**< GPIO Bank 2 */
129 #define XGPIOPS_BANK3 3 /**< GPIO Bank 3 */
131 #define XGPIOPS_MAX_BANKS 4 /**< Max banks in a GPIO device */
132 #define XGPIOPS_BANK_MAX_PINS 32 /**< Max pins in a GPIO bank */
134 #define XGPIOPS_DEVICE_MAX_PIN_NUM 118 /*< Max pins in the GPIO device
141 /**************************** Type Definitions *******************************/
143 /****************************************************************************/
145 * This handler data type allows the user to define a callback function to
146 * handle the interrupts for the GPIO device. The application using this
147 * driver is expected to define a handler of this type, to support interrupt
148 * driven mode. The handler executes in an interrupt context such that minimal
149 * processing should be performed.
151 * @param CallBackRef is a callback reference passed in by the upper layer
152 * when setting the callback functions for a GPIO bank. It is
153 * passed back to the upper layer when the callback is invoked. Its
154 * type is not important to the driver component, so it is a void
156 * @param Bank is the bank for which the interrupt status has changed.
157 * @param Status is the Interrupt status of the GPIO bank.
159 *****************************************************************************/
160 typedef void (*XGpioPs_Handler) (void *CallBackRef, int Bank, u32 Status);
163 * This typedef contains configuration information for a device.
166 u16 DeviceId; /**< Unique ID of device */
167 u32 BaseAddr; /**< Register base address */
171 * The XGpioPs driver instance data. The user is required to allocate a
172 * variable of this type for the GPIO device in the system. A pointer
173 * to a variable of this type is then passed to the driver API functions.
176 XGpioPs_Config GpioConfig; /**< Device configuration */
177 u32 IsReady; /**< Device is initialized and ready */
178 XGpioPs_Handler Handler; /**< Status handlers for all banks */
179 void *CallBackRef; /**< Callback ref for bank handlers */
182 /***************** Macros (Inline Functions) Definitions *********************/
184 /************************** Function Prototypes ******************************/
187 * Functions in xgpiops.c
189 int XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
193 * Bank APIs in xgpiops.c
195 u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
196 void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
197 void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
198 u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
199 void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 Enable);
200 u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
201 void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank);
204 * Pin APIs in xgpiops.c
206 int XGpioPs_ReadPin(XGpioPs *InstancePtr, int Pin);
207 void XGpioPs_WritePin(XGpioPs *InstancePtr, int Pin, int Data);
208 void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, int Pin, int Direction);
209 int XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, int Pin);
210 void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, int Pin, int Enable);
211 int XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, int Pin);
214 * Diagnostic functions in xgpiops_selftest.c
216 int XGpioPs_SelfTest(XGpioPs *InstancePtr);
219 * Functions in xgpiops_intr.c
222 * Bank APIs in xgpiops_intr.c
224 void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
225 void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
226 u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
227 u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
228 void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
229 void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
230 u32 IntrPolarity, u32 IntrOnAny);
231 void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
232 u32 *IntrPolarity, u32 *IntrOnAny);
233 void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
234 XGpioPs_Handler FuncPtr);
235 void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
238 * Pin APIs in xgpiops_intr.c
240 void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, int Pin, u8 IrqType);
241 u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, int Pin);
243 void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, int Pin);
244 void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, int Pin);
245 int XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, int Pin);
246 int XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, int Pin);
247 void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, int Pin);
250 * Functions in xgpiops_sinit.c
252 XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
258 #endif /* end of protection macro */