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40 ******************************************************************************/
41 /*****************************************************************************/
46 * The Xilinx CAN driver component. This component supports the Xilinx
49 * The CAN Controller supports the following features:
50 * - Confirms to the ISO 11898-1, CAN 2.0A and CAN 2.0B standards.
51 * - Supports both Standard (11 bit Identifier) and Extended (29 bit
53 * - Supports Bit Rates up to 1 Mbps.
54 * - Transmit message object FIFO with a user configurable depth of
55 * up to 64 message objects.
56 * - Transmit prioritization through one TX High Priority Buffer.
57 * - Receive message object FIFO with a user configurable depth of
58 * up to 64 message objects.
59 * - Watermark interrupts for Rx FIFO with configurable Watermark.
60 * - Acceptance filtering with 4 acceptance filters.
61 * - Sleep mode with automatic wake up.
62 * - Loop Back mode for diagnostic applications.
63 * - Snoop mode for diagnostic applications.
64 * - Maskable Error and Status Interrupts.
65 * - Readable Error Counters.
66 * - External PHY chip required.
67 * - Receive Timestamp.
69 * The device driver supports all the features listed above, if applicable.
71 * <b>Driver Description</b>
73 * The device driver enables higher layer software (e.g., an application) to
74 * communicate to the CAN. The driver handles transmission and reception of
75 * CAN frames, as well as configuration of the controller. The driver is simply a
76 * pass-through mechanism between a protocol stack and the CAN. A single device
77 * driver can support multiple CANs.
79 * Since the driver is a simple pass-through mechanism between a protocol stack
80 * and the CAN, no assembly or disassembly of CAN frames is done at the
81 * driver-level. This assumes that the protocol stack passes a correctly
82 * formatted CAN frame to the driver for transmission, and that the driver
83 * does not validate the contents of an incoming frame
85 * <b>Operation Modes</b>
87 * The CAN controller supports the following modes of operation:
88 * - <b>Configuration Mode</b>: In this mode the CAN timing parameters and
89 * Baud Rate Pre-scalar parameters can be changed. In this mode the CAN
90 * controller loses synchronization with the CAN bus and drives a
91 * constant recessive bit on the bus line. The Error Counter Register are
92 * reset. The CAN controller does not receive or transmit any messages
93 * even if there are pending transmit requests from the TX FIFO or the TX
94 * High Priority Buffer. The Storage FIFOs and the CAN configuration
95 * registers are still accessible.
96 * - <b>Normal Mode</b>:In Normal Mode the CAN controller participates in bus
97 * communication, by transmitting and receiving messages.
98 * - <b>Sleep Mode</b>: In Sleep Mode the CAN Controller does not transmit any
99 * messages. However, if any other node transmits a message, then the CAN
100 * Controller receives the transmitted message and exits from Sleep Mode.
101 * If there are new transmission requests from either the TX FIFO or the
102 * TX High Priority Buffer when the CAN Controller is in Sleep Mode, these
103 * requests are not serviced, and the CAN Controller continues to remain
104 * in Sleep Mode. Interrupts are generated when the CAN controller enters
105 * Sleep mode or Wakes up from Sleep mode.
106 * - <b>Loop Back Mode</b>: In Loop Back mode, the CAN controller transmits a
107 * recessive bit stream on to the CAN Bus. Any message that is transmitted
108 * is looped back to the
\91Rx
\92 line and acknowledged. The CAN controller
109 * thus receives any message that it transmits. It does not participate in
110 * normal bus communication and does not receive any messages that are
111 * transmitted by other CAN nodes. This mode is used for diagnostic
113 * - <b>Snoop Mode</b>: In Snoop mode, the CAN controller transmits a
114 * recessive bit stream on to the CAN Bus and does not participate
115 * in normal bus communication but receives messages that are transmitted
116 * by other CAN nodes. This mode is used for diagnostic purposes.
119 * <b>Buffer Alignment</b>
121 * It is important to note that frame buffers passed to the driver must be
124 * <b>Receive Address Filtering</b>
126 * The device can be set to accept frames whose Identifiers match any of the
127 * 4 filters set in the Acceptance Filter Mask/ID registers.
129 * The incoming Identifier is masked with the bits in the Acceptance Filter Mask
130 * Register. This value is compared with the result of masking the bits in the
131 * Acceptance Filter ID Register with the Acceptance Filter Mask Register. If
132 * both these values are equal, the message will be stored in the RX FIFO.
134 * Acceptance Filtering is performed by each of the defined acceptance filters.
135 * If the incoming identifier passes through any acceptance filter then the
136 * frame is stored in the RX FIFO.
138 * If the Accpetance Filters are not set up then all the received messages are
139 * stroed in the RX FIFO.
141 * <b>PHY Communication</b>
143 * This driver does not provide any mechanism for directly programming PHY.
147 * The driver has no dependencies on the interrupt controller. The driver
148 * provides an interrupt handler. User of this driver needs to provide
149 * callback functions. An interrupt handler example is available with
154 * This driver is not thread safe. Any needs for threads or thread mutual
155 * exclusion must be satisfied by the layer above this driver.
157 * <b>Device Reset</b>
159 * Bus Off interrupt that can occur in the device requires a device reset.
160 * The user is responsible for resetting the device and re-configuring it
161 * based on its needs (the driver does not save the current configuration).
162 * When integrating into an RTOS, these reset and re-configure obligations are
163 * taken care of by the OS adapter software if it exists for that RTOS.
165 * <b>Device Configuration</b>
167 * The device can be configured in various ways during the FPGA implementation
168 * process. Configuration parameters are stored in the xcanps_g.c files.
169 * A table is defined where each entry contains configuration information
170 * for a CAN device. This information includes such things as the base address
171 * of the memory-mapped device.
175 * Asserts are used within all Xilinx drivers to enforce constraints on argument
176 * values. Asserts can be turned off on a system-wide basis by defining, at
177 * compile time, the NDEBUG identifier. By default, asserts are turned on and it
178 * is recommended that users leave asserts on during development.
180 * <b>Building the driver</b>
182 * The XCanPs driver is composed of several source files. This allows the user
183 * to build and link only those parts of the driver that are necessary.
187 * MODIFICATION HISTORY:
189 * Ver Who Date Changes
190 * ----- ----- -------- -----------------------------------------------
191 * 1.00a xd/sv 01/12/10 First release
192 * 1.01a bss 12/27/11 Added the APIs XCanPs_SetTxIntrWatermark and
193 * XCanPs_GetTxIntrWatermark.
194 * Updated the Register/bit definitions
195 * Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
196 * Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
197 * Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
198 * Changed XCANPS_IXR_RXFLL_MASK to
199 * XCANPS_IXR_RXFWMFLL_MASK
201 * XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
202 * XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
203 * XCANPS_TXBUF_DW1_OFFSET to XCANPS_TXHPB_DW1_OFFSET
204 * XCANPS_TXBUF_DW2_OFFSET to XCANPS_TXHPB_DW2_OFFSET
207 ******************************************************************************/
208 #ifndef XCANPS_H /* prevent circular inclusions */
209 #define XCANPS_H /* by using protection macros */
215 /***************************** Include Files *********************************/
218 #include "xcanps_hw.h"
220 /************************** Constant Definitions *****************************/
222 /** @name CAN operation modes
225 #define XCANPS_MODE_CONFIG 0x00000001 /**< Configuration mode */
226 #define XCANPS_MODE_NORMAL 0x00000002 /**< Normal mode */
227 #define XCANPS_MODE_LOOPBACK 0x00000004 /**< Loop Back mode */
228 #define XCANPS_MODE_SLEEP 0x00000008 /**< Sleep mode */
229 #define XCANPS_MODE_SNOOP 0x00000010 /**< Snoop mode */
232 /** @name Callback identifiers used as parameters to XCanPs_SetHandler()
235 #define XCANPS_HANDLER_SEND 1 /**< Handler type for frame sending interrupt */
236 #define XCANPS_HANDLER_RECV 2 /**< Handler type for frame reception interrupt*/
237 #define XCANPS_HANDLER_ERROR 3 /**< Handler type for error interrupt */
238 #define XCANPS_HANDLER_EVENT 4 /**< Handler type for all other interrupts */
241 /**************************** Type Definitions *******************************/
244 * This typedef contains configuration information for a device.
247 u16 DeviceId; /**< Unique ID of device */
248 u32 BaseAddr; /**< Register base address */
251 /******************************************************************************/
253 * Callback type for frame sending and reception interrupts.
255 * @param CallBackRef is a callback reference passed in by the upper layer
256 * when setting the callback functions, and passed back to the
257 * upper layer when the callback is invoked.
258 *******************************************************************************/
259 typedef void (*XCanPs_SendRecvHandler) (void *CallBackRef);
261 /******************************************************************************/
263 * Callback type for error interrupt.
265 * @param CallBackRef is a callback reference passed in by the upper layer
266 * when setting the callback functions, and passed back to the
267 * upper layer when the callback is invoked.
268 * @param ErrorMask is a bit mask indicating the cause of the error. Its
269 * value equals 'OR'ing one or more XCANPS_ESR_* values defined in
271 *******************************************************************************/
272 typedef void (*XCanPs_ErrorHandler) (void *CallBackRef, u32 ErrorMask);
274 /******************************************************************************/
276 * Callback type for all kinds of interrupts except sending frame interrupt,
277 * receiving frame interrupt, and error interrupt.
279 * @param CallBackRef is a callback reference passed in by the upper layer
280 * when setting the callback functions, and passed back to the
281 * upper layer when the callback is invoked.
282 * @param Mask is a bit mask indicating the pending interrupts. Its value
283 * equals 'OR'ing one or more XCANPS_IXR_* defined in xcanps_hw.h
284 *******************************************************************************/
285 typedef void (*XCanPs_EventHandler) (void *CallBackRef, u32 Mask);
288 * The XCanPs driver instance data. The user is required to allocate a
289 * variable of this type for every CAN device in the system. A pointer
290 * to a variable of this type is then passed to the driver API functions.
293 XCanPs_Config CanConfig; /**< Device configuration */
294 u32 IsReady; /**< Device is initialized and ready */
297 * Callback and callback reference for TXOK interrupt.
299 XCanPs_SendRecvHandler SendHandler;
303 * Callback and callback reference for RXOK/RXNEMP/RXFLL interrupts.
305 XCanPs_SendRecvHandler RecvHandler;
309 * Callback and callback reference for ERROR interrupt.
311 XCanPs_ErrorHandler ErrorHandler;
315 * Callback and callback reference for RXOFLW/RXUFLW/TXBFLL/TXFLL/
316 * Wakeup/Sleep/Bus off/ARBLST interrupts.
318 XCanPs_EventHandler EventHandler;
324 /***************** Macros (Inline Functions) Definitions *********************/
326 /****************************************************************************/
329 * This macro checks if the transmission is complete.
331 * @param InstancePtr is a pointer to the XCanPs instance.
334 * - TRUE if the transmission is done.
335 * - FALSE if the transmission is not done.
337 * @note C-Style signature:
338 * int XCanPs_IsTxDone(XCanPs *InstancePtr);
340 *******************************************************************************/
341 #define XCanPs_IsTxDone(InstancePtr) \
342 ((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
343 XCANPS_ISR_OFFSET) & XCANPS_IXR_TXOK_MASK) ? TRUE : FALSE)
346 /****************************************************************************/
349 * This macro checks if the transmission FIFO is full.
351 * @param InstancePtr is a pointer to the XCanPs instance.
354 * - TRUE if TX FIFO is full.
355 * - FALSE if the TX FIFO is NOT full.
357 * @note C-Style signature:
358 * int XCanPs_IsTxFifoFull(XCanPs *InstancePtr);
360 *****************************************************************************/
361 #define XCanPs_IsTxFifoFull(InstancePtr) \
362 ((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
363 XCANPS_SR_OFFSET) & XCANPS_SR_TXFLL_MASK) ? TRUE : FALSE)
366 /****************************************************************************/
369 * This macro checks if the Transmission High Priority Buffer is full.
371 * @param InstancePtr is a pointer to the XCanPs instance.
374 * - TRUE if the TX High Priority Buffer is full.
375 * - FALSE if the TX High Priority Buffer is NOT full.
377 * @note C-Style signature:
378 * int XCanPs_IsHighPriorityBufFull(XCanPs *InstancePtr);
380 *****************************************************************************/
381 #define XCanPs_IsHighPriorityBufFull(InstancePtr) \
382 ((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
383 XCANPS_SR_OFFSET) & XCANPS_SR_TXBFLL_MASK) ? TRUE : FALSE)
386 /****************************************************************************/
389 * This macro checks if the receive FIFO is empty.
391 * @param InstancePtr is a pointer to the XCanPs instance.
394 * - TRUE if RX FIFO is empty.
395 * - FALSE if the RX FIFO is NOT empty.
397 * @note C-Style signature:
398 * int XCanPs_IsRxEmpty(XCanPs *InstancePtr);
400 *****************************************************************************/
401 #define XCanPs_IsRxEmpty(InstancePtr) \
402 ((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
403 XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK) ? FALSE : TRUE)
406 /****************************************************************************/
409 * This macro checks if the CAN device is ready for the driver to change
410 * Acceptance Filter Identifier Registers (AFIR) and Acceptance Filter Mask
413 * AFIR and AFMR for a filter are changeable only after the filter is disabled
414 * and this routine returns FALSE. The filter can be disabled using the
415 * XCanPs_AcceptFilterDisable function.
417 * Use the XCanPs_Accept_* functions for configuring the acceptance filters.
419 * @param InstancePtr is a pointer to the XCanPs instance.
422 * - TRUE if the device is busy and NOT ready to accept writes to
424 * - FALSE if the device is ready to accept writes to AFIR and
427 * @note C-Style signature:
428 * int XCanPs_IsAcceptFilterBusy(XCanPs *InstancePtr);
430 *****************************************************************************/
431 #define XCanPs_IsAcceptFilterBusy(InstancePtr) \
432 ((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
433 XCANPS_SR_OFFSET) & XCANPS_SR_ACFBSY_MASK) ? TRUE : FALSE)
436 /****************************************************************************/
439 * This macro calculates CAN message identifier value given identifier field
442 * @param StandardId contains Standard Message ID value.
443 * @param SubRemoteTransReq contains Substitute Remote Transmission
445 * @param IdExtension contains Identifier Extension value.
446 * @param ExtendedId contains Extended Message ID value.
447 * @param RemoteTransReq contains Remote Transmission Request value.
449 * @return Message Identifier value.
451 * @note C-Style signature:
452 * u32 XCanPs_CreateIdValue(u32 StandardId,
453 * u32 SubRemoteTransReq,
454 * u32 IdExtension, u32 ExtendedId,
455 * u32 RemoteTransReq);
457 * Read the CAN specification for meaning of each parameter.
459 *****************************************************************************/
460 #define XCanPs_CreateIdValue(StandardId, SubRemoteTransReq, IdExtension, \
461 ExtendedId, RemoteTransReq) \
462 ((((StandardId) << XCANPS_IDR_ID1_SHIFT) & XCANPS_IDR_ID1_MASK) | \
463 (((SubRemoteTransReq) << XCANPS_IDR_SRR_SHIFT) & XCANPS_IDR_SRR_MASK)|\
464 (((IdExtension) << XCANPS_IDR_IDE_SHIFT) & XCANPS_IDR_IDE_MASK) | \
465 (((ExtendedId) << XCANPS_IDR_ID2_SHIFT) & XCANPS_IDR_ID2_MASK) | \
466 ((RemoteTransReq) & XCANPS_IDR_RTR_MASK))
469 /****************************************************************************/
472 * This macro calculates value for Data Length Code register given Data
475 * @param DataLengCode indicates Data Length Code value.
477 * @return Value that can be assigned to Data Length Code register.
479 * @note C-Style signature:
480 * u32 XCanPs_CreateDlcValue(u32 DataLengCode);
482 * Read the CAN specification for meaning of Data Length Code.
484 *****************************************************************************/
485 #define XCanPs_CreateDlcValue(DataLengCode) \
486 (((DataLengCode) << XCANPS_DLCR_DLC_SHIFT) & XCANPS_DLCR_DLC_MASK)
489 /****************************************************************************/
492 * This macro clears the timestamp in the Timestamp Control Register.
494 * @param InstancePtr is a pointer to the XCanPs instance.
498 * @note C-Style signature:
499 * void XCanPs_ClearTimestamp(XCanPs *InstancePtr);
501 *****************************************************************************/
502 #define XCanPs_ClearTimestamp(InstancePtr) \
503 XCanPs_WriteReg((InstancePtr)->CanConfig.BaseAddr, \
504 XCANPS_TCR_OFFSET, XCANPS_TCR_CTS_MASK)
506 /************************** Function Prototypes ******************************/
509 * Functions in xcanps.c
511 int XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr,
514 void XCanPs_Reset(XCanPs *InstancePtr);
515 u8 XCanPs_GetMode(XCanPs *InstancePtr);
516 void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode);
517 u32 XCanPs_GetStatus(XCanPs *InstancePtr);
518 void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount,
520 u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr);
521 void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask);
522 int XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr);
523 int XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr);
524 int XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr);
525 void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes);
526 void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes);
527 u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr);
528 int XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex,
529 u32 MaskValue, u32 IdValue);
530 void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex,
531 u32 *MaskValue, u32 *IdValue);
533 int XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler);
534 u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr);
535 int XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth,
536 u8 TimeSegment2, u8 TimeSegment1);
537 void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth,
538 u8 *TimeSegment2, u8 *TimeSegment1);
540 int XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold);
541 u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr);
544 * Diagnostic functions in xcanps_selftest.c
546 int XCanPs_SelfTest(XCanPs *InstancePtr);
549 * Functions in xcanps_intr.c
551 void XCanPs_IntrEnable(XCanPs *InstancePtr, u32 Mask);
552 void XCanPs_IntrDisable(XCanPs *InstancePtr, u32 Mask);
553 u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr);
554 u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr);
555 void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask);
556 void XCanPs_IntrHandler(void *InstancePtr);
557 int XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType,
558 void *CallBackFunc, void *CallBackRef);
561 * Functions in xcanps_sinit.c
563 XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId);
569 #endif /* end of protection macro */