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  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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  31 ******************************************************************************/
  32 /*****************************************************************************/
  33 /**
  34 *
  35 * @file xemacps_intr.c
  36 * @addtogroup emacps_v3_1
  37 * @{
  38 *
  39 * Functions in this file implement general purpose interrupt processing related
  40 * functionality. See xemacps.h for a detailed description of the driver.
  41 *
  42 * <pre>
  43 * MODIFICATION HISTORY:
  44 *
  45 * Ver   Who  Date     Changes
  46 * ----- ---- -------- -------------------------------------------------------
  47 * 1.00a wsy  01/10/10 First release
  48 * 1.03a asa  01/24/13 Fix for CR #692702 which updates error handling for
  49 *                     Rx errors. Under heavy Rx traffic, there will be a large
  50 *                     number of errors related to receive buffer not available.
  51 *                     Because of a HW bug (SI #692601), under such heavy errors,
  52 *                     the Rx data path can become unresponsive. To reduce the
  53 *                     probabilities for hitting this HW bug, the SW writes to
  54 *                     bit 18 to flush a packet from Rx DPRAM immediately. The
  55 *                     changes for it are done in the function
  56 *                     XEmacPs_IntrHandler.
  57 * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification
  58 *                      and 64-bit changes.
  59 * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
  60 * 3.1   hk   07/27/15 Do not call error handler with '0' error code when
  61 *                     there is no error. CR# 869403
  62 * </pre>
  63 ******************************************************************************/
  64
  65 /***************************** Include Files *********************************/
  66
  67 #include "xemacps.h"
  68
  69 /************************** Constant Definitions *****************************/
  70
  71
  72 /**************************** Type Definitions *******************************/
  73
  74
  75 /***************** Macros (Inline Functions) Definitions *********************/
  76
  77
  78 /************************** Function Prototypes ******************************/
  79
  80
  81 /************************** Variable Definitions *****************************/
  82
  83
  84 /*****************************************************************************/
  85 /**
  86  * Install an asynchronious handler function for the given HandlerType:
  87  *
  88  * @param InstancePtr is a pointer to the instance to be worked on.
  89  * @param HandlerType indicates what interrupt handler type is.
  90  *        XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
  91  *        XEMACPS_HANDLER_ERROR.
  92  * @param FuncPointer is the pointer to the callback function
  93  * @param CallBackRef is the upper layer callback reference passed back when
  94  *        when the callback function is invoked.
  95  *
  96  * @return
  97  *
  98  * None.
  99  *
 100  * @note
 101  * There is no assert on the CallBackRef since the driver doesn't know what
 102  * it is.
 103  *
 104  *****************************************************************************/
 105 LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
 106                         void *FuncPointer, void *CallBackRef)
 107 {
 108         LONG Status;
 109         Xil_AssertNonvoid(InstancePtr != NULL);
 110         Xil_AssertNonvoid(FuncPointer != NULL);
 111         Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
 112
 113         switch (HandlerType) {
 114         case XEMACPS_HANDLER_DMASEND:
 115                 Status = (LONG)(XST_SUCCESS);
 116                 InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
 117                 InstancePtr->SendRef = CallBackRef;
 118                 break;
 119         case XEMACPS_HANDLER_DMARECV:
 120                 Status = (LONG)(XST_SUCCESS);
 121                 InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
 122                 InstancePtr->RecvRef = CallBackRef;
 123                 break;
 124         case XEMACPS_HANDLER_ERROR:
 125                 Status = (LONG)(XST_SUCCESS);
 126                 InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
 127                 InstancePtr->ErrorRef = CallBackRef;
 128                 break;
 129         default:
 130                 Status = (LONG)(XST_INVALID_PARAM);
 131                 break;
 132         }
 133         return Status;
 134 }
 135
 136 /*****************************************************************************/
 137 /**
 138 * Master interrupt handler for EMAC driver. This routine will query the
 139 * status of the device, bump statistics, and invoke user callbacks.
 140 *
 141 * This routine must be connected to an interrupt controller using OS/BSP
 142 * specific methods.
 143 *
 144 * @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the
 145 *        interrupt.
 146 *
 147 ******************************************************************************/
 148 void XEmacPs_IntrHandler(void *XEmacPsPtr)
 149 {
 150         u32 RegISR;
 151         u32 RegSR;
 152         u32 RegCtrl;
 153         u32 RegQ1ISR = 0U;
 154         XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
 155
 156         Xil_AssertVoid(InstancePtr != NULL);
 157         Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
 158
 159         /* This ISR will try to handle as many interrupts as it can in a single
 160          * call. However, in most of the places where the user's error handler
 161          * is called, this ISR exits because it is expected that the user will
 162          * reset the device in nearly all instances.
 163          */
 164         RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
 165                                    XEMACPS_ISR_OFFSET);
 166
 167         /* Read Transmit Q1 ISR */
 168
 169         if (InstancePtr->Version > 2)
 170                 RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
 171                                    XEMACPS_INTQ1_STS_OFFSET);
 172
 173         /* Clear the interrupt status register */
 174         XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
 175                            RegISR);
 176
 177         /* Receive complete interrupt */
 178         if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
 179                 /* Clear RX status register RX complete indication but preserve
 180                  * error bits if there is any */
 181                 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 182                                    XEMACPS_RXSR_OFFSET,
 183                                    ((u32)XEMACPS_RXSR_FRAMERX_MASK |
 184                                    (u32)XEMACPS_RXSR_BUFFNA_MASK));
 185                 InstancePtr->RecvHandler(InstancePtr->RecvRef);
 186         }
 187
 188         /* Transmit Q1 complete interrupt */
 189         if ((InstancePtr->Version > 2) &&
 190                         ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
 191                 /* Clear TX status register TX complete indication but preserve
 192                  * error bits if there is any */
 193                 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 194                                    XEMACPS_INTQ1_STS_OFFSET,
 195                                    XEMACPS_INTQ1SR_TXCOMPL_MASK);
 196                 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 197                                    XEMACPS_TXSR_OFFSET,
 198                                    ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
 199                                    (u32)XEMACPS_TXSR_USEDREAD_MASK));
 200                 InstancePtr->SendHandler(InstancePtr->SendRef);
 201         }
 202
 203         /* Transmit complete interrupt */
 204         if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
 205                 /* Clear TX status register TX complete indication but preserve
 206                  * error bits if there is any */
 207                 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 208                                    XEMACPS_TXSR_OFFSET,
 209                                    ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
 210                                    (u32)XEMACPS_TXSR_USEDREAD_MASK));
 211                 InstancePtr->SendHandler(InstancePtr->SendRef);
 212         }
 213
 214         /* Receive error conditions interrupt */
 215         if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
 216                 /* Clear RX status register */
 217                 RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
 218                                           XEMACPS_RXSR_OFFSET);
 219                 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 220                                    XEMACPS_RXSR_OFFSET, RegSR);
 221
 222                 /* Fix for CR # 692702. Write to bit 18 of net_ctrl
 223                  * register to flush a packet out of Rx SRAM upon
 224                  * an error for receive buffer not available. */
 225                 if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
 226                         RegCtrl =
 227                         XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
 228                                                 XEMACPS_NWCTRL_OFFSET);
 229                         RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
 230                         XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 231                                         XEMACPS_NWCTRL_OFFSET, RegCtrl);
 232                 }
 233
 234                 if(RegSR != 0) {
 235                         InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
 236                                                 XEMACPS_RECV, RegSR);
 237                 }
 238         }
 239
 240         /* When XEMACPS_IXR_TXCOMPL_MASK is flaged, XEMACPS_IXR_TXUSED_MASK
 241          * will be asserted the same time.
 242          * Have to distinguish this bit to handle the real error condition.
 243          */
 244         /* Transmit Q1 error conditions interrupt */
 245         if ((InstancePtr->Version > 2) &&
 246                         ((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
 247             ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
 248                         /* Clear Interrupt Q1 status register */
 249                         XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 250                                    XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
 251                         InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
 252                                           RegQ1ISR);
 253            }
 254
 255         /* Transmit error conditions interrupt */
 256         if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
 257             (!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
 258                 /* Clear TX status register */
 259                 RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
 260                                           XEMACPS_TXSR_OFFSET);
 261                 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 262                                    XEMACPS_TXSR_OFFSET, RegSR);
 263                 InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
 264                                           RegSR);
 265         }
 266
 267 }
 268 /** @} */