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40 ******************************************************************************/
41 /*****************************************************************************/
46 * The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
49 * The GPIO Controller supports the following features:
51 * - Masked writes (There are no masked reads)
53 * - Configurable Interrupts (Level/Edge)
55 * This driver is intended to be RTOS and processor independent. Any needs for
56 * dynamic memory management, threads or thread mutual exclusion, virtual
57 * memory, or cache control must be satisfied by the layer above this driver.
59 * This driver supports all the features listed above, if applicable.
61 * <b>Driver Description</b>
63 * The device driver enables higher layer software (e.g., an application) to
64 * communicate to the GPIO.
68 * The driver provides interrupt management functions and an interrupt handler.
69 * Users of this driver need to provide callback functions. An interrupt handler
70 * example is available with the driver.
74 * This driver is not thread safe. Any needs for threads or thread mutual
75 * exclusion must be satisfied by the layer above this driver.
79 * Asserts are used within all Xilinx drivers to enforce constraints on argument
80 * values. Asserts can be turned off on a system-wide basis by defining, at
81 * compile time, the NDEBUG identifier. By default, asserts are turned on and it
82 * is recommended that users leave asserts on during development.
84 * <b>Building the driver</b>
86 * The XGpioPs driver is composed of several source files. This allows the user
87 * to build and link only those parts of the driver that are necessary.
91 * MODIFICATION HISTORY:
93 * Ver Who Date Changes
94 * ----- ---- -------- -----------------------------------------------
95 * 1.00a sv 01/15/10 First Release
96 * 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
97 * XGpioPs_GetMode, XGpioPs_GetModePin as they are not
98 * relevant to Zynq device.The interrupts are disabled
99 * for output pins on all banks during initialization.
100 * 1.02a hk 08/22/13 Added low level reset API
101 * 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
105 ******************************************************************************/
106 #ifndef XGPIOPS_H /* prevent circular inclusions */
107 #define XGPIOPS_H /* by using protection macros */
113 /***************************** Include Files *********************************/
116 #include "xgpiops_hw.h"
118 /************************** Constant Definitions *****************************/
120 /** @name Interrupt types
122 * The following constants define the interrupt types that can be set for each
125 #define XGPIOPS_IRQ_TYPE_EDGE_RISING 0 /**< Interrupt on Rising edge */
126 #define XGPIOPS_IRQ_TYPE_EDGE_FALLING 1 /**< Interrupt Falling edge */
127 #define XGPIOPS_IRQ_TYPE_EDGE_BOTH 2 /**< Interrupt on both edges */
128 #define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 3 /**< Interrupt on high level */
129 #define XGPIOPS_IRQ_TYPE_LEVEL_LOW 4 /**< Interrupt on low level */
132 #define XGPIOPS_BANK0 0 /**< GPIO Bank 0 */
133 #define XGPIOPS_BANK1 1 /**< GPIO Bank 1 */
134 #define XGPIOPS_BANK2 2 /**< GPIO Bank 2 */
135 #define XGPIOPS_BANK3 3 /**< GPIO Bank 3 */
137 #define XGPIOPS_MAX_BANKS 4 /**< Max banks in a GPIO device */
138 #define XGPIOPS_BANK_MAX_PINS 32 /**< Max pins in a GPIO bank */
140 #define XGPIOPS_DEVICE_MAX_PIN_NUM 118 /*< Max pins in the GPIO device
147 /**************************** Type Definitions *******************************/
149 /****************************************************************************/
151 * This handler data type allows the user to define a callback function to
152 * handle the interrupts for the GPIO device. The application using this
153 * driver is expected to define a handler of this type, to support interrupt
154 * driven mode. The handler executes in an interrupt context such that minimal
155 * processing should be performed.
157 * @param CallBackRef is a callback reference passed in by the upper layer
158 * when setting the callback functions for a GPIO bank. It is
159 * passed back to the upper layer when the callback is invoked. Its
160 * type is not important to the driver component, so it is a void
162 * @param Bank is the bank for which the interrupt status has changed.
163 * @param Status is the Interrupt status of the GPIO bank.
165 *****************************************************************************/
166 typedef void (*XGpioPs_Handler) (void *CallBackRef, int Bank, u32 Status);
169 * This typedef contains configuration information for a device.
172 u16 DeviceId; /**< Unique ID of device */
173 u32 BaseAddr; /**< Register base address */
177 * The XGpioPs driver instance data. The user is required to allocate a
178 * variable of this type for the GPIO device in the system. A pointer
179 * to a variable of this type is then passed to the driver API functions.
182 XGpioPs_Config GpioConfig; /**< Device configuration */
183 u32 IsReady; /**< Device is initialized and ready */
184 XGpioPs_Handler Handler; /**< Status handlers for all banks */
185 void *CallBackRef; /**< Callback ref for bank handlers */
188 /***************** Macros (Inline Functions) Definitions *********************/
190 /************************** Function Prototypes ******************************/
193 * Functions in xgpiops.c
195 int XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
199 * Bank APIs in xgpiops.c
201 u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
202 void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
203 void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
204 u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
205 void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 Enable);
206 u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
207 void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank);
210 * Pin APIs in xgpiops.c
212 int XGpioPs_ReadPin(XGpioPs *InstancePtr, int Pin);
213 void XGpioPs_WritePin(XGpioPs *InstancePtr, int Pin, int Data);
214 void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, int Pin, int Direction);
215 int XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, int Pin);
216 void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, int Pin, int Enable);
217 int XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, int Pin);
220 * Diagnostic functions in xgpiops_selftest.c
222 int XGpioPs_SelfTest(XGpioPs *InstancePtr);
225 * Functions in xgpiops_intr.c
228 * Bank APIs in xgpiops_intr.c
230 void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
231 void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
232 u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
233 u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
234 void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
235 void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
236 u32 IntrPolarity, u32 IntrOnAny);
237 void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
238 u32 *IntrPolarity, u32 *IntrOnAny);
239 void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
240 XGpioPs_Handler FuncPtr);
241 void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
244 * Pin APIs in xgpiops_intr.c
246 void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, int Pin, u8 IrqType);
247 u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, int Pin);
249 void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, int Pin);
250 void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, int Pin);
251 int XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, int Pin);
252 int XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, int Pin);
253 void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, int Pin);
256 * Functions in xgpiops_sinit.c
258 XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
264 #endif /* end of protection macro */