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40 ******************************************************************************/
41 /*****************************************************************************/
46 * This header file contains the identifiers and basic driver functions (or
47 * macros) that can be used to access the device. Other driver functions
48 * are defined in xgpiops.h.
51 * MODIFICATION HISTORY:
53 * Ver Who Date Changes
54 * ----- ---- -------- -------------------------------------------------
55 * 1.00a sv 01/15/10 First Release
56 * 1.02a hk 08/22/13 Added low level reset API function prototype and
57 * related constant definitions
60 ******************************************************************************/
61 #ifndef XGPIOPS_HW_H /* prevent circular inclusions */
62 #define XGPIOPS_HW_H /* by using protection macros */
66 #endif /* __cplusplus */
68 /***************************** Include Files *********************************/
70 #include "xil_types.h"
71 #include "xil_assert.h"
74 /************************** Constant Definitions *****************************/
76 /** @name Register offsets for the GPIO. Each register is 32 bits.
79 #define XGPIOPS_DATA_LSW_OFFSET 0x000 /* Mask and Data Register LSW, WO */
80 #define XGPIOPS_DATA_MSW_OFFSET 0x004 /* Mask and Data Register MSW, WO */
81 #define XGPIOPS_DATA_OFFSET 0x040 /* Data Register, RW */
82 #define XGPIOPS_DATA_RO_OFFSET 0x060 /* Data Register - Input, RO */
83 #define XGPIOPS_DIRM_OFFSET 0x204 /* Direction Mode Register, RW */
84 #define XGPIOPS_OUTEN_OFFSET 0x208 /* Output Enable Register, RW */
85 #define XGPIOPS_INTMASK_OFFSET 0x20C /* Interrupt Mask Register, RO */
86 #define XGPIOPS_INTEN_OFFSET 0x210 /* Interrupt Enable Register, WO */
87 #define XGPIOPS_INTDIS_OFFSET 0x214 /* Interrupt Disable Register, WO*/
88 #define XGPIOPS_INTSTS_OFFSET 0x218 /* Interrupt Status Register, RO */
89 #define XGPIOPS_INTTYPE_OFFSET 0x21C /* Interrupt Type Register, RW */
90 #define XGPIOPS_INTPOL_OFFSET 0x220 /* Interrupt Polarity Register, RW */
91 #define XGPIOPS_INTANY_OFFSET 0x224 /* Interrupt On Any Register, RW */
94 /** @name Register offsets for each Bank.
97 #define XGPIOPS_DATA_MASK_OFFSET 0x8 /* Data/Mask Registers offset */
98 #define XGPIOPS_DATA_BANK_OFFSET 0x4 /* Data Registers offset */
99 #define XGPIOPS_REG_MASK_OFFSET 0x40 /* Registers offset */
102 /* For backwards compatibility */
103 #define XGPIOPS_BYPM_MASK_OFFSET XGPIOPS_REG_MASK_OFFSET
105 /** @name Interrupt type reset values for each bank
108 #define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFF
109 #define XGPIOPS_INTTYPE_BANK1_RESET 0x3FFFFFFF
110 #define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFF
111 #define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFF
114 /**************************** Type Definitions *******************************/
116 /***************** Macros (Inline Functions) Definitions *********************/
118 /****************************************************************************/
121 * This macro reads the given register.
123 * @param BaseAddr is the base address of the device.
124 * @param RegOffset is the register offset to be read.
126 * @return The 32-bit value of the register
130 *****************************************************************************/
131 #define XGpioPs_ReadReg(BaseAddr, RegOffset) \
132 Xil_In32((BaseAddr) + (RegOffset))
134 /****************************************************************************/
137 * This macro writes to the given register.
139 * @param BaseAddr is the base address of the device.
140 * @param RegOffset is the offset of the register to be written.
141 * @param Data is the 32-bit value to write to the register.
147 *****************************************************************************/
148 #define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
149 Xil_Out32((BaseAddr) + (RegOffset), (Data))
151 /************************** Function Prototypes ******************************/
153 void XGpioPs_ResetHw(u32 BaseAddress);
157 #endif /* __cplusplus */
159 #endif /* XGPIOPS_HW_H */