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41 /*****************************************************************************/
46 * Contains implementation of required functions for providing the reset sequence
47 * to the i2c interface
49 * <pre> MODIFICATION HISTORY:
51 * Ver Who Date Changes
52 * ----- ------ -------- --------------------------------------------
53 * 1.04a kpc 11/07/13 First release
57 ******************************************************************************/
59 /***************************** Include Files *********************************/
61 #include "xiicps_hw.h"
63 /************************** Constant Definitions *****************************/
65 /**************************** Type Definitions *******************************/
67 /***************** Macros (Inline Functions) Definitions *********************/
69 /************************** Function Prototypes ******************************/
71 /************************** Variable Definitions *****************************/
72 /*****************************************************************************/
74 * This function perform the reset sequence to the given I2c interface by
75 * configuring the appropriate control bits in the I2c specifc registers
76 * the i2cps reset squence involves the following steps
77 * Disable all the interuupts
79 * Clear FIFO's and disable hold bit
80 * Clear the line status
81 * Update relevant config registers with reset values
83 * @param BaseAddress of the interface
88 * This function will not modify the slcr registers that are relavant for
90 ******************************************************************************/
91 void XIicPs_ResetHw(u32 BaseAddress)
95 /* Disable all the interrupts */
96 XIicPs_WriteReg(BaseAddress, XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
97 /* Clear the interrupt status */
98 RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_ISR_OFFSET);
99 XIicPs_WriteReg(BaseAddress, XIICPS_ISR_OFFSET, RegVal);
100 /* Clear the hold bit,master enable bit and ack bit */
101 RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_CR_OFFSET);
102 RegVal &= ~(XIICPS_CR_HOLD_MASK|XIICPS_CR_MS_MASK|XIICPS_CR_ACKEN_MASK);
103 /* Clear the fifos */
104 RegVal |= XIICPS_CR_CLR_FIFO_MASK;
105 XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, RegVal);
106 /* Clear the timeout register */
107 XIicPs_WriteReg(BaseAddress, XIICPS_TIME_OUT_OFFSET, 0x0);
108 /* Clear the transfer size register */
109 XIicPs_WriteReg(BaseAddress, XIICPS_TRANS_SIZE_OFFSET, 0x0);
110 /* Clear the status register */
111 RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_SR_OFFSET);
112 XIicPs_WriteReg(BaseAddress, XIICPS_SR_OFFSET, RegVal);
113 /* Update the configuraqtion register with reset value */
114 XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, 0x0);