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   1 /******************************************************************************
   2 *
   3 * (c) Copyright 2013 Xilinx, Inc. All rights reserved.
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  12 * license issued to you by Xilinx, and to the maximum extent permitted by
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  40 ******************************************************************************/
  41 /*****************************************************************************/
  42 /**
  43 *
  44 * @file xqspips_hw.c
  45 *
  46 * Contains low level functions, primarily reset related.
  47 *
  48 * <pre>
  49 * MODIFICATION HISTORY:
  50 *
  51 * Ver   Who Date     Changes
  52 * ----- --- -------- -----------------------------------------------
  53 * 2.03a hk  09/17/13 First release
  54 *
  55 * </pre>
  56 *
  57 ******************************************************************************/
  58
  59 /***************************** Include Files *********************************/
  60
  61 #include "xqspips_hw.h"
  62 #include "xqspips.h"
  63
  64 /************************** Constant Definitions *****************************/
  65
  66 /** @name Pre-scaler value for divided by 4
  67  *
  68  * Pre-scaler value for divided by 4
  69  *
  70  * @{
  71  */
  72 #define XQSPIPS_CR_PRESC_DIV_BY_4       0x01
  73 /* @} */
  74
  75 /**************************** Type Definitions *******************************/
  76
  77 /***************** Macros (Inline Functions) Definitions *********************/
  78
  79 /************************** Function Prototypes ******************************/
  80
  81 /************************** Variable Definitions *****************************/
  82
  83
  84 /*****************************************************************************/
  85 /**
  86 *
  87 * Resets QSPI by disabling the device and bringing it to reset state through
  88 * register writes.
  89 *
  90 * @param        None
  91 *
  92 * @return       None.
  93 *
  94 * @note         None.
  95 *
  96 ******************************************************************************/
  97 void XQspiPs_ResetHw(u32 BaseAddress)
  98 {
  99         u32 ConfigReg;
 100
 101         /*
 102          * Disable interrupts
 103          */
 104         XQspiPs_WriteReg(BaseAddress, XQSPIPS_IDR_OFFSET,
 105                                 XQSPIPS_IXR_DISABLE_ALL);
 106
 107         /*
 108          * Disable device
 109          */
 110         XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
 111                                 0);
 112
 113         /*
 114          * De-assert slave select lines.
 115          */
 116         ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
 117         ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
 118         XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
 119
 120         /*
 121          * Write default value to RX and TX threshold registers
 122          * RX threshold should be set to 1 here because the corresponding
 123          * status bit is used next to clear the RXFIFO
 124          */
 125         XQspiPs_WriteReg(BaseAddress, XQSPIPS_TXWR_OFFSET,
 126                         (XQSPIPS_TXWR_RESET_VALUE & XQSPIPS_TXWR_MASK));
 127         XQspiPs_WriteReg(BaseAddress, XQSPIPS_RXWR_OFFSET,
 128                         (XQSPIPS_RXWR_RESET_VALUE & XQSPIPS_RXWR_MASK));
 129
 130         /*
 131          * Clear RXFIFO
 132          */
 133         while ((XQspiPs_ReadReg(BaseAddress,XQSPIPS_SR_OFFSET) &
 134                 XQSPIPS_IXR_RXNEMPTY_MASK) != 0) {
 135                 XQspiPs_ReadReg(BaseAddress, XQSPIPS_RXD_OFFSET);
 136         }
 137
 138         /*
 139          * Clear status register by reading register and
 140          * writing 1 to clear the write to clear bits
 141          */
 142         XQspiPs_ReadReg(BaseAddress, XQSPIPS_SR_OFFSET);
 143         XQspiPs_WriteReg(BaseAddress, XQSPIPS_SR_OFFSET,
 144                                 XQSPIPS_IXR_WR_TO_CLR_MASK);
 145
 146         /*
 147          * Write default value to configuration register
 148          */
 149         XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET,
 150                                 XQSPIPS_CR_RESET_STATE);
 151
 152
 153         /*
 154          * De-select linear mode
 155          */
 156         XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
 157                                 0x0);
 158
 159 }
 160
 161 /*****************************************************************************/
 162 /**
 163 *
 164 * Initializes QSPI to Linear mode with default QSPI boot settings.
 165 *
 166 * @param        None
 167 *
 168 * @return       None.
 169 *
 170 * @note         None.
 171 *
 172 ******************************************************************************/
 173 void XQspiPs_LinearInit(u32 BaseAddress)
 174 {
 175         u32 BaudRateDiv;
 176         u32 LinearCfg;
 177
 178         /*
 179          * Baud rate divisor for dividing by 4. Value of CR bits [5:3]
 180          * should be set to 0x001; hence shift the value and use the mask.
 181          */
 182         BaudRateDiv = ( (XQSPIPS_CR_PRESC_DIV_BY_4) <<
 183                         XQSPIPS_CR_PRESC_SHIFT) & XQSPIPS_CR_PRESC_MASK;
 184         /*
 185          * Write configuration register with default values, slave selected &
 186          * pre-scaler value for divide by 4
 187          */
 188         XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET,
 189                                 ((XQSPIPS_CR_RESET_STATE |
 190                                 XQSPIPS_CR_HOLD_B_MASK | BaudRateDiv) &
 191                                 (~XQSPIPS_CR_SSCTRL_MASK) ));
 192
 193         /*
 194          * Write linear configuration register with default value -
 195          * enable linear mode and use fast read.
 196          */
 197
 198         if(XPAR_PS7_QSPI_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_SINGLE){
 199
 200                 LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE;
 201
 202         }else if(XPAR_PS7_QSPI_0_QSPI_MODE ==
 203                         XQSPIPS_CONNECTION_MODE_STACKED){
 204
 205                 LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
 206                                 XQSPIPS_LQSPI_CR_TWO_MEM_MASK;
 207
 208         }else if(XPAR_PS7_QSPI_0_QSPI_MODE ==
 209                         XQSPIPS_CONNECTION_MODE_PARALLEL){
 210
 211                 LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
 212                                 XQSPIPS_LQSPI_CR_TWO_MEM_MASK |
 213                                 XQSPIPS_LQSPI_CR_SEP_BUS_MASK;
 214
 215         }
 216
 217         XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
 218                                 LinearCfg);
 219
 220         /*
 221          * Enable device
 222          */
 223         XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
 224                                 XQSPIPS_ER_ENABLE_MASK);
 225
 226 }
 227
 228