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   1 /******************************************************************************
   2 *
   3 * (c) Copyright 2013-2014 Xilinx, Inc. All rights reserved.
   4 *
   5 * This file contains confidential and proprietary information of Xilinx, Inc.
   6 * and is protected under U.S. and international copyright and other
   7 * intellectual property laws.
   8 *
   9 * DISCLAIMER
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  11 * materials distributed herewith. Except as otherwise provided in a valid
  12 * license issued to you by Xilinx, and to the maximum extent permitted by
  13 * applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
  14 * FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
  15 * IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
  16 * MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
  17 * and (2) Xilinx shall not be liable (whether in contract or tort, including
  18 * negligence, or under any other theory of liability) for any loss or damage
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  25 *
  26 * CRITICAL APPLICATIONS
  27 * Xilinx products are not designed or intended to be fail-safe, or for use in
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  31 * that could lead to death, personal injury, or severe property or
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  34 * Xilinx products in Critical Applications, subject only to applicable laws
  35 * and regulations governing limitations on product liability.
  36 *
  37 * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
  38 * AT ALL TIMES.
  39 *
  40 ******************************************************************************/
  41 /*****************************************************************************/
  42 /**
  43 *
  44 * @file xsdps_options.c
  45 *
  46 * Contains API's for changing the various options in host and card.
  47 * See xsdps.h for a detailed description of the device and driver.
  48 *
  49 * <pre>
  50 * MODIFICATION HISTORY:
  51 *
  52 * Ver   Who    Date     Changes
  53 * ----- ---    -------- -----------------------------------------------
  54 * 1.00a hk/sg  10/17/13 Initial release
  55 * 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
  56 *                       Add sleep for microblaze designs. CR# 781117.
  57 *
  58 * </pre>
  59 *
  60 ******************************************************************************/
  61
  62 /***************************** Include Files *********************************/
  63 #include "xsdps.h"
  64 /*
  65  * The header sleep.h and API usleep() can only be used with an arm design.
  66  * MB_Sleep() is used for microblaze design.
  67  */
  68 #ifdef __arm__
  69
  70 #include "sleep.h"
  71
  72 #endif
  73
  74 #ifdef __MICROBLAZE__
  75
  76 #include "microblaze_sleep.h"
  77
  78 #endif
  79
  80 /************************** Constant Definitions *****************************/
  81 #define XSDPS_SCR_BLKCNT        1
  82 #define XSDPS_SCR_BLKSIZE       8
  83 #define XSDPS_4_BIT_WIDTH       0x2
  84 #define XSDPS_SWITCH_CMD_BLKCNT         1
  85 #define XSDPS_SWITCH_CMD_BLKSIZE        64
  86 #define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0
  87 #define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1
  88 #define XSDPS_EXT_CSD_CMD_BLKCNT        1
  89 #define XSDPS_EXT_CSD_CMD_BLKSIZE       512
  90 #define XSDPS_CLK_52_MHZ                52000000
  91 #define XSDPS_MMC_HIGH_SPEED_ARG        0x03B90100
  92 #define XSDPS_MMC_4_BIT_BUS_ARG         0x03B70100
  93 #define XSDPS_MMC_DELAY_FOR_SWITCH      2000
  94
  95 /**************************** Type Definitions *******************************/
  96
  97 /***************** Macros (Inline Functions) Definitions *********************/
  98
  99 /************************** Function Prototypes ******************************/
 100 int XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
 101 void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
 102
 103 /*****************************************************************************/
 104 /**
 105 * Update Block size for read/write operations.
 106 *
 107 * @param        InstancePtr is a pointer to the instance to be worked on.
 108 * @param        BlkSize - Block size passed by the user.
 109 *
 110 * @return       None
 111 *
 112 ******************************************************************************/
 113 int XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize)
 114 {
 115         u32 Status = 0;
 116         u32 PresentStateReg = 0;
 117
 118         Xil_AssertNonvoid(InstancePtr != NULL);
 119         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 120
 121         PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
 122                         XSDPS_PRES_STATE_OFFSET);
 123
 124         if (PresentStateReg & (XSDPS_PSR_INHIBIT_CMD_MASK |
 125                         XSDPS_PSR_INHIBIT_DAT_MASK |
 126                         XSDPS_PSR_WR_ACTIVE_MASK | XSDPS_PSR_RD_ACTIVE_MASK)) {
 127                 Status = XST_FAILURE;
 128                 goto RETURN_PATH;
 129         }
 130
 131
 132         /*
 133          * Send block write command
 134          */
 135         Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0);
 136         if (Status != XST_SUCCESS) {
 137                 Status = XST_FAILURE;
 138                 goto RETURN_PATH;
 139         }
 140
 141         Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
 142                         XSDPS_RESP0_OFFSET);
 143
 144         /*
 145          * Set block size to the value passed
 146          */
 147         BlkSize &= XSDPS_BLK_SIZE_MASK;
 148         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
 149                          BlkSize);
 150
 151         Status = XST_SUCCESS;
 152
 153         RETURN_PATH:
 154                 return Status;
 155
 156 }
 157
 158 /*****************************************************************************/
 159 /**
 160 *
 161 * API to get bus width support by card.
 162 *
 163 *
 164 * @param        InstancePtr is a pointer to the XSdPs instance.
 165 * @param        SCR - buffer to store SCR register returned by card.
 166 *
 167 * @return
 168 *               - XST_SUCCESS if successful.
 169 *               - XST_FAILURE if fail.
 170 *
 171 * @note         None.
 172 *
 173 ******************************************************************************/
 174 int XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR)
 175 {
 176         u32 Status = 0;
 177         u32 StatusReg = 0x0;
 178         u16 BlkCnt;
 179         u16 BlkSize;
 180         int LoopCnt;
 181
 182         Xil_AssertNonvoid(InstancePtr != NULL);
 183         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 184
 185         for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) {
 186                 SCR[LoopCnt] = 0;
 187         }
 188
 189         /*
 190          * Send block write command
 191          */
 192         Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
 193                         InstancePtr->RelCardAddr, 0);
 194         if (Status != XST_SUCCESS) {
 195                 Status = XST_FAILURE;
 196                 goto RETURN_PATH;
 197         }
 198
 199         BlkCnt = XSDPS_SCR_BLKCNT;
 200         BlkSize = XSDPS_SCR_BLKSIZE;
 201
 202         /*
 203          * Set block size to the value passed
 204          */
 205         BlkSize &= XSDPS_BLK_SIZE_MASK;
 206         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 207                         XSDPS_BLK_SIZE_OFFSET, BlkSize);
 208
 209         XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SCR);
 210
 211         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 212                         XSDPS_XFER_MODE_OFFSET,
 213                         XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
 214
 215         Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0, BlkCnt);
 216         if (Status != XST_SUCCESS) {
 217                 Status = XST_FAILURE;
 218                 goto RETURN_PATH;
 219         }
 220
 221         /*
 222          * Check for transfer complete
 223          * Polling for response for now
 224          */
 225         do {
 226                 StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
 227                                         XSDPS_NORM_INTR_STS_OFFSET);
 228                 if (StatusReg & XSDPS_INTR_ERR_MASK) {
 229                         /*
 230                          * Write to clear error bits
 231                          */
 232                         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 233                                         XSDPS_ERR_INTR_STS_OFFSET,
 234                                         XSDPS_ERROR_INTR_ALL_MASK);
 235                         Status = XST_FAILURE;
 236                         goto RETURN_PATH;
 237                 }
 238         } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0);
 239
 240         /*
 241          * Write to clear bit
 242          */
 243         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 244                         XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
 245
 246         Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
 247                         XSDPS_RESP0_OFFSET);
 248
 249         Status = XST_SUCCESS;
 250
 251         RETURN_PATH:
 252                 return Status;
 253
 254 }
 255
 256 /*****************************************************************************/
 257 /**
 258 *
 259 * API to set bus width to 4-bit in card and host
 260 *
 261 *
 262 * @param        InstancePtr is a pointer to the XSdPs instance.
 263 *
 264 * @return
 265 *               - XST_SUCCESS if successful.
 266 *               - XST_FAILURE if fail.
 267 *
 268 * @note         None.
 269 *
 270 ******************************************************************************/
 271 int XSdPs_Change_BusWidth(XSdPs *InstancePtr)
 272 {
 273         u32 Status = 0;
 274         u32 StatusReg = 0x0;
 275         u32 Arg = 0;
 276
 277         Xil_AssertNonvoid(InstancePtr != NULL);
 278         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 279
 280 #ifndef MMC_CARD
 281
 282         Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
 283                         InstancePtr->RelCardAddr, 0);
 284         if (Status != XST_SUCCESS) {
 285                 Status = XST_FAILURE;
 286                 goto RETURN_PATH;
 287         }
 288
 289         Arg = XSDPS_4_BIT_WIDTH;
 290         Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0);
 291         if (Status != XST_SUCCESS) {
 292                 Status = XST_FAILURE;
 293                 goto RETURN_PATH;
 294         }
 295
 296         StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
 297                                         XSDPS_HOST_CTRL1_OFFSET);
 298         StatusReg |= XSDPS_HC_WIDTH_MASK;
 299         XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
 300                         XSDPS_HOST_CTRL1_OFFSET,StatusReg);
 301
 302         Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
 303                         XSDPS_RESP0_OFFSET);
 304
 305 #else
 306
 307         Arg = XSDPS_MMC_4_BIT_BUS_ARG;
 308         Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0);
 309         if (Status != XST_SUCCESS) {
 310                 Status = XST_FAILURE;
 311                 goto RETURN_PATH;
 312         }
 313
 314 #ifdef __arm__
 315
 316         usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
 317
 318 #endif
 319
 320 #ifdef __MICROBLAZE__
 321
 322         /* 2 msec delay */
 323         MB_Sleep(2);
 324
 325 #endif
 326
 327         StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
 328                                         XSDPS_HOST_CTRL1_OFFSET);
 329         StatusReg |= XSDPS_HC_WIDTH_MASK;
 330         XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
 331                         XSDPS_HOST_CTRL1_OFFSET,StatusReg);
 332
 333         Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
 334                         XSDPS_RESP0_OFFSET);
 335
 336 #endif
 337
 338         Status = XST_SUCCESS;
 339
 340         RETURN_PATH:
 341                 return Status;
 342
 343 }
 344
 345 /*****************************************************************************/
 346 /**
 347 *
 348 * API to get bus speed supported by card.
 349 *
 350 *
 351 * @param        InstancePtr is a pointer to the XSdPs instance.
 352 * @param        ReadBuff - buffer to store function group support data
 353 *               returned by card.
 354 *
 355 * @return
 356 *               - XST_SUCCESS if successful.
 357 *               - XST_FAILURE if fail.
 358 *
 359 * @note         None.
 360 *
 361 ******************************************************************************/
 362 int XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
 363 {
 364         u32 Status = 0;
 365         u32 StatusReg = 0x0;
 366         u32 Arg = 0;
 367         u16 BlkCnt;
 368         u16 BlkSize;
 369         int LoopCnt;
 370
 371         Xil_AssertNonvoid(InstancePtr != NULL);
 372         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 373
 374         for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) {
 375                 ReadBuff[LoopCnt] = 0;
 376         }
 377
 378         BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
 379         BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
 380         BlkSize &= XSDPS_BLK_SIZE_MASK;
 381         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 382                         XSDPS_BLK_SIZE_OFFSET, BlkSize);
 383
 384         XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
 385
 386         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 387                         XSDPS_XFER_MODE_OFFSET,
 388                         XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
 389
 390         Arg = XSDPS_SWITCH_CMD_HS_GET;
 391
 392         Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1);
 393         if (Status != XST_SUCCESS) {
 394                 Status = XST_FAILURE;
 395                 goto RETURN_PATH;
 396         }
 397
 398         /*
 399          * Check for transfer complete
 400          * Polling for response for now
 401          */
 402         do {
 403                 StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
 404                                         XSDPS_NORM_INTR_STS_OFFSET);
 405                 if (StatusReg & XSDPS_INTR_ERR_MASK) {
 406                         /*
 407                          * Write to clear error bits
 408                          */
 409                         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 410                                         XSDPS_ERR_INTR_STS_OFFSET,
 411                                         XSDPS_ERROR_INTR_ALL_MASK);
 412                         Status = XST_FAILURE;
 413                         goto RETURN_PATH;
 414                 }
 415         } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0);
 416
 417         /*
 418          * Write to clear bit
 419          */
 420         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 421                         XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
 422
 423         Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
 424                         XSDPS_RESP0_OFFSET);
 425
 426         Status = XST_SUCCESS;
 427
 428         RETURN_PATH:
 429                 return Status;
 430
 431 }
 432
 433 /*****************************************************************************/
 434 /**
 435 *
 436 * API to set high speed in card and host. Changes clock in host accordingly.
 437 *
 438 *
 439 * @param        InstancePtr is a pointer to the XSdPs instance.
 440 *
 441 * @return
 442 *               - XST_SUCCESS if successful.
 443 *               - XST_FAILURE if fail.
 444 *
 445 * @note         None.
 446 *
 447 ******************************************************************************/
 448 int XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
 449 {
 450         u32 Status = 0;
 451         u32 StatusReg = 0x0;
 452         u32 Arg = 0;
 453
 454 #ifndef MMC_CARD
 455         u32 ClockReg;
 456         u8 ReadBuff[64];
 457         u16 BlkCnt;
 458         u16 BlkSize;
 459 #endif
 460
 461         Xil_AssertNonvoid(InstancePtr != NULL);
 462         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 463
 464 #ifndef MMC_CARD
 465
 466         BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
 467         BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
 468         BlkSize &= XSDPS_BLK_SIZE_MASK;
 469         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 470                         XSDPS_BLK_SIZE_OFFSET, BlkSize);
 471
 472         XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
 473
 474         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 475                         XSDPS_XFER_MODE_OFFSET,
 476                         XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
 477
 478         Arg = XSDPS_SWITCH_CMD_HS_SET;
 479         Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1);
 480         if (Status != XST_SUCCESS) {
 481                 Status = XST_FAILURE;
 482                 goto RETURN_PATH;
 483         }
 484
 485         /*
 486          * Check for transfer complete
 487          * Polling for response for now
 488          */
 489         do {
 490                 StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
 491                                         XSDPS_NORM_INTR_STS_OFFSET);
 492                 if (StatusReg & XSDPS_INTR_ERR_MASK) {
 493                         /*
 494                          * Write to clear error bits
 495                          */
 496                         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 497                                         XSDPS_ERR_INTR_STS_OFFSET,
 498                                         XSDPS_ERROR_INTR_ALL_MASK);
 499                         Status = XST_FAILURE;
 500                         goto RETURN_PATH;
 501                 }
 502         } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0);
 503
 504         /*
 505          * Write to clear bit
 506          */
 507         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 508                         XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
 509
 510         ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
 511                         XSDPS_CLK_CTRL_OFFSET);
 512         ClockReg &= ~(XSDPS_CC_INT_CLK_EN_MASK | XSDPS_CC_SD_CLK_EN_MASK);
 513
 514         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 515                         XSDPS_CLK_CTRL_OFFSET, ClockReg);
 516
 517         ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
 518                         XSDPS_CLK_CTRL_OFFSET);
 519         ClockReg &= (~XSDPS_CC_SDCLK_FREQ_SEL_MASK);
 520         ClockReg |= XSDPS_CC_SDCLK_FREQ_BASE_MASK | XSDPS_CC_INT_CLK_EN_MASK;
 521         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 522                         XSDPS_CLK_CTRL_OFFSET, ClockReg);
 523
 524         /*
 525          * Wait for internal clock to stabilize
 526          */
 527         while((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
 528                 XSDPS_CLK_CTRL_OFFSET) & XSDPS_CC_INT_CLK_STABLE_MASK) == 0);
 529
 530         /*
 531          * Enable SD clock
 532          */
 533         ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
 534                         XSDPS_CLK_CTRL_OFFSET);
 535         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 536                         XSDPS_CLK_CTRL_OFFSET,
 537                         ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
 538
 539
 540         StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
 541                                         XSDPS_HOST_CTRL1_OFFSET);
 542         StatusReg |= XSDPS_HC_SPEED_MASK;
 543         XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
 544                         XSDPS_HOST_CTRL1_OFFSET,StatusReg);
 545
 546         Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
 547                         XSDPS_RESP0_OFFSET);
 548
 549 #else
 550
 551         Arg = XSDPS_MMC_HIGH_SPEED_ARG;
 552         Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0);
 553         if (Status != XST_SUCCESS) {
 554                 Status = XST_FAILURE;
 555                 goto RETURN_PATH;
 556         }
 557
 558 #ifdef __arm__
 559
 560         usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
 561
 562 #endif
 563
 564 #ifdef __MICROBLAZE__
 565
 566         /* 2 msec delay */
 567         MB_Sleep(2);
 568
 569 #endif
 570
 571         XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ);
 572
 573         StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
 574                                         XSDPS_HOST_CTRL1_OFFSET);
 575         StatusReg |= XSDPS_HC_SPEED_MASK;
 576         XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
 577                         XSDPS_HOST_CTRL1_OFFSET,StatusReg);
 578
 579         Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
 580                         XSDPS_RESP0_OFFSET);
 581 #endif
 582
 583         Status = XST_SUCCESS;
 584
 585         RETURN_PATH:
 586                 return Status;
 587
 588 }
 589
 590 /*****************************************************************************/
 591 /**
 592 *
 593 * API to change clock freq to given value.
 594 *
 595 *
 596 * @param        InstancePtr is a pointer to the XSdPs instance.
 597 * @param        SelFreq - Clock frequency in Hz.
 598 *
 599 * @return       None
 600 *
 601 * @note         This API will change clock frequency to the value less than
 602 *               or equal to the given value using the permissible dividors.
 603 *
 604 ******************************************************************************/
 605 int XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
 606 {
 607         u16 ClockReg;
 608         int DivCnt;
 609         u16 Divisor;
 610         u16 ClkLoopCnt;
 611         int Status;
 612
 613         Xil_AssertNonvoid(InstancePtr != NULL);
 614         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 615
 616         /*
 617          * Disable clock
 618          */
 619         ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
 620                         XSDPS_CLK_CTRL_OFFSET);
 621         ClockReg &= ~(XSDPS_CC_INT_CLK_EN_MASK | XSDPS_CC_SD_CLK_EN_MASK);
 622
 623         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 624                         XSDPS_CLK_CTRL_OFFSET, ClockReg);
 625
 626         /*
 627          * Calculate divisor
 628          */
 629         DivCnt = 0x1;
 630         for(ClkLoopCnt = 0; ClkLoopCnt < XSDPS_CC_MAX_NUM_OF_DIV;
 631                 ClkLoopCnt++) {
 632                 if( ((InstancePtr->Config.InputClockHz)/DivCnt) <= SelFreq) {
 633                         Divisor = DivCnt/2;
 634                         Divisor = Divisor << XSDPS_CC_DIV_SHIFT;
 635                         break;
 636                 }
 637                 DivCnt = DivCnt << 1;
 638         }
 639
 640         if(ClkLoopCnt == 9) {
 641
 642                 /*
 643                  * No valid divisor found for given frequency
 644                  */
 645                 Status = XST_FAILURE;
 646                 goto RETURN_PATH;
 647         }
 648
 649         /*
 650          * Set clock divisor
 651          */
 652         ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
 653                         XSDPS_CLK_CTRL_OFFSET);
 654         ClockReg &= (~XSDPS_CC_SDCLK_FREQ_SEL_MASK);
 655
 656         ClockReg |= Divisor | XSDPS_CC_INT_CLK_EN_MASK;
 657         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 658                         XSDPS_CLK_CTRL_OFFSET, ClockReg);
 659
 660         /*
 661          * Wait for internal clock to stabilize
 662          */
 663         while((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
 664                 XSDPS_CLK_CTRL_OFFSET) & XSDPS_CC_INT_CLK_STABLE_MASK) == 0);
 665
 666         /*
 667          * Enable SD clock
 668          */
 669         ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
 670                         XSDPS_CLK_CTRL_OFFSET);
 671         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 672                         XSDPS_CLK_CTRL_OFFSET,
 673                         ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
 674
 675         Status = XST_SUCCESS;
 676
 677         RETURN_PATH:
 678                 return Status;
 679
 680 }
 681
 682 /*****************************************************************************/
 683 /**
 684 *
 685 * API to send pullup command to card before using DAT line 3(using 4-bit bus)
 686 *
 687 *
 688 * @param        InstancePtr is a pointer to the XSdPs instance.
 689 *
 690 * @return
 691 *               - XST_SUCCESS if successful.
 692 *               - XST_FAILURE if fail.
 693 *
 694 * @note         None.
 695 *
 696 ******************************************************************************/
 697 int XSdPs_Pullup(XSdPs *InstancePtr)
 698 {
 699         u32 Status = 0;
 700
 701         Xil_AssertNonvoid(InstancePtr != NULL);
 702         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 703
 704         Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
 705                         InstancePtr->RelCardAddr, 0);
 706         if (Status != XST_SUCCESS) {
 707                 Status = XST_FAILURE;
 708                 goto RETURN_PATH;
 709         }
 710
 711         Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0, 0);
 712         if (Status != XST_SUCCESS) {
 713                 Status = XST_FAILURE;
 714                 goto RETURN_PATH;
 715         }
 716
 717         Status = XST_SUCCESS;
 718
 719         RETURN_PATH:
 720                 return Status;
 721
 722 }
 723
 724 /*****************************************************************************/
 725 /**
 726 *
 727 * API to get EXT_CSD register of eMMC.
 728 *
 729 *
 730 * @param        InstancePtr is a pointer to the XSdPs instance.
 731 * @param        ReadBuff - buffer to store EXT_CSD
 732 *
 733 * @return
 734 *               - XST_SUCCESS if successful.
 735 *               - XST_FAILURE if fail.
 736 *
 737 * @note         None.
 738 *
 739 ******************************************************************************/
 740 int XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
 741 {
 742         u32 Status = 0;
 743         u32 StatusReg = 0x0;
 744         u32 Arg = 0;
 745         u16 BlkCnt;
 746         u16 BlkSize;
 747         int LoopCnt;
 748
 749         Xil_AssertNonvoid(InstancePtr != NULL);
 750         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 751
 752         for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) {
 753                 ReadBuff[LoopCnt] = 0;
 754         }
 755
 756         BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT;
 757         BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE;
 758         BlkSize &= XSDPS_BLK_SIZE_MASK;
 759         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 760                         XSDPS_BLK_SIZE_OFFSET, BlkSize);
 761
 762         XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
 763
 764         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 765                         XSDPS_XFER_MODE_OFFSET,
 766                         XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
 767
 768         Arg = 0;
 769
 770         /*
 771          * Send SEND_EXT_CSD command
 772          */
 773         Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1);
 774         if (Status != XST_SUCCESS) {
 775                 Status = XST_FAILURE;
 776                 goto RETURN_PATH;
 777         }
 778
 779         /*
 780          * Check for transfer complete
 781          * Polling for response for now
 782          */
 783         do {
 784                 StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
 785                                         XSDPS_NORM_INTR_STS_OFFSET);
 786                 if (StatusReg & XSDPS_INTR_ERR_MASK) {
 787                         /*
 788                          * Write to clear error bits
 789                          */
 790                         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 791                                         XSDPS_ERR_INTR_STS_OFFSET,
 792                                         XSDPS_ERROR_INTR_ALL_MASK);
 793                         Status = XST_FAILURE;
 794                         goto RETURN_PATH;
 795                 }
 796         } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0);
 797
 798         /*
 799          * Write to clear bit
 800          */
 801         XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 802                         XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
 803
 804         Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
 805                         XSDPS_RESP0_OFFSET);
 806
 807         Status = XST_SUCCESS;
 808
 809         RETURN_PATH:
 810                 return Status;
 811
 812 }
 813