4 * Copyright (c) 2012 Atmel Corporation. All rights reserved.
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10 * Redistribution and use in source and binary forms, with or without
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11 * modification, are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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16 * 2. Redistributions in binary form must reproduce the above copyright notice,
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17 * this list of conditions and the following disclaimer in the documentation
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18 * and/or other materials provided with the distribution.
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20 * 3. The name of Atmel may not be used to endorse or promote products derived
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21 * from this software without specific prior written permission.
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23 * 4. This software may only be redistributed and used in connection with an
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24 * Atmel microcontroller product.
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26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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36 * POSSIBILITY OF SUCH DAMAGE.
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42 #ifndef _SAM3XA_EMAC_INSTANCE_
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43 #define _SAM3XA_EMAC_INSTANCE_
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45 /* ========== Register definition for EMAC peripheral ========== */
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46 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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47 #define REG_EMAC_NCR (0x400B0000U) /**< \brief (EMAC) Network Control Register */
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48 #define REG_EMAC_NCFGR (0x400B0004U) /**< \brief (EMAC) Network Configuration Register */
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49 #define REG_EMAC_NSR (0x400B0008U) /**< \brief (EMAC) Network Status Register */
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50 #define REG_EMAC_TSR (0x400B0014U) /**< \brief (EMAC) Transmit Status Register */
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51 #define REG_EMAC_RBQP (0x400B0018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */
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52 #define REG_EMAC_TBQP (0x400B001CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */
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53 #define REG_EMAC_RSR (0x400B0020U) /**< \brief (EMAC) Receive Status Register */
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54 #define REG_EMAC_ISR (0x400B0024U) /**< \brief (EMAC) Interrupt Status Register */
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55 #define REG_EMAC_IER (0x400B0028U) /**< \brief (EMAC) Interrupt Enable Register */
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56 #define REG_EMAC_IDR (0x400B002CU) /**< \brief (EMAC) Interrupt Disable Register */
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57 #define REG_EMAC_IMR (0x400B0030U) /**< \brief (EMAC) Interrupt Mask Register */
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58 #define REG_EMAC_MAN (0x400B0034U) /**< \brief (EMAC) Phy Maintenance Register */
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59 #define REG_EMAC_PTR (0x400B0038U) /**< \brief (EMAC) Pause Time Register */
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60 #define REG_EMAC_PFR (0x400B003CU) /**< \brief (EMAC) Pause Frames Received Register */
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61 #define REG_EMAC_FTO (0x400B0040U) /**< \brief (EMAC) Frames Transmitted Ok Register */
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62 #define REG_EMAC_SCF (0x400B0044U) /**< \brief (EMAC) Single Collision Frames Register */
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63 #define REG_EMAC_MCF (0x400B0048U) /**< \brief (EMAC) Multiple Collision Frames Register */
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64 #define REG_EMAC_FRO (0x400B004CU) /**< \brief (EMAC) Frames Received Ok Register */
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65 #define REG_EMAC_FCSE (0x400B0050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */
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66 #define REG_EMAC_ALE (0x400B0054U) /**< \brief (EMAC) Alignment Errors Register */
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67 #define REG_EMAC_DTF (0x400B0058U) /**< \brief (EMAC) Deferred Transmission Frames Register */
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68 #define REG_EMAC_LCOL (0x400B005CU) /**< \brief (EMAC) Late Collisions Register */
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69 #define REG_EMAC_ECOL (0x400B0060U) /**< \brief (EMAC) Excessive Collisions Register */
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70 #define REG_EMAC_TUND (0x400B0064U) /**< \brief (EMAC) Transmit Underrun Errors Register */
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71 #define REG_EMAC_CSE (0x400B0068U) /**< \brief (EMAC) Carrier Sense Errors Register */
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72 #define REG_EMAC_RRE (0x400B006CU) /**< \brief (EMAC) Receive Resource Errors Register */
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73 #define REG_EMAC_ROV (0x400B0070U) /**< \brief (EMAC) Receive Overrun Errors Register */
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74 #define REG_EMAC_RSE (0x400B0074U) /**< \brief (EMAC) Receive Symbol Errors Register */
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75 #define REG_EMAC_ELE (0x400B0078U) /**< \brief (EMAC) Excessive Length Errors Register */
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76 #define REG_EMAC_RJA (0x400B007CU) /**< \brief (EMAC) Receive Jabbers Register */
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77 #define REG_EMAC_USF (0x400B0080U) /**< \brief (EMAC) Undersize Frames Register */
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78 #define REG_EMAC_STE (0x400B0084U) /**< \brief (EMAC) SQE Test Errors Register */
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79 #define REG_EMAC_RLE (0x400B0088U) /**< \brief (EMAC) Received Length Field Mismatch Register */
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80 #define REG_EMAC_HRB (0x400B0090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */
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81 #define REG_EMAC_HRT (0x400B0094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */
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82 #define REG_EMAC_SA1B (0x400B0098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */
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83 #define REG_EMAC_SA1T (0x400B009CU) /**< \brief (EMAC) Specific Address 1 Top Register */
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84 #define REG_EMAC_SA2B (0x400B00A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */
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85 #define REG_EMAC_SA2T (0x400B00A4U) /**< \brief (EMAC) Specific Address 2 Top Register */
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86 #define REG_EMAC_SA3B (0x400B00A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */
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87 #define REG_EMAC_SA3T (0x400B00ACU) /**< \brief (EMAC) Specific Address 3 Top Register */
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88 #define REG_EMAC_SA4B (0x400B00B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */
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89 #define REG_EMAC_SA4T (0x400B00B4U) /**< \brief (EMAC) Specific Address 4 Top Register */
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90 #define REG_EMAC_TID (0x400B00B8U) /**< \brief (EMAC) Type ID Checking Register */
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91 #define REG_EMAC_USRIO (0x400B00C0U) /**< \brief (EMAC) User Input/Output Register */
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93 #define REG_EMAC_NCR (*(RwReg*)0x400B0000U) /**< \brief (EMAC) Network Control Register */
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94 #define REG_EMAC_NCFGR (*(RwReg*)0x400B0004U) /**< \brief (EMAC) Network Configuration Register */
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95 #define REG_EMAC_NSR (*(RoReg*)0x400B0008U) /**< \brief (EMAC) Network Status Register */
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96 #define REG_EMAC_TSR (*(RwReg*)0x400B0014U) /**< \brief (EMAC) Transmit Status Register */
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97 #define REG_EMAC_RBQP (*(RwReg*)0x400B0018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */
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98 #define REG_EMAC_TBQP (*(RwReg*)0x400B001CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */
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99 #define REG_EMAC_RSR (*(RwReg*)0x400B0020U) /**< \brief (EMAC) Receive Status Register */
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100 #define REG_EMAC_ISR (*(RwReg*)0x400B0024U) /**< \brief (EMAC) Interrupt Status Register */
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101 #define REG_EMAC_IER (*(WoReg*)0x400B0028U) /**< \brief (EMAC) Interrupt Enable Register */
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102 #define REG_EMAC_IDR (*(WoReg*)0x400B002CU) /**< \brief (EMAC) Interrupt Disable Register */
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103 #define REG_EMAC_IMR (*(RoReg*)0x400B0030U) /**< \brief (EMAC) Interrupt Mask Register */
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104 #define REG_EMAC_MAN (*(RwReg*)0x400B0034U) /**< \brief (EMAC) Phy Maintenance Register */
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105 #define REG_EMAC_PTR (*(RwReg*)0x400B0038U) /**< \brief (EMAC) Pause Time Register */
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106 #define REG_EMAC_PFR (*(RwReg*)0x400B003CU) /**< \brief (EMAC) Pause Frames Received Register */
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107 #define REG_EMAC_FTO (*(RwReg*)0x400B0040U) /**< \brief (EMAC) Frames Transmitted Ok Register */
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108 #define REG_EMAC_SCF (*(RwReg*)0x400B0044U) /**< \brief (EMAC) Single Collision Frames Register */
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109 #define REG_EMAC_MCF (*(RwReg*)0x400B0048U) /**< \brief (EMAC) Multiple Collision Frames Register */
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110 #define REG_EMAC_FRO (*(RwReg*)0x400B004CU) /**< \brief (EMAC) Frames Received Ok Register */
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111 #define REG_EMAC_FCSE (*(RwReg*)0x400B0050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */
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112 #define REG_EMAC_ALE (*(RwReg*)0x400B0054U) /**< \brief (EMAC) Alignment Errors Register */
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113 #define REG_EMAC_DTF (*(RwReg*)0x400B0058U) /**< \brief (EMAC) Deferred Transmission Frames Register */
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114 #define REG_EMAC_LCOL (*(RwReg*)0x400B005CU) /**< \brief (EMAC) Late Collisions Register */
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115 #define REG_EMAC_ECOL (*(RwReg*)0x400B0060U) /**< \brief (EMAC) Excessive Collisions Register */
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116 #define REG_EMAC_TUND (*(RwReg*)0x400B0064U) /**< \brief (EMAC) Transmit Underrun Errors Register */
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117 #define REG_EMAC_CSE (*(RwReg*)0x400B0068U) /**< \brief (EMAC) Carrier Sense Errors Register */
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118 #define REG_EMAC_RRE (*(RwReg*)0x400B006CU) /**< \brief (EMAC) Receive Resource Errors Register */
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119 #define REG_EMAC_ROV (*(RwReg*)0x400B0070U) /**< \brief (EMAC) Receive Overrun Errors Register */
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120 #define REG_EMAC_RSE (*(RwReg*)0x400B0074U) /**< \brief (EMAC) Receive Symbol Errors Register */
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121 #define REG_EMAC_ELE (*(RwReg*)0x400B0078U) /**< \brief (EMAC) Excessive Length Errors Register */
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122 #define REG_EMAC_RJA (*(RwReg*)0x400B007CU) /**< \brief (EMAC) Receive Jabbers Register */
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123 #define REG_EMAC_USF (*(RwReg*)0x400B0080U) /**< \brief (EMAC) Undersize Frames Register */
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124 #define REG_EMAC_STE (*(RwReg*)0x400B0084U) /**< \brief (EMAC) SQE Test Errors Register */
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125 #define REG_EMAC_RLE (*(RwReg*)0x400B0088U) /**< \brief (EMAC) Received Length Field Mismatch Register */
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126 #define REG_EMAC_HRB (*(RwReg*)0x400B0090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */
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127 #define REG_EMAC_HRT (*(RwReg*)0x400B0094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */
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128 #define REG_EMAC_SA1B (*(RwReg*)0x400B0098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */
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129 #define REG_EMAC_SA1T (*(RwReg*)0x400B009CU) /**< \brief (EMAC) Specific Address 1 Top Register */
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130 #define REG_EMAC_SA2B (*(RwReg*)0x400B00A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */
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131 #define REG_EMAC_SA2T (*(RwReg*)0x400B00A4U) /**< \brief (EMAC) Specific Address 2 Top Register */
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132 #define REG_EMAC_SA3B (*(RwReg*)0x400B00A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */
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133 #define REG_EMAC_SA3T (*(RwReg*)0x400B00ACU) /**< \brief (EMAC) Specific Address 3 Top Register */
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134 #define REG_EMAC_SA4B (*(RwReg*)0x400B00B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */
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135 #define REG_EMAC_SA4T (*(RwReg*)0x400B00B4U) /**< \brief (EMAC) Specific Address 4 Top Register */
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136 #define REG_EMAC_TID (*(RwReg*)0x400B00B8U) /**< \brief (EMAC) Type ID Checking Register */
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137 #define REG_EMAC_USRIO (*(RwReg*)0x400B00C0U) /**< \brief (EMAC) User Input/Output Register */
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138 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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140 #endif /* _SAM3XA_EMAC_INSTANCE_ */
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