4 * Copyright (c) 2012 Atmel Corporation. All rights reserved.
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10 * Redistribution and use in source and binary forms, with or without
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11 * modification, are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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16 * 2. Redistributions in binary form must reproduce the above copyright notice,
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17 * this list of conditions and the following disclaimer in the documentation
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18 * and/or other materials provided with the distribution.
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20 * 3. The name of Atmel may not be used to endorse or promote products derived
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21 * from this software without specific prior written permission.
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23 * 4. This software may only be redistributed and used in connection with an
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24 * Atmel microcontroller product.
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26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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36 * POSSIBILITY OF SUCH DAMAGE.
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42 #ifndef _SAM3XA_USART1_INSTANCE_
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43 #define _SAM3XA_USART1_INSTANCE_
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45 /* ========== Register definition for USART1 peripheral ========== */
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46 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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47 #define REG_USART1_CR (0x4009C000U) /**< \brief (USART1) Control Register */
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48 #define REG_USART1_MR (0x4009C004U) /**< \brief (USART1) Mode Register */
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49 #define REG_USART1_IER (0x4009C008U) /**< \brief (USART1) Interrupt Enable Register */
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50 #define REG_USART1_IDR (0x4009C00CU) /**< \brief (USART1) Interrupt Disable Register */
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51 #define REG_USART1_IMR (0x4009C010U) /**< \brief (USART1) Interrupt Mask Register */
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52 #define REG_USART1_CSR (0x4009C014U) /**< \brief (USART1) Channel Status Register */
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53 #define REG_USART1_RHR (0x4009C018U) /**< \brief (USART1) Receiver Holding Register */
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54 #define REG_USART1_THR (0x4009C01CU) /**< \brief (USART1) Transmitter Holding Register */
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55 #define REG_USART1_BRGR (0x4009C020U) /**< \brief (USART1) Baud Rate Generator Register */
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56 #define REG_USART1_RTOR (0x4009C024U) /**< \brief (USART1) Receiver Time-out Register */
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57 #define REG_USART1_TTGR (0x4009C028U) /**< \brief (USART1) Transmitter Timeguard Register */
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58 #define REG_USART1_FIDI (0x4009C040U) /**< \brief (USART1) FI DI Ratio Register */
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59 #define REG_USART1_NER (0x4009C044U) /**< \brief (USART1) Number of Errors Register */
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60 #define REG_USART1_IF (0x4009C04CU) /**< \brief (USART1) IrDA Filter Register */
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61 #define REG_USART1_MAN (0x4009C050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
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62 #define REG_USART1_LINMR (0x4009C054U) /**< \brief (USART1) LIN Mode Register */
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63 #define REG_USART1_LINIR (0x4009C058U) /**< \brief (USART1) LIN Identifier Register */
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64 #define REG_USART1_WPMR (0x4009C0E4U) /**< \brief (USART1) Write Protect Mode Register */
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65 #define REG_USART1_WPSR (0x4009C0E8U) /**< \brief (USART1) Write Protect Status Register */
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66 #define REG_USART1_RPR (0x4009C100U) /**< \brief (USART1) Receive Pointer Register */
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67 #define REG_USART1_RCR (0x4009C104U) /**< \brief (USART1) Receive Counter Register */
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68 #define REG_USART1_TPR (0x4009C108U) /**< \brief (USART1) Transmit Pointer Register */
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69 #define REG_USART1_TCR (0x4009C10CU) /**< \brief (USART1) Transmit Counter Register */
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70 #define REG_USART1_RNPR (0x4009C110U) /**< \brief (USART1) Receive Next Pointer Register */
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71 #define REG_USART1_RNCR (0x4009C114U) /**< \brief (USART1) Receive Next Counter Register */
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72 #define REG_USART1_TNPR (0x4009C118U) /**< \brief (USART1) Transmit Next Pointer Register */
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73 #define REG_USART1_TNCR (0x4009C11CU) /**< \brief (USART1) Transmit Next Counter Register */
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74 #define REG_USART1_PTCR (0x4009C120U) /**< \brief (USART1) Transfer Control Register */
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75 #define REG_USART1_PTSR (0x4009C124U) /**< \brief (USART1) Transfer Status Register */
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77 #define REG_USART1_CR (*(WoReg*)0x4009C000U) /**< \brief (USART1) Control Register */
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78 #define REG_USART1_MR (*(RwReg*)0x4009C004U) /**< \brief (USART1) Mode Register */
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79 #define REG_USART1_IER (*(WoReg*)0x4009C008U) /**< \brief (USART1) Interrupt Enable Register */
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80 #define REG_USART1_IDR (*(WoReg*)0x4009C00CU) /**< \brief (USART1) Interrupt Disable Register */
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81 #define REG_USART1_IMR (*(RoReg*)0x4009C010U) /**< \brief (USART1) Interrupt Mask Register */
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82 #define REG_USART1_CSR (*(RoReg*)0x4009C014U) /**< \brief (USART1) Channel Status Register */
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83 #define REG_USART1_RHR (*(RoReg*)0x4009C018U) /**< \brief (USART1) Receiver Holding Register */
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84 #define REG_USART1_THR (*(WoReg*)0x4009C01CU) /**< \brief (USART1) Transmitter Holding Register */
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85 #define REG_USART1_BRGR (*(RwReg*)0x4009C020U) /**< \brief (USART1) Baud Rate Generator Register */
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86 #define REG_USART1_RTOR (*(RwReg*)0x4009C024U) /**< \brief (USART1) Receiver Time-out Register */
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87 #define REG_USART1_TTGR (*(RwReg*)0x4009C028U) /**< \brief (USART1) Transmitter Timeguard Register */
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88 #define REG_USART1_FIDI (*(RwReg*)0x4009C040U) /**< \brief (USART1) FI DI Ratio Register */
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89 #define REG_USART1_NER (*(RoReg*)0x4009C044U) /**< \brief (USART1) Number of Errors Register */
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90 #define REG_USART1_IF (*(RwReg*)0x4009C04CU) /**< \brief (USART1) IrDA Filter Register */
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91 #define REG_USART1_MAN (*(RwReg*)0x4009C050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
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92 #define REG_USART1_LINMR (*(RwReg*)0x4009C054U) /**< \brief (USART1) LIN Mode Register */
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93 #define REG_USART1_LINIR (*(RwReg*)0x4009C058U) /**< \brief (USART1) LIN Identifier Register */
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94 #define REG_USART1_WPMR (*(RwReg*)0x4009C0E4U) /**< \brief (USART1) Write Protect Mode Register */
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95 #define REG_USART1_WPSR (*(RoReg*)0x4009C0E8U) /**< \brief (USART1) Write Protect Status Register */
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96 #define REG_USART1_RPR (*(RwReg*)0x4009C100U) /**< \brief (USART1) Receive Pointer Register */
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97 #define REG_USART1_RCR (*(RwReg*)0x4009C104U) /**< \brief (USART1) Receive Counter Register */
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98 #define REG_USART1_TPR (*(RwReg*)0x4009C108U) /**< \brief (USART1) Transmit Pointer Register */
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99 #define REG_USART1_TCR (*(RwReg*)0x4009C10CU) /**< \brief (USART1) Transmit Counter Register */
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100 #define REG_USART1_RNPR (*(RwReg*)0x4009C110U) /**< \brief (USART1) Receive Next Pointer Register */
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101 #define REG_USART1_RNCR (*(RwReg*)0x4009C114U) /**< \brief (USART1) Receive Next Counter Register */
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102 #define REG_USART1_TNPR (*(RwReg*)0x4009C118U) /**< \brief (USART1) Transmit Next Pointer Register */
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103 #define REG_USART1_TNCR (*(RwReg*)0x4009C11CU) /**< \brief (USART1) Transmit Next Counter Register */
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104 #define REG_USART1_PTCR (*(WoReg*)0x4009C120U) /**< \brief (USART1) Transfer Control Register */
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105 #define REG_USART1_PTSR (*(RoReg*)0x4009C124U) /**< \brief (USART1) Transfer Status Register */
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106 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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108 #endif /* _SAM3XA_USART1_INSTANCE_ */
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