git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_EFM32_Giant_Gecko_Simplicity_Studio/Full_Demo/RegTest.c

   1 /*\r
   2  * FreeRTOS Kernel V10.0.0\r
   3  * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software. If you wish to use our Amazon\r
  14  * FreeRTOS name, please do so in a fair use way that does not cause confusion.\r
  15  *\r
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  18  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  19  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  20  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  22  *\r
  23  * http://www.FreeRTOS.org\r
  24  * http://aws.amazon.com/freertos\r
  25  *\r
  26  * 1 tab == 4 spaces!\r
  27  */\r
  28 \r
  29 /*\r
  30  * "Reg test" tasks - These fill the registers with known values, then check\r
  31  * that each register maintains its expected value for the lifetime of the\r
  32  * task.  Each task uses a different set of values.  The reg test tasks execute\r
  33  * with a very low priority, so get preempted very frequently.  A register\r
  34  * containing an unexpected value is indicative of an error in the context\r
  35  * switching mechanism.\r
  36  */\r
  37 \r
  38 void vRegTest1Implementation( void ) __attribute__ ((naked));\r
  39 void vRegTest2Implementation( void ) __attribute__ ((naked));\r
  40 \r
  41 void vRegTest1Implementation( void )\r
  42 {\r
  43         __asm volatile\r
  44         (\r
  45                 ".extern ulRegTest1LoopCounter \n"\r
  46                 "/* Fill the core registers with known values. */               \n"\r
  47                 "mov    r0, #100                        \n"\r
  48                 "mov    r1, #101                        \n"\r
  49                 "mov    r2, #102                        \n"\r
  50                 "mov    r3, #103                        \n"\r
  51                 "mov    r4, #104                        \n"\r
  52                 "mov    r5, #105                        \n"\r
  53                 "mov    r6, #106                        \n"\r
  54                 "mov    r7, #107                        \n"\r
  55                 "mov    r8, #108                        \n"\r
  56                 "mov    r9, #109                        \n"\r
  57                 "mov    r10, #110                       \n"\r
  58                 "mov    r11, #111                       \n"\r
  59                 "mov    r12, #112                       \n"\r
  60 \r
  61         "reg1_loop:                                             \n"\r
  62 \r
  63                 "/* Check each register has maintained its expected value. */   \n"\r
  64                 "cmp    r0, #100                        \n"\r
  65                 "bne    reg1_error_loop         \n"\r
  66                 "cmp    r1, #101                        \n"\r
  67                 "bne    reg1_error_loop         \n"\r
  68                 "cmp    r2, #102                        \n"\r
  69                 "bne    reg1_error_loop         \n"\r
  70                 "cmp    r3, #103                        \n"\r
  71                 "bne    reg1_error_loop         \n"\r
  72                 "cmp    r4, #104                        \n"\r
  73                 "bne    reg1_error_loop         \n"\r
  74                 "cmp    r5, #105                        \n"\r
  75                 "bne    reg1_error_loop         \n"\r
  76                 "cmp    r6, #106                        \n"\r
  77                 "bne    reg1_error_loop         \n"\r
  78                 "cmp    r7, #107                        \n"\r
  79                 "bne    reg1_error_loop         \n"\r
  80                 "cmp    r8, #108                        \n"\r
  81                 "bne    reg1_error_loop         \n"\r
  82                 "cmp    r9, #109                        \n"\r
  83                 "bne    reg1_error_loop         \n"\r
  84                 "cmp    r10, #110                       \n"\r
  85                 "bne    reg1_error_loop         \n"\r
  86                 "cmp    r11, #111                       \n"\r
  87                 "bne    reg1_error_loop         \n"\r
  88                 "cmp    r12, #112                       \n"\r
  89                 "bne    reg1_error_loop         \n"\r
  90 \r
  91                 "/* Everything passed, increment the loop counter. */   \n"\r
  92                 "push   { r0-r1 }                       \n"\r
  93                 "ldr    r0, =ulRegTest1LoopCounter      \n"\r
  94                 "ldr    r1, [r0]                        \n"\r
  95                 "adds   r1, r1, #1                      \n"\r
  96                 "str    r1, [r0]                        \n"\r
  97                 "pop    { r0-r1 }                       \n"\r
  98 \r
  99                 "/* Start again. */                     \n"\r
 100                 "b              reg1_loop                       \n"\r
 101 \r
 102         "reg1_error_loop:                               \n"\r
 103                 "/* If this line is hit then there was an error in a core register value. \n"\r
 104                 "The loop ensures the loop counter stops incrementing. */       \n"\r
 105                 "b      reg1_error_loop                 \n"\r
 106                 "nop                                            "\r
 107         ); /* __asm volatile. */\r
 108 }\r
 109 /*-----------------------------------------------------------*/\r
 110 \r
 111 void vRegTest2Implementation( void )\r
 112 {\r
 113         __asm volatile\r
 114         (\r
 115                 ".extern ulRegTest2LoopCounter \n"\r
 116                 "/* Set all the core registers to known values. */      \n"\r
 117                 "mov    r0, #-1                         \n"\r
 118                 "mov    r1, #1                          \n"\r
 119                 "mov    r2, #2                          \n"\r
 120                 "mov    r3, #3                          \n"\r
 121                 "mov    r4, #4                          \n"\r
 122                 "mov    r5, #5                          \n"\r
 123                 "mov    r6, #6                          \n"\r
 124                 "mov    r7, #7                          \n"\r
 125                 "mov    r8, #8                          \n"\r
 126                 "mov    r9, #9                          \n"\r
 127                 "mov    r10, #10                        \n"\r
 128                 "mov    r11, #11                        \n"\r
 129                 "mov    r12, #12                        \n"\r
 130 \r
 131         "reg2_loop:                                             \n"\r
 132 \r
 133                 "cmp    r0, #-1                         \n"\r
 134                 "bne    reg2_error_loop         \n"\r
 135                 "cmp    r1, #1                          \n"\r
 136                 "bne    reg2_error_loop         \n"\r
 137                 "cmp    r2, #2                          \n"\r
 138                 "bne    reg2_error_loop         \n"\r
 139                 "cmp    r3, #3                          \n"\r
 140                 "bne    reg2_error_loop         \n"\r
 141                 "cmp    r4, #4                          \n"\r
 142                 "bne    reg2_error_loop         \n"\r
 143                 "cmp    r5, #5                          \n"\r
 144                 "bne    reg2_error_loop         \n"\r
 145                 "cmp    r6, #6                          \n"\r
 146                 "bne    reg2_error_loop         \n"\r
 147                 "cmp    r7, #7                          \n"\r
 148                 "bne    reg2_error_loop         \n"\r
 149                 "cmp    r8, #8                          \n"\r
 150                 "bne    reg2_error_loop         \n"\r
 151                 "cmp    r9, #9                          \n"\r
 152                 "bne    reg2_error_loop         \n"\r
 153                 "cmp    r10, #10                        \n"\r
 154                 "bne    reg2_error_loop         \n"\r
 155                 "cmp    r11, #11                        \n"\r
 156                 "bne    reg2_error_loop         \n"\r
 157                 "cmp    r12, #12                        \n"\r
 158                 "bne    reg2_error_loop         \n"\r
 159 \r
 160                 "/* Increment the loop counter to indicate this test is still functioning       \n"\r
 161                 "correctly. */                          \n"\r
 162                 "push   { r0-r1 }                       \n"\r
 163                 "ldr    r0, =ulRegTest2LoopCounter      \n"\r
 164                 "ldr    r1, [r0]                        \n"\r
 165                 "adds   r1, r1, #1                      \n"\r
 166                 "str    r1, [r0]                        \n"\r
 167 \r
 168                 "/* Yield to increase test coverage. */                 \n"\r
 169                 "movs   r0, #0x01                       \n"\r
 170                 "ldr    r1, =0xe000ed04 /*NVIC_INT_CTRL */              \n"\r
 171                 "lsl    r0, r0, #28 /* Shift to PendSV bit */   \n"\r
 172                 "str    r0, [r1]                        \n"\r
 173                 "dsb                                            \n"\r
 174 \r
 175                 "pop { r0-r1 }                          \n"\r
 176 \r
 177                 "/* Start again. */                     \n"\r
 178                 "b reg2_loop                            \n"\r
 179 \r
 180         "reg2_error_loop:                               \n"\r
 181                 "/* If this line is hit then there was an error in a core register value.       \n"\r
 182                 "This loop ensures the loop counter variable stops incrementing. */                     \n"\r
 183                 "b reg2_error_loop                      \n"\r
 184         ); /* __asm volatile */\r
 185 }\r
 186 /*-----------------------------------------------------------*/\r
 187 \r