1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
\r
2 <html xmlns:p="urn:schemas-microsoft-com:office:powerpoint" xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office"><head>
\r
4 <title>CMSIS: Cortex Microcontroller Software Interface Standard</title><meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
\r
5 <meta name="ProgId" content="FrontPage.Editor.Document">
\r
8 /*-----------------------------------------------------------Keil Software CHM Style Sheet
\r
9 -----------------------------------------------------------*/
\r
10 body { color: #000000; background-color: #FFFFFF; font-size: 75%; font-family: Verdana, Arial, 'Sans Serif' }
\r
11 a:link { color: #0000FF; text-decoration: underline }
\r
12 a:visited { color: #0000FF; text-decoration: underline }
\r
13 a:active { color: #FF0000; text-decoration: underline }
\r
14 a:hover { color: #FF0000; text-decoration: underline }
\r
15 h1 { font-family: Verdana; font-size: 18pt; color: #000080; font-weight: bold; text-align: Center; margin-right: 3 }
\r
16 h2 { font-family: Verdana; font-size: 14pt; color: #000080; font-weight: bold; background-color: #CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 }
\r
17 h3 { font-family: Verdana; font-size: 10pt; font-weight: bold; background-color: #CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 }
\r
18 pre { font-family: Courier New; font-size: 10pt; background-color: #CCFFCC; margin-left: 24; margin-right: 24 }
\r
19 ul { list-style-type: square; margin-top: 6pt; margin-bottom: 0 }
\r
20 ol { margin-top: 6pt; margin-bottom: 0 }
\r
21 li { clear: both; margin-bottom: 6pt }
\r
22 table { font-size: 100%; border-width: 0; padding: 0 }
\r
23 th { color: #FFFFFF; background-color: #000080; text-align: left; vertical-align: bottom; padding-right: 6pt }
\r
24 tr { text-align: left; vertical-align: top }
\r
25 td { text-align: left; vertical-align: top; padding-right: 6pt }
\r
26 .ToolT { font-size: 8pt; color: #808080 }
\r
27 .TinyT { font-size: 8pt; text-align: Center }
\r
28 code { color: #000000; background-color: #E0E0E0; font-family: 'Courier New', Courier; line-height: 120%; font-style: normal }
\r
29 /*-----------------------------------------------------------Notes
\r
30 -----------------------------------------------------------*/
\r
31 p.note { font-weight: bold; clear: both; margin-bottom: 3pt; padding-top: 6pt }
\r
32 /*-----------------------------------------------------------Expanding/Contracting Divisions
\r
33 -----------------------------------------------------------*/
\r
34 #expand { text-decoration: none; margin-bottom: 3pt }
\r
35 img.expand { border-style: none; border-width: medium }
\r
36 div.expand { display: none; margin-left: 9pt; margin-top: 0 }
\r
37 /*-----------------------------------------------------------Where List Tags
\r
38 -----------------------------------------------------------*/
\r
39 p.wh { font-weight: bold; clear: both; margin-top: 6pt; margin-bottom: 3pt }
\r
40 table.wh { width: 100% }
\r
41 td.whItem { white-space: nowrap; font-style: italic; padding-right: 6pt; padding-bottom: 6pt }
\r
42 td.whDesc { padding-bottom: 6pt }
\r
43 /*-----------------------------------------------------------Keil Table Tags
\r
44 -----------------------------------------------------------*/
\r
45 table.kt { width: 100%; border: 1pt solid #000000 }
\r
46 th.kt { white-space: nowrap; border-bottom: 1pt solid #000000; padding-left: 6pt; padding-right: 6pt; padding-top: 4pt; padding-bottom: 4pt }
\r
48 td.kt { color: #000000; background-color: #E0E0E0; border-top: 1pt solid #A0A0A0; padding-left: 6pt; padding-right: 6pt; padding-top: 2pt; padding-bottom: 2pt }
\r
49 /*----------------------------------------------------------------------------------------------------------------------*/
\r
51 background-color: #E0E0E0;
\r
59 <h1>Cortex Microcontroller Software Interface Standard</h1>
\r
61 <p align="center">This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).</p>
\r
62 <p align="center">Version: 1.30 - 30. October 2009</p>
\r
64 <p class="TinyT">Information in this file, the accompany manuals, and software is<br>
\r
65 Copyright © ARM Ltd.<br>All rights reserved.
\r
70 <p><span style="FONT-WEIGHT: bold">Revision History</span></p>
\r
72 <li>Version 1.00: initial release. </li>
\r
73 <li>Version 1.01: added __LDREX<em>x</em>, __STREX<em>x</em>, and __CLREX.</li>
\r
74 <li>Version 1.02: added Cortex-M0. </li>
\r
75 <li>Version 1.10: second review. </li>
\r
76 <li>Version 1.20: third review. </li>
\r
77 <li>Version 1.30 PRE-RELEASE: reworked Startup Concept, additional Debug Functionality.</li>
\r
78 <li>Version 1.30 2nd PRE-RELEASE: changed folder structure, added doxyGen comments, added Bit definitions.</li>
\r
79 <li>Version 1.30: updated Device Support Packages.</li>
\r
87 <li class="LI2"><a href="#1">About</a></li>
\r
88 <li class="LI2"><a href="#2">Coding Rules and Conventions</a></li>
\r
89 <li class="LI2"><a href="#3">CMSIS Files</a></li>
\r
90 <li class="LI2"><a href="#4">Core Peripheral Access Layer</a></li>
\r
91 <li class="LI2"><a href="#5">CMSIS Example</a></li>
\r
94 <h2><a name="1"></a>About</h2>
\r
97 The <strong>Cortex Microcontroller Software Interface Standard (CMSIS)</strong> answers the challenges
\r
98 that are faced when software components are deployed to physical microcontroller devices based on a
\r
99 Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M
\r
100 processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation
\r
101 with various silicon and software vendors and provides a common approach to interface to peripherals,
\r
102 real-time operating systems, and middleware components.
\r
105 <p>ARM provides as part of the CMSIS the following software layers that are
\r
106 available for various compiler implementations:</p>
\r
108 <li><strong>Core Peripheral Access Layer</strong>: contains name definitions,
\r
109 address definitions and helper functions to
\r
110 access core registers and peripherals. It defines also a device
\r
111 independent interface for RTOS Kernels that includes debug channel
\r
115 <p>These software layers are expanded by Silicon partners with:</p>
\r
117 <li><strong>Device Peripheral Access Layer</strong>: provides definitions
\r
118 for all device peripherals</li>
\r
119 <li><strong>Access Functions for Peripherals (optional)</strong>: provides
\r
120 additional helper functions for peripherals</li>
\r
123 <p>CMSIS defines for a Cortex-M Microcontroller System:</p>
\r
125 <li style="text-align: left;">A common way to access peripheral registers
\r
126 and a common way to define exception vectors.</li>
\r
127 <li style="text-align: left;">The register names of the <strong>Core
\r
128 Peripherals</strong> and<strong> </strong>the names of the <strong>Core
\r
129 Exception Vectors</strong>.</li>
\r
130 <li>An device independent interface for RTOS Kernels including a debug
\r
135 By using CMSIS compliant software components, the user can easier re-use template code.
\r
136 CMSIS is intended to enable the combination of software components from multiple middleware vendors.
\r
139 <h2><a name="2"></a>Coding Rules and Conventions</h2>
\r
142 The following section describes the coding rules and conventions used in the CMSIS
\r
143 implementation. It contains also information about data types and version number information.
\r
146 <h3>Essentials</h3>
\r
148 <li>The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations,
\r
149 there are disable and enable sequences for PC-LINT inserted.</li>
\r
150 <li>ANSI standard data types defined in the ANSI C header file
\r
151 <strong><stdint.h></strong> are used.</li>
\r
152 <li>#define constants that include expressions must be enclosed by
\r
154 <li>Variables and parameters have a complete data type.</li>
\r
155 <li>All functions in the <strong>Core Peripheral Access Layer</strong> are
\r
157 <li>The <strong>Core Peripheral Access Layer</strong> has no blocking code
\r
158 (which means that wait/query loops are done at other software layers).</li>
\r
159 <li>For each exception/interrupt there is definition for:
\r
161 <li>an exception/interrupt handler with the postfix <strong>_Handler </strong>
\r
162 (for exceptions) or <strong>_IRQHandler</strong> (for interrupts).</li>
\r
163 <li>a default exception/interrupt handler (weak definition) that contains an endless loop.</li>
\r
164 <li>a #define of the interrupt number with the postfix <strong>_IRQn</strong>.</li>
\r
168 <h3>Recommendations</h3>
\r
170 <p>The CMSIS recommends the following conventions for identifiers.</p>
\r
172 <li><strong>CAPITAL</strong> names to identify Core Registers, Peripheral Registers, and CPU Instructions.</li>
\r
173 <li><strong>CamelCase</strong> names to identify peripherals access functions and interrupts.</li>
\r
174 <li><strong>PERIPHERAL_</strong> prefix to identify functions that belong to specify peripherals.</li>
\r
175 <li><strong>Doxygen</strong> comments for all functions are included as described under <strong>Function Comments</strong> below.</li>
\r
181 <li>Comments use the ANSI C90 style (<em>/* comment */</em>) or C++ style
\r
182 (<em>// comment</em>). It is assumed that the programming tools support today
\r
183 consistently the C++ comment style.</li>
\r
184 <li><strong>Function Comments</strong> provide for each function the following information:
\r
186 <li>one-line brief function overview.</li>
\r
187 <li>detailed parameter explanation.</li>
\r
188 <li>detailed information about return values.</li>
\r
189 <li>detailed description of the actual function.</li>
\r
191 <p><b>Doxygen Example:</b></p>
\r
194 * @brief Enable Interrupt in NVIC Interrupt Controller
\r
195 * @param IRQn interrupt number that specifies the interrupt
\r
197 * Enable the specified interrupt in the NVIC Interrupt Controller.
\r
198 * Other settings of the interrupt such as priority are not affected.
\r
203 <h3>Data Types and IO Type Qualifiers</h3>
\r
206 The <strong>Cortex-M HAL</strong> uses the standard types from the standard ANSI C header file
\r
207 <strong><stdint.h></strong>. <strong>IO Type Qualifiers</strong> are used to specify the access
\r
208 to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of
\r
209 debug information of peripheral registers.
\r
212 <table class="kt" border="0" cellpadding="0" cellspacing="0">
\r
215 <th class="kt" nowrap="nowrap">IO Type Qualifier</th>
\r
216 <th class="kt">#define</th>
\r
217 <th class="kt">Description</th>
\r
220 <td class="kt" nowrap="nowrap">__I</td>
\r
221 <td class="kt">volatile const</td>
\r
222 <td class="kt">Read access only</td>
\r
225 <td class="kt" nowrap="nowrap">__O</td>
\r
226 <td class="kt">volatile</td>
\r
227 <td class="kt">Write access only</td>
\r
230 <td class="kt" nowrap="nowrap">__IO</td>
\r
231 <td class="kt">volatile</td>
\r
232 <td class="kt">Read and write access</td>
\r
237 <h3>CMSIS Version Number</h3>
\r
239 File <strong>core_cm3.h</strong> contains the version number of the CMSIS with the following define:
\r
243 #define __CM3_CMSIS_VERSION_MAIN (0x01) /* [31:16] main version */
\r
244 #define __CM3_CMSIS_VERSION_SUB (0x30) /* [15:0] sub version */
\r
245 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)</pre>
\r
248 File <strong>core_cm0.h</strong> contains the version number of the CMSIS with the following define:
\r
252 #define __CM0_CMSIS_VERSION_MAIN (0x01) /* [31:16] main version */
\r
253 #define __CM0_CMSIS_VERSION_SUB (0x30) /* [15:0] sub version */
\r
254 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)</pre>
\r
257 <h3>CMSIS Cortex Core</h3>
\r
259 File <strong>core_cm3.h</strong> contains the type of the CMSIS Cortex-M with the following define:
\r
263 #define __CORTEX_M (0x03)</pre>
\r
266 File <strong>core_cm0.h</strong> contains the type of the CMSIS Cortex-M with the following define:
\r
270 #define __CORTEX_M (0x00)</pre>
\r
273 <h2><a name="3"></a>CMSIS Files</h2>
\r
275 This section describes the Files provided in context with the CMSIS to access the Cortex-M
\r
276 hardware and peripherals.
\r
279 <table class="kt" border="0" cellpadding="0" cellspacing="0">
\r
282 <th class="kt" nowrap="nowrap">File</th>
\r
283 <th class="kt">Provider</th>
\r
284 <th class="kt">Description</th>
\r
287 <td class="kt" nowrap="nowrap"><i>device.h</i></td>
\r
288 <td class="kt">Device specific (provided by silicon partner)</td>
\r
289 <td class="kt">Defines the peripherals for the actual device. The file may use
\r
290 several other include files to define the peripherals of the actual device.</td>
\r
293 <td class="kt" nowrap="nowrap">core_cm0.h</td>
\r
294 <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
\r
295 <td class="kt">Defines the core peripherals for the Cortex-M0 CPU and core peripherals.</td>
\r
298 <td class="kt" nowrap="nowrap">core_cm3.h</td>
\r
299 <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
\r
300 <td class="kt">Defines the core peripherals for the Cortex-M3 CPU and core peripherals.</td>
\r
303 <td class="kt" nowrap="nowrap">core_cm0.c</td>
\r
304 <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
\r
305 <td class="kt">Provides helper functions that access core registers.</td>
\r
308 <td class="kt" nowrap="nowrap">core_cm3.c</td>
\r
309 <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
\r
310 <td class="kt">Provides helper functions that access core registers.</td>
\r
313 <td class="kt" nowrap="nowrap">startup<i>_device</i></td>
\r
314 <td class="kt">ARM (adapted by compiler partner / silicon partner)</td>
\r
315 <td class="kt">Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table</td>
\r
318 <td class="kt" nowrap="nowrap">system<i>_device</i></td>
\r
319 <td class="kt">ARM (adapted by silicon partner)</td>
\r
320 <td class="kt">Provides a device specific configuration file for the device. It configures the device initializes
\r
321 typically the oscillator (PLL) that is part of the microcontroller device</td>
\r
326 <h3><em>device.h</em></h3>
\r
329 The file <em><strong>device.h</strong></em> is provided by the silicon vendor and is the
\r
330 <u><strong>central include file</strong></u> that the application programmer is using in
\r
331 the C source code. This file contains:
\r
335 <p><strong>Interrupt Number Definition</strong>: provides interrupt numbers
\r
336 (IRQn) for all core and device specific exceptions and interrupts.</p>
\r
339 <p><strong>Configuration for core_cm0.h / core_cm3.h</strong>: reflects the
\r
340 actual configuration of the Cortex-M processor that is part of the actual
\r
341 device. As such the file <strong>core_cm0.h / core_cm3.h</strong> is included that
\r
342 implements access to processor registers and core peripherals. </p>
\r
345 <p><strong>Device Peripheral Access Layer</strong>: provides definitions
\r
346 for all device peripherals. It contains all data structures and the address
\r
347 mapping for the device specific peripherals. </p>
\r
349 <li><strong>Access Functions for Peripherals (optional)</strong>: provides
\r
350 additional helper functions for peripherals that are useful for programming
\r
351 of these peripherals. Access Functions may be provided as inline functions
\r
352 or can be extern references to a device specific library provided by the
\r
353 silicon vendor.</li>
\r
357 <h4><strong>Interrupt Number Definition</strong></h4>
\r
359 <p>To access the device specific interrupts the device.h file defines IRQn
\r
360 numbers for the complete device using a enum typedef as shown below:</p>
\r
364 /****** Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
\r
365 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
\r
366 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
\r
367 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
\r
368 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
\r
369 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
\r
370 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
\r
371 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
\r
372 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
\r
373 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
\r
374 /****** STM32 specific Interrupt Numbers ****************************************************************/
\r
375 WWDG_STM_IRQn = 0, /*!< Window WatchDog Interrupt */
\r
376 PVD_STM_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
\r
382 <h4>Configuration for core_cm0.h / core_cm3.h</h4>
\r
384 The Cortex-M core configuration options which are defined for each device implementation. Some
\r
385 configuration options are reflected in the CMSIS layer using the #define settings described below.
\r
388 To access core peripherals file <em><strong>device.h</strong></em> includes file <b>core_cm0.h / core_cm3.h</b>.
\r
389 Several features in <strong>core_cm0.h / core_cm3.h</strong> are configured by the following defines that must be
\r
390 defined before <strong>#include <core_cm0.h></strong> / <strong>#include <core_cm3.h></strong>
\r
391 preprocessor command.
\r
394 <table class="kt" border="0" cellpadding="0" cellspacing="0">
\r
397 <th class="kt" nowrap="nowrap">#define</th>
\r
398 <th class="kt" nowrap="nowrap">File</th>
\r
399 <th class="kt" nowrap="nowrap">Value</th>
\r
400 <th class="kt">Description</th>
\r
403 <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td>
\r
404 <td class="kt">core_cm0.h</td>
\r
405 <td class="kt" nowrap="nowrap">(2)</td>
\r
406 <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td>
\r
409 <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td>
\r
410 <td class="kt">core_cm3.h</td>
\r
411 <td class="kt" nowrap="nowrap">(2 ... 8)</td>
\r
412 <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td>
\r
415 <td class="kt" nowrap="nowrap">__MPU_PRESENT</td>
\r
416 <td class="kt">core_cm0.h, core_cm3.h</td>
\r
417 <td class="kt" nowrap="nowrap">(0, 1)</td>
\r
418 <td class="kt">Defines if an MPU is present or not</td>
\r
421 <td class="kt" nowrap="nowrap">__Vendor_SysTickConfig</td>
\r
422 <td class="kt">core_cm0.h, core_cm3.h</td>
\r
423 <td class="kt" nowrap="nowrap">(1)</td>
\r
424 <td class="kt">When this define is setup to 1, the <strong>SysTickConfig</strong> function
\r
425 in <strong>core_cm3.h</strong> is excluded. In this case the <em><strong>device.h</strong></em>
\r
426 file must contain a vendor specific implementation of this function.</td>
\r
432 <h4>Device Peripheral Access Layer</h4>
\r
434 Each peripheral uses a prefix which consists of <strong><device abbreviation>_</strong>
\r
435 and <strong><peripheral name>_</strong> to identify peripheral registers that access this
\r
436 specific peripheral. The intention of this is to avoid name collisions caused
\r
437 due to short names. If more than one peripheral of the same type exists,
\r
438 identifiers have a postfix (digit or letter). For example:
\r
441 <li><device abbreviation>_UART_Type: defines the generic register layout for all UART channels in a device.
\r
446 __I uint8_t RBR; /*!< Offset: 0x000 Receiver Buffer Register */
\r
447 __O uint8_t THR; /*!< Offset: 0x000 Transmit Holding Register */
\r
448 __IO uint8_t DLL; /*!< Offset: 0x000 Divisor Latch LSB */
\r
449 uint32_t RESERVED0;
\r
452 __IO uint8_t DLM; /*!< Offset: 0x004 Divisor Latch MSB */
\r
453 __IO uint32_t IER; /*!< Offset: 0x004 Interrupt Enable Register */
\r
456 __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register */
\r
457 __O uint8_t FCR; /*!< Offset: 0x008 FIFO Control Register */
\r
459 __IO uint8_t LCR; /*!< Offset: 0x00C Line Control Register */
\r
460 uint8_t RESERVED1[7];
\r
461 __I uint8_t LSR; /*!< Offset: 0x014 Line Status Register */
\r
462 uint8_t RESERVED2[7];
\r
463 __IO uint8_t SCR; /*!< Offset: 0x01C Scratch Pad Register */
\r
464 uint8_t RESERVED3[3];
\r
465 __IO uint32_t ACR; /*!< Offset: 0x020 Autobaud Control Register */
\r
466 __IO uint8_t ICR; /*!< Offset: 0x024 IrDA Control Register */
\r
467 uint8_t RESERVED4[3];
\r
468 __IO uint8_t FDR; /*!< Offset: 0x028 Fractional Divider Register */
\r
469 uint8_t RESERVED5[7];
\r
470 __IO uint8_t TER; /*!< Offset: 0x030 Transmit Enable Register */
\r
471 uint8_t RESERVED6[39];
\r
472 __I uint8_t FIFOLVL; /*!< Offset: 0x058 FIFO Level Register */
\r
473 } LPC_UART_TypeDef;</pre>
\r
475 <li><device abbreviation>_UART1: is a pointer to a register structure that refers to a specific UART.
\r
476 For example UART1->DR is the data register of UART1.
\r
478 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
\r
479 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )</pre>
\r
483 <h5>Minimal Requiements</h5>
\r
485 To access the peripheral registers and related function in a device the files <strong><em>device.h</em></strong>
\r
486 and <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong> defines as a minimum:
\r
489 <li>The <strong>Register Layout Typedef</strong> for each peripheral that defines all register names.
\r
490 Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of
\r
491 the peripheral registers. For example:
\r
494 __IO uint32_t CTRL; /* SysTick Control and Status Register */
\r
495 __IO uint32_t LOAD; /* SysTick Reload Value Register */
\r
496 __IO uint32_t VAL; /* SysTick Current Value Register */
\r
497 __I uint32_t CALIB; /* SysTick Calibration Register */
\r
498 } SysTick_Type;</pre>
\r
502 <strong>Base Address</strong> for each peripheral (in case of multiple peripherals
\r
503 that use the same <strong>register layout typedef</strong> multiple base addresses are defined). For example:
\r
505 #define SysTick_BASE (SCS_BASE + 0x0010) /* SysTick Base Address */</pre>
\r
509 <strong>Access Definition</strong> for each peripheral (in case of multiple peripherals that use
\r
510 the same <strong>register layout typedef</strong> multiple access definitions exist, i.e. LPC_UART0,
\r
511 LPC_UART2). For Example:
\r
513 #define SysTick ((SysTick_Type *) SysTick_BASE) /* SysTick access definition */</pre>
\r
518 These definitions allow to access the peripheral registers from user code with simple assignments like:
\r
520 <pre>SysTick->CTRL = 0;</pre>
\r
522 <h5>Optional Features</h5>
\r
523 <p>In addition the <em> <strong>device.h </strong></em>file may define:</p>
\r
526 #define constants that simplify access to the peripheral registers.
\r
527 These constant define bit-positions or other specific patterns are that required for the
\r
528 programming of the peripheral registers. The identifiers used start with
\r
529 <strong><device abbreviation>_</strong> and <strong><peripheral name>_</strong>.
\r
530 It is recommended to use CAPITAL letters for such #define constants.
\r
533 Functions that perform more complex functions with the peripheral (i.e. status query before
\r
534 a sending register is accessed). Again these function start with
\r
535 <strong><device abbreviation>_</strong> and <strong><peripheral name>_</strong>.
\r
539 <h3>core_cm0.h and core_cm0.c</h3>
\r
541 File <b>core_cm0.h</b> describes the data structures for the Cortex-M0 core peripherals and does
\r
542 the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers
\r
543 and core peripherals with efficient functions (defined as <strong>static inline</strong>).
\r
546 File <b>core_cm0.c</b> defines several helper functions that access processor registers.
\r
548 <p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M0.</p>
\r
550 <h3>core_cm3.h and core_cm3.c</h3>
\r
552 File <b>core_cm3.h</b> describes the data structures for the Cortex-M3 core peripherals and does
\r
553 the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers
\r
554 and core peripherals with efficient functions (defined as <strong>static inline</strong>).
\r
557 File <b>core_cm3.c</b> defines several helper functions that access processor registers.
\r
559 <p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M3.</p>
\r
561 <h3>startup_<em>device</em></h3>
\r
563 A template file for <strong>startup_<em>device</em></strong> is provided by ARM for each supported
\r
564 compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific
\r
565 interrupt handlers. Each interrupt handler is defined as <strong><em>weak</em></strong> function
\r
566 to an dummy handler. Therefore the interrupt handler can be directly used in application software
\r
567 without any requirements to adapt the <strong>startup_<em>device</em></strong> file.
\r
570 The following exception names are fixed and define the start of the vector table for a Cortex-M0:
\r
573 __Vectors DCD __initial_sp ; Top of Stack
\r
574 DCD Reset_Handler ; Reset Handler
\r
575 DCD NMI_Handler ; NMI Handler
\r
576 DCD HardFault_Handler ; Hard Fault Handler
\r
584 DCD SVC_Handler ; SVCall Handler
\r
587 DCD PendSV_Handler ; PendSV Handler
\r
588 DCD SysTick_Handler ; SysTick Handler</pre>
\r
591 The following exception names are fixed and define the start of the vector table for a Cortex-M3:
\r
594 __Vectors DCD __initial_sp ; Top of Stack
\r
595 DCD Reset_Handler ; Reset Handler
\r
596 DCD NMI_Handler ; NMI Handler
\r
597 DCD HardFault_Handler ; Hard Fault Handler
\r
598 DCD MemManage_Handler ; MPU Fault Handler
\r
599 DCD BusFault_Handler ; Bus Fault Handler
\r
600 DCD UsageFault_Handler ; Usage Fault Handler
\r
605 DCD SVC_Handler ; SVCall Handler
\r
606 DCD DebugMon_Handler ; Debug Monitor Handler
\r
608 DCD PendSV_Handler ; PendSV Handler
\r
609 DCD SysTick_Handler ; SysTick Handler</pre>
\r
612 In the following examples for device specific interrupts are shown:
\r
615 ; External Interrupts
\r
616 DCD WWDG_IRQHandler ; Window Watchdog
\r
617 DCD PVD_IRQHandler ; PVD through EXTI Line detect
\r
618 DCD TAMPER_IRQHandler ; Tamper</pre>
\r
621 Device specific interrupts must have a dummy function that can be overwritten in user code.
\r
622 Below is an example for this dummy function.
\r
625 Default_Handler PROC
\r
626 EXPORT WWDG_IRQHandler [WEAK]
\r
627 EXPORT PVD_IRQHandler [WEAK]
\r
628 EXPORT TAMPER_IRQHandler [WEAK]
\r
640 The user application may simply define an interrupt handler function by using the handler name
\r
644 void WWDG_IRQHandler(void)
\r
651 <h3><a name="4"></a>system_<em>device</em>.c</h3>
\r
653 A template file for <strong>system_<em>device</em>.c</strong> is provided by ARM but adapted by
\r
654 the silicon vendor to match their actual device. As a <strong>minimum requirement</strong>
\r
655 this file must provide a device specific system configuration function and a global variable
\r
656 that contains the system frequency. It configures the device and initializes typically the
\r
657 oscillator (PLL) that is part of the microcontroller device.
\r
660 The file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong> must provide
\r
661 as a minimum requirement the SystemInit function as shown below.
\r
664 <table class="kt" border="0" cellpadding="0" cellspacing="0">
\r
667 <th class="kt">Function Definition</th>
\r
668 <th class="kt">Description</th>
\r
671 <td class="kt" nowrap="nowrap">void SystemInit (void)</td>
\r
672 <td class="kt">Setup the microcontroller system. Typically this function configures the
\r
673 oscillator (PLL) that is part of the microcontroller device. For systems
\r
674 with variable clock speed it also updates the variable SystemCoreClock.<br>
\r
675 SystemInit is called from startup<i>_device</i> file.</td>
\r
678 <td class="kt" nowrap="nowrap">void SystemCoreClockUpdate (void)</td>
\r
679 <td class="kt">Updates the variable SystemCoreClock and must be called whenever the
\r
680 core clock is changed during program execution. SystemCoreClockUpdate()
\r
681 evaluates the clock register settings and calculates the current core clock.
\r
688 Also part of the file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong>
\r
689 is the variable <strong>SystemCoreClock</strong> which contains the current CPU clock speed shown below.
\r
692 <table class="kt" border="0" cellpadding="0" cellspacing="0">
\r
695 <th class="kt">Variable Definition</th>
\r
696 <th class="kt">Description</th>
\r
699 <td class="kt" nowrap="nowrap">uint32_t SystemCoreClock</td>
\r
700 <td class="kt">Contains the system core clock (which is the system clock frequency supplied
\r
701 to the SysTick timer and the processor core clock). This variable can be
\r
702 used by the user application to setup the SysTick timer or configure other
\r
703 parameters. It may also be used by debugger to query the frequency of the
\r
704 debug timer or configure the trace clock speed.<br>
\r
705 SystemCoreClock is initialized with a correct predefined value.<br><br>
\r
706 The compiler must be configured to avoid the removal of this variable in
\r
707 case that the application program is not using it. It is important for
\r
708 debug systems that the variable is physically present in memory so that
\r
709 it can be examined to configure the debugger.</td>
\r
714 <p class="Note">Note</p>
\r
716 <li><p>The above definitions are the minimum requirements for the file <strong>
\r
717 system_</strong><em><strong>device</strong></em><strong>.c</strong>. This
\r
718 file may export more functions or variables that provide a more flexible
\r
719 configuration of the microcontroller system.</p>
\r
724 <h2>Core Peripheral Access Layer</h2>
\r
726 <h3>Cortex-M Core Register Access</h3>
\r
728 The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>
\r
729 and provide access to Cortex-M core registers.
\r
732 <table class="kt" border="0" cellpadding="0" cellspacing="0">
\r
735 <th class="kt">Function Definition</th>
\r
736 <th class="kt">Core</th>
\r
737 <th class="kt">Core Register</th>
\r
738 <th class="kt">Description</th>
\r
741 <td class="kt" nowrap="nowrap">void __enable_irq (void)</td>
\r
742 <td class="kt">M0, M3</td>
\r
743 <td class="kt">PRIMASK = 0</td>
\r
744 <td class="kt">Global Interrupt enable (using the instruction <strong>CPSIE
\r
748 <td class="kt" nowrap="nowrap">void __disable_irq (void)</td>
\r
749 <td class="kt">M0, M3</td>
\r
750 <td class="kt">PRIMASK = 1</td>
\r
751 <td class="kt">Global Interrupt disable (using the instruction <strong>
\r
752 CPSID i</strong>)</td>
\r
755 <td class="kt" nowrap="nowrap">void __set_PRIMASK (uint32_t value)</td>
\r
756 <td class="kt">M0, M3</td>
\r
757 <td class="kt">PRIMASK = value</td>
\r
758 <td class="kt">Assign value to Priority Mask Register (using the instruction
\r
759 <strong>MSR</strong>)</td>
\r
762 <td class="kt" nowrap="nowrap">uint32_t __get_PRIMASK (void)</td>
\r
763 <td class="kt">M0, M3</td>
\r
764 <td class="kt">return PRIMASK</td>
\r
765 <td class="kt">Return Priority Mask Register (using the instruction
\r
766 <strong>MRS</strong>)</td>
\r
769 <td class="kt" nowrap="nowrap">void __enable_fault_irq (void)</td>
\r
770 <td class="kt">M3</td>
\r
771 <td class="kt">FAULTMASK = 0</td>
\r
772 <td class="kt">Global Fault exception and Interrupt enable (using the
\r
773 instruction <strong>CPSIE
\r
777 <td class="kt" nowrap="nowrap">void __disable_fault_irq (void)</td>
\r
778 <td class="kt">M3</td>
\r
779 <td class="kt">FAULTMASK = 1</td>
\r
780 <td class="kt">Global Fault exception and Interrupt disable (using the
\r
781 instruction <strong>CPSID f</strong>)</td>
\r
784 <td class="kt" nowrap="nowrap">void __set_FAULTMASK (uint32_t value)</td>
\r
785 <td class="kt">M3</td>
\r
786 <td class="kt">FAULTMASK = value</td>
\r
787 <td class="kt">Assign value to Fault Mask Register (using the instruction
\r
788 <strong>MSR</strong>)</td>
\r
791 <td class="kt" nowrap="nowrap">uint32_t __get_FAULTMASK (void)</td>
\r
792 <td class="kt">M3</td>
\r
793 <td class="kt">return FAULTMASK</td>
\r
794 <td class="kt">Return Fault Mask Register (using the instruction <strong>MRS</strong>)</td>
\r
797 <td class="kt" nowrap="nowrap">void __set_BASEPRI (uint32_t value)</td>
\r
798 <td class="kt">M3</td>
\r
799 <td class="kt">BASEPRI = value</td>
\r
800 <td class="kt">Set Base Priority (using the instruction <strong>MSR</strong>)</td>
\r
803 <td class="kt" nowrap="nowrap">uiuint32_t __get_BASEPRI (void)</td>
\r
804 <td class="kt">M3</td>
\r
805 <td class="kt">return BASEPRI</td>
\r
806 <td class="kt">Return Base Priority (using the instruction <strong>MRS</strong>)</td>
\r
809 <td class="kt" nowrap="nowrap">void __set_CONTROL (uint32_t value)</td>
\r
810 <td class="kt">M0, M3</td>
\r
811 <td class="kt">CONTROL = value</td>
\r
812 <td class="kt">Set CONTROL register value (using the instruction <strong>MSR</strong>)</td>
\r
815 <td class="kt" nowrap="nowrap">uint32_t __get_CONTROL (void)</td>
\r
816 <td class="kt">M0, M3</td>
\r
817 <td class="kt">return CONTROL</td>
\r
818 <td class="kt">Return Control Register Value (using the instruction
\r
819 <strong>MRS</strong>)</td>
\r
822 <td class="kt" nowrap="nowrap">void __set_PSP (uint32_t TopOfProcStack)</td>
\r
823 <td class="kt">M0, M3</td>
\r
824 <td class="kt">PSP = TopOfProcStack</td>
\r
825 <td class="kt">Set Process Stack Pointer value (using the instruction
\r
826 <strong>MSR</strong>)</td>
\r
829 <td class="kt" nowrap="nowrap">uint32_t __get_PSP (void)</td>
\r
830 <td class="kt">M0, M3</td>
\r
831 <td class="kt">return PSP</td>
\r
832 <td class="kt">Return Process Stack Pointer (using the instruction <strong>MRS</strong>)</td>
\r
835 <td class="kt" nowrap="nowrap">void __set_MSP (uint32_t TopOfMainStack)</td>
\r
836 <td class="kt">M0, M3</td>
\r
837 <td class="kt">MSP = TopOfMainStack</td>
\r
838 <td class="kt">Set Main Stack Pointer (using the instruction <strong>MSR</strong>)</td>
\r
841 <td class="kt" nowrap="nowrap">uint32_t __get_MSP (void)</td>
\r
842 <td class="kt">M0, M3</td>
\r
843 <td class="kt">return MSP</td>
\r
844 <td class="kt">Return Main Stack Pointer (using the instruction <strong>MRS</strong>)</td>
\r
849 <h3>Cortex-M Instruction Access</h3>
\r
851 The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>and
\r
852 generate specific Cortex-M instructions. The functions are implemented in the file
\r
853 <strong>core_cm0.c</strong> / <strong>core_cm3.c</strong>.
\r
856 <table class="kt" border="0" cellpadding="0" cellspacing="0">
\r
859 <th class="kt">Name</th>
\r
860 <th class="kt">Core</th>
\r
861 <th class="kt">Generated CPU Instruction</th>
\r
862 <th class="kt">Description</th>
\r
865 <td class="kt" nowrap="nowrap">void __NOP (void)</td>
\r
866 <td class="kt">M0, M3</td>
\r
867 <td class="kt">NOP</td>
\r
868 <td class="kt">No Operation</td>
\r
871 <td class="kt" nowrap="nowrap">void __WFI (void)</td>
\r
872 <td class="kt">M0, M3</td>
\r
873 <td class="kt">WFI</td>
\r
874 <td class="kt">Wait for Interrupt</td>
\r
877 <td class="kt" nowrap="nowrap">void __WFE (void)</td>
\r
878 <td class="kt">M0, M3</td>
\r
879 <td class="kt">WFE</td>
\r
880 <td class="kt">Wait for Event</td>
\r
883 <td class="kt" nowrap="nowrap">void __SEV (void)</td>
\r
884 <td class="kt">M0, M3</td>
\r
885 <td class="kt">SEV</td>
\r
886 <td class="kt">Set Event</td>
\r
889 <td class="kt" nowrap="nowrap">void __ISB (void)</td>
\r
890 <td class="kt">M0, M3</td>
\r
891 <td class="kt">ISB</td>
\r
892 <td class="kt">Instruction Synchronization Barrier</td>
\r
895 <td class="kt" nowrap="nowrap">void __DSB (void)</td>
\r
896 <td class="kt">M0, M3</td>
\r
897 <td class="kt">DSB</td>
\r
898 <td class="kt">Data Synchronization Barrier</td>
\r
901 <td class="kt" nowrap="nowrap">void __DMB (void)</td>
\r
902 <td class="kt">M0, M3</td>
\r
903 <td class="kt">DMB</td>
\r
904 <td class="kt">Data Memory Barrier</td>
\r
907 <td class="kt" nowrap="nowrap">uint32_t __REV (uint32_t value)</td>
\r
908 <td class="kt">M0, M3</td>
\r
909 <td class="kt">REV</td>
\r
910 <td class="kt">Reverse byte order in integer value.</td>
\r
913 <td class="kt" nowrap="nowrap">uint32_t __REV16 (uint16_t value)</td>
\r
914 <td class="kt">M0, M3</td>
\r
915 <td class="kt">REV16</td>
\r
916 <td class="kt">Reverse byte order in unsigned short value. </td>
\r
919 <td class="kt" nowrap="nowrap">sint32_t __REVSH (sint16_t value)</td>
\r
920 <td class="kt">M0, M3</td>
\r
921 <td class="kt">REVSH</td>
\r
922 <td class="kt">Reverse byte order in signed short value with sign extension to integer.</td>
\r
925 <td class="kt" nowrap="nowrap">uint32_t __RBIT (uint32_t value)</td>
\r
926 <td class="kt">M3</td>
\r
927 <td class="kt">RBIT</td>
\r
928 <td class="kt">Reverse bit order of value</td>
\r
931 <td class="kt" nowrap="nowrap">uint8_t __LDREXB (uint8_t *addr)</td>
\r
932 <td class="kt">M3</td>
\r
933 <td class="kt">LDREXB</td>
\r
934 <td class="kt">Load exclusive byte</td>
\r
937 <td class="kt" nowrap="nowrap">uint16_t __LDREXH (uint16_t *addr)</td>
\r
938 <td class="kt">M3</td>
\r
939 <td class="kt">LDREXH</td>
\r
940 <td class="kt">Load exclusive half-word</td>
\r
943 <td class="kt" nowrap="nowrap">uint32_t __LDREXW (uint32_t *addr)</td>
\r
944 <td class="kt">M3</td>
\r
945 <td class="kt">LDREXW</td>
\r
946 <td class="kt">Load exclusive word</td>
\r
949 <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint8_t value, uint8_t *addr)</td>
\r
950 <td class="kt">M3</td>
\r
951 <td class="kt">STREXB</td>
\r
952 <td class="kt">Store exclusive byte</td>
\r
955 <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint16_t value, uint16_t *addr)</td>
\r
956 <td class="kt">M3</td>
\r
957 <td class="kt">STREXH</td>
\r
958 <td class="kt">Store exclusive half-word</td>
\r
961 <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint32_t value, uint32_t *addr)</td>
\r
962 <td class="kt">M3</td>
\r
963 <td class="kt">STREXW</td>
\r
964 <td class="kt">Store exclusive word</td>
\r
967 <td class="kt" nowrap="nowrap">void __CLREX (void)</td>
\r
968 <td class="kt">M3</td>
\r
969 <td class="kt">CLREX</td>
\r
970 <td class="kt">Remove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW</td>
\r
976 <h3>NVIC Access Functions</h3>
\r
978 The CMSIS provides access to the NVIC via the register interface structure and several helper
\r
979 functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to
\r
980 identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative
\r
981 IRQn values are used for processor core exceptions.
\r
984 For the IRQn values of core exceptions the file <strong><em>device.h</em></strong> provides
\r
985 the following enum names.
\r
988 <table class="kt" border="0" cellpadding="0" cellspacing="0">
\r
991 <th class="kt" nowrap="nowrap">Core Exception enum Value</th>
\r
992 <th class="kt">Core</th>
\r
993 <th class="kt">IRQn</th>
\r
994 <th class="kt">Description</th>
\r
997 <td class="kt" nowrap="nowrap">NonMaskableInt_IRQn</td>
\r
998 <td class="kt">M0, M3</td>
\r
999 <td class="kt">-14</td>
\r
1000 <td class="kt">Cortex-M Non Maskable Interrupt</td>
\r
1003 <td class="kt" nowrap="nowrap">HardFault_IRQn</td>
\r
1004 <td class="kt">M0, M3</td>
\r
1005 <td class="kt">-13</td>
\r
1006 <td class="kt">Cortex-M Hard Fault Interrupt</td>
\r
1009 <td class="kt" nowrap="nowrap">MemoryManagement_IRQn</td>
\r
1010 <td class="kt">M3</td>
\r
1011 <td class="kt">-12</td>
\r
1012 <td class="kt">Cortex-M Memory Management Interrupt</td>
\r
1015 <td class="kt" nowrap="nowrap">BusFault_IRQn</td>
\r
1016 <td class="kt">M3</td>
\r
1017 <td class="kt">-11</td>
\r
1018 <td class="kt">Cortex-M Bus Fault Interrupt</td>
\r
1021 <td class="kt" nowrap="nowrap">UsageFault_IRQn</td>
\r
1022 <td class="kt">M3</td>
\r
1023 <td class="kt">-10</td>
\r
1024 <td class="kt">Cortex-M Usage Fault Interrupt</td>
\r
1027 <td class="kt" nowrap="nowrap">SVCall_IRQn</td>
\r
1028 <td class="kt">M0, M3</td>
\r
1029 <td class="kt">-5</td>
\r
1030 <td class="kt">Cortex-M SV Call Interrupt </td>
\r
1033 <td class="kt" nowrap="nowrap">DebugMonitor_IRQn</td>
\r
1034 <td class="kt">M3</td>
\r
1035 <td class="kt">-4</td>
\r
1036 <td class="kt">Cortex-M Debug Monitor Interrupt</td>
\r
1039 <td class="kt" nowrap="nowrap">PendSV_IRQn</td>
\r
1040 <td class="kt">M0, M3</td>
\r
1041 <td class="kt">-2</td>
\r
1042 <td class="kt">Cortex-M Pend SV Interrupt</td>
\r
1045 <td class="kt" nowrap="nowrap">SysTick_IRQn</td>
\r
1046 <td class="kt">M0, M3</td>
\r
1047 <td class="kt">-1</td>
\r
1048 <td class="kt">Cortex-M System Tick Interrupt</td>
\r
1053 <p>The following functions simplify the setup of the NVIC.
\r
1054 The functions are defined as <strong>static inline</strong>.</p>
\r
1056 <table class="kt" border="0" cellpadding="0" cellspacing="0">
\r
1059 <th class="kt" nowrap="nowrap">Name</th>
\r
1060 <th class="kt">Core</th>
\r
1061 <th class="kt">Parameter</th>
\r
1062 <th class="kt">Description</th>
\r
1065 <td class="kt" nowrap="nowrap">void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)</td>
\r
1066 <td class="kt">M3</td>
\r
1067 <td class="kt">Priority Grouping Value</td>
\r
1068 <td class="kt">Set the Priority Grouping (Groups . Subgroups)</td>
\r
1071 <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriorityGrouping (void)</td>
\r
1072 <td class="kt">M3</td>
\r
1073 <td class="kt">(void)</td>
\r
1074 <td class="kt">Get the Priority Grouping (Groups . Subgroups)</td>
\r
1077 <td class="kt" nowrap="nowrap">void NVIC_EnableIRQ (IRQn_Type IRQn)</td>
\r
1078 <td class="kt">M0, M3</td>
\r
1079 <td class="kt">IRQ Number</td>
\r
1080 <td class="kt">Enable IRQn</td>
\r
1083 <td class="kt" nowrap="nowrap">void NVIC_DisableIRQ (IRQn_Type IRQn)</td>
\r
1084 <td class="kt">M0, M3</td>
\r
1085 <td class="kt">IRQ Number</td>
\r
1086 <td class="kt">Disable IRQn</td>
\r
1089 <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)</td>
\r
1090 <td class="kt">M0, M3</td>
\r
1091 <td class="kt">IRQ Number</td>
\r
1092 <td class="kt">Return 1 if IRQn is pending else 0</td>
\r
1095 <td class="kt" nowrap="nowrap">void NVIC_SetPendingIRQ (IRQn_Type IRQn)</td>
\r
1096 <td class="kt">M0, M3</td>
\r
1097 <td class="kt">IRQ Number</td>
\r
1098 <td class="kt">Set IRQn Pending</td>
\r
1101 <td class="kt" nowrap="nowrap">void NVIC_ClearPendingIRQ (IRQn_Type IRQn)</td>
\r
1102 <td class="kt">M0, M3</td>
\r
1103 <td class="kt">IRQ Number</td>
\r
1104 <td class="kt">Clear IRQn Pending Status</td>
\r
1107 <td class="kt" nowrap="nowrap">uint32_t NVIC_GetActive (IRQn_Type IRQn)</td>
\r
1108 <td class="kt">M3</td>
\r
1109 <td class="kt">IRQ Number</td>
\r
1110 <td class="kt">Return 1 if IRQn is active else 0</td>
\r
1113 <td class="kt" nowrap="nowrap">void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)</td>
\r
1114 <td class="kt">M0, M3</td>
\r
1115 <td class="kt">IRQ Number, Priority</td>
\r
1116 <td class="kt">Set Priority for IRQn<br>
\r
1117 (not threadsafe for Cortex-M0)</td>
\r
1120 <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriority (IRQn_Type IRQn)</td>
\r
1121 <td class="kt">M0, M3</td>
\r
1122 <td class="kt">IRQ Number</td>
\r
1123 <td class="kt">Get Priority for IRQn</td>
\r
1126 <!-- <td class="kt" nowrap="nowrap">uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td> -->
\r
1127 <td class="kt">uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td>
\r
1128 <td class="kt">M3</td>
\r
1129 <td class="kt">IRQ Number, Priority Group, Preemptive Priority, Sub Priority</td>
\r
1130 <td class="kt">Encode priority for given group, preemptive and sub priority</td>
\r
1132 <!-- <td class="kt" nowrap="nowrap">NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)</td> -->
\r
1133 <td class="kt">NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)</td>
\r
1134 <td class="kt">M3</td>
\r
1135 <td class="kt">IRQ Number, Priority, pointer to Priority Group, pointer to Preemptive Priority, pointer to Sub Priority</td>
\r
1136 <td class="kt">Deccode given priority to group, preemptive and sub priority</td>
\r
1139 <td class="kt" nowrap="nowrap">void NVIC_SystemReset (void)</td>
\r
1140 <td class="kt">M0, M3</td>
\r
1141 <td class="kt">(void)</td>
\r
1142 <td class="kt">Resets the System</td>
\r
1146 <p class="Note">Note</p>
\r
1148 <li><p>The processor exceptions have negative enum values. Device specific interrupts
\r
1149 have positive enum values and start with 0. The values are defined in
\r
1150 <b><em>device.h</em></b> file.
\r
1153 <li><p>The values for <b>PreemptPriority</b> and <b>SubPriority</b>
\r
1154 used in functions <b>NVIC_EncodePriority</b> and <b>NVIC_DecodePriority</b>
\r
1155 depend on the available __NVIC_PRIO_BITS implemented in the NVIC.
\r
1161 <h3>SysTick Configuration Function</h3>
\r
1163 <p>The following function is used to configure the SysTick timer and start the
\r
1164 SysTick interrupt.</p>
\r
1166 <table class="kt" border="0" cellpadding="0" cellspacing="0">
\r
1169 <th class="kt" nowrap="nowrap">Name</th>
\r
1170 <th class="kt">Parameter</th>
\r
1171 <th class="kt">Description</th>
\r
1174 <td class="kt" nowrap="nowrap">uint32_t Sys<span class="style1">TickConfig
\r
1175 (uint32_t ticks)</span></td>
\r
1176 <td class="kt">ticks is SysTick counter reload value</td>
\r
1177 <td class="kt">Setup the SysTick timer and enable the SysTick interrupt. After this
\r
1178 call the SysTick timer creates interrupts with the specified time
\r
1181 Return: 0 when successful, 1 on failure.<br>
\r
1188 <h3>Cortex-M3 ITM Debug Access</h3>
\r
1190 <p>The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that
\r
1191 provides together with the Serial Viewer Output trace capabilities for the
\r
1192 microcontroller system. The ITM has 32 communication channels; two ITM
\r
1193 communication channels are used by CMSIS to output the following information:</p>
\r
1195 <li>ITM Channel 0: implements the <strong>ITM_SendChar</strong> function
\r
1196 which can be used for printf-style output via the debug interface.</li>
\r
1197 <li>ITM Channel 31: is reserved for the RTOS kernel and can be used for
\r
1198 kernel awareness debugging.</li>
\r
1200 <p class="Note">Note</p>
\r
1202 <li><p>The ITM channel 31 is selected for the RTOS kernel since some kernels
\r
1203 may use the Privileged level for program execution. ITM
\r
1204 channels have 4 groups with 8 channels each, whereby each group can be
\r
1205 configured for access rights in the Unprivileged level. The ITM channel 0
\r
1206 may be therefore enabled for the user task whereas ITM channel 31 may be
\r
1207 accessible only in Privileged level from the RTOS kernel itself.</p>
\r
1211 <p>The prototype of the <strong>ITM_SendChar</strong> routine is shown in the
\r
1214 <table class="kt" border="0" cellpadding="0" cellspacing="0">
\r
1217 <th class="kt" nowrap="nowrap">Name</th>
\r
1218 <th class="kt">Parameter</th>
\r
1219 <th class="kt">Description</th>
\r
1222 <td class="kt" nowrap="nowrap">void uint32_t ITM_SendChar(uint32_t chr)</td>
\r
1223 <td class="kt">character to output</td>
\r
1224 <td class="kt">The function outputs a character via the ITM channel 0. The
\r
1225 function returns when no debugger is connected that has booked the
\r
1226 output. It is blocking when a debugger is connected, but the
\r
1227 previous character send is not transmitted. <br><br>
\r
1228 Return: the input character 'chr'.</td>
\r
1234 Example for the usage of the ITM Channel 31 for RTOS Kernels:
\r
1237 // check if debugger connected and ITM channel enabled for tracing
\r
1238 if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
\r
1239 (ITM->TCR & ITM_TCR_ITMENA) &&
\r
1240 (ITM->TER & (1UL << 31))) {
\r
1241 // transmit trace data
\r
1242 while (ITM->PORT31_U32 == 0);
\r
1243 ITM->PORT[31].u8 = task_id; // id of next task
\r
1244 while (ITM->PORT[31].u32 == 0);
\r
1245 ITM->PORT[31].u32 = task_status; // status information
\r
1249 <h3>Cortex-M3 additional Debug Access</h3>
\r
1251 <p>CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access.
\r
1252 Data can be transmitted via a certain global buffer variable towards the target system.</p>
\r
1254 <p>The buffer variable and the prototypes of the additional functions are shown in the
\r
1257 <table class="kt" border="0" cellpadding="0" cellspacing="0">
\r
1260 <th class="kt" nowrap="nowrap">Name</th>
\r
1261 <th class="kt">Parameter</th>
\r
1262 <th class="kt">Description</th>
\r
1265 <td class="kt" nowrap="nowrap">extern volatile int ITM_RxBuffer</td>
\r
1266 <td class="kt"> </td>
\r
1267 <td class="kt">Buffer to transmit data towards debug system. <br><br>
\r
1268 Value 0x5AA55AA5 indicates that buffer is empty.</td>
\r
1271 <td class="kt" nowrap="nowrap">int ITM_ReceiveChar (void)</td>
\r
1272 <td class="kt">none</td>
\r
1273 <td class="kt">The nonblocking functions returns the character stored in
\r
1274 ITM_RxBuffer. <br><br>
\r
1275 Return: -1 indicates that no character was received.</td>
\r
1278 <td class="kt" nowrap="nowrap">int ITM_CheckChar (void)</td>
\r
1279 <td class="kt">none</td>
\r
1280 <td class="kt">The function checks if a character is available in ITM_RxBuffer. <br><br>
\r
1281 Return: 1 indicates that a character is available, 0 indicates that
\r
1282 no character is available.</td>
\r
1288 <h2><a name="5"></a>CMSIS Example</h2>
\r
1290 The following section shows a typical example for using the CMSIS layer in user applications.
\r
1291 The example is based on a STM32F10x Device.
\r
1294 #include "stm32f10x.h"
\r
1296 volatile uint32_t msTicks; /* timeTicks counter */
\r
1298 void SysTick_Handler(void) {
\r
1299 msTicks++; /* increment timeTicks counter */
\r
1302 __INLINE static void Delay (uint32_t dlyTicks) {
\r
1303 uint32_t curTicks = msTicks;
\r
1305 while ((msTicks - curTicks) < dlyTicks);
\r
1308 __INLINE static void LED_Config(void) {
\r
1309 ; /* Configure the LEDs */
\r
1312 __INLINE static void LED_On (uint32_t led) {
\r
1313 ; /* Turn On LED */
\r
1316 __INLINE static void LED_Off (uint32_t led) {
\r
1317 ; /* Turn Off LED */
\r
1321 if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */
\r
1322 ; /* Handle Error */
\r
1326 LED_Config(); /* configure the LEDs */
\r
1329 LED_On (0x100); /* Turn on the LED */
\r
1330 Delay (100); /* delay 100 Msec */
\r
1331 LED_Off (0x100); /* Turn off the LED */
\r
1332 Delay (100); /* delay 100 Msec */
\r
projects / freertos / blob