git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_uart.h

   1 //*****************************************************************************\r
   2 //\r
   3 // hw_uart.h - Macros and defines used when accessing the UART hardware\r
   4 //\r
   5 // Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
   6 //\r
   7 // Software License Agreement\r
   8 //\r
   9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
  10 // exclusively on LMI's Stellaris Family of microcontroller products.\r
  11 //\r
  12 // The software is owned by LMI and/or its suppliers, and is protected under\r
  13 // applicable copyright laws.  All rights are reserved.  Any use in violation\r
  14 // of the foregoing restrictions may subject the user to criminal sanctions\r
  15 // under applicable laws, as well as to civil liability for the breach of the\r
  16 // terms and conditions of this license.\r
  17 //\r
  18 // THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
  19 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
  20 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
  21 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
  22 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
  23 //\r
  24 // This is part of revision 991 of the Stellaris Driver Library.\r
  25 //\r
  26 //*****************************************************************************\r
  27 \r
  28 #ifndef __HW_UART_H__\r
  29 #define __HW_UART_H__\r
  30 \r
  31 //*****************************************************************************\r
  32 //\r
  33 // UART Register Offsets.\r
  34 //\r
  35 //*****************************************************************************\r
  36 #define UART_O_DR               0x00000000  // Data Register\r
  37 #define UART_O_RSR              0x00000004  // Receive Status Register (read)\r
  38 #define UART_O_ECR              0x00000004  // Error Clear Register (write)\r
  39 #define UART_O_FR               0x00000018  // Flag Register (read only)\r
  40 #define UART_O_IBRD             0x00000024  // Integer Baud Rate Divisor Reg\r
  41 #define UART_O_FBRD             0x00000028  // Fractional Baud Rate Divisor Reg\r
  42 #define UART_O_LCR_H            0x0000002C  // Line Control Register, HIGH byte\r
  43 #define UART_O_CTL              0x00000030  // Control Register\r
  44 #define UART_O_IFLS             0x00000034  // Interrupt FIFO Level Select Reg\r
  45 #define UART_O_IM               0x00000038  // Interrupt Mask Set/Clear Reg\r
  46 #define UART_O_RIS              0x0000003C  // Raw Interrupt Status Register\r
  47 #define UART_O_MIS              0x00000040  // Masked Interrupt Status Register\r
  48 #define UART_O_ICR              0x00000044  // Interrupt Clear Register\r
  49 #define UART_O_PeriphID4        0x00000FD0  //\r
  50 #define UART_O_PeriphID5        0x00000FD4  //\r
  51 #define UART_O_PeriphID6        0x00000FD8  //\r
  52 #define UART_O_PeriphID7        0x00000FDC  //\r
  53 #define UART_O_PeriphID0        0x00000FE0  //\r
  54 #define UART_O_PeriphID1        0x00000FE4  //\r
  55 #define UART_O_PeriphID2        0x00000FE8  //\r
  56 #define UART_O_PeriphID3        0x00000FEC  //\r
  57 #define UART_O_PCellID0         0x00000FF0  //\r
  58 #define UART_O_PCellID1         0x00000FF4  //\r
  59 #define UART_O_PCellID2         0x00000FF8  //\r
  60 #define UART_O_PCellID3         0x00000FFC  //\r
  61 \r
  62 //*****************************************************************************\r
  63 //\r
  64 // Data Register bits\r
  65 //\r
  66 //*****************************************************************************\r
  67 #define UART_DR_OE              0x00000800  // Overrun Error\r
  68 #define UART_DR_BE              0x00000400  // Break Error\r
  69 #define UART_DR_PE              0x00000200  // Parity Error\r
  70 #define UART_DR_FE              0x00000100  // Framing Error\r
  71 #define UART_DR_DATA_MASK       0x000000FF  // UART data\r
  72 \r
  73 //*****************************************************************************\r
  74 //\r
  75 // Receive Status Register bits\r
  76 //\r
  77 //*****************************************************************************\r
  78 #define UART_RSR_OE             0x00000008  // Overrun Error\r
  79 #define UART_RSR_BE             0x00000004  // Break Error\r
  80 #define UART_RSR_PE             0x00000002  // Parity Error\r
  81 #define UART_RSR_FE             0x00000001  // Framing Error\r
  82 \r
  83 //*****************************************************************************\r
  84 //\r
  85 // Flag Register bits\r
  86 //\r
  87 //*****************************************************************************\r
  88 #define UART_FR_TXFE            0x00000080  // TX FIFO Empty\r
  89 #define UART_FR_RXFF            0x00000040  // RX FIFO Full\r
  90 #define UART_FR_TXFF            0x00000020  // TX FIFO Full\r
  91 #define UART_FR_RXFE            0x00000010  // RX FIFO Empty\r
  92 #define UART_FR_BUSY            0x00000008  // UART Busy\r
  93 \r
  94 //*****************************************************************************\r
  95 //\r
  96 // Integer baud-rate divisor\r
  97 //\r
  98 //*****************************************************************************\r
  99 #define UART_IBRD_DIVINT_MASK   0x0000FFFF  // Integer baud-rate divisor\r
 100 \r
 101 //*****************************************************************************\r
 102 //\r
 103 // Fractional baud-rate divisor\r
 104 //\r
 105 //*****************************************************************************\r
 106 #define UART_FBRD_DIVFRAC_MASK  0x0000003F  // Fractional baud-rate divisor\r
 107 \r
 108 //*****************************************************************************\r
 109 //\r
 110 // Line Control Register High bits\r
 111 //\r
 112 //*****************************************************************************\r
 113 #define UART_LCR_H_SPS          0x00000080  // Stick Parity Select\r
 114 #define UART_LCR_H_WLEN         0x00000060  // Word length\r
 115 #define UART_LCR_H_WLEN_8       0x00000060  // 8 bit data\r
 116 #define UART_LCR_H_WLEN_7       0x00000040  // 7 bit data\r
 117 #define UART_LCR_H_WLEN_6       0x00000020  // 6 bit data\r
 118 #define UART_LCR_H_WLEN_5       0x00000000  // 5 bit data\r
 119 #define UART_LCR_H_FEN          0x00000010  // Enable FIFO\r
 120 #define UART_LCR_H_STP2         0x00000008  // Two Stop Bits Select\r
 121 #define UART_LCR_H_EPS          0x00000004  // Even Parity Select\r
 122 #define UART_LCR_H_PEN          0x00000002  // Parity Enable\r
 123 #define UART_LCR_H_BRK          0x00000001  // Send Break\r
 124 \r
 125 //*****************************************************************************\r
 126 //\r
 127 // Control Register bits\r
 128 //\r
 129 //*****************************************************************************\r
 130 #define UART_CTL_RXE            0x00000200  // Receive Enable\r
 131 #define UART_CTL_TXE            0x00000100  // Transmit Enable\r
 132 #define UART_CTL_LBE            0x00000080  // Loopback Enable\r
 133 #define UART_CTL_UARTEN         0x00000001  // UART Enable\r
 134 \r
 135 //*****************************************************************************\r
 136 //\r
 137 // Interrupt FIFO Level Select Register bits\r
 138 //\r
 139 //*****************************************************************************\r
 140 #define UART_IFLS_RX1_8         0x00000000  // 1/8 Full\r
 141 #define UART_IFLS_RX2_8         0x00000010  // 1/4 Full\r
 142 #define UART_IFLS_RX4_8         0x00000020  // 1/2 Full\r
 143 #define UART_IFLS_RX6_8         0x00000030  // 3/4 Full\r
 144 #define UART_IFLS_RX7_8         0x00000040  // 7/8 Full\r
 145 #define UART_IFLS_TX1_8         0x00000000  // 1/8 Full\r
 146 #define UART_IFLS_TX2_8         0x00000001  // 1/4 Full\r
 147 #define UART_IFLS_TX4_8         0x00000002  // 1/2 Full\r
 148 #define UART_IFLS_TX6_8         0x00000003  // 3/4 Full\r
 149 #define UART_IFLS_TX7_8         0x00000004  // 7/8 Full\r
 150 \r
 151 //*****************************************************************************\r
 152 //\r
 153 // Interrupt Mask Set/Clear Register bits\r
 154 //\r
 155 //*****************************************************************************\r
 156 #define UART_IM_OEIM            0x00000400  // Overrun Error Interrupt Mask\r
 157 #define UART_IM_BEIM            0x00000200  // Break Error Interrupt Mask\r
 158 #define UART_IM_PEIM            0x00000100  // Parity Error Interrupt Mask\r
 159 #define UART_IM_FEIM            0x00000080  // Framing Error Interrupt Mask\r
 160 #define UART_IM_RTIM            0x00000040  // Receive Timeout Interrupt Mask\r
 161 #define UART_IM_TXIM            0x00000020  // Transmit Interrupt Mask\r
 162 #define UART_IM_RXIM            0x00000010  // Receive Interrupt Mask\r
 163 \r
 164 //*****************************************************************************\r
 165 //\r
 166 // Raw Interrupt Status Register\r
 167 //\r
 168 //*****************************************************************************\r
 169 #define UART_RIS_OERIS          0x00000400  // Overrun Error Interrupt Status\r
 170 #define UART_RIS_BERIS          0x00000200  // Break Error Interrupt Status\r
 171 #define UART_RIS_PERIS          0x00000100  // Parity Error Interrupt Status\r
 172 #define UART_RIS_FERIS          0x00000080  // Framing Error Interrupt Status\r
 173 #define UART_RIS_RTRIS          0x00000040  // Receive Timeout Interrupt Status\r
 174 #define UART_RIS_TXRIS          0x00000020  // Transmit Interrupt Status\r
 175 #define UART_RIS_RXRIS          0x00000010  // Receive Interrupt Status\r
 176 \r
 177 //*****************************************************************************\r
 178 //\r
 179 // Masked Interrupt Status Register\r
 180 //\r
 181 //*****************************************************************************\r
 182 #define UART_MIS_OEMIS          0x00000400  // Overrun Error Interrupt Status\r
 183 #define UART_MIS_BEMIS          0x00000200  // Break Error Interrupt Status\r
 184 #define UART_MIS_PEMIS          0x00000100  // Parity Error Interrupt Status\r
 185 #define UART_MIS_FEMIS          0x00000080  // Framing Error Interrupt Status\r
 186 #define UART_MIS_RTMIS          0x00000040  // Receive Timeout Interrupt Status\r
 187 #define UART_MIS_TXMIS          0x00000020  // Transmit Interrupt Status\r
 188 #define UART_MIS_RXMIS          0x00000010  // Receive Interrupt Status\r
 189 \r
 190 //*****************************************************************************\r
 191 //\r
 192 // Interrupt Clear Register bits\r
 193 //\r
 194 //*****************************************************************************\r
 195 #define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear\r
 196 #define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear\r
 197 #define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear\r
 198 #define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear\r
 199 #define UART_ICR_RTIC           0x00000040  // Receive Timeout Interrupt Clear\r
 200 #define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear\r
 201 #define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear\r
 202 \r
 203 #define UART_RSR_ANY            (UART_RSR_OE |                                \\r
 204                                  UART_RSR_BE |                                \\r
 205                                  UART_RSR_PE |                                \\r
 206                                  UART_RSR_FE)\r
 207 \r
 208 //*****************************************************************************\r
 209 //\r
 210 // Reset Values for UART Registers.\r
 211 //\r
 212 //*****************************************************************************\r
 213 #define UART_RV_DR              0x00000000\r
 214 #define UART_RV_RSR             0x00000000\r
 215 #define UART_RV_ECR             0x00000000\r
 216 #define UART_RV_FR              0x00000090\r
 217 #define UART_RV_IBRD            0x00000000\r
 218 #define UART_RV_FBRD            0x00000000\r
 219 #define UART_RV_LCR_H           0x00000000\r
 220 #define UART_RV_CTL             0x00000300\r
 221 #define UART_RV_IFLS            0x00000012\r
 222 #define UART_RV_IM              0x00000000\r
 223 #define UART_RV_RIS             0x00000000\r
 224 #define UART_RV_MIS             0x00000000\r
 225 #define UART_RV_ICR             0x00000000\r
 226 #define UART_RV_PeriphID4       0x00000000\r
 227 #define UART_RV_PeriphID5       0x00000000\r
 228 #define UART_RV_PeriphID6       0x00000000\r
 229 #define UART_RV_PeriphID7       0x00000000\r
 230 #define UART_RV_PeriphID0       0x00000011\r
 231 #define UART_RV_PeriphID1       0x00000000\r
 232 #define UART_RV_PeriphID2       0x00000018\r
 233 #define UART_RV_PeriphID3       0x00000001\r
 234 #define UART_RV_PCellID0        0x0000000D\r
 235 #define UART_RV_PCellID1        0x000000F0\r
 236 #define UART_RV_PCellID2        0x00000005\r
 237 #define UART_RV_PCellID3        0x000000B1\r
 238 \r
 239 #endif // __HW_UART_H__\r