2 * FreeRTOS Kernel V10.3.0
\r
3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
\r
5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
\r
6 * this software and associated documentation files (the "Software"), to deal in
\r
7 * the Software without restriction, including without limitation the rights to
\r
8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
\r
9 * the Software, and to permit persons to whom the Software is furnished to do so,
\r
10 * subject to the following conditions:
\r
12 * The above copyright notice and this permission notice shall be included in all
\r
13 * copies or substantial portions of the Software.
\r
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
\r
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
\r
17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
\r
18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
\r
19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
\r
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
\r
22 * http://www.FreeRTOS.org
\r
23 * http://aws.amazon.com/freertos
\r
25 * 1 tab == 4 spaces!
\r
28 /* Kernel includes. */
\r
29 #include "FreeRTOS.h"
\r
33 /* Demo includes. */
\r
39 /* Hardware library includes. */
\r
40 #include "hw_types.h"
\r
41 #include "hw_memmap.h"
\r
42 #include "hw_ints.h"
\r
43 #include "hw_ethernet.h"
\r
44 #include "ethernet.h"
\r
45 #include "interrupt.h"
\r
47 #define emacNUM_RX_BUFFERS 5
\r
48 #define emacFRAM_SIZE_BYTES 2
\r
49 #define macNEGOTIATE_DELAY 2000
\r
50 #define macWAIT_SEND_TIME ( 10 )
\r
52 /* The task that handles the MAC peripheral. This is created at a high
\r
53 priority and is effectively a deferred interrupt handler. The peripheral
\r
54 handling is deferred to a task to prevent the entire FIFO having to be read
\r
55 from within an ISR. */
\r
56 void vMACHandleTask( void *pvParameters );
\r
58 /*-----------------------------------------------------------*/
\r
60 /* The semaphore used to wake the uIP task when data arrives. */
\r
61 SemaphoreHandle_t xEMACSemaphore = NULL;
\r
63 /* The semaphore used to wake the interrupt handler task. The peripheral
\r
64 is processed at the task level to prevent the need to read the entire FIFO from
\r
65 within the ISR itself. */
\r
66 SemaphoreHandle_t xMACInterruptSemaphore = NULL;
\r
68 /* The buffer used by the uIP stack. In this case the pointer is used to
\r
69 point to one of the Rx buffers. */
\r
70 unsigned char *uip_buf;
\r
72 /* Buffers into which Rx data is placed. */
\r
73 static unsigned char ucRxBuffers[ emacNUM_RX_BUFFERS ][ UIP_BUFSIZE + ( 4 * emacFRAM_SIZE_BYTES ) ] __attribute__((aligned(4)));
\r
75 /* The length of the data within each of the Rx buffers. */
\r
76 static unsigned long ulRxLength[ emacNUM_RX_BUFFERS ];
\r
78 /* Used to keep a track of the number of bytes to transmit. */
\r
79 static unsigned long ulNextTxSpace;
\r
81 /*-----------------------------------------------------------*/
\r
83 portBASE_TYPE vInitEMAC( void )
\r
85 unsigned long ulTemp;
\r
86 portBASE_TYPE xReturn;
\r
88 /* Ensure all interrupts are disabled. */
\r
89 EthernetIntDisable( ETH_BASE, ( ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX));
\r
91 /* Clear any interrupts that were already pending. */
\r
92 ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE );
\r
93 EthernetIntClear( ETH_BASE, ulTemp );
\r
95 /* Initialise the MAC and connect. */
\r
96 EthernetInit( ETH_BASE );
\r
97 EthernetConfigSet( ETH_BASE, ( ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN ) );
\r
98 EthernetEnable( ETH_BASE );
\r
100 /* Mark each Rx buffer as empty. */
\r
101 for( ulTemp = 0; ulTemp < emacNUM_RX_BUFFERS; ulTemp++ )
\r
103 ulRxLength[ ulTemp ] = 0;
\r
106 /* Create the queue and task used to defer the MAC processing to the
\r
108 vSemaphoreCreateBinary( xMACInterruptSemaphore );
\r
109 xSemaphoreTake( xMACInterruptSemaphore, 0 );
\r
110 xReturn = xTaskCreate( vMACHandleTask, "MAC", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );
\r
111 vTaskDelay( macNEGOTIATE_DELAY );
\r
113 /* We are only interested in Rx interrupts. */
\r
114 IntPrioritySet( INT_ETH, configKERNEL_INTERRUPT_PRIORITY );
\r
115 IntEnable( INT_ETH );
\r
116 EthernetIntEnable(ETH_BASE, ETH_INT_RX);
\r
120 /*-----------------------------------------------------------*/
\r
122 unsigned int uiGetEMACRxData( unsigned char *ucBuffer )
\r
124 static unsigned long ulNextRxBuffer = 0;
\r
127 iLen = ulRxLength[ ulNextRxBuffer ];
\r
131 /* Leave room for the size at the start of the buffer. */
\r
132 uip_buf = &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] );
\r
134 ulRxLength[ ulNextRxBuffer ] = 0;
\r
137 if( ulNextRxBuffer >= emacNUM_RX_BUFFERS )
\r
139 ulNextRxBuffer = 0;
\r
145 /*-----------------------------------------------------------*/
\r
147 void vInitialiseSend( void )
\r
149 /* Set the index to the first byte to send - skipping over the size
\r
153 /*-----------------------------------------------------------*/
\r
155 void vIncrementTxLength( unsigned long ulLength )
\r
157 ulNextTxSpace += ulLength;
\r
159 /*-----------------------------------------------------------*/
\r
161 void vSendBufferToMAC( void )
\r
163 unsigned long *pulSource;
\r
164 unsigned short * pus;
\r
165 unsigned long ulNextWord;
\r
167 /* Locate the data to be send. */
\r
168 pus = ( unsigned short * ) uip_buf;
\r
170 /* Add in the size of the data. */
\r
172 *pus = ulNextTxSpace;
\r
174 /* Wait for data to be sent if there is no space immediately. */
\r
175 while( !EthernetSpaceAvail( ETH_BASE ) )
\r
177 vTaskDelay( macWAIT_SEND_TIME );
\r
180 pulSource = ( unsigned long * ) pus;
\r
182 for( ulNextWord = 0; ulNextWord < ulNextTxSpace; ulNextWord += sizeof( unsigned long ) )
\r
184 HWREG(ETH_BASE + MAC_O_DATA) = *pulSource;
\r
189 HWREG( ETH_BASE + MAC_O_TR ) = MAC_TR_NEWTX;
\r
191 /*-----------------------------------------------------------*/
\r
193 void vEMAC_ISR( void )
\r
195 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
\r
196 unsigned long ulTemp;
\r
198 /* Clear the interrupt. */
\r
199 ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE );
\r
200 EthernetIntClear( ETH_BASE, ulTemp );
\r
202 /* Was it an Rx interrupt? */
\r
203 if( ulTemp & ETH_INT_RX )
\r
205 xSemaphoreGiveFromISR( xMACInterruptSemaphore, &xHigherPriorityTaskWoken );
\r
206 EthernetIntDisable( ETH_BASE, ETH_INT_RX );
\r
209 /* Switch to the uIP task. */
\r
210 portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
\r
212 /*-----------------------------------------------------------*/
\r
214 void vMACHandleTask( void *pvParameters )
\r
217 unsigned long ulLength, ulInt;
\r
218 unsigned long *pulBuffer;
\r
219 static unsigned long ulNextRxBuffer = 0;
\r
223 /* Wait for something to do. */
\r
224 xSemaphoreTake( xMACInterruptSemaphore, portMAX_DELAY );
\r
226 while( ( ulInt = ( EthernetIntStatus( ETH_BASE, pdFALSE ) & ETH_INT_RX ) ) != 0 )
\r
228 ulLength = HWREG( ETH_BASE + MAC_O_DATA );
\r
230 /* Leave room at the start of the buffer for the size. */
\r
231 pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] );
\r
232 *pulBuffer = ( ulLength >> 16 );
\r
234 /* Get the size of the data. */
\r
235 pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 4 ] );
\r
236 ulLength &= 0xFFFF;
\r
242 if( ulLength >= UIP_BUFSIZE )
\r
244 /* The data won't fit in our buffer. Ensure we don't
\r
245 try to write into the buffer. */
\r
249 /* Read out the data into our buffer. */
\r
250 for( i = 0; i < ulLength; i += sizeof( unsigned long ) )
\r
252 *pulBuffer = HWREG( ETH_BASE + MAC_O_DATA );
\r
256 /* Store the length of the data into the separate array. */
\r
257 ulRxLength[ ulNextRxBuffer ] = ulLength;
\r
259 /* Use the next buffer the next time through. */
\r
261 if( ulNextRxBuffer >= emacNUM_RX_BUFFERS )
\r
263 ulNextRxBuffer = 0;
\r
266 /* Ensure the uIP task is not blocked as data has arrived. */
\r
267 xSemaphoreGive( xEMACSemaphore );
\r
271 EthernetIntEnable( ETH_BASE, ETH_INT_RX );
\r