2 FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.
\r
4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
\r
5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
7 ***************************************************************************
\r
9 * FreeRTOS tutorial books are available in pdf and paperback. *
\r
10 * Complete, revised, and edited pdf reference manuals are also *
\r
13 * Purchasing FreeRTOS documentation will not only help you, by *
\r
14 * ensuring you get running as quickly as possible and with an *
\r
15 * in-depth knowledge of how to use FreeRTOS, it will also help *
\r
16 * the FreeRTOS project to continue with its mission of providing *
\r
17 * professional grade, cross platform, de facto standard solutions *
\r
18 * for microcontrollers - completely free of charge! *
\r
20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
\r
22 * Thank you for using FreeRTOS, and thank you for your support! *
\r
24 ***************************************************************************
\r
27 This file is part of the FreeRTOS distribution.
\r
29 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
30 the terms of the GNU General Public License (version 2) as published by the
\r
31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
\r
32 >>>NOTE<<< The modification to the GPL is included to allow you to
\r
33 distribute a combined work that includes FreeRTOS without being obliged to
\r
34 provide the source code for proprietary components outside of the FreeRTOS
\r
35 kernel. FreeRTOS is distributed in the hope that it will be useful, but
\r
36 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
\r
37 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
\r
38 more details. You should have received a copy of the GNU General Public
\r
39 License and the FreeRTOS license exception along with FreeRTOS; if not it
\r
40 can be viewed here: http://www.freertos.org/a00114.html and also obtained
\r
41 by writing to Richard Barry, contact details for whom are available on the
\r
46 ***************************************************************************
\r
48 * Having a problem? Start by reading the FAQ "My application does *
\r
49 * not run, what could be wrong?" *
\r
51 * http://www.FreeRTOS.org/FAQHelp.html *
\r
53 ***************************************************************************
\r
56 http://www.FreeRTOS.org - Documentation, training, latest versions, license
\r
57 and contact details.
\r
59 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
60 including FreeRTOS+Trace - an indispensable productivity tool.
\r
62 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
\r
63 the code with commercial support, indemnification, and middleware, under
\r
64 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
\r
65 provide a safety engineered and independently SIL3 certified version under
\r
66 the SafeRTOS brand: http://www.SafeRTOS.com.
\r
69 /* Kernel includes. */
\r
70 #include "FreeRTOS.h"
\r
74 /* Demo includes. */
\r
80 /* Hardware library includes. */
\r
81 #include "hw_types.h"
\r
82 #include "hw_memmap.h"
\r
83 #include "hw_ints.h"
\r
84 #include "hw_ethernet.h"
\r
85 #include "ethernet.h"
\r
86 #include "interrupt.h"
\r
88 #define emacNUM_RX_BUFFERS 5
\r
89 #define emacFRAM_SIZE_BYTES 2
\r
90 #define macNEGOTIATE_DELAY 2000
\r
91 #define macWAIT_SEND_TIME ( 10 )
\r
93 /* The task that handles the MAC peripheral. This is created at a high
\r
94 priority and is effectively a deferred interrupt handler. The peripheral
\r
95 handling is deferred to a task to prevent the entire FIFO having to be read
\r
96 from within an ISR. */
\r
97 void vMACHandleTask( void *pvParameters );
\r
99 /*-----------------------------------------------------------*/
\r
101 /* The semaphore used to wake the uIP task when data arrives. */
\r
102 xSemaphoreHandle xEMACSemaphore = NULL;
\r
104 /* The semaphore used to wake the interrupt handler task. The peripheral
\r
105 is processed at the task level to prevent the need to read the entire FIFO from
\r
106 within the ISR itself. */
\r
107 xSemaphoreHandle xMACInterruptSemaphore = NULL;
\r
109 /* The buffer used by the uIP stack. In this case the pointer is used to
\r
110 point to one of the Rx buffers. */
\r
111 unsigned char *uip_buf;
\r
113 /* Buffers into which Rx data is placed. */
\r
114 static unsigned char ucRxBuffers[ emacNUM_RX_BUFFERS ][ UIP_BUFSIZE + ( 4 * emacFRAM_SIZE_BYTES ) ] __attribute__((aligned(4)));
\r
116 /* The length of the data within each of the Rx buffers. */
\r
117 static unsigned long ulRxLength[ emacNUM_RX_BUFFERS ];
\r
119 /* Used to keep a track of the number of bytes to transmit. */
\r
120 static unsigned long ulNextTxSpace;
\r
122 /*-----------------------------------------------------------*/
\r
124 portBASE_TYPE vInitEMAC( void )
\r
126 unsigned long ulTemp;
\r
127 portBASE_TYPE xReturn;
\r
129 /* Ensure all interrupts are disabled. */
\r
130 EthernetIntDisable( ETH_BASE, ( ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX));
\r
132 /* Clear any interrupts that were already pending. */
\r
133 ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE );
\r
134 EthernetIntClear( ETH_BASE, ulTemp );
\r
136 /* Initialise the MAC and connect. */
\r
137 EthernetInit( ETH_BASE );
\r
138 EthernetConfigSet( ETH_BASE, ( ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN ) );
\r
139 EthernetEnable( ETH_BASE );
\r
141 /* Mark each Rx buffer as empty. */
\r
142 for( ulTemp = 0; ulTemp < emacNUM_RX_BUFFERS; ulTemp++ )
\r
144 ulRxLength[ ulTemp ] = 0;
\r
147 /* Create the queue and task used to defer the MAC processing to the
\r
149 vSemaphoreCreateBinary( xMACInterruptSemaphore );
\r
150 xSemaphoreTake( xMACInterruptSemaphore, 0 );
\r
151 xReturn = xTaskCreate( vMACHandleTask, ( signed char * ) "MAC", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );
\r
152 vTaskDelay( macNEGOTIATE_DELAY );
\r
154 /* We are only interested in Rx interrupts. */
\r
155 IntPrioritySet( INT_ETH, configKERNEL_INTERRUPT_PRIORITY );
\r
156 IntEnable( INT_ETH );
\r
157 EthernetIntEnable(ETH_BASE, ETH_INT_RX);
\r
161 /*-----------------------------------------------------------*/
\r
163 unsigned int uiGetEMACRxData( unsigned char *ucBuffer )
\r
165 static unsigned long ulNextRxBuffer = 0;
\r
168 iLen = ulRxLength[ ulNextRxBuffer ];
\r
172 /* Leave room for the size at the start of the buffer. */
\r
173 uip_buf = &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] );
\r
175 ulRxLength[ ulNextRxBuffer ] = 0;
\r
178 if( ulNextRxBuffer >= emacNUM_RX_BUFFERS )
\r
180 ulNextRxBuffer = 0;
\r
186 /*-----------------------------------------------------------*/
\r
188 void vInitialiseSend( void )
\r
190 /* Set the index to the first byte to send - skipping over the size
\r
194 /*-----------------------------------------------------------*/
\r
196 void vIncrementTxLength( unsigned long ulLength )
\r
198 ulNextTxSpace += ulLength;
\r
200 /*-----------------------------------------------------------*/
\r
202 void vSendBufferToMAC( void )
\r
204 unsigned long *pulSource;
\r
205 unsigned short * pus;
\r
206 unsigned long ulNextWord;
\r
208 /* Locate the data to be send. */
\r
209 pus = ( unsigned short * ) uip_buf;
\r
211 /* Add in the size of the data. */
\r
213 *pus = ulNextTxSpace;
\r
215 /* Wait for data to be sent if there is no space immediately. */
\r
216 while( !EthernetSpaceAvail( ETH_BASE ) )
\r
218 vTaskDelay( macWAIT_SEND_TIME );
\r
221 pulSource = ( unsigned long * ) pus;
\r
223 for( ulNextWord = 0; ulNextWord < ulNextTxSpace; ulNextWord += sizeof( unsigned long ) )
\r
225 HWREG(ETH_BASE + MAC_O_DATA) = *pulSource;
\r
230 HWREG( ETH_BASE + MAC_O_TR ) = MAC_TR_NEWTX;
\r
232 /*-----------------------------------------------------------*/
\r
234 void vEMAC_ISR( void )
\r
236 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
\r
237 unsigned long ulTemp;
\r
239 /* Clear the interrupt. */
\r
240 ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE );
\r
241 EthernetIntClear( ETH_BASE, ulTemp );
\r
243 /* Was it an Rx interrupt? */
\r
244 if( ulTemp & ETH_INT_RX )
\r
246 xSemaphoreGiveFromISR( xMACInterruptSemaphore, &xHigherPriorityTaskWoken );
\r
247 EthernetIntDisable( ETH_BASE, ETH_INT_RX );
\r
250 /* Switch to the uIP task. */
\r
251 portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
\r
253 /*-----------------------------------------------------------*/
\r
255 void vMACHandleTask( void *pvParameters )
\r
257 unsigned long ulLen = 0, i;
\r
258 unsigned long ulLength, ulInt;
\r
259 unsigned long *pulBuffer;
\r
260 static unsigned long ulNextRxBuffer = 0;
\r
261 portBASE_TYPE xSwitchRequired = pdFALSE;
\r
265 /* Wait for something to do. */
\r
266 xSemaphoreTake( xMACInterruptSemaphore, portMAX_DELAY );
\r
268 while( ( ulInt = ( EthernetIntStatus( ETH_BASE, pdFALSE ) & ETH_INT_RX ) ) != 0 )
\r
270 ulLength = HWREG( ETH_BASE + MAC_O_DATA );
\r
272 /* Leave room at the start of the buffer for the size. */
\r
273 pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] );
\r
274 *pulBuffer = ( ulLength >> 16 );
\r
276 /* Get the size of the data. */
\r
277 pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 4 ] );
\r
278 ulLength &= 0xFFFF;
\r
284 if( ulLength >= UIP_BUFSIZE )
\r
286 /* The data won't fit in our buffer. Ensure we don't
\r
287 try to write into the buffer. */
\r
291 /* Read out the data into our buffer. */
\r
292 for( i = 0; i < ulLength; i += sizeof( unsigned long ) )
\r
294 *pulBuffer = HWREG( ETH_BASE + MAC_O_DATA );
\r
298 /* Store the length of the data into the separate array. */
\r
299 ulRxLength[ ulNextRxBuffer ] = ulLength;
\r
301 /* Use the next buffer the next time through. */
\r
303 if( ulNextRxBuffer >= emacNUM_RX_BUFFERS )
\r
305 ulNextRxBuffer = 0;
\r
308 /* Ensure the uIP task is not blocked as data has arrived. */
\r
309 xSemaphoreGive( xEMACSemaphore );
\r
313 EthernetIntEnable( ETH_BASE, ETH_INT_RX );
\r