2 * FreeRTOS Kernel V10.0.0
\r
3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
\r
5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
\r
6 * this software and associated documentation files (the "Software"), to deal in
\r
7 * the Software without restriction, including without limitation the rights to
\r
8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
\r
9 * the Software, and to permit persons to whom the Software is furnished to do so,
\r
10 * subject to the following conditions:
\r
12 * The above copyright notice and this permission notice shall be included in all
\r
13 * copies or substantial portions of the Software. If you wish to use our Amazon
\r
14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
\r
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
\r
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
\r
18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
\r
19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
\r
20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
\r
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
\r
23 * http://www.FreeRTOS.org
\r
24 * http://aws.amazon.com/freertos
\r
26 * 1 tab == 4 spaces!
\r
29 /* Originally adapted from file written by Andreas Dannenberg. Supplied with permission. */
\r
31 /* Kernel includes. */
\r
32 #include "FreeRTOS.h"
\r
36 /* Hardware specific includes. */
\r
37 #include "EthDev_LPC17xx.h"
\r
39 /* Time to wait between each inspection of the link status. */
\r
40 #define emacWAIT_FOR_LINK_TO_ESTABLISH ( 500 / portTICK_PERIOD_MS )
\r
42 /* Short delay used in several places during the initialisation process. */
\r
43 #define emacSHORT_DELAY ( 2 )
\r
45 /* Hardware specific bit definitions. */
\r
46 #define emacLINK_ESTABLISHED ( 0x0020)
\r
47 #define emacFULL_DUPLEX_ENABLED ( 0x0010 )
\r
48 #define emac10BASE_T_MODE ( 0x0004 )
\r
49 #define emacPINSEL2_VALUE ( 0x50150105 )
\r
50 #define emacDIV_44 ( 0x28 )
\r
52 /* If no buffers are available, then wait this long before looking again.... */
\r
53 #define emacBUFFER_WAIT_DELAY ( 3 / portTICK_PERIOD_MS )
\r
55 /* ...and don't look more than this many times. */
\r
56 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
\r
58 /* Index to the Tx descriptor that is always used first for every Tx. The second
\r
59 descriptor is then used to re-send in order to speed up the uIP Tx process. */
\r
60 #define emacTX_DESC_INDEX ( 0 )
\r
62 /*-----------------------------------------------------------*/
\r
65 * Configure both the Rx and Tx descriptors during the init process.
\r
67 static void prvInitDescriptors( void );
\r
70 * Setup the IO and peripherals required for Ethernet communication.
\r
72 static void prvSetupEMACHardware( void );
\r
75 * Control the auto negotiate process.
\r
77 static void prvConfigurePHY( void );
\r
80 * Wait for a link to be established, then setup the PHY according to the link
\r
83 static long prvSetupLinkStatus( void );
\r
86 * Search the pool of buffers to find one that is free. If a buffer is found
\r
87 * mark it as in use before returning its address.
\r
89 static unsigned char *prvGetNextBuffer( void );
\r
92 * Return an allocated buffer to the pool of free buffers.
\r
94 static void prvReturnBuffer( unsigned char *pucBuffer );
\r
97 * Send lValue to the lPhyReg within the PHY.
\r
99 static long prvWritePHY( long lPhyReg, long lValue );
\r
102 * Read a value from ucPhyReg within the PHY. *plStatus will be set to
\r
103 * pdFALSE if there is an error.
\r
105 static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus );
\r
107 /*-----------------------------------------------------------*/
\r
109 /* The semaphore used to wake the uIP task when data arrives. */
\r
110 extern SemaphoreHandle_t xEMACSemaphore;
\r
112 /* Each ucBufferInUse index corresponds to a position in the pool of buffers.
\r
113 If the index contains a 1 then the buffer within pool is in use, if it
\r
114 contains a 0 then the buffer is free. */
\r
115 static unsigned char ucBufferInUse[ ETH_NUM_BUFFERS ] = { pdFALSE };
\r
117 /* The uip_buffer is not a fixed array, but instead gets pointed to the buffers
\r
118 allocated within this file. */
\r
119 unsigned char * uip_buf;
\r
121 /* Store the length of the data being sent so the data can be sent twice. The
\r
122 value will be set back to 0 once the data has been sent twice. */
\r
123 static unsigned short usSendLen = 0;
\r
125 /*-----------------------------------------------------------*/
\r
127 long lEMACInit( void )
\r
129 long lReturn = pdPASS;
\r
130 unsigned long ulID1, ulID2;
\r
132 /* Reset peripherals, configure port pins and registers. */
\r
133 prvSetupEMACHardware();
\r
135 /* Check the PHY part number is as expected. */
\r
136 ulID1 = prvReadPHY( PHY_REG_IDR1, &lReturn );
\r
137 ulID2 = prvReadPHY( PHY_REG_IDR2, &lReturn );
\r
138 if( ( (ulID1 << 16UL ) | ( ulID2 & 0xFFFFUL ) ) == KS8721_ID )
\r
140 /* Set the Ethernet MAC Address registers */
\r
141 EMAC->SA0 = ( configMAC_ADDR0 << 8 ) | configMAC_ADDR1;
\r
142 EMAC->SA1 = ( configMAC_ADDR2 << 8 ) | configMAC_ADDR3;
\r
143 EMAC->SA2 = ( configMAC_ADDR4 << 8 ) | configMAC_ADDR5;
\r
145 /* Initialize Tx and Rx DMA Descriptors */
\r
146 prvInitDescriptors();
\r
148 /* Receive broadcast and perfect match packets */
\r
149 EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
\r
151 /* Setup the PHY. */
\r
159 /* Check the link status. */
\r
160 if( lReturn == pdPASS )
\r
162 lReturn = prvSetupLinkStatus();
\r
165 if( lReturn == pdPASS )
\r
167 /* Initialise uip_buf to ensure it points somewhere valid. */
\r
168 uip_buf = prvGetNextBuffer();
\r
170 /* Reset all interrupts */
\r
171 EMAC->IntClear = ( INT_RX_OVERRUN | INT_RX_ERR | INT_RX_FIN | INT_RX_DONE | INT_TX_UNDERRUN | INT_TX_ERR | INT_TX_FIN | INT_TX_DONE | INT_SOFT_INT | INT_WAKEUP );
\r
173 /* Enable receive and transmit mode of MAC Ethernet core */
\r
174 EMAC->Command |= ( CR_RX_EN | CR_TX_EN );
\r
175 EMAC->MAC1 |= MAC1_REC_EN;
\r
180 /*-----------------------------------------------------------*/
\r
182 static unsigned char *prvGetNextBuffer( void )
\r
185 unsigned char *pucReturn = NULL;
\r
186 unsigned long ulAttempts = 0;
\r
188 while( pucReturn == NULL )
\r
190 /* Look through the buffers to find one that is not in use by
\r
192 for( x = 0; x < ETH_NUM_BUFFERS; x++ )
\r
194 if( ucBufferInUse[ x ] == pdFALSE )
\r
196 ucBufferInUse[ x ] = pdTRUE;
\r
197 pucReturn = ( unsigned char * ) ETH_BUF( x );
\r
202 /* Was a buffer found? */
\r
203 if( pucReturn == NULL )
\r
207 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
\r
212 /* Wait then look again. */
\r
213 vTaskDelay( emacBUFFER_WAIT_DELAY );
\r
219 /*-----------------------------------------------------------*/
\r
221 static void prvInitDescriptors( void )
\r
223 long x, lNextBuffer = 0;
\r
225 for( x = 0; x < NUM_RX_FRAG; x++ )
\r
227 /* Allocate the next Ethernet buffer to this descriptor. */
\r
228 RX_DESC_PACKET( x ) = ETH_BUF( lNextBuffer );
\r
229 RX_DESC_CTRL( x ) = RCTRL_INT | ( ETH_FRAG_SIZE - 1 );
\r
230 RX_STAT_INFO( x ) = 0;
\r
231 RX_STAT_HASHCRC( x ) = 0;
\r
233 /* The Ethernet buffer is now in use. */
\r
234 ucBufferInUse[ lNextBuffer ] = pdTRUE;
\r
238 /* Set EMAC Receive Descriptor Registers. */
\r
239 EMAC->RxDescriptor = RX_DESC_BASE;
\r
240 EMAC->RxStatus = RX_STAT_BASE;
\r
241 EMAC->RxDescriptorNumber = NUM_RX_FRAG - 1;
\r
243 /* Rx Descriptors Point to 0 */
\r
244 EMAC->RxConsumeIndex = 0;
\r
246 /* A buffer is not allocated to the Tx descriptors until they are actually
\r
248 for( x = 0; x < NUM_TX_FRAG; x++ )
\r
250 TX_DESC_PACKET( x ) = ( unsigned long ) NULL;
\r
251 TX_DESC_CTRL( x ) = 0;
\r
252 TX_STAT_INFO( x ) = 0;
\r
255 /* Set EMAC Transmit Descriptor Registers. */
\r
256 EMAC->TxDescriptor = TX_DESC_BASE;
\r
257 EMAC->TxStatus = TX_STAT_BASE;
\r
258 EMAC->TxDescriptorNumber = NUM_TX_FRAG - 1;
\r
260 /* Tx Descriptors Point to 0 */
\r
261 EMAC->TxProduceIndex = 0;
\r
263 /*-----------------------------------------------------------*/
\r
265 static void prvSetupEMACHardware( void )
\r
270 /* Enable P1 Ethernet Pins. */
\r
271 PINCON->PINSEL2 = emacPINSEL2_VALUE;
\r
272 PINCON->PINSEL3 = ( PINCON->PINSEL3 & ~0x0000000F ) | 0x00000005;
\r
274 /* Power Up the EMAC controller. */
\r
275 SC->PCONP |= PCONP_PCENET;
\r
276 vTaskDelay( emacSHORT_DELAY );
\r
278 /* Reset all EMAC internal modules. */
\r
279 EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
\r
280 EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
\r
282 /* A short delay after reset. */
\r
283 vTaskDelay( emacSHORT_DELAY );
\r
285 /* Initialize MAC control registers. */
\r
286 EMAC->MAC1 = MAC1_PASS_ALL;
\r
287 EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
\r
288 EMAC->MAXF = ETH_MAX_FLEN;
\r
289 EMAC->CLRT = CLRT_DEF;
\r
290 EMAC->IPGR = IPGR_DEF;
\r
291 EMAC->MCFG = emacDIV_44;
\r
293 /* Enable Reduced MII interface. */
\r
294 EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
\r
296 /* Reset Reduced MII Logic. */
\r
297 EMAC->SUPP = SUPP_RES_RMII;
\r
298 vTaskDelay( emacSHORT_DELAY );
\r
301 /* Put the PHY in reset mode */
\r
302 prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
\r
303 prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
\r
305 /* Wait for hardware reset to end. */
\r
306 for( x = 0; x < 100; x++ )
\r
308 vTaskDelay( emacSHORT_DELAY * 5 );
\r
309 us = prvReadPHY( PHY_REG_BMCR, &lDummy );
\r
310 if( !( us & MCFG_RES_MII ) )
\r
312 /* Reset complete */
\r
317 /*-----------------------------------------------------------*/
\r
319 static void prvConfigurePHY( void )
\r
324 /* Auto negotiate the configuration. */
\r
325 if( prvWritePHY( PHY_REG_BMCR, PHY_AUTO_NEG ) )
\r
327 vTaskDelay( emacSHORT_DELAY * 5 );
\r
329 for( x = 0; x < 10; x++ )
\r
331 us = prvReadPHY( PHY_REG_BMSR, &lDummy );
\r
333 if( us & PHY_AUTO_NEG_COMPLETE )
\r
338 vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
\r
342 /*-----------------------------------------------------------*/
\r
344 static long prvSetupLinkStatus( void )
\r
346 long lReturn = pdFAIL, x;
\r
347 unsigned short usLinkStatus;
\r
349 /* Wait with timeout for the link to be established. */
\r
350 for( x = 0; x < 10; x++ )
\r
352 usLinkStatus = prvReadPHY( PHY_CTRLER, &lReturn );
\r
353 if( usLinkStatus != 0x00 )
\r
355 /* Link is established. */
\r
360 vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
\r
363 if( lReturn == pdPASS )
\r
365 /* Configure Full/Half Duplex mode. */
\r
366 if( usLinkStatus & emacFULL_DUPLEX_ENABLED )
\r
368 /* Full duplex is enabled. */
\r
369 EMAC->MAC2 |= MAC2_FULL_DUP;
\r
370 EMAC->Command |= CR_FULL_DUP;
\r
371 EMAC->IPGT = IPGT_FULL_DUP;
\r
375 /* Half duplex mode. */
\r
376 EMAC->IPGT = IPGT_HALF_DUP;
\r
379 /* Configure 100MBit/10MBit mode. */
\r
380 if( usLinkStatus & emac10BASE_T_MODE )
\r
387 /* 100MBit mode. */
\r
388 EMAC->SUPP = SUPP_SPEED;
\r
394 /*-----------------------------------------------------------*/
\r
396 static void prvReturnBuffer( unsigned char *pucBuffer )
\r
400 /* Return a buffer to the pool of free buffers. */
\r
401 for( ul = 0; ul < ETH_NUM_BUFFERS; ul++ )
\r
403 if( ETH_BUF( ul ) == ( unsigned long ) pucBuffer )
\r
405 ucBufferInUse[ ul ] = pdFALSE;
\r
410 /*-----------------------------------------------------------*/
\r
412 unsigned long ulGetEMACRxData( void )
\r
414 unsigned long ulLen = 0;
\r
417 if( EMAC->RxProduceIndex != EMAC->RxConsumeIndex )
\r
419 /* Mark the current buffer as free as uip_buf is going to be set to
\r
420 the buffer that contains the received data. */
\r
421 prvReturnBuffer( uip_buf );
\r
423 ulLen = ( RX_STAT_INFO( EMAC->RxConsumeIndex ) & RINFO_SIZE ) - 3;
\r
424 uip_buf = ( unsigned char * ) RX_DESC_PACKET( EMAC->RxConsumeIndex );
\r
426 /* Allocate a new buffer to the descriptor. */
\r
427 RX_DESC_PACKET( EMAC->RxConsumeIndex ) = ( unsigned long ) prvGetNextBuffer();
\r
429 /* Move the consume index onto the next position, ensuring it wraps to
\r
430 the beginning at the appropriate place. */
\r
431 lIndex = EMAC->RxConsumeIndex;
\r
434 if( lIndex >= NUM_RX_FRAG )
\r
439 EMAC->RxConsumeIndex = lIndex;
\r
444 /*-----------------------------------------------------------*/
\r
446 void vSendEMACTxData( unsigned short usTxDataLen )
\r
448 unsigned long ulAttempts = 0UL;
\r
450 /* Check to see if the Tx descriptor is free, indicated by its buffer being
\r
452 while( TX_DESC_PACKET( emacTX_DESC_INDEX ) != ( unsigned long ) NULL )
\r
454 /* Wait for the Tx descriptor to become available. */
\r
455 vTaskDelay( emacBUFFER_WAIT_DELAY );
\r
458 if( ulAttempts > emacBUFFER_WAIT_ATTEMPTS )
\r
460 /* Something has gone wrong as the Tx descriptor is still in use.
\r
461 Clear it down manually, the data it was sending will probably be
\r
463 prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );
\r
468 /* Setup the Tx descriptor for transmission. Remember the length of the
\r
469 data being sent so the second descriptor can be used to send it again from
\r
471 usSendLen = usTxDataLen;
\r
472 TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) uip_buf;
\r
473 TX_DESC_CTRL( emacTX_DESC_INDEX ) = ( usTxDataLen | TCTRL_LAST | TCTRL_INT );
\r
474 EMAC->TxProduceIndex = ( emacTX_DESC_INDEX + 1 );
\r
476 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer. */
\r
477 uip_buf = prvGetNextBuffer();
\r
479 /*-----------------------------------------------------------*/
\r
481 static long prvWritePHY( long lPhyReg, long lValue )
\r
483 const long lMaxTime = 10;
\r
486 EMAC->MADR = KS8721_DEF_ADR | lPhyReg;
\r
487 EMAC->MWTD = lValue;
\r
490 for( x = 0; x < lMaxTime; x++ )
\r
492 if( ( EMAC->MIND & MIND_BUSY ) == 0 )
\r
494 /* Operation has finished. */
\r
498 vTaskDelay( emacSHORT_DELAY );
\r
510 /*-----------------------------------------------------------*/
\r
512 static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus )
\r
515 const long lMaxTime = 10;
\r
517 EMAC->MADR = KS8721_DEF_ADR | ucPhyReg;
\r
518 EMAC->MCMD = MCMD_READ;
\r
520 for( x = 0; x < lMaxTime; x++ )
\r
522 /* Operation has finished. */
\r
523 if( ( EMAC->MIND & MIND_BUSY ) == 0 )
\r
528 vTaskDelay( emacSHORT_DELAY );
\r
533 if( x >= lMaxTime )
\r
535 *plStatus = pdFAIL;
\r
538 return( EMAC->MRDD );
\r
540 /*-----------------------------------------------------------*/
\r
542 void vEMAC_ISR( void )
\r
544 unsigned long ulStatus;
\r
545 long lHigherPriorityTaskWoken = pdFALSE;
\r
547 ulStatus = EMAC->IntStatus;
\r
549 /* Clear the interrupt. */
\r
550 EMAC->IntClear = ulStatus;
\r
552 if( ulStatus & INT_RX_DONE )
\r
554 /* Ensure the uIP task is not blocked as data has arrived. */
\r
555 xSemaphoreGiveFromISR( xEMACSemaphore, &lHigherPriorityTaskWoken );
\r
558 if( ulStatus & INT_TX_DONE )
\r
560 if( usSendLen > 0 )
\r
562 /* Send the data again, using the second descriptor. As there are
\r
563 only two descriptors the index is set back to 0. */
\r
564 TX_DESC_PACKET( ( emacTX_DESC_INDEX + 1 ) ) = TX_DESC_PACKET( emacTX_DESC_INDEX );
\r
565 TX_DESC_CTRL( ( emacTX_DESC_INDEX + 1 ) ) = ( usSendLen | TCTRL_LAST | TCTRL_INT );
\r
566 EMAC->TxProduceIndex = ( emacTX_DESC_INDEX );
\r
568 /* This is the second Tx so set usSendLen to 0 to indicate that the
\r
569 Tx descriptors will be free again. */
\r
574 /* The Tx buffer is no longer required. */
\r
575 prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );
\r
576 TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) NULL;
\r
580 portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );
\r