2 * FreeRTOS Kernel V10.1.1
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3 * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /* Originally adapted from file written by Andreas Dannenberg. Supplied with permission. */
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30 /* Kernel includes. */
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31 #include "FreeRTOS.h"
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35 /* Hardware specific includes. */
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36 #include "EthDev_LPC17xx.h"
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38 /* Time to wait between each inspection of the link status. */
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39 #define emacWAIT_FOR_LINK_TO_ESTABLISH ( 500 / portTICK_PERIOD_MS )
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41 /* Short delay used in several places during the initialisation process. */
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42 #define emacSHORT_DELAY ( 2 )
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44 /* Hardware specific bit definitions. */
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45 #define emacLINK_ESTABLISHED ( 0x0020)
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46 #define emacFULL_DUPLEX_ENABLED ( 0x0010 )
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47 #define emac10BASE_T_MODE ( 0x0004 )
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48 #define emacPINSEL2_VALUE ( 0x50150105 )
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49 #define emacDIV_44 ( 0x28 )
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51 /* If no buffers are available, then wait this long before looking again.... */
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52 #define emacBUFFER_WAIT_DELAY ( 3 / portTICK_PERIOD_MS )
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54 /* ...and don't look more than this many times. */
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55 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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57 /* Index to the Tx descriptor that is always used first for every Tx. The second
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58 descriptor is then used to re-send in order to speed up the uIP Tx process. */
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59 #define emacTX_DESC_INDEX ( 0 )
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61 /*-----------------------------------------------------------*/
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64 * Configure both the Rx and Tx descriptors during the init process.
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66 static void prvInitDescriptors( void );
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69 * Setup the IO and peripherals required for Ethernet communication.
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71 static void prvSetupEMACHardware( void );
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74 * Control the auto negotiate process.
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76 static void prvConfigurePHY( void );
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79 * Wait for a link to be established, then setup the PHY according to the link
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82 static long prvSetupLinkStatus( void );
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85 * Search the pool of buffers to find one that is free. If a buffer is found
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86 * mark it as in use before returning its address.
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88 static unsigned char *prvGetNextBuffer( void );
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91 * Return an allocated buffer to the pool of free buffers.
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93 static void prvReturnBuffer( unsigned char *pucBuffer );
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96 * Send lValue to the lPhyReg within the PHY.
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98 static long prvWritePHY( long lPhyReg, long lValue );
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101 * Read a value from ucPhyReg within the PHY. *plStatus will be set to
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102 * pdFALSE if there is an error.
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104 static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus );
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106 /*-----------------------------------------------------------*/
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108 /* The semaphore used to wake the uIP task when data arrives. */
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109 extern SemaphoreHandle_t xEMACSemaphore;
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111 /* Each ucBufferInUse index corresponds to a position in the pool of buffers.
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112 If the index contains a 1 then the buffer within pool is in use, if it
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113 contains a 0 then the buffer is free. */
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114 static unsigned char ucBufferInUse[ ETH_NUM_BUFFERS ] = { pdFALSE };
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116 /* The uip_buffer is not a fixed array, but instead gets pointed to the buffers
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117 allocated within this file. */
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118 unsigned char * uip_buf;
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120 /* Store the length of the data being sent so the data can be sent twice. The
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121 value will be set back to 0 once the data has been sent twice. */
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122 static unsigned short usSendLen = 0;
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124 /*-----------------------------------------------------------*/
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126 long lEMACInit( void )
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128 long lReturn = pdPASS;
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129 unsigned long ulID1, ulID2;
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131 /* Reset peripherals, configure port pins and registers. */
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132 prvSetupEMACHardware();
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134 /* Check the PHY part number is as expected. */
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135 ulID1 = prvReadPHY( PHY_REG_IDR1, &lReturn );
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136 ulID2 = prvReadPHY( PHY_REG_IDR2, &lReturn );
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137 if( ( (ulID1 << 16UL ) | ( ulID2 & 0xFFFFUL ) ) == KS8721_ID )
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139 /* Set the Ethernet MAC Address registers */
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140 EMAC->SA0 = ( configMAC_ADDR0 << 8 ) | configMAC_ADDR1;
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141 EMAC->SA1 = ( configMAC_ADDR2 << 8 ) | configMAC_ADDR3;
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142 EMAC->SA2 = ( configMAC_ADDR4 << 8 ) | configMAC_ADDR5;
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144 /* Initialize Tx and Rx DMA Descriptors */
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145 prvInitDescriptors();
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147 /* Receive broadcast and perfect match packets */
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148 EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
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150 /* Setup the PHY. */
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158 /* Check the link status. */
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159 if( lReturn == pdPASS )
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161 lReturn = prvSetupLinkStatus();
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164 if( lReturn == pdPASS )
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166 /* Initialise uip_buf to ensure it points somewhere valid. */
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167 uip_buf = prvGetNextBuffer();
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169 /* Reset all interrupts */
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170 EMAC->IntClear = ( INT_RX_OVERRUN | INT_RX_ERR | INT_RX_FIN | INT_RX_DONE | INT_TX_UNDERRUN | INT_TX_ERR | INT_TX_FIN | INT_TX_DONE | INT_SOFT_INT | INT_WAKEUP );
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172 /* Enable receive and transmit mode of MAC Ethernet core */
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173 EMAC->Command |= ( CR_RX_EN | CR_TX_EN );
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174 EMAC->MAC1 |= MAC1_REC_EN;
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179 /*-----------------------------------------------------------*/
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181 static unsigned char *prvGetNextBuffer( void )
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184 unsigned char *pucReturn = NULL;
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185 unsigned long ulAttempts = 0;
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187 while( pucReturn == NULL )
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189 /* Look through the buffers to find one that is not in use by
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191 for( x = 0; x < ETH_NUM_BUFFERS; x++ )
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193 if( ucBufferInUse[ x ] == pdFALSE )
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195 ucBufferInUse[ x ] = pdTRUE;
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196 pucReturn = ( unsigned char * ) ETH_BUF( x );
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201 /* Was a buffer found? */
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202 if( pucReturn == NULL )
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206 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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211 /* Wait then look again. */
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212 vTaskDelay( emacBUFFER_WAIT_DELAY );
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218 /*-----------------------------------------------------------*/
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220 static void prvInitDescriptors( void )
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222 long x, lNextBuffer = 0;
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224 for( x = 0; x < NUM_RX_FRAG; x++ )
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226 /* Allocate the next Ethernet buffer to this descriptor. */
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227 RX_DESC_PACKET( x ) = ETH_BUF( lNextBuffer );
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228 RX_DESC_CTRL( x ) = RCTRL_INT | ( ETH_FRAG_SIZE - 1 );
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229 RX_STAT_INFO( x ) = 0;
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230 RX_STAT_HASHCRC( x ) = 0;
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232 /* The Ethernet buffer is now in use. */
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233 ucBufferInUse[ lNextBuffer ] = pdTRUE;
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237 /* Set EMAC Receive Descriptor Registers. */
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238 EMAC->RxDescriptor = RX_DESC_BASE;
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239 EMAC->RxStatus = RX_STAT_BASE;
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240 EMAC->RxDescriptorNumber = NUM_RX_FRAG - 1;
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242 /* Rx Descriptors Point to 0 */
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243 EMAC->RxConsumeIndex = 0;
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245 /* A buffer is not allocated to the Tx descriptors until they are actually
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247 for( x = 0; x < NUM_TX_FRAG; x++ )
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249 TX_DESC_PACKET( x ) = ( unsigned long ) NULL;
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250 TX_DESC_CTRL( x ) = 0;
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251 TX_STAT_INFO( x ) = 0;
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254 /* Set EMAC Transmit Descriptor Registers. */
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255 EMAC->TxDescriptor = TX_DESC_BASE;
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256 EMAC->TxStatus = TX_STAT_BASE;
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257 EMAC->TxDescriptorNumber = NUM_TX_FRAG - 1;
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259 /* Tx Descriptors Point to 0 */
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260 EMAC->TxProduceIndex = 0;
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262 /*-----------------------------------------------------------*/
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264 static void prvSetupEMACHardware( void )
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269 /* Enable P1 Ethernet Pins. */
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270 PINCON->PINSEL2 = emacPINSEL2_VALUE;
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271 PINCON->PINSEL3 = ( PINCON->PINSEL3 & ~0x0000000F ) | 0x00000005;
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273 /* Power Up the EMAC controller. */
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274 SC->PCONP |= PCONP_PCENET;
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275 vTaskDelay( emacSHORT_DELAY );
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277 /* Reset all EMAC internal modules. */
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278 EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
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279 EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
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281 /* A short delay after reset. */
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282 vTaskDelay( emacSHORT_DELAY );
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284 /* Initialize MAC control registers. */
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285 EMAC->MAC1 = MAC1_PASS_ALL;
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286 EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
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287 EMAC->MAXF = ETH_MAX_FLEN;
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288 EMAC->CLRT = CLRT_DEF;
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289 EMAC->IPGR = IPGR_DEF;
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290 EMAC->MCFG = emacDIV_44;
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292 /* Enable Reduced MII interface. */
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293 EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
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295 /* Reset Reduced MII Logic. */
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296 EMAC->SUPP = SUPP_RES_RMII;
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297 vTaskDelay( emacSHORT_DELAY );
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300 /* Put the PHY in reset mode */
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301 prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
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302 prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
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304 /* Wait for hardware reset to end. */
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305 for( x = 0; x < 100; x++ )
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307 vTaskDelay( emacSHORT_DELAY * 5 );
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308 us = prvReadPHY( PHY_REG_BMCR, &lDummy );
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309 if( !( us & MCFG_RES_MII ) )
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311 /* Reset complete */
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316 /*-----------------------------------------------------------*/
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318 static void prvConfigurePHY( void )
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323 /* Auto negotiate the configuration. */
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324 if( prvWritePHY( PHY_REG_BMCR, PHY_AUTO_NEG ) )
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326 vTaskDelay( emacSHORT_DELAY * 5 );
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328 for( x = 0; x < 10; x++ )
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330 us = prvReadPHY( PHY_REG_BMSR, &lDummy );
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332 if( us & PHY_AUTO_NEG_COMPLETE )
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337 vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
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341 /*-----------------------------------------------------------*/
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343 static long prvSetupLinkStatus( void )
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345 long lReturn = pdFAIL, x;
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346 unsigned short usLinkStatus;
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348 /* Wait with timeout for the link to be established. */
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349 for( x = 0; x < 10; x++ )
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351 usLinkStatus = prvReadPHY( PHY_CTRLER, &lReturn );
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352 if( usLinkStatus != 0x00 )
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354 /* Link is established. */
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359 vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
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362 if( lReturn == pdPASS )
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364 /* Configure Full/Half Duplex mode. */
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365 if( usLinkStatus & emacFULL_DUPLEX_ENABLED )
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367 /* Full duplex is enabled. */
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368 EMAC->MAC2 |= MAC2_FULL_DUP;
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369 EMAC->Command |= CR_FULL_DUP;
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370 EMAC->IPGT = IPGT_FULL_DUP;
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374 /* Half duplex mode. */
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375 EMAC->IPGT = IPGT_HALF_DUP;
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378 /* Configure 100MBit/10MBit mode. */
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379 if( usLinkStatus & emac10BASE_T_MODE )
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386 /* 100MBit mode. */
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387 EMAC->SUPP = SUPP_SPEED;
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393 /*-----------------------------------------------------------*/
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395 static void prvReturnBuffer( unsigned char *pucBuffer )
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399 /* Return a buffer to the pool of free buffers. */
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400 for( ul = 0; ul < ETH_NUM_BUFFERS; ul++ )
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402 if( ETH_BUF( ul ) == ( unsigned long ) pucBuffer )
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404 ucBufferInUse[ ul ] = pdFALSE;
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409 /*-----------------------------------------------------------*/
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411 unsigned long ulGetEMACRxData( void )
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413 unsigned long ulLen = 0;
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416 if( EMAC->RxProduceIndex != EMAC->RxConsumeIndex )
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418 /* Mark the current buffer as free as uip_buf is going to be set to
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419 the buffer that contains the received data. */
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420 prvReturnBuffer( uip_buf );
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422 ulLen = ( RX_STAT_INFO( EMAC->RxConsumeIndex ) & RINFO_SIZE ) - 3;
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423 uip_buf = ( unsigned char * ) RX_DESC_PACKET( EMAC->RxConsumeIndex );
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425 /* Allocate a new buffer to the descriptor. */
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426 RX_DESC_PACKET( EMAC->RxConsumeIndex ) = ( unsigned long ) prvGetNextBuffer();
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428 /* Move the consume index onto the next position, ensuring it wraps to
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429 the beginning at the appropriate place. */
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430 lIndex = EMAC->RxConsumeIndex;
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433 if( lIndex >= NUM_RX_FRAG )
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438 EMAC->RxConsumeIndex = lIndex;
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443 /*-----------------------------------------------------------*/
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445 void vSendEMACTxData( unsigned short usTxDataLen )
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447 unsigned long ulAttempts = 0UL;
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449 /* Check to see if the Tx descriptor is free, indicated by its buffer being
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451 while( TX_DESC_PACKET( emacTX_DESC_INDEX ) != ( unsigned long ) NULL )
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453 /* Wait for the Tx descriptor to become available. */
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454 vTaskDelay( emacBUFFER_WAIT_DELAY );
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457 if( ulAttempts > emacBUFFER_WAIT_ATTEMPTS )
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459 /* Something has gone wrong as the Tx descriptor is still in use.
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460 Clear it down manually, the data it was sending will probably be
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462 prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );
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467 /* Setup the Tx descriptor for transmission. Remember the length of the
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468 data being sent so the second descriptor can be used to send it again from
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470 usSendLen = usTxDataLen;
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471 TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) uip_buf;
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472 TX_DESC_CTRL( emacTX_DESC_INDEX ) = ( usTxDataLen | TCTRL_LAST | TCTRL_INT );
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473 EMAC->TxProduceIndex = ( emacTX_DESC_INDEX + 1 );
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475 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer. */
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476 uip_buf = prvGetNextBuffer();
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478 /*-----------------------------------------------------------*/
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480 static long prvWritePHY( long lPhyReg, long lValue )
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482 const long lMaxTime = 10;
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485 EMAC->MADR = KS8721_DEF_ADR | lPhyReg;
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486 EMAC->MWTD = lValue;
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489 for( x = 0; x < lMaxTime; x++ )
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491 if( ( EMAC->MIND & MIND_BUSY ) == 0 )
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493 /* Operation has finished. */
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497 vTaskDelay( emacSHORT_DELAY );
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509 /*-----------------------------------------------------------*/
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511 static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus )
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514 const long lMaxTime = 10;
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516 EMAC->MADR = KS8721_DEF_ADR | ucPhyReg;
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517 EMAC->MCMD = MCMD_READ;
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519 for( x = 0; x < lMaxTime; x++ )
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521 /* Operation has finished. */
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522 if( ( EMAC->MIND & MIND_BUSY ) == 0 )
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527 vTaskDelay( emacSHORT_DELAY );
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532 if( x >= lMaxTime )
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534 *plStatus = pdFAIL;
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537 return( EMAC->MRDD );
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539 /*-----------------------------------------------------------*/
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541 void vEMAC_ISR( void )
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543 unsigned long ulStatus;
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544 long lHigherPriorityTaskWoken = pdFALSE;
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546 ulStatus = EMAC->IntStatus;
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548 /* Clear the interrupt. */
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549 EMAC->IntClear = ulStatus;
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551 if( ulStatus & INT_RX_DONE )
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553 /* Ensure the uIP task is not blocked as data has arrived. */
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554 xSemaphoreGiveFromISR( xEMACSemaphore, &lHigherPriorityTaskWoken );
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557 if( ulStatus & INT_TX_DONE )
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559 if( usSendLen > 0 )
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561 /* Send the data again, using the second descriptor. As there are
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562 only two descriptors the index is set back to 0. */
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563 TX_DESC_PACKET( ( emacTX_DESC_INDEX + 1 ) ) = TX_DESC_PACKET( emacTX_DESC_INDEX );
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564 TX_DESC_CTRL( ( emacTX_DESC_INDEX + 1 ) ) = ( usSendLen | TCTRL_LAST | TCTRL_INT );
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565 EMAC->TxProduceIndex = ( emacTX_DESC_INDEX );
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567 /* This is the second Tx so set usSendLen to 0 to indicate that the
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568 Tx descriptors will be free again. */
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573 /* The Tx buffer is no longer required. */
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574 prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );
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575 TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) NULL;
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579 portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );
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