2 FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.
\r
4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
\r
5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
7 ***************************************************************************
\r
9 * FreeRTOS tutorial books are available in pdf and paperback. *
\r
10 * Complete, revised, and edited pdf reference manuals are also *
\r
13 * Purchasing FreeRTOS documentation will not only help you, by *
\r
14 * ensuring you get running as quickly as possible and with an *
\r
15 * in-depth knowledge of how to use FreeRTOS, it will also help *
\r
16 * the FreeRTOS project to continue with its mission of providing *
\r
17 * professional grade, cross platform, de facto standard solutions *
\r
18 * for microcontrollers - completely free of charge! *
\r
20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
\r
22 * Thank you for using FreeRTOS, and thank you for your support! *
\r
24 ***************************************************************************
\r
27 This file is part of the FreeRTOS distribution.
\r
29 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
30 the terms of the GNU General Public License (version 2) as published by the
\r
31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
\r
32 >>>NOTE<<< The modification to the GPL is included to allow you to
\r
33 distribute a combined work that includes FreeRTOS without being obliged to
\r
34 provide the source code for proprietary components outside of the FreeRTOS
\r
35 kernel. FreeRTOS is distributed in the hope that it will be useful, but
\r
36 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
\r
37 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
\r
38 more details. You should have received a copy of the GNU General Public
\r
39 License and the FreeRTOS license exception along with FreeRTOS; if not it
\r
40 can be viewed here: http://www.freertos.org/a00114.html and also obtained
\r
41 by writing to Richard Barry, contact details for whom are available on the
\r
46 ***************************************************************************
\r
48 * Having a problem? Start by reading the FAQ "My application does *
\r
49 * not run, what could be wrong?" *
\r
51 * http://www.FreeRTOS.org/FAQHelp.html *
\r
53 ***************************************************************************
\r
56 http://www.FreeRTOS.org - Documentation, training, latest versions, license
\r
57 and contact details.
\r
59 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
60 including FreeRTOS+Trace - an indispensable productivity tool.
\r
62 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
\r
63 the code with commercial support, indemnification, and middleware, under
\r
64 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
\r
65 provide a safety engineered and independently SIL3 certified version under
\r
66 the SafeRTOS brand: http://www.SafeRTOS.com.
\r
69 /* Originally adapted from file written by Andreas Dannenberg. Supplied with permission. */
\r
71 /* Kernel includes. */
\r
72 #include "FreeRTOS.h"
\r
76 /* Hardware specific includes. */
\r
77 #include "EthDev_LPC17xx.h"
\r
79 /* Time to wait between each inspection of the link status. */
\r
80 #define emacWAIT_FOR_LINK_TO_ESTABLISH ( 500 / portTICK_RATE_MS )
\r
82 /* Short delay used in several places during the initialisation process. */
\r
83 #define emacSHORT_DELAY ( 2 )
\r
85 /* Hardware specific bit definitions. */
\r
86 #define emacLINK_ESTABLISHED ( 0x0020)
\r
87 #define emacFULL_DUPLEX_ENABLED ( 0x0010 )
\r
88 #define emac10BASE_T_MODE ( 0x0004 )
\r
89 #define emacPINSEL2_VALUE ( 0x50150105 )
\r
90 #define emacDIV_44 ( 0x28 )
\r
92 /* If no buffers are available, then wait this long before looking again.... */
\r
93 #define emacBUFFER_WAIT_DELAY ( 3 / portTICK_RATE_MS )
\r
95 /* ...and don't look more than this many times. */
\r
96 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
\r
98 /* Index to the Tx descriptor that is always used first for every Tx. The second
\r
99 descriptor is then used to re-send in order to speed up the uIP Tx process. */
\r
100 #define emacTX_DESC_INDEX ( 0 )
\r
102 /*-----------------------------------------------------------*/
\r
105 * Configure both the Rx and Tx descriptors during the init process.
\r
107 static void prvInitDescriptors( void );
\r
110 * Setup the IO and peripherals required for Ethernet communication.
\r
112 static void prvSetupEMACHardware( void );
\r
115 * Control the auto negotiate process.
\r
117 static void prvConfigurePHY( void );
\r
120 * Wait for a link to be established, then setup the PHY according to the link
\r
123 static long prvSetupLinkStatus( void );
\r
126 * Search the pool of buffers to find one that is free. If a buffer is found
\r
127 * mark it as in use before returning its address.
\r
129 static unsigned char *prvGetNextBuffer( void );
\r
132 * Return an allocated buffer to the pool of free buffers.
\r
134 static void prvReturnBuffer( unsigned char *pucBuffer );
\r
137 * Send lValue to the lPhyReg within the PHY.
\r
139 static long prvWritePHY( long lPhyReg, long lValue );
\r
142 * Read a value from ucPhyReg within the PHY. *plStatus will be set to
\r
143 * pdFALSE if there is an error.
\r
145 static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus );
\r
147 /*-----------------------------------------------------------*/
\r
149 /* The semaphore used to wake the uIP task when data arrives. */
\r
150 extern xSemaphoreHandle xEMACSemaphore;
\r
152 /* Each ucBufferInUse index corresponds to a position in the pool of buffers.
\r
153 If the index contains a 1 then the buffer within pool is in use, if it
\r
154 contains a 0 then the buffer is free. */
\r
155 static unsigned char ucBufferInUse[ ETH_NUM_BUFFERS ] = { pdFALSE };
\r
157 /* The uip_buffer is not a fixed array, but instead gets pointed to the buffers
\r
158 allocated within this file. */
\r
159 unsigned char * uip_buf;
\r
161 /* Store the length of the data being sent so the data can be sent twice. The
\r
162 value will be set back to 0 once the data has been sent twice. */
\r
163 static unsigned short usSendLen = 0;
\r
165 /*-----------------------------------------------------------*/
\r
167 long lEMACInit( void )
\r
169 long lReturn = pdPASS;
\r
170 unsigned long ulID1, ulID2;
\r
172 /* Reset peripherals, configure port pins and registers. */
\r
173 prvSetupEMACHardware();
\r
175 /* Check the PHY part number is as expected. */
\r
176 ulID1 = prvReadPHY( PHY_REG_IDR1, &lReturn );
\r
177 ulID2 = prvReadPHY( PHY_REG_IDR2, &lReturn );
\r
178 if( ( (ulID1 << 16UL ) | ( ulID2 & 0xFFFFUL ) ) == KS8721_ID )
\r
180 /* Set the Ethernet MAC Address registers */
\r
181 EMAC->SA0 = ( configMAC_ADDR0 << 8 ) | configMAC_ADDR1;
\r
182 EMAC->SA1 = ( configMAC_ADDR2 << 8 ) | configMAC_ADDR3;
\r
183 EMAC->SA2 = ( configMAC_ADDR4 << 8 ) | configMAC_ADDR5;
\r
185 /* Initialize Tx and Rx DMA Descriptors */
\r
186 prvInitDescriptors();
\r
188 /* Receive broadcast and perfect match packets */
\r
189 EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
\r
191 /* Setup the PHY. */
\r
199 /* Check the link status. */
\r
200 if( lReturn == pdPASS )
\r
202 lReturn = prvSetupLinkStatus();
\r
205 if( lReturn == pdPASS )
\r
207 /* Initialise uip_buf to ensure it points somewhere valid. */
\r
208 uip_buf = prvGetNextBuffer();
\r
210 /* Reset all interrupts */
\r
211 EMAC->IntClear = ( INT_RX_OVERRUN | INT_RX_ERR | INT_RX_FIN | INT_RX_DONE | INT_TX_UNDERRUN | INT_TX_ERR | INT_TX_FIN | INT_TX_DONE | INT_SOFT_INT | INT_WAKEUP );
\r
213 /* Enable receive and transmit mode of MAC Ethernet core */
\r
214 EMAC->Command |= ( CR_RX_EN | CR_TX_EN );
\r
215 EMAC->MAC1 |= MAC1_REC_EN;
\r
220 /*-----------------------------------------------------------*/
\r
222 static unsigned char *prvGetNextBuffer( void )
\r
225 unsigned char *pucReturn = NULL;
\r
226 unsigned long ulAttempts = 0;
\r
228 while( pucReturn == NULL )
\r
230 /* Look through the buffers to find one that is not in use by
\r
232 for( x = 0; x < ETH_NUM_BUFFERS; x++ )
\r
234 if( ucBufferInUse[ x ] == pdFALSE )
\r
236 ucBufferInUse[ x ] = pdTRUE;
\r
237 pucReturn = ( unsigned char * ) ETH_BUF( x );
\r
242 /* Was a buffer found? */
\r
243 if( pucReturn == NULL )
\r
247 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
\r
252 /* Wait then look again. */
\r
253 vTaskDelay( emacBUFFER_WAIT_DELAY );
\r
259 /*-----------------------------------------------------------*/
\r
261 static void prvInitDescriptors( void )
\r
263 long x, lNextBuffer = 0;
\r
265 for( x = 0; x < NUM_RX_FRAG; x++ )
\r
267 /* Allocate the next Ethernet buffer to this descriptor. */
\r
268 RX_DESC_PACKET( x ) = ETH_BUF( lNextBuffer );
\r
269 RX_DESC_CTRL( x ) = RCTRL_INT | ( ETH_FRAG_SIZE - 1 );
\r
270 RX_STAT_INFO( x ) = 0;
\r
271 RX_STAT_HASHCRC( x ) = 0;
\r
273 /* The Ethernet buffer is now in use. */
\r
274 ucBufferInUse[ lNextBuffer ] = pdTRUE;
\r
278 /* Set EMAC Receive Descriptor Registers. */
\r
279 EMAC->RxDescriptor = RX_DESC_BASE;
\r
280 EMAC->RxStatus = RX_STAT_BASE;
\r
281 EMAC->RxDescriptorNumber = NUM_RX_FRAG - 1;
\r
283 /* Rx Descriptors Point to 0 */
\r
284 EMAC->RxConsumeIndex = 0;
\r
286 /* A buffer is not allocated to the Tx descriptors until they are actually
\r
288 for( x = 0; x < NUM_TX_FRAG; x++ )
\r
290 TX_DESC_PACKET( x ) = ( unsigned long ) NULL;
\r
291 TX_DESC_CTRL( x ) = 0;
\r
292 TX_STAT_INFO( x ) = 0;
\r
295 /* Set EMAC Transmit Descriptor Registers. */
\r
296 EMAC->TxDescriptor = TX_DESC_BASE;
\r
297 EMAC->TxStatus = TX_STAT_BASE;
\r
298 EMAC->TxDescriptorNumber = NUM_TX_FRAG - 1;
\r
300 /* Tx Descriptors Point to 0 */
\r
301 EMAC->TxProduceIndex = 0;
\r
303 /*-----------------------------------------------------------*/
\r
305 static void prvSetupEMACHardware( void )
\r
310 /* Enable P1 Ethernet Pins. */
\r
311 PINCON->PINSEL2 = emacPINSEL2_VALUE;
\r
312 PINCON->PINSEL3 = ( PINCON->PINSEL3 & ~0x0000000F ) | 0x00000005;
\r
314 /* Power Up the EMAC controller. */
\r
315 SC->PCONP |= PCONP_PCENET;
\r
316 vTaskDelay( emacSHORT_DELAY );
\r
318 /* Reset all EMAC internal modules. */
\r
319 EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
\r
320 EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
\r
322 /* A short delay after reset. */
\r
323 vTaskDelay( emacSHORT_DELAY );
\r
325 /* Initialize MAC control registers. */
\r
326 EMAC->MAC1 = MAC1_PASS_ALL;
\r
327 EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
\r
328 EMAC->MAXF = ETH_MAX_FLEN;
\r
329 EMAC->CLRT = CLRT_DEF;
\r
330 EMAC->IPGR = IPGR_DEF;
\r
331 EMAC->MCFG = emacDIV_44;
\r
333 /* Enable Reduced MII interface. */
\r
334 EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
\r
336 /* Reset Reduced MII Logic. */
\r
337 EMAC->SUPP = SUPP_RES_RMII;
\r
338 vTaskDelay( emacSHORT_DELAY );
\r
341 /* Put the PHY in reset mode */
\r
342 prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
\r
343 prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
\r
345 /* Wait for hardware reset to end. */
\r
346 for( x = 0; x < 100; x++ )
\r
348 vTaskDelay( emacSHORT_DELAY * 5 );
\r
349 us = prvReadPHY( PHY_REG_BMCR, &lDummy );
\r
350 if( !( us & MCFG_RES_MII ) )
\r
352 /* Reset complete */
\r
357 /*-----------------------------------------------------------*/
\r
359 static void prvConfigurePHY( void )
\r
364 /* Auto negotiate the configuration. */
\r
365 if( prvWritePHY( PHY_REG_BMCR, PHY_AUTO_NEG ) )
\r
367 vTaskDelay( emacSHORT_DELAY * 5 );
\r
369 for( x = 0; x < 10; x++ )
\r
371 us = prvReadPHY( PHY_REG_BMSR, &lDummy );
\r
373 if( us & PHY_AUTO_NEG_COMPLETE )
\r
378 vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
\r
382 /*-----------------------------------------------------------*/
\r
384 static long prvSetupLinkStatus( void )
\r
386 long lReturn = pdFAIL, x;
\r
387 unsigned short usLinkStatus;
\r
389 /* Wait with timeout for the link to be established. */
\r
390 for( x = 0; x < 10; x++ )
\r
392 usLinkStatus = prvReadPHY( PHY_CTRLER, &lReturn );
\r
393 if( usLinkStatus != 0x00 )
\r
395 /* Link is established. */
\r
400 vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
\r
403 if( lReturn == pdPASS )
\r
405 /* Configure Full/Half Duplex mode. */
\r
406 if( usLinkStatus & emacFULL_DUPLEX_ENABLED )
\r
408 /* Full duplex is enabled. */
\r
409 EMAC->MAC2 |= MAC2_FULL_DUP;
\r
410 EMAC->Command |= CR_FULL_DUP;
\r
411 EMAC->IPGT = IPGT_FULL_DUP;
\r
415 /* Half duplex mode. */
\r
416 EMAC->IPGT = IPGT_HALF_DUP;
\r
419 /* Configure 100MBit/10MBit mode. */
\r
420 if( usLinkStatus & emac10BASE_T_MODE )
\r
427 /* 100MBit mode. */
\r
428 EMAC->SUPP = SUPP_SPEED;
\r
434 /*-----------------------------------------------------------*/
\r
436 static void prvReturnBuffer( unsigned char *pucBuffer )
\r
440 /* Return a buffer to the pool of free buffers. */
\r
441 for( ul = 0; ul < ETH_NUM_BUFFERS; ul++ )
\r
443 if( ETH_BUF( ul ) == ( unsigned long ) pucBuffer )
\r
445 ucBufferInUse[ ul ] = pdFALSE;
\r
450 /*-----------------------------------------------------------*/
\r
452 unsigned long ulGetEMACRxData( void )
\r
454 unsigned long ulLen = 0;
\r
457 if( EMAC->RxProduceIndex != EMAC->RxConsumeIndex )
\r
459 /* Mark the current buffer as free as uip_buf is going to be set to
\r
460 the buffer that contains the received data. */
\r
461 prvReturnBuffer( uip_buf );
\r
463 ulLen = ( RX_STAT_INFO( EMAC->RxConsumeIndex ) & RINFO_SIZE ) - 3;
\r
464 uip_buf = ( unsigned char * ) RX_DESC_PACKET( EMAC->RxConsumeIndex );
\r
466 /* Allocate a new buffer to the descriptor. */
\r
467 RX_DESC_PACKET( EMAC->RxConsumeIndex ) = ( unsigned long ) prvGetNextBuffer();
\r
469 /* Move the consume index onto the next position, ensuring it wraps to
\r
470 the beginning at the appropriate place. */
\r
471 lIndex = EMAC->RxConsumeIndex;
\r
474 if( lIndex >= NUM_RX_FRAG )
\r
479 EMAC->RxConsumeIndex = lIndex;
\r
484 /*-----------------------------------------------------------*/
\r
486 void vSendEMACTxData( unsigned short usTxDataLen )
\r
488 unsigned long ulAttempts = 0UL;
\r
490 /* Check to see if the Tx descriptor is free, indicated by its buffer being
\r
492 while( TX_DESC_PACKET( emacTX_DESC_INDEX ) != ( unsigned long ) NULL )
\r
494 /* Wait for the Tx descriptor to become available. */
\r
495 vTaskDelay( emacBUFFER_WAIT_DELAY );
\r
498 if( ulAttempts > emacBUFFER_WAIT_ATTEMPTS )
\r
500 /* Something has gone wrong as the Tx descriptor is still in use.
\r
501 Clear it down manually, the data it was sending will probably be
\r
503 prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );
\r
508 /* Setup the Tx descriptor for transmission. Remember the length of the
\r
509 data being sent so the second descriptor can be used to send it again from
\r
511 usSendLen = usTxDataLen;
\r
512 TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) uip_buf;
\r
513 TX_DESC_CTRL( emacTX_DESC_INDEX ) = ( usTxDataLen | TCTRL_LAST | TCTRL_INT );
\r
514 EMAC->TxProduceIndex = ( emacTX_DESC_INDEX + 1 );
\r
516 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer. */
\r
517 uip_buf = prvGetNextBuffer();
\r
519 /*-----------------------------------------------------------*/
\r
521 static long prvWritePHY( long lPhyReg, long lValue )
\r
523 const long lMaxTime = 10;
\r
526 EMAC->MADR = KS8721_DEF_ADR | lPhyReg;
\r
527 EMAC->MWTD = lValue;
\r
530 for( x = 0; x < lMaxTime; x++ )
\r
532 if( ( EMAC->MIND & MIND_BUSY ) == 0 )
\r
534 /* Operation has finished. */
\r
538 vTaskDelay( emacSHORT_DELAY );
\r
550 /*-----------------------------------------------------------*/
\r
552 static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus )
\r
555 const long lMaxTime = 10;
\r
557 EMAC->MADR = KS8721_DEF_ADR | ucPhyReg;
\r
558 EMAC->MCMD = MCMD_READ;
\r
560 for( x = 0; x < lMaxTime; x++ )
\r
562 /* Operation has finished. */
\r
563 if( ( EMAC->MIND & MIND_BUSY ) == 0 )
\r
568 vTaskDelay( emacSHORT_DELAY );
\r
573 if( x >= lMaxTime )
\r
575 *plStatus = pdFAIL;
\r
578 return( EMAC->MRDD );
\r
580 /*-----------------------------------------------------------*/
\r
582 void vEMAC_ISR( void )
\r
584 unsigned long ulStatus;
\r
585 long lHigherPriorityTaskWoken = pdFALSE;
\r
587 ulStatus = EMAC->IntStatus;
\r
589 /* Clear the interrupt. */
\r
590 EMAC->IntClear = ulStatus;
\r
592 if( ulStatus & INT_RX_DONE )
\r
594 /* Ensure the uIP task is not blocked as data has arrived. */
\r
595 xSemaphoreGiveFromISR( xEMACSemaphore, &lHigherPriorityTaskWoken );
\r
598 if( ulStatus & INT_TX_DONE )
\r
600 if( usSendLen > 0 )
\r
602 /* Send the data again, using the second descriptor. As there are
\r
603 only two descriptors the index is set back to 0. */
\r
604 TX_DESC_PACKET( ( emacTX_DESC_INDEX + 1 ) ) = TX_DESC_PACKET( emacTX_DESC_INDEX );
\r
605 TX_DESC_CTRL( ( emacTX_DESC_INDEX + 1 ) ) = ( usSendLen | TCTRL_LAST | TCTRL_INT );
\r
606 EMAC->TxProduceIndex = ( emacTX_DESC_INDEX );
\r
608 /* This is the second Tx so set usSendLen to 0 to indicate that the
\r
609 Tx descriptors will be free again. */
\r
614 /* The Tx buffer is no longer required. */
\r
615 prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );
\r
616 TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) NULL;
\r
620 portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );
\r