4 * \brief Instance description for GCLK
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6 * Copyright (c) 2013 Atmel Corporation. All rights reserved.
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12 * Redistribution and use in source and binary forms, with or without
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13 * modification, are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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18 * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 * this list of conditions and the following disclaimer in the documentation
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20 * and/or other materials provided with the distribution.
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22 * 3. The name of Atmel may not be used to endorse or promote products derived
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23 * from this software without specific prior written permission.
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25 * 4. This software may only be redistributed and used in connection with an
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26 * Atmel microcontroller product.
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28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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38 * POSSIBILITY OF SUCH DAMAGE.
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44 #ifndef _SAMD20_GCLK_INSTANCE_
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45 #define _SAMD20_GCLK_INSTANCE_
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47 /* ========== Register definition for GCLK peripheral ========== */
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48 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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49 #define REG_GCLK_CTRL (0x40000C00U) /**< \brief (GCLK) Control Register */
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50 #define REG_GCLK_STATUS (0x40000C01U) /**< \brief (GCLK) Status Register */
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51 #define REG_GCLK_CLKCTRL (0x40000C02U) /**< \brief (GCLK) Generic Clock Control Register */
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52 #define REG_GCLK_GENCTRL (0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control Register */
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53 #define REG_GCLK_GENDIV (0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division Register */
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55 #define REG_GCLK_CTRL (*(RwReg8 *)0x40000C00U) /**< \brief (GCLK) Control Register */
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56 #define REG_GCLK_STATUS (*(RoReg8 *)0x40000C01U) /**< \brief (GCLK) Status Register */
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57 #define REG_GCLK_CLKCTRL (*(RwReg16*)0x40000C02U) /**< \brief (GCLK) Generic Clock Control Register */
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58 #define REG_GCLK_GENCTRL (*(RwReg *)0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control Register */
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59 #define REG_GCLK_GENDIV (*(RwReg *)0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division Register */
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60 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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62 /* ========== Instance parameters for GCLK peripheral ========== */
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63 #define GCLK_GEN_NUM_MSB 7
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64 #define GCLK_GEN_SOURCE_NUM_MSB 7
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65 #define GCLK_MAX_DIV_BITS 16
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67 #define GCLK_SOURCE_DFLL48M 7
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68 #define GCLK_SOURCE_GCLKGEN1 2
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69 #define GCLK_SOURCE_GCLKIN 1
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70 #define GCLK_SOURCE_OSCULP32K 3
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71 #define GCLK_SOURCE_OSC8M 6
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72 #define GCLK_SOURCE_OSC32K 4
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73 #define GCLK_SOURCE_XOSC 0
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74 #define GCLK_SOURCE_XOSC32K 5
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76 #endif /* _SAMD20_GCLK_INSTANCE_ */
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