4 * \brief Instance description for SYSCTRL
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6 * Copyright (c) 2013 Atmel Corporation. All rights reserved.
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12 * Redistribution and use in source and binary forms, with or without
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13 * modification, are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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18 * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 * this list of conditions and the following disclaimer in the documentation
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20 * and/or other materials provided with the distribution.
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22 * 3. The name of Atmel may not be used to endorse or promote products derived
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23 * from this software without specific prior written permission.
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25 * 4. This software may only be redistributed and used in connection with an
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26 * Atmel microcontroller product.
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28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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38 * POSSIBILITY OF SUCH DAMAGE.
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44 #ifndef _SAMD20_SYSCTRL_INSTANCE_
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45 #define _SAMD20_SYSCTRL_INSTANCE_
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47 /* ========== Register definition for SYSCTRL peripheral ========== */
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48 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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49 #define REG_SYSCTRL_INTENCLR (0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear Register */
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50 #define REG_SYSCTRL_INTENSET (0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set Register */
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51 #define REG_SYSCTRL_INTFLAG (0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear Register */
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52 #define REG_SYSCTRL_PCLKSR (0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status Register */
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53 #define REG_SYSCTRL_XOSC (0x40000810U) /**< \brief (SYSCTRL) XOSC Control Register */
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54 #define REG_SYSCTRL_XOSC32K (0x40000814U) /**< \brief (SYSCTRL) XOSC32K Control Register */
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55 #define REG_SYSCTRL_OSC32K (0x40000818U) /**< \brief (SYSCTRL) OSC32K Control Register */
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56 #define REG_SYSCTRL_OSCULP32K (0x4000081CU) /**< \brief (SYSCTRL) OSCULP32K Control Register */
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57 #define REG_SYSCTRL_OSC8M (0x40000820U) /**< \brief (SYSCTRL) OSC8M Control Register A */
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58 #define REG_SYSCTRL_DFLLCTRL (0x40000824U) /**< \brief (SYSCTRL) DFLL Config Register */
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59 #define REG_SYSCTRL_DFLLVAL (0x40000828U) /**< \brief (SYSCTRL) DFLL Calibration Value Register */
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60 #define REG_SYSCTRL_DFLLMUL (0x4000082CU) /**< \brief (SYSCTRL) DFLL Multiplier Register */
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61 #define REG_SYSCTRL_DFLLSYNC (0x40000830U) /**< \brief (SYSCTRL) DFLL Synchronization Register */
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62 #define REG_SYSCTRL_BOD33 (0x40000834U) /**< \brief (SYSCTRL) BOD33 Control Register */
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63 #define REG_SYSCTRL_BOD12 (0x40000838U) /**< \brief (SYSCTRL) BOD12 Control Register */
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64 #define REG_SYSCTRL_VREG (0x4000083CU) /**< \brief (SYSCTRL) VREG Control Register */
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65 #define REG_SYSCTRL_VREF (0x40000840U) /**< \brief (SYSCTRL) VREF Control Register A */
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67 #define REG_SYSCTRL_INTENCLR (*(RwReg *)0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear Register */
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68 #define REG_SYSCTRL_INTENSET (*(RwReg *)0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set Register */
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69 #define REG_SYSCTRL_INTFLAG (*(RwReg *)0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear Register */
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70 #define REG_SYSCTRL_PCLKSR (*(RoReg *)0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status Register */
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71 #define REG_SYSCTRL_XOSC (*(RwReg16*)0x40000810U) /**< \brief (SYSCTRL) XOSC Control Register */
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72 #define REG_SYSCTRL_XOSC32K (*(RwReg16*)0x40000814U) /**< \brief (SYSCTRL) XOSC32K Control Register */
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73 #define REG_SYSCTRL_OSC32K (*(RwReg *)0x40000818U) /**< \brief (SYSCTRL) OSC32K Control Register */
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74 #define REG_SYSCTRL_OSCULP32K (*(RwReg8 *)0x4000081CU) /**< \brief (SYSCTRL) OSCULP32K Control Register */
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75 #define REG_SYSCTRL_OSC8M (*(RwReg *)0x40000820U) /**< \brief (SYSCTRL) OSC8M Control Register A */
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76 #define REG_SYSCTRL_DFLLCTRL (*(RwReg16*)0x40000824U) /**< \brief (SYSCTRL) DFLL Config Register */
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77 #define REG_SYSCTRL_DFLLVAL (*(RwReg *)0x40000828U) /**< \brief (SYSCTRL) DFLL Calibration Value Register */
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78 #define REG_SYSCTRL_DFLLMUL (*(RwReg *)0x4000082CU) /**< \brief (SYSCTRL) DFLL Multiplier Register */
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79 #define REG_SYSCTRL_DFLLSYNC (*(RwReg8 *)0x40000830U) /**< \brief (SYSCTRL) DFLL Synchronization Register */
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80 #define REG_SYSCTRL_BOD33 (*(RwReg *)0x40000834U) /**< \brief (SYSCTRL) BOD33 Control Register */
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81 #define REG_SYSCTRL_BOD12 (*(RwReg *)0x40000838U) /**< \brief (SYSCTRL) BOD12 Control Register */
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82 #define REG_SYSCTRL_VREG (*(RwReg16*)0x4000083CU) /**< \brief (SYSCTRL) VREG Control Register */
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83 #define REG_SYSCTRL_VREF (*(RwReg *)0x40000840U) /**< \brief (SYSCTRL) VREF Control Register A */
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84 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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86 /* ========== Instance parameters for SYSCTRL peripheral ========== */
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87 #define SYSCTRL_BGAP_CALIB_MSB 11
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88 #define SYSCTRL_BOD12_CALIB_MSB 4
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89 #define SYSCTRL_BOD33_CALIB_MSB 5
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90 #define SYSCTRL_DFLL48M_COARSE_MSB 4
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91 #define SYSCTRL_DFLL48M_FINE_MSB 7
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92 #define SYSCTRL_DFLL48M_TESTEN_MSB 1
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93 #define SYSCTRL_GCLK_ID_DFLL48 0
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94 #define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6
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95 #define SYSCTRL_POR33_ENTEST_MSB 1
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96 #define SYSCTRL_ULPVREF_DIVLEV_MSB 3
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97 #define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1
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98 #define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2
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99 #define SYSCTRL_VREF_CONTROL_MSB 48
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100 #define SYSCTRL_VREF_STATUS_MSB 7
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101 #define SYSCTRL_VREG_LEVEL_MSB 2
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102 #define SYSCTRL_BOD12_VERSION 0x110
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103 #define SYSCTRL_BOD33_VERSION 0x110
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104 #define SYSCTRL_DFLL48M_VERSION 0x200
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105 #define SYSCTRL_GCLK_VERSION 0x200
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106 #define SYSCTRL_OSCULP32K_VERSION 0x110
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107 #define SYSCTRL_OSC8M_VERSION 0x110
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108 #define SYSCTRL_OSC32K_VERSION 0x110
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109 #define SYSCTRL_VREF_VERSION 0x200
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110 #define SYSCTRL_VREG_VERSION 0x200
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111 #define SYSCTRL_XOSC_VERSION 0x110
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112 #define SYSCTRL_XOSC32K_VERSION 0x110
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114 #endif /* _SAMD20_SYSCTRL_INSTANCE_ */
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