4 * \brief Peripheral I/O description for SAMD20G16
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6 * Copyright (c) 2013 Atmel Corporation. All rights reserved.
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12 * Redistribution and use in source and binary forms, with or without
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13 * modification, are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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18 * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 * this list of conditions and the following disclaimer in the documentation
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20 * and/or other materials provided with the distribution.
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22 * 3. The name of Atmel may not be used to endorse or promote products derived
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23 * from this software without specific prior written permission.
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25 * 4. This software may only be redistributed and used in connection with an
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26 * Atmel microcontroller product.
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28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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38 * POSSIBILITY OF SUCH DAMAGE.
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44 #ifndef _SAMD20G16_PIO_
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45 #define _SAMD20G16_PIO_
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47 #define PIN_PA00 0 /**< \brief Pin Number for PA00 */
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48 #define PORT_PA00 (1u << 0) /**< \brief PORT Mask for PA00 */
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49 #define PIN_PA01 1 /**< \brief Pin Number for PA01 */
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50 #define PORT_PA01 (1u << 1) /**< \brief PORT Mask for PA01 */
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51 #define PIN_PA02 2 /**< \brief Pin Number for PA02 */
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52 #define PORT_PA02 (1u << 2) /**< \brief PORT Mask for PA02 */
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53 #define PIN_PA03 3 /**< \brief Pin Number for PA03 */
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54 #define PORT_PA03 (1u << 3) /**< \brief PORT Mask for PA03 */
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55 #define PIN_PA04 4 /**< \brief Pin Number for PA04 */
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56 #define PORT_PA04 (1u << 4) /**< \brief PORT Mask for PA04 */
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57 #define PIN_PA05 5 /**< \brief Pin Number for PA05 */
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58 #define PORT_PA05 (1u << 5) /**< \brief PORT Mask for PA05 */
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59 #define PIN_PA06 6 /**< \brief Pin Number for PA06 */
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60 #define PORT_PA06 (1u << 6) /**< \brief PORT Mask for PA06 */
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61 #define PIN_PA07 7 /**< \brief Pin Number for PA07 */
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62 #define PORT_PA07 (1u << 7) /**< \brief PORT Mask for PA07 */
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63 #define PIN_PA08 8 /**< \brief Pin Number for PA08 */
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64 #define PORT_PA08 (1u << 8) /**< \brief PORT Mask for PA08 */
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65 #define PIN_PA09 9 /**< \brief Pin Number for PA09 */
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66 #define PORT_PA09 (1u << 9) /**< \brief PORT Mask for PA09 */
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67 #define PIN_PA10 10 /**< \brief Pin Number for PA10 */
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68 #define PORT_PA10 (1u << 10) /**< \brief PORT Mask for PA10 */
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69 #define PIN_PA11 11 /**< \brief Pin Number for PA11 */
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70 #define PORT_PA11 (1u << 11) /**< \brief PORT Mask for PA11 */
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71 #define PIN_PA12 12 /**< \brief Pin Number for PA12 */
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72 #define PORT_PA12 (1u << 12) /**< \brief PORT Mask for PA12 */
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73 #define PIN_PA13 13 /**< \brief Pin Number for PA13 */
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74 #define PORT_PA13 (1u << 13) /**< \brief PORT Mask for PA13 */
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75 #define PIN_PA14 14 /**< \brief Pin Number for PA14 */
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76 #define PORT_PA14 (1u << 14) /**< \brief PORT Mask for PA14 */
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77 #define PIN_PA15 15 /**< \brief Pin Number for PA15 */
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78 #define PORT_PA15 (1u << 15) /**< \brief PORT Mask for PA15 */
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79 #define PIN_PA16 16 /**< \brief Pin Number for PA16 */
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80 #define PORT_PA16 (1u << 16) /**< \brief PORT Mask for PA16 */
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81 #define PIN_PA17 17 /**< \brief Pin Number for PA17 */
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82 #define PORT_PA17 (1u << 17) /**< \brief PORT Mask for PA17 */
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83 #define PIN_PA18 18 /**< \brief Pin Number for PA18 */
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84 #define PORT_PA18 (1u << 18) /**< \brief PORT Mask for PA18 */
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85 #define PIN_PA19 19 /**< \brief Pin Number for PA19 */
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86 #define PORT_PA19 (1u << 19) /**< \brief PORT Mask for PA19 */
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87 #define PIN_PA20 20 /**< \brief Pin Number for PA20 */
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88 #define PORT_PA20 (1u << 20) /**< \brief PORT Mask for PA20 */
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89 #define PIN_PA21 21 /**< \brief Pin Number for PA21 */
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90 #define PORT_PA21 (1u << 21) /**< \brief PORT Mask for PA21 */
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91 #define PIN_PA22 22 /**< \brief Pin Number for PA22 */
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92 #define PORT_PA22 (1u << 22) /**< \brief PORT Mask for PA22 */
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93 #define PIN_PA23 23 /**< \brief Pin Number for PA23 */
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94 #define PORT_PA23 (1u << 23) /**< \brief PORT Mask for PA23 */
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95 #define PIN_PA24 24 /**< \brief Pin Number for PA24 */
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96 #define PORT_PA24 (1u << 24) /**< \brief PORT Mask for PA24 */
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97 #define PIN_PA25 25 /**< \brief Pin Number for PA25 */
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98 #define PORT_PA25 (1u << 25) /**< \brief PORT Mask for PA25 */
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99 #define PIN_PA27 27 /**< \brief Pin Number for PA27 */
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100 #define PORT_PA27 (1u << 27) /**< \brief PORT Mask for PA27 */
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101 #define PIN_PA28 28 /**< \brief Pin Number for PA28 */
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102 #define PORT_PA28 (1u << 28) /**< \brief PORT Mask for PA28 */
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103 #define PIN_PA30 30 /**< \brief Pin Number for PA30 */
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104 #define PORT_PA30 (1u << 30) /**< \brief PORT Mask for PA30 */
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105 #define PIN_PA31 31 /**< \brief Pin Number for PA31 */
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106 #define PORT_PA31 (1u << 31) /**< \brief PORT Mask for PA31 */
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107 #define PIN_PB02 34 /**< \brief Pin Number for PB02 */
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108 #define PORT_PB02 (1u << 2) /**< \brief PORT Mask for PB02 */
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109 #define PIN_PB03 35 /**< \brief Pin Number for PB03 */
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110 #define PORT_PB03 (1u << 3) /**< \brief PORT Mask for PB03 */
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111 #define PIN_PB08 40 /**< \brief Pin Number for PB08 */
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112 #define PORT_PB08 (1u << 8) /**< \brief PORT Mask for PB08 */
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113 #define PIN_PB09 41 /**< \brief Pin Number for PB09 */
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114 #define PORT_PB09 (1u << 9) /**< \brief PORT Mask for PB09 */
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115 #define PIN_PB10 42 /**< \brief Pin Number for PB10 */
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116 #define PORT_PB10 (1u << 10) /**< \brief PORT Mask for PB10 */
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117 #define PIN_PB11 43 /**< \brief Pin Number for PB11 */
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118 #define PORT_PB11 (1u << 11) /**< \brief PORT Mask for PB11 */
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119 #define PIN_PB22 54 /**< \brief Pin Number for PB22 */
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120 #define PORT_PB22 (1u << 22) /**< \brief PORT Mask for PB22 */
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121 #define PIN_PB23 55 /**< \brief Pin Number for PB23 */
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122 #define PORT_PB23 (1u << 23) /**< \brief PORT Mask for PB23 */
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123 /* ========== PORT definition for CORE peripheral ========== */
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124 #define PIN_PA30G_CORE_SWCLK 30 /**< \brief CORE signal: SWCLK on PA30 mux G */
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125 #define MUX_PA30G_CORE_SWCLK 6
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126 #define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)
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127 #define PORT_PA30G_CORE_SWCLK (1u << 30)
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128 /* ========== PORT definition for GCLK peripheral ========== */
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129 #define PIN_PB22H_GCLK_IO0 54 /**< \brief GCLK signal: IO0 on PB22 mux H */
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130 #define MUX_PB22H_GCLK_IO0 7
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131 #define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
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132 #define PORT_PB22H_GCLK_IO0 (1u << 22)
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133 #define PIN_PA14H_GCLK_IO0 14 /**< \brief GCLK signal: IO0 on PA14 mux H */
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134 #define MUX_PA14H_GCLK_IO0 7
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135 #define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
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136 #define PORT_PA14H_GCLK_IO0 (1u << 14)
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137 #define PIN_PA27H_GCLK_IO0 27 /**< \brief GCLK signal: IO0 on PA27 mux H */
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138 #define MUX_PA27H_GCLK_IO0 7
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139 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
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140 #define PORT_PA27H_GCLK_IO0 (1u << 27)
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141 #define PIN_PA28H_GCLK_IO0 28 /**< \brief GCLK signal: IO0 on PA28 mux H */
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142 #define MUX_PA28H_GCLK_IO0 7
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143 #define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
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144 #define PORT_PA28H_GCLK_IO0 (1u << 28)
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145 #define PIN_PA30H_GCLK_IO0 30 /**< \brief GCLK signal: IO0 on PA30 mux H */
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146 #define MUX_PA30H_GCLK_IO0 7
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147 #define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
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148 #define PORT_PA30H_GCLK_IO0 (1u << 30)
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149 #define PIN_PB23H_GCLK_IO1 55 /**< \brief GCLK signal: IO1 on PB23 mux H */
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150 #define MUX_PB23H_GCLK_IO1 7
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151 #define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
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152 #define PORT_PB23H_GCLK_IO1 (1u << 23)
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153 #define PIN_PA15H_GCLK_IO1 15 /**< \brief GCLK signal: IO1 on PA15 mux H */
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154 #define MUX_PA15H_GCLK_IO1 7
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155 #define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
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156 #define PORT_PA15H_GCLK_IO1 (1u << 15)
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157 #define PIN_PA16H_GCLK_IO2 16 /**< \brief GCLK signal: IO2 on PA16 mux H */
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158 #define MUX_PA16H_GCLK_IO2 7
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159 #define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
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160 #define PORT_PA16H_GCLK_IO2 (1u << 16)
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161 #define PIN_PA17H_GCLK_IO3 17 /**< \brief GCLK signal: IO3 on PA17 mux H */
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162 #define MUX_PA17H_GCLK_IO3 7
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163 #define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
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164 #define PORT_PA17H_GCLK_IO3 (1u << 17)
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165 #define PIN_PA10H_GCLK_IO4 10 /**< \brief GCLK signal: IO4 on PA10 mux H */
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166 #define MUX_PA10H_GCLK_IO4 7
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167 #define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
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168 #define PORT_PA10H_GCLK_IO4 (1u << 10)
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169 #define PIN_PA20H_GCLK_IO4 20 /**< \brief GCLK signal: IO4 on PA20 mux H */
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170 #define MUX_PA20H_GCLK_IO4 7
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171 #define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
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172 #define PORT_PA20H_GCLK_IO4 (1u << 20)
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173 #define PIN_PB10H_GCLK_IO4 42 /**< \brief GCLK signal: IO4 on PB10 mux H */
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174 #define MUX_PB10H_GCLK_IO4 7
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175 #define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
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176 #define PORT_PB10H_GCLK_IO4 (1u << 10)
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177 #define PIN_PA11H_GCLK_IO5 11 /**< \brief GCLK signal: IO5 on PA11 mux H */
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178 #define MUX_PA11H_GCLK_IO5 7
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179 #define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
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180 #define PORT_PA11H_GCLK_IO5 (1u << 11)
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181 #define PIN_PA21H_GCLK_IO5 21 /**< \brief GCLK signal: IO5 on PA21 mux H */
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182 #define MUX_PA21H_GCLK_IO5 7
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183 #define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
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184 #define PORT_PA21H_GCLK_IO5 (1u << 21)
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185 #define PIN_PB11H_GCLK_IO5 43 /**< \brief GCLK signal: IO5 on PB11 mux H */
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186 #define MUX_PB11H_GCLK_IO5 7
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187 #define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
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188 #define PORT_PB11H_GCLK_IO5 (1u << 11)
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189 #define PIN_PA22H_GCLK_IO6 22 /**< \brief GCLK signal: IO6 on PA22 mux H */
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190 #define MUX_PA22H_GCLK_IO6 7
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191 #define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
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192 #define PORT_PA22H_GCLK_IO6 (1u << 22)
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193 #define PIN_PA23H_GCLK_IO7 23 /**< \brief GCLK signal: IO7 on PA23 mux H */
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194 #define MUX_PA23H_GCLK_IO7 7
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195 #define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
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196 #define PORT_PA23H_GCLK_IO7 (1u << 23)
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197 /* ========== PORT definition for EIC peripheral ========== */
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198 #define PIN_PA16A_EIC_EXTINT0 16 /**< \brief EIC signal: EXTINT0 on PA16 mux A */
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199 #define MUX_PA16A_EIC_EXTINT0 0
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200 #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
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201 #define PORT_PA16A_EIC_EXTINT0 (1u << 16)
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202 #define PIN_PA00A_EIC_EXTINT0 0 /**< \brief EIC signal: EXTINT0 on PA00 mux A */
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203 #define MUX_PA00A_EIC_EXTINT0 0
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204 #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
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205 #define PORT_PA00A_EIC_EXTINT0 (1u << 0)
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206 #define PIN_PA17A_EIC_EXTINT1 17 /**< \brief EIC signal: EXTINT1 on PA17 mux A */
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207 #define MUX_PA17A_EIC_EXTINT1 0
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208 #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
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209 #define PORT_PA17A_EIC_EXTINT1 (1u << 17)
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210 #define PIN_PA01A_EIC_EXTINT1 1 /**< \brief EIC signal: EXTINT1 on PA01 mux A */
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211 #define MUX_PA01A_EIC_EXTINT1 0
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212 #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
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213 #define PORT_PA01A_EIC_EXTINT1 (1u << 1)
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214 #define PIN_PA02A_EIC_EXTINT2 2 /**< \brief EIC signal: EXTINT2 on PA02 mux A */
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215 #define MUX_PA02A_EIC_EXTINT2 0
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216 #define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
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217 #define PORT_PA02A_EIC_EXTINT2 (1u << 2)
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218 #define PIN_PA18A_EIC_EXTINT2 18 /**< \brief EIC signal: EXTINT2 on PA18 mux A */
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219 #define MUX_PA18A_EIC_EXTINT2 0
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220 #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
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221 #define PORT_PA18A_EIC_EXTINT2 (1u << 18)
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222 #define PIN_PB02A_EIC_EXTINT2 34 /**< \brief EIC signal: EXTINT2 on PB02 mux A */
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223 #define MUX_PB02A_EIC_EXTINT2 0
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224 #define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
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225 #define PORT_PB02A_EIC_EXTINT2 (1u << 2)
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226 #define PIN_PA03A_EIC_EXTINT3 3 /**< \brief EIC signal: EXTINT3 on PA03 mux A */
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227 #define MUX_PA03A_EIC_EXTINT3 0
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228 #define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
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229 #define PORT_PA03A_EIC_EXTINT3 (1u << 3)
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230 #define PIN_PA19A_EIC_EXTINT3 19 /**< \brief EIC signal: EXTINT3 on PA19 mux A */
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231 #define MUX_PA19A_EIC_EXTINT3 0
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232 #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
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233 #define PORT_PA19A_EIC_EXTINT3 (1u << 19)
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234 #define PIN_PB03A_EIC_EXTINT3 35 /**< \brief EIC signal: EXTINT3 on PB03 mux A */
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235 #define MUX_PB03A_EIC_EXTINT3 0
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236 #define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
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237 #define PORT_PB03A_EIC_EXTINT3 (1u << 3)
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238 #define PIN_PA04A_EIC_EXTINT4 4 /**< \brief EIC signal: EXTINT4 on PA04 mux A */
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239 #define MUX_PA04A_EIC_EXTINT4 0
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240 #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
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241 #define PORT_PA04A_EIC_EXTINT4 (1u << 4)
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242 #define PIN_PA20A_EIC_EXTINT4 20 /**< \brief EIC signal: EXTINT4 on PA20 mux A */
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243 #define MUX_PA20A_EIC_EXTINT4 0
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244 #define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
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245 #define PORT_PA20A_EIC_EXTINT4 (1u << 20)
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246 #define PIN_PA05A_EIC_EXTINT5 5 /**< \brief EIC signal: EXTINT5 on PA05 mux A */
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247 #define MUX_PA05A_EIC_EXTINT5 0
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248 #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
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249 #define PORT_PA05A_EIC_EXTINT5 (1u << 5)
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250 #define PIN_PA21A_EIC_EXTINT5 21 /**< \brief EIC signal: EXTINT5 on PA21 mux A */
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251 #define MUX_PA21A_EIC_EXTINT5 0
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252 #define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
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253 #define PORT_PA21A_EIC_EXTINT5 (1u << 21)
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254 #define PIN_PA06A_EIC_EXTINT6 6 /**< \brief EIC signal: EXTINT6 on PA06 mux A */
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255 #define MUX_PA06A_EIC_EXTINT6 0
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256 #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
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257 #define PORT_PA06A_EIC_EXTINT6 (1u << 6)
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258 #define PIN_PA22A_EIC_EXTINT6 22 /**< \brief EIC signal: EXTINT6 on PA22 mux A */
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259 #define MUX_PA22A_EIC_EXTINT6 0
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260 #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
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261 #define PORT_PA22A_EIC_EXTINT6 (1u << 22)
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262 #define PIN_PB22A_EIC_EXTINT6 54 /**< \brief EIC signal: EXTINT6 on PB22 mux A */
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263 #define MUX_PB22A_EIC_EXTINT6 0
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264 #define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
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265 #define PORT_PB22A_EIC_EXTINT6 (1u << 22)
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266 #define PIN_PA07A_EIC_EXTINT7 7 /**< \brief EIC signal: EXTINT7 on PA07 mux A */
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267 #define MUX_PA07A_EIC_EXTINT7 0
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268 #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
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269 #define PORT_PA07A_EIC_EXTINT7 (1u << 7)
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270 #define PIN_PA23A_EIC_EXTINT7 23 /**< \brief EIC signal: EXTINT7 on PA23 mux A */
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271 #define MUX_PA23A_EIC_EXTINT7 0
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272 #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
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273 #define PORT_PA23A_EIC_EXTINT7 (1u << 23)
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274 #define PIN_PB23A_EIC_EXTINT7 55 /**< \brief EIC signal: EXTINT7 on PB23 mux A */
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275 #define MUX_PB23A_EIC_EXTINT7 0
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276 #define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
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277 #define PORT_PB23A_EIC_EXTINT7 (1u << 23)
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278 #define PIN_PA28A_EIC_EXTINT8 28 /**< \brief EIC signal: EXTINT8 on PA28 mux A */
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279 #define MUX_PA28A_EIC_EXTINT8 0
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280 #define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
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281 #define PORT_PA28A_EIC_EXTINT8 (1u << 28)
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282 #define PIN_PB08A_EIC_EXTINT8 40 /**< \brief EIC signal: EXTINT8 on PB08 mux A */
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283 #define MUX_PB08A_EIC_EXTINT8 0
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284 #define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
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285 #define PORT_PB08A_EIC_EXTINT8 (1u << 8)
\r
286 #define PIN_PA09A_EIC_EXTINT9 9 /**< \brief EIC signal: EXTINT9 on PA09 mux A */
\r
287 #define MUX_PA09A_EIC_EXTINT9 0
\r
288 #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
\r
289 #define PORT_PA09A_EIC_EXTINT9 (1u << 9)
\r
290 #define PIN_PB09A_EIC_EXTINT9 41 /**< \brief EIC signal: EXTINT9 on PB09 mux A */
\r
291 #define MUX_PB09A_EIC_EXTINT9 0
\r
292 #define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
\r
293 #define PORT_PB09A_EIC_EXTINT9 (1u << 9)
\r
294 #define PIN_PA10A_EIC_EXTINT10 10 /**< \brief EIC signal: EXTINT10 on PA10 mux A */
\r
295 #define MUX_PA10A_EIC_EXTINT10 0
\r
296 #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
\r
297 #define PORT_PA10A_EIC_EXTINT10 (1u << 10)
\r
298 #define PIN_PA30A_EIC_EXTINT10 30 /**< \brief EIC signal: EXTINT10 on PA30 mux A */
\r
299 #define MUX_PA30A_EIC_EXTINT10 0
\r
300 #define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
\r
301 #define PORT_PA30A_EIC_EXTINT10 (1u << 30)
\r
302 #define PIN_PB10A_EIC_EXTINT10 42 /**< \brief EIC signal: EXTINT10 on PB10 mux A */
\r
303 #define MUX_PB10A_EIC_EXTINT10 0
\r
304 #define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
\r
305 #define PORT_PB10A_EIC_EXTINT10 (1u << 10)
\r
306 #define PIN_PA11A_EIC_EXTINT11 11 /**< \brief EIC signal: EXTINT11 on PA11 mux A */
\r
307 #define MUX_PA11A_EIC_EXTINT11 0
\r
308 #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
\r
309 #define PORT_PA11A_EIC_EXTINT11 (1u << 11)
\r
310 #define PIN_PA31A_EIC_EXTINT11 31 /**< \brief EIC signal: EXTINT11 on PA31 mux A */
\r
311 #define MUX_PA31A_EIC_EXTINT11 0
\r
312 #define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
\r
313 #define PORT_PA31A_EIC_EXTINT11 (1u << 31)
\r
314 #define PIN_PB11A_EIC_EXTINT11 43 /**< \brief EIC signal: EXTINT11 on PB11 mux A */
\r
315 #define MUX_PB11A_EIC_EXTINT11 0
\r
316 #define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
\r
317 #define PORT_PB11A_EIC_EXTINT11 (1u << 11)
\r
318 #define PIN_PA12A_EIC_EXTINT12 12 /**< \brief EIC signal: EXTINT12 on PA12 mux A */
\r
319 #define MUX_PA12A_EIC_EXTINT12 0
\r
320 #define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
\r
321 #define PORT_PA12A_EIC_EXTINT12 (1u << 12)
\r
322 #define PIN_PA24A_EIC_EXTINT12 24 /**< \brief EIC signal: EXTINT12 on PA24 mux A */
\r
323 #define MUX_PA24A_EIC_EXTINT12 0
\r
324 #define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
\r
325 #define PORT_PA24A_EIC_EXTINT12 (1u << 24)
\r
326 #define PIN_PA13A_EIC_EXTINT13 13 /**< \brief EIC signal: EXTINT13 on PA13 mux A */
\r
327 #define MUX_PA13A_EIC_EXTINT13 0
\r
328 #define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
\r
329 #define PORT_PA13A_EIC_EXTINT13 (1u << 13)
\r
330 #define PIN_PA25A_EIC_EXTINT13 25 /**< \brief EIC signal: EXTINT13 on PA25 mux A */
\r
331 #define MUX_PA25A_EIC_EXTINT13 0
\r
332 #define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
\r
333 #define PORT_PA25A_EIC_EXTINT13 (1u << 25)
\r
334 #define PIN_PA14A_EIC_EXTINT14 14 /**< \brief EIC signal: EXTINT14 on PA14 mux A */
\r
335 #define MUX_PA14A_EIC_EXTINT14 0
\r
336 #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
\r
337 #define PORT_PA14A_EIC_EXTINT14 (1u << 14)
\r
338 #define PIN_PA27A_EIC_EXTINT15 27 /**< \brief EIC signal: EXTINT15 on PA27 mux A */
\r
339 #define MUX_PA27A_EIC_EXTINT15 0
\r
340 #define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
\r
341 #define PORT_PA27A_EIC_EXTINT15 (1u << 27)
\r
342 #define PIN_PA15A_EIC_EXTINT15 15 /**< \brief EIC signal: EXTINT15 on PA15 mux A */
\r
343 #define MUX_PA15A_EIC_EXTINT15 0
\r
344 #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
\r
345 #define PORT_PA15A_EIC_EXTINT15 (1u << 15)
\r
346 #define PIN_PA08A_EIC_NMI 8 /**< \brief EIC signal: NMI on PA08 mux A */
\r
347 #define MUX_PA08A_EIC_NMI 0
\r
348 #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
\r
349 #define PORT_PA08A_EIC_NMI (1u << 8)
\r
350 /* ========== PORT definition for SERCOM0 peripheral ========== */
\r
351 #define PIN_PA04D_SERCOM0_PAD0 4 /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
\r
352 #define MUX_PA04D_SERCOM0_PAD0 3
\r
353 #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
\r
354 #define PORT_PA04D_SERCOM0_PAD0 (1u << 4)
\r
355 #define PIN_PA08C_SERCOM0_PAD0 8 /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
\r
356 #define MUX_PA08C_SERCOM0_PAD0 2
\r
357 #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
\r
358 #define PORT_PA08C_SERCOM0_PAD0 (1u << 8)
\r
359 #define PIN_PA05D_SERCOM0_PAD1 5 /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
\r
360 #define MUX_PA05D_SERCOM0_PAD1 3
\r
361 #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
\r
362 #define PORT_PA05D_SERCOM0_PAD1 (1u << 5)
\r
363 #define PIN_PA09C_SERCOM0_PAD1 9 /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
\r
364 #define MUX_PA09C_SERCOM0_PAD1 2
\r
365 #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
\r
366 #define PORT_PA09C_SERCOM0_PAD1 (1u << 9)
\r
367 #define PIN_PA06D_SERCOM0_PAD2 6 /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
\r
368 #define MUX_PA06D_SERCOM0_PAD2 3
\r
369 #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
\r
370 #define PORT_PA06D_SERCOM0_PAD2 (1u << 6)
\r
371 #define PIN_PA10C_SERCOM0_PAD2 10 /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
\r
372 #define MUX_PA10C_SERCOM0_PAD2 2
\r
373 #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
\r
374 #define PORT_PA10C_SERCOM0_PAD2 (1u << 10)
\r
375 #define PIN_PA07D_SERCOM0_PAD3 7 /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
\r
376 #define MUX_PA07D_SERCOM0_PAD3 3
\r
377 #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
\r
378 #define PORT_PA07D_SERCOM0_PAD3 (1u << 7)
\r
379 #define PIN_PA11C_SERCOM0_PAD3 11 /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
\r
380 #define MUX_PA11C_SERCOM0_PAD3 2
\r
381 #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
\r
382 #define PORT_PA11C_SERCOM0_PAD3 (1u << 11)
\r
383 /* ========== PORT definition for SERCOM1 peripheral ========== */
\r
384 #define PIN_PA16C_SERCOM1_PAD0 16 /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
\r
385 #define MUX_PA16C_SERCOM1_PAD0 2
\r
386 #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
\r
387 #define PORT_PA16C_SERCOM1_PAD0 (1u << 16)
\r
388 #define PIN_PA00D_SERCOM1_PAD0 0 /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
\r
389 #define MUX_PA00D_SERCOM1_PAD0 3
\r
390 #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
\r
391 #define PORT_PA00D_SERCOM1_PAD0 (1u << 0)
\r
392 #define PIN_PA17C_SERCOM1_PAD1 17 /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
\r
393 #define MUX_PA17C_SERCOM1_PAD1 2
\r
394 #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
\r
395 #define PORT_PA17C_SERCOM1_PAD1 (1u << 17)
\r
396 #define PIN_PA01D_SERCOM1_PAD1 1 /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
\r
397 #define MUX_PA01D_SERCOM1_PAD1 3
\r
398 #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
\r
399 #define PORT_PA01D_SERCOM1_PAD1 (1u << 1)
\r
400 #define PIN_PA30D_SERCOM1_PAD2 30 /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
\r
401 #define MUX_PA30D_SERCOM1_PAD2 3
\r
402 #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
\r
403 #define PORT_PA30D_SERCOM1_PAD2 (1u << 30)
\r
404 #define PIN_PA18C_SERCOM1_PAD2 18 /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
\r
405 #define MUX_PA18C_SERCOM1_PAD2 2
\r
406 #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
\r
407 #define PORT_PA18C_SERCOM1_PAD2 (1u << 18)
\r
408 #define PIN_PA31D_SERCOM1_PAD3 31 /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
\r
409 #define MUX_PA31D_SERCOM1_PAD3 3
\r
410 #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
\r
411 #define PORT_PA31D_SERCOM1_PAD3 (1u << 31)
\r
412 #define PIN_PA19C_SERCOM1_PAD3 19 /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
\r
413 #define MUX_PA19C_SERCOM1_PAD3 2
\r
414 #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
\r
415 #define PORT_PA19C_SERCOM1_PAD3 (1u << 19)
\r
416 /* ========== PORT definition for SERCOM2 peripheral ========== */
\r
417 #define PIN_PA08D_SERCOM2_PAD0 8 /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
\r
418 #define MUX_PA08D_SERCOM2_PAD0 3
\r
419 #define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
\r
420 #define PORT_PA08D_SERCOM2_PAD0 (1u << 8)
\r
421 #define PIN_PA12C_SERCOM2_PAD0 12 /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
\r
422 #define MUX_PA12C_SERCOM2_PAD0 2
\r
423 #define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
\r
424 #define PORT_PA12C_SERCOM2_PAD0 (1u << 12)
\r
425 #define PIN_PA09D_SERCOM2_PAD1 9 /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
\r
426 #define MUX_PA09D_SERCOM2_PAD1 3
\r
427 #define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
\r
428 #define PORT_PA09D_SERCOM2_PAD1 (1u << 9)
\r
429 #define PIN_PA13C_SERCOM2_PAD1 13 /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
\r
430 #define MUX_PA13C_SERCOM2_PAD1 2
\r
431 #define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
\r
432 #define PORT_PA13C_SERCOM2_PAD1 (1u << 13)
\r
433 #define PIN_PA10D_SERCOM2_PAD2 10 /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
\r
434 #define MUX_PA10D_SERCOM2_PAD2 3
\r
435 #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
\r
436 #define PORT_PA10D_SERCOM2_PAD2 (1u << 10)
\r
437 #define PIN_PA14C_SERCOM2_PAD2 14 /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
\r
438 #define MUX_PA14C_SERCOM2_PAD2 2
\r
439 #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
\r
440 #define PORT_PA14C_SERCOM2_PAD2 (1u << 14)
\r
441 #define PIN_PA11D_SERCOM2_PAD3 11 /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
\r
442 #define MUX_PA11D_SERCOM2_PAD3 3
\r
443 #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
\r
444 #define PORT_PA11D_SERCOM2_PAD3 (1u << 11)
\r
445 #define PIN_PA15C_SERCOM2_PAD3 15 /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
\r
446 #define MUX_PA15C_SERCOM2_PAD3 2
\r
447 #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
\r
448 #define PORT_PA15C_SERCOM2_PAD3 (1u << 15)
\r
449 /* ========== PORT definition for SERCOM3 peripheral ========== */
\r
450 #define PIN_PA16D_SERCOM3_PAD0 16 /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
\r
451 #define MUX_PA16D_SERCOM3_PAD0 3
\r
452 #define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
\r
453 #define PORT_PA16D_SERCOM3_PAD0 (1u << 16)
\r
454 #define PIN_PA22C_SERCOM3_PAD0 22 /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
\r
455 #define MUX_PA22C_SERCOM3_PAD0 2
\r
456 #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
\r
457 #define PORT_PA22C_SERCOM3_PAD0 (1u << 22)
\r
458 #define PIN_PA17D_SERCOM3_PAD1 17 /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
\r
459 #define MUX_PA17D_SERCOM3_PAD1 3
\r
460 #define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
\r
461 #define PORT_PA17D_SERCOM3_PAD1 (1u << 17)
\r
462 #define PIN_PA23C_SERCOM3_PAD1 23 /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
\r
463 #define MUX_PA23C_SERCOM3_PAD1 2
\r
464 #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
\r
465 #define PORT_PA23C_SERCOM3_PAD1 (1u << 23)
\r
466 #define PIN_PA18D_SERCOM3_PAD2 18 /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
\r
467 #define MUX_PA18D_SERCOM3_PAD2 3
\r
468 #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
\r
469 #define PORT_PA18D_SERCOM3_PAD2 (1u << 18)
\r
470 #define PIN_PA20D_SERCOM3_PAD2 20 /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
\r
471 #define MUX_PA20D_SERCOM3_PAD2 3
\r
472 #define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
\r
473 #define PORT_PA20D_SERCOM3_PAD2 (1u << 20)
\r
474 #define PIN_PA24C_SERCOM3_PAD2 24 /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
\r
475 #define MUX_PA24C_SERCOM3_PAD2 2
\r
476 #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
\r
477 #define PORT_PA24C_SERCOM3_PAD2 (1u << 24)
\r
478 #define PIN_PA19D_SERCOM3_PAD3 19 /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
\r
479 #define MUX_PA19D_SERCOM3_PAD3 3
\r
480 #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
\r
481 #define PORT_PA19D_SERCOM3_PAD3 (1u << 19)
\r
482 #define PIN_PA21D_SERCOM3_PAD3 21 /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
\r
483 #define MUX_PA21D_SERCOM3_PAD3 3
\r
484 #define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
\r
485 #define PORT_PA21D_SERCOM3_PAD3 (1u << 21)
\r
486 #define PIN_PA25C_SERCOM3_PAD3 25 /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
\r
487 #define MUX_PA25C_SERCOM3_PAD3 2
\r
488 #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
\r
489 #define PORT_PA25C_SERCOM3_PAD3 (1u << 25)
\r
490 /* ========== PORT definition for SERCOM4 peripheral ========== */
\r
491 #define PIN_PA12D_SERCOM4_PAD0 12 /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
\r
492 #define MUX_PA12D_SERCOM4_PAD0 3
\r
493 #define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
\r
494 #define PORT_PA12D_SERCOM4_PAD0 (1u << 12)
\r
495 #define PIN_PB08D_SERCOM4_PAD0 40 /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
\r
496 #define MUX_PB08D_SERCOM4_PAD0 3
\r
497 #define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
\r
498 #define PORT_PB08D_SERCOM4_PAD0 (1u << 8)
\r
499 #define PIN_PA13D_SERCOM4_PAD1 13 /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
\r
500 #define MUX_PA13D_SERCOM4_PAD1 3
\r
501 #define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
\r
502 #define PORT_PA13D_SERCOM4_PAD1 (1u << 13)
\r
503 #define PIN_PB09D_SERCOM4_PAD1 41 /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
\r
504 #define MUX_PB09D_SERCOM4_PAD1 3
\r
505 #define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
\r
506 #define PORT_PB09D_SERCOM4_PAD1 (1u << 9)
\r
507 #define PIN_PA14D_SERCOM4_PAD2 14 /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
\r
508 #define MUX_PA14D_SERCOM4_PAD2 3
\r
509 #define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
\r
510 #define PORT_PA14D_SERCOM4_PAD2 (1u << 14)
\r
511 #define PIN_PB10D_SERCOM4_PAD2 42 /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
\r
512 #define MUX_PB10D_SERCOM4_PAD2 3
\r
513 #define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
\r
514 #define PORT_PB10D_SERCOM4_PAD2 (1u << 10)
\r
515 #define PIN_PA15D_SERCOM4_PAD3 15 /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
\r
516 #define MUX_PA15D_SERCOM4_PAD3 3
\r
517 #define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
\r
518 #define PORT_PA15D_SERCOM4_PAD3 (1u << 15)
\r
519 #define PIN_PB11D_SERCOM4_PAD3 43 /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
\r
520 #define MUX_PB11D_SERCOM4_PAD3 3
\r
521 #define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
\r
522 #define PORT_PB11D_SERCOM4_PAD3 (1u << 11)
\r
523 /* ========== PORT definition for SERCOM5 peripheral ========== */
\r
524 #define PIN_PA22D_SERCOM5_PAD0 22 /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
\r
525 #define MUX_PA22D_SERCOM5_PAD0 3
\r
526 #define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
\r
527 #define PORT_PA22D_SERCOM5_PAD0 (1u << 22)
\r
528 #define PIN_PB02D_SERCOM5_PAD0 34 /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
\r
529 #define MUX_PB02D_SERCOM5_PAD0 3
\r
530 #define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
\r
531 #define PORT_PB02D_SERCOM5_PAD0 (1u << 2)
\r
532 #define PIN_PA23D_SERCOM5_PAD1 23 /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
\r
533 #define MUX_PA23D_SERCOM5_PAD1 3
\r
534 #define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
\r
535 #define PORT_PA23D_SERCOM5_PAD1 (1u << 23)
\r
536 #define PIN_PB03D_SERCOM5_PAD1 35 /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
\r
537 #define MUX_PB03D_SERCOM5_PAD1 3
\r
538 #define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
\r
539 #define PORT_PB03D_SERCOM5_PAD1 (1u << 3)
\r
540 #define PIN_PA24D_SERCOM5_PAD2 24 /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
\r
541 #define MUX_PA24D_SERCOM5_PAD2 3
\r
542 #define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
\r
543 #define PORT_PA24D_SERCOM5_PAD2 (1u << 24)
\r
544 #define PIN_PB22D_SERCOM5_PAD2 54 /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
\r
545 #define MUX_PB22D_SERCOM5_PAD2 3
\r
546 #define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
\r
547 #define PORT_PB22D_SERCOM5_PAD2 (1u << 22)
\r
548 #define PIN_PA20C_SERCOM5_PAD2 20 /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
\r
549 #define MUX_PA20C_SERCOM5_PAD2 2
\r
550 #define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
\r
551 #define PORT_PA20C_SERCOM5_PAD2 (1u << 20)
\r
552 #define PIN_PA25D_SERCOM5_PAD3 25 /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
\r
553 #define MUX_PA25D_SERCOM5_PAD3 3
\r
554 #define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
\r
555 #define PORT_PA25D_SERCOM5_PAD3 (1u << 25)
\r
556 #define PIN_PB23D_SERCOM5_PAD3 55 /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
\r
557 #define MUX_PB23D_SERCOM5_PAD3 3
\r
558 #define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
\r
559 #define PORT_PB23D_SERCOM5_PAD3 (1u << 23)
\r
560 #define PIN_PA21C_SERCOM5_PAD3 21 /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
\r
561 #define MUX_PA21C_SERCOM5_PAD3 2
\r
562 #define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
\r
563 #define PORT_PA21C_SERCOM5_PAD3 (1u << 21)
\r
564 /* ========== PORT definition for TC0 peripheral ========== */
\r
565 #define PIN_PA04F_TC0_WO0 4 /**< \brief TC0 signal: WO0 on PA04 mux F */
\r
566 #define MUX_PA04F_TC0_WO0 5
\r
567 #define PINMUX_PA04F_TC0_WO0 ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0)
\r
568 #define PORT_PA04F_TC0_WO0 (1u << 4)
\r
569 #define PIN_PA08E_TC0_WO0 8 /**< \brief TC0 signal: WO0 on PA08 mux E */
\r
570 #define MUX_PA08E_TC0_WO0 4
\r
571 #define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
\r
572 #define PORT_PA08E_TC0_WO0 (1u << 8)
\r
573 #define PIN_PA05F_TC0_WO1 5 /**< \brief TC0 signal: WO1 on PA05 mux F */
\r
574 #define MUX_PA05F_TC0_WO1 5
\r
575 #define PINMUX_PA05F_TC0_WO1 ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1)
\r
576 #define PORT_PA05F_TC0_WO1 (1u << 5)
\r
577 #define PIN_PA09E_TC0_WO1 9 /**< \brief TC0 signal: WO1 on PA09 mux E */
\r
578 #define MUX_PA09E_TC0_WO1 4
\r
579 #define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
\r
580 #define PORT_PA09E_TC0_WO1 (1u << 9)
\r
581 /* ========== PORT definition for TC1 peripheral ========== */
\r
582 #define PIN_PA06F_TC1_WO0 6 /**< \brief TC1 signal: WO0 on PA06 mux F */
\r
583 #define MUX_PA06F_TC1_WO0 5
\r
584 #define PINMUX_PA06F_TC1_WO0 ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0)
\r
585 #define PORT_PA06F_TC1_WO0 (1u << 6)
\r
586 #define PIN_PA30F_TC1_WO0 30 /**< \brief TC1 signal: WO0 on PA30 mux F */
\r
587 #define MUX_PA30F_TC1_WO0 5
\r
588 #define PINMUX_PA30F_TC1_WO0 ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0)
\r
589 #define PORT_PA30F_TC1_WO0 (1u << 30)
\r
590 #define PIN_PA10E_TC1_WO0 10 /**< \brief TC1 signal: WO0 on PA10 mux E */
\r
591 #define MUX_PA10E_TC1_WO0 4
\r
592 #define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
\r
593 #define PORT_PA10E_TC1_WO0 (1u << 10)
\r
594 #define PIN_PA07F_TC1_WO1 7 /**< \brief TC1 signal: WO1 on PA07 mux F */
\r
595 #define MUX_PA07F_TC1_WO1 5
\r
596 #define PINMUX_PA07F_TC1_WO1 ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1)
\r
597 #define PORT_PA07F_TC1_WO1 (1u << 7)
\r
598 #define PIN_PA31F_TC1_WO1 31 /**< \brief TC1 signal: WO1 on PA31 mux F */
\r
599 #define MUX_PA31F_TC1_WO1 5
\r
600 #define PINMUX_PA31F_TC1_WO1 ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1)
\r
601 #define PORT_PA31F_TC1_WO1 (1u << 31)
\r
602 #define PIN_PA11E_TC1_WO1 11 /**< \brief TC1 signal: WO1 on PA11 mux E */
\r
603 #define MUX_PA11E_TC1_WO1 4
\r
604 #define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
\r
605 #define PORT_PA11E_TC1_WO1 (1u << 11)
\r
606 /* ========== PORT definition for TC2 peripheral ========== */
\r
607 #define PIN_PA16F_TC2_WO0 16 /**< \brief TC2 signal: WO0 on PA16 mux F */
\r
608 #define MUX_PA16F_TC2_WO0 5
\r
609 #define PINMUX_PA16F_TC2_WO0 ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0)
\r
610 #define PORT_PA16F_TC2_WO0 (1u << 16)
\r
611 #define PIN_PA12E_TC2_WO0 12 /**< \brief TC2 signal: WO0 on PA12 mux E */
\r
612 #define MUX_PA12E_TC2_WO0 4
\r
613 #define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
\r
614 #define PORT_PA12E_TC2_WO0 (1u << 12)
\r
615 #define PIN_PA00F_TC2_WO0 0 /**< \brief TC2 signal: WO0 on PA00 mux F */
\r
616 #define MUX_PA00F_TC2_WO0 5
\r
617 #define PINMUX_PA00F_TC2_WO0 ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0)
\r
618 #define PORT_PA00F_TC2_WO0 (1u << 0)
\r
619 #define PIN_PA17F_TC2_WO1 17 /**< \brief TC2 signal: WO1 on PA17 mux F */
\r
620 #define MUX_PA17F_TC2_WO1 5
\r
621 #define PINMUX_PA17F_TC2_WO1 ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1)
\r
622 #define PORT_PA17F_TC2_WO1 (1u << 17)
\r
623 #define PIN_PA13E_TC2_WO1 13 /**< \brief TC2 signal: WO1 on PA13 mux E */
\r
624 #define MUX_PA13E_TC2_WO1 4
\r
625 #define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
\r
626 #define PORT_PA13E_TC2_WO1 (1u << 13)
\r
627 #define PIN_PA01F_TC2_WO1 1 /**< \brief TC2 signal: WO1 on PA01 mux F */
\r
628 #define MUX_PA01F_TC2_WO1 5
\r
629 #define PINMUX_PA01F_TC2_WO1 ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1)
\r
630 #define PORT_PA01F_TC2_WO1 (1u << 1)
\r
631 /* ========== PORT definition for TC3 peripheral ========== */
\r
632 #define PIN_PA18F_TC3_WO0 18 /**< \brief TC3 signal: WO0 on PA18 mux F */
\r
633 #define MUX_PA18F_TC3_WO0 5
\r
634 #define PINMUX_PA18F_TC3_WO0 ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0)
\r
635 #define PORT_PA18F_TC3_WO0 (1u << 18)
\r
636 #define PIN_PA14E_TC3_WO0 14 /**< \brief TC3 signal: WO0 on PA14 mux E */
\r
637 #define MUX_PA14E_TC3_WO0 4
\r
638 #define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
\r
639 #define PORT_PA14E_TC3_WO0 (1u << 14)
\r
640 #define PIN_PA19F_TC3_WO1 19 /**< \brief TC3 signal: WO1 on PA19 mux F */
\r
641 #define MUX_PA19F_TC3_WO1 5
\r
642 #define PINMUX_PA19F_TC3_WO1 ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1)
\r
643 #define PORT_PA19F_TC3_WO1 (1u << 19)
\r
644 #define PIN_PA15E_TC3_WO1 15 /**< \brief TC3 signal: WO1 on PA15 mux E */
\r
645 #define MUX_PA15E_TC3_WO1 4
\r
646 #define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
\r
647 #define PORT_PA15E_TC3_WO1 (1u << 15)
\r
648 /* ========== PORT definition for TC4 peripheral ========== */
\r
649 #define PIN_PA22F_TC4_WO0 22 /**< \brief TC4 signal: WO0 on PA22 mux F */
\r
650 #define MUX_PA22F_TC4_WO0 5
\r
651 #define PINMUX_PA22F_TC4_WO0 ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0)
\r
652 #define PORT_PA22F_TC4_WO0 (1u << 22)
\r
653 #define PIN_PB08F_TC4_WO0 40 /**< \brief TC4 signal: WO0 on PB08 mux F */
\r
654 #define MUX_PB08F_TC4_WO0 5
\r
655 #define PINMUX_PB08F_TC4_WO0 ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0)
\r
656 #define PORT_PB08F_TC4_WO0 (1u << 8)
\r
657 #define PIN_PA23F_TC4_WO1 23 /**< \brief TC4 signal: WO1 on PA23 mux F */
\r
658 #define MUX_PA23F_TC4_WO1 5
\r
659 #define PINMUX_PA23F_TC4_WO1 ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1)
\r
660 #define PORT_PA23F_TC4_WO1 (1u << 23)
\r
661 #define PIN_PB09F_TC4_WO1 41 /**< \brief TC4 signal: WO1 on PB09 mux F */
\r
662 #define MUX_PB09F_TC4_WO1 5
\r
663 #define PINMUX_PB09F_TC4_WO1 ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1)
\r
664 #define PORT_PB09F_TC4_WO1 (1u << 9)
\r
665 /* ========== PORT definition for TC5 peripheral ========== */
\r
666 #define PIN_PA24F_TC5_WO0 24 /**< \brief TC5 signal: WO0 on PA24 mux F */
\r
667 #define MUX_PA24F_TC5_WO0 5
\r
668 #define PINMUX_PA24F_TC5_WO0 ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0)
\r
669 #define PORT_PA24F_TC5_WO0 (1u << 24)
\r
670 #define PIN_PB10F_TC5_WO0 42 /**< \brief TC5 signal: WO0 on PB10 mux F */
\r
671 #define MUX_PB10F_TC5_WO0 5
\r
672 #define PINMUX_PB10F_TC5_WO0 ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0)
\r
673 #define PORT_PB10F_TC5_WO0 (1u << 10)
\r
674 #define PIN_PA25F_TC5_WO1 25 /**< \brief TC5 signal: WO1 on PA25 mux F */
\r
675 #define MUX_PA25F_TC5_WO1 5
\r
676 #define PINMUX_PA25F_TC5_WO1 ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1)
\r
677 #define PORT_PA25F_TC5_WO1 (1u << 25)
\r
678 #define PIN_PB11F_TC5_WO1 43 /**< \brief TC5 signal: WO1 on PB11 mux F */
\r
679 #define MUX_PB11F_TC5_WO1 5
\r
680 #define PINMUX_PB11F_TC5_WO1 ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1)
\r
681 #define PORT_PB11F_TC5_WO1 (1u << 11)
\r
682 /* ========== PORT definition for TC6 peripheral ========== */
\r
683 #define PIN_PB02F_TC6_WO0 34 /**< \brief TC6 signal: WO0 on PB02 mux F */
\r
684 #define MUX_PB02F_TC6_WO0 5
\r
685 #define PINMUX_PB02F_TC6_WO0 ((PIN_PB02F_TC6_WO0 << 16) | MUX_PB02F_TC6_WO0)
\r
686 #define PORT_PB02F_TC6_WO0 (1u << 2)
\r
687 #define PIN_PB03F_TC6_WO1 35 /**< \brief TC6 signal: WO1 on PB03 mux F */
\r
688 #define MUX_PB03F_TC6_WO1 5
\r
689 #define PINMUX_PB03F_TC6_WO1 ((PIN_PB03F_TC6_WO1 << 16) | MUX_PB03F_TC6_WO1)
\r
690 #define PORT_PB03F_TC6_WO1 (1u << 3)
\r
691 /* ========== PORT definition for TC7 peripheral ========== */
\r
692 #define PIN_PB22F_TC7_WO0 54 /**< \brief TC7 signal: WO0 on PB22 mux F */
\r
693 #define MUX_PB22F_TC7_WO0 5
\r
694 #define PINMUX_PB22F_TC7_WO0 ((PIN_PB22F_TC7_WO0 << 16) | MUX_PB22F_TC7_WO0)
\r
695 #define PORT_PB22F_TC7_WO0 (1u << 22)
\r
696 #define PIN_PA20E_TC7_WO0 20 /**< \brief TC7 signal: WO0 on PA20 mux E */
\r
697 #define MUX_PA20E_TC7_WO0 4
\r
698 #define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
\r
699 #define PORT_PA20E_TC7_WO0 (1u << 20)
\r
700 #define PIN_PB23F_TC7_WO1 55 /**< \brief TC7 signal: WO1 on PB23 mux F */
\r
701 #define MUX_PB23F_TC7_WO1 5
\r
702 #define PINMUX_PB23F_TC7_WO1 ((PIN_PB23F_TC7_WO1 << 16) | MUX_PB23F_TC7_WO1)
\r
703 #define PORT_PB23F_TC7_WO1 (1u << 23)
\r
704 #define PIN_PA21E_TC7_WO1 21 /**< \brief TC7 signal: WO1 on PA21 mux E */
\r
705 #define MUX_PA21E_TC7_WO1 4
\r
706 #define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
\r
707 #define PORT_PA21E_TC7_WO1 (1u << 21)
\r
708 /* ========== PORT definition for ADC peripheral ========== */
\r
709 #define PIN_PA02B_ADC_AIN0 2 /**< \brief ADC signal: AIN0 on PA02 mux B */
\r
710 #define MUX_PA02B_ADC_AIN0 1
\r
711 #define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
\r
712 #define PORT_PA02B_ADC_AIN0 (1u << 2)
\r
713 #define PIN_PA03B_ADC_AIN1 3 /**< \brief ADC signal: AIN1 on PA03 mux B */
\r
714 #define MUX_PA03B_ADC_AIN1 1
\r
715 #define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
\r
716 #define PORT_PA03B_ADC_AIN1 (1u << 3)
\r
717 #define PIN_PB08B_ADC_AIN2 40 /**< \brief ADC signal: AIN2 on PB08 mux B */
\r
718 #define MUX_PB08B_ADC_AIN2 1
\r
719 #define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
\r
720 #define PORT_PB08B_ADC_AIN2 (1u << 8)
\r
721 #define PIN_PB09B_ADC_AIN3 41 /**< \brief ADC signal: AIN3 on PB09 mux B */
\r
722 #define MUX_PB09B_ADC_AIN3 1
\r
723 #define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
\r
724 #define PORT_PB09B_ADC_AIN3 (1u << 9)
\r
725 #define PIN_PA04B_ADC_AIN4 4 /**< \brief ADC signal: AIN4 on PA04 mux B */
\r
726 #define MUX_PA04B_ADC_AIN4 1
\r
727 #define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
\r
728 #define PORT_PA04B_ADC_AIN4 (1u << 4)
\r
729 #define PIN_PA05B_ADC_AIN5 5 /**< \brief ADC signal: AIN5 on PA05 mux B */
\r
730 #define MUX_PA05B_ADC_AIN5 1
\r
731 #define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
\r
732 #define PORT_PA05B_ADC_AIN5 (1u << 5)
\r
733 #define PIN_PA06B_ADC_AIN6 6 /**< \brief ADC signal: AIN6 on PA06 mux B */
\r
734 #define MUX_PA06B_ADC_AIN6 1
\r
735 #define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
\r
736 #define PORT_PA06B_ADC_AIN6 (1u << 6)
\r
737 #define PIN_PA07B_ADC_AIN7 7 /**< \brief ADC signal: AIN7 on PA07 mux B */
\r
738 #define MUX_PA07B_ADC_AIN7 1
\r
739 #define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
\r
740 #define PORT_PA07B_ADC_AIN7 (1u << 7)
\r
741 #define PIN_PB02B_ADC_AIN10 34 /**< \brief ADC signal: AIN10 on PB02 mux B */
\r
742 #define MUX_PB02B_ADC_AIN10 1
\r
743 #define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
\r
744 #define PORT_PB02B_ADC_AIN10 (1u << 2)
\r
745 #define PIN_PB03B_ADC_AIN11 35 /**< \brief ADC signal: AIN11 on PB03 mux B */
\r
746 #define MUX_PB03B_ADC_AIN11 1
\r
747 #define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
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748 #define PORT_PB03B_ADC_AIN11 (1u << 3)
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749 #define PIN_PA08B_ADC_AIN16 8 /**< \brief ADC signal: AIN16 on PA08 mux B */
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750 #define MUX_PA08B_ADC_AIN16 1
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751 #define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
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752 #define PORT_PA08B_ADC_AIN16 (1u << 8)
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753 #define PIN_PA09B_ADC_AIN17 9 /**< \brief ADC signal: AIN17 on PA09 mux B */
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754 #define MUX_PA09B_ADC_AIN17 1
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755 #define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
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756 #define PORT_PA09B_ADC_AIN17 (1u << 9)
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757 #define PIN_PA10B_ADC_AIN18 10 /**< \brief ADC signal: AIN18 on PA10 mux B */
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758 #define MUX_PA10B_ADC_AIN18 1
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759 #define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
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760 #define PORT_PA10B_ADC_AIN18 (1u << 10)
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761 #define PIN_PA11B_ADC_AIN19 11 /**< \brief ADC signal: AIN19 on PA11 mux B */
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762 #define MUX_PA11B_ADC_AIN19 1
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763 #define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
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764 #define PORT_PA11B_ADC_AIN19 (1u << 11)
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765 #define PIN_PA04B_ADC_VREFP 4 /**< \brief ADC signal: VREFP on PA04 mux B */
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766 #define MUX_PA04B_ADC_VREFP 1
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767 #define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
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768 #define PORT_PA04B_ADC_VREFP (1u << 4)
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769 /* ========== PORT definition for AC peripheral ========== */
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770 #define PIN_PA04B_AC_AIN0 4 /**< \brief AC signal: AIN0 on PA04 mux B */
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771 #define MUX_PA04B_AC_AIN0 1
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772 #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
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773 #define PORT_PA04B_AC_AIN0 (1u << 4)
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774 #define PIN_PA05B_AC_AIN1 5 /**< \brief AC signal: AIN1 on PA05 mux B */
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775 #define MUX_PA05B_AC_AIN1 1
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776 #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
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777 #define PORT_PA05B_AC_AIN1 (1u << 5)
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778 #define PIN_PA06B_AC_AIN2 6 /**< \brief AC signal: AIN2 on PA06 mux B */
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779 #define MUX_PA06B_AC_AIN2 1
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780 #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
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781 #define PORT_PA06B_AC_AIN2 (1u << 6)
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782 #define PIN_PA07B_AC_AIN3 7 /**< \brief AC signal: AIN3 on PA07 mux B */
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783 #define MUX_PA07B_AC_AIN3 1
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784 #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
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785 #define PORT_PA07B_AC_AIN3 (1u << 7)
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786 #define PIN_PA12H_AC_CMP0 12 /**< \brief AC signal: CMP0 on PA12 mux H */
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787 #define MUX_PA12H_AC_CMP0 7
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788 #define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
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789 #define PORT_PA12H_AC_CMP0 (1u << 12)
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790 #define PIN_PA18H_AC_CMP0 18 /**< \brief AC signal: CMP0 on PA18 mux H */
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791 #define MUX_PA18H_AC_CMP0 7
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792 #define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
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793 #define PORT_PA18H_AC_CMP0 (1u << 18)
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794 #define PIN_PA13H_AC_CMP1 13 /**< \brief AC signal: CMP1 on PA13 mux H */
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795 #define MUX_PA13H_AC_CMP1 7
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796 #define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
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797 #define PORT_PA13H_AC_CMP1 (1u << 13)
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798 #define PIN_PA19H_AC_CMP1 19 /**< \brief AC signal: CMP1 on PA19 mux H */
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799 #define MUX_PA19H_AC_CMP1 7
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800 #define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
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801 #define PORT_PA19H_AC_CMP1 (1u << 19)
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802 /* ========== PORT definition for DAC peripheral ========== */
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803 #define PIN_PA02B_DAC_VOUT 2 /**< \brief DAC signal: VOUT on PA02 mux B */
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804 #define MUX_PA02B_DAC_VOUT 1
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805 #define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
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806 #define PORT_PA02B_DAC_VOUT (1u << 2)
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807 #define PIN_PA03B_DAC_VREFP 3 /**< \brief DAC signal: VREFP on PA03 mux B */
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808 #define MUX_PA03B_DAC_VREFP 1
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809 #define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
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810 #define PORT_PA03B_DAC_VREFP (1u << 3)
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812 #endif /* _SAMD20G16_PIO_ */
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projects / freertos / blob