4 * \brief Header file for SAMD20E16
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6 * Copyright (c) 2013 Atmel Corporation. All rights reserved.
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12 * Redistribution and use in source and binary forms, with or without
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13 * modification, are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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18 * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 * this list of conditions and the following disclaimer in the documentation
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20 * and/or other materials provided with the distribution.
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22 * 3. The name of Atmel may not be used to endorse or promote products derived
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23 * from this software without specific prior written permission.
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25 * 4. This software may only be redistributed and used in connection with an
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26 * Atmel microcontroller product.
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28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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38 * POSSIBILITY OF SUCH DAMAGE.
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48 * \ingroup SAMD20_definitions
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49 * \addtogroup SAMD20E16_definitions SAMD20E16 definitions
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50 * This file defines all structures and symbols for SAMD20E16:
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51 * - registers and bitfields
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52 * - peripheral base address
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62 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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65 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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66 typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
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67 typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
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69 typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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70 typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
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71 typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
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73 typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
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74 typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
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75 typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
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76 typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
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77 typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
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78 typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
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79 #define CAST(type, value) ((type *)(value))
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80 #define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
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82 #define CAST(type, value) (value)
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83 #define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
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86 /* ************************************************************************** */
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87 /** CMSIS DEFINITIONS FOR SAMD20E16 */
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88 /* ************************************************************************** */
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89 /** \defgroup SAMD20E16_cmsis CMSIS Definitions */
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92 /** Interrupt Number Definition */
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95 /****** Cortex-M0+ Processor Exceptions Numbers *******************************/
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96 NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
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97 HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
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98 SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
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99 PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
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100 SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
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101 /****** SAMD20E16-specific Interrupt Numbers ***********************/
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102 PM_IRQn = 0, /**< 0 SAMD20E16 Power Manager (PM) */
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103 SYSCTRL_IRQn = 1, /**< 1 SAMD20E16 System Control (SYSCTRL) */
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104 WDT_IRQn = 2, /**< 2 SAMD20E16 Watchdog Timer (WDT) */
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105 RTC_IRQn = 3, /**< 3 SAMD20E16 Real-Time Counter (RTC) */
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106 EIC_IRQn = 4, /**< 4 SAMD20E16 External Interrupt Controller (EIC) */
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107 NVMCTRL_IRQn = 5, /**< 5 SAMD20E16 Non-Volatile Memory Controller (NVMCTRL) */
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108 EVSYS_IRQn = 6, /**< 6 SAMD20E16 Event System Interface (EVSYS) */
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109 SERCOM0_IRQn = 7, /**< 7 SAMD20E16 Serial Communication Interface 0 (SERCOM0) */
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110 SERCOM1_IRQn = 8, /**< 8 SAMD20E16 Serial Communication Interface 1 (SERCOM1) */
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111 SERCOM2_IRQn = 9, /**< 9 SAMD20E16 Serial Communication Interface 2 (SERCOM2) */
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112 SERCOM3_IRQn = 10, /**< 10 SAMD20E16 Serial Communication Interface 3 (SERCOM3) */
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113 TC0_IRQn = 13, /**< 13 SAMD20E16 Basic Timer Counter 0 (TC0) */
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114 TC1_IRQn = 14, /**< 14 SAMD20E16 Basic Timer Counter 1 (TC1) */
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115 TC2_IRQn = 15, /**< 15 SAMD20E16 Basic Timer Counter 2 (TC2) */
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116 TC3_IRQn = 16, /**< 16 SAMD20E16 Basic Timer Counter 3 (TC3) */
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117 TC4_IRQn = 17, /**< 17 SAMD20E16 Basic Timer Counter 4 (TC4) */
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118 TC5_IRQn = 18, /**< 18 SAMD20E16 Basic Timer Counter 5 (TC5) */
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119 ADC_IRQn = 21, /**< 21 SAMD20E16 Analog Digital Converter (ADC) */
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120 AC_IRQn = 22, /**< 22 SAMD20E16 Analog Comparators (AC) */
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121 DAC_IRQn = 23, /**< 23 SAMD20E16 Digital Analog Converter (DAC) */
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123 PERIPH_COUNT_IRQn = 24 /**< Number of peripheral IDs */
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126 typedef struct _DeviceVectors
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128 /* Stack pointer */
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131 /* Cortex-M handlers */
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132 void* pfnReset_Handler;
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133 void* pfnNMI_Handler;
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134 void* pfnHardFault_Handler;
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135 void* pfnReservedM12;
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136 void* pfnReservedM11;
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137 void* pfnReservedM10;
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138 void* pfnReservedM9;
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139 void* pfnReservedM8;
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140 void* pfnReservedM7;
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141 void* pfnReservedM6;
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142 void* pfnSVC_Handler;
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143 void* pfnReservedM4;
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144 void* pfnReservedM3;
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145 void* pfnPendSV_Handler;
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146 void* pfnSysTick_Handler;
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148 /* Peripheral handlers */
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149 void* pfnPM_Handler; /* 0 Power Manager */
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150 void* pfnSYSCTRL_Handler; /* 1 System Control */
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151 void* pfnWDT_Handler; /* 2 Watchdog Timer */
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152 void* pfnRTC_Handler; /* 3 Real-Time Counter */
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153 void* pfnEIC_Handler; /* 4 External Interrupt Controller */
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154 void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
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155 void* pfnEVSYS_Handler; /* 6 Event System Interface */
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156 void* pfnSERCOM0_Handler; /* 7 Serial Communication Interface 0 */
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157 void* pfnSERCOM1_Handler; /* 8 Serial Communication Interface 1 */
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158 void* pfnSERCOM2_Handler; /* 9 Serial Communication Interface 2 */
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159 void* pfnSERCOM3_Handler; /* 10 Serial Communication Interface 3 */
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160 void* pfnReserved11;
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161 void* pfnReserved12;
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162 void* pfnTC0_Handler; /* 13 Basic Timer Counter 0 */
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163 void* pfnTC1_Handler; /* 14 Basic Timer Counter 1 */
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164 void* pfnTC2_Handler; /* 15 Basic Timer Counter 2 */
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165 void* pfnTC3_Handler; /* 16 Basic Timer Counter 3 */
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166 void* pfnTC4_Handler; /* 17 Basic Timer Counter 4 */
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167 void* pfnTC5_Handler; /* 18 Basic Timer Counter 5 */
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168 void* pfnReserved19;
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169 void* pfnReserved20;
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170 void* pfnADC_Handler; /* 21 Analog Digital Converter */
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171 void* pfnAC_Handler; /* 22 Analog Comparators */
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172 void* pfnDAC_Handler; /* 23 Digital Analog Converter */
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175 /* Cortex-M0+ processor handlers */
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176 void Reset_Handler ( void );
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177 void NMI_Handler ( void );
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178 void HardFault_Handler ( void );
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179 void SVC_Handler ( void );
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180 void PendSV_Handler ( void );
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181 void SysTick_Handler ( void );
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183 /* Peripherals handlers */
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184 void PM_Handler ( void );
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185 void SYSCTRL_Handler ( void );
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186 void WDT_Handler ( void );
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187 void RTC_Handler ( void );
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188 void EIC_Handler ( void );
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189 void NVMCTRL_Handler ( void );
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190 void EVSYS_Handler ( void );
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191 void SERCOM0_Handler ( void );
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192 void SERCOM1_Handler ( void );
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193 void SERCOM2_Handler ( void );
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194 void SERCOM3_Handler ( void );
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195 void TC0_Handler ( void );
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196 void TC1_Handler ( void );
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197 void TC2_Handler ( void );
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198 void TC3_Handler ( void );
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199 void TC4_Handler ( void );
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200 void TC5_Handler ( void );
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201 void ADC_Handler ( void );
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202 void AC_Handler ( void );
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203 void DAC_Handler ( void );
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206 * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
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209 #define LITTLE_ENDIAN 1
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210 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
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211 #define __MPU_PRESENT 0 /*!< MPU present or not */
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212 #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
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213 #define __VTOR_PRESENT 1 /*!< VTOR present or not */
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214 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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217 * \brief CMSIS includes
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220 #include <core_cm0plus.h>
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221 #if !defined DONT_USE_CMSIS_INIT
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222 #include "system_samd20.h"
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223 #endif /* DONT_USE_CMSIS_INIT */
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227 /* ************************************************************************** */
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228 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20E16 */
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229 /* ************************************************************************** */
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230 /** \defgroup SAMD20E16_api Peripheral Software API */
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233 #include "component/component_ac.h"
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234 #include "component/component_adc.h"
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235 #include "component/component_dac.h"
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236 #include "component/component_dsu.h"
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237 #include "component/component_eic.h"
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238 #include "component/component_evsys.h"
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239 #include "component/component_gclk.h"
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240 #include "component/component_nvmctrl.h"
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241 #include "component/component_pac.h"
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242 #include "component/component_pm.h"
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243 #include "component/component_port.h"
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244 #include "component/component_rtc.h"
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245 #include "component/component_sercom.h"
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246 #include "component/component_sysctrl.h"
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247 #include "component/component_tc.h"
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248 #include "component/component_wdt.h"
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251 /* ************************************************************************** */
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252 /** REGISTERS ACCESS DEFINITIONS FOR SAMD20E16 */
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253 /* ************************************************************************** */
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254 /** \defgroup SAMD20E16_reg Registers Access Definitions */
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257 #include "instance/instance_ac.h"
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258 #include "instance/instance_adc.h"
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259 #include "instance/instance_dac.h"
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260 #include "instance/instance_dsu.h"
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261 #include "instance/instance_eic.h"
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262 #include "instance/instance_evsys.h"
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263 #include "instance/instance_gclk.h"
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264 #include "instance/instance_nvmctrl.h"
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265 #include "instance/instance_pac0.h"
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266 #include "instance/instance_pac1.h"
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267 #include "instance/instance_pac2.h"
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268 #include "instance/instance_pm.h"
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269 #include "instance/instance_port.h"
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270 #include "instance/instance_rtc.h"
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271 #include "instance/instance_sercom0.h"
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272 #include "instance/instance_sercom1.h"
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273 #include "instance/instance_sercom2.h"
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274 #include "instance/instance_sercom3.h"
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275 #include "instance/instance_sysctrl.h"
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276 #include "instance/instance_tc0.h"
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277 #include "instance/instance_tc1.h"
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278 #include "instance/instance_tc2.h"
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279 #include "instance/instance_tc3.h"
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280 #include "instance/instance_tc4.h"
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281 #include "instance/instance_tc5.h"
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282 #include "instance/instance_wdt.h"
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285 /* ************************************************************************** */
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286 /** PERIPHERAL ID DEFINITIONS FOR SAMD20E16 */
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287 /* ************************************************************************** */
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288 /** \defgroup SAMD20E16_id Peripheral Ids Definitions */
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291 // Peripheral instances on HPB0 bridge
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292 #define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
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293 #define ID_PM 1 /**< \brief Power Manager (PM) */
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294 #define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
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295 #define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
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296 #define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
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297 #define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
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298 #define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
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300 // Peripheral instances on HPB1 bridge
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301 #define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
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302 #define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
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303 #define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
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304 #define ID_PORT 35 /**< \brief Port Module (PORT) */
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306 // Peripheral instances on HPB2 bridge
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307 #define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
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308 #define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
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309 #define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
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310 #define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
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311 #define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
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312 #define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
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313 #define ID_TC0 72 /**< \brief Basic Timer Counter TC (TC0) */
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314 #define ID_TC1 73 /**< \brief Basic Timer Counter TC (TC1) */
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315 #define ID_TC2 74 /**< \brief Basic Timer Counter TC (TC2) */
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316 #define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
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317 #define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
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318 #define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
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319 #define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
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320 #define ID_AC 81 /**< \brief Analog Comparators (AC) */
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321 #define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
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323 #define ID_PERIPH_COUNT 83 /**< \brief Number of peripheral IDs */
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326 /* ************************************************************************** */
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327 /** BASE ADDRESS DEFINITIONS FOR SAMD20E16 */
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328 /* ************************************************************************** */
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329 /** \defgroup SAMD20E16_base Peripheral Base Address Definitions */
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332 #if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
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333 #define AC (0x42004400U) /**< \brief (AC) APB Base Address */
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334 #define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
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335 #define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
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336 #define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
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337 #define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
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338 #define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
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339 #define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
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340 #define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
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341 #define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
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342 #define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
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343 #define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
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344 #define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
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345 #define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
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346 #define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
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347 #define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
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348 #define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
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349 #define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
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350 #define PM (0x40000400U) /**< \brief (PM) APB Base Address */
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351 #define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
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352 #define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
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353 #define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
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354 #define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
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355 #define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
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356 #define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
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357 #define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
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358 #define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
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359 #define TC0 (0x42002000U) /**< \brief (TC0) APB Base Address */
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360 #define TC1 (0x42002400U) /**< \brief (TC1) APB Base Address */
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361 #define TC2 (0x42002800U) /**< \brief (TC2) APB Base Address */
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362 #define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
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363 #define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
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364 #define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
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365 #define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
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367 #define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
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368 #define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
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369 #define AC_INSTS { AC } /**< \brief (AC) Instances List */
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371 #define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
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372 #define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
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373 #define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
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375 #define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
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376 #define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
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377 #define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
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379 #define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
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380 #define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
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381 #define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
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383 #define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
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384 #define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
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385 #define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
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387 #define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
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388 #define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
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389 #define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
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391 #define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
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392 #define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
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393 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
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395 #define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
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396 #define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
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397 #define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
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398 #define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
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399 #define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
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400 #define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
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401 #define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
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402 #define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
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403 #define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
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405 #define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
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406 #define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
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407 #define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
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408 #define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
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409 #define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
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411 #define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
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412 #define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
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413 #define PM_INSTS { PM } /**< \brief (PM) Instances List */
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415 #define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
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416 #define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
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417 #define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
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418 #define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
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420 #define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
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421 #define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
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422 #define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
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424 #define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
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425 #define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
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426 #define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
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427 #define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
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428 #define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
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429 #define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
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431 #define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
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432 #define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
\r
433 #define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
\r
435 #define TC0 ((Tc *)0x42002000U) /**< \brief (TC0) APB Base Address */
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436 #define TC1 ((Tc *)0x42002400U) /**< \brief (TC1) APB Base Address */
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437 #define TC2 ((Tc *)0x42002800U) /**< \brief (TC2) APB Base Address */
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438 #define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
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439 #define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
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440 #define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
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441 #define TC_INST_NUM 6 /**< \brief (TC) Number of instances */
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442 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
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444 #define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
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445 #define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
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446 #define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
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448 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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451 /* ************************************************************************** */
\r
452 /** PORT DEFINITIONS FOR SAMD20E16 */
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453 /* ************************************************************************** */
\r
454 /** \defgroup SAMD20E16_port PORT Definitions */
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457 #include "pio/pio_samd20e16.h"
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460 /* ************************************************************************** */
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461 /** MEMORY MAPPING DEFINITIONS FOR SAMD20E16 */
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462 /* ************************************************************************** */
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464 #define FLASH_SIZE 0x10000 /* 64 kB */
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465 #define FLASH_PAGE_SIZE 64
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466 #define FLASH_NB_OF_PAGES 1024
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467 #define FLASH_USER_PAGE_SIZE 64
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468 #define HRAMC0_SIZE 0x2000 /* 8 kB */
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469 #define FLASH_ADDR (0x00000000U) /**< FLASH base address */
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470 #define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
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471 #define HRAMC0_ADDR (0x20000000U) /**< HRAMC0 base address */
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473 /* ************************************************************************** */
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474 /** ELECTRICAL DEFINITIONS FOR SAMD20E16 */
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475 /* ************************************************************************** */
\r
484 #endif /* SAMD20E16_H */
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